diff --git a/dv/verilator/top_verilator.sv b/dv/verilator/top_verilator.sv
index 1c57f8ba0..5682f01cb 100644
--- a/dv/verilator/top_verilator.sv
+++ b/dv/verilator/top_verilator.sv
@@ -13,7 +13,7 @@ module top_verilator (input logic clk_i, rst_ni);
   // Instantiating the Sonata System.
   sonata_system u_sonata_system (
     // Clock and Reset
-    .clk_sys_i (clk_i),
+    .clk_sys_i (clk_i ),
     .rst_sys_ni(rst_ni),
 
     // UART TX and RX
@@ -21,27 +21,27 @@ module top_verilator (input logic clk_i, rst_ni);
     .uart_tx_o (uart_sys_tx),
 
     // Remaining IO
-    .gp_i      (0),
-    .gp_o      ( ),
-    .pwm_o     ( ),
-    .spi_rx_i  (0),
-    .spi_tx_o  ( ),
-    .spi_sck_o ( ),
+    .gp_i     (0),
+    .gp_o     ( ),
+    .pwm_o    ( ),
+    .spi_rx_i (0),
+    .spi_tx_o ( ),
+    .spi_sck_o( ),
 
     // CHERI output
-    .cheri_err_o ( ),
-    .cheri_en_o  ( )
+    .cheri_err_o(),
+    .cheri_en_o ()
   );
 
   // Virtual UART
   uartdpi #(
-    .BAUD(BaudRate),
-    .FREQ(ClockFrequency)
+    .BAUD ( BaudRate       ),
+    .FREQ ( ClockFrequency )
   ) u_uartdpi (
     .clk_i,
     .rst_ni,
-    .active (1'b1       ),
-    .tx_o   (uart_sys_rx),
-    .rx_i   (uart_sys_tx)
+    .active(1'b1       ),
+    .tx_o  (uart_sys_rx),
+    .rx_i  (uart_sys_tx)
   );
 endmodule