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IP to suspend/reset on both FPGA and sim #380

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marnovandermaas opened this issue Jan 17, 2025 · 0 comments
Open

IP to suspend/reset on both FPGA and sim #380

marnovandermaas opened this issue Jan 17, 2025 · 0 comments

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@marnovandermaas
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          As discussed in person, and annotated here just for future consideration....a simple register/IP block on the Sonata bus that provided power down/suspend/reset on a physical system (we still have a requirement for a reset block) could also provide shutdown in simulation more elegantly.

Originally posted by @alees24 in #368 (comment)
@marnovandermaas marnovandermaas changed the title As discussed in person, and annotated here just for future consideration....a simple register/IP block on the Sonata bus that provided power down/suspend/reset on a physical system (we still have a requirement for a reset block) could also provide shutdown in simulation more elegantly. IP to suspend/reset on both FPGA and sim Jan 17, 2025
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