Partial Reconfiguration
This guide will lead you through the steps necessary for building a dynamic design using ReconOS. We will be using a simple example with one reconfigurable slot containing a dynamic hardware thread. As application we implement a sorter.
Initially, the application generates numbers sorted in descending order. It is the goal of the application to continuously sort the data alternating between ascending and descending order. The hardware thread 'sort8k' sorts data chunks of 8Kbyte in ascending order while the hardware thread 'sort8kinv' sorts them in descending order (both use the bubble sort algorithm). The application switches between both hardware threads (and therefore reconfigure the hardware slot) after sorting the entire data sets. Before reconfiguring the hardware thread, the data chunks are merged and checked for correctness in software.
First we create the structure of the project. This is easily done by using the command
reconos_mkprj.py <project_name>
This creates the typical ReconOS Projekt environment with the sw and hw directory. Now we have to change the project settings. From this point, we assume that $WORK describes the path to your project folder.
file: <project_name>.rprj
The line beginning with STATIC-THREADS has to be edited, because we add a hardware threads that can sort 8 KBytes of data. Name the threads sort8k sort8kinv by adding this to the line.
Note:This tutorial creates the multi-core environment on the ML605-board. If you want to create it for a different board, you have to change the reference design in the project file.
Now edit the layout file:
hw/<project_name>.lyt
Delete everything except the TARGET definition and two empty hardware slot definition. The final file should look like this (for the ML605-Board):
target
device xc6vlx240t
family xc6vlx
end
slot hw_task_0
end
slot hw_task_1
end
In a last step, set the environment variable $HW_THREADS:
source $WORK/settings.sh
After this, the project structure is ready to be worked with.
In this tutorial, we will use existing simple example threads that sorts 8 kbytes of data. Both threads wait for a message from an incoming message queue containing the address of the data chunk and sends a message to an outgoing queue when sorting is done.
The sort8k thread is composed in two VHDL files that can be found under $RECONOS/demos/sort_demo_inv_pr/hw/src/sort8k/bubble_sorter.vhd and $RECONOS/demos/sort_demo_inv_pr/hw/src/sort8k/sort8k.vhd. Copy both files to the $PROJECT_NAME/hw directory and add the reconos thread to the static hardware design.
cd $WORK/hw
mkdir sort8k
cp $RECONOS/demos/sort_demo_inv_pr/hw/sort8k/src/*.vhd $WORK/hw/sort8k/*.vhd
cd $WORK/hw/hwthreads
reconos_addhwthread.py sort8k sort8k ../sort8k/bubble_sorter.vhd ../sort8k/sort8k.vhd
The arguments to the reconos_addwthread.py script are the hardware thread's entity name, the user logic entity's name (often the same as the one before), and the source files sorted after dependency such that the top file comes last. The script now creates an EDK pcore that contains the interface structures necessary to connect our hardware thread to the already instantiated OSIF.
Do the same for the 'sort8kinv' hardware thread
cd $WORK/hw
mkdir sort8kinv
cp $RECONOS/demos/sort_demo_inv_pr/hw/sort8kinv/src/*.vhd $WORK/hw/sort8kinv/*.vhd
cd $WORK/hw/hwthreads
reconos_addhwthread.py sort8kinv sort8kinv ../sort8kinv/bubble_sorter.vhd ../sort8kinv/sort8kinv.vhd
Now create the static hardware list. For this we call
make static-threads
which adds both hardware threads and two OSIFS to the initial reference system.
Now start Xilinx Platformstudio xps and open the project file $WORK/hw/edk-static/system.xmp. You will see that our design has two hardware threads and two OSIFs. Delete the hardware thread hw_task_1 and the corresponding OSIF osif_1. We only need one reconfigurable hardware slot in this tutorial.
Compile the software drivers and library functions into a BSP, using the Software->Generate libraries and BSPs menu item. This will generate the Xilinx headers and particularly libxil.a which we will need when compiling the eCos library. You need to regenerate this BSP whenever you change the hardware architecture (e.g. add OSIFs/slots, peripherals, change the memory map, etc.).
Finally, generate the bitstream, using the Hardware->Generate Bitstream menu item.
For the dynamic design we will need the netlists for both hardware threads for the first hardware slot. These can be made using the Makefile in the folder hwthreads.
export NUM_DYNAMIC_OSIFS=1
cd $WORK/hw/hwthreads/sortk8k
make all
cd $WORK/hw/hwthreads/sortk8kinv
make all
This step should create the netlists $WORK/hw/hwthreads/sortk8k/implementation/hw_task_0_wrapper.ngc and $WORK/hw/hwthreads/sortk8kinv/implementation/hw_task_0_wrapper.ngc.
In the next step, we remove the old netlist for the hardware thread hw_task_0.
rm $HW_DESIGN/implementation/hw_task_0.ngc
When we have a static design, we can add reconfigurable slots into the design by using planAhead (
Xilinx PlanAhead Tutorial - Overview of the Partial Reconfiguration Flow). Therefore, we start planAhead and create a new project.
planAhead
Call the project planahead and set the project location to $WORK/hw/ Select the 2nd option and check the Set PR Project box (necessary for designs with partial reconfguration).
Specify synthesized (EDIF or NGC) netlist
You will be able to run post-synthesis design analysis, planning, and implementation.
Set PR project: yes
As the Top Netlist File select $HW_DESIGN/implementation/system.ngc and hit the Add Directories...-button, where you select the implementation directory of our static design $HW_DESIGN/implementation. In the next window, the constraint file should be already included. If this is not the case, include $HW_DESIGN/implementation/system.ucf. Click Finish to create the project.
In planAhead, open the netlist design by selecting Netlist Design->Open Netlist Design in the Project Manager window.
In the Netlist Design window, highlight the netlist hw_task_0, right-click and choose Set Partition. Click Next on the first screen and select that the partion is a reconfigurable Partition. Set hw_task_0 as reconfigurable module name.
Again in the Netlist Design window, highlight the netlist hw_task_0, right-click and choose Add Reconfigurable Module.... Set the module name to sort8k and check the option that the netlist is already available. Select $WORK/hw/hwthreads/sortk8/implementation/hw_task_0_wrapper.ngc as the netlist. Do not provide a ucf-contraint file. Redo these steps for the reconfigurable module sort8kinv where you select the netlist $WORK/hw/hwthreads/sortk8inv/implementation/hw_task_0_wrapper.ngc.
Finally, we add a black box module called black_box. Therefore, this time we select the option Add this Reconfigurable module as block box without a netlist. Select the black_box module as active module in the Netlist Design window.
Switch to the Physical Constraints window, where we will define the hardware slot region for the threads. Highlight hw_task_0, right-click and select Set Pblock Size. In the Design Planner window, you see the FPGA board. In this window, draw a rectangle that contains slices and RAMB18s. Align the rectangle to the blue horizontal lines (select complete frames) and avoid to mix different clock regions. For instance, your slot could look like this.
Save the project!
In the Project Manager window, click Run DRC to check, if the partial reconfiguration specific design rules are met. This step should be done before creating configurations.
In the Design Runs window, highlight the configuration config_1 and verify in the Partitions window that black_box is selected as module variant. Furthermore, check that for the static logic and black_box the status is Implement. Back in the Design Runs window, right-click config_1 and select Launch Runs. This might take a while. When the configuration is implemented, the status of the static logic and black_box should be changed to Implemented. In the Project Manager window, click Promote Partitions to promote configuration 1. The status of config_1 should change to Promoted. You can verify the configuration clicking Program and Debug>Verify configuration in the Project Manager window.
In this step, we will create the configurations that contain the hardware threads sort8k and sort8kinv. Therefore, in the Design Runs window, right-click and select Create Multiple Runs. In the step Choose Implementation Strategies and Reconfigurable Modules klick the ... button. Select sort8k as reconfigurable module for config_2. For the static logic choose the action Import. For the sort8k choose Implement. Do the same steps for config_3 that implements sort8kinv.
In the Design Runs window, highlight the configurations config_2 and config_3, right-click and select Launch Runs. Again, this step will take some time. You can verify the configurations by clicking Program and Debug>Verify configuration in the Project Manager window.
In the Design Runs window, highlight all configurations, perform a right-click and select Generate Bitstream. The bitstreams are stored in $WORK/hw/planahead/planahead.runs/config_*/*.bit
Copy the files for software application from the $RECONOS respository.
cp -r $RECONOS/demos/sort_demo_inv_pr/sw/* $WORK/sw
Compile eCos and the software application.
cd $WORK/sw
make mrproper setup
make clean all
In a new shell, start the minicom modem, such that the print-functions, which are called by the software part of application and forwarded through the serial port to your computer, is shown to you.
minicom
Check, if the baudrate of minicom is set correctly to 57600 8N1 ([STRG]+[A] [O]). When you have uploaded an executable, the print output will be shown here.
To configure the FPGA with your dynamic hardware design, you have to download the bitstream and the software application to the board. To use our dow tool you have to specify the processor architecture and the target board as environment variables.
cd $WORK/sw
export ARCH=mb
export RECONOS_BOARD=ml605
dow ../hw/planahead/planahead.runs/config_1/config_1.bit
dow sort_ecos_2_dynamic_threads.elf
You should receive the similar output on minicom:
enabling data cache for external ram
initializing ICAP interface...done
Generating data...done
########## Sort8k: 1. RUN ##############
CHECK FAILED!
Flushing cache...done
Sorting data...done
Invalidating cache...done
Merging data...done
Checking sorted data...check successful.
Running times (size: 131072 words):
Sort data : 6830 ms
Merge data : 201 ms
Check data : 27 ms
Total computation time (sort & merge): 7031 ms
########## Sort8kinv: 1. RUN ##############
CHECK FAILED!
Flushing cache...done
Sorting data...inverse...done
Invalidating cache...done
Merging data...done
Checking sorted data...check successful.
Running times (size: 131072 words):
Sort data : 6786 ms
Merge data : 201 ms
Check data : 27 ms
Total computation time (sort & merge): 6987 ms
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