risc-v/mmu: Configure T-Head MMU to cache User Text, Data and Heap #76
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lupyuen
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This PR configures the T-Head MMU to cache the the User Text, Data and Heap. We enable the MMU Flags for Shareable, Bufferable and Cacheable, as explained in this article: https://lupyuen.github.io/articles/plic3#appendix-mmu-caching-for-t-head-c906 This PR fixes the Slow Memory Access for NuttX Apps on BL808 and SG2000 SoCs: apache#12696. With this fix, SG2000 NuttX CoreMark jumps from 21 to 2,423. (Close to SG2000 Debian CoreMark) We introduce a Kconfig Option: `ARCH_MMU_EXT_THEAD` ("System Type > Enable T-Head MMU extension support"). Enabling this Kconfig Option will configure the T-Head MMU to cache the User Text, Data and Heap. This PR enables the MMU cache for only SG2000 SoC (Milk-V Duo S SBC). The next PR will apply the same settings to BL808 SoC (Pine64 Ox64 SBC). Modified Files: `arch/risc-v/Kconfig`: Added Kconfig Option `ARCH_MMU_EXT_THEAD` that will configure the T-Head MMU. Enabled `ARCH_MMU_EXT_THEAD` for SG2000 SoC. `arch/risc-v/src/common/riscv_mmu.h`: Set the T-Head MMU Flags (Shareable, Bufferable and Cacheable) for User Text, Data and Heap, if `ARCH_MMU_EXT_THEAD` is enabled `arch/risc-v/src/common/riscv_addrenv.c`: Extended the MMU Flags from 32 bits to 64 bits, to accommodate the T-Head MMU Flags `arch/risc-v/src/common/riscv_exception.c`: Extended the MMU Flags from 32 bits to 64 bit, to accommodate the T-Head MMU Flags. This code is enabled only for MMU Paging (`CONFIG_PAGING`).
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[Experimental Bot, please feedback here] NuttX PR Requirement CheckThis PR generally meets the requirements, but with some minor improvements needed: Summary:
Impact:
Testing:
Overall: The PR demonstrates a good understanding of NuttX requirements. Addressing the highlighted points, particularly compatibility and testing clarity, will significantly enhance its readiness for review. |
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Summary
This PR configures the T-Head MMU to cache the the User Text, Data and Heap. We enable the MMU Flags for Shareable, Bufferable and Cacheable, as explained in this article.
This PR fixes the Slow Memory Access for NuttX Apps on BL808 and SG2000 SoCs: apache#12696. With this fix, SG2000 NuttX CoreMark jumps from 21 to 2,422. (Close to SG2000 Debian CoreMark)
We introduce a Kconfig Option:
ARCH_MMU_EXT_THEAD("System Type > Enable T-Head MMU extension support"). Enabling this Kconfig Option will configure the T-Head MMU to cache the User Text, Data and Heap.This PR enables the MMU cache for only SG2000 SoC (Milk-V Duo S SBC). The next PR will apply the same settings to BL808 SoC (Pine64 Ox64 SBC).
Modified Files
arch/risc-v/Kconfig: Added Kconfig OptionARCH_MMU_EXT_THEADthat will configure the T-Head MMU. EnabledARCH_MMU_EXT_THEADfor SG2000 SoC.arch/risc-v/src/common/riscv_mmu.h: Set the T-Head MMU Flags (Shareable, Bufferable and Cacheable) for User Text, Data and Heap, ifARCH_MMU_EXT_THEADis enabledarch/risc-v/src/common/riscv_addrenv.c: Extended the MMU Flags from 32 bits to 64 bits, to accommodate the T-Head MMU Flagsarch/risc-v/src/common/riscv_exception.c: Extended the MMU Flags from 32 bits to 64 bit, to accommodate the T-Head MMU Flags. This code is enabled only for MMU Paging (CONFIG_PAGING).Impact
This PR affects only the platforms that have
ARCH_MMU_EXT_THEADenabled. Right now, only SG2000 SoC enablesARCH_MMU_EXT_THEAD.Testing
We tested on Milk-V Duo S SBC with SG2000 SoC:
Before the PR: CoreMark is 17 (NuttX Log)
After the PR: CoreMark increases to 1,759 (NuttX Log)
And OSTest completes successfully:
Note that CoreMark will increase further to 2,422 when we compile CoreMark optimised with
-O2Regression Testing: We tested OSTest on QEMU RISC-V 32-bit and 64-bit (Flat Build and Kernel Build):
MMU Paging: With
CONFIG_PAGINGenabled,rv-virt:knsh_pagingcompiles correctly. However we were unable to testknsh_paging. OSTest failed with the same error, before and after our PR: