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pci.c
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pci.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2020 Realtek Corporation
*/
#include <linux/pci.h>
#include "mac.h"
#include "pci.h"
#include "reg.h"
#include "ser.h"
static bool rtw89_pci_disable_clkreq;
static bool rtw89_pci_disable_aspm_l1;
static bool rtw89_pci_disable_l1ss;
module_param_named(disable_clkreq, rtw89_pci_disable_clkreq, bool, 0644);
module_param_named(disable_aspm_l1, rtw89_pci_disable_aspm_l1, bool, 0644);
module_param_named(disable_aspm_l1ss, rtw89_pci_disable_l1ss, bool, 0644);
MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support");
MODULE_PARM_DESC(disable_aspm_l1, "Set Y to disable PCI ASPM L1 support");
MODULE_PARM_DESC(disable_aspm_l1ss, "Set Y to disable PCI L1SS support");
static int rtw89_pci_get_phy_offset_by_link_speed(struct rtw89_dev *rtwdev,
u32 *phy_offset)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct pci_dev *pdev = rtwpci->pdev;
u32 val;
int ret;
ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val);
if (ret)
return ret;
val = u32_get_bits(val, RTW89_BCFG_LINK_SPEED_MASK);
if (val == RTW89_PCIE_GEN1_SPEED) {
*phy_offset = R_RAC_DIRECT_OFFSET_G1;
} else if (val == RTW89_PCIE_GEN2_SPEED) {
*phy_offset = R_RAC_DIRECT_OFFSET_G2;
} else {
rtw89_warn(rtwdev, "Unknown PCI link speed %d\n", val);
return -EFAULT;
}
return 0;
}
static int rtw89_pci_rst_bdram_ax(struct rtw89_dev *rtwdev)
{
u32 val;
int ret;
rtw89_write32_set(rtwdev, R_AX_PCIE_INIT_CFG1, B_AX_RST_BDRAM);
ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM),
1, RTW89_PCI_POLL_BDRAM_RST_CNT, false,
rtwdev, R_AX_PCIE_INIT_CFG1);
return ret;
}
static u32 rtw89_pci_dma_recalc(struct rtw89_dev *rtwdev,
struct rtw89_pci_dma_ring *bd_ring,
u32 cur_idx, bool tx)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
u32 cnt, cur_rp, wp, rp, len;
rp = bd_ring->rp;
wp = bd_ring->wp;
len = bd_ring->len;
cur_rp = FIELD_GET(TXBD_HW_IDX_MASK, cur_idx);
if (tx) {
cnt = cur_rp >= rp ? cur_rp - rp : len - (rp - cur_rp);
} else {
if (info->rx_ring_eq_is_full)
wp += 1;
cnt = cur_rp >= wp ? cur_rp - wp : len - (wp - cur_rp);
}
bd_ring->rp = cur_rp;
return cnt;
}
static u32 rtw89_pci_txbd_recalc(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_dma_ring *bd_ring = &tx_ring->bd_ring;
u32 addr_idx = bd_ring->addr.idx;
u32 cnt, idx;
idx = rtw89_read32(rtwdev, addr_idx);
cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, true);
return cnt;
}
static void rtw89_pci_release_fwcmd(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci,
u32 cnt, bool release_all)
{
struct rtw89_pci_tx_data *tx_data;
struct sk_buff *skb;
u32 qlen;
while (cnt--) {
skb = skb_dequeue(&rtwpci->h2c_queue);
if (!skb) {
rtw89_err(rtwdev, "failed to pre-release fwcmd\n");
return;
}
skb_queue_tail(&rtwpci->h2c_release_queue, skb);
}
qlen = skb_queue_len(&rtwpci->h2c_release_queue);
if (!release_all)
qlen = qlen > RTW89_PCI_MULTITAG ? qlen - RTW89_PCI_MULTITAG : 0;
while (qlen--) {
skb = skb_dequeue(&rtwpci->h2c_release_queue);
if (!skb) {
rtw89_err(rtwdev, "failed to release fwcmd\n");
return;
}
tx_data = RTW89_PCI_TX_SKB_CB(skb);
dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len,
DMA_TO_DEVICE);
dev_kfree_skb_any(skb);
}
}
static void rtw89_pci_reclaim_tx_fwcmd(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci)
{
struct rtw89_pci_tx_ring *tx_ring = &rtwpci->tx_rings[RTW89_TXCH_CH12];
u32 cnt;
cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring);
if (!cnt)
return;
rtw89_pci_release_fwcmd(rtwdev, rtwpci, cnt, false);
}
static u32 rtw89_pci_rxbd_recalc(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
u32 addr_idx = bd_ring->addr.idx;
u32 cnt, idx;
idx = rtw89_read32(rtwdev, addr_idx);
cnt = rtw89_pci_dma_recalc(rtwdev, bd_ring, idx, false);
return cnt;
}
static void rtw89_pci_sync_skb_for_cpu(struct rtw89_dev *rtwdev,
struct sk_buff *skb)
{
struct rtw89_pci_rx_info *rx_info;
dma_addr_t dma;
rx_info = RTW89_PCI_RX_SKB_CB(skb);
dma = rx_info->dma;
dma_sync_single_for_cpu(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE,
DMA_FROM_DEVICE);
}
static void rtw89_pci_sync_skb_for_device(struct rtw89_dev *rtwdev,
struct sk_buff *skb)
{
struct rtw89_pci_rx_info *rx_info;
dma_addr_t dma;
rx_info = RTW89_PCI_RX_SKB_CB(skb);
dma = rx_info->dma;
dma_sync_single_for_device(rtwdev->dev, dma, RTW89_PCI_RX_BUF_SIZE,
DMA_FROM_DEVICE);
}
static void rtw89_pci_rxbd_info_update(struct rtw89_dev *rtwdev,
struct sk_buff *skb)
{
struct rtw89_pci_rxbd_info *rxbd_info;
struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb);
rxbd_info = (struct rtw89_pci_rxbd_info *)skb->data;
rx_info->fs = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_FS);
rx_info->ls = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_LS);
rx_info->len = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_WRITE_SIZE);
rx_info->tag = le32_get_bits(rxbd_info->dword, RTW89_PCI_RXBD_TAG);
}
static int rtw89_pci_validate_rx_tag(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring,
struct sk_buff *skb)
{
struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb);
const struct rtw89_pci_info *info = rtwdev->pci_info;
u32 target_rx_tag;
if (!info->check_rx_tag)
return 0;
/* valid range is 1 ~ 0x1FFF */
if (rx_ring->target_rx_tag == 0)
target_rx_tag = 1;
else
target_rx_tag = rx_ring->target_rx_tag;
if (rx_info->tag != target_rx_tag) {
rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "mismatch RX tag 0x%x 0x%x\n",
rx_info->tag, target_rx_tag);
return -EAGAIN;
}
return 0;
}
static
int rtw89_pci_sync_skb_for_device_and_validate_rx_info(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring,
struct sk_buff *skb)
{
struct rtw89_pci_rx_info *rx_info = RTW89_PCI_RX_SKB_CB(skb);
int rx_tag_retry = 100;
int ret;
do {
rtw89_pci_sync_skb_for_cpu(rtwdev, skb);
rtw89_pci_rxbd_info_update(rtwdev, skb);
ret = rtw89_pci_validate_rx_tag(rtwdev, rx_ring, skb);
if (ret != -EAGAIN)
break;
} while (rx_tag_retry--);
/* update target rx_tag for next RX */
rx_ring->target_rx_tag = rx_info->tag + 1;
return ret;
}
static void rtw89_pci_ctrl_txdma_ch_ax(struct rtw89_dev *rtwdev, bool enable)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1;
const struct rtw89_reg_def *dma_stop2 = &info->dma_stop2;
if (enable) {
rtw89_write32_clr(rtwdev, dma_stop1->addr, dma_stop1->mask);
if (dma_stop2->addr)
rtw89_write32_clr(rtwdev, dma_stop2->addr, dma_stop2->mask);
} else {
rtw89_write32_set(rtwdev, dma_stop1->addr, dma_stop1->mask);
if (dma_stop2->addr)
rtw89_write32_set(rtwdev, dma_stop2->addr, dma_stop2->mask);
}
}
static void rtw89_pci_ctrl_txdma_fw_ch_ax(struct rtw89_dev *rtwdev, bool enable)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
const struct rtw89_reg_def *dma_stop1 = &info->dma_stop1;
if (enable)
rtw89_write32_clr(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
else
rtw89_write32_set(rtwdev, dma_stop1->addr, B_AX_STOP_CH12);
}
static bool
rtw89_skb_put_rx_data(struct rtw89_dev *rtwdev, bool fs, bool ls,
struct sk_buff *new,
const struct sk_buff *skb, u32 offset,
const struct rtw89_pci_rx_info *rx_info,
const struct rtw89_rx_desc_info *desc_info)
{
u32 copy_len = rx_info->len - offset;
if (unlikely(skb_tailroom(new) < copy_len)) {
rtw89_debug(rtwdev, RTW89_DBG_TXRX,
"invalid rx data length bd_len=%d desc_len=%d offset=%d (fs=%d ls=%d)\n",
rx_info->len, desc_info->pkt_size, offset, fs, ls);
rtw89_hex_dump(rtwdev, RTW89_DBG_TXRX, "rx_data: ",
skb->data, rx_info->len);
/* length of a single segment skb is desc_info->pkt_size */
if (fs && ls) {
copy_len = desc_info->pkt_size;
} else {
rtw89_info(rtwdev, "drop rx data due to invalid length\n");
return false;
}
}
skb_put_data(new, skb->data + offset, copy_len);
return true;
}
static u32 rtw89_pci_get_rx_skb_idx(struct rtw89_dev *rtwdev,
struct rtw89_pci_dma_ring *bd_ring)
{
const struct rtw89_pci_info *info = rtwdev->pci_info;
u32 wp = bd_ring->wp;
if (!info->rx_ring_eq_is_full)
return wp;
if (++wp >= bd_ring->len)
wp = 0;
return wp;
}
static u32 rtw89_pci_rxbd_deliver_skbs(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
struct rtw89_pci_rx_info *rx_info;
struct rtw89_rx_desc_info *desc_info = &rx_ring->diliver_desc;
struct sk_buff *new = rx_ring->diliver_skb;
struct sk_buff *skb;
u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info);
u32 skb_idx;
u32 offset;
u32 cnt = 1;
bool fs, ls;
int ret;
skb_idx = rtw89_pci_get_rx_skb_idx(rtwdev, bd_ring);
skb = rx_ring->buf[skb_idx];
ret = rtw89_pci_sync_skb_for_device_and_validate_rx_info(rtwdev, rx_ring, skb);
if (ret) {
rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n",
bd_ring->wp, ret);
goto err_sync_device;
}
rx_info = RTW89_PCI_RX_SKB_CB(skb);
fs = rx_info->fs;
ls = rx_info->ls;
if (fs) {
if (new) {
rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
"skb should not be ready before first segment start\n");
goto err_sync_device;
}
if (desc_info->ready) {
rtw89_warn(rtwdev, "desc info should not be ready before first segment start\n");
goto err_sync_device;
}
rtw89_chip_query_rxdesc(rtwdev, desc_info, skb->data, rxinfo_size);
new = rtw89_alloc_skb_for_rx(rtwdev, desc_info->pkt_size);
if (!new)
goto err_sync_device;
rx_ring->diliver_skb = new;
/* first segment has RX desc */
offset = desc_info->offset + desc_info->rxd_len;
} else {
offset = sizeof(struct rtw89_pci_rxbd_info);
if (!new) {
rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "no last skb\n");
goto err_sync_device;
}
}
if (!rtw89_skb_put_rx_data(rtwdev, fs, ls, new, skb, offset, rx_info, desc_info))
goto err_sync_device;
rtw89_pci_sync_skb_for_device(rtwdev, skb);
rtw89_pci_rxbd_increase(rx_ring, 1);
if (!desc_info->ready) {
rtw89_warn(rtwdev, "no rx desc information\n");
goto err_free_resource;
}
if (ls) {
rtw89_core_rx(rtwdev, desc_info, new);
rx_ring->diliver_skb = NULL;
desc_info->ready = false;
}
return cnt;
err_sync_device:
rtw89_pci_sync_skb_for_device(rtwdev, skb);
rtw89_pci_rxbd_increase(rx_ring, 1);
err_free_resource:
if (new)
dev_kfree_skb_any(new);
rx_ring->diliver_skb = NULL;
desc_info->ready = false;
return cnt;
}
static void rtw89_pci_rxbd_deliver(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring,
u32 cnt)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
u32 rx_cnt;
while (cnt && rtwdev->napi_budget_countdown > 0) {
rx_cnt = rtw89_pci_rxbd_deliver_skbs(rtwdev, rx_ring);
if (!rx_cnt) {
rtw89_err(rtwdev, "failed to deliver RXBD skb\n");
/* skip the rest RXBD bufs */
rtw89_pci_rxbd_increase(rx_ring, cnt);
break;
}
cnt -= rx_cnt;
}
rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp);
}
static int rtw89_pci_poll_rxq_dma(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci, int budget)
{
struct rtw89_pci_rx_ring *rx_ring;
int countdown = rtwdev->napi_budget_countdown;
u32 cnt;
rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RXQ];
cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring);
if (!cnt)
return 0;
cnt = min_t(u32, budget, cnt);
rtw89_pci_rxbd_deliver(rtwdev, rx_ring, cnt);
/* In case of flushing pending SKBs, the countdown may exceed. */
if (rtwdev->napi_budget_countdown <= 0)
return budget;
return budget - countdown;
}
static void rtw89_pci_tx_status(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring,
struct sk_buff *skb, u8 tx_status)
{
struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
struct ieee80211_tx_info *info;
rtw89_core_tx_wait_complete(rtwdev, skb_data, tx_status == RTW89_TX_DONE);
info = IEEE80211_SKB_CB(skb);
ieee80211_tx_info_clear_status(info);
if (info->flags & IEEE80211_TX_CTL_NO_ACK)
info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
if (tx_status == RTW89_TX_DONE) {
info->flags |= IEEE80211_TX_STAT_ACK;
tx_ring->tx_acked++;
} else {
if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)
rtw89_debug(rtwdev, RTW89_DBG_FW,
"failed to TX of status %x\n", tx_status);
switch (tx_status) {
case RTW89_TX_RETRY_LIMIT:
tx_ring->tx_retry_lmt++;
break;
case RTW89_TX_LIFE_TIME:
tx_ring->tx_life_time++;
break;
case RTW89_TX_MACID_DROP:
tx_ring->tx_mac_id_drop++;
break;
default:
rtw89_warn(rtwdev, "invalid TX status %x\n", tx_status);
break;
}
}
ieee80211_tx_status_ni(rtwdev->hw, skb);
}
static void rtw89_pci_reclaim_txbd(struct rtw89_dev *rtwdev, struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_tx_wd *txwd;
u32 cnt;
cnt = rtw89_pci_txbd_recalc(rtwdev, tx_ring);
while (cnt--) {
txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list);
if (!txwd) {
rtw89_warn(rtwdev, "No busy txwd pages available\n");
break;
}
list_del_init(&txwd->list);
/* this skb has been freed by RPP */
if (skb_queue_len(&txwd->queue) == 0)
rtw89_pci_enqueue_txwd(tx_ring, txwd);
}
}
static void rtw89_pci_release_busy_txwd(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
struct rtw89_pci_tx_wd *txwd;
int i;
for (i = 0; i < wd_ring->page_num; i++) {
txwd = list_first_entry_or_null(&tx_ring->busy_pages, struct rtw89_pci_tx_wd, list);
if (!txwd)
break;
list_del_init(&txwd->list);
}
}
static void rtw89_pci_release_txwd_skb(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring,
struct rtw89_pci_tx_wd *txwd, u16 seq,
u8 tx_status)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_tx_data *tx_data;
struct sk_buff *skb, *tmp;
u8 txch = tx_ring->txch;
if (!list_empty(&txwd->list)) {
rtw89_pci_reclaim_txbd(rtwdev, tx_ring);
/* In low power mode, RPP can receive before updating of TX BD.
* In normal mode, it should not happen so give it a warning.
*/
if (!rtwpci->low_power && !list_empty(&txwd->list))
rtw89_warn(rtwdev, "queue %d txwd %d is not idle\n",
txch, seq);
}
skb_queue_walk_safe(&txwd->queue, skb, tmp) {
skb_unlink(skb, &txwd->queue);
tx_data = RTW89_PCI_TX_SKB_CB(skb);
dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len,
DMA_TO_DEVICE);
rtw89_pci_tx_status(rtwdev, tx_ring, skb, tx_status);
}
if (list_empty(&txwd->list))
rtw89_pci_enqueue_txwd(tx_ring, txwd);
}
static void rtw89_pci_release_rpp(struct rtw89_dev *rtwdev,
struct rtw89_pci_rpp_fmt *rpp)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
struct rtw89_pci_tx_ring *tx_ring;
struct rtw89_pci_tx_wd_ring *wd_ring;
struct rtw89_pci_tx_wd *txwd;
u16 seq;
u8 qsel, tx_status, txch;
seq = le32_get_bits(rpp->dword, RTW89_PCI_RPP_SEQ);
qsel = le32_get_bits(rpp->dword, RTW89_PCI_RPP_QSEL);
tx_status = le32_get_bits(rpp->dword, RTW89_PCI_RPP_TX_STATUS);
txch = rtw89_core_get_ch_dma(rtwdev, qsel);
if (txch == RTW89_TXCH_CH12) {
rtw89_warn(rtwdev, "should no fwcmd release report\n");
return;
}
tx_ring = &rtwpci->tx_rings[txch];
wd_ring = &tx_ring->wd_ring;
txwd = &wd_ring->pages[seq];
rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, seq, tx_status);
}
static void rtw89_pci_release_pending_txwd_skb(struct rtw89_dev *rtwdev,
struct rtw89_pci_tx_ring *tx_ring)
{
struct rtw89_pci_tx_wd_ring *wd_ring = &tx_ring->wd_ring;
struct rtw89_pci_tx_wd *txwd;
int i;
for (i = 0; i < wd_ring->page_num; i++) {
txwd = &wd_ring->pages[i];
if (!list_empty(&txwd->list))
continue;
rtw89_pci_release_txwd_skb(rtwdev, tx_ring, txwd, i, RTW89_TX_MACID_DROP);
}
}
static u32 rtw89_pci_release_tx_skbs(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring,
u32 max_cnt)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
struct rtw89_pci_rx_info *rx_info;
struct rtw89_pci_rpp_fmt *rpp;
struct rtw89_rx_desc_info desc_info = {};
struct sk_buff *skb;
u32 cnt = 0;
u32 rpp_size = sizeof(struct rtw89_pci_rpp_fmt);
u32 rxinfo_size = sizeof(struct rtw89_pci_rxbd_info);
u32 skb_idx;
u32 offset;
int ret;
skb_idx = rtw89_pci_get_rx_skb_idx(rtwdev, bd_ring);
skb = rx_ring->buf[skb_idx];
ret = rtw89_pci_sync_skb_for_device_and_validate_rx_info(rtwdev, rx_ring, skb);
if (ret) {
rtw89_err(rtwdev, "failed to update %d RXBD info: %d\n",
bd_ring->wp, ret);
goto err_sync_device;
}
rx_info = RTW89_PCI_RX_SKB_CB(skb);
if (!rx_info->fs || !rx_info->ls) {
rtw89_err(rtwdev, "cannot process RP frame not set FS/LS\n");
return cnt;
}
rtw89_chip_query_rxdesc(rtwdev, &desc_info, skb->data, rxinfo_size);
/* first segment has RX desc */
offset = desc_info.offset + desc_info.rxd_len;
for (; offset + rpp_size <= rx_info->len; offset += rpp_size) {
rpp = (struct rtw89_pci_rpp_fmt *)(skb->data + offset);
rtw89_pci_release_rpp(rtwdev, rpp);
}
rtw89_pci_sync_skb_for_device(rtwdev, skb);
rtw89_pci_rxbd_increase(rx_ring, 1);
cnt++;
return cnt;
err_sync_device:
rtw89_pci_sync_skb_for_device(rtwdev, skb);
return 0;
}
static void rtw89_pci_release_tx(struct rtw89_dev *rtwdev,
struct rtw89_pci_rx_ring *rx_ring,
u32 cnt)
{
struct rtw89_pci_dma_ring *bd_ring = &rx_ring->bd_ring;
u32 release_cnt;
while (cnt) {
release_cnt = rtw89_pci_release_tx_skbs(rtwdev, rx_ring, cnt);
if (!release_cnt) {
rtw89_err(rtwdev, "failed to release TX skbs\n");
/* skip the rest RXBD bufs */
rtw89_pci_rxbd_increase(rx_ring, cnt);
break;
}
cnt -= release_cnt;
}
rtw89_write16(rtwdev, bd_ring->addr.idx, bd_ring->wp);
}
static int rtw89_pci_poll_rpq_dma(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci, int budget)
{
struct rtw89_pci_rx_ring *rx_ring;
u32 cnt;
int work_done;
rx_ring = &rtwpci->rx_rings[RTW89_RXCH_RPQ];
spin_lock_bh(&rtwpci->trx_lock);
cnt = rtw89_pci_rxbd_recalc(rtwdev, rx_ring);
if (cnt == 0)
goto out_unlock;
rtw89_pci_release_tx(rtwdev, rx_ring, cnt);
out_unlock:
spin_unlock_bh(&rtwpci->trx_lock);
/* always release all RPQ */
work_done = min_t(int, cnt, budget);
rtwdev->napi_budget_countdown -= work_done;
return work_done;
}
static void rtw89_pci_isr_rxd_unavail(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci)
{
struct rtw89_pci_rx_ring *rx_ring;
struct rtw89_pci_dma_ring *bd_ring;
u32 reg_idx;
u16 hw_idx, hw_idx_next, host_idx;
int i;
for (i = 0; i < RTW89_RXCH_NUM; i++) {
rx_ring = &rtwpci->rx_rings[i];
bd_ring = &rx_ring->bd_ring;
reg_idx = rtw89_read32(rtwdev, bd_ring->addr.idx);
hw_idx = FIELD_GET(TXBD_HW_IDX_MASK, reg_idx);
host_idx = FIELD_GET(TXBD_HOST_IDX_MASK, reg_idx);
hw_idx_next = (hw_idx + 1) % bd_ring->len;
if (hw_idx_next == host_idx)
rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "%d RXD unavailable\n", i);
rtw89_debug(rtwdev, RTW89_DBG_TXRX,
"%d RXD unavailable, idx=0x%08x, len=%d\n",
i, reg_idx, bd_ring->len);
}
}
void rtw89_pci_recognize_intrs(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci,
struct rtw89_pci_isrs *isrs)
{
isrs->halt_c2h_isrs = rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs;
isrs->isrs[0] = rtw89_read32(rtwdev, R_AX_PCIE_HISR00) & rtwpci->intrs[0];
isrs->isrs[1] = rtw89_read32(rtwdev, R_AX_PCIE_HISR10) & rtwpci->intrs[1];
rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs);
rtw89_write32(rtwdev, R_AX_PCIE_HISR00, isrs->isrs[0]);
rtw89_write32(rtwdev, R_AX_PCIE_HISR10, isrs->isrs[1]);
}
EXPORT_SYMBOL(rtw89_pci_recognize_intrs);
void rtw89_pci_recognize_intrs_v1(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci,
struct rtw89_pci_isrs *isrs)
{
isrs->ind_isrs = rtw89_read32(rtwdev, R_AX_PCIE_HISR00_V1) & rtwpci->ind_intrs;
isrs->halt_c2h_isrs = isrs->ind_isrs & B_AX_HS0ISR_IND_INT_EN ?
rtw89_read32(rtwdev, R_AX_HISR0) & rtwpci->halt_c2h_intrs : 0;
isrs->isrs[0] = isrs->ind_isrs & B_AX_HCI_AXIDMA_INT_EN ?
rtw89_read32(rtwdev, R_AX_HAXI_HISR00) & rtwpci->intrs[0] : 0;
isrs->isrs[1] = isrs->ind_isrs & B_AX_HS1ISR_IND_INT_EN ?
rtw89_read32(rtwdev, R_AX_HISR1) & rtwpci->intrs[1] : 0;
if (isrs->halt_c2h_isrs)
rtw89_write32(rtwdev, R_AX_HISR0, isrs->halt_c2h_isrs);
if (isrs->isrs[0])
rtw89_write32(rtwdev, R_AX_HAXI_HISR00, isrs->isrs[0]);
if (isrs->isrs[1])
rtw89_write32(rtwdev, R_AX_HISR1, isrs->isrs[1]);
}
EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v1);
void rtw89_pci_recognize_intrs_v2(struct rtw89_dev *rtwdev,
struct rtw89_pci *rtwpci,
struct rtw89_pci_isrs *isrs)
{
isrs->ind_isrs = rtw89_read32(rtwdev, R_BE_PCIE_HISR) & rtwpci->ind_intrs;
isrs->halt_c2h_isrs = isrs->ind_isrs & B_BE_HS0ISR_IND_INT ?
rtw89_read32(rtwdev, R_BE_HISR0) & rtwpci->halt_c2h_intrs : 0;
isrs->isrs[0] = isrs->ind_isrs & B_BE_HCI_AXIDMA_INT ?
rtw89_read32(rtwdev, R_BE_HAXI_HISR00) & rtwpci->intrs[0] : 0;
isrs->isrs[1] = rtw89_read32(rtwdev, R_BE_PCIE_DMA_ISR) & rtwpci->intrs[1];
if (isrs->halt_c2h_isrs)
rtw89_write32(rtwdev, R_BE_HISR0, isrs->halt_c2h_isrs);
if (isrs->isrs[0])
rtw89_write32(rtwdev, R_BE_HAXI_HISR00, isrs->isrs[0]);
if (isrs->isrs[1])
rtw89_write32(rtwdev, R_BE_PCIE_DMA_ISR, isrs->isrs[1]);
rtw89_write32(rtwdev, R_BE_PCIE_HISR, isrs->ind_isrs);
}
EXPORT_SYMBOL(rtw89_pci_recognize_intrs_v2);
void rtw89_pci_enable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
{
rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, rtwpci->intrs[0]);
rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, rtwpci->intrs[1]);
}
EXPORT_SYMBOL(rtw89_pci_enable_intr);
void rtw89_pci_disable_intr(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
{
rtw89_write32(rtwdev, R_AX_HIMR0, 0);
rtw89_write32(rtwdev, R_AX_PCIE_HIMR00, 0);
rtw89_write32(rtwdev, R_AX_PCIE_HIMR10, 0);
}
EXPORT_SYMBOL(rtw89_pci_disable_intr);
void rtw89_pci_enable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
{
rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, rtwpci->ind_intrs);
rtw89_write32(rtwdev, R_AX_HIMR0, rtwpci->halt_c2h_intrs);
rtw89_write32(rtwdev, R_AX_HAXI_HIMR00, rtwpci->intrs[0]);
rtw89_write32(rtwdev, R_AX_HIMR1, rtwpci->intrs[1]);
}
EXPORT_SYMBOL(rtw89_pci_enable_intr_v1);
void rtw89_pci_disable_intr_v1(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
{
rtw89_write32(rtwdev, R_AX_PCIE_HIMR00_V1, 0);
}
EXPORT_SYMBOL(rtw89_pci_disable_intr_v1);
void rtw89_pci_enable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
{
rtw89_write32(rtwdev, R_BE_HIMR0, rtwpci->halt_c2h_intrs);
rtw89_write32(rtwdev, R_BE_HAXI_HIMR00, rtwpci->intrs[0]);
rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, rtwpci->intrs[1]);
rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, rtwpci->ind_intrs);
}
EXPORT_SYMBOL(rtw89_pci_enable_intr_v2);
void rtw89_pci_disable_intr_v2(struct rtw89_dev *rtwdev, struct rtw89_pci *rtwpci)
{
rtw89_write32(rtwdev, R_BE_PCIE_HIMR0, 0);
rtw89_write32(rtwdev, R_BE_PCIE_DMA_IMR_0_V1, 0);
}
EXPORT_SYMBOL(rtw89_pci_disable_intr_v2);
static void rtw89_pci_ops_recovery_start(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
unsigned long flags;
spin_lock_irqsave(&rtwpci->irq_lock, flags);
rtw89_chip_disable_intr(rtwdev, rtwpci);
rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RECOVERY_START);
rtw89_chip_enable_intr(rtwdev, rtwpci);
spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
}
static void rtw89_pci_ops_recovery_complete(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
unsigned long flags;
spin_lock_irqsave(&rtwpci->irq_lock, flags);
rtw89_chip_disable_intr(rtwdev, rtwpci);
rtw89_chip_config_intr_mask(rtwdev, RTW89_PCI_INTR_MASK_RECOVERY_COMPLETE);
rtw89_chip_enable_intr(rtwdev, rtwpci);
spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
}
static void rtw89_pci_low_power_interrupt_handler(struct rtw89_dev *rtwdev)
{
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
int budget = NAPI_POLL_WEIGHT;
/* To prevent RXQ get stuck due to run out of budget. */
rtwdev->napi_budget_countdown = budget;
rtw89_pci_poll_rpq_dma(rtwdev, rtwpci, budget);
rtw89_pci_poll_rxq_dma(rtwdev, rtwpci, budget);
}
static irqreturn_t rtw89_pci_interrupt_threadfn(int irq, void *dev)
{
struct rtw89_dev *rtwdev = dev;
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
const struct rtw89_pci_info *info = rtwdev->pci_info;
const struct rtw89_pci_gen_def *gen_def = info->gen_def;
struct rtw89_pci_isrs isrs;
unsigned long flags;
spin_lock_irqsave(&rtwpci->irq_lock, flags);
rtw89_chip_recognize_intrs(rtwdev, rtwpci, &isrs);
spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
if (unlikely(isrs.isrs[0] & gen_def->isr_rdu))
rtw89_pci_isr_rxd_unavail(rtwdev, rtwpci);
if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_halt_c2h))
rtw89_ser_notify(rtwdev, rtw89_mac_get_err_status(rtwdev));
if (unlikely(isrs.halt_c2h_isrs & gen_def->isr_wdt_timeout))
rtw89_ser_notify(rtwdev, MAC_AX_ERR_L2_ERR_WDT_TIMEOUT_INT);
if (unlikely(rtwpci->under_recovery))
goto enable_intr;
if (unlikely(rtwpci->low_power)) {
rtw89_pci_low_power_interrupt_handler(rtwdev);
goto enable_intr;
}
if (likely(rtwpci->running)) {
local_bh_disable();
napi_schedule(&rtwdev->napi);
local_bh_enable();
}
return IRQ_HANDLED;
enable_intr:
spin_lock_irqsave(&rtwpci->irq_lock, flags);
if (likely(rtwpci->running))
rtw89_chip_enable_intr(rtwdev, rtwpci);
spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
return IRQ_HANDLED;
}
static irqreturn_t rtw89_pci_interrupt_handler(int irq, void *dev)
{
struct rtw89_dev *rtwdev = dev;
struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv;
unsigned long flags;
irqreturn_t irqret = IRQ_WAKE_THREAD;
spin_lock_irqsave(&rtwpci->irq_lock, flags);
/* If interrupt event is on the road, it is still trigger interrupt
* even we have done pci_stop() to turn off IMR.
*/
if (unlikely(!rtwpci->running)) {
irqret = IRQ_HANDLED;
goto exit;
}
rtw89_chip_disable_intr(rtwdev, rtwpci);
exit:
spin_unlock_irqrestore(&rtwpci->irq_lock, flags);
return irqret;
}
#define DEF_TXCHADDRS_TYPE2(gen, ch_idx, txch, v...) \
[RTW89_TXCH_##ch_idx] = { \
.num = R_##gen##_##txch##_TXBD_NUM ##v, \
.idx = R_##gen##_##txch##_TXBD_IDX ##v, \
.bdram = 0, \
.desa_l = R_##gen##_##txch##_TXBD_DESA_L ##v, \
.desa_h = R_##gen##_##txch##_TXBD_DESA_H ##v, \
}
#define DEF_TXCHADDRS_TYPE1(info, txch, v...) \
[RTW89_TXCH_##txch] = { \
.num = R_AX_##txch##_TXBD_NUM ##v, \
.idx = R_AX_##txch##_TXBD_IDX ##v, \
.bdram = R_AX_##txch##_BDRAM_CTRL ##v, \
.desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \
.desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \
}
#define DEF_TXCHADDRS(info, txch, v...) \
[RTW89_TXCH_##txch] = { \
.num = R_AX_##txch##_TXBD_NUM, \
.idx = R_AX_##txch##_TXBD_IDX, \
.bdram = R_AX_##txch##_BDRAM_CTRL ##v, \
.desa_l = R_AX_##txch##_TXBD_DESA_L ##v, \
.desa_h = R_AX_##txch##_TXBD_DESA_H ##v, \
}
#define DEF_RXCHADDRS(gen, ch_idx, rxch, v...) \
[RTW89_RXCH_##ch_idx] = { \
.num = R_##gen##_##rxch##_RXBD_NUM ##v, \
.idx = R_##gen##_##rxch##_RXBD_IDX ##v, \
.desa_l = R_##gen##_##rxch##_RXBD_DESA_L ##v, \
.desa_h = R_##gen##_##rxch##_RXBD_DESA_H ##v, \
}
const struct rtw89_pci_ch_dma_addr_set rtw89_pci_ch_dma_addr_set = {
.tx = {
DEF_TXCHADDRS(info, ACH0),
DEF_TXCHADDRS(info, ACH1),
DEF_TXCHADDRS(info, ACH2),
DEF_TXCHADDRS(info, ACH3),
DEF_TXCHADDRS(info, ACH4),
DEF_TXCHADDRS(info, ACH5),
DEF_TXCHADDRS(info, ACH6),
DEF_TXCHADDRS(info, ACH7),
DEF_TXCHADDRS(info, CH8),
DEF_TXCHADDRS(info, CH9),
DEF_TXCHADDRS_TYPE1(info, CH10),
DEF_TXCHADDRS_TYPE1(info, CH11),
DEF_TXCHADDRS(info, CH12),
},
.rx = {
DEF_RXCHADDRS(AX, RXQ, RXQ),
DEF_RXCHADDRS(AX, RPQ, RPQ),
},
};
EXPORT_SYMBOL(rtw89_pci_ch_dma_addr_set);