SU-Servo: Gateware feed ASF to outdated default profile

[occheung]

Bug Report

One-Line Summary

The SU-Servo gateware sends data to profile 0, while profile 7 is enabled by default on the CPLD.

Issue Details

It is caused by not updating the gateware of SU-Servo after this change of urukul.py in #1584. @pmldrmota

Steps to Reproduce

Enable SU-Servo. Run an experiment that involves SU-Servo.

Example: (Similar to the one on artiq_sinara_tester)

class SUServoExample(EnvExperiment):
    def build(self):
        self.setattr_device("core")
        self.suservo = self.get_device("suservo0")
        self.suschannels = [
            self.get_device("suservo0_ch"+str(i)) for i in range(8)
        ]

    @kernel
    def run(self):
        self.core.reset()
        self.core.break_realtime()
        self.suservo.init()
        self.suservo.set_pgia_mu(0, 0)  # unity gain
        self.suservo.cplds[0].set_att(0, 15.)
        self.suschannels[0].set_y(profile=0, y=0.) # Clear integrator
        self.suschannels[0].set_iir(
            profile=0,
            adc=0,          # take data from Sampler channel 0
            kp=-1.,         # -1 P gain
            ki=0./s,        # no integrator gain
            g=0.,           # no integrator gain limit
            delay=0.        # no IIR update delay after enabling
        )
        self.suschannels[0].set_dds(
            profile=0,
            offset=-.3,     # 3 V with above PGIA settings
            frequency=10*MHz,
            phase=0.)
        # enable RF, IIR updates and set profile
        self.suschannels[0].set(en_out=1, en_iir=1, profile=0)
        self.suservo.set_config(enable=1)

Expected Behavior

Urukul is able to output waveform.

Actual (undesired) Behavior

No waveform from Urukul.

Your System (omit irrelevant parts)

• ARTIQ version (including gateware & firmware): Latest master as of writing this issue.
• Hardware involved: SU-Servo

Proposed Solution

Update the profile that the SU-Servo gateware will feed ASF to. (See this line)

[pmldrmota]

A software-only solution would be adding a derived CPLD class like this to coredevice/urukul.py and changing the device_db so that all SUServo cards use it instead.

from artiq.coredevice import urukul

class CPLD(urukul.CPLD):
    def __init__(self, *args, **kwargs):
        super().__init__(*args, **kwargs)
        self.cfg_reg &= ~(7 << urukul.CFG_PROFILE)

We use this pattern to implement half-duplex readback for phase-coherent SUServo. The PR for this is still in the waiting stage (will follow up on #1782), but you can have a look at 4d3c889.