Commits on Jun 16, 2020

1. SUServo: support arbitrary number of Urukuls and add coherent phase m… …

   …ode with per-channel control.
   
    - Refactoring of the pipelined IIR processing core, accepting any number of ADC input channels and DDS output channels with minimal ressource usage. (Previously restricted to a power of 2.)
    - Using half-duplex SPI mode for readback from Urukul CPLDs in NU-mode (DIP switches configured for SUServo operation). To use this feature, the CPLDs require the corresponding update.
    - Extension of the per-channel control interface by a flag , serving to enable coherent DDS phase mode. This works by tracking the DDS-internal phase accumulator as well as the servo runtime to calculate the POW accordingly.
    - Reverse-compatible extension of the channel RTIO addresses for setting the reference time of a channel for coherent phase mode in real time (intended for use in DMA sequences).
    - To ensure coherent phase updates, the io_update line of an Urukul is converted into a SERDES output. The I/O update alignment delays can be configured by writing to servo memory. The optimal alignment delay can be found using the existing method, relying on half-duplex CPLD readback capability.
    - Further, to ensure coherent phase updates, the sync_in line of all Urukuls is connected to a  phy. The optimal sync settings can be found using the existing method, relying on half-duplex CPLD readback capability.
    - Restructuring of the servo RTIO addresses to make space for the I/O update alignment delay memory. This is done efficiently and does not increase the address width.

   

   pmldrmota committed Jun 16, 2020
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