From 573e4cc0ba599d7de24cb8da8f404dfbdc46a417 Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Thu, 10 Oct 2024 12:00:34 +0800
Subject: [PATCH] fifo: implement almost_empty/full

---
 migen/genlib/fifo.py | 25 ++++++++++++++++++++++---
 1 file changed, 22 insertions(+), 3 deletions(-)

diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index 0b90e3359..381628fa7 100644
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -1,3 +1,6 @@
+from functools import reduce
+from operator import and_, or_
+
 from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 from migen.fhdl.specials import Memory, READ_FIRST
@@ -79,6 +82,22 @@ def write(self, data):
         yield self.we.eq(0)
         yield
 
+    def add_almost_full(self, hi_wm):
+        self.almost_full = Signal()
+        if hi_wm.bit_count() == 1:
+            self.comb += self.almost_full.eq(
+                reduce(or_, [level_i for level_i in self.level[log2_int(hi_wm):]]))
+        else:
+            self.comb += self.almost_full.eq(self.level >= hi_wm)
+
+    def add_almost_empty(self, lo_wm):
+        self.almost_empty = Signal()
+        if lo_wm.bit_count() == 1:
+            self.comb += self.almost_empty.eq(
+                reduce(and_, [~level_i for level_i in self.level[log2_int(lo_wm):]]) | (self.level == lo_wm))
+        else:
+            self.comb += self.almost_empty.eq(self.level <= lo_wm)
+
 
 class SyncFIFO(Module, _FIFOInterface):
     """Synchronous FIFO (first in, first out)
@@ -96,7 +115,7 @@ class SyncFIFO(Module, _FIFOInterface):
     """
     __doc__ = __doc__.format(interface=_FIFOInterface.__doc__)
 
-    def __init__(self, width, depth, fwft=True):
+    def __init__(self, width, depth, fwft=True, hi_wm=None, lo_wm=None):
         _FIFOInterface.__init__(self, width, depth)
 
         self.level = Signal(max=depth+1)
@@ -152,9 +171,9 @@ class SyncFIFOBuffered(Module, _FIFOInterface):
     """Has an interface compatible with SyncFIFO with fwft=True,
     but does not use asynchronous RAM reads that are not compatible
     with block RAMs. Increases latency by one cycle."""
-    def __init__(self, width, depth):
+    def __init__(self, width, depth, hi_wm=None, lo_wm=None):
         _FIFOInterface.__init__(self, width, depth)
-        self.submodules.fifo = fifo = SyncFIFO(width, depth, False)
+        self.submodules.fifo = fifo = SyncFIFO(width, depth, False, hi_wm, lo_wm)
 
         self.writable = fifo.writable
         self.din = fifo.din