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I came across this bug, too. Only mode=READ_FIRST leads to vivado inferring a TDP ram. mode=WRITE_FIRST leads to distributed ram which somehow shows different behavior than a write first TDP. Specifically vivado would sometimes omit the write enable signal and set it to constant high. NextPnR had no problem correctly inferring a write first TDP.
No mention of it being detected as a TDP pattern by Vivado (when WRITE_FIRST it is detected)
Used in artiq/suservo:
https://github.com/m-labs/artiq/blob/7d4a103a43a2cc4c1787eaa7aff2f37de8738050/artiq/gateware/suservo/iir.py#L347
https://github.com/m-labs/artiq/blob/7d4a103a43a2cc4c1787eaa7aff2f37de8738050/artiq/gateware/rtio/phy/servo.py#L34-L37
Verilog:
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