Negative initialization produces incorrect verilog

[JohnSully]

Migen:
self.idx = Signal(max=depth, reset=-1)

Generated Verilog:
reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_idx = 4'd-1;

The assigned value should be -4'd1 instead to be valid Verilog. Not my favourite thing about the language.

[sbourdeauducq]

Your signal must be signed for a negative value to be legitimate. Migen should print an error here instead of emitting invalid verilog, maybe at the minimum add an assert in _printconstant.

[sbourdeauducq]

Though this isn't consistent with what happens when assigning a negative value to an unsigned signal; so maybe _printconstant should handle it.

[JohnSully]

It's probably horrible practice, but I do it to set a signal to 0xFF regardless of its length. The rest of the code uses it unsigned.

[JohnSully]

Signal(max=depth, ~0) produces the same incorrect code. What's the right way to initialize a signal to all 1s?

[sbourdeauducq]

2**depth-1

[JohnSully]

I think it would have to be 2**(ceil(log2(depth))-1 right?

-1 or ~0 is much easier, and should be supported for this case in my opinion.

[sbourdeauducq]

OK.
~0 == -1 in Python.

[whitequark]

Triage: fixed in nMigen. In particular, ~0 and -1 initialization values for signed as well as unsigned signals produce the expected result.