Incorrect simulation of Cat()

[enurseitov]

Consider this minimal example:

from migen import *
from migen.fhdl import verilog

class my_module(Module):
    def __init__(self):
        self.input = Signal(8)
        self.output = Signal(32)
        self.comb += self.output.eq(Cat(self.input, self.input+1, self.input+2, self.input+3))
        
def tb(dut):
    yield dut.input.eq(0)
    print(f'{(yield dut.output):#010x}')

m = my_module()
run_simulation(m, tb(m))
# print(verilog.convert(m))

Expected output: 0x03020100
Produced output: 0x0c040100, i.e. self.input+1 takes 9 bits, the next one takes 10 bits etc.

Yet, the generated Verilog code is correct and produces expected results when simulated by Vivado simulator: assign output_1 = {(input_1 + 2'd3), (input_1 + 2'd2), (input_1 + 1'd1), input_1};

[sbourdeauducq]

It's the generated Verilog that's incorrect - self.input+x are supposed to be 9-bit numbers.

[sbourdeauducq]

the next one takes 10 bits

It doesn't.

[enurseitov]

Yes after thinking about it I admit that my expectations were wrong, the way migen behaves makes sense. Still, the mismatch with Verilog is there...