nec/pc9801_v.cpp: fix 15 kHz pixel clock

mamedev · Nov 14, 2024 · e9bdabe · e9bdabe
1 parent 99a165c
commit e9bdabe
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Showing 2 changed files with 9 additions and 2 deletions.
diff --git a/src/devices/bus/cbus/pc9801_86.cpp b/src/devices/bus/cbus/pc9801_86.cpp
@@ -357,7 +357,13 @@ void pc9801_86_device::io_map(address_map &map)
 		}),
 		NAME([this] (u8 data) {
 			if(m_pcm_ctrl & 0x20)
+			{
+				// TODO: may fall over with the irq logic math
+				// queue_count() < (0xff + 1) << 7 = 0x8000 -> always true
+				if (data == 0xff)
+					popmessage("pc9801_86: $a46a irq_rate == 0xff");
 				m_irq_rate = (data + 1) * 128;
+			}
 			else
 				m_pcm_mode = data;
 		})

diff --git a/src/mame/nec/pc9801_v.cpp b/src/mame/nec/pc9801_v.cpp
@@ -502,8 +502,9 @@ void pc9801vm_state::border_color_w(offs_t offset, u8 data)
 	if (offset)
 	{
 		// 24.83/15.75 kHz selector, available for everything but vanilla class
-		// TODO: verify clock for 200 line mode (handtuned), verify that vanilla effectively cannot select it thru dips.
-		const XTAL screen_clock = (data & 1 ? XTAL(21'052'600) : (XTAL(21'052'600) / 3) * 2) / 8;
+		// TODO: verify that vanilla effectively cannot select it thru dips.
+		// TODO: pc9801vm doesn't access this
+		const XTAL screen_clock = (data & 1 ? XTAL(21'052'600) : XTAL(14'318'181)) / 8;
 
 		m_hgdc[0]->set_unscaled_clock(screen_clock);
 		m_hgdc[1]->set_unscaled_clock(screen_clock);