Update dependency at_clifford_yosys2 to v0.46

[renovate]

This PR contains the following updates:

Package	Type	Update	Change
at_clifford_yosys2	http_archive	minor	yosys-0.44 -> 0.46

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Release Notes

YosysHQ/yosys (at_clifford_yosys2)

v0.46

Compare Source

v0.45

Compare Source

• Various

  • Added new "functional backend" infrastructure with three example
    backends (C++, SMTLIB and Rosette).
  • Added new coarse-grain buffer cell type "$buf" to RTLIL.
  • Added "-y" command line option to execute a Python script with
    libyosys available as a built-in module.
  • Added support for casting to type in Verilog frontend.

• New commands and options

  • Added "clockgate" pass for automatic clock gating cell insertion.
  • Added "bufnorm" experimental pass to convert design into
    buffered-normalized form.
  • Added experimental "aiger2" and "xaiger2" backends, and an
    experimental "abc_new" command
  • Added "-force-detailed-loop-check" option to "check" pass.
  • Added "-unit_delay" option to "read_liberty" pass.

• Verific support

  • Added left and right bound properties to wires when using
    specific VHDL types.

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