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Nrfx 5848 add gpio edriver #1
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e565bdf
manifest: update hal_nordic version
magp-nordic 9708bb4
dts: bindings: add new binding for eGPIO
magp-nordic 646d119
modules: hal_nordic: add option for emulated peripherals drivers
magp-nordic d3d264b
soc: nordic: common: add eGPIO to peripherals
magp-nordic 5967087
soc: nordic: nrf54l: add support for NRFE
magp-nordic b3473e0
dts: arm: nordic: nRF54L15: add egpio node
magp-nordic 31cfe71
drivers: gpio: add eGPIO driver
magp-nordic 6c04740
samples: basic: blinky: modify to use eGPIO
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Original file line number | Diff line number | Diff line change |
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# Copyright (c) 2024 Nordic Semiconductor ASA | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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menuconfig GPIO_NRFE | ||
bool "Emulated GPIO" | ||
default y | ||
depends on DT_HAS_NORDIC_NRF_EGPIO_ENABLED | ||
select NRFE_GPIO if HAS_HW_NRF_EGPIO | ||
select IPC_SERVICE | ||
select IPC_SERVICE_BACKEND_ICMSG | ||
select MBOX | ||
help | ||
Use emulated GPIO driver. | ||
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# eGPIO initialization depends on IPC initialization which is done at the same init level and | ||
# has init priority equal to 46. | ||
config EGPIO_INIT_PRIORITY | ||
int "eGPIO init priority" | ||
depends on GPIO_NRFE | ||
default 48 | ||
help | ||
eGPIO driver device initialization priority. |
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/* | ||
* Copyright (c) 2024, Nordic Semiconductor ASA | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#define DT_DRV_COMPAT nordic_nrf_egpio | ||
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#include <nrfe_gpio.h> | ||
#include <zephyr/drivers/gpio.h> | ||
#include <zephyr/drivers/gpio/gpio_utils.h> | ||
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#include <zephyr/device.h> | ||
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#include <zephyr/ipc/ipc_service.h> | ||
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K_SEM_DEFINE(bound_sem, 0, 1); | ||
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static void ep_bound(void *priv) | ||
{ | ||
k_sem_give(&bound_sem); | ||
} | ||
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static void ep_recv(const void *data, size_t len, void *priv) | ||
{ | ||
} | ||
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static struct ipc_ept_cfg ep_cfg = { | ||
.cb = { | ||
.bound = ep_bound, | ||
.received = ep_recv, | ||
}, | ||
}; | ||
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struct ipc_ept ep; | ||
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struct gpio_nrfe_data { | ||
/* gpio_driver_data needs to be first */ | ||
struct gpio_driver_data common; | ||
}; | ||
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struct gpio_nrfe_cfg { | ||
/* gpio_driver_config needs to be first */ | ||
struct gpio_driver_config common; | ||
uint8_t port_num; | ||
}; | ||
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static inline const struct gpio_nrfe_cfg *get_port_cfg(const struct device *port) | ||
{ | ||
return port->config; | ||
} | ||
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static int gpio_nrfe_pin_configure(const struct device *port, gpio_pin_t pin, gpio_flags_t flags) | ||
{ | ||
nrfe_gpio_data_packet_t msg = {.opcode = NRFE_GPIO_PIN_CONFIGURE, | ||
.pin = pin, | ||
.port = get_port_cfg(port)->port_num, | ||
.flags = flags}; | ||
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return ipc_service_send(&ep, (void *)(&msg), sizeof(nrfe_gpio_data_packet_t)); | ||
} | ||
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static int gpio_nrfe_port_set_masked_raw(const struct device *port, gpio_port_pins_t mask, | ||
gpio_port_value_t value) | ||
{ | ||
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const uint32_t set_mask = value & mask; | ||
const uint32_t clear_mask = (~set_mask) & mask; | ||
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nrfe_gpio_data_packet_t msg = { | ||
.opcode = NRFE_GPIO_PIN_SET, .pin = set_mask, .port = get_port_cfg(port)->port_num}; | ||
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int ret_val = ipc_service_send(&ep, (void *)(&msg), sizeof(nrfe_gpio_data_packet_t)); | ||
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if (ret_val < 0) { | ||
return ret_val; | ||
} | ||
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msg.opcode = NRFE_GPIO_PIN_CLEAR; | ||
msg.pin = clear_mask; | ||
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return ipc_service_send(&ep, (void *)(&msg), sizeof(nrfe_gpio_data_packet_t)); | ||
} | ||
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static int gpio_nrfe_port_set_bits_raw(const struct device *port, gpio_port_pins_t mask) | ||
{ | ||
nrfe_gpio_data_packet_t msg = { | ||
.opcode = NRFE_GPIO_PIN_SET, .pin = mask, .port = get_port_cfg(port)->port_num}; | ||
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return ipc_service_send(&ep, (void *)(&msg), sizeof(nrfe_gpio_data_packet_t)); | ||
} | ||
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static int gpio_nrfe_port_clear_bits_raw(const struct device *port, gpio_port_pins_t mask) | ||
{ | ||
nrfe_gpio_data_packet_t msg = { | ||
.opcode = NRFE_GPIO_PIN_CLEAR, .pin = mask, .port = get_port_cfg(port)->port_num}; | ||
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return ipc_service_send(&ep, (void *)(&msg), sizeof(nrfe_gpio_data_packet_t)); | ||
} | ||
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static int gpio_nrfe_port_toggle_bits(const struct device *port, gpio_port_pins_t mask) | ||
{ | ||
nrfe_gpio_data_packet_t msg = { | ||
.opcode = NRFE_GPIO_PIN_TOGGLE, .pin = mask, .port = get_port_cfg(port)->port_num}; | ||
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return ipc_service_send(&ep, (void *)(&msg), sizeof(nrfe_gpio_data_packet_t)); | ||
} | ||
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static int gpio_nrfe_init(const struct device *port) | ||
{ | ||
const struct device *ipc0_instance = DEVICE_DT_GET(DT_NODELABEL(ipc0)); | ||
int ret = ipc_service_open_instance(ipc0_instance); | ||
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if ((ret < 0) && (ret != -EALREADY)) { | ||
return ret; | ||
} | ||
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ret = ipc_service_register_endpoint(ipc0_instance, &ep, &ep_cfg); | ||
if (ret < 0) { | ||
return ret; | ||
} | ||
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k_sem_take(&bound_sem, K_FOREVER); | ||
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return 0; | ||
} | ||
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static const struct gpio_driver_api gpio_nrfe_drv_api_funcs = { | ||
.pin_configure = gpio_nrfe_pin_configure, | ||
.port_set_masked_raw = gpio_nrfe_port_set_masked_raw, | ||
.port_set_bits_raw = gpio_nrfe_port_set_bits_raw, | ||
.port_clear_bits_raw = gpio_nrfe_port_clear_bits_raw, | ||
.port_toggle_bits = gpio_nrfe_port_toggle_bits, | ||
}; | ||
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#define GPIO_NRFE_DEVICE(id) \ | ||
static const struct gpio_nrfe_cfg gpio_nrfe_p##id##_cfg = { \ | ||
.common = \ | ||
{ \ | ||
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id), \ | ||
}, \ | ||
.port_num = DT_INST_PROP(id, port), \ | ||
}; \ | ||
\ | ||
static struct gpio_nrfe_data gpio_nrfe_p##id##_data; \ | ||
\ | ||
DEVICE_DT_INST_DEFINE(id, gpio_nrfe_init, NULL, &gpio_nrfe_p##id##_data, \ | ||
&gpio_nrfe_p##id##_cfg, POST_KERNEL, CONFIG_EGPIO_INIT_PRIORITY, \ | ||
&gpio_nrfe_drv_api_funcs); | ||
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DT_INST_FOREACH_STATUS_OKAY(GPIO_NRFE_DEVICE) |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,29 @@ | ||
# Copyright (c) 2018, marc-cpdesign | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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description: Emulated GPIO node | ||
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compatible: "nordic,nrf-egpio" | ||
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include: [gpio-controller.yaml, base.yaml] | ||
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properties: | ||
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"#gpio-cells": | ||
const: 2 | ||
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port: | ||
type: int | ||
required: true | ||
description: | | ||
The GPIO port number. GPIO port P0 has: | ||
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port = <0>; | ||
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And P1 has: | ||
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port = <1>; | ||
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gpio-cells: | ||
- pin | ||
- flags |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,6 @@ | ||
# Copyright (c) 2024 Nordic Semiconductor ASA | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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zephyr_library() | ||
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zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/nrfe) |
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# Copyright (c) 2024 Nordic Semiconductor ASA | ||
# SPDX-License-Identifier: Apache-2.0 | ||
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config HAS_NRFE | ||
bool | ||
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menu "nRF Emulated Peripherals" | ||
depends on HAS_NRFE | ||
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config NRFE_GPIO | ||
bool "eGPIO driver instance" | ||
depends on $(dt_nodelabel_has_compat,egpio,$(DT_COMPAT_NORDIC_NRF_EGPIO)) | ||
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endmenu |
53 changes: 53 additions & 0 deletions
53
samples/basic/blinky/boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
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/* | ||
* Copyright (c) 2024 Nordic Semiconductor ASA | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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/ { | ||
soc { | ||
reserved-memory { | ||
#address-cells = <1>; | ||
#size-cells = <1>; | ||
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sram_rx: memory@20018000 { | ||
reg = <0x20018000 0x0800>; | ||
}; | ||
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sram_tx: memory@20020000 { | ||
reg = <0x20020000 0x0800>; | ||
}; | ||
}; | ||
}; | ||
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ipc { | ||
ipc0: ipc0 { | ||
compatible = "zephyr,ipc-icmsg"; | ||
tx-region = <&sram_tx>; | ||
rx-region = <&sram_rx>; | ||
mboxes = <&cpuapp_vevif_rx 15>, <&cpuapp_vevif_tx 16>; | ||
mbox-names = "rx", "tx"; | ||
status = "okay"; | ||
}; | ||
}; | ||
}; | ||
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&gpio2 { | ||
status = "disabled"; | ||
}; | ||
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&egpio { | ||
status = "okay"; | ||
}; | ||
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&cpuapp_vevif_rx { | ||
status = "okay"; | ||
}; | ||
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&cpuapp_vevif_tx { | ||
status = "okay"; | ||
}; | ||
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&led0 { | ||
gpios = <&egpio 9 GPIO_ACTIVE_HIGH>; | ||
}; |
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A way to detect pin conflicts would be needed in future.