register file: explicitly use synchronous read RAM #2
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Lattice was essentially implicitly instanciating the Write_Data, Bypass_D and Bypass_R registers and adding the apropriate muxes. Now that the register bypass is explcit, there should be no more race conditions (i.e. concurrent <= assignments) and yosys is able to infer the correct RAM.
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Lattice was essentially implicitly instanciating
the Write_Data, Bypass_D and Bypass_R registers
and adding the apropriate muxes.
Now that the register bypass is explcit, there should
be no more race conditions (i.e. concurrent <= assignments)
and yosys is able to infer the correct RAM.
Let me know if you are interested in this change.