From 90efe16dca7e82c4fef605ef26aa61fb222cd8c2 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 7 Mar 2022 10:57:18 +0800 Subject: [PATCH 1/4] feat: add hello demo module --- rtl/tc_l1/hello/Makefile | 8 ++++++++ rtl/tc_l1/hello/hello.cpp | 16 ++++++++++++++++ rtl/tc_l1/hello/hello.v | 6 ++++++ 3 files changed, 30 insertions(+) create mode 100644 rtl/tc_l1/hello/Makefile create mode 100644 rtl/tc_l1/hello/hello.cpp create mode 100644 rtl/tc_l1/hello/hello.v diff --git a/rtl/tc_l1/hello/Makefile b/rtl/tc_l1/hello/Makefile new file mode 100644 index 0000000..c1d08ac --- /dev/null +++ b/rtl/tc_l1/hello/Makefile @@ -0,0 +1,8 @@ +comp: + verilator -Wall --cc --exe --build hello.cpp hello.v -o emu -Mdir build + +run: + ./build/emu + +.PHONY: + comp run \ No newline at end of file diff --git a/rtl/tc_l1/hello/hello.cpp b/rtl/tc_l1/hello/hello.cpp new file mode 100644 index 0000000..87caf78 --- /dev/null +++ b/rtl/tc_l1/hello/hello.cpp @@ -0,0 +1,16 @@ +#include "Vhello.h" +#include "verilated.h" + +int main(int argc, char **argv, char **env) +{ + VerilatedContext *contextp = new VerilatedContext; + contextp->commandArgs(argc, argv); + Vhello *top = new Vhello{contextp}; + while (!contextp->gotFinish()) + { + top->eval(); + } + delete top; + delete contextp; + return 0; +} \ No newline at end of file diff --git a/rtl/tc_l1/hello/hello.v b/rtl/tc_l1/hello/hello.v new file mode 100644 index 0000000..bab6f81 --- /dev/null +++ b/rtl/tc_l1/hello/hello.v @@ -0,0 +1,6 @@ +module hello; + initial begin + $display("Hello World"); + $finish; + end +endmodule From 2d503510af635e8ffd95536f5f30a05314134338 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Mon, 7 Mar 2022 11:06:35 +0800 Subject: [PATCH 2/4] feat: add 2bit ctrl switch demo --- rtl/tc_l1/switch/Makefile | 8 ++++++++ rtl/tc_l1/switch/top.cpp | 26 ++++++++++++++++++++++++++ rtl/tc_l1/switch/top.v | 7 +++++++ 3 files changed, 41 insertions(+) create mode 100644 rtl/tc_l1/switch/Makefile create mode 100644 rtl/tc_l1/switch/top.cpp create mode 100644 rtl/tc_l1/switch/top.v diff --git a/rtl/tc_l1/switch/Makefile b/rtl/tc_l1/switch/Makefile new file mode 100644 index 0000000..9f99ab1 --- /dev/null +++ b/rtl/tc_l1/switch/Makefile @@ -0,0 +1,8 @@ +comp: + verilator -Wall --cc --exe --build top.cpp top.v -o emu -Mdir build + +run: + ./build/emu + +.PHONY: + comp run \ No newline at end of file diff --git a/rtl/tc_l1/switch/top.cpp b/rtl/tc_l1/switch/top.cpp new file mode 100644 index 0000000..e396397 --- /dev/null +++ b/rtl/tc_l1/switch/top.cpp @@ -0,0 +1,26 @@ +#include +#include +#include + +#include "Vtop.h" +#include "verilated.h" + +int main(int argc, char **argv, char **env) +{ + VerilatedContext *contextp = new VerilatedContext; + contextp->commandArgs(argc, argv); + Vtop *top = new Vtop{contextp}; + while (!contextp->gotFinish()) + { + int a = rand() & 1; + int b = rand() & 1; + top->a = a; + top->b = b; + top->eval(); + printf("a = %d, b = %d, f = %d\n", a, b, top->f); + assert(top->f == a ^ b); + } + delete top; + delete contextp; + return 0; +} diff --git a/rtl/tc_l1/switch/top.v b/rtl/tc_l1/switch/top.v new file mode 100644 index 0000000..878492a --- /dev/null +++ b/rtl/tc_l1/switch/top.v @@ -0,0 +1,7 @@ +module top( + input a, + input b, + output f +); + assign f = a ^ b; +endmodule From 39f69c9ef972a6761425d92ded71dc7fd6d2a195 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Thu, 10 Mar 2022 18:41:39 +0800 Subject: [PATCH 3/4] chore: add exec perms to install and record scripts --- rtl/scripts/install.sh | 0 rtl/scripts/record.sh | 2 ++ 2 files changed, 2 insertions(+) mode change 100644 => 100755 rtl/scripts/install.sh create mode 100755 rtl/scripts/record.sh diff --git a/rtl/scripts/install.sh b/rtl/scripts/install.sh old mode 100644 new mode 100755 diff --git a/rtl/scripts/record.sh b/rtl/scripts/record.sh new file mode 100755 index 0000000..05a7907 --- /dev/null +++ b/rtl/scripts/record.sh @@ -0,0 +1,2 @@ +#!/bin/bash + From a7f94f6cf73eb13d7fcef0e777767b6730bc5ba7 Mon Sep 17 00:00:00 2001 From: maksyuki Date: Sat, 12 Mar 2022 13:17:51 +0800 Subject: [PATCH 4/4] docs: add 3rd party licenses statement --- LICENSE_3RD_PARTY.md | 56 ++++++++++++++++++++++++++++++++++++++++++++ README.md | 2 +- 2 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 LICENSE_3RD_PARTY.md diff --git a/LICENSE_3RD_PARTY.md b/LICENSE_3RD_PARTY.md new file mode 100644 index 0000000..65cd98d --- /dev/null +++ b/LICENSE_3RD_PARTY.md @@ -0,0 +1,56 @@ +# Open Source License Acknowledgements and Third-Party Copyrights + +TreeCore CPU utilizes third party software from various sources. Portions of this software are copyrighted by their respective owners as indicated in the copyright notices below. + +The following acknowledgements pertain to this software license. + +## Main components used by TreeCore CPU +These components are installed via composer or via npm. You can check all the dependencies using the instructions from the section Libraries dynamically referenced via Composer and Libraries dynamically referenced via npm. + +### verilator +* maintainer: [verilator](https://github.com/verilator) +* License: [LGPL-3.0](https://github.com/verilator/verilator/blob/master/LICENSE) +* repo: https://github.com/verilator/verilator + +### mill +* maintainer: [com-lihaoyi](https://github.com/com-lihaoyi) +* License: [MIT](https://github.com/com-lihaoyi/mill/blob/main/LICENSE) +* repo: https://github.com/com-lihaoyi/mill + +### riscv-test +* maintainer: [NJU-ProjectN](https://github.com/NJU-ProjectN) +* License: [custom](https://github.com/NJU-ProjectN/riscv-tests/blob/master/LICENSE) +* repo: https://github.com/NJU-ProjectN/riscv-tests + +### difftest +* maintainer: [oscpu](https://gitee.com/oscpu) +* License: [MulanPSL-2.0](https://gitee.com/oscpu/difftest/blob/master/LICENSE) +* repo: https://gitee.com/oscpu/difftest + +### NEMU +* maintainer: [oscpu](https://gitee.com/oscpu) +* License: [MulanPSL-2.0](https://gitee.com/oscpu/difftest/blob/master/LICENSE) +* repo: https://gitee.com/oscpu/NEMU + +### DRAMsim3 +* maintainer: [OpenXiangShan](https://github.com/OpenXiangShan) +* License: [MIT](https://github.com/OpenXiangShan/DRAMsim3/blob/co-simulation/LICENSE) +* repo: https://github.com/OpenXiangShan/DRAMsim3 + +### ysyxSoC +* maintainer: [oscpu](https://github.com/OSCPU) +* License: [custom](https://github.com/OSCPU/ysyxSoC/blob/master/LICENSE.Berkeley) +* repo: https://github.com/OSCPU/ysyxSoC + +## Libraries modified for TreeCore CPU +These libraries derive from [NJU-ProjectN](https://github.com/NJU-ProjectN) and are modified specifically for TreeCore CPU. + +### abstract-machine +* maintainer: [maksyuki](https://github.com/maksyuki) +* License: [GPL-3.0](https://github.com/maksyuki/ysyx-software-file/blob/master/LICENSE) +* repo: https://github.com/maksyuki/ysyx-software-file/tree/master/abstract-machine + +### am-kernels +* maintainer: [maksyuki](https://github.com/maksyuki) +* License: [GPL-3.0](https://github.com/maksyuki/ysyx-software-file/blob/master/LICENSE) +* repo: https://github.com/maksyuki/ysyx-software-file/tree/master/am-kernels \ No newline at end of file diff --git a/README.md b/README.md index 9cc2378..a585a3e 100644 --- a/README.md +++ b/README.md @@ -282,7 +282,7 @@ $ make template ## Update ## License -All of the TreeCore codes are release under the [GPL-3.0 License](LICENSE). +TreeCore CPU's codes are release under the [GPL-3.0 License](LICENSE) and compliance with other open source agreements. You can find all 3rd party libraries licenses in [LICENSE_3RD_PARTY.md](LICENSE_3RD_PARTY). ## Acknowledgement 1. [oscpu-framework](https://github.com/OSCPU/oscpu-framework)