feat: modify some vars's name

microdynamics-cpu · Jan 7, 2022 · e1e5773 · e1e5773
1 parent 5548122
commit e1e5773
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Showing 2 changed files with 6 additions and 6 deletions.
diff --git a/rtl/tc_l2/src/main/scala/core/if/BTB.scala b/rtl/tc_l2/src/main/scala/core/if/BTB.scala
@@ -40,9 +40,9 @@ class BTB extends Module {
   }
 
   // signals about BTB lookup
-  val lookupIdx   = io.lookupPc(ConstVal.BTBIdxLen - 1, 0)
-  val lookupPcSel = io.lookupPc
-  val btbHit      = valids(lookupIdx) && lines(lookupIdx).pc === lookupPcSel
+  protected val lookupIdx   = io.lookupPc(ConstVal.BTBIdxLen - 1, 0)
+  protected val lookupPcSel = io.lookupPc
+  protected val btbHit      = valids(lookupIdx) && lines(lookupIdx).pc === lookupPcSel
 
   // BTB lookup
   io.lookupBranch := btbHit

diff --git a/rtl/tc_l2/src/main/scala/core/if/GHR.scala b/rtl/tc_l2/src/main/scala/core/if/GHR.scala
@@ -12,11 +12,11 @@ class GHR extends Module {
     val idx    = Output(UInt(ConstVal.GHRLen.W))
   })
 
-  protected val ghr = Reg(UInt(ConstVal.GHRLen.W))
+  protected val shiftReg = Reg(UInt(ConstVal.GHRLen.W))
 
   when(io.branch) {
-    ghr := Cat(ghr(ConstVal.GHRLen - 2, 0), io.taken)
+    shiftReg := Cat(shiftReg(ConstVal.GHRLen - 2, 0), io.taken)
   }
 
-  io.idx := ghr
+  io.idx := shiftReg
 }