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TreeCore IP: A series of HDL IP with Accurate-cycle, Event-driven Simulation Model and UVM Verification

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Overview

Core

  1. RV32
  2. RV64

System

  1. UART
  2. SPI FLASH
  3. AMBA BUS
  4. TRACE
  5. JTAG

Peripheral

  1. TIMER
  2. GPIO
  3. PS/2
  4. SPI
  5. I2C
  6. I2S
  7. USB
  8. SDIO

Memory System

  1. ChipLink
  2. SDRAM
  3. DDR1

Graphics Interface:

  1. VGA
  2. HDMI
  3. MIPI
  4. GPU

Motivation

Feature

Usage

License

All of the TreeCore IP codes are release under the GPL-3.0 License.

Acknowledgement

  1. Free Books, Why Not?
  2. IP Cores Design from Specifications to Production
  3. Open Hardware Verification
  4. apb_timer

Reference