From a03fcee07c789328fa6c1304566e4b1e2ec2e67b Mon Sep 17 00:00:00 2001
From: David CARLIER <devnexen@gmail.com>
Date: Tue, 25 Jul 2023 20:41:45 +0100
Subject: [PATCH] risc-v aal tick implementation proposal.

---
 src/snmalloc/aal/aal_riscv.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/snmalloc/aal/aal_riscv.h b/src/snmalloc/aal/aal_riscv.h
index 2d2f7a4f1..e80660786 100644
--- a/src/snmalloc/aal/aal_riscv.h
+++ b/src/snmalloc/aal/aal_riscv.h
@@ -48,6 +48,26 @@ namespace snmalloc
        * microarchitecture.
        */
     }
+
+    static inline uint64_t tick() noexcept
+    {
+      uint64_t t;
+#if defined(SNMALLOC_VA_BITS_64)
+      __asm__ volatile("rdcycle %0" : "=r"(t));
+#else
+      uint32_t high, low, nhigh;
+      __asm__ volatile(
+        "jmp%=:"
+        "rdcycleh %0\n"
+        "rdcycle %1\n"
+        "rdcycleh %2\n"
+        "bne %0, %2, jmp%="
+        : "=r"(high), "=r"(low), "=r"(nhigh));
+
+      t = (static_cast<uint64_t>(high) << 32) | low;
+#endif
+      return t;
+    }
   };
 
   using AAL_Arch = AAL_RISCV;