SAMV71: insert extra delay between bytes for SPI in Minimig FDC

mist-devel · May 18, 2024 · af4993a · af4993a
1 parent 936c5f1
commit af4993a
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Showing 4 changed files with 16 additions and 7 deletions.
diff --git a/fdd.c b/fdd.c
@@ -195,7 +195,7 @@ void ReadTrack(adfTYPE *drive)
     }
     fdd_debugf("sector: %d\r", sector);
 
-    EnableFpga();
+    EnableFpgaMinimig();
     status   = SPI(0); // read request signal
     track    = SPI(0); // track number (cylinder & head)
     dsksync  = (SPI(0)) << 8; // disk sync high byte
@@ -211,7 +211,7 @@ void ReadTrack(adfTYPE *drive)
     {
         FileReadBlock(&drive->file, sector_buffer);
 
-        EnableFpga();
+        EnableFpgaMinimig();
 
         // check if FPGA is still asking for data
         status   = SPI(0); // read request signal
@@ -286,7 +286,7 @@ unsigned char FindSync(adfTYPE *drive)
 
     while (1)
     {
-        EnableFpga();
+        EnableFpgaMinimig();
         c1 = SPI(0); // write request signal
         c2 = SPI(0); // track number (cylinder & head)
         if (!(c1 & CMD_WRTRK)) {
@@ -335,7 +335,7 @@ unsigned char GetHeader(unsigned char *pTrack, unsigned char *pSector)
     Error = 0;
     while (1)
     {
-        EnableFpga();
+        EnableFpgaMinimig();
         c1 = SPI(0); // write request signal
         c2 = SPI(0); // track number (cylinder & head)
         if (!(c1 & CMD_WRTRK)) {
@@ -482,7 +482,7 @@ unsigned char GetData(void)
     Error = 0;
     while (1)
     {
-        EnableFpga();
+        EnableFpgaMinimig();
         c1 = SPI(0); // write request signal
         c2 = SPI(0); // track number (cylinder & head)
         if (!(c1 & CMD_WRTRK)) {
@@ -641,7 +641,7 @@ void WriteTrack(adfTYPE *drive)
 
 void UpdateDriveStatus(void)
 {
-    EnableFpga();
+    EnableFpgaMinimig();
     SPI(0x10);
     SPI(df[0].status | (df[1].status << 1) | (df[2].status << 2) | (df[3].status << 3));
     DisableFpga();

diff --git a/hw/AT91SAM/spi.h b/hw/AT91SAM/spi.h
@@ -17,6 +17,7 @@ unsigned char spi_get_speed();
 void spi_set_speed(unsigned char speed);
 
 /* chip select functions */
+#define EnableFpgaMinimig EnableFpga
 void EnableFpga(void);
 void DisableFpga(void);
 void EnableOsd(void);

diff --git a/hw/ATSAMV71/spi.c b/hw/ATSAMV71/spi.c
@@ -35,7 +35,6 @@ void spi_init()
     SPI0->SPI_CSR[1] = SPI_CSR_CPOL | SPI_CSR_SCBR(SPI_SDC_CLK_VALUE) | SPI_CSR_DLYBCT(0) | SPI_CSR_CSAAT | SPI_CSR_DLYBS(15); // USB
     SPI0->SPI_CSR[2] = SPI_CSR_CPOL | SPI_CSR_SCBR(SPI_SDC_CLK_VALUE) | SPI_CSR_DLYBCT(0) | SPI_CSR_CSAAT | SPI_CSR_DLYBS(10); // CONF_DATA0
     SPI0->SPI_CSR[3] = SPI_CSR_CPOL | SPI_CSR_SCBR(SPI_SDC_CLK_VALUE) | SPI_CSR_DLYBCT(0) | SPI_CSR_CSAAT | SPI_CSR_DLYBS(10); // SS2
-
 }
 
 void spi_wait4xfer_end()
@@ -45,6 +44,14 @@ void spi_wait4xfer_end()
 
 void EnableFpga()
 {
+    SPI0->SPI_CSR[3] = SPI_CSR_CPOL | SPI_CSR_SCBR(SPI_SDC_CLK_VALUE) | SPI_CSR_DLYBCT(0) | SPI_CSR_CSAAT | SPI_CSR_DLYBS(10); // SS2
+    SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCS(0x7); // NPCS3
+    SPI0->SPI_CR = SPI_CR_SPIEN;
+}
+
+void EnableFpgaMinimig()
+{
+    SPI0->SPI_CSR[3] = SPI_CSR_CPOL | SPI_CSR_SCBR(SPI_SDC_CLK_VALUE) | SPI_CSR_DLYBCT(2) | SPI_CSR_CSAAT | SPI_CSR_DLYBS(10); // SS2
     SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PCS(0x7); // NPCS3
     SPI0->SPI_CR = SPI_CR_SPIEN;
 }

diff --git a/hw/ATSAMV71/spi.h b/hw/ATSAMV71/spi.h
@@ -34,6 +34,7 @@ void spi_set_speed(unsigned char speed);
 
 /* chip select functions */
 void EnableFpga(void);
+void EnableFpgaMinimig(void);
 void DisableFpga(void);
 void EnableOsd(void);
 void DisableOsd(void);