Supermodel1 replacement board + MISE + MIRE diagnostics #17
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Hi! This sounds like an interesting project. You’re welcome to use this code and I’d be interested in helping adapt it for your project. Looks like all 3 of us are in the Portland area. Cool! I’m currently out of town until the 14th, and I know Adrian is under the weather. Let’s figure out the most effective means of communication. How far along is your project? Cheers, |
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Excellent! Well, if it matters, I'm one of the owners of Ground Kontrol in downtown and live in Tigard, and am a huge retrocomputing nerd and a fan of Adrian's channel. ;-) The CPLD for video has been completed - both VGA and composite out. CPLD For decode and everything else is being worked on now. We're likely to order dev boards by the end of the week. Next steps for me is putting an emulator together for it (with all our hardware extensions), so... maybe a couple of weeks until we're powering on? I definitely have work to do! Spec-wise, it's essentially this: 512K SRAM (16K pages) We considered doing an expansion interface, but MISE kinda has that all taken care of. I have both a MIRE and a MISE, too. |
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Just got done with the proto board. This doesn't include the video circuitry (that's next) and it's not TRS-80 form factor - yet. We'll do that in the final design.
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(if you'd like details, ask) - so I'm asking :-) Will this have the standard 40 pin expansion bus, or is everything totally self contained? I'd like to watch this develop - where is the project page hosted at? Will it have cassette input/output? |
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It's a full size replacement board for the model 1, including the 40 pin expansion bus. It will have a cassette input/output. There isn't a web page for the project yet. |
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Yeah sounds good just email me and I can add David. We're not precious about the code -- so we could merge the changes back into the main brance. Sounds like an additional version would be needed to support these extra features. You thinking of just including it right into the system ROM so a user could chose to run diagnostics as needed? |
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Can do! Yes, the idea was to have the system be able to boot any of the level II ROM versions, level I, diagnostics, or our yet-to-be-decided custom ROM for the extended features. I'll do my best to analyze how the existing code works and do my best to cooperate with the existing architecture. I realize that the MIRE and MISE diagnostics are definitely extras, so I'll keep them segmented as much as possible, and that'll give us the flexibility we need to conditionally include them. |
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I’d be happy to go over how the existing code works. It’s definitely unconventional, but that shouldn’t keep you from using conventional z80 code elsewhere. It ended up that way as a way to write non-trivial code in an environment where we did not yet trust any RAM or VRAM.
I’m not a Z80 expert. This was my first Z80 project. But I’d be interested in helping out if possible.
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David Giller
… On Aug 10, 2023, at 3:41 PM, neilbradley2084 ***@***.***> wrote:
Can do! Yes, the idea was to have the system be able to boot any of the level II ROM versions, level I, diagnostics, or our yet-to-be-decided custom ROM for the extended features. I'll do my best to analyze how the existing code works and do my best to cooperate with the existing architecture. I realize that the MIRE and MISE diagnostics are definitely extras, so I'll keep them segmented as much as possible, and that'll give us the flexibility we need to conditionally include them.
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Sounds great! I actually read your theory of operation and it does make a lot of sense. I've used several tricks you've used when doing BIOS development, back in the day when you had to run for a while before RAM got initialized and you couldn't use on-chip cache as temp RAM. It makes Ultimately we'll want to detect the MISE/MIRE/SuperModel1 automatically and there are programmatic ways to detect their presence. If you have specific guidance on where I should look to adding said tests that'd be appreciated, or basically any hints on where stuff is or where it should be added to lessen the amount of work to include in the main tree. Ultimately I think MISE/MIRE should just have their own modules for testing what's on each device, but for the SuperModel1, it might make sense for that to be part of the mainline test. |
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For those interested, here's the updated/routed board:
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Very nice looking! Is there a specific list of features it will have? |
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So far I've just been copying this list around: 512K SRAM (16K pages) Yes, all characters are programmable, so lower case and true descenders, including a memory mapped graphics (unlike the Grafyx) mode and 80x25. It has 512K of SRAM (no more dynamic!) in the keyboard so no need for memory in the EI (also, it being slow RAM wouldn't really matter since the TRS-80 didn't push it anywhere near that hard). The idea with the 512K is so you can page in 16K chunks of RAM (or flash). The idea also is to have multiple images in the flash so you can boot model 1 level 1, model 1 level II, built-in diagnostics, or whatever else we figure we'll put in it. |
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How do you plan to get ROM images loaded? What’s the plan for page mapping of ROM/RAM (in terms of how software/firmware will swap pages and what combinations of ROM/RAM paging will be possible), and for selecting the ROM to boot from? If the memory map will need to be Model I compatible, and for booting an actual Model I ROM, I assume you’ll need to be able to map in a 2K page of ROM. In that case, the diagnostics should probably be a separate optional ROM or part of a larger mappable enhanced-mode ROM that gets mapped out when running Model I/III software. Any plans to support Model 4 software? If the peripherals can alternately be memory (for Model I/III software) or I/O mapped, that might be not be far off from Model 4 compatibility? |
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Our existing plan is to have 4 bank switch registers, each for 16K of available address space. Something like this: I/O ports 0x70-0x73: 0x70=Page 0 (0-16K), 0x71=Page 1 (16K-32K), etc... Bits 0-5 - 16K Page within SRAM or flash (this is A Mapping peripherals like video, FDD, keyboard is separately controllable so you can map it in or out of the lowest region. Ideally we want to have an alternate method of access to FDD, keyboard (as I/O driven instead of memory mapped) so things like CP/M can run unrestricted. Upon initial boot, the lowest part of flash will be mapped at 0. I had in mind to include all flash images into the flash, and reserve a 16K page for a boot loader/selector. Some sort of a startup sequence, like pressing and holding 1-6 on the keyboard while turning it on or resetting it to select which image you want to boot, or a boot loader menu that allows you to change it, but boots by default if no one touches it for a few seconds. Once the correct image is selected, code would just map it down to 0, disable interrupts, and jump to 0, so the hardware itself wouldn't be choosing the image to boot. The idea would be for it to remember which image to boot from in a nonvolatile fashion. Before any of the other ROMs operate unrestricted, the code will need to load up the TRS-80 character set into the video controller, too, so there will be some bootstrapping code required regardless. There is a read protect there, too and there's a very specific reason why you can lock RAM regions. The ROM basic does do some destructive operations to itself - shifts on memory locations in ROM. When in ROM, the write gets completely ignored, but if it were RAM, it would be modified. So now anyone can map RAM into the lowest region, copy the ROM image down to RAM, then set it read only and voila - instant modified ROM. I had my eye on the model 4 software. What I've come away with is we'd be required to use the CRTC to get 80 column mode (which we don't want to do, given our video subsystem is considerably better), the HDD controller is different, and the bank switching scheme is just... well, weird. The short of it is I didn't see a nice/easy way to deal with all of the model 4 specific oddities, but if you have a different opinion or specific guidance or ideas on how to make everything more compatible, I'm all ears! |
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Haha the M4 banking is a little weird. I think I remember seeing it write to ROM space in the parts of the M4 ROM I disassembled… I think it does that when loading the Model III compatibility mode “ROM” from disk into the RAM under the ROM when it’s mapped. Come to think about it, given that the M4 can emulate a M3, it might not be too hard to at least emulate a floppy-based M4. As far as the CRTC is concerned I would think you would only need to emulate the control registers, and you might need to do that anyway. But that’s just idle speculation… you’ve done a lot of work and I’m sure you’ve looked at it. I’m really happy the project will be open source. We will all be able to learn from your work. |
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Hey, don't give me too much credit! I'm certainly just getting started and am all ears if someone can come up with a better way, or a "more compatible" way. Additionally, the CPLD has a lot of marcocells left over, so a lot is still possible even if we lock everything down. The control registers in the CRTC aren't necessary for the 80x25 and graphics modes we're doing, but it's possible that all the code does currently is write to those registers, which we can handily ignore. But we're learning on this, too. I just started to piece together an emulator. Jeff managed to get the hardware CPLD generating characters last night in VGA mode.
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For those interested, there's a Discord for the Supermodel-1: https://discord.com/channels/458077089493680160/1140065692960432128 |
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I’d love to join the discord, unfortunately the invite links will expire after one day. |
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Quick update... I did manage to get the emulator going, initial boards have been ordered as have parts. Exciting stuff!
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And to get things on topic, the diagnostic ROM now runs unmodified! I had to implement several undocumented Z80 instructions...
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Fixed the video:
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Got the boot loader all done as well as the emulator to go along with it. |
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A bit of an update from Jeff (HW designer) and me.... A small update on our supermodel1 project. The first set of PCBs for the prototype are here and working great, and the video controller is also working with both NTSC and VGA, and no flicker or noise of any kind during CPU access even with the CPU at 16MHz. CPU speed is software controllable from 1Mhz to 16Mhz.
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A bit of an update for everyone. We're going to include a microSD card so we'll emulate full floppy and hard disks, including the ability to format disks and (hopefully) have an operating system image we can image a disk. |
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And yet more of an update - we are finally doing board layout for the final form factor:
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I'm creating a Model I replacement board (if you'd like details, ask), and I'd like to include this diagnostic ROM in the image itself. Our project is open source GPLv2 so it should be compatible with the licensing, here.
In addition to permission to use, I'd also like to extend the diagnostics to include MISE and MIRE diagnostics, as well as our board's additional features (512K flash, 512K RAM, full graphics, programmable characters, etc...). All can be auto-detected, though I suspect with the diagnostic extensions it would no longer fit in a 2K ROM.
I'd rather cooperate with this project and am looking for guidance on engagement on how or what you'd like me to do, or even if you're interested at all.
FYI, As with Adrian, I'm in the Portland area, too.
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