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Fiscarelli
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@@ -56,6 +56,9 @@ BARE_TEST_LIST = \ | |
| ddr3 \ | ||
| cacheCoherence \ | ||
| idcache_smc \ | ||
| miscTests \ | ||
| lrscOps \ | ||
| atomicOps \ | ||
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| #//************************************************************************ | ||
| #// Copyright (C) 2020 Massachusetts Institute of Technology | ||
| #// SPDX short identifier: BSD-2-Clause | ||
| #// | ||
| #// File Name: | ||
| #// Program: Common Evaluation Platform (CEP) | ||
| #// Description: | ||
| #// Notes: | ||
| #// | ||
| #//************************************************************************ | ||
| # | ||
| # | ||
| # | ||
| COSIM_NAME = $(shell cd ../..; basename `pwd`) | ||
| DUT_TOP_DIR = $(shell cd ../../..; pwd | ./${COSIM_NAME}/bin/strip_net.pl ) | ||
| BLD_DIR = $(shell cd ..; pwd | ../bin/strip_net.pl ) | ||
| TEST_SUITE = $(shell basename ${BLD_DIR}) | ||
| TEST_DIR = $(shell cd .; pwd | ../../bin/strip_net.pl ) | ||
| TEST_NAME = $(shell basename `pwd`) | ||
| SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME} | ||
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| # | ||
| # Top target!!! | ||
| # | ||
| all: .vrun_flag riscv_wrapper.elf | ||
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| # | ||
| # override anything here before calling the common file | ||
| # | ||
| include ${BLD_DIR}/common.make | ||
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| //************************************************************************ | ||
| // Copyright (C) 2020 Massachusetts Institute of Technology | ||
| // SPDX short identifier: BSD-2-Clause | ||
| // | ||
| // File Name: | ||
| // Program: Common Evaluation Platform (CEP) | ||
| // Description: | ||
| // Notes: | ||
| // | ||
| //************************************************************************ | ||
| #include <unistd.h> | ||
| #include "v2c_cmds.h" | ||
| #include "access.h" | ||
| #include "c_dispatch.h" | ||
| #include "c_module.h" | ||
| #include "cep_apis.h" | ||
| #include "cep_adrMap.h" | ||
| #include "simPio.h" | ||
| /* | ||
| * main | ||
| */ | ||
| int main(int argc, char *argv[]) | ||
| { | ||
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| /* ===================================== */ | ||
| /* SETUP SECTION FOR SIMULATION */ | ||
| /* ===================================== */ | ||
| unsigned long seed; | ||
| sscanf(argv[1],"0x%x",&seed); | ||
| printf("Seed = 0x%x\n",seed); | ||
| int errCnt = 0; | ||
| int verbose = 0x1f; | ||
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| /* ===================================== */ | ||
| /* spawn all the paralle threads */ | ||
| /* ===================================== */ | ||
| int activeSlot=0; // only 1 board | ||
| // | ||
| // ============================ | ||
| // fork all the tests here | ||
| // ============================ | ||
| // | ||
| shPthread thr; | ||
| // | ||
| // max number of cores not include the system thread | ||
| // | ||
| int maxHost = MAX_CORES; // number of cores/threads | ||
| // | ||
| // each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..) | ||
| // | ||
| long unsigned int mask = 1 << (seed & 0x3); | ||
| // | ||
| // Set the active CPU mask before spawn the threads... | ||
| // | ||
| thr.SetActiveMask(mask); | ||
| // | ||
| // c_module is the threead to run | ||
| // | ||
| for (int i=0;i<maxHost;i++) { | ||
| if ((long unsigned int)(1 << i) & mask) { | ||
| thr.ForkAThread(activeSlot,i,verbose, seed * (1+i), c_module); | ||
| } | ||
| } | ||
| // | ||
| // lastly: Added system thread always | ||
| // | ||
| thr.AddSysThread(SYSTEM_SLOT_ID,SYSTEM_CPU_ID); | ||
| // | ||
| // ============================ | ||
| // Turn on the wave here | ||
| // ============================ | ||
| // | ||
| int cycle2start=0; | ||
| int cycle2capture=-1; // til end | ||
| int wave_enable=1; | ||
| #ifndef NOWAVE | ||
| dump_wave(cycle2start, cycle2capture, wave_enable); | ||
| #endif | ||
| // | ||
| // Enable main memory logging | ||
| // | ||
| //DUT_WRITE_DVT(DVTF_ENABLE_MAIN_MEM_LOGGING, DVTF_ENABLE_MAIN_MEM_LOGGING, 1); | ||
| // | ||
| // wait for calibration?? | ||
| // | ||
| #if 1 | ||
| //int calibDone = calibrate_ddr3(50); | ||
| int backdoor_on = 1; | ||
| int verify = 0; | ||
| int srcOffset = 0x1000; | ||
| int destOffset = 0; | ||
| errCnt += load_mainMemory((char *)"./riscv_wrapper.elf", ddr3_base_adr,srcOffset, destOffset, backdoor_on, verify); | ||
| #endif | ||
| DUT_WRITE_DVT(DVTF_DISABLE_MAIN_MEM_LOGGING, DVTF_DISABLE_MAIN_MEM_LOGGING, 1); | ||
| // | ||
| // log the write only | ||
| DUT_WRITE_DVT(DVTF_ENABLE_MAIN_MEMWR_LOGGING, DVTF_ENABLE_MAIN_MEMWR_LOGGING, 1); | ||
| // | ||
| // ============================ | ||
| // wait until all the threads are done | ||
| // ============================ | ||
| // | ||
| int Done = 0; | ||
| while (!Done) { | ||
| Done = thr.AllThreadDone(); | ||
| sleep(2); | ||
| } | ||
| /* ===================================== */ | ||
| /* END-OF-TEST CHECKING */ | ||
| /* ===================================== */ | ||
| errCnt += thr.GetErrorCount(); | ||
| if (errCnt != 0) { | ||
| LOGE("======== TEST FAIL ========== %x\n",errCnt); | ||
| } else { | ||
| LOGI("%s ======== TEST PASS ========== \n",__FUNCTION__); | ||
| } | ||
| // | ||
| // shutdown HW side | ||
| // dont call this DUT_SetInActiveStatus is used | ||
| thr.Shutdown(); | ||
| return(errCnt); | ||
| } |
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,23 @@ | ||
| //************************************************************************ | ||
| // Copyright (C) 2020 Massachusetts Institute of Technology | ||
| // SPDX short identifier: BSD-2-Clause | ||
| // | ||
| // File Name: | ||
| // Program: Common Evaluation Platform (CEP) | ||
| // Description: | ||
| // Notes: | ||
| // | ||
| //************************************************************************ | ||
| #ifndef __C_DISPATCH_H | ||
| #define __C_DISPATCH_H | ||
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| // Dispatch setup | ||
| #ifdef LONGTEST | ||
| #define MAX_LOOP 50 | ||
| #else | ||
| #define MAX_LOOP 5 | ||
| #endif | ||
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| #endif | ||
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