diff --git a/.DS_Store b/.DS_Store deleted file mode 100644 index 822c417..0000000 Binary files a/.DS_Store and /dev/null differ diff --git a/README.md b/README.md index 681aa1b..d2c2d3f 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,7 @@

- +

Copyright 2021 Massachusetts Institute of Technology @@ -17,11 +17,9 @@

-The Common Evaluation Platform (CEP) is intended as a surrogate System on a Chip (SoC) that provides users an open-source evaluation platform for the evaluation of custom tools and techniques. An extensive verification environment is provided to ensure the underlying functionality is maintained even after modification. +The Common Evaluation Platform (CEP) is an Open Source Hardware (OSH) System on a Chip (SoC). It has been developed to support the test and evluation of custom tools and techniques. An extensive verification environment is provided to ensure the underlying functionality is maintained even after modification. -The Logic Locking Key Interface (LLKI) has been provided as a representative means of distributing key / configuration material to LLKI-enabled cores. - -For CEP v3.1+, the full LLKI has been added. This includes the Surrogate Root of Trust (SRoT) and mock Technique Specific Shims (TSS) for all accelerator cores. +The Lincoln Laboratory Key Interface (LLKI) has been provided as a representative means of distributing key / configuration material to LLKI-enabled cores. ### Please check the [Release Notes](./RELEASE_NOTES.md) to understand what has changed and a list of known issues. @@ -206,7 +204,7 @@ See ./cosim/drivers/diag/cepMacroMix.cc for example code. As one might be aware: the endianess usage is not consistent thru out the design, expesially where Chisel wrappers are used to connect to various HW cores. For some cores, little endian is used for loading keys/plain text but big-endian is used to produce cipher text as output. This creates confusion and inconsistent as one might try to understand/follow SW driver for these cores. Also, please note, RISCV is little endian. -As of release CEP v2.4 and later, unless otherwise specify, big endian is used thru out the design to match key/plain/ciphertext network order. +Unless otherwise specified, big endian is used thru out the design to match key/plain/ciphertext network order. This makes it consistent and easier to debug when key/plain text are printed to match against registers. @@ -311,11 +309,15 @@ make install append If subsequent changes are made to the source code in /cosim/drivers/linux, simply copy the changes over to the Linux build by running `make install`. -Next, one needs to build linux. First, change to the `/software/freedom-u-sdk` directory. Ensure that the linux variant of the RISC-V toolset is used by executing `unset RISCV` -For Ubuntu 18.04 LTS, the default PERL installation may cause a conflict with the build process. You may need to execute `unset PERL_MM_OPT` if set. +Next, one needs to build linux. First, change to the `/software/freedom-u-sdk` directory. + +A few cautionary notes: +- Ensure that the linux variant of the RISC-V toolset is used by executing `unset RISCV` +- For Ubuntu 18.04 LTS, the default PERL installation may cause a conflict with the build process. You may need to execute `unset PERL_MM_OPT` if set. +- If you patched the LIBRARY_PATH environment variable to allow for compilation of the Xilinx simulation libraries, this may cause the linux build to fail -Begin the build by running `make -jN BOARD=vc707devkit_nopci all` where N is the numbers of cores you can dedicate to the build. Ensure that you have NOT sourced the Xilinx Vivado environment setup script before running this step. +Begin the build by running `make -jN BOARD=vc707devkit_nopci all` where N is the numbers of cores you can dedicate to the build. Following the linux build, which can take 30 - 60 minutes, you will have a binary which you can load onto an SD card. @@ -342,7 +344,7 @@ You should see the following logo/text appear: ./+++++++++++oo+++: +oo++o++++o+o+oo+oo.- `s+++s`- .--:---:-:-::-::` -::::::::::::::::::. :::::. - Common Evaluation Platform v3.40 + Common Evaluation Platform v3.41 Copyright 2021 Massachusetts Institute of Technology Built upon the SiFive Freedom U500 Platform using @@ -365,7 +367,7 @@ At the command prompt, you can run the CEP diagnostics by commanding `cep_diag`. A partial output should be similar to: ```sh -*** CEP SW=0x3.40 HW VERSION = v3.40 was built on Aug 5 2021 08:36:41 *** +*** CEP SW=0x3.41 HW VERSION = v3.41 was built on Aug 5 2021 08:36:41 *** CEP FPGA Physical: cepReg/ddr3/other/sys -> Virtual=0x700000000, 0x800000000, 0x600000000, 0xc00000000 ScratchPad=0x2000400000 gSkipInit=0/0 @@ -428,7 +430,7 @@ The following cores have been integrated into the "standard" CEP build: - Infinite Impulse Response - GPS code generator -Beginning with the v2.4 release, the following "generated" cores have been added to the repository, but are currently not integrated into the CEP build. +The following "generated" cores have been added to the repository, but are currently not integrated into the CEP build. - A(EE)ES-WB : Advanced Egregiously Extended Encryption Standard - Whitebox Edition [./hdl_cores/aeees/README.md](./hdl_cores/aeees/README.md). - (RI)IIR : Randomly Indeterminate Infinite Impulse Response [./hdl_cores/auto-fir/README.md](./hdl_cores/auto-fir/README.md). - SHA(AA) : Secure Hash Algorithm Arbitrarily Augment [./hdl_cores/shaaa/README.md](./hdl_cores/shaaa/README.md). diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md index 8f88153..a1db531 100644 --- a/RELEASE_NOTES.md +++ b/RELEASE_NOTES.md @@ -144,4 +144,11 @@ v3.4 - (6 August 2021) * Scratchpad RAM changed to blackbox implementation to facilitate ASIC development * OpenSSL replaced by Cryptopp for crypto-related tests (cosim + linux) +v3.41 - (10 September 2021) +* CEP Configuration nows includes 4xGPS and 4xSHA-256 cores +* Integrated configurable co-simulation environment (provide a co-sim that can more easily adapt to CEP architecture changes) +* Known Issues: + - Some idft test vectors fail under QuestaSim (xcellium regression ran successfully) + - Multithreaded test (#23) non-functional under linux + #### Return to the root CEP [README](./README.md) \ No newline at end of file diff --git a/cosim/.DS_Store b/cosim/.DS_Store index 0dbd832..5be3fbf 100644 Binary files a/cosim/.DS_Store and b/cosim/.DS_Store differ diff --git a/cosim/.gitignore b/cosim/.gitignore index b53e2f5..e3f80a6 100644 --- a/cosim/.gitignore +++ b/cosim/.gitignore @@ -1,5 +1,6 @@ .Xil/ xil_lib/ +.xil_lib/ .cxl.ip/ .cxl* *.log* @@ -8,6 +9,7 @@ xil_lib/ *.bin **/*.o **/*.obj +**/*.bobj **/*.hex **/*.a **/*.KEY @@ -16,6 +18,7 @@ modelsim.ini* **/c_dispatch **/testHistory.txt vsim.do +.c_children.mk **/transcript **/*.wlf **/*.dump @@ -25,4 +28,5 @@ dvt/behav_models/ddr3.v include/cep_adrMap.h include/v2c_cmds.h lib/dll/libvpp.so - +lib/libvpp.so +lib/.buildLibs diff --git a/cosim/README.md b/cosim/README.md index b295b77..4418881 100644 --- a/cosim/README.md +++ b/cosim/README.md @@ -6,7 +6,7 @@ # README for CEP co-simulation environment -This SW/HW co-simulation evironment has been developed to support "chip-level" simulation of the CEP. +This SW/HW co-simulation evironment has been developed to support "chip-level" simulation of the CEP. Several environments are supported: @@ -25,19 +25,19 @@ Several environments are supported: * SW and HW are de-coupled such that mistakes that are found in the test/driver (SW side) during development process can be quickly corrected and rerun without having to rebuild the HW. Sometimes, it might takes minutes (or even hours for big ASIC) just to rebuild the HW if test and DUT (Device Under Test) are tightly coupled -* Makefile is setup to support vendor independent designs such that same design can be used to target FPGA vendor as Xilinx or TSMC for ASIC, for example. +* Makefile is setup to support vendor independent designs such that the same design can be used to target an FPGA vendor such as Xilinx or TSMC for ASIC. * To take advantage of multi-core machines, support up to 4K+ threads where all threads can run in parallel and target different HW sections. For example: one core can target the AES block while another core targets the FIR block, etc... * Mailboxes are setup to support in between thread communication for synchronization, handshaking, etc... -* All are *makefile* driven with scripts to support auto-dependencies generation. Which means anything changes in either HW files or SW files: incremental builds will be called to save time. This is a must in order to support parallel batching. +* All are *makefile* driven with scripts to support auto-dependencies generation. Which means when anything changes in either HW files or SW files, incremental builds will be called to save time. This is a must in order to support parallel batching. * Provide 100% visibility to everything in the test bench via wave capturing. From the SW (test) side, any signal in HW can be observed and forced (for negative testing) or to be used to synchronize events (wait for something before sending packet, etc...) * Same setup can be used for any design. Therefore, it takes only hour to set up new test bench for new design and let designer/verification engineers start writing tests right away. -* Most of the tests can even be re-used across multiple projects such as memory test, register tests, packet generator and checker. They are written as template where only simple read/write methods need to be overload. +* Most of the tests can even be re-used across multiple projects such as memory test, register tests, packet generator and checker. They are written as templates where only simple read/write methods need to be overload. * Open source codebase @@ -66,7 +66,19 @@ For CEP, the path to tools required are as listed below (see **common.make**) SIMULATOR_PATH ?= /opt/questa-2019.1/questasim/bin RISCV ?= /opt/riscv -**NOTE**: If they are not matched your setup, dont need to edit the common.make file, use enviroment variables to override as such (assuming bash shell is used). +As of release 3.2 or later, Cadence tool set is also supported, all setup related to Cadence tool set can be found in `cadence.make` + +If you decide to use Cadence's xcelium for simulation, modify cadence.make or override with environment variables to match the below variables: + +``` +export VMGR_VERSION ?= VMANAGERAGILE20.06.001 +export XCELIUM_VERSION ?= XCELIUMAGILE20.09.001 + +export VMGR_PATH ?= /brewhouse/cad4/x86_64/Cadence/${VMGR_VERSION} +export XCELIUM_INSTALL ?= /brewhouse/cad4/x86_64/Cadence/${XCELIUM_VERSION} +``` + +**NOTE**: If they are not matched to your setup, you dont need to edit the common.make file. Instead, use enviroment variables to override as such (assuming bash shell is used). ``` export VIVADO_PATH= export SIMULATOR_PATH= @@ -116,7 +128,7 @@ You should see something like this under *cosim* directory: ## Compiling the Xilinx Simulation Libraries ## -**NOTE**: xil_lib is the generated library packages created via vivado 's compile_simlib command. Not all Vivado / Modelsim version combinations yield the desired result. See the following notes: +**NOTE**: xil_lib is the generated library packages created via vivado's compile_simlib command. Not all Vivado / Modelsim version combinations yield the desired result. See the following notes: - When Vivado 2019.1 and Questa 2019.1 is selected ,the compilation will stop and not generate the appropriate modelsim.ini file, which is required by the co-simulation environemt. - When Vivado 2018.3 and Questa 2019.1 (or Quest 10.7c) is selected, the compilation will return with an error in the qdma_v3_0_0 library. This library is not required for CEP simulation and thus the error can be safely ignored. - When Vivado 2018.3 and Question 10.6c is selected, the compilation will complete without error. However, it is recommended that Questa 2019.1 be used in order to take advantage of optimizations and bug fixes. diff --git a/cosim/bareMetalTests/.DS_Store b/cosim/bareMetalTests/.DS_Store index 8f91a1f..000f97c 100644 Binary files a/cosim/bareMetalTests/.DS_Store and b/cosim/bareMetalTests/.DS_Store differ diff --git a/cosim/bfmTests/Makefile b/cosim/bfmTests/Makefile index eea5a61..6cf81b6 100644 --- a/cosim/bfmTests/Makefile +++ b/cosim/bfmTests/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/ddr3Test/Makefile b/cosim/bfmTests/ddr3Test/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/ddr3Test/Makefile +++ b/cosim/bfmTests/ddr3Test/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/fragmentors/cepFragmentorTest.cc b/cosim/bfmTests/fragmentors/cepFragmentorTest.cc index 009155f..c601a3c 100644 --- a/cosim/bfmTests/fragmentors/cepFragmentorTest.cc +++ b/cosim/bfmTests/fragmentors/cepFragmentorTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/fragmentors/cepFragmentorTest.h b/cosim/bfmTests/fragmentors/cepFragmentorTest.h index f0de8f3..d30421b 100644 --- a/cosim/bfmTests/fragmentors/cepFragmentorTest.h +++ b/cosim/bfmTests/fragmentors/cepFragmentorTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/lockTest/Makefile b/cosim/bfmTests/lockTest/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/lockTest/Makefile +++ b/cosim/bfmTests/lockTest/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/macroMix/Makefile b/cosim/bfmTests/macroMix/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/macroMix/Makefile +++ b/cosim/bfmTests/macroMix/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/macroMix/c_dispatch.cc b/cosim/bfmTests/macroMix/c_dispatch.cc index e42b9a9..1fd2019 100644 --- a/cosim/bfmTests/macroMix/c_dispatch.cc +++ b/cosim/bfmTests/macroMix/c_dispatch.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/macroMix/c_dispatch.h b/cosim/bfmTests/macroMix/c_dispatch.h index ee74fe2..7219034 100644 --- a/cosim/bfmTests/macroMix/c_dispatch.h +++ b/cosim/bfmTests/macroMix/c_dispatch.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/macroMix/c_module.cc b/cosim/bfmTests/macroMix/c_module.cc index e7477c4..c236b18 100644 --- a/cosim/bfmTests/macroMix/c_module.cc +++ b/cosim/bfmTests/macroMix/c_module.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -54,27 +54,30 @@ void *c_module(void *arg) { // ====================================== // Test starts here // ====================================== - // MUST - // wait until Calibration is done.. - //int calibDone = calibrate_ddr3(50); + // MUST wait until Calibration is done.. pio.RunClk(1000); - // + + int mask = seed; // seed is used as cpuActiveMask from c_dispatch - // Select which tests to run. Core indicies are defined in CEP.h - int mask = seed; // seed is used as cpuActiveMask from c_displatch - int cryptoMask = 0xFFFFFFFF; // all cores -// int cryptoMask = 0x00000001; // AES only -// int cryptoMask = 0x00000002; // MD5 only -// int cryptoMask = 0x00000004; // SHA256 only -// int cryptoMask = 0x00000008; // RSA only -// int cryptoMask = 0x00000010; // DES3 only -// int cryptoMask = 0x00000020; // DFT only -// int cryptoMask = 0x00000040; // IDFT only -// int cryptoMask = 0x00000080; // FIR only -// int cryptoMask = 0x00000100; // IIR only -// int cryptoMask = 0x00000200; // GPS only + int coreMask = 0xFFFFFFFF; // all cores +// int coreMask = 0x00000001; // AES +// int coreMask = 0x00000002; // MD5 +// int coreMask = 0x00000004; // SHA256.0 +// int coreMask = 0x00000008; // SHA256.1 +// int coreMask = 0x00000010; // SHA256.2 +// int coreMask = 0x00000020; // SHA256.3 +// int coreMask = 0x00000040; // RSA +// int coreMask = 0x00000080; // DES3 +// int coreMask = 0x00000100; // DFT +// int coreMask = 0x00000200; // IDFT +// int coreMask = 0x00000400; // FIR +// int coreMask = 0x00000800; // IIR +// int coreMask = 0x00001000; // GPS.0 +// int coreMask = 0x00002000; // GPS.1 +// int coreMask = 0x00004000; // GPS.2 +// int coreMask = 0x00008000; // GPS.3 - if (!errCnt) { errCnt = cepMacroMix_runTest(cpuId, mask, cryptoMask, seed, verbose); } + if (!errCnt) { errCnt = cepMacroMix_runTest(cpuId, mask, coreMask, seed, verbose); } // pio.RunClk(100); // diff --git a/cosim/bfmTests/macroMix/c_module.h b/cosim/bfmTests/macroMix/c_module.h index c4e93df..e3f9000 100644 --- a/cosim/bfmTests/macroMix/c_module.h +++ b/cosim/bfmTests/macroMix/c_module.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/memPreload/Makefile b/cosim/bfmTests/memPreload/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/memPreload/Makefile +++ b/cosim/bfmTests/memPreload/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/memPreload/c_dispatch.cc b/cosim/bfmTests/memPreload/c_dispatch.cc index 8d66dbb..5a2eab8 100644 --- a/cosim/bfmTests/memPreload/c_dispatch.cc +++ b/cosim/bfmTests/memPreload/c_dispatch.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/memPreload/c_dispatch.h b/cosim/bfmTests/memPreload/c_dispatch.h index ee74fe2..7219034 100644 --- a/cosim/bfmTests/memPreload/c_dispatch.h +++ b/cosim/bfmTests/memPreload/c_dispatch.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/memPreload/c_module.cc b/cosim/bfmTests/memPreload/c_module.cc index 10e385f..e372bb4 100644 --- a/cosim/bfmTests/memPreload/c_module.cc +++ b/cosim/bfmTests/memPreload/c_module.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/memPreload/c_module.h b/cosim/bfmTests/memPreload/c_module.h index c4e93df..e3f9000 100644 --- a/cosim/bfmTests/memPreload/c_module.h +++ b/cosim/bfmTests/memPreload/c_module.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/memPreload/riscv_wrapper.cc b/cosim/bfmTests/memPreload/riscv_wrapper.cc index 4390afa..67dc3df 100644 --- a/cosim/bfmTests/memPreload/riscv_wrapper.cc +++ b/cosim/bfmTests/memPreload/riscv_wrapper.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/multiLock/Makefile b/cosim/bfmTests/multiLock/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/multiLock/Makefile +++ b/cosim/bfmTests/multiLock/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/multiThread/Makefile b/cosim/bfmTests/multiThread/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/multiThread/Makefile +++ b/cosim/bfmTests/multiThread/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/multiThread/c_dispatch.cc b/cosim/bfmTests/multiThread/c_dispatch.cc index e42b9a9..1fd2019 100644 --- a/cosim/bfmTests/multiThread/c_dispatch.cc +++ b/cosim/bfmTests/multiThread/c_dispatch.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/multiThread/c_dispatch.h b/cosim/bfmTests/multiThread/c_dispatch.h index ee74fe2..7219034 100644 --- a/cosim/bfmTests/multiThread/c_dispatch.h +++ b/cosim/bfmTests/multiThread/c_dispatch.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/multiThread/c_module.cc b/cosim/bfmTests/multiThread/c_module.cc index c042314..953e75e 100644 --- a/cosim/bfmTests/multiThread/c_module.cc +++ b/cosim/bfmTests/multiThread/c_module.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -37,8 +37,6 @@ void *c_module(void *arg) { int restart = tParm->restart; int offset = GET_OFFSET(slotId,cpuId); GlobalShMemory.getSlotCpuId(offset,&slotId,&cpuId); - //printf("offset=%x seed=%x verbose=%x GlobalShMemory=%x\n",offset,seed, verbose,(unsigned long) &GlobalShMemory); - // notify I am Alive!!! shIpc *ptr = GlobalShMemory.getIpcPtr(offset); ptr->SetAliveStatus(); sleep(1); @@ -59,19 +57,18 @@ void *c_module(void *arg) { // wait until Calibration is done.. int calibDone = calibrate_ddr3(50); //pio.RunClk(1000); - // - int coreMask = seed; // seed is used as cpuActiveMask from c_displatch - int cryptoMask = ((1<<10)-1) & ~(1 << RSA_BASE_K); - // + + int cpuActiveMask = seed; // seed is used as cpuActiveMask from c_displatch + int maxTest = 10; int maxLoop = 2; uint64_t testLockBuf = 0x90000000; if (!errCnt) { - errCnt += cepMultiThread_setup(cpuId, testLockBuf, maxTest, coreMask, verbose) ; + errCnt += cepMultiThread_setup(cpuId, testLockBuf, maxTest, cpuActiveMask, verbose) ; } // LOGI(" errCnt=%d\n",errCnt); - if (!errCnt) { errCnt += cepMultiThread_runThr(cpuId, testLockBuf, cryptoMask, maxTest, maxLoop,seed, verbose); } + if (!errCnt) { errCnt += cepMultiThread_runThr(cpuId, testLockBuf, cpuActiveMask, maxTest, maxLoop,seed, verbose); } // // pio.RunClk(100); diff --git a/cosim/bfmTests/multiThread/c_module.h b/cosim/bfmTests/multiThread/c_module.h index c4e93df..e3f9000 100644 --- a/cosim/bfmTests/multiThread/c_module.h +++ b/cosim/bfmTests/multiThread/c_module.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/scratchpadTest/Makefile b/cosim/bfmTests/scratchpadTest/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/scratchpadTest/Makefile +++ b/cosim/bfmTests/scratchpadTest/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotBadKeys/.gitignore b/cosim/bfmTests/srotBadKeys/.gitignore new file mode 100644 index 0000000..0744632 --- /dev/null +++ b/cosim/bfmTests/srotBadKeys/.gitignore @@ -0,0 +1 @@ +BIO_OUT diff --git a/cosim/bfmTests/srotBadKeys/Makefile b/cosim/bfmTests/srotBadKeys/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/srotBadKeys/Makefile +++ b/cosim/bfmTests/srotBadKeys/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotBadKeys/c_dispatch.cc b/cosim/bfmTests/srotBadKeys/c_dispatch.cc index f4d4551..2d5feee 100644 --- a/cosim/bfmTests/srotBadKeys/c_dispatch.cc +++ b/cosim/bfmTests/srotBadKeys/c_dispatch.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotBadKeys/c_dispatch.h b/cosim/bfmTests/srotBadKeys/c_dispatch.h index ee74fe2..7219034 100644 --- a/cosim/bfmTests/srotBadKeys/c_dispatch.h +++ b/cosim/bfmTests/srotBadKeys/c_dispatch.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotBadKeys/c_module.cc b/cosim/bfmTests/srotBadKeys/c_module.cc index e2a46b8..14eaee0 100644 --- a/cosim/bfmTests/srotBadKeys/c_module.cc +++ b/cosim/bfmTests/srotBadKeys/c_module.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -54,13 +54,29 @@ void *c_module(void *arg) { // ====================================== // Test starts here // ====================================== - // MUST - // wait until Calibration is done.. - //int calibDone = calibrate_ddr3(50); + // MUST wait until Calibration is done.. pio.RunClk(1000); - // int mask = seed; // seed is used as cpuActiveMask from c_displatch - if (!errCnt) { errCnt = cepMacroMix_runBadKeysTest(cpuId, mask, seed, verbose); } + + int coreMask = 0xFFFFFFFF; // all cores +// int coreMask = 0x00000001; // AES +// int coreMask = 0x00000002; // MD5 +// int coreMask = 0x00000004; // SHA256.0 +// int coreMask = 0x00000008; // SHA256.1 +// int coreMask = 0x00000010; // SHA256.2 +// int coreMask = 0x00000020; // SHA256.3 +// int coreMask = 0x00000040; // RSA +// int coreMask = 0x00000080; // DES3 +// int coreMask = 0x00000100; // DFT +// int coreMask = 0x00000200; // IDFT +// int coreMask = 0x00000400; // FIR +// int coreMask = 0x00000800; // IIR +// int coreMask = 0x00001000; // GPS.0 +// int coreMask = 0x00002000; // GPS.1 +// int coreMask = 0x00004000; // GPS.2 +// int coreMask = 0x00008000; // GPS.3 + + if (!errCnt) { errCnt = cepMacroMix_runBadKeysTest(cpuId, mask, coreMask, seed, verbose); } // pio.RunClk(100); // diff --git a/cosim/bfmTests/srotBadKeys/c_module.h b/cosim/bfmTests/srotBadKeys/c_module.h index c4e93df..e3f9000 100644 --- a/cosim/bfmTests/srotBadKeys/c_module.h +++ b/cosim/bfmTests/srotBadKeys/c_module.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotErrorTest/Makefile b/cosim/bfmTests/srotErrorTest/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/srotErrorTest/Makefile +++ b/cosim/bfmTests/srotErrorTest/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotKeyTest/Makefile b/cosim/bfmTests/srotKeyTest/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/srotKeyTest/Makefile +++ b/cosim/bfmTests/srotKeyTest/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotKeyTest/c_dispatch.cc b/cosim/bfmTests/srotKeyTest/c_dispatch.cc index a362d90..0fc2ffa 100644 --- a/cosim/bfmTests/srotKeyTest/c_dispatch.cc +++ b/cosim/bfmTests/srotKeyTest/c_dispatch.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotKeyTest/c_dispatch.h b/cosim/bfmTests/srotKeyTest/c_dispatch.h index ee74fe2..7219034 100644 --- a/cosim/bfmTests/srotKeyTest/c_dispatch.h +++ b/cosim/bfmTests/srotKeyTest/c_dispatch.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotKeyTest/c_module.cc b/cosim/bfmTests/srotKeyTest/c_module.cc index adafb0d..ff9fbcb 100644 --- a/cosim/bfmTests/srotKeyTest/c_module.cc +++ b/cosim/bfmTests/srotKeyTest/c_module.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotKeyTest/c_module.h b/cosim/bfmTests/srotKeyTest/c_module.h index c4e93df..e3f9000 100644 --- a/cosim/bfmTests/srotKeyTest/c_module.h +++ b/cosim/bfmTests/srotKeyTest/c_module.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/bfmTests/srotMemTest/Makefile b/cosim/bfmTests/srotMemTest/Makefile index bf3e9c7..ae7fa91 100644 --- a/cosim/bfmTests/srotMemTest/Makefile +++ b/cosim/bfmTests/srotMemTest/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: #// Program: Common Evaluation Platform (CEP) diff --git a/cosim/bin/createPassFail.pl b/cosim/bin/createPassFail.pl index f440a61..bce0628 100755 --- a/cosim/bin/createPassFail.pl +++ b/cosim/bin/createPassFail.pl @@ -1,8 +1,9 @@ #!/usr/bin/perl #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology +#// SPDX License Identifier: BSD-2-Clause #// -#// File Name: insertLLKI.pl +#// File Name: createPassFail.pl #// Program: Common Evaluation Platform (CEP) #// Description: #// Notes: diff --git a/cosim/bin/mkDepend.pl b/cosim/bin/mkDepend.pl index 849c17c..5772951 100755 --- a/cosim/bin/mkDepend.pl +++ b/cosim/bin/mkDepend.pl @@ -1,8 +1,9 @@ #!/usr/bin/perl #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology +#// SPDX License Identifier: BSD-2-Clause #// -#// File Name: +#// File Name: mkDepend.pl #// Program: Common Evaluation Platform (CEP) #// Description: #// Notes: diff --git a/cosim/bin/strip_net.pl b/cosim/bin/strip_net.pl index 3ddcce7..98a9d49 100755 --- a/cosim/bin/strip_net.pl +++ b/cosim/bin/strip_net.pl @@ -1,8 +1,9 @@ #!/usr/bin/perl #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology +#// SPDX License Identifier: BSD-2-Clause #// -#// File Name: +#// File Name: strip_net.pl #// Program: Common Evaluation Platform (CEP) #// Description: #// Notes: diff --git a/cosim/bin/v2c.pl b/cosim/bin/v2c.pl index e85f6c1..26af4c7 100755 --- a/cosim/bin/v2c.pl +++ b/cosim/bin/v2c.pl @@ -1,8 +1,9 @@ #!/usr/bin/perl #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology +#// SPDX License Identifier: BSD-2-Clause #// -#// File Name: +#// File Name: v2c.pl #// Program: Common Evaluation Platform (CEP) #// Description: #// Notes: diff --git a/cosim/bin/vpp.pl b/cosim/bin/vpp.pl index 1013e43..140a85c 100755 --- a/cosim/bin/vpp.pl +++ b/cosim/bin/vpp.pl @@ -1,8 +1,9 @@ #!/usr/bin/perl #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology +#// SPDX License Identifier: BSD-2-Clause #// -#// File Name: +#// File Name: vpp.pl #// Program: Common Evaluation Platform (CEP) #// Description: #// Notes: diff --git a/cosim/drivers/.DS_Store b/cosim/drivers/.DS_Store index 085cc7c..ab37861 100644 Binary files a/cosim/drivers/.DS_Store and b/cosim/drivers/.DS_Store differ diff --git a/cosim/drivers/bare/bare_malloc.c b/cosim/drivers/bare/bare_malloc.c index 72aeac3..9e73e54 100644 --- a/cosim/drivers/bare/bare_malloc.c +++ b/cosim/drivers/bare/bare_malloc.c @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/bare/syscalls.c b/cosim/drivers/bare/syscalls.c index 81c6bf2..e4d3d21 100644 --- a/cosim/drivers/bare/syscalls.c +++ b/cosim/drivers/bare/syscalls.c @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/cep_tests/CEP.h b/cosim/drivers/cep_tests/CEP.h index 3910478..5ae8ecd 100644 --- a/cosim/drivers/cep_tests/CEP.h +++ b/cosim/drivers/cep_tests/CEP.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -10,15 +10,10 @@ //************************************************************************ +#ifndef cep_H +#define cep_H #include "cep_version.h" - // CEP Verion String -/* Tony D. 04/10/21 - these are auot-extracted from scala file in cep_version.h" above - const uint8_t CEP_MAJOR_VERSION = 0x03; - const uint8_t CEP_MINOR_VERSION = 0x20; -*/ - // General Constants const uint32_t BITS_PER_BYTE = 8; const uint32_t BYTES_PER_WORD = 8; // 64-bit word accesses for RISC-V @@ -27,50 +22,67 @@ // Maximum expected name size for the ipCoreData structure #define MAX_CONFIG_STRING_K 32 - - // Indexes used to select the desired core - // Also used by the LLKI to identify the core index - // that a key is destined for... must match - // the values in LLKI_CORE_INDEX_ARRAY in srot_wrapper.sv, - // which is passed down from DevKitsConfig.scala - #define AES_BASE_K 0 - #define MD5_BASE_K 1 - #define SHA256_BASE_K 2 - #define RSA_BASE_K 3 - #define DES3_BASE_K 4 - #define DFT_BASE_K 5 - #define IDFT_BASE_K 6 - #define FIR_BASE_K 7 - #define IIR_BASE_K 8 - #define GPS_BASE_K 9 - #define CEP_VERSION_REG_K 10 - #define SROT_BASE_K 11 - // Defines the total number of cores in the CEP - #define CEP_TOTAL_CORES 12 + // Enumerated type that is used by cepMacroMix to know which type of test + // to run on the selected core + typedef enum core_type_t { + AES_CORE, + MD5_CORE, + SHA256_CORE, + RSA_CORE, + DES3_CORE, + DFT_CORE, + IDFT_CORE, + FIR_CORE, + IIR_CORE, + GPS_CORE, + CEP_VERSION_CORE, + SROT_CORE + } core_type_t; // Structure defining the base address and status // of the CEP cores typedef struct cep_core_info_t { const char *name; + core_type_t type; uint32_t base_address; bool enabled; } cep_core_info_t; + // Defines the total number of cores in the CEP + #define CEP_TOTAL_CORES 18 + // Array containing the base addresses and enable status of - // all the CEP cores (indexed by the constants above) + // all the CEP cores (index in array == core index) + // cepMacroMix.cc implementation limits this to 32 total cores. const cep_core_info_t cep_core_info[CEP_TOTAL_CORES] = { - {"AES", 0x70000000, true}, // AES - {"MD5", 0x70010000, true}, // MD5 - {"SHA256", 0x70020000, true}, // SHA256 - {"RSA", 0x70030000, true}, // RSA - {"DES3", 0x70040000, true}, // DES3 - {"DFT", 0x70050000, true}, // DFT - {"IDFT", 0x70060000, true}, // IDFT - {"FIR", 0x70070000, true}, // FIR - {"IIR", 0x70080000, true}, // IIR - {"GPS", 0x70090000, true}, // GPS - {"CEP Version", 0x700F0000, true}, // CEP Version Register - {"SROT", 0x70200000, true}}; // SRoT + {"AES", AES_CORE, 0x70000000, true }, // AES + {"MD5", MD5_CORE, 0x70010000, true }, // MD5 + {"SHA256.0", SHA256_CORE, 0x70020000, true }, // SHA256 .0 + {"SHA256.1", SHA256_CORE, 0x70021000, true }, // SHA256 .1 + {"SHA256.2", SHA256_CORE, 0x70022000, true }, // SHA256 .2 + {"SHA256.3", SHA256_CORE, 0x70023000, true }, // SHA256 .3 + {"RSA", RSA_CORE, 0x70030000, true }, // RSA + {"DES3", DES3_CORE, 0x70040000, true }, // DES3 + {"DFT", DFT_CORE, 0x70050000, true }, // DFT + {"IDFT", IDFT_CORE, 0x70060000, true }, // IDFT + {"FIR", FIR_CORE, 0x70070000, true }, // FIR + {"IIR", IIR_CORE, 0x70080000, true }, // IIR + {"GPS.0", GPS_CORE, 0x70090000, true }, // GPS .0 + {"GPS.1", GPS_CORE, 0x70091000, true }, // GPS .1 + {"GPS.2", GPS_CORE, 0x70092000, true }, // GPS .2 + {"GPS.3", GPS_CORE, 0x70093000, true }, // GPS .3 + {"CEP Version", CEP_VERSION_CORE, 0x700F0000, true }, // CEP Version Register + {"SROT", SROT_CORE, 0x70200000, true }}; // SRoT + + // Direct indexes of version+SROT "cores" + #define CEP_VERSION_REG_INDEX (CEP_TOTAL_CORES - 2) + #define SROT_INDEX (CEP_TOTAL_CORES - 1) + + + // ------------------------------------------------------------------------------------------------------------ + // The constants below, copied from the original implementations of the CEP + // cores, provide constants and offsets for a given core, but not + // ------------------------------------------------------------------------------------------------------------ // Constants copied from AES.h const uint32_t AES_KEY_BITS = 192; @@ -250,11 +262,14 @@ // Constants related to the Surrogate Root of Trust // These constants MUST be equal to those in llki_pkg.sv // + // Additional, those constants which are addresses (i.e., ***_ADDR) are offsets + // within the SRoT memory map. + // // Note: Other LLKI related constants/definitions may be found in cep_crypto.h // ------------------------------------------------------------------------------------------------------------ - const uint32_t SROT_KEYINDEXRAM_ADDR = 0x00000100; // Offset from SROT_BASE_K + const uint32_t SROT_KEYINDEXRAM_ADDR = 0x00000100; // Offset from SROT base address const uint32_t SROT_KEYINDEXRAM_SIZE = 0x00000020; // 32 64-bit words - const uint32_t SROT_KEYRAM_ADDR = 0x00000200; // Offset from SROT_BASE_K + const uint32_t SROT_KEYRAM_ADDR = 0x00000200; // Offset from SROT base address // Note: This cannot be less than SROT_KEYINDEXRAM_ADDR + (SROT_KEYINDEXRAM_SIZE * 8)!!! const uint32_t SROT_KEYRAM_SIZE = 0x00000800; // 2048 64-bit words @@ -270,3 +285,5 @@ const uint32_t SROT_LLKIC2_SCRATCHPAD1_ADDR = 0x00000018; // ------------------------------------------------------------------------------------------------------------ + +#endif \ No newline at end of file diff --git a/cosim/drivers/cep_tests/cep_aes.cc b/cosim/drivers/cep_tests/cep_aes.cc index 597cdb9..d9c7958 100644 --- a/cosim/drivers/cep_tests/cep_aes.cc +++ b/cosim/drivers/cep_tests/cep_aes.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_aes.cc/h // Program: Common Evaluation Platform (CEP) @@ -29,8 +29,8 @@ // // -cep_aes::cep_aes(int seed, int verbose) { - init(); +cep_aes::cep_aes(int coreIndex, int seed, int verbose) { + init(coreIndex); // SetKeySize(192/8); SetBlockSize(128/8); @@ -72,7 +72,7 @@ void cep_aes::LoadKey(void) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)mKEY[i*8 + j]; } - cep_writeNcapture(AES_BASE_K, AES_KEY_BASE + (i * BYTES_PER_WORD), word); + cep_writeNcapture(AES_KEY_BASE + (i * BYTES_PER_WORD), word); } #else for(int i = 0; i < mKeySize/8; i++) { // 8-bytes/word @@ -80,7 +80,7 @@ void cep_aes::LoadKey(void) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)mKEY[i*8 + j]; } - cep_writeNcapture(AES_BASE_K, AES_KEY_BASE + (((AES_KEY_WORDS - 1) - i) * BYTES_PER_WORD), word); + cep_writeNcapture(AES_KEY_BASE + (((AES_KEY_WORDS - 1) - i) * BYTES_PER_WORD), word); } #endif } @@ -94,7 +94,7 @@ void cep_aes::LoadPlaintext(void) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)mHwPt[i*8 + j]; } - cep_writeNcapture(AES_BASE_K, AES_PT_BASE + (i* BYTES_PER_WORD), word); + cep_writeNcapture(AES_PT_BASE + (i* BYTES_PER_WORD), word); } #else for(int i = 0; i < mBlockSize/8; i++) { // 8-bytes/word @@ -102,24 +102,24 @@ void cep_aes::LoadPlaintext(void) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)mHwPt[i*8 + j]; } - cep_writeNcapture(AES_BASE_K, AES_PT_BASE + (((AES_BLOCK_WORDS - 1) - i) * BYTES_PER_WORD), word); + cep_writeNcapture(AES_PT_BASE + (((AES_BLOCK_WORDS - 1) - i) * BYTES_PER_WORD), word); } #endif } void cep_aes::StartEncrypt(void) { - cep_writeNcapture(AES_BASE_K, AES_START, 0x1); - cep_writeNcapture(AES_BASE_K, AES_START, 0x0); + cep_writeNcapture(AES_START, 0x1); + cep_writeNcapture(AES_START, 0x0); } int cep_aes::waitTilDone(int maxTO) { #if 1 if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(AES_BASE_K, AES_DONE, 2, maxTO); + return cep_readNspin(AES_DONE, 2, maxTO); #else while (maxTO > 0) { - if (cep_readNcapture(AES_BASE_K, AES_DONE)) break; + if (cep_readNcapture(AES_DONE)) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -130,14 +130,14 @@ void cep_aes::ReadCiphertext(void) { uint64_t word; #ifdef BIG_ENDIAN for(int i = 0; i < mBlockSize/8; i++) { // 8-bytes/word - word = cep_readNcapture(AES_BASE_K, AES_CT_BASE +(i * BYTES_PER_WORD)); + word = cep_readNcapture(AES_CT_BASE +(i * BYTES_PER_WORD)); for (int j=0;j<8;j++) { mHwCp[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; } } #else for(int i = 0; i < mBlockSize/8; i++) { // 8-bytes/word - word = cep_readNcapture(AES_BASE_K, AES_CT_BASE +(((AES_BLOCK_WORDS - 1) - i) * BYTES_PER_WORD)); + word = cep_readNcapture(AES_CT_BASE +(((AES_BLOCK_WORDS - 1) - i) * BYTES_PER_WORD)); for (int j=0;j<8;j++) { mHwCp[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; } @@ -163,10 +163,10 @@ int cep_aes::RunAes192Test(int maxLoop) { // if (i < 256) { for (int j=0;j 0) { - rdDat = cep_read(device, pAddress); + rdDat = cep_read(coreIndex, pAddress); if (((rdDat ^ pData) & mask) == 0) { break; } diff --git a/cosim/drivers/cep_tests/cep_crypto.h b/cosim/drivers/cep_tests/cep_crypto.h index c8bf3df..2e29c62 100644 --- a/cosim/drivers/cep_tests/cep_crypto.h +++ b/cosim/drivers/cep_tests/cep_crypto.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -61,14 +61,18 @@ class cep_crypto { // To support capturing for playback in BAREMetal mode and Unit-testbench // void SetSrotFlag(int mode) { mSrotFlag = mode; } // no write to file - void SetCaptureMode(int mode, const char *path, const char *testName); - void cep_writeNcapture(int device, uint32_t pAddress, uint64_t pData); - uint64_t cep_readNcapture(int device, uint32_t pAddress); - int cep_readNspin(int device, uint32_t pAddress,uint64_t pData, uint64_t mask, int timeOut); - int cep_readNspin(int device, uint32_t pAddress,uint64_t pData, int timeOut); + void SetCaptureMode(int mode, const char *path, const char *testName); + void cep_writeNcapture(uint32_t pAddress, uint64_t pData); + void cep_writeNcapture(int coreIndex, uint32_t pAddress, uint64_t pData); + uint64_t cep_readNcapture(uint32_t pAddress); + uint64_t cep_readNcapture(int coreIndex, uint32_t pAddress); + int cep_readNspin(int coreIndex, uint32_t pAddress,uint64_t pData, uint64_t mask, int timeOut); + int cep_readNspin(uint32_t pAddress,uint64_t pData, uint64_t mask, int timeOut); + int cep_readNspin(uint32_t pAddress,uint64_t pData, int timeOut); + void MarkSingle(int loop); // - void init(void); + void init(int coreIndex); void freeMe(void); // @@ -77,6 +81,7 @@ class cep_crypto { // protected: + int mCoreIndex; int mSeed; int mVerbose; int mKeySize; diff --git a/cosim/drivers/cep_tests/cep_des3.cc b/cosim/drivers/cep_tests/cep_des3.cc index b853343..2856215 100644 --- a/cosim/drivers/cep_tests/cep_des3.cc +++ b/cosim/drivers/cep_tests/cep_des3.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_des3.cc/h // Program: Common Evaluation Platform (CEP) @@ -26,8 +26,8 @@ // // -cep_des3::cep_des3(int seed, int verbose) { - init(); +cep_des3::cep_des3(int coreIndex, int seed, int verbose) { + init(coreIndex); SetKeySize(24); // 56*3 = 21 bytes SetBlockSize(64/8); // 8 bytes SetSeed(seed); @@ -70,8 +70,8 @@ void cep_des3::LoadKey(void) { //uint64_t word; for(int i = 0; i < 3; i++) { // 7-bytes/word for des3 - // cep_writeNcapture(DES3_BASE_K, DES3_KEY_BASE + (((DES3_KEY_WORDS - 1) - i) * BYTES_PER_WORD),word); - cep_writeNcapture(DES3_BASE_K, DES3_KEY_BASE + (i * BYTES_PER_WORD),mHwKEY[i]); + // cep_writeNcapture(DES3_KEY_BASE + (((DES3_KEY_WORDS - 1) - i) * BYTES_PER_WORD),word); + cep_writeNcapture(DES3_KEY_BASE + (i * BYTES_PER_WORD),mHwKEY[i]); } } @@ -84,29 +84,29 @@ void cep_des3::LoadInText(void) { word = (word << 8) | (uint64_t)mHwPt[i*8 + j]; } #ifdef BIG_ENDIAN - cep_writeNcapture(DES3_BASE_K, DES3_IN_BASE + (i * BYTES_PER_WORD), word); + cep_writeNcapture(DES3_IN_BASE + (i * BYTES_PER_WORD), word); #else - cep_writeNcapture(DES3_BASE_K, DES3_IN_BASE + (((DES3_BLOCK_WORDS - 1) - i) * BYTES_PER_WORD), word); + cep_writeNcapture(DES3_IN_BASE + (((DES3_BLOCK_WORDS - 1) - i) * BYTES_PER_WORD), word); #endif } } void cep_des3::SetMode(void) { - cep_writeNcapture(DES3_BASE_K, DES3_DECRYPT, GetDecrypt()); + cep_writeNcapture(DES3_DECRYPT, GetDecrypt()); } void cep_des3::Start(void) { - cep_writeNcapture(DES3_BASE_K, DES3_START, 0x1); - cep_writeNcapture(DES3_BASE_K, DES3_START, 0x0); + cep_writeNcapture(DES3_START, 0x1); + cep_writeNcapture(DES3_START, 0x0); } int cep_des3::waitTilDone(int maxTO) { #if 1 if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(DES3_BASE_K, DES3_DONE, 1, maxTO); + return cep_readNspin(DES3_DONE, 1, maxTO); #else while (maxTO > 0) { - if (cep_readNcapture(DES3_BASE_K, DES3_DONE)) break; + if (cep_readNcapture(DES3_DONE)) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -117,9 +117,9 @@ void cep_des3::ReadOutText(void) { uint64_t word; for(int i = 0; i < GetBlockSize()/8; i++) { // 8-bytes/word #ifdef BIG_ENDIAN - word = cep_readNcapture(DES3_BASE_K, DES3_CT_BASE +(i * BYTES_PER_WORD)); + word = cep_readNcapture(DES3_CT_BASE +(i * BYTES_PER_WORD)); #else - word = cep_readNcapture(DES3_BASE_K, DES3_CT_BASE +(((DES3_BLOCK_WORDS - 1) - i) * BYTES_PER_WORD)); + word = cep_readNcapture(DES3_CT_BASE +(((DES3_BLOCK_WORDS - 1) - i) * BYTES_PER_WORD)); #endif for (int j=0;j<8;j++) { mHwCp[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; diff --git a/cosim/drivers/cep_tests/cep_des3.h b/cosim/drivers/cep_tests/cep_des3.h index b10445f..2dfa864 100644 --- a/cosim/drivers/cep_tests/cep_des3.h +++ b/cosim/drivers/cep_tests/cep_des3.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_des3.cc/h // Program: Common Evaluation Platform (CEP) @@ -21,7 +21,7 @@ class cep_des3 : public cep_crypto { public: // // constructors // - cep_des3(int seed, int verbose); + cep_des3(int coreIndex, int seed, int verbose); ~cep_des3(); void SetDecrypt(int decrypt) { mDecrypt = decrypt; } @@ -30,7 +30,7 @@ class cep_des3 : public cep_crypto { // int RunDes3Test(int maxLoop); - protected: +protected: // // Routine only supports a single DES block // diff --git a/cosim/drivers/cep_tests/cep_dft.cc b/cosim/drivers/cep_tests/cep_dft.cc index a09707d..28938d9 100644 --- a/cosim/drivers/cep_tests/cep_dft.cc +++ b/cosim/drivers/cep_tests/cep_dft.cc @@ -1,6 +1,6 @@ //************************************************************************ -// Copyright (C) 2020 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// Copyright (C) 2021 Massachusetts Institute of Technology +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_dft/idft.cc/h // Program: Common Evaluation Platform (CEP) @@ -48,13 +48,13 @@ inline double fixed_to_float(fixp16 input) // // // -cep_dft::cep_dft(int seed, int verbose) +cep_dft::cep_dft(int coreIndex, int seed, int verbose) { - init(); + init(coreIndex); SetSeed(0); SetVerbose(verbose); mRTolerance = 5; // % - mITolerance = 20; // % + mITolerance = 20; // % } // cep_dft::~cep_dft() { @@ -70,17 +70,17 @@ void cep_dft::adjust_float(double *rl, double *img, int length) LOGI("%s: len=%d\n",__FUNCTION__,length); } for (int i=0;i 0x%04x/%04x -> %.5f/%.5f\n",i, - rl[i],img[i], newFix & 0xFFFF,iFix & 0xFFFF, newFloat, iFloat); + rl[i],img[i], newFix & 0xFFFF,iFix & 0xFFFF, newFloat, iFloat); } rl[i] = newFloat; img[i] = iFloat; @@ -92,19 +92,21 @@ void cep_dft::adjust_float(double *rl, double *img, int length) // void cep_dft::adjust_fixp(fixp16 *rl, fixp16 *img, int length) { + if (GetVerbose(2)) { LOGI("%s: len=%d\n",__FUNCTION__,length); } + for (int i=0;i %.5f/%.5f -> 0x%04x/%04x\n",i, - rl[i],img[i], newFloat, iFloat,newFix & 0xFFFF,iFix & 0xFFFF); + rl[i],img[i], newFloat, iFloat,newFix & 0xFFFF,iFix & 0xFFFF); } rl[i] = newFix; img[i] = iFix; @@ -121,41 +123,27 @@ void cep_dft::do_dft(const double *rIn, const double *iIn, double *rOut, double #endif } -// IDFT -void cep_dft::do_idft(const double *rIn, const double *iIn, double *rOut, double *iOut, int len) -{ - memcpy(rOut, rIn, sizeof(double)*len); - memcpy(iOut, iIn, sizeof(double)*len); -#if defined(BARE_MODE) -#else - (void)Fft_inverseTransform(rOut, iOut, len); -#endif -} - -// -// DFT -// void cep_dft::dft_setX(double *rbuf, double *ibuf, int len) { uint64_t temp; if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } for (int i=0;i> 48) & 0xFFFF); ibuf[i*2] = fixed_to_float((temp >> 32) & 0xFFFF); rbuf[(i*2)+1] = fixed_to_float((temp >> 16) & 0xFFFF); @@ -174,292 +162,142 @@ void cep_dft::dft_getY(double *rbuf, double *ibuf, int len) { void cep_dft::dft_Start(void) { - if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - cep_writeNcapture(DFT_BASE_K, DFT_START, 0x1); - cep_writeNcapture(DFT_BASE_K, DFT_START, 0x0); + if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } + cep_writeNcapture(DFT_START, 0x1); + cep_writeNcapture(DFT_START, 0x0); } int cep_dft::dft_waitTilDone(int maxTO) { -#if 1 - if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(DFT_BASE_K, DFT_DONE, 4, maxTO); -#else - if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } - while (maxTO > 0) { - if (cep_readNcapture(DFT_BASE_K, DFT_DONE)) break; - maxTO--; - }; - return (maxTO <= 0) ? 1 : 0; -#endif -} - -int cep_dft::dft_CheckSamples(int lpCnt, int startIdx,int samCnt) { - if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - // - double repsilon,rdiff; - double iepsilon,idiff; - for (int i=startIdx;i repsilon) { // || (idiff > iepsilon)) { - if (GetExpErr()==0) { - LOGE("%s: dft lp=%d i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,lpCnt ,i, - mRexp[i],mIexp[i], mRact[i],mIact[i], - rdiff,idiff,repsilon,iepsilon); - } - mErrCnt++; - } else if (GetVerbose(2)) { - LOGI("%s: i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,i, - mRexp[i],mIexp[i], mRact[i],mIact[i], - rdiff,idiff,repsilon,iepsilon); - } - } - return mErrCnt; -} - -// -// IDFT -// -void cep_dft::idft_setX(double *rbuf, double *ibuf, int len) { - uint64_t temp; - if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - for (int i=0;i((temp >> 48) & 0xFFFF)); - ibuf[i*2] = fixed_to_float(static_cast((temp >> 32) & 0xFFFF)); - rbuf[(i*2)+1] = fixed_to_float(static_cast((temp >> 16) & 0xFFFF)); - ibuf[(i*2)+1] = fixed_to_float(static_cast((temp >> 0) & 0xFFFF)); - } -} - -void cep_dft::idft_Start(void) { - if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - cep_writeNcapture(IDFT_BASE_K, IDFT_START, 0x1); - cep_writeNcapture(IDFT_BASE_K, IDFT_START, 0x0); -} + double repsilon, rdiff; + double iepsilon, idiff; -int cep_dft::idft_waitTilDone(int maxTO) { -#if 1 - if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(IDFT_BASE_K, IDFT_DONE, 4, maxTO); -#else - if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } - while (maxTO > 0) { - if (cep_readNcapture(IDFT_BASE_K, IDFT_DONE)) break; - maxTO--; - }; - return (maxTO <= 0) ? 1 : 0; -#endif -} + // Loop to check all samples + for (int i = startIdx ; i < samCnt ; i++) { -int cep_dft::idft_CheckSamples(int lpCnt, int startIdx,int samCnt) { - if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - // - double repsilon,rdiff; - double iepsilon,idiff; - for (int i=startIdx;i repsilon) || (idiff > iepsilon)) { // FIXME: dont know why only the real part are good if (rdiff > repsilon) { if (!GetExpErr()) { - LOGE("%s: idft lp=%d i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,lpCnt, i, - mRexp[i],mIexp[i], mRact[i],mIact[i], - rdiff,idiff,repsilon,iepsilon); + LOGE("%s: lp=%d i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,lpCnt ,i, + mRexp[i],mIexp[i], mRact[i],mIact[i], + rdiff,idiff,repsilon,iepsilon); } mErrCnt++; } else if (GetVerbose(2)) { - LOGI("%s: i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,i, - mRexp[i],mIexp[i], mRact[i],mIact[i], - rdiff,idiff,repsilon,iepsilon); + LOGI("%s: lp=%d i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,lpCnt ,i, + mRexp[i],mIexp[i], mRact[i],mIact[i], + rdiff,idiff,repsilon,iepsilon); } } return mErrCnt; } -/* -Due to lost of precision, only these test can be used - -Single FFT tests - N inputs and N outputs -Input random data -Inputs are all zeros -Inputs are all ones (or some other nonzero value) -Inputs alternate between +1 and -1. -Input is e^(8*j*2*pi*i/N) for i = 0,1,2, ...,N-1. (j = sqrt(-1)) -Input is cos(8*2*pi*i/N) for i = 0,1,2, ...,N-1. -Input is e^((43/7)*j*2*pi*i/N) for i = 0,1,2, ...,N-1. (j= sqrt(-1)) -Input is cos((43/7)*2*pi*i/N) for i = 0,1,2, ...,N-1. - -*/ int cep_dft::RunDftTest(int maxLoop) { fixp16 fixR, fixI; uint32_t ranX; - // - // - int skipFirstSample = 0; + + int skipFirstNSamples = 0; - for (int i=0;i>16) & 0xFFFF; - for (int j=0; j < MAX_DFT_SAMPLES; j++) { - mRin[j] = fixed_to_float(fixR+j); - mIin[j] = fixed_to_float(fixI+j); - } - skipFirstSample = 1; // dont know why??? when random - mRTolerance = 70; // % FIXME!!!! - mITolerance = 70; // % FIXME!!!! - break; + case 0: + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = cos(8*2*M_PI*j/MAX_DFT_SAMPLES); + mIin[j] = sin(8*2*M_PI*j/MAX_DFT_SAMPLES); + } + break; + case 1: + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = cos((43/7)*M_PI*j/MAX_DFT_SAMPLES); + mIin[j] = sin((43/7)*M_PI*j/MAX_DFT_SAMPLES); + } + break; + case 2: + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = (j&0x1) ? 1.0 : -1.0; + mIin[j] = (j&0x1) ? -1.0 : 1.0; + } + break; + case 3: + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = 1.0; + mIin[j] = 1.0; + } + break; + default: + ranX = GetSeed(); + SetSeed(ranX++); // multi-thread might destroy the semi-fixed randome of this test + fixR = ranX & 0xFFFF; + fixI = (ranX>>16) & 0xFFFF; + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = fixed_to_float(fixR+j); + mIin[j] = fixed_to_float(fixI+j); + } + + skipFirstNSamples = 1; + mRTolerance = 70; + mITolerance = 70; + + break; } - // adjust ?? + adjust_float(mRin, mIin, MAX_DFT_SAMPLES); - // - do_dft(mRin,mIin,mRexp, mIexp, MAX_DFT_SAMPLES); - //adjust_float(mRexp, mIexp, MAX_DFT_SAMPLES); + + do_dft(mRin, mIin, mRexp, mIexp, MAX_DFT_SAMPLES); + if (GetVerbose(2)) { PrintMe("DFT-In",mRin,mIin,MAX_DFT_SAMPLES); PrintMe("DFT-Exp",mRexp,mIexp,MAX_DFT_SAMPLES); } - // -#if 1 + // DFT - if (!mErrCnt) { + if (!mErrCnt) { dft_setX(mRin, mIin, MAX_DFT_SAMPLES); dft_Start(); mErrCnt += dft_waitTilDone(500); if (!mErrCnt) { - dft_getY(mRact, mIact, MAX_DFT_SAMPLES); - if (GetVerbose(2)) { - PrintMe("DFT-act",mRact,mIact,MAX_DFT_SAMPLES); - } - //adjust_float(mRact, mIact, MAX_DFT_SAMPLES); - mErrCnt += dft_CheckSamples(i,skipFirstSample,MAX_DFT_SAMPLES); + dft_getY(mRact, mIact, MAX_DFT_SAMPLES); + if (GetVerbose(2)) { + PrintMe("DFT-act",mRact,mIact,MAX_DFT_SAMPLES); + } + mErrCnt += dft_CheckSamples(i, skipFirstNSamples, MAX_DFT_SAMPLES); } - } -#endif -#if 1 - // IDFT - if (!mErrCnt) { - // input to IDFT - adjust_float(mRact, mIact, MAX_DFT_SAMPLES); - // - do_idft(mRact, mIact, mRexp, mIexp, MAX_DFT_SAMPLES); - //adjust_float(mRAin, mIAin, MAX_DFT_SAMPLES); - if (GetVerbose(2)) { - PrintMe("IDFT-in",mRact,mIact,MAX_DFT_SAMPLES); - PrintMe("IDFT-exp",mRexp,mIexp,MAX_DFT_SAMPLES); - } - // - idft_setX(mRact, mIact, MAX_DFT_SAMPLES); - idft_Start(); - mErrCnt += idft_waitTilDone(500); - if (!mErrCnt) { - idft_getY(mRact, mIact, MAX_DFT_SAMPLES); - if (GetVerbose(2)) { - PrintMe("IDFT-act",mRact,mIact,MAX_DFT_SAMPLES); - } - //adjust_float(mRAin, mIAin, MAX_DFT_SAMPLES); - mErrCnt += idft_CheckSamples(i,skipFirstSample,MAX_DFT_SAMPLES); - } - } -#endif - - // MarkSingle(i); if (mErrCnt) break; + } + return mErrCnt; } diff --git a/cosim/drivers/cep_tests/cep_dft.h b/cosim/drivers/cep_tests/cep_dft.h index 56ec783..7c1ed0d 100644 --- a/cosim/drivers/cep_tests/cep_dft.h +++ b/cosim/drivers/cep_tests/cep_dft.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright (C) 2020 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_dft/idft.cc/h // Program: Common Evaluation Platform (CEP) @@ -27,16 +27,16 @@ class cep_dft : public cep_crypto { public: // // constructors // - cep_dft(int seed, int verbose); + cep_dft(int coreIndex, int seed, int verbose); ~cep_dft(); int RunDftTest(int maxLoop); - protected: +protected: void adjust_float(double *rl, double *img, int length); void adjust_fixp(fixp16 *rl, fixp16 *img, int length); void do_dft(const double *rIn, const double *iIn, double *rOut, double *iOut, int len); - void do_idft(const double *rIn, const double *iIn, double *rOut, double *iOut, int len); + //void do_idft(const double *rIn, const double *iIn, double *rOut, double *iOut, int len); // void dft_setX(double *rbuf, double *ibuf, int len) ; void dft_getY(double *rbuf, double *ibuf, int len) ; @@ -44,11 +44,11 @@ class cep_dft : public cep_crypto { int dft_waitTilDone(int maxTO); int dft_CheckSamples(int lpCnt, int startIdx,int samCnt) ; // - void idft_setX(double *rbuf, double *ibuf, int len) ; + /*void idft_setX(double *rbuf, double *ibuf, int len) ; void idft_getY(double *rbuf, double *ibuf, int len) ; void idft_Start(void) ; int idft_waitTilDone(int maxTO); - int idft_CheckSamples(int lpCnt, int startIdx,int samCnt) ; + int idft_CheckSamples(int lpCnt, int startIdx,int samCnt) ; */ // double mRin[MAX_DFT_SAMPLES]; double mIin[MAX_DFT_SAMPLES]; diff --git a/cosim/drivers/cep_tests/cep_fir.cc b/cosim/drivers/cep_tests/cep_fir.cc index 80fcc7c..c5d6d33 100644 --- a/cosim/drivers/cep_tests/cep_fir.cc +++ b/cosim/drivers/cep_tests/cep_fir.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_fir.cc/h // Program: Common Evaluation Platform (CEP) @@ -46,9 +46,9 @@ double cep_fir::fixed_to_float(fixp32_8 input) // // // -cep_fir::cep_fir(int seed, int verbose) +cep_fir::cep_fir(int coreIndex, int seed, int verbose) { - init(); + init(coreIndex); SetSeed(28147424); SetVerbose(verbose); mTolerance = 1; // % @@ -158,34 +158,34 @@ void cep_fir::LoadInSamples(int samCnt) { // duplicate 32 to 64 for coverage word |= (word << 32) | (word & 0xFFFFFFFFLL); // - cep_writeNcapture(FIR_BASE_K, FIR_IN_DATA, word); //Write data - cep_writeNcapture(FIR_BASE_K, FIR_IN_ADDR, i); //Write addr - cep_writeNcapture(FIR_BASE_K, FIR_IN_WRITE, 0x02); //Load data - cep_writeNcapture(FIR_BASE_K, FIR_IN_WRITE, 0x00); //Stop + cep_writeNcapture(FIR_IN_DATA, word); //Write data + cep_writeNcapture(FIR_IN_ADDR, i); //Write addr + cep_writeNcapture(FIR_IN_WRITE, 0x02); //Load data + cep_writeNcapture(FIR_IN_WRITE, 0x00); //Stop } } void cep_fir::Start(void) { - cep_writeNcapture(FIR_BASE_K, FIR_START, 0x1); - cep_writeNcapture(FIR_BASE_K, FIR_START, 0x0); + cep_writeNcapture(FIR_START, 0x1); + cep_writeNcapture(FIR_START, 0x0); } void cep_fir::Reset(int assert) { - cep_writeNcapture(FIR_BASE_K, FIR_RESET, assert); + cep_writeNcapture(FIR_RESET, assert); } void cep_fir::Reset(void) { - cep_writeNcapture(FIR_BASE_K, FIR_RESET, 0x1); - cep_writeNcapture(FIR_BASE_K, FIR_RESET, 0x0); + cep_writeNcapture(FIR_RESET, 0x1); + cep_writeNcapture(FIR_RESET, 0x0); } int cep_fir::waitTilDone(int maxTO) { #if 1 if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(FIR_BASE_K, FIR_DONE, 0x4, maxTO); + return cep_readNspin(FIR_DONE, 0x4, maxTO); #else while (maxTO > 0) { - if (cep_readNcapture(FIR_BASE_K, FIR_DONE) & 0x4) break; + if (cep_readNcapture(FIR_DONE) & 0x4) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -195,8 +195,8 @@ int cep_fir::waitTilDone(int maxTO) { void cep_fir::ReadOutSamples(int samCnt) { uint64_t word; for(int i = 0; i < samCnt; i++) { // 8-bytes/word - cep_writeNcapture(FIR_BASE_K, FIR_OUT_ADDR, i); //Write addr - word=cep_readNcapture(FIR_BASE_K, FIR_OUT_DATA); //Read data + cep_writeNcapture(FIR_OUT_ADDR, i); //Write addr + word=cep_readNcapture(FIR_OUT_DATA); //Read data mAct[i] = fixed_to_float(word); } } diff --git a/cosim/drivers/cep_tests/cep_fir.h b/cosim/drivers/cep_tests/cep_fir.h index 3409538..407b0c0 100644 --- a/cosim/drivers/cep_tests/cep_fir.h +++ b/cosim/drivers/cep_tests/cep_fir.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_fir.cc/h // Program: Common Evaluation Platform (CEP) @@ -28,7 +28,7 @@ class cep_fir : public cep_crypto { public: // // constructors // - cep_fir(int seed, int verbose); + cep_fir(int coreIndex, int seed, int verbose); cep_fir() { } ~cep_fir(); @@ -37,7 +37,7 @@ class cep_fir : public cep_crypto { int RunFirTest(int maxLoop); - protected: +protected: fixp32_8 float_to_fixed(double input); double fixed_to_float(fixp32_8 input); void adjust_float(double *inout, int length); diff --git a/cosim/drivers/cep_tests/cep_gps.cc b/cosim/drivers/cep_tests/cep_gps.cc index 1a8b74a..f5aa90e 100644 --- a/cosim/drivers/cep_tests/cep_gps.cc +++ b/cosim/drivers/cep_tests/cep_gps.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_gps.cc/h // Program: Common Evaluation Platform (CEP) @@ -24,12 +24,8 @@ #include "random48.h" // // -cep_gps::cep_gps(int seed, int verbose) : cep_aes(seed,verbose) { - init(); - // - //SetSvNum(0); - // can't call this!!! since we dont know which core is running it yet!!! - //ResetCA_code(); +cep_gps::cep_gps(int coreIndex, int seed, int verbose) : cep_aes(coreIndex, seed,verbose) { + init(coreIndex); } // @@ -40,7 +36,7 @@ void cep_gps::SetSvNum (int svNum) { mSvNum= svNum; } // Load SvNum - cep_writeNcapture(GPS_BASE_K, GPS_SV_NUM, GetSvNum()); + cep_writeNcapture(GPS_SV_NUM, GetSvNum()); // } @@ -52,7 +48,7 @@ void cep_gps::SetPcodeSpeed (uint16_t xn_cnt_speed, uint32_t z_cnt_speed) { xn_cnt_speed &= 0xfff; z_cnt_speed &= 0x7ffff; uint64_t pcode_speed = xn_cnt_speed | (z_cnt_speed << 12); - cep_writeNcapture(GPS_BASE_K, GPS_PCODE_SPEED, pcode_speed); + cep_writeNcapture(GPS_PCODE_SPEED, pcode_speed); } /* Defaults: @@ -72,7 +68,7 @@ void cep_gps::SetPcodeXnInit (uint16_t x1a_initial, uint16_t x1b_initial, uint16 pcode_xinitial |= (uint64_t)x1b_initial << 12; pcode_xinitial |= (uint64_t)x2a_initial << 24; pcode_xinitial |= (uint64_t)x2b_initial << 36; - cep_writeNcapture(GPS_BASE_K, GPS_PCODE_XINI, pcode_xinitial); + cep_writeNcapture(GPS_PCODE_XINI, pcode_xinitial); } @@ -85,7 +81,7 @@ void cep_gps::LoadKey(void) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)mKEY[i*8 + j]; } - cep_writeNcapture(GPS_BASE_K, GPS_KEY_BASE + (i * BYTES_PER_WORD), word); + cep_writeNcapture(GPS_KEY_BASE + (i * BYTES_PER_WORD), word); } #else for(int i = 0; i < mKeySize/8; i++) { // 8-bytes/word @@ -93,7 +89,7 @@ void cep_gps::LoadKey(void) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)mKEY[i*8 + j]; } - cep_writeNcapture(GPS_BASE_K, GPS_KEY_BASE + (((AES_KEY_WORDS - 1) - i) * BYTES_PER_WORD), word); + cep_writeNcapture(GPS_KEY_BASE + (((AES_KEY_WORDS - 1) - i) * BYTES_PER_WORD), word); } #endif } @@ -101,20 +97,20 @@ void cep_gps::LoadKey(void) { void cep_gps::Start(void) { // - cep_writeNcapture(GPS_BASE_K, GPS_GEN_NEXT, 0x1); - cep_writeNcapture(GPS_BASE_K, GPS_GEN_NEXT, 0x0); + cep_writeNcapture(GPS_GEN_NEXT, 0x1); + cep_writeNcapture(GPS_GEN_NEXT, 0x0); } void cep_gps::BusReset(int assert) { - cep_writeNcapture(GPS_BASE_K, GPS_RESET, 0x01); + cep_writeNcapture(GPS_RESET, 0x01); } void cep_gps::BusReset(void) { // need to extend at least for slow clock can catch for (int i=0;i<5;i++) { - cep_writeNcapture(GPS_BASE_K, GPS_RESET, 0x01); + cep_writeNcapture(GPS_RESET, 0x01); } - cep_writeNcapture(GPS_BASE_K, GPS_RESET, 0x00); + cep_writeNcapture(GPS_RESET, 0x00); // } @@ -123,7 +119,7 @@ int cep_gps::ReadNCheck_CA_Code(int mask) { int errCnt = 0; int expCACode= GetCA_code(GetSvNum()); - int actCACode = cep_readNcapture(GPS_BASE_K, GPS_CA_BASE); + int actCACode = cep_readNcapture(GPS_CA_BASE); errCnt += ((expCACode ^ actCACode) & mask); // @@ -141,10 +137,10 @@ int cep_gps::ReadNCheck_CA_Code(int mask) int cep_gps::waitTilDone(int maxTO) { #if 1 if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(GPS_BASE_K, GPS_GEN_DONE, 2, 2, maxTO); + return cep_readNspin(GPS_GEN_DONE, 2, 2, maxTO); #else while (maxTO > 0) { - if (cep_readNcapture(GPS_BASE_K, GPS_GEN_DONE)) break; + if (cep_readNcapture(GPS_GEN_DONE)) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -157,14 +153,14 @@ void cep_gps::Read_PCode(void) { uint64_t word; #ifdef BIG_ENDIAN for(int i = 0; i < mBlockSize/8; i++) { // 8-bytes/word - word = cep_readNcapture(GPS_BASE_K, GPS_P_BASE + i*8); + word = cep_readNcapture(GPS_P_BASE + i*8); for (int j=0;j<8;j++) { mHwPt[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; } } #else for(int i = 0; i < mBlockSize/8; i++) { // 8-bytes/word - word = cep_readNcapture(GPS_BASE_K, GPS_P_BASE + (1-i)*8); + word = cep_readNcapture(GPS_P_BASE + (1-i)*8); // As of 04/12/20: each 32 bits are swapped within 64-bit register (see gps.scala) for (int j=0;j<8;j++) { switch (j) { @@ -186,14 +182,14 @@ void cep_gps::Read_LCode(void) { uint64_t word; #ifdef BIG_ENDIAN for(int i = 0; i < mBlockSize/8; i++) { // 8-bytes/word - word = cep_readNcapture(GPS_BASE_K, GPS_L_BASE + i*8); + word = cep_readNcapture(GPS_L_BASE + i*8); for (int j=0;j<8;j++) { mHwCp[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; } } #else for(int i = 0; i < mBlockSize/8; i++) { // 8-bytes/word - word = cep_readNcapture(GPS_BASE_K, GPS_L_BASE + (1-i)*8); + word = cep_readNcapture(GPS_L_BASE + (1-i)*8); // As of 04/12/20: each 32 bits are swapped within 64-bit register (see gps.scala) for (int j=0;j<8;j++) { switch (j) { diff --git a/cosim/drivers/cep_tests/cep_gps.h b/cosim/drivers/cep_tests/cep_gps.h index 89225f7..70279d4 100644 --- a/cosim/drivers/cep_tests/cep_gps.h +++ b/cosim/drivers/cep_tests/cep_gps.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_gps.cc/h // Program: Common Evaluation Platform (CEP) @@ -23,7 +23,7 @@ class cep_gps : public cep_aes { public: // // constructors // - cep_gps(int seed, int verbose); + cep_gps(int coreIndex, int seed, int verbose); ~cep_gps() {}; int GetSvNum ( ) { return mSvNum; } @@ -44,7 +44,7 @@ class cep_gps : public cep_aes { // int RunGpsTest(int maxLoop); - protected: +protected: // int mSvNum; int mExpCaCode; diff --git a/cosim/drivers/cep_tests/cep_idft.cc b/cosim/drivers/cep_tests/cep_idft.cc index a9a9484..38c7c65 100644 --- a/cosim/drivers/cep_tests/cep_idft.cc +++ b/cosim/drivers/cep_tests/cep_idft.cc @@ -1,8 +1,8 @@ //************************************************************************ -// Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// Copyright (C) 2021 Massachusetts Institute of Technology +// SPDX License Identifier: BSD-2-Clause // -// File Name: cep_idft/idft.cc/h +// File Name: cep_dft/idft.cc/h // Program: Common Evaluation Platform (CEP) // Description: dft/idft test for CEP // Notes: @@ -48,9 +48,9 @@ inline double fixed_to_float(fixp16 input) // // // -cep_idft::cep_idft(int seed, int verbose) +cep_idft::cep_idft(int coreIndex, int seed, int verbose) { - init(); + init(coreIndex); SetSeed(0); SetVerbose(verbose); mRTolerance = 5; // % @@ -66,9 +66,11 @@ cep_idft::~cep_idft() { void cep_idft::adjust_float(double *rl, double *img, int length) { - if (GetVerbose()) { + + if (GetVerbose(2)) { LOGI("%s: len=%d\n",__FUNCTION__,length); } + for (int i=0;i 0x%04x/%04x -> %.5f/%.5f\n",i, - rl[i],img[i], newFix & 0xFFFF,iFix & 0xFFFF, newFloat, iFloat); + rl[i],img[i], newFix & 0xFFFF,iFix & 0xFFFF, newFloat, iFloat); } rl[i] = newFloat; img[i] = iFloat; @@ -92,7 +94,7 @@ void cep_idft::adjust_float(double *rl, double *img, int length) // void cep_idft::adjust_fixp(fixp16 *rl, fixp16 *img, int length) { - if (GetVerbose()) { + if (GetVerbose(2)) { LOGI("%s: len=%d\n",__FUNCTION__,length); } for (int i=0;i %.5f/%.5f -> 0x%04x/%04x\n",i, - rl[i],img[i], newFloat, iFloat,newFix & 0xFFFF,iFix & 0xFFFF); + rl[i],img[i], newFloat, iFloat,newFix & 0xFFFF,iFix & 0xFFFF); } rl[i] = newFix; img[i] = iFix; } } -// IDFT void cep_idft::do_idft(const double *rIn, const double *iIn, double *rOut, double *iOut, int len) { memcpy(rOut, rIn, sizeof(double)*len); @@ -122,96 +123,88 @@ void cep_idft::do_idft(const double *rIn, const double *iIn, double *rOut, doubl #endif } -// -// IDFT -// void cep_idft::idft_setX(double *rbuf, double *ibuf, int len) { uint64_t temp; - if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } + if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } for (int i=0;i((temp >> 48) & 0xFFFF)); - ibuf[i*2] = fixed_to_float(static_cast((temp >> 32) & 0xFFFF)); - rbuf[(i*2)+1] = fixed_to_float(static_cast((temp >> 16) & 0xFFFF)); - ibuf[(i*2)+1] = fixed_to_float(static_cast((temp >> 0) & 0xFFFF)); + cep_writeNcapture(IDFT_OUT_ADDR, i); //Write addr + temp = cep_readNcapture(IDFT_OUT_DATA); //Read data + rbuf[i*2] = fixed_to_float((temp >> 48) & 0xFFFF); + ibuf[i*2] = fixed_to_float((temp >> 32) & 0xFFFF); + rbuf[(i*2)+1] = fixed_to_float((temp >> 16) & 0xFFFF); + ibuf[(i*2)+1] = fixed_to_float((temp >> 0) & 0xFFFF); } } - void cep_idft::idft_Start(void) { - if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } - cep_writeNcapture(IDFT_BASE_K, IDFT_START, 0x1); - cep_writeNcapture(IDFT_BASE_K, IDFT_START, 0x0); + if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } + cep_writeNcapture(IDFT_START, 0x1); + cep_writeNcapture(IDFT_START, 0x0); } int cep_idft::idft_waitTilDone(int maxTO) { -#if 1 - if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(IDFT_BASE_K, IDFT_DONE, 4, maxTO); -#else - if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } - while (maxTO > 0) { - if (cep_readNcapture(IDFT_BASE_K, IDFT_DONE)) break; - maxTO--; - }; - return (maxTO <= 0) ? 1 : 0; -#endif + if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } + return cep_readNspin(IDFT_DONE, 4, maxTO); } -int cep_idft::idft_CheckSamples(int startIdx,int samCnt) { - if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } - // - double repsilon,rdiff; - double iepsilon,idiff; - for (int i=startIdx;i repsilon) || (idiff > iepsilon)) { // FIXME: dont know why only the real part are good if (rdiff > repsilon) { if (!GetExpErr()) { - LOGE("%s: i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,i, - mRexp[i],mIexp[i], mRact[i],mIact[i], - rdiff,idiff,repsilon,iepsilon); + LOGE("%s: lp=%d i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,lpCnt ,i, + mRexp[i],mIexp[i], mRact[i],mIact[i], + rdiff,idiff,repsilon,iepsilon); } mErrCnt++; - } else if (GetVerbose()) { - LOGI("%s: i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,i, - mRexp[i],mIexp[i], mRact[i],mIact[i], - rdiff,idiff,repsilon,iepsilon); + } else if (GetVerbose(2)) { + LOGI("%s: lp=%d i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,lpCnt ,i, + mRexp[i],mIexp[i], mRact[i],mIact[i], + rdiff,idiff,repsilon,iepsilon); } } return mErrCnt; @@ -234,95 +227,87 @@ Input is cos((43/7)*2*pi*i/N) for i = 0,1,2, ...,N-1. int cep_idft::RunIdftTest(int maxLoop) { fixp16 fixR, fixI; uint32_t ranX; - // - // - int skipFirstSample = 0; + + int skipFirstNSamples = 0; + Random48_srand48(GetSeed()); - for (int i=0;i>16) & 0xFFFF; - for (int j=0; j < MAX_DFT_SAMPLES; j++) { - mRin[j] = fixed_to_float(fixR+j); - mIin[j] = fixed_to_float(fixI+j); - } - skipFirstSample = 1; // dont know why??? when random - mRTolerance = 60; // % FIXME!!!! - mITolerance = 60; // % FIXME!!!! - break; + case 0: + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = cos(8*2*M_PI*j/MAX_DFT_SAMPLES); + mIin[j] = sin(8*2*M_PI*j/MAX_DFT_SAMPLES); + } + break; + case 1: + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = cos((43/7)*M_PI*j/MAX_DFT_SAMPLES); + mIin[j] = sin((43/7)*M_PI*j/MAX_DFT_SAMPLES); + } + break; + case 2: + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = (j&0x1) ? 1.0 : -1.0; + mIin[j] = (j&0x1) ? -1.0 : 1.0; + } + break; + case 3: + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = 1.0; + mIin[j] = 1.0; + } + break; + default: + ranX = GetSeed(); + SetSeed(ranX++); // multi-thread might destroy the semi-fixed randome of this test + fixR = ranX & 0xFFFF; + fixI = (ranX>>16) & 0xFFFF; + for (int j=0; j < MAX_DFT_SAMPLES; j++) { + mRin[j] = fixed_to_float(fixR+j); + mIin[j] = fixed_to_float(fixI+j); + } + + skipFirstNSamples = 1; + mRTolerance = 70; + mITolerance = 70; + + break; + } + + adjust_float(mRact, mIact, MAX_DFT_SAMPLES); + + do_idft(mRact, mIact, mRexp, mIexp, MAX_DFT_SAMPLES); + + if (GetVerbose(2)) { + PrintMe("IDFT-in",mRact,mIact,MAX_DFT_SAMPLES); + PrintMe("IDFT-exp",mRexp,mIexp,MAX_DFT_SAMPLES); } -#if 1 // IDFT if (!mErrCnt) { - // input to IDFT - adjust_float(mRact, mIact, MAX_DFT_SAMPLES); - // - do_idft(mRact, mIact, mRexp, mIexp, MAX_DFT_SAMPLES); - //adjust_float(mRAin, mIAin, MAX_DFT_SAMPLES); - if (GetVerbose()) { - PrintMe("IDFT-in",mRact,mIact,MAX_DFT_SAMPLES); - PrintMe("IDFT-exp",mRexp,mIexp,MAX_DFT_SAMPLES); - } - // idft_setX(mRact, mIact, MAX_DFT_SAMPLES); idft_Start(); mErrCnt += idft_waitTilDone(500); if (!mErrCnt) { - idft_getY(mRact, mIact, MAX_DFT_SAMPLES); - if (GetVerbose()) { - PrintMe("IDFT-act",mRact,mIact,MAX_DFT_SAMPLES); - } - //adjust_float(mRAin, mIAin, MAX_DFT_SAMPLES); - mErrCnt += idft_CheckSamples(skipFirstSample,MAX_DFT_SAMPLES); + idft_getY(mRact, mIact, MAX_DFT_SAMPLES); + if (GetVerbose(2)) { + PrintMe("IDFT-act",mRact,mIact,MAX_DFT_SAMPLES); + } + mErrCnt += idft_CheckSamples(i, skipFirstNSamples, MAX_DFT_SAMPLES); } } -#endif - // MarkSingle(i); if (mErrCnt) break; } diff --git a/cosim/drivers/cep_tests/cep_idft.h b/cosim/drivers/cep_tests/cep_idft.h index c992f0d..9be88be 100644 --- a/cosim/drivers/cep_tests/cep_idft.h +++ b/cosim/drivers/cep_tests/cep_idft.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_idft.cc/h // Program: Common Evaluation Platform (CEP) @@ -27,12 +27,12 @@ class cep_idft : public cep_crypto { public: // // constructors // - cep_idft(int seed, int verbose); + cep_idft(int coreIndex, int seed, int verbose); ~cep_idft(); int RunIdftTest(int maxLoop); - protected: +protected: void adjust_float(double *rl, double *img, int length); void adjust_fixp(fixp16 *rl, fixp16 *img, int length); void do_idft(const double *rIn, const double *iIn, double *rOut, double *iOut, int len); @@ -42,7 +42,7 @@ class cep_idft : public cep_crypto { void idft_getY(double *rbuf, double *ibuf, int len) ; void idft_Start(void) ; int idft_waitTilDone(int maxTO); - int idft_CheckSamples(int startIdx,int samCnt) ; + int idft_CheckSamples(int lpCnt, int startIdx,int samCnt) ; // double mRin[MAX_DFT_SAMPLES]; double mIin[MAX_DFT_SAMPLES]; @@ -51,11 +51,11 @@ class cep_idft : public cep_crypto { double mIexp[MAX_DFT_SAMPLES]; double mRact[MAX_DFT_SAMPLES]; double mIact[MAX_DFT_SAMPLES]; - // tolerance in percentage int mRTolerance; int mITolerance; + }; // diff --git a/cosim/drivers/cep_tests/cep_iir.cc b/cosim/drivers/cep_tests/cep_iir.cc index 481f2cd..c8764bc 100644 --- a/cosim/drivers/cep_tests/cep_iir.cc +++ b/cosim/drivers/cep_tests/cep_iir.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -48,9 +48,9 @@ double cep_iir::fixed_to_float(fixp32_8 input) // // // -cep_iir::cep_iir(int seed, int verbose) +cep_iir::cep_iir(int coreIndex, int seed, int verbose) { - init(); + init(coreIndex); SetSeed(15145975); SetVerbose(verbose); mTolerance = 1; // % @@ -158,34 +158,34 @@ void cep_iir::LoadInSamples(int samCnt) { // duplicate 32 to 64 for coverage word |= (word << 32) | (word & 0xFFFFFFFFLL); // - cep_writeNcapture(IIR_BASE_K, IIR_IN_DATA, word); //Write data - cep_writeNcapture(IIR_BASE_K, IIR_IN_ADDR, i); //Write addr - cep_writeNcapture(IIR_BASE_K, IIR_IN_WRITE, 0x02); //Load data - cep_writeNcapture(IIR_BASE_K, IIR_IN_WRITE, 0x00); //Stop + cep_writeNcapture(IIR_IN_DATA, word); //Write data + cep_writeNcapture(IIR_IN_ADDR, i); //Write addr + cep_writeNcapture(IIR_IN_WRITE, 0x02); //Load data + cep_writeNcapture(IIR_IN_WRITE, 0x00); //Stop } } void cep_iir::Start(void) { - cep_writeNcapture(IIR_BASE_K, IIR_START, 0x1); - cep_writeNcapture(IIR_BASE_K, IIR_START, 0x0); + cep_writeNcapture(IIR_START, 0x1); + cep_writeNcapture(IIR_START, 0x0); } void cep_iir::Reset(int assert) { - cep_writeNcapture(IIR_BASE_K, IIR_RESET, assert); + cep_writeNcapture(IIR_RESET, assert); } void cep_iir::Reset(void) { - cep_writeNcapture(IIR_BASE_K, IIR_RESET, 0x1); - cep_writeNcapture(IIR_BASE_K, IIR_RESET, 0x0); + cep_writeNcapture(IIR_RESET, 0x1); + cep_writeNcapture(IIR_RESET, 0x0); } int cep_iir::waitTilDone(int maxTO) { #if 1 if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(IIR_BASE_K, IIR_DONE, 0x4, maxTO); + return cep_readNspin(IIR_DONE, 0x4, maxTO); #else while (maxTO > 0) { - if (cep_readNcapture(IIR_BASE_K, IIR_DONE) & 0x4) break; + if (cep_readNcapture(IIR_DONE) & 0x4) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -195,8 +195,8 @@ int cep_iir::waitTilDone(int maxTO) { void cep_iir::ReadOutSamples(int samCnt) { uint64_t word; for(int i = 0; i < samCnt; i++) { // 8-bytes/word - cep_writeNcapture(IIR_BASE_K, IIR_OUT_ADDR, i); //Write addr - word=cep_readNcapture(IIR_BASE_K, IIR_OUT_DATA); //Read data + cep_writeNcapture(IIR_OUT_ADDR, i); //Write addr + word=cep_readNcapture(IIR_OUT_DATA); //Read data mAct[i] = fixed_to_float(word); } } diff --git a/cosim/drivers/cep_tests/cep_iir.h b/cosim/drivers/cep_tests/cep_iir.h index 12d2b06..2d867d1 100644 --- a/cosim/drivers/cep_tests/cep_iir.h +++ b/cosim/drivers/cep_tests/cep_iir.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_iir.cc/h // Program: Common Evaluation Platform (CEP) @@ -28,7 +28,7 @@ class cep_iir : public cep_crypto { public: // // constructors // - cep_iir(int seed, int verbose); + cep_iir(int coreIndex, int seed, int verbose); cep_iir() { } ~cep_iir(); @@ -37,7 +37,7 @@ class cep_iir : public cep_crypto { int RunIirTest(int maxLoop); - protected: +protected: fixp32_8 float_to_fixed(double input); double fixed_to_float(fixp32_8 input); void adjust_float(double *inout, int length); diff --git a/cosim/drivers/cep_tests/cep_md5.cc b/cosim/drivers/cep_tests/cep_md5.cc index 7e04b39..d050049 100644 --- a/cosim/drivers/cep_tests/cep_md5.cc +++ b/cosim/drivers/cep_tests/cep_md5.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_md5.cc/h // Program: Common Evaluation Platform (CEP) @@ -27,8 +27,8 @@ // // -cep_md5::cep_md5(int seed, int verbose) { - init(); +cep_md5::cep_md5(int coreIndex, int seed, int verbose) { + init(coreIndex); SetBlockSize(64); // 64bytes bytes SetSeed(seed); SetVerbose(verbose); @@ -71,7 +71,7 @@ void cep_md5::LoadInText(uint8_t *buf) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)buf[i*8 + j]; } - cep_writeNcapture(MD5_BASE_K, MD5_MSG_BASE + (i * BYTES_PER_WORD), word); + cep_writeNcapture(MD5_MSG_BASE + (i * BYTES_PER_WORD), word); } #else // NOT the same as SHA256, it is byte flipped @@ -81,32 +81,32 @@ void cep_md5::LoadInText(uint8_t *buf) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)buf[i*8 + (7-j)]; } - cep_writeNcapture(MD5_BASE_K, MD5_MSG_BASE + (i * BYTES_PER_WORD), word); + cep_writeNcapture(MD5_MSG_BASE + (i * BYTES_PER_WORD), word); } #endif } void cep_md5::Clear(void) { if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - cep_writeNcapture(MD5_BASE_K, MD5_RST, 0x2); // bit[1]=init , bit[0]=rst - cep_writeNcapture(MD5_BASE_K, MD5_RST, 0x0); + cep_writeNcapture(MD5_RST, 0x2); // bit[1]=init , bit[0]=rst + cep_writeNcapture(MD5_RST, 0x0); waitTilReady(100); } void cep_md5::Start(void) { if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - cep_writeNcapture(MD5_BASE_K, MD5_MSG_IN_VALID, 0x1); - cep_writeNcapture(MD5_BASE_K, MD5_MSG_IN_VALID, 0x0); + cep_writeNcapture(MD5_MSG_IN_VALID, 0x1); + cep_writeNcapture(MD5_MSG_IN_VALID, 0x0); } int cep_md5::waitTilReady(int maxTO) { #if 1 if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(MD5_BASE_K, MD5_READY, 1, maxTO); + return cep_readNspin(MD5_READY, 1, maxTO); #else if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } while (maxTO > 0) { - if (cep_readNcapture(MD5_BASE_K, MD5_READY)) break; + if (cep_readNcapture(MD5_READY)) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -116,10 +116,10 @@ int cep_md5::waitTilReady(int maxTO) { int cep_md5::waitTilDone(int maxTO) { #if 1 if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(MD5_BASE_K, MD5_MSG_OUT_VALID, 1, maxTO); + return cep_readNspin(MD5_MSG_OUT_VALID, 1, maxTO); #else while (maxTO > 0) { - if (cep_readNcapture(MD5_BASE_K, MD5_MSG_OUT_VALID)) break; + if (cep_readNcapture(MD5_MSG_OUT_VALID)) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -131,14 +131,14 @@ void cep_md5::ReadOutText(void) { if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } #ifdef BIG_ENDIAN for(int i = 0; i < 2; i++) { // 128bits - word = cep_readNcapture(MD5_BASE_K, MD5_HASH_BASE + (i*8)); + word = cep_readNcapture(MD5_HASH_BASE + (i*8)); for (int j=0;j<8;j++) { mHwCp[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; } } #else for(int i = 0; i < 2; i++) { // 128bits - word = cep_readNcapture(MD5_BASE_K, MD5_HASH_BASE + (8*(1-i))); + word = cep_readNcapture(MD5_HASH_BASE + (8*(1-i))); for (int j=0;j<8;j++) { mHwCp[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; } diff --git a/cosim/drivers/cep_tests/cep_md5.h b/cosim/drivers/cep_tests/cep_md5.h index 358ed38..39e44c4 100644 --- a/cosim/drivers/cep_tests/cep_md5.h +++ b/cosim/drivers/cep_tests/cep_md5.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_md5.cc/h // Program: Common Evaluation Platform (CEP) @@ -21,13 +21,13 @@ class cep_md5 : public cep_crypto { public: // // constructors // - cep_md5(int seed, int verbose); + cep_md5(int coreIndex, int seed, int verbose); ~cep_md5(); // int RunMd5Test(int maxLoop); - protected: +protected: // int prepare_md5_key_N_text ( diff --git a/cosim/drivers/cep_tests/cep_riscv.cc b/cosim/drivers/cep_tests/cep_riscv.cc index 4eda7d5..134233a 100644 --- a/cosim/drivers/cep_tests/cep_riscv.cc +++ b/cosim/drivers/cep_tests/cep_riscv.cc @@ -1,6 +1,6 @@ // ************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/cep_tests/cep_riscv.h b/cosim/drivers/cep_tests/cep_riscv.h index 3c1239e..c1a2882 100644 --- a/cosim/drivers/cep_tests/cep_riscv.h +++ b/cosim/drivers/cep_tests/cep_riscv.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/cep_tests/cep_rsa.cc b/cosim/drivers/cep_tests/cep_rsa.cc index 6dc084f..7eacad1 100644 --- a/cosim/drivers/cep_tests/cep_rsa.cc +++ b/cosim/drivers/cep_tests/cep_rsa.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_rsa.cc/h // Program: Common Evaluation Platform (CEP) @@ -41,8 +41,8 @@ #define SetModSize SetBlockSize #define GetModSize GetBlockSize -cep_rsa::cep_rsa(int seed, int verbose) { - init(); +cep_rsa::cep_rsa(int coreIndex, int seed, int verbose) { + init(coreIndex); SetSeed(seed); SetVerbose(verbose); SetAddZeros(1); // 32bit become 32+32, etc.. @@ -85,8 +85,8 @@ void cep_rsa::LoadMessage(uint8_t *msg, int msgBytes, int wrEn) { int j=0; if (GetVerbose(2)) { LOGI("%s wCnt=%d\n",__FUNCTION__,wCnt); } // - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_MESSAGE_CTRL , 1<>32,&(msg[j])); j += 4; // issue for next - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_MESSAGE_CTRL , (1 << MESSAGE_MEM_API_CS)); - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_MESSAGE_CTRL , 0x0000000000000000); + cep_writeNcapture(RSA_ADDR_MESSAGE_CTRL , (1 << MESSAGE_MEM_API_CS)); + cep_writeNcapture(RSA_ADDR_MESSAGE_CTRL , 0x0000000000000000); } } } @@ -126,8 +126,8 @@ void cep_rsa::LoadModulus(uint8_t *modulus, int modulusBytes, int wrEn) { int j=0; if (GetVerbose(2)) { LOGI("%s wCnt=%d\n",__FUNCTION__,wCnt); } // - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_MODULUS_CTRL , 1<>32,&(modulus[j])); j += 4; // issue for next - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_MODULUS_CTRL , (1 << MODULUS_MEM_API_CS)); - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_MODULUS_CTRL , 0x0000000000000000); + cep_writeNcapture(RSA_ADDR_MODULUS_CTRL , (1 << MODULUS_MEM_API_CS)); + cep_writeNcapture(RSA_ADDR_MODULUS_CTRL , 0x0000000000000000); } } } @@ -165,8 +165,8 @@ void cep_rsa::LoadExponent(uint8_t *exponent, int exponentBytes, int wrEn) { int j=0; if (GetVerbose(2)) { LOGI("%s wCnt=%d\n",__FUNCTION__,wCnt); } // - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_EXPONENT_CTRL , 1<>32,&(exponent[j])); j += 4; // next - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_EXPONENT_CTRL , (1 << EXPONENT_MEM_API_CS)); - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_EXPONENT_CTRL , 0x0000000000000000); + cep_writeNcapture(RSA_ADDR_EXPONENT_CTRL , (1 << EXPONENT_MEM_API_CS)); + cep_writeNcapture(RSA_ADDR_EXPONENT_CTRL , 0x0000000000000000); } } } @@ -207,14 +207,14 @@ void cep_rsa::ReadResult(uint8_t *result, int resultBytes) { int j=0; if (GetVerbose(2)) { LOGI("%s: wCnt=%d\n",__FUNCTION__,wCnt); } // - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_RESULT_CTRL , 1< 0))) { Word2Byte(word,&(result[j])); // @@ -225,13 +225,13 @@ void cep_rsa::ReadResult(uint8_t *result, int resultBytes) { void cep_rsa::Start(void) { if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); } - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_CTRL , 0x0000000000000002); - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_CTRL , 0x0000000000000000); + cep_writeNcapture(RSA_ADDR_CTRL , 0x0000000000000002); + cep_writeNcapture(RSA_ADDR_CTRL , 0x0000000000000000); } int cep_rsa::waitTilDone(int maxTO) { if (GetVerbose(2)) { LOGI("%s: to=%d\n",__FUNCTION__,maxTO); } - return cep_readNspin(RSA_BASE_K, RSA_ADDR_STATUS, 1, maxTO); + return cep_readNspin(RSA_ADDR_STATUS, 1, maxTO); } // Use Crypto++ to compute c = m^e mod n; @@ -436,10 +436,10 @@ int cep_rsa::RunRsaMemTest(int memMask, int sizeInBytes) { // // Just for coverage // - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_EXPONENT_LENGTH , -1); - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_EXPONENT_LENGTH , 0); - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_MODULUS_LENGTH , -1); - cep_writeNcapture(RSA_BASE_K, RSA_ADDR_MODULUS_LENGTH , 0); + cep_writeNcapture(RSA_ADDR_EXPONENT_LENGTH , -1); + cep_writeNcapture(RSA_ADDR_EXPONENT_LENGTH , 0); + cep_writeNcapture(RSA_ADDR_MODULUS_LENGTH , -1); + cep_writeNcapture(RSA_ADDR_MODULUS_LENGTH , 0); // // Modulus memory // diff --git a/cosim/drivers/cep_tests/cep_rsa.h b/cosim/drivers/cep_tests/cep_rsa.h index 3010c83..7a2d230 100644 --- a/cosim/drivers/cep_tests/cep_rsa.h +++ b/cosim/drivers/cep_tests/cep_rsa.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_rsa.cc/h // Program: Common Evaluation Platform (CEP) @@ -40,12 +40,11 @@ class cep_rsa : public cep_crypto { public: // // constructors // - cep_rsa(int seed, int verbose); + cep_rsa(int coreIndex, int seed, int verbose); ~cep_rsa(); int RunRsaTest(int maxLoop, int maxBytes); int RunRsaMemTest(int memMask, int sizeInBytes); - protected: // int GetAddZeros(void) { return mAddZeros; } diff --git a/cosim/drivers/cep_tests/cep_sha256.cc b/cosim/drivers/cep_tests/cep_sha256.cc index 8be8e39..12e3b19 100644 --- a/cosim/drivers/cep_tests/cep_sha256.cc +++ b/cosim/drivers/cep_tests/cep_sha256.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_sha256.cc/h // Program: Common Evaluation Platform (CEP) @@ -26,8 +26,8 @@ // // -cep_sha256::cep_sha256(int seed, int verbose) { - init(); +cep_sha256::cep_sha256(int coreIndex, int seed, int verbose) { + init(coreIndex); SetBlockSize(64); // 64 bytes SetSeed(seed); @@ -70,7 +70,7 @@ void cep_sha256::LoadInText(uint8_t *buf) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)buf[i*8 + j]; } - cep_writeNcapture(SHA256_BASE_K, SHA256_MSG_BASE + (i * BYTES_PER_WORD), word); + cep_writeNcapture(SHA256_MSG_BASE + (i * BYTES_PER_WORD), word); } #else for(int i = 0; i < GetBlockSize()/8; i++) { // 8-bytes/word @@ -78,7 +78,7 @@ void cep_sha256::LoadInText(uint8_t *buf) { for (int j=0;j<8;j++) { word = (word << 8) | (uint64_t)buf[i*8 + j]; } - cep_writeNcapture(SHA256_BASE_K, SHA256_MSG_BASE + ((7-i) * BYTES_PER_WORD), word); + cep_writeNcapture(SHA256_MSG_BASE + ((7-i) * BYTES_PER_WORD), word); } #endif } @@ -86,21 +86,21 @@ void cep_sha256::LoadInText(uint8_t *buf) { void cep_sha256::Start(int firstTime) { if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } if (firstTime) { - cep_writeNcapture(SHA256_BASE_K, SHA256_NEXT_INIT, 0x0000000000000002); + cep_writeNcapture(SHA256_NEXT_INIT, 0x0000000000000002); } else { - cep_writeNcapture(SHA256_BASE_K, SHA256_NEXT_INIT, 0x0000000000000004); + cep_writeNcapture(SHA256_NEXT_INIT, 0x0000000000000004); } - cep_writeNcapture(SHA256_BASE_K, SHA256_NEXT_INIT, 0x0000000000000000); + cep_writeNcapture(SHA256_NEXT_INIT, 0x0000000000000000); } int cep_sha256::waitTilReady(int maxTO) { #if 1 if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(SHA256_BASE_K, SHA256_READY, 1, maxTO); + return cep_readNspin(SHA256_READY, 1, maxTO); #else if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } while (maxTO > 0) { - if (cep_readNcapture(SHA256_BASE_K, SHA256_READY)) break; + if (cep_readNcapture(SHA256_READY)) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -110,11 +110,11 @@ int cep_sha256::waitTilReady(int maxTO) { int cep_sha256::waitTilDone(int maxTO) { #if 1 if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } - return cep_readNspin(SHA256_BASE_K, SHA256_HASH_DONE, 1, maxTO); + return cep_readNspin(SHA256_HASH_DONE, 1, maxTO); #else if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } while (maxTO > 0) { - if (cep_readNcapture(SHA256_BASE_K, SHA256_HASH_DONE)) break; + if (cep_readNcapture(SHA256_HASH_DONE)) break; maxTO--; }; return (maxTO <= 0) ? 1 : 0; @@ -126,14 +126,14 @@ void cep_sha256::ReadOutText(void) { if (GetVerbose()) { LOGI("%s\n",__FUNCTION__); } #ifdef BIG_ENDIAN for(int i = 0; i < 4; i++) { // 256-bits=32 - word = cep_readNcapture(SHA256_BASE_K, SHA256_HASH_BASE + (i*8)); + word = cep_readNcapture(SHA256_HASH_BASE + (i*8)); for (int j=0;j<8;j++) { mHwCp[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; } } #else for(int i = 0; i < 4; i++) { // 256-bits=32 - word = cep_readNcapture(SHA256_BASE_K, SHA256_HASH_BASE + (8*(3-i))); + word = cep_readNcapture(SHA256_HASH_BASE + (8*(3-i))); for (int j=0;j<8;j++) { mHwCp[i*8 +j]= (word >> (8*(7-j)) ) & 0xff; } diff --git a/cosim/drivers/cep_tests/cep_sha256.h b/cosim/drivers/cep_tests/cep_sha256.h index d918535..60af7c2 100644 --- a/cosim/drivers/cep_tests/cep_sha256.h +++ b/cosim/drivers/cep_tests/cep_sha256.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_sha256.cc/h // Program: Common Evaluation Platform (CEP) @@ -21,13 +21,13 @@ class cep_sha256 : public cep_crypto { public: // // constructors // - cep_sha256(int seed, int verbose); + cep_sha256(int coreIndex, int seed, int verbose); ~cep_sha256(); // int RunSha256Test(int maxLoop); - protected: +protected: // int prepare_sha256_key_N_text ( diff --git a/cosim/drivers/cep_tests/cep_srot.cc b/cosim/drivers/cep_tests/cep_srot.cc index 337820d..9383a81 100644 --- a/cosim/drivers/cep_tests/cep_srot.cc +++ b/cosim/drivers/cep_tests/cep_srot.cc @@ -1,11 +1,17 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // -// File Name: cep_srot.cc/h -// Program: Common Evaluation Platform (CEP) -// Description: Functions / Test for the CEP Surrogate Root of Trust -// Notes: +// File Name: cep_srot.cc/h +// Program: Common Evaluation Platform (CEP) +// Description: Functions / Test for the CEP Surrogate Root of Trust +// Notes: In the constructor function below, there are two +// indicies (coreIndex & statusIndex). These are +// references to the ipCores data structure +// (cepregression.cc/h). coreIndex for the surrogate +// root of trust and statusIndex is for the +// CEP Registers. +// //************************************************************************ #if defined(BARE_MODE) @@ -25,11 +31,14 @@ #include "cep_adrMap.h" #include "cepregression.h" -#define IS_CRYPTO_ENABLED(c) ((1 << c ## _BASE_K) & GetCryptoMask()) +#define IS_ON(c) ((1 << c) & GetCoreMask()) -// -cep_srot::cep_srot(int verbose) { - init(); +cep_srot::cep_srot(int coreIndex, int statusIndex, int verbose) { + + init(coreIndex); + + + mStatusIndex = statusIndex; // Default Timeout Parameter maxTO = 5000; @@ -39,11 +48,8 @@ cep_srot::cep_srot(int verbose) { // Set the default CPU Active Mask SetCpuActiveMask(0xf); - SetCryptoMask(-1); // all present - + // Initialize some of the core datastructures - init_srot(); - init_cepregs(); mInvertKey = 0; mInvertMask = 0x5555555555555555LLU; @@ -65,7 +71,7 @@ int cep_srot::InitKeyIndexRAM (void) LOGI("\n"); } for (int i = 0; i < (int)SROT_KEYINDEXRAM_SIZE; i++) { - cep_writeNcapture(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + (i*8), 0); + cep_writeNcapture(SROT_KEYINDEXRAM_ADDR + (i*8), 0); } return errCnt; @@ -80,7 +86,7 @@ int cep_srot::InitKeyIndexRAM (void) // ------------------------------------------------------------------------------------------------------------ // Parameter list: // KeyIndex - Selected Index into the Key Index RAM -// CoreIndex - Which core is this key for? The XXXX_BASE_K constants in CEP.h should be used +// CoreIndex - Which core is this key for? // LowPointer - The location of the first key word in the KeyRAM // HighPointer - The location of the last key word in the KeyRAM // Key - Contains the actual key bits (length = High_Pointer - Low_Pointer + 1) @@ -106,7 +112,7 @@ int cep_srot::LoadLLKIKey (uint8_t KeyIndex, uint8_t CoreIndex, uint16_t LowPoin } for (int i = 0; i < (HighPointer - LowPointer + 1); i++) { // not invert all the bits, just the odd bits, IIR will give the same results if flip all bits - cep_writeNcapture(SROT_BASE_K, SROT_KEYRAM_ADDR + LowPointer*8 + (i*8), mInvertKey ? (Key[i] ^ mInvertMask) : Key[i]); + cep_writeNcapture(SROT_KEYRAM_ADDR + LowPointer*8 + (i*8), mInvertKey ? (Key[i] ^ mInvertMask) : Key[i]); } // Load a valid key index @@ -117,7 +123,7 @@ int cep_srot::LoadLLKIKey (uint8_t KeyIndex, uint8_t CoreIndex, uint16_t LowPoin LOGI("----------------------------------------------------------------------------\n"); LOGI("\n"); } - cep_writeNcapture(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + KeyIndex*8, key_index_pack( + cep_writeNcapture(SROT_KEYINDEXRAM_ADDR + KeyIndex*8, key_index_pack( LowPointer, // low pointer HighPointer, // high pointer CoreIndex, // core index @@ -148,7 +154,7 @@ int cep_srot::SetOperationalMode (void) LOGI("----------------------------------------------------------------------------\n"); LOGI("\n"); } - cep_writeNcapture(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_MODEBIT0_MASK | SROT_CTRLSTS_MODEBIT1_MASK); + cep_writeNcapture(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_MODEBIT0_MASK | SROT_CTRLSTS_MODEBIT1_MASK); return errCnt; @@ -163,8 +169,8 @@ int cep_srot::SetOperationalMode (void) int cep_srot::EnableLLKI (uint8_t KeyIndex) { - int errCnt = 0; - uint8_t status = 0; + int errCnt = 0; + uint8_t status = 0; // if (GetVerbose(2)) { @@ -177,7 +183,7 @@ int cep_srot::EnableLLKI (uint8_t KeyIndex) } // Write a word to the LLKI C2 Send FIFO - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -185,10 +191,10 @@ int cep_srot::EnableLLKI (uint8_t KeyIndex) 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Read and check the response - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); CHECK_RESPONSE(status, LLKI_STATUS_GOOD, GetVerbose()); // Return the error count @@ -205,8 +211,8 @@ int cep_srot::EnableLLKI (uint8_t KeyIndex) int cep_srot::DisableLLKI (uint8_t KeyIndex) { - int errCnt = 0; - uint8_t status = 0; + int errCnt = 0; + uint8_t status = 0; if (GetVerbose(2)) { LOGI("\n"); @@ -217,7 +223,7 @@ int cep_srot::DisableLLKI (uint8_t KeyIndex) LOGI("\n"); } // Write a word to the LLKI C2 Send FIFO - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2CLEARKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -225,10 +231,10 @@ int cep_srot::DisableLLKI (uint8_t KeyIndex) 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Read and check the response - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); CHECK_RESPONSE(status, LLKI_STATUS_GOOD, GetVerbose()); // Return the error count @@ -239,213 +245,107 @@ int cep_srot::DisableLLKI (uint8_t KeyIndex) - // ------------------------------------------------------------------------------------------------------------ -// The following method will set a bit in the cep_core0_status register in order to indicate to the other -// cores that the LLKI operations have been completed. -// -// For core0, the method will set the appropriate bit in the cep_core0_status register -// For the other cores, this function will poll the status bit continuously until it is set +// Public Method for setting up the LLKI // +// Every call to this method will begin by initializing the SRoT's KeyIndexRAM, which will effectively "erase" +// all existing SRoT keys // ------------------------------------------------------------------------------------------------------------ -int cep_srot::LLKIInitComplete (int cpuId) -{ - - int errCnt = 0; - int maxTO = 50000; // Maximum number of "counts" to try before continuing +int cep_srot::LLKI_Setup(int cpuId) { - - // If I am core 0 - if (cpuId == 0) { + int errCnt = 0; - if (GetVerbose()) { - LOGI("\n"); - LOGI("----------------------------------------------------------------------------\n"); - LOGI("%s: Core 0 setting interlock bit... \n",__FUNCTION__); - LOGI("----------------------------------------------------------------------------\n"); - LOGI("\n"); + // + // pick the first LSB in cpuActiveMask as master + // + int iAMmaster = 0; + for (int i = 0; i < 4; i++) { + if (((1 << i) & GetCpuActiveMask())) { // found the first LSB=1 bit + if (i == cpuId) { + iAMmaster = 1; + } + break; } + } - // Write to the core0 status register indicating that the LLKI operations are complete - cep_writeNcapture(CEP_VERSION_REG_K, cep_core0_status, 0x0000000000000001); - - } else { - - if (GetVerbose()) { - LOGI("\n"); - LOGI("----------------------------------------------------------------------------\n"); - LOGI("%s: Core %d waiting for interlock bit... \n", __FUNCTION__, cpuId); - LOGI("----------------------------------------------------------------------------\n"); - LOGI("\n"); + // + // Only one core can perform LLKI operations + // + if (iAMmaster) { + +#ifdef SIM_ENV_ONLY + if (mSrotFlag) { + LOGI("%s: cpu#%d: enable SROT vector capture\n",__FUNCTION__,cpuId); + DUT_WRITE_DVT(DVTF_SROT_START_CAPTURE_BIT, DVTF_SROT_START_CAPTURE_BIT , 1); } - - // Wait for the interlock bit to be set (and capture if a timeout occurs) - errCnt += cep_readNspin(CEP_VERSION_REG_K, cep_core0_status, 0x0000000000000001, 0x0000000000000001, maxTO); - +#endif + if (GetVerbose()) { - LOGI("\n"); - LOGI("----------------------------------------------------------------------------\n"); - LOGI("%s: Core %d interlock bit received... \n", __FUNCTION__, cpuId); - LOGI("----------------------------------------------------------------------------\n"); - LOGI("\n"); + LOGI("%s: cpu#%d is the master. mask=0x%x\n",__FUNCTION__,cpuId,GetCpuActiveMask()); } - } // else if (cpuId == 0) - return errCnt; - -} // cep_srot::LLKIInitComplete -// ------------------------------------------------------------------------------------------------------------ - - - - -// ------------------------------------------------------------------------------------------------------------ -// Simple method that will clear the cep_core0_status register if this is cpuId 0 -// ------------------------------------------------------------------------------------------------------------ -int cep_srot::LLKIClearComplete (int cpuId) -{ - - int errCnt = 0; - - // If I am core 0 - if (cpuId == 0) { - - if (GetVerbose()) { - LOGI("\n"); - LOGI("----------------------------------------------------------------------------\n"); - LOGI("%s: Core 0 clearing interlock bit... \n",__FUNCTION__); - LOGI("----------------------------------------------------------------------------\n"); - LOGI("\n"); - } - - // Write to the core0 status register indicating that the LLKI operations are complete - cep_writeNcapture(CEP_VERSION_REG_K, cep_core0_status, 0); - - return errCnt; - - } else { + - return errCnt; + // + // Initialize the LLKI Key Index RAM to all zeroes (thus effectively deleting any existing keys) + // + InitKeyIndexRAM(); + + // + // Loop through all the LLKI cores and load keys if the following conditions are met: + // 1) The core is enabled as define in cep_core_info (CEP.h) + // 2) The current CoreMask has selected the current core + // + // As a single index is being used to access both the cep_core_info and KEY_DATA arrays, + // the cores that use keys must be lower justified in cep_core_info array + for (int coreIndex = 0; coreIndex < CEP_LLKI_CORES; coreIndex ++) { + cep_core_info_t core = cep_core_info[coreIndex]; + cep_key_info_t key = KEY_DATA[coreIndex]; - } // else if (cpuId == 0) + core_type_t coreType = core.type; + + if (IS_ON(coreIndex) && core.enabled) { + // Load the appropriate key + LoadLLKIKey(coreIndex, // KeyIndex (address in the KeyIndexRAM) + coreIndex, // CoreIndex (defines the core for which this key is destined for. Corresponds + // to the core indecies defined in DevKitConfigs.scala) + key.lowPointer, + key.highPointer, + key.keyData, + key.invertType); -} // cep_srot::LLKIInitComplete -// ------------------------------------------------------------------------------------------------------------ + DisableLLKI(coreIndex); + EnableLLKI(coreIndex); + } // if (IS_ON(keyIndex) && core.enabled) -// ------------------------------------------------------------------------------------------------------------ -// Public Method for setting up the LLKI -// ------------------------------------------------------------------------------------------------------------ -int cep_srot::LLKI_Setup(int cpuId) { - int errCnt = 0; - - // pick the first LSB in cpuActiveMask as master - // - int iAMmaster = 0; - for (int i = 0; i < 4; i++) { - if (((1 << i) & GetCpuActiveMask())) { // found the first LSB=1 bit - if (i == cpuId) { - iAMmaster = 1; - } - break; - } - } - - // - // Master stuffs - // - if (iAMmaster) { - -#ifdef SIM_ENV_ONLY - if (mSrotFlag) { - LOGI("%s: cpu#%d: enable SROT vector capture\n",__FUNCTION__,cpuId); - DUT_WRITE_DVT(DVTF_SROT_START_CAPTURE_BIT, DVTF_SROT_START_CAPTURE_BIT , 1); - } -#endif + } // for (int coreIndex = 0; coreIndex < CEP_LLKI_CORES; coreIndex ++) - if (GetVerbose()) { - LOGI("%s: cpu#%d is the master. mask=0x%x\n",__FUNCTION__,cpuId,GetCpuActiveMask()); - } - // - // Initiate the LLKI for all cores - // For multi-core tests, core0 will be responsible for the following: - // - Initializing the LLKI Key Index RAM for ALL KEYS - // - Loading all keys into the SRoT - // - Enabling the LLKI for all cores - - // - // Initialize the LLKI - // - InitKeyIndexRAM(); + // Write to the core0 status register indicating that the LLKI operations are complete + cep_writeNcapture(mStatusIndex, cep_core0_status, CEP_OK2RUN_SIGNATURE); - // Load the all the keys (Core indicies MUST correspond - // to those identified in the LLKI_CORE_INDEX_ARRAY as - // listed in llki_pkg.sv - // tony duong 02/26/21: - /* for the sake of easy testing, use keyIndex same as core Index for now */ - if (IS_CRYPTO_ENABLED(AES)) { - LoadLLKIKey(AES_BASE_K , AES_BASE_K, 0, 1, AES_MOCK_TSS_KEY, INVERT_ALL_BITS); - DisableLLKI(AES_BASE_K ); EnableLLKI(AES_BASE_K ); - } - if (IS_CRYPTO_ENABLED(DES3)) { - LoadLLKIKey(DES3_BASE_K , DES3_BASE_K, 2, 2, DES3_MOCK_TSS_KEY, INVERT_ALL_BITS); - DisableLLKI(DES3_BASE_K ); EnableLLKI(DES3_BASE_K ); - } - // NOTE: DFT/IDFT: they go together - if (IS_CRYPTO_ENABLED(DFT) || IS_CRYPTO_ENABLED(IDFT)) { - LoadLLKIKey(DFT_BASE_K , DFT_BASE_K, 3, 3, DFT_MOCK_TSS_KEY, INVERT_ALL_BITS); - DisableLLKI(DFT_BASE_K ); EnableLLKI(DFT_BASE_K ); - // - LoadLLKIKey(IDFT_BASE_K , IDFT_BASE_K, 10, 10, IDFT_MOCK_TSS_KEY, INVERT_ALL_BITS); - DisableLLKI(IDFT_BASE_K ); EnableLLKI(IDFT_BASE_K ); - } - if (IS_CRYPTO_ENABLED(FIR)) { - LoadLLKIKey(FIR_BASE_K , FIR_BASE_K, 4, 4, FIR_MOCK_TSS_KEY, INVERT_ALTERNATE); - DisableLLKI(FIR_BASE_K ); EnableLLKI(FIR_BASE_K ); - } - if (IS_CRYPTO_ENABLED(GPS)) { - LoadLLKIKey(GPS_BASE_K , GPS_BASE_K, 5, 9, GPS_MOCK_TSS_KEY, INVERT_ALL_BITS); - DisableLLKI(GPS_BASE_K ); EnableLLKI(GPS_BASE_K ); - } - if (IS_CRYPTO_ENABLED(IIR)) { - LoadLLKIKey(IIR_BASE_K , IIR_BASE_K, 11, 11, IIR_MOCK_TSS_KEY, INVERT_ALTERNATE); // can't use invert_all_bits - DisableLLKI(IIR_BASE_K ); EnableLLKI(IIR_BASE_K ); - } - if (IS_CRYPTO_ENABLED(MD5)) { - LoadLLKIKey(MD5_BASE_K , MD5_BASE_K, 12, 19, MD5_MOCK_TSS_KEY, INVERT_ALL_BITS); - DisableLLKI(MD5_BASE_K ); EnableLLKI(MD5_BASE_K ); - } - if (IS_CRYPTO_ENABLED(RSA)) { - LoadLLKIKey(RSA_BASE_K , RSA_BASE_K, 20, 20, RSA_MOCK_TSS_KEY, INVERT_ALL_BITS); - DisableLLKI(RSA_BASE_K ); EnableLLKI(RSA_BASE_K ); - } - if (IS_CRYPTO_ENABLED(SHA256)) { - LoadLLKIKey(SHA256_BASE_K , SHA256_BASE_K, 21, 28, SHA256_MOCK_TSS_KEY, INVERT_ALL_BITS); - DisableLLKI(SHA256_BASE_K ); EnableLLKI(SHA256_BASE_K ); - } - - // Write to the core0 status register indicating that the LLKI operations are complete - cep_writeNcapture(CEP_VERSION_REG_K, cep_core0_status, CEP_OK2RUN_SIGNATURE); - // - // Done!! - // + // + // Done!! + // #ifdef SIM_ENV_ONLY - if (mSrotFlag) { - DUT_WRITE_DVT(DVTF_SROT_STOP_CAPTURE_BIT, DVTF_SROT_STOP_CAPTURE_BIT , 1); - } -#endif - - } else { - if (GetVerbose()) { - LOGI("%s: cpu#%d will be the slave. mask=0x%x\n",__FUNCTION__,cpuId,GetCpuActiveMask()); - } - errCnt += cep_readNspin(CEP_VERSION_REG_K, cep_core0_status, CEP_OK2RUN_SIGNATURE, 0xFFFFFFFF,maxTO); + if (mSrotFlag) { + DUT_WRITE_DVT(DVTF_SROT_STOP_CAPTURE_BIT, DVTF_SROT_STOP_CAPTURE_BIT , 1); } +#endif + + } else { // else if (iAMMaster) if (GetVerbose()) { - LOGI("%s: Done ...cpu=%d !!!\n",__FUNCTION__,cpuId); - } - // - return errCnt; + LOGI("%s: cpu#%d will be the slave. mask=0x%x\n",__FUNCTION__,cpuId,GetCpuActiveMask()); + } + errCnt += cep_readNspin(mStatusIndex, cep_core0_status, CEP_OK2RUN_SIGNATURE, 0xFFFFFFFF, maxTO); + + } // if (iAMmaster) { + + if (GetVerbose()) { + LOGI("%s: Done ...cpu=%d !!!\n",__FUNCTION__,cpuId); + } + + return errCnt; } // cep_srot::LLKI_Setup // ------------------------------------------------------------------------------------------------------------ @@ -455,8 +355,8 @@ int cep_srot::LLKI_Setup(int cpuId) { // ------------------------------------------------------------------------------------------------------------ int cep_srot::LLKI_ErrorTest(int cpuId) { - int errCnt = 0; - uint8_t status = 0; + int errCnt = 0; + uint8_t status = 0; // pick the first LSB in cpuActiveMask as master // @@ -488,29 +388,34 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { // -------------------------------------------------------------------------------------------------------- // Load some Key Indexes - Some good, some bad // -------------------------------------------------------------------------------------------------------- - errCnt += LoadLLKIKey(0 , AES_BASE_K, 0, 1, AES_MOCK_TSS_KEY, INVERT_ALL_BITS); - errCnt += LoadLLKIKey(1 , AES_BASE_K, 2, 6, GPS_MOCK_TSS_KEY, INVERT_ALL_BITS); + cep_key_info_t key0 = KEY_DATA[0]; + cep_key_info_t key1 = KEY_DATA[1]; + + errCnt += LoadLLKIKey(0 , 0, key0.lowPointer, key0.highPointer, key0.keyData, key0.invertType); + + // Bad core index + errCnt += LoadLLKIKey(1 , 0, key1.lowPointer, key1.highPointer, key1.keyData, key1.invertType); // Disable LLKI to clear it.. to make it independent of the states of the chip, tony d. errCnt += DisableLLKI (0); // Load a Key Index with a bad pointer pair (low pointer > high pointer) - cep_writeNcapture(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + 2*8, key_index_pack( + cep_writeNcapture(SROT_KEYINDEXRAM_ADDR + 2*8, key_index_pack( 2, // low pointer 1, // high pointer - AES_BASE_K, // core index + 0, // core index 0x1)); // Valid // Load a Key Index with a bad pointer pair (pointer exceeds key ram size) - cep_writeNcapture(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + 3*8, key_index_pack( + cep_writeNcapture(SROT_KEYINDEXRAM_ADDR + 3*8, key_index_pack( 0, // low pointer SROT_KEYRAM_SIZE, // high pointer - AES_BASE_K, // core index + 0, // core index 0x1)); // Valid // Load a Key Index with a bad core index - cep_writeNcapture(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + 4*8, key_index_pack( + cep_writeNcapture(SROT_KEYINDEXRAM_ADDR + 4*8, key_index_pack( 0, // low pointer 1, // high pointer 31, // core index @@ -525,7 +430,7 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { // -------------------------------------------------------------------------------------------------------- // Peform a redundant key load load for the AES Core // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -533,10 +438,10 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); CHECK_RESPONSE(status, LLKI_STATUS_KL_KEY_OVERWRITE, GetVerbose()); // -------------------------------------------------------------------------------------------------------- @@ -548,7 +453,7 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { // -------------------------------------------------------------------------------------------------------- // Load a bad length key into the AES Core // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -556,10 +461,10 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); CHECK_RESPONSE(status, LLKI_STATUS_KL_BAD_KEY_LEN, GetVerbose()); // -------------------------------------------------------------------------------------------------------- @@ -567,7 +472,7 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { // -------------------------------------------------------------------------------------------------------- // Send a BAD message ID // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( 0xFF, // Bad Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -575,10 +480,10 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); CHECK_RESPONSE(status, LLKI_STATUS_BAD_MSG_ID, GetVerbose()); // -------------------------------------------------------------------------------------------------------- @@ -586,7 +491,7 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { // -------------------------------------------------------------------------------------------------------- // Send a BAD message Length (all LLKI-C2 messages are length 1) // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0002, // BAD Message Length @@ -594,18 +499,18 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); - CHECK_RESPONSE(status, LLKI_STATUS_BAD_MSG_LEN, GetVerbose()); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); + CHECK_RESPONSE(status, LLKI_STATUS_BAD_MSG_LEN, GetVerbose()); // -------------------------------------------------------------------------------------------------------- // -------------------------------------------------------------------------------------------------------- // Stimulate the LLKI_STATUS_KEY_INDX_EXCEED error // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -613,18 +518,18 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); - CHECK_RESPONSE(status, LLKI_STATUS_KEY_INDEX_EXCEED, GetVerbose()); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); + CHECK_RESPONSE(status, LLKI_STATUS_KEY_INDEX_EXCEED, GetVerbose()); // -------------------------------------------------------------------------------------------------------- // -------------------------------------------------------------------------------------------------------- // Stimulate the LLKI_STATUS_KEY_INDEX_INVALID error // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -632,10 +537,10 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); CHECK_RESPONSE(status, LLKI_STATUS_KEY_INDEX_INVALID, GetVerbose()); // -------------------------------------------------------------------------------------------------------- @@ -643,7 +548,7 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { // -------------------------------------------------------------------------------------------------------- // Stimulate the LLKI_STATUS_BAD_POINTER_PAIR error (low > high) // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -651,18 +556,18 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); - CHECK_RESPONSE(status, LLKI_STATUS_BAD_POINTER_PAIR, GetVerbose()); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); + CHECK_RESPONSE(status, LLKI_STATUS_BAD_POINTER_PAIR, GetVerbose()); // -------------------------------------------------------------------------------------------------------- // -------------------------------------------------------------------------------------------------------- // Stimulate the LLKI_STATUS_BAD_POINTER_PAIR error (high pointer > Key RAM size) // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -670,10 +575,10 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); CHECK_RESPONSE(status, LLKI_STATUS_BAD_POINTER_PAIR, GetVerbose()); // -------------------------------------------------------------------------------------------------------- @@ -681,7 +586,7 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { // -------------------------------------------------------------------------------------------------------- // Stimulate the LLKI_STATUS_BAD_CORE_INDEX error // -------------------------------------------------------------------------------------------------------- - cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( + cep_writeNcapture(SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack( LLKI_MID_C2LOADKEYREQ, // Message ID 0x00, // Status (unused) 0x0001, // Message Length @@ -689,10 +594,10 @@ int cep_srot::LLKI_ErrorTest(int cpuId) { 0xDEADBE)); // rsvd1 // Poll the response waiting bit - cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); + cep_readNspin(SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100); // Compare expected and received responses - status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR)); + status = llkic2_extract_status(cep_readNcapture(SROT_LLKIC2_SENDRECV_ADDR)); CHECK_RESPONSE(status, LLKI_STATUS_BAD_CORE_INDEX, GetVerbose()); // -------------------------------------------------------------------------------------------------------- diff --git a/cosim/drivers/cep_tests/cep_srot.h b/cosim/drivers/cep_tests/cep_srot.h index bc95fbb..07e648a 100644 --- a/cosim/drivers/cep_tests/cep_srot.h +++ b/cosim/drivers/cep_tests/cep_srot.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cep_srot.cc/h // Program: Common Evaluation Platform (CEP) @@ -14,8 +14,11 @@ #include "stdint.h" #include "cep_crypto.h" -#define INVERT_ALL_BITS 1 -#define INVERT_ALTERNATE 2 + +// Include srot keys - must define invert modes first. +#include "cep_srot_keys.h" + + #define MAX_LLKI_KEY_SIZE 256 // Maximize size of an LLKI Key in units // of 64-bit words @@ -92,65 +95,6 @@ const uint8_t LLKI_KEYINDEX_VALID = 0x80; } \ } while (0) -// Mock TSS Keys -const uint64_t AES_MOCK_TSS_KEY[] = { - 0xAE53456789ABCDEF, - 0xFEDCBA9876543210 -}; - -const uint64_t DES3_MOCK_TSS_KEY[] = { - 0xDE53456789ABCDEF -}; - -const uint64_t SHA256_MOCK_TSS_KEY[] = { - 0x54A3456789ABCDEF, - 0xFEDCBA9876543210, - 0x0123456789ABCDEF, - 0xFEDCBA9876543210, - 0x0123456789ABCDEF, - 0xFEDCBA9876543210, - 0x0123456789ABCDEF, - 0xFEDCBA9876543210 -}; - -const uint64_t MD5_MOCK_TSS_KEY[] = { - 0x3D53456789ABCDEF, - 0xFEDCBA9876543210, - 0x0123456789ABCDEF, - 0xFEDCBA9876543210, - 0x0123456789ABCDEF, - 0xFEDCBA9876543210, - 0x0123456789ABCDEF, - 0xFEDCBA9876543210 -}; - -const uint64_t RSA_MOCK_TSS_KEY[] = { - 0x45A3456789ABCDEF -}; - -const uint64_t IIR_MOCK_TSS_KEY[] = { - 0x1143456789ABCDEF -}; - -const uint64_t FIR_MOCK_TSS_KEY[] = { - 0xF143456789ABCDEF -}; - -const uint64_t DFT_MOCK_TSS_KEY[] = { - 0xDF73456789ABCDEF -}; - -const uint64_t IDFT_MOCK_TSS_KEY[] = { - 0x1DF7456789ABCDEF -}; - -const uint64_t GPS_MOCK_TSS_KEY[] = { - 0x6953456789ABCDEF, - 0xFEDCBA9876543210, - 0x0123456789ABCDEF, - 0xFEDCBA9876543210, - 0x0123456789ABCDEF -}; // // CEP's SRoT @@ -161,7 +105,7 @@ class cep_srot : public cep_crypto { // Public methods // public: - cep_srot(int verbose); + cep_srot(int coreIndex, int statusIndex, int verbose); ~cep_srot() {}; // @@ -175,12 +119,12 @@ class cep_srot : public cep_crypto { void SetCpuActiveMask(int mask) { mCpuActiveMask = mask; } int GetCpuActiveMask(void) { return mCpuActiveMask; } - // - void SetCryptoMask(int mask) { mCryptoMask = mask; } - int GetCryptoMask(void) { return mCryptoMask; } - + void SetCoreMask(int mask) { mCoreMask = mask; } + int GetCoreMask(void) { return mCoreMask; } + // for negative testing void LLKI_invertKey(int enable) { mInvertKey = enable; } + // // Private methods // @@ -191,15 +135,11 @@ class cep_srot : public cep_crypto { // ------------------------------------------------------ int InitKeyIndexRAM (void); int LoadLLKIKey (uint8_t KeyIndex, uint8_t CoreIndex, uint16_t LowPointer, uint16_t HighPointer, const uint64_t *Key, int invertType); - int LLKIInitComplete (int cpuId); - int LLKIClearComplete (int cpuId); + int mStatusIndex; int mCpuActiveMask; int maxTO; - // - int mCryptoMask; - - // + int mCoreMask; int mInvertKey; uint64_t mInvertMask; }; diff --git a/cosim/drivers/cep_tests/cep_srot_keys.h b/cosim/drivers/cep_tests/cep_srot_keys.h new file mode 100644 index 0000000..f02ef57 --- /dev/null +++ b/cosim/drivers/cep_tests/cep_srot_keys.h @@ -0,0 +1,120 @@ +//************************************************************************ +// Copyright 2021 Massachusetts Institute of Technology +// SPDX License Identifier: BSD-2-Clause +// +// File Name: cep_srot.cc/h +// Program: Common Evaluation Platform (CEP) +// Description: SRoT class for CEP +// Notes: +//************************************************************************ + +#ifndef cep_srot_keys_H +#define cep_srot_keys_H + +#include "stdint.h" + +#define INVERT_ALL_BITS 1 +#define INVERT_ALTERNATE 2 + +// Include all core unlock keys here. +// Mock TSS keys are defined in llki_pkg.sv, and duplicated here. +const uint64_t AES_MOCK_TSS_KEY[] = { + 0xAE53456789ABCDEF, + 0xFEDCBA9876543210 +}; + +const uint64_t DES3_MOCK_TSS_KEY[] = { + 0xDE53456789ABCDEF +}; + +const uint64_t SHA256_MOCK_TSS_KEY[] = { + 0x54A3456789ABCDEF, + 0xFEDCBA9876543210, + 0x0123456789ABCDEF, + 0xFEDCBA9876543210, + 0x0123456789ABCDEF, + 0xFEDCBA9876543210, + 0x0123456789ABCDEF, + 0xFEDCBA9876543210 +}; + +const uint64_t MD5_MOCK_TSS_KEY[] = { + 0x3D53456789ABCDEF, + 0xFEDCBA9876543210, + 0x0123456789ABCDEF, + 0xFEDCBA9876543210, + 0x0123456789ABCDEF, + 0xFEDCBA9876543210, + 0x0123456789ABCDEF, + 0xFEDCBA9876543210 +}; + +const uint64_t RSA_MOCK_TSS_KEY[] = { + 0x45A3456789ABCDEF +}; + +const uint64_t IIR_MOCK_TSS_KEY[] = { + 0x1143456789ABCDEF +}; + +const uint64_t FIR_MOCK_TSS_KEY[] = { + 0xF143456789ABCDEF +}; + +const uint64_t DFT_MOCK_TSS_KEY[] = { + 0xDF73456789ABCDEF +}; + +const uint64_t IDFT_MOCK_TSS_KEY[] = { + 0x1DF7456789ABCDEF +}; + +const uint64_t GPS_MOCK_TSS_KEY[] = { + 0x6953456789ABCDEF, + 0xFEDCBA9876543210, + 0x0123456789ABCDEF, + 0xFEDCBA9876543210, + 0x0123456789ABCDEF +}; + +//Key info struct for unlocking LLKI cores. +typedef struct cep_key_info_t { + const char *name; // + const uint64_t *keyData; // Actual Key Bits + const uint64_t lowPointer; // Lower bound of where key will be loaded into KeyRAM + const uint64_t highPointer; // Upper bound of where key will be loaded into KeyRAM + const int invertType; // +} cep_key_info_t; + +// Number of LLKI cores for MacroMix to cover. +// Don't include SROT or CEP Version "cores", which must be the last ones in this list. +#define CEP_LLKI_CORES 16 + +// +// Array of keys and key lengths (number of 64 bit words) +// index in array == core index +// The order defined here **MUST** correspond to those +// defined in DevKitConfigs.scala +// +// KeyLength = High Pointer - Low Pointer + 1 +// +const cep_key_info_t KEY_DATA[CEP_LLKI_CORES] = { + {"AES", AES_MOCK_TSS_KEY, 0 , 1, INVERT_ALL_BITS}, + {"MD5", MD5_MOCK_TSS_KEY, 2 , 9, INVERT_ALL_BITS}, + {"SHA256.0", SHA256_MOCK_TSS_KEY, 10, 17, INVERT_ALL_BITS}, + {"SHA256.1", SHA256_MOCK_TSS_KEY, 18, 25, INVERT_ALL_BITS}, + {"SHA256.2", SHA256_MOCK_TSS_KEY, 26, 33, INVERT_ALL_BITS}, + {"SHA256.3", SHA256_MOCK_TSS_KEY, 34, 41, INVERT_ALL_BITS}, + {"RSA", RSA_MOCK_TSS_KEY, 42, 42, INVERT_ALL_BITS}, + {"DES3", DES3_MOCK_TSS_KEY, 43, 43, INVERT_ALL_BITS}, + {"DFT", DFT_MOCK_TSS_KEY, 44, 44, INVERT_ALL_BITS}, + {"IDFT", IDFT_MOCK_TSS_KEY, 45, 45, INVERT_ALL_BITS}, + {"FIR", FIR_MOCK_TSS_KEY, 46, 46, INVERT_ALTERNATE}, + {"IIR", IIR_MOCK_TSS_KEY, 47, 47, INVERT_ALTERNATE}, + {"GPS.0", GPS_MOCK_TSS_KEY, 48, 52, INVERT_ALL_BITS}, + {"GPS.1", GPS_MOCK_TSS_KEY, 53, 57, INVERT_ALL_BITS}, + {"GPS.2", GPS_MOCK_TSS_KEY, 58, 62, INVERT_ALL_BITS}, + {"GPS.3", GPS_MOCK_TSS_KEY, 63, 67, INVERT_ALL_BITS} +}; + +#endif diff --git a/cosim/drivers/cep_tests/cepregression.cc b/cosim/drivers/cep_tests/cepregression.cc index 2dd720a..3c9a1b3 100644 --- a/cosim/drivers/cep_tests/cepregression.cc +++ b/cosim/drivers/cep_tests/cepregression.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: cepregression.cc // Program: Common Evaluation Platform (CEP) @@ -76,10 +76,6 @@ extern int printf(const char *format, ...); // // // -#include "dft_input.h" -#include "fir_input.h" -#include "idft_input.h" -#include "iir_input.h" #include "CEP.h" @@ -169,131 +165,12 @@ void cep_write(int device, uint32_t pAddress, uint64_t pData) { #endif } -// =========== -// AES Test -// =========== -void init_aes(void) { -#if 1 // def BARE_MODE - ipCores[AES_BASE_K].address = cep_core_info[AES_BASE_K].base_address; - ipCores[AES_BASE_K].enabled = true; -#endif -} - -// =========== -// DES3 Test -// =========== -void init_des3(void) { -#if 1 // def BARE_MODE - ipCores[DES3_BASE_K].address = cep_core_info[DES3_BASE_K].base_address; - ipCores[DES3_BASE_K].enabled = true; -#endif - -} - -// =========== -// DFT Test -// =========== -void init_dft(void) { -#if 1 // def BARE_MODE - ipCores[DFT_BASE_K].address = cep_core_info[DFT_BASE_K].base_address; - ipCores[DFT_BASE_K].enabled = true; -#endif -} - -// =========== -// IDFT Test -// =========== -void init_idft(void) { -#if 1 // def BARE_MODE - ipCores[IDFT_BASE_K].address = cep_core_info[IDFT_BASE_K].base_address; - ipCores[IDFT_BASE_K].enabled = true; -#endif -} - -// =========== -// FIR Test -// =========== -void init_fir(void) -{ -#if 1 // def BARE_MODE - ipCores[FIR_BASE_K].address = cep_core_info[FIR_BASE_K].base_address; - ipCores[FIR_BASE_K].enabled = true; -#endif -} - -// =========== -// IIR Test -// =========== -void init_iir(void) { -#if 1 // def BARE_MODE - ipCores[IIR_BASE_K].address = cep_core_info[IIR_BASE_K].base_address; - ipCores[IIR_BASE_K].enabled = true; -#endif -} - -// =========== -// GPS Test -// =========== -void init_gps(void) { -#if 1 // def BARE_MODE - ipCores[GPS_BASE_K].address = cep_core_info[GPS_BASE_K].base_address; - ipCores[GPS_BASE_K].enabled = true; -#endif -} - -// =========== -// MD5 Test -// =========== -void init_md5(void) { -#if 1 // def BARE_MODE - ipCores[MD5_BASE_K].address = cep_core_info[MD5_BASE_K].base_address; - ipCores[MD5_BASE_K].enabled = true; -#endif -} - -// =========== -// RSA Test -// =========== -void init_rsa(void) { -#if 1 // def BARE_MODE - ipCores[RSA_BASE_K].address = cep_core_info[RSA_BASE_K].base_address; - ipCores[RSA_BASE_K].enabled = true; -#endif -} - -// =========== -// SHA256 Test -// =========== -void init_sha256(void) { -#if 1 // def BARE_MODE - ipCores[SHA256_BASE_K].address = cep_core_info[SHA256_BASE_K].base_address; - ipCores[SHA256_BASE_K].enabled = true; -#endif -} - -// =========== -// SRoT Test -// =========== -void init_srot(void) { -#if 1 // def BARE_MODE - ipCores[SROT_BASE_K].address = cep_core_info[SROT_BASE_K].base_address; - ipCores[SROT_BASE_K].enabled = true; -#endif -} - -void init_cepregs(void) { -#if 1 // def BARE_MODE - ipCores[CEP_VERSION_REG_K].address = cep_core_info[CEP_VERSION_REG_K].base_address; - ipCores[CEP_VERSION_REG_K].enabled = true; -#endif -} - - //************************************************************************ // BEGIN: Config File Functions //************************************************************************ int __initConfigDone = 0; + // Initializes the ipCore_st structure for all cores void initConfig() { @@ -308,8 +185,8 @@ void initConfig() for (int i = 0; i < CEP_TOTAL_CORES; i++) { ipCores[i].address = cep_core_info[i].base_address; strncpy(ipCores[i].name, cep_core_info[i].name, strlen(cep_core_info[i].name)); - ipCores[i].fd = -1; - ipCores[i].mem = (unsigned char *)MAP_FAILED; + ipCores[i].fd = -1; // Used in linux diagnostics + ipCores[i].mem = (unsigned char *)MAP_FAILED; // Used in linux diagnostics ipCores[i].pagesize = pagesize; ipCores[i].enabled = cep_core_info[i].enabled; } diff --git a/cosim/drivers/cep_tests/cepregression.h b/cosim/drivers/cep_tests/cepregression.h index ab24373..e950887 100644 --- a/cosim/drivers/cep_tests/cepregression.h +++ b/cosim/drivers/cep_tests/cepregression.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -20,19 +20,7 @@ extern "C" { // // for use with cep_diag // - void initConfig(); - void init_md5(void) ; - void init_sha256(void) ; - void init_iir(void) ; - void init_fir(void) ; - void init_des3(void) ; - void init_gps(void) ; - void init_aes(void) ; - void init_dft(void) ; - void init_idft(void) ; - void init_rsa(void) ; - void init_srot(void); - void init_cepregs(void); + void initConfig(); // Initializes the ipCores datastructures uint64_t get_physical_adr(int device, uint32_t pAddress); // 32-bits diff --git a/cosim/drivers/cep_tests/dft_input.h b/cosim/drivers/cep_tests/dft_input.h deleted file mode 100644 index 1130f11..0000000 --- a/cosim/drivers/cep_tests/dft_input.h +++ /dev/null @@ -1,76 +0,0 @@ -//************************************************************************ -// Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT -// -// File Name: dft_input.h -// Program: Common Evaluation Platform (CEP) -// Description: Header file containing expected test vectors -//************************************************************************ - -uint64_t dft_exp_1[32][1]={ - {0x0fc01000faa304cf}, - {0xfd330246fe0b0165}, - {0xfe7d0100fec000b9}, - {0xfeeb008eff080070}, - {0xff25005aff390045}, - {0xff490035ff550025}, - {0xff60001eff6b0013}, - {0xff70000cff790004}, - {0xff800000ff87fff8}, - {0xff8cfff4ff93ffee}, - {0xff96ffeaff9bffe5}, - {0xff9fffe0ffa3ffdc}, - {0xffa6ffdaffabffd7}, - {0xffaeffd3ffb2ffcf}, - {0xffb3ffccffb8ffc9}, - {0xffbaffc5ffbdffc2}, - {0xffc0ffc0ffc3ffbd}, - {0xffc7ffbaffcbffb7}, - {0xffcdffb4ffd2ffb1}, - {0xffd5ffaeffd8ffa8}, - {0xffdbffa6ffdfffa3}, - {0xffe3ff9fffe9ff9b}, - {0xffecff96fff1ff93}, - {0xfff6ff8cfffbff86}, - {0x0000ff800007ff7c}, - {0x000eff740017ff6e}, - {0x0020ff62002bff59}, - {0x0039ff4c0049ff3c}, - {0x005aff260071ff11}, - {0x0092fef100c0fec9}, - {0x0101fe80016cfe19}, - {0x0248fd3b04d3fab4}}; - -uint64_t dft_exp_2[32][1]={ - {0x2fc03000faa304cf}, - {0xfd330246fe0b0165}, - {0xfe7d0100fec000b9}, - {0xfeeb008eff080070}, - {0xff25005aff390045}, - {0xff490035ff550025}, - {0xff60001eff6b0013}, - {0xff70000cff790004}, - {0xff800000ff87fff8}, - {0xff8cfff4ff93ffee}, - {0xff96ffeaff9bffe5}, - {0xff9fffe0ffa3ffdc}, - {0xffa6ffdaffabffd7}, - {0xffaeffd3ffb2ffcf}, - {0xffb3ffccffb8ffc9}, - {0xffbaffc5ffbdffc2}, - {0xffc0ffc0ffc3ffbd}, - {0xffc7ffbaffcbffb7}, - {0xffcdffb4ffd2ffb1}, - {0xffd5ffaeffd8ffa8}, - {0xffdbffa6ffdfffa3}, - {0xffe3ff9fffe9ff9b}, - {0xffecff96fff1ff93}, - {0xfff6ff8cfffbff86}, - {0x0000ff800007ff7c}, - {0x000eff740017ff6e}, - {0x0020ff62002bff59}, - {0x0039ff4c0049ff3c}, - {0x005aff260071ff11}, - {0x0092fef100c0fec9}, - {0x0101fe80016cfe19}, - {0x0248fd3b04d3fab4}}; \ No newline at end of file diff --git a/cosim/drivers/cep_tests/fir_input.h b/cosim/drivers/cep_tests/fir_input.h deleted file mode 100644 index 338bdd0..0000000 --- a/cosim/drivers/cep_tests/fir_input.h +++ /dev/null @@ -1,79 +0,0 @@ -//************************************************************************ -// Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT -// -// File Name: fir_input.h -// Program: Common Evaluation Platform (CEP) -// Description: Header file containing expected test vectors -//************************************************************************ -#if 1 -// was captured 6 samples too late, tony duong 04/22/20 -uint32_t fir_exp_1[32]={ - 0, - 0, - 0, - 0, - 1, - 4, -0x00000006, -0x0000000c, -0x00000012, -0x00000018, -0x0000001e, -0x00000025, -0x0000002c, -0x00000031, -0x00000039, -0x0000003f, -0x00000045, -0x0000004d, -0x00000052, -0x0000005a, -0x00000060, -0x00000067, -0x0000006c, -0x00000075, -0x0000007a, -0x00000081, -0x00000088, -0x0000008e, -0x00000095, -0x0000009b, -0x000000a2, -0x000000a8}; - -#else -uint32_t fir_exp_1[32]={ -0x00000006, -0x0000000c, -0x00000012, -0x00000018, -0x0000001e, -0x00000025, -0x0000002c, -0x00000031, -0x00000039, -0x0000003f, -0x00000045, -0x0000004d, -0x00000052, -0x0000005a, -0x00000060, -0x00000067, -0x0000006c, -0x00000075, -0x0000007a, -0x00000081, -0x00000088, -0x0000008e, -0x00000095, -0x0000009b, -0x000000a2, -0x000000a8, -0x000000af, -0x000000b4, -0x000000b1, -0x0000009f, -0x0000007a, -0x00000049}; -#endif diff --git a/cosim/drivers/cep_tests/idft_input.h b/cosim/drivers/cep_tests/idft_input.h deleted file mode 100644 index caf3cfb..0000000 --- a/cosim/drivers/cep_tests/idft_input.h +++ /dev/null @@ -1,76 +0,0 @@ -//************************************************************************ -// Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT -// -// File Name: idft_input.h -// Program: Common Evaluation Platform (CEP) -// Description: Header file containing expected test vectors -//************************************************************************ - -uint64_t idft_exp_1[32][1]={{0x0fc0100004defa9e}, - {0x024dfd310173fe06}, - {0x0103fe7c00c0feb9}, - {0x0094fee80078ff08}, - {0x005bff250047ff36}, - {0x0037ff450028ff51}, - {0x0020ff5e0016ff67}, - {0x0010ff6f0008ff76}, - {0x0000ff80fff8ff85}, - {0xfff4ff8bffefff8f}, - {0xffeaff94ffe5ff98}, - {0xffe0ff9dffddff9f}, - {0xffdaffa5ffd5ffa8}, - {0xffd3ffacffcfffaf}, - {0xffcdffb2ffc8ffb6}, - {0xffc6ffb8ffc2ffbc}, - {0xffc0ffc0ffbcffc4}, - {0xffb9ffc7ffb5ffca}, - {0xffb3ffceffaeffd1}, - {0xffacffd4ffa8ffd6}, - {0xffa5ffdbffa1ffe0}, - {0xff9dffe3ff98ffe9}, - {0xff94ffecff90fff1}, - {0xff8afff5ff84fffa}, - {0xff800000ff7a0009}, - {0xff720011ff690019}, - {0xff600022ff55002e}, - {0xff48003bff37004b}, - {0xff26005bff0f007a}, - {0xfeed0098fec100c7}, - {0xfe7f0104fe12017a}, - {0xfd380250faae04e4}}; - -uint64_t idft_exp_2[32][1]={{0x2fc0300004defa9e}, - {0x024dfd310173fe06}, - {0x0103fe7c00c0feb9}, - {0x0094fee80078ff08}, - {0x005bff250047ff36}, - {0x0037ff450028ff51}, - {0x0020ff5e0016ff67}, - {0x0010ff6f0008ff76}, - {0x0000ff80fff8ff85}, - {0xfff4ff8bffefff8f}, - {0xffeaff94ffe5ff98}, - {0xffe0ff9dffddff9f}, - {0xffdaffa5ffd5ffa8}, - {0xffd3ffacffcfffaf}, - {0xffcdffb2ffc8ffb6}, - {0xffc6ffb8ffc2ffbc}, - {0xffc0ffc0ffbcffc4}, - {0xffb9ffc7ffb5ffca}, - {0xffb3ffceffaeffd1}, - {0xffacffd4ffa8ffd6}, - {0xffa5ffdbffa1ffe0}, - {0xff9dffe3ff98ffe9}, - {0xff94ffecff90fff1}, - {0xff8afff5ff84fffa}, - {0xff800000ff7a0009}, - {0xff720011ff690019}, - {0xff600022ff55002e}, - {0xff48003bff37004b}, - {0xff26005bff0f007a}, - {0xfeed0098fec100c7}, - {0xfe7f0104fe12017a}, - {0xfd380250faae04e4}}; - - \ No newline at end of file diff --git a/cosim/drivers/cep_tests/iir_input.h b/cosim/drivers/cep_tests/iir_input.h deleted file mode 100644 index 0f7422a..0000000 --- a/cosim/drivers/cep_tests/iir_input.h +++ /dev/null @@ -1,82 +0,0 @@ -//************************************************************************ -// Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT -// -// File Name: iir_input.h -// Program: Common Evaluation Platform (CEP) -// Description: Header file containing expected test vectors -//************************************************************************ - -#if 1 -// was captured 6 samples too late, tony duong 04/22/20 -uint32_t iir_exp_1[32]={ - 0, - 0, - 0, - 0, - 1, - 5, -0x00000008, -0x0000000a, -0x00000011, -0x00000017, -0x00000015, -0x00000019, -0x00000023, -0x00000024, -0x00000023, -0x0000002c, -0x00000033, -0x00000032, -0x00000034, -0x0000003d, -0x00000043, -0x00000042, -0x00000043, -0x0000004c, -0x00000055, -0x00000052, -0x00000052, -0x0000005c, -0x00000063, -0x00000063, -0x00000064, -0x0000006a}; - -#else -//OLD 88888 -uint32_t iir_exp_1[32]={ -0x00000008, -0x0000000a, -0x00000011, -0x00000017, -0x00000015, -0x00000019, -0x00000023, -0x00000024, -0x00000023, -0x0000002c, -0x00000033, -0x00000032, -0x00000034, -0x0000003d, -0x00000043, -0x00000042, -0x00000043, -0x0000004c, -0x00000055, -0x00000052, -0x00000052, -0x0000005c, -0x00000063, -0x00000063, -0x00000064, -0x0000006a, -0x00000071, -0x00000073, -0x0000006a, -0x0000004d, -0x0000001e, -0xfffffff1}; - -#endif diff --git a/cosim/drivers/diag/cepAccessTest.cc b/cosim/drivers/diag/cepAccessTest.cc index 3959e7f..b5b716c 100644 --- a/cosim/drivers/diag/cepAccessTest.cc +++ b/cosim/drivers/diag/cepAccessTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepAccessTest.h b/cosim/drivers/diag/cepAccessTest.h index 3567134..afbf6bd 100644 --- a/cosim/drivers/diag/cepAccessTest.h +++ b/cosim/drivers/diag/cepAccessTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepClintTest.cc b/cosim/drivers/diag/cepClintTest.cc index dd452aa..5e74e21 100644 --- a/cosim/drivers/diag/cepClintTest.cc +++ b/cosim/drivers/diag/cepClintTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepClintTest.h b/cosim/drivers/diag/cepClintTest.h index dec7043..6da4588 100644 --- a/cosim/drivers/diag/cepClintTest.h +++ b/cosim/drivers/diag/cepClintTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepCsrTest.cc b/cosim/drivers/diag/cepCsrTest.cc index f41efa8..b7cf6ef 100644 --- a/cosim/drivers/diag/cepCsrTest.cc +++ b/cosim/drivers/diag/cepCsrTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright (C) 2020 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepCsrTest.h b/cosim/drivers/diag/cepCsrTest.h index 47052a7..cac56a8 100644 --- a/cosim/drivers/diag/cepCsrTest.h +++ b/cosim/drivers/diag/cepCsrTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright (C) 2020 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepDdr3MemTest.cc b/cosim/drivers/diag/cepDdr3MemTest.cc index f8d4624..b45b267 100644 --- a/cosim/drivers/diag/cepDdr3MemTest.cc +++ b/cosim/drivers/diag/cepDdr3MemTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepDdr3MemTest.h b/cosim/drivers/diag/cepDdr3MemTest.h index a8d030f..131383a 100644 --- a/cosim/drivers/diag/cepDdr3MemTest.h +++ b/cosim/drivers/diag/cepDdr3MemTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepGpioTest.cc b/cosim/drivers/diag/cepGpioTest.cc index 82fba17..b180aa3 100644 --- a/cosim/drivers/diag/cepGpioTest.cc +++ b/cosim/drivers/diag/cepGpioTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepGpioTest.h b/cosim/drivers/diag/cepGpioTest.h index 1dda7da..80523c8 100644 --- a/cosim/drivers/diag/cepGpioTest.h +++ b/cosim/drivers/diag/cepGpioTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepLockTest.cc b/cosim/drivers/diag/cepLockTest.cc index 88ca434..8679af2 100644 --- a/cosim/drivers/diag/cepLockTest.cc +++ b/cosim/drivers/diag/cepLockTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepLockTest.h b/cosim/drivers/diag/cepLockTest.h index b8e2d60..cf3a1ef 100644 --- a/cosim/drivers/diag/cepLockTest.h +++ b/cosim/drivers/diag/cepLockTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepLockfreeAtomic.cc b/cosim/drivers/diag/cepLockfreeAtomic.cc index 94bfe63..c868cd5 100644 --- a/cosim/drivers/diag/cepLockfreeAtomic.cc +++ b/cosim/drivers/diag/cepLockfreeAtomic.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepLockfreeAtomic.h b/cosim/drivers/diag/cepLockfreeAtomic.h index 1d4d518..a38104f 100644 --- a/cosim/drivers/diag/cepLockfreeAtomic.h +++ b/cosim/drivers/diag/cepLockfreeAtomic.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepMacroMix.cc b/cosim/drivers/diag/cepMacroMix.cc index 39d9e4a..035faa5 100644 --- a/cosim/drivers/diag/cepMacroMix.cc +++ b/cosim/drivers/diag/cepMacroMix.cc @@ -1,11 +1,15 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // -// File Name: +// File Name: cepMacroMix.cc // Program: Common Evaluation Platform (CEP) -// Description: -// Notes: +// Description: Allows for selective test of CEP acclerator cores +// Notes: CEP.h defines the core types as well as the currently +// enabled cores. The cryptomix parameter defines which +// of the currently enabled cores to test. Bit definition +// (up to 32) corresponds to the index in the cep_core_info +// array. // //************************************************************************ @@ -33,9 +37,11 @@ #include "cep_fir.h" #include "cep_iir.h" #include "cep_dft.h" +#include "cep_idft.h" #include "cep_rsa.h" #include "cep_srot.h" +#define IS_ON(c) ((1 << c) & coreMask) #define CHECK4ERR(e,name) do { \ if (!errCnt) { \ if (srot.GetVerbose()) { \ @@ -55,18 +61,14 @@ // ============================= // The test itself // ============================= -// -// 04/07/21 : added cryptoMask to allow running indiviual crypto core -// -#define IS_ON(c) (1 << c ## _BASE_K) & cryptoMask -int cepMacroMix_runTest(int cpuId, int mask, int cryptoMask, int seed, int verbose) { +int cepMacroMix_runTest(int cpuId, int cpuActiveMask, int coreMask, int seed, int verbose) { // int errCnt = 0; #ifndef BARE_MODE // - // ONly if in the cryptoMask + // ONly if in the coreMask // // int captureOn = 0; @@ -75,377 +77,398 @@ int cepMacroMix_runTest(int cpuId, int mask, int cryptoMask, int seed, int verbo #endif int maxLoop; if (VERBOSE1()) { - LOGI("%s: mask=0x%x cryptoMask=0x%08x\n",__FUNCTION__,mask,cryptoMask); + LOGI("%s: cpuActiveMask=0x%x coreMask=0x%08x\n",__FUNCTION__, cpuActiveMask, coreMask); } - // - // - // do the LLKI unlock here - // - cep_srot srot(verbose); - srot.SetCpuActiveMask(mask); + + // Instantiate and initialize an SRoT object + cep_srot srot(SROT_INDEX, CEP_VERSION_REG_INDEX, verbose); + + srot.SetCpuActiveMask(cpuActiveMask); srot.SetSrotFlag(captureOn); - srot.SetCryptoMask(cryptoMask); + srot.SetCoreMask(coreMask); + + // Initialize the LLKI (One a single core will perform this function) errCnt += srot.LLKI_Setup(cpuId); + if (errCnt) return errCnt; - // - // - switch (cpuId) { - case 0 : - // - // AES - // - if (IS_ON(AES)) { - cep_aes aes(seed,verbose); - aes.init(); - aes.SetCaptureMode(captureOn,"../../drivers/vectors","aes"); - // - maxLoop = 200; - init_aes(); - errCnt += aes.RunAes192Test(maxLoop); - // - aes.freeMe(); - if (errCnt) return errCnt; - } - // - // DES3 - // - if (IS_ON(DES3)) { - cep_des3 des3(seed,verbose); - des3.init(); - des3.SetCaptureMode(captureOn,"../../drivers/vectors","des3"); - // - maxLoop = 150; - init_des3(); - errCnt += des3.RunDes3Test(maxLoop); - // - des3.freeMe(); - if (errCnt) return errCnt; - } - // - // MD5 - // - if (IS_ON(MD5)) { - cep_md5 md5(seed,verbose); - md5.init(); - md5.SetCaptureMode(captureOn,"../../drivers/vectors","md5"); - // - maxLoop = 32; - init_md5(); - errCnt += md5.RunMd5Test(maxLoop); - // - md5.freeMe(); - } - // Free the srot object at the end of thread 0 (freeing it too soon will result - // problems with the other threads who use the object) - - if (errCnt) return errCnt; - break; - - case 1 : - // - // FIR - // - if (IS_ON(FIR)) { - cep_fir fir(seed,verbose); - fir.init(); - fir.SetCaptureMode(captureOn,"../../drivers/vectors","fir"); - // - maxLoop = 10; - init_fir(); - errCnt += fir.RunFirTest(maxLoop); - // - fir.freeMe(); - if (errCnt) return errCnt; - } - // - // IIR - // - if (IS_ON(IIR)) { - cep_iir iir(seed,verbose); - iir.init(); - iir.SetCaptureMode(captureOn,"../../drivers/vectors","iir"); - // - maxLoop = 10; - init_iir(); - errCnt += iir.RunIirTest(maxLoop); - // - iir.freeMe(); - if (errCnt) return errCnt; - } - // - // SHA256 - // - if (IS_ON(SHA256)) { - cep_sha256 sha256(seed,verbose); - sha256.init(); - sha256.SetCaptureMode(captureOn,"../../drivers/vectors","sha256"); - // - maxLoop = 32; - init_sha256(); - errCnt += sha256.RunSha256Test(maxLoop); - // - sha256.freeMe(); + + int maxCoreIndex = CEP_LLKI_CORES; + + for (int coreIndex = 0; coreIndex < maxCoreIndex; coreIndex ++) { + cep_core_info_t core = cep_core_info[coreIndex]; + core_type_t coreType = core.type; + if (IS_ON(coreIndex) && core.enabled) { + switch (coreType) { + case AES_CORE : + // + // AES + // + if (cpuId == 0) { + cep_aes aes(coreIndex,seed,verbose); + aes.SetCaptureMode(captureOn,"../../drivers/vectors","aes"); + + maxLoop = 200; + errCnt += aes.RunAes192Test(maxLoop); + + aes.freeMe(); + } + break; + case DES3_CORE: + // + // DES3 + // + if (cpuId == 0) { + cep_des3 des3(coreIndex,seed,verbose); + des3.SetCaptureMode(captureOn,"../../drivers/vectors","des3"); + + maxLoop = 150; + errCnt += des3.RunDes3Test(maxLoop); + + des3.freeMe(); + } + break; + case MD5_CORE: + // + // MD5 + // + if (cpuId == 0) { + cep_md5 md5(coreIndex,seed,verbose); + md5.SetCaptureMode(captureOn,"../../drivers/vectors","md5"); + + maxLoop = 32; + errCnt += md5.RunMd5Test(maxLoop); + + md5.freeMe(); + } + break; + case FIR_CORE: + // + // FIR + // + if (cpuId == 1) { + cep_fir fir(coreIndex,seed,verbose); + fir.SetCaptureMode(captureOn,"../../drivers/vectors","fir"); + + maxLoop = 10; + errCnt += fir.RunFirTest(maxLoop); + + fir.freeMe(); + } + break; + case IIR_CORE: + // + // IIR + // + if (cpuId == 1) { + cep_iir iir(coreIndex,seed,verbose); + iir.SetCaptureMode(captureOn,"../../drivers/vectors","iir"); + + maxLoop = 10; + errCnt += iir.RunIirTest(maxLoop); + + iir.freeMe(); + } + break; + case SHA256_CORE: + // + // SHA256 + // + if (cpuId == 1) { + cep_sha256 sha256(coreIndex,seed,verbose); + sha256.SetCaptureMode(captureOn,"../../drivers/vectors","sha256"); + + maxLoop = 32; + errCnt += sha256.RunSha256Test(maxLoop); + + sha256.freeMe(); + } + break; + case GPS_CORE: + // + // GPS + // + if (cpuId == 2) { + cep_gps gps(coreIndex,seed,verbose); + gps.SetCaptureMode(captureOn,"../../drivers/vectors","gps"); + + maxLoop = 38; + errCnt += gps.RunGpsTest(maxLoop); + + gps.freeMe(); + } + break; + case DFT_CORE: + // + // DFT + // + if (cpuId == 2) { + cep_dft dft(coreIndex,seed,verbose); + dft.SetCaptureMode(captureOn,"../../drivers/vectors","dft"); + + maxLoop = 10; + errCnt += dft.RunDftTest(maxLoop); + + dft.freeMe(); + } + break; + case IDFT_CORE: + // + // IDFT + // + if (cpuId == 2) { + cep_idft idft(coreIndex,seed,verbose); + idft.SetCaptureMode(captureOn,"../../drivers/vectors","idft"); + + maxLoop = 10; + errCnt += idft.RunIdftTest(maxLoop); + + idft.freeMe(); + } + + break; + case RSA_CORE: + // + // RSA + // + if (cpuId == 3) { + cep_rsa rsa(coreIndex,seed,verbose); + rsa.SetCaptureMode(captureOn,"../../drivers/vectors","rsa"); + + maxLoop = 4; + errCnt += rsa.RunRsaTest(maxLoop,8); + + rsa.freeMe(); + } + break; + + } // switch (cpuId) if (errCnt) return errCnt; - } - - break; - - case 2: - // - // GPS - // - if (IS_ON(GPS)) { - cep_gps gps(seed,verbose); // Note: The GPS constructor does write to the core - gps.init(); - gps.SetCaptureMode(captureOn,"../../drivers/vectors","gps"); - // - maxLoop = 38; - init_gps(); - errCnt += gps.RunGpsTest(maxLoop); - // - gps.freeMe(); - if (errCnt) return errCnt; - } - // - // DFT & IDFT - // - if (IS_ON(DFT)) { - cep_dft dft(seed,verbose); - dft.init(); - dft.SetCaptureMode(captureOn,"../../drivers/vectors","dft"); - // - maxLoop = 10; - init_dft(); - errCnt += dft.RunDftTest(maxLoop); - // - dft.freeMe(); - } - if (errCnt) return errCnt; - break; - - case 3: - // - // RSA - // - if (IS_ON(RSA)) { - cep_rsa rsa(seed,verbose); - rsa.init(); - rsa.SetCaptureMode(captureOn,"../../drivers/vectors","rsa"); - // - maxLoop = 4; - int maxBytes = 8; - - init_rsa(); - if (!errCnt) {errCnt += rsa.RunRsaTest(maxLoop, 8);} // Max Msg/Mod Size = 8 bytes -// if (!errCnt) {errCnt += rsa.RunRsaMemTest(0xf, 1024);}} // 8K bits - rsa.freeMe(); - - } - if (errCnt) return errCnt; - break; - - } // switch (cpuId) - srot.freeMe(); + } // if isOn(coreIndex) + } // for (coreIndex) + + srot.freeMe(); // else do nothing #endif return errCnt; } -// +// // ============================= // With bad keys // ============================= // -int cepMacroMix_runBadKeysTest(int cpuId, int mask, int seed, int verbose) { +int cepMacroMix_runBadKeysTest(int cpuId, int cpuActiveMask, int coreMask, int seed, int verbose) { // int errCnt = 0; +// Do nothing in Bare Mode #ifndef BARE_MODE - // - // - int captureOn = 0; // no capturing!!! + + // No capturing for this test + int captureOn = 0; int maxLoop; - // - // - // do the LLKI unlock here - // - cep_srot srot(verbose); - srot.SetCpuActiveMask(mask); + + // Instantiate and initialize an SRoT object + cep_srot srot(SROT_INDEX, CEP_VERSION_REG_INDEX, verbose); + + srot.SetCpuActiveMask(cpuActiveMask); srot.SetSrotFlag(captureOn); - srot.LLKI_invertKey(1); // all test should fails!! + srot.SetCoreMask(coreMask); + srot.LLKI_invertKey(1); // all test should fails!! + + // Initialize the LLKI (One a single core will perform this function) errCnt += srot.LLKI_Setup(cpuId); + if (errCnt) return errCnt; - // - // - switch (cpuId) { - case 0 : { - // - // AES - // - cep_aes aes(seed,verbose); - aes.init(); - aes.SetCaptureMode(captureOn,"../../drivers/vectors","aes"); - aes.SetExpErr(1); - // - maxLoop = 2; - init_aes(); - errCnt += aes.RunAes192Test(maxLoop); - // - aes.freeMe(); - srot.DisableLLKI(AES_BASE_K); // use as KeyIndex - // - CHECK4ERR(errCnt,"aes"); - // - // DES3 - // - cep_des3 des3(seed,verbose); - des3.init(); - des3.SetCaptureMode(captureOn,"../../drivers/vectors","des3"); - des3.SetExpErr(1); - // - maxLoop = 2; - init_des3(); - errCnt += des3.RunDes3Test(maxLoop); - // - des3.freeMe(); - srot.DisableLLKI(DES3_BASE_K); // use as KeyIndex - CHECK4ERR(errCnt,"des3"); - // - // MD5 - // - cep_md5 md5(seed,verbose); - md5.init(); - md5.SetCaptureMode(captureOn,"../../drivers/vectors","md5"); - md5.SetExpErr(1); - // - maxLoop = 2; - init_md5(); - errCnt += md5.RunMd5Test(maxLoop); - // - md5.freeMe(); - srot.DisableLLKI(MD5_BASE_K); // use as KeyIndex - // Free the srot object at the end of thread 0 (freeing it too soon will result - // problems with the other threads who use the object) - CHECK4ERR(errCnt,"md5"); - break; - } - - case 1 : { - // - // IIR - // - cep_iir iir(seed,verbose); - iir.init(); - iir.SetCaptureMode(captureOn,"../../drivers/vectors","iir"); - iir.SetExpErr(1); - // - maxLoop = 2; - init_iir(); - errCnt += iir.RunIirTest(maxLoop); - // - iir.freeMe(); - srot.DisableLLKI(IIR_BASE_K); // use as KeyIndex - CHECK4ERR(errCnt,"iir"); - // - // FIR - // - cep_fir fir(seed,verbose); - fir.init(); - fir.SetCaptureMode(captureOn,"../../drivers/vectors","fir"); - fir.SetExpErr(1); - // - maxLoop = 2; - init_fir(); - errCnt += fir.RunFirTest(maxLoop); - // - fir.freeMe(); - srot.DisableLLKI(FIR_BASE_K); // use as KeyIndex - CHECK4ERR(errCnt,"fir"); - - // - // SHA256 - // - cep_sha256 sha256(seed,verbose); - sha256.init(); - sha256.SetCaptureMode(captureOn,"../../drivers/vectors","sha256"); - sha256.SetExpErr(1); - // - maxLoop = 2; - init_sha256(); - errCnt += sha256.RunSha256Test(maxLoop); - // - sha256.freeMe(); - srot.DisableLLKI(SHA256_BASE_K); // use as KeyIndex - CHECK4ERR(errCnt,"sha256"); - - break; - } - case 2: { - // - // GPS - // - cep_gps gps(seed,verbose); // Note: The GPS constructor does write to the core - gps.init(); - gps.SetCaptureMode(captureOn,"../../drivers/vectors","gps"); - gps.SetExpErr(1); - // - maxLoop = 2; - init_gps(); - errCnt += gps.RunGpsTest(maxLoop); - // - gps.freeMe(); - srot.DisableLLKI(GPS_BASE_K); // use as KeyIndex - CHECK4ERR(errCnt,"gps"); - // - // DFT & IDFT - // - cep_dft dft(seed,verbose); - dft.init(); - dft.SetCaptureMode(captureOn,"../../drivers/vectors","dft"); - dft.SetExpErr(1); - // - maxLoop = 2; - init_dft(); - errCnt += dft.RunDftTest(maxLoop); - // - dft.freeMe(); - srot.DisableLLKI(DFT_BASE_K); // use as KeyIndex - srot.DisableLLKI(IDFT_BASE_K); // use as KeyIndex - CHECK4ERR(errCnt,"dft"); - break; - } - - case 3: { - // - // RSA - // - cep_rsa rsa(seed,verbose); - rsa.init(); - rsa.SetCaptureMode(captureOn,"../../drivers/vectors","rsa"); - rsa.SetExpErr(1); - // - maxLoop = 2; - int maxBytes=8; - // - init_rsa(); - if (!errCnt) { - errCnt += rsa.RunRsaTest(maxLoop,maxBytes); - } - // - rsa.freeMe(); - srot.DisableLLKI(RSA_BASE_K); // use as KeyIndex - CHECK4ERR(errCnt,"rsa"); - break; - } + int maxCoreIndex = CEP_LLKI_CORES; + + for (int coreIndex = 0; coreIndex < maxCoreIndex; coreIndex ++) { + cep_core_info_t core = cep_core_info[coreIndex]; + core_type_t coreType = core.type; + if (IS_ON(coreIndex) && core.enabled) { + switch (coreType) { + case AES_CORE : + // + // AES + // + if (cpuId == 0) { + cep_aes aes(coreIndex,seed,verbose); + aes.SetCaptureMode(captureOn,"../../drivers/vectors","aes"); + aes.SetExpErr(1); + + maxLoop = 2; + errCnt += aes.RunAes192Test(maxLoop); + + aes.freeMe(); + + CHECK4ERR(errCnt,"aes"); + } + break; + case DES3_CORE: + // + // DES3 + // + if (cpuId == 0) { + cep_des3 des3(coreIndex,seed,verbose); + des3.SetCaptureMode(captureOn,"../../drivers/vectors","des3"); + des3.SetExpErr(1); + + maxLoop = 2; + errCnt += des3.RunDes3Test(maxLoop); + + des3.freeMe(); + + CHECK4ERR(errCnt,"des3"); + } + break; + case MD5_CORE: + // + // MD5 + // + if (cpuId == 0) { + cep_md5 md5(coreIndex,seed,verbose); + md5.SetCaptureMode(captureOn,"../../drivers/vectors","md5"); + md5.SetExpErr(1); + + maxLoop = 2; + errCnt += md5.RunMd5Test(maxLoop); + + md5.freeMe(); + + CHECK4ERR(errCnt,"md5"); + } + break; + case FIR_CORE: + // + // FIR + // + if (cpuId == 1) { + cep_fir fir(coreIndex,seed,verbose); + fir.SetCaptureMode(captureOn,"../../drivers/vectors","fir"); + fir.SetExpErr(1); + + maxLoop = 2; + errCnt += fir.RunFirTest(maxLoop); + + fir.freeMe(); + + CHECK4ERR(errCnt,"fir"); + } + break; + case IIR_CORE: + // + // IIR + // + if (cpuId == 1) { + cep_iir iir(coreIndex,seed,verbose); + iir.SetCaptureMode(captureOn,"../../drivers/vectors","iir"); + iir.SetExpErr(1); + + maxLoop = 2; + errCnt += iir.RunIirTest(maxLoop); + + iir.freeMe(); + + CHECK4ERR(errCnt,"iir"); + } + break; + case SHA256_CORE: + // + // SHA256 + // + if (cpuId == 1) { + cep_sha256 sha256(coreIndex,seed,verbose); + sha256.SetCaptureMode(captureOn,"../../drivers/vectors","sha256"); + sha256.SetExpErr(1); + + maxLoop = 2; + errCnt += sha256.RunSha256Test(maxLoop); + + sha256.freeMe(); + + CHECK4ERR(errCnt,"sha256"); + } + break; + case GPS_CORE: + // + // GPS + // + if (cpuId == 2) { + cep_gps gps(coreIndex,seed,verbose); + gps.SetCaptureMode(captureOn,"../../drivers/vectors","gps"); + gps.SetExpErr(1); + + maxLoop = 2; + errCnt += gps.RunGpsTest(maxLoop); + + gps.freeMe(); + + CHECK4ERR(errCnt,"gps"); + } + break; + case DFT_CORE: + // + // DFT + // + if (cpuId == 2) { + cep_dft dft(coreIndex,seed,verbose); + dft.SetCaptureMode(captureOn,"../../drivers/vectors","dft"); + dft.SetExpErr(1); + + maxLoop = 2; + errCnt += dft.RunDftTest(maxLoop); + + dft.freeMe(); + + CHECK4ERR(errCnt,"dft"); + } + break; + case IDFT_CORE: + // + // IDFT + // + if (cpuId == 2) { + cep_idft idft(coreIndex,seed,verbose); + idft.SetCaptureMode(captureOn,"../../drivers/vectors","idft"); + idft.SetExpErr(1); + + maxLoop = 2; + errCnt += idft.RunIdftTest(maxLoop); + + idft.freeMe(); + + CHECK4ERR(errCnt,"idft"); + } + + break; + case RSA_CORE: + // + // RSA + // + if (cpuId == 3) { + cep_rsa rsa(coreIndex,seed,verbose); + rsa.SetCaptureMode(captureOn,"../../drivers/vectors","rsa"); + rsa.SetExpErr(1); + + maxLoop = 2; + errCnt += rsa.RunRsaTest(maxLoop,8); + + rsa.freeMe(); + + CHECK4ERR(errCnt,"rsa"); + } + break; + + } // switch (cpuId) + if (errCnt) return errCnt; + } // if isOn(coreIndex) + } // for (coreIndex) + + srot.freeMe(); - } // switch (cpuId) - srot.freeMe(); // else do nothing #endif - // - return errCnt; } - diff --git a/cosim/drivers/diag/cepMacroMix.h b/cosim/drivers/diag/cepMacroMix.h index f21adb9..02183e9 100644 --- a/cosim/drivers/diag/cepMacroMix.h +++ b/cosim/drivers/diag/cepMacroMix.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -15,8 +15,8 @@ #ifdef __cplusplus extern "C" { #endif - int cepMacroMix_runTest(int cpuId, int mask, int cryptoMask, int seed, int verbose); - int cepMacroMix_runBadKeysTest(int cpuId, int mask, int seed, int verbose); + int cepMacroMix_runTest(int cpuId, int cpuActiveMask, int coreMask, int seed, int verbose); + int cepMacroMix_runBadKeysTest(int cpuId, int cpuActiveMask, int coreMask, int seed, int verbose); #ifdef __cplusplus } diff --git a/cosim/drivers/diag/cepMaskromTest.cc b/cosim/drivers/diag/cepMaskromTest.cc index 217ceef..a447ab8 100644 --- a/cosim/drivers/diag/cepMaskromTest.cc +++ b/cosim/drivers/diag/cepMaskromTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepMaskromTest.h b/cosim/drivers/diag/cepMaskromTest.h index fe25ee0..309e87f 100644 --- a/cosim/drivers/diag/cepMaskromTest.h +++ b/cosim/drivers/diag/cepMaskromTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepMemTest.cc b/cosim/drivers/diag/cepMemTest.cc index 930b154..22addad 100644 --- a/cosim/drivers/diag/cepMemTest.cc +++ b/cosim/drivers/diag/cepMemTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepMemTest.h b/cosim/drivers/diag/cepMemTest.h index dc530c8..e689376 100644 --- a/cosim/drivers/diag/cepMemTest.h +++ b/cosim/drivers/diag/cepMemTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepMultiThread.cc b/cosim/drivers/diag/cepMultiThread.cc index 52a5528..773cc27 100644 --- a/cosim/drivers/diag/cepMultiThread.cc +++ b/cosim/drivers/diag/cepMultiThread.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -34,6 +34,7 @@ #include "cep_fir.h" #include "cep_iir.h" #include "cep_dft.h" +#include "cep_idft.h" #include "cep_rsa.h" #include "cep_srot.h" @@ -120,7 +121,7 @@ int cepMultiThread_releaseTestLock(int thrId, int testId,uint64_t testLockPtr) // // SRoT // -int cepMultiThread_setup(int cpuId, uint64_t testLockPtr,int maxTest, int coreMask, int verbose) +int cepMultiThread_setup(int cpuId, uint64_t testLockPtr,int maxTest, int cpuActiveMask, int verbose) { // int errCnt =0; @@ -132,8 +133,8 @@ int cepMultiThread_setup(int cpuId, uint64_t testLockPtr,int maxTest, int coreMa DUT_WRITE32_64(testLockPtr + (i*8), 0); } #endif - cep_srot srot(verbose); - srot.SetCpuActiveMask(coreMask); + cep_srot srot(SROT_INDEX, CEP_VERSION_REG_INDEX, verbose); + srot.SetCpuActiveMask(cpuActiveMask); errCnt += srot.LLKI_Setup(cpuId); srot.freeMe(); #endif @@ -146,7 +147,7 @@ int cepMultiThread_setup(int cpuId, uint64_t testLockPtr,int maxTest, int coreMa // // Run Multi-thread // -int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int maxTest, int maxLoop, int seed, int verbose) +int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cpuActiveMask, int maxTest, int maxLoop, int seed, int verbose) { // int errCnt = 0; @@ -157,9 +158,9 @@ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int m #ifndef BARE_MODE int myDoneMask = 0; // - while ((myDoneMask != cryptoMask) && (errCnt == 0)) { + while ((myDoneMask != cpuActiveMask) && (errCnt == 0)) { // - int testId = cepMultiThread_findATest2Run(thrId, testLockPtr, cryptoMask & ~myDoneMask, maxTest, verbose); + int testId = cepMultiThread_findATest2Run(thrId, testLockPtr, cpuActiveMask & ~myDoneMask, maxTest, verbose); if (testId == -1) { LOGE("%s: can't find a test to run thrId=%d myDoneMask=0x%x\n",__FUNCTION__,thrId,myDoneMask); return 1; @@ -172,20 +173,17 @@ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int m if (verbose) { LOGI("===== RUNNING test=%d thrId=%d doneMask=0x%x\n",testId,thrId,myDoneMask); } - - switch (testId) { - case AES_BASE_K : + + int coreIndex = testId; + cep_core_info_t core = cep_core_info[coreIndex]; + switch (core.type) { + case AES_CORE : { // // AES // - cep_aes aes(seed,verbose); - aes.init(); - // - //maxLoop = 20; - init_aes(); + cep_aes aes(coreIndex,seed,verbose); errCnt += aes.RunAes192Test(maxLoop); - // aes.freeMe(); break; } @@ -193,28 +191,18 @@ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int m // // DES3 // - case DES3_BASE_K : + case DES3_CORE : { - cep_des3 des3(seed,verbose); - des3.init(); - // - //maxLoop = 10; - init_des3(); + cep_des3 des3(coreIndex,seed,verbose); errCnt += des3.RunDes3Test(maxLoop); - // des3.freeMe(); break; } - case MD5_BASE_K : + case MD5_CORE : { - cep_md5 md5(seed,verbose); - md5.init(); - // - //maxLoop = 8; - init_md5(); + cep_md5 md5(coreIndex,seed,verbose); errCnt += md5.RunMd5Test(maxLoop); - // md5.freeMe(); break; } @@ -222,15 +210,10 @@ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int m // // FIR // - case FIR_BASE_K : + case FIR_CORE : { - cep_fir fir(seed,verbose); - fir.init(); - // - //maxLoop = 5; - init_fir(); + cep_fir fir(coreIndex,seed,verbose); errCnt += fir.RunFirTest(maxLoop); - // fir.freeMe(); break; } @@ -238,16 +221,11 @@ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int m // // IIR // - case IIR_BASE_K: + case IIR_CORE: { - cep_iir iir(seed,verbose); - iir.init(); - // - //maxLoop = 5; - init_iir(); + cep_iir iir(coreIndex,seed,verbose); errCnt += iir.RunIirTest(maxLoop); - // iir.freeMe(); break; } @@ -255,16 +233,11 @@ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int m // // SHA256 // - case SHA256_BASE_K: + case SHA256_CORE: { - cep_sha256 sha256(seed,verbose); - sha256.init(); - // - //maxLoop = 8; - init_sha256(); + cep_sha256 sha256(coreIndex,seed,verbose); errCnt += sha256.RunSha256Test(maxLoop); - // sha256.freeMe(); break; } @@ -272,16 +245,11 @@ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int m // // GPS // - case GPS_BASE_K: + case GPS_CORE: { - cep_gps gps(seed,verbose); // Note: The GPS constructor does write to the core - gps.init(); - // - //maxLoop = 38; - init_gps(); + cep_gps gps(coreIndex,seed,verbose); // Note: The GPS constructor does write to the core errCnt += gps.RunGpsTest(maxLoop); - // gps.freeMe(); break; } @@ -289,34 +257,30 @@ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int m // // DFT & IDFT // - case DFT_BASE_K: + case DFT_CORE: { - - cep_dft dft(seed,verbose); - dft.init(); - // - //maxLoop = 5; - init_dft(); - init_idft(); + cep_dft dft(coreIndex,seed,verbose); errCnt += dft.RunDftTest(maxLoop); - // dft.freeMe(); break; } + case IDFT_CORE: + { + cep_idft idft(coreIndex,seed,verbose); + errCnt += idft.RunIdftTest(maxLoop); + // + idft.freeMe(); + break; + } // // RSA // - case RSA_BASE_K: + case RSA_CORE: { - cep_rsa rsa(seed,verbose); - rsa.init(); - // - //maxLoop = 4; + cep_rsa rsa(coreIndex,seed,verbose); int maxBytes=8; - // - init_rsa(); if (!errCnt) { errCnt += rsa.RunRsaMemTest(0xf, 1024); // 8K bits } diff --git a/cosim/drivers/diag/cepMultiThread.h b/cosim/drivers/diag/cepMultiThread.h index a915ab2..1e6d30d 100644 --- a/cosim/drivers/diag/cepMultiThread.h +++ b/cosim/drivers/diag/cepMultiThread.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -18,8 +18,8 @@ extern "C" { #endif int cepMultiThread_findATest2Run(int thrId, uint64_t testLockPtr, int doneMask, int maxTest, int verbose); int cepMultiThread_releaseTestLock(int thrId, int testId,uint64_t testLockPtr); - int cepMultiThread_setup(int cpuId, uint64_t testLockPtr,int maxTest, int coreMask, int verbose); - int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int maxTest, int maxLoop,int seed, int verbose); + int cepMultiThread_setup(int cpuId, uint64_t testLockPtr,int maxTest, int cpuActiveMask, int verbose); + int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cpuActiveMask, int maxTest, int maxLoop,int seed, int verbose); #ifdef __cplusplus } diff --git a/cosim/drivers/diag/cepPlicTest.cc b/cosim/drivers/diag/cepPlicTest.cc index 2cd07a9..b094bf8 100644 --- a/cosim/drivers/diag/cepPlicTest.cc +++ b/cosim/drivers/diag/cepPlicTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepPlicTest.h b/cosim/drivers/diag/cepPlicTest.h index 22cb473..995e3be 100644 --- a/cosim/drivers/diag/cepPlicTest.h +++ b/cosim/drivers/diag/cepPlicTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepRegTest.cc b/cosim/drivers/diag/cepRegTest.cc index 2d684f2..3ad446b 100644 --- a/cosim/drivers/diag/cepRegTest.cc +++ b/cosim/drivers/diag/cepRegTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -71,7 +71,7 @@ int cepRegTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb ((uint64_t)(CEP_MINOR_VERSION & 0xFF) << 56)); if (revCheck) { - (*regp->AddROReg_p)(regp, CEP_VERSION_REG, expectedVersion,CEP_VERSION_MASK); + (*regp->AddROReg_p)(regp, CEP_VERSION_REG, expectedVersion, CEP_VERSION_MASK); } switch (cpuId) { case 0: { diff --git a/cosim/drivers/diag/cepRegTest.h b/cosim/drivers/diag/cepRegTest.h index 7982b6f..e0fd338 100644 --- a/cosim/drivers/diag/cepRegTest.h +++ b/cosim/drivers/diag/cepRegTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepSpiTest.cc b/cosim/drivers/diag/cepSpiTest.cc index cc8ff58..2740617 100644 --- a/cosim/drivers/diag/cepSpiTest.cc +++ b/cosim/drivers/diag/cepSpiTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepSpiTest.h b/cosim/drivers/diag/cepSpiTest.h index a6df052..9f22053 100644 --- a/cosim/drivers/diag/cepSpiTest.h +++ b/cosim/drivers/diag/cepSpiTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepSrotMemTest.cc b/cosim/drivers/diag/cepSrotMemTest.cc index f0485fd..e3ef132 100644 --- a/cosim/drivers/diag/cepSrotMemTest.cc +++ b/cosim/drivers/diag/cepSrotMemTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepSrotMemTest.h b/cosim/drivers/diag/cepSrotMemTest.h index 57137b8..f574be8 100644 --- a/cosim/drivers/diag/cepSrotMemTest.h +++ b/cosim/drivers/diag/cepSrotMemTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepSrotTest.cc b/cosim/drivers/diag/cepSrotTest.cc index bd95252..4c3697e 100644 --- a/cosim/drivers/diag/cepSrotTest.cc +++ b/cosim/drivers/diag/cepSrotTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -42,34 +42,24 @@ uint8_t send_srot_message(int verbose, uint64_t message) { // // Send a message to the SRoT // - cep_write(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, message); + cep_write(SROT_INDEX, SROT_LLKIC2_SENDRECV_ADDR, message); // Poll the response waiting bit //do {;} while (!(cep_read(SROT_BASE_K, SROT_CTRLSTS_ADDR) & SROT_CTRLSTS_RESP_WAITING_MASK)); while (timeOut > 0) { - if (cep_read(SROT_BASE_K, SROT_CTRLSTS_ADDR) & SROT_CTRLSTS_RESP_WAITING_MASK) break; + if (cep_read(SROT_INDEX, SROT_CTRLSTS_ADDR) & SROT_CTRLSTS_RESP_WAITING_MASK) break; timeOut--; if (timeOut == 0) return 0xff; // bad!! } // Read the response - response_message = cep_read(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR); + response_message = cep_read(SROT_INDEX, SROT_LLKIC2_SENDRECV_ADDR); // Return the status return((uint8_t)llkic2_extract_status(response_message)); } // end send_srot_message -// -// Macro to selective assign MOCK_TSS_KEY and its size based on the selected core -// -#define SET_KEY_PARAM(k) \ - case k ## _BASE_K : \ - kPtr = (uint64_t *)k ## _MOCK_TSS_KEY; \ - kSize = sizeof(k ## _MOCK_TSS_KEY)/sizeof(uint64_t); \ - maxKeySize = 128; \ - break \ - int cepSrotTest_maxKeyTest(int cpuId, int verbose) { int errCnt=0; @@ -89,30 +79,21 @@ int cepSrotTest_maxKeyTest(int cpuId, int verbose) { LOGI("%s : Initializing Key RAM to all Ones\n",__FUNCTION__); for (int i = 0; i < MAX_LLKI_KEY_SIZE; i++) { - cep_write(SROT_BASE_K, SROT_KEYRAM_ADDR + (i*8), (uint64_t)-1); + cep_write(SROT_INDEX, SROT_KEYRAM_ADDR + (i*8), (uint64_t)-1); } // // Goes thru all the cores!!! // - for (core_index = AES_BASE_K; core_index <= GPS_BASE_K; core_index++) { + for (core_index = 0; core_index < CEP_LLKI_CORES; core_index++) { // For now, the key_index will equal the core_index (though this is not required) key_index = core_index; - // Set the Key Paramaters - switch (key_index) { - SET_KEY_PARAM(AES); - SET_KEY_PARAM(MD5); - SET_KEY_PARAM(SHA256); - SET_KEY_PARAM(RSA); - SET_KEY_PARAM(DES3); - SET_KEY_PARAM(DFT); - SET_KEY_PARAM(IDFT); - SET_KEY_PARAM(FIR); - SET_KEY_PARAM(IIR); - SET_KEY_PARAM(GPS); - } + cep_key_info_t key = KEY_DATA[core_index]; + kPtr = (uint64_t *) key.keyData; + kSize = key.highPointer - key.lowPointer + 1; + maxKeySize = 128; // Loop through different keys for the current core for (int l = 0; l < 4; l++) { @@ -128,7 +109,7 @@ int cepSrotTest_maxKeyTest(int cpuId, int verbose) { // BAD!!! Keys=0xFFFF...FFF... // ----------------------- for (int i = 0; i < kSize; i++) { - cep_write(SROT_BASE_K, SROT_KEYRAM_ADDR + (i*8), (uint64_t) - 1); + cep_write(SROT_INDEX, SROT_KEYRAM_ADDR + (i*8), (uint64_t) - 1); } break; case 1: @@ -136,7 +117,7 @@ int cepSrotTest_maxKeyTest(int cpuId, int verbose) { // Inverted Key // ----------------------- for (int i = 0; i < kSize; i++) { - cep_write(SROT_BASE_K, SROT_KEYRAM_ADDR + (i*8), ~kPtr[i]); + cep_write(SROT_INDEX, SROT_KEYRAM_ADDR + (i*8), ~kPtr[i]); } break; case 2: @@ -144,7 +125,7 @@ int cepSrotTest_maxKeyTest(int cpuId, int verbose) { // BAD LEN : max len Key with the front end = expected key // ----------------------- for (int i = 0; i < kSize; i++) { - cep_write(SROT_BASE_K, SROT_KEYRAM_ADDR + (i*8), kPtr[i]); + cep_write(SROT_INDEX, SROT_KEYRAM_ADDR + (i*8), kPtr[i]); } ks = maxKeySize - 1; break; @@ -157,7 +138,7 @@ int cepSrotTest_maxKeyTest(int cpuId, int verbose) { // Load the Key Index (based on the currently selected core) in the Key Index RAM LOGI("%s : Loading the Key Index into the Key Index RAM\n",__FUNCTION__); - cep_write(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + key_index * 8, key_index_pack( 0x0000, // low pointer + cep_write(SROT_INDEX, SROT_KEYINDEXRAM_ADDR + key_index * 8, key_index_pack( 0x0000, // low pointer ks, // high pointer core_index, // core index 0x1)); // Valid @@ -228,7 +209,7 @@ int cepSrotTest_maxKeyTest(int cpuId, int verbose) { if (errCnt) return 1; } // for (int l = 0; l < 4; l++) - } // for (core_index=AES_BASE_K;core_index<=GPS_BASE_K;core_index++) + } // for (core_index = 0; core_index < CEP_LLKI_CORES; core_index++) #endif // diff --git a/cosim/drivers/diag/cepSrotTest.h b/cosim/drivers/diag/cepSrotTest.h index d28d108..17505cf 100644 --- a/cosim/drivers/diag/cepSrotTest.h +++ b/cosim/drivers/diag/cepSrotTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepUartTest.cc b/cosim/drivers/diag/cepUartTest.cc index d797e04..380cd5b 100644 --- a/cosim/drivers/diag/cepUartTest.cc +++ b/cosim/drivers/diag/cepUartTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/cepUartTest.h b/cosim/drivers/diag/cepUartTest.h index d442103..61cfef3 100644 --- a/cosim/drivers/diag/cepUartTest.h +++ b/cosim/drivers/diag/cepUartTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/regBaseTest.cc b/cosim/drivers/diag/regBaseTest.cc index d515a1c..dec486f 100644 --- a/cosim/drivers/diag/regBaseTest.cc +++ b/cosim/drivers/diag/regBaseTest.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/regBaseTest.h b/cosim/drivers/diag/regBaseTest.h index 21b9823..fb9d10d 100644 --- a/cosim/drivers/diag/regBaseTest.h +++ b/cosim/drivers/diag/regBaseTest.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/simdiag_global.cc b/cosim/drivers/diag/simdiag_global.cc index bba9051..d6aa6a3 100644 --- a/cosim/drivers/diag/simdiag_global.cc +++ b/cosim/drivers/diag/simdiag_global.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/diag/simdiag_global.h b/cosim/drivers/diag/simdiag_global.h index ae8175f..ed76585 100644 --- a/cosim/drivers/diag/simdiag_global.h +++ b/cosim/drivers/diag/simdiag_global.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/Makefile b/cosim/drivers/linux/Makefile index 9a4fcbd..49e6e7e 100644 --- a/cosim/drivers/linux/Makefile +++ b/cosim/drivers/linux/Makefile @@ -150,10 +150,18 @@ clean: rm -f $(TARGET) # -# This target just to rebuild the cep_diag. Assuming everything else already being built via ../README.md file -# +# Helper make targets for updating the cep_diag in the linux build +# NOTE: Manual hacks of buildroot make products to allow for an incremental build were unsuccessful, thus +# a "make clean-buildroot" is the best that can be accomplished resulting in a ~10min build everytime +# cep_diag is updated # buildMe: make install - (cd ${FREEDOM_U_SDK_DIR}/work/buildroot_initramfs; rm -rf build/cep_diag*; make) - (cd ${FREEDOM_U_SDK_DIR}; make -j8 BOARD=vc707devkit_nopci all) + (unset RISCV; unset PERL_MM_OPT; cd ${FREEDOM_U_SDK_DIR}; make clean-buildroot; make -j8 BOARD=vc707devkit_nopci all) + +writeSD: +ifneq ($(DISK),) + (unset RISCV; unset PERL_MM_OPT; cd ${FREEDOM_U_SDK_DIR}; sudo make DISK=$(DISK) vc707-sd-write) +else + @echo "--- DISK variable needs to be set ---" +endif \ No newline at end of file diff --git a/cosim/drivers/linux/cep_acc.cc b/cosim/drivers/linux/cep_acc.cc index 5b04a58..a35760b 100644 --- a/cosim/drivers/linux/cep_acc.cc +++ b/cosim/drivers/linux/cep_acc.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_acc.h b/cosim/drivers/linux/cep_acc.h index cf9a96a..130d237 100644 --- a/cosim/drivers/linux/cep_acc.h +++ b/cosim/drivers/linux/cep_acc.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_cmds.cc b/cosim/drivers/linux/cep_cmds.cc index d2ac65a..5760775 100644 --- a/cosim/drivers/linux/cep_cmds.cc +++ b/cosim/drivers/linux/cep_cmds.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -435,13 +435,10 @@ int cep_init_cmds(void) CEP_ADD_CMD(memRead, 5, cep_acc_memRead, " [word2read]"); CEP_ADD_CMD(memSearch, 7, cep_acc_memSearch, " <#2search> "); CEP_ADD_CMD(system, 1, run_cep_system, "system "); - // + // must do this - // cep_set_max_cmd_count(CMD_zzMAX_CEP_COUNT); - // - // - // ===================================== + return errCnt; } diff --git a/cosim/drivers/linux/cep_cmds.h b/cosim/drivers/linux/cep_cmds.h index dc2e98d..27e70bd 100644 --- a/cosim/drivers/linux/cep_cmds.h +++ b/cosim/drivers/linux/cep_cmds.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_dbg.h b/cosim/drivers/linux/cep_dbg.h index 9eb1fbc..ca20058 100644 --- a/cosim/drivers/linux/cep_dbg.h +++ b/cosim/drivers/linux/cep_dbg.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_diag.cc b/cosim/drivers/linux/cep_diag.cc index 0be1ef0..6f2efe1 100644 --- a/cosim/drivers/linux/cep_diag.cc +++ b/cosim/drivers/linux/cep_diag.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -287,7 +287,7 @@ main (int argc, char * const *argv) { int gErrCnt = 0; //int flags = 0; - int gSkipInit=0, gVerbose=0; + int gVerbose=0; // //int my_id=0, slot=0, targetMask=0; // @@ -308,12 +308,7 @@ main (int argc, char * const *argv) // Global setup // if (argc > 1) { - sscanf(argv[1],"%d",&gSkipInit); - SET_VAR_VALUE(skipInit,gSkipInit); - } - printf("gSkipInit=%d/%d\n",gSkipInit,GET_VAR_VALUE(skipInit)); - if (argc > 2) { - sscanf(argv[2],"%d",&gVerbose); + sscanf(argv[1],"%d",&gVerbose); SET_VAR_VALUE(verbose,gVerbose); } diff --git a/cosim/drivers/linux/cep_diag.h b/cosim/drivers/linux/cep_diag.h index 2a73e48..7d0105c 100644 --- a/cosim/drivers/linux/cep_diag.h +++ b/cosim/drivers/linux/cep_diag.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_exports.cc b/cosim/drivers/linux/cep_exports.cc index d8f7c4d..1117241 100644 --- a/cosim/drivers/linux/cep_exports.cc +++ b/cosim/drivers/linux/cep_exports.cc @@ -1,10 +1,10 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // -// File Name: +// File Name: cep_exports.cc/.h // Program: Common Evaluation Platform (CEP) -// Description: +// Description: Exports to the Linux Diagnostics // Notes: // //************************************************************************ @@ -17,8 +17,6 @@ #include #include #include -//#include -// #include "simdiag_global.h" #include "cep_adrMap.h" #include "cep_io.h" @@ -61,7 +59,7 @@ static void thr_test_func(int id) { int run_threadTest(void) { int errCnt = 0; cep_set_thr_function(thr_test_func); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } @@ -148,7 +146,7 @@ static void cepRegTest_thr(int id) { int run_cepRegTest(void) { int errCnt = 0; cep_set_thr_function(cepRegTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } // @@ -168,7 +166,7 @@ static void cepLockTest_thr(int id) { int run_cepLockTest(void) { int errCnt = 0; cep_set_thr_function(cepLockTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } // @@ -187,7 +185,7 @@ static void cepMultiLock_thr(int id) { int run_cepMultiLock(void) { int errCnt = 0; cep_set_thr_function(cepMultiLock_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } // @@ -234,7 +232,7 @@ int run_cepMaskromTest(void) { int errCnt = 0; // cep_set_thr_function(cepMaskromTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } @@ -255,7 +253,7 @@ int run_cepClintTest(void) { int errCnt = 0; // cep_set_thr_function(cepClintTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } @@ -275,7 +273,7 @@ int run_cepPlicTest(void) { int errCnt = 0; // cep_set_thr_function(cepPlicTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } @@ -291,7 +289,7 @@ int run_cepPlicPrioIntrTest(void) { int errCnt = 0; // cep_set_thr_function(cepPlicPrioIntrTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } #endif @@ -508,7 +506,7 @@ int run_dcacheCoherency(void) { // dcache_gCnt = 0; cep_set_thr_function(dcacheCoherency_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } @@ -583,7 +581,7 @@ int run_icacheCoherency(void) { set_selfModCodeValue(0, GET_VAR_VALUE(verbose)); // start from core 0 // cep_set_thr_function(icacheCoherency_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); } // return errCnt; @@ -616,7 +614,7 @@ int run_ddr3Test(void) { int errCnt = 0; // cep_set_thr_function(ddr3Test_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); //free(scratch_ptr); return errCnt; } @@ -651,7 +649,7 @@ int run_smemTest(void) { int errCnt = 0; // cep_set_thr_function(smemTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } @@ -660,23 +658,30 @@ int run_smemTest(void) { // cepMacroMix Test (4 per test) // ******************** // -//#include "cepregression.h" #include "cepMacroMix.h" static void cepMacroMix_thr(int id) { int errCnt = thr_waitTilLock(id, 5); - errCnt += cepMacroMix_runTest(id,GET_VAR_VALUE(coreMask),GET_VAR_VALUE(testMask),GET_VAR_VALUE(seed),GET_VAR_VALUE(verbose)); + errCnt += cepMacroMix_runTest(id, GET_VAR_VALUE(cpuMask), GET_VAR_VALUE(coreMask), GET_VAR_VALUE(seed), GET_VAR_VALUE(verbose)); cep_set_thr_errCnt(errCnt); } int run_cepMacroMix(void) { + + // Initialize the error count to zero int errCnt = 0; - // - cep_set_thr_function(cepMacroMix_thr); + + // Initialize the core data structures initConfig(); + + // Set the threads function pointer + cep_set_thr_function(cepMacroMix_thr); + // clear the signature DUT_WRITE32_64(reg_base_addr + cep_core0_status, 0); - // - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + + // Spawn the cepMacroMix thread + errCnt += run_multiThreads(GET_VAR_VALUE(cpuMask)); + return errCnt; } @@ -687,43 +692,29 @@ int run_cepMacroMix(void) { // static void cepMacroBadKey_thr(int id) { int errCnt = thr_waitTilLock(id, 5); - errCnt += cepMacroMix_runBadKeysTest(id,GET_VAR_VALUE(coreMask),GET_VAR_VALUE(seed),GET_VAR_VALUE(verbose)); + errCnt += cepMacroMix_runBadKeysTest(id, GET_VAR_VALUE(cpuMask), GET_VAR_VALUE(coreMask), GET_VAR_VALUE(seed), GET_VAR_VALUE(verbose)); cep_set_thr_errCnt(errCnt); } int run_cepMacroBadKey(void) { + + // Initialize the error count to zero int errCnt = 0; - // - cep_set_thr_function(cepMacroBadKey_thr); + + // Initialize the core data structures initConfig(); + + // Set the threads function pointer + cep_set_thr_function(cepMacroBadKey_thr); + + // clear the signature DUT_WRITE32_64(reg_base_addr + cep_core0_status, 0); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); - return errCnt; - } -// -// ******************** -// Single Macros -// ******************** -// -#define RUN_SINGLE(c) \ - int run_cep_ ## c (void) { \ - int saveTestMask = GET_VAR_VALUE(testMask); \ - SET_VAR_VALUE(testMask, 1 << c ## _BASE_K); \ - int errCnt = run_cepMacroMix(); \ - SET_VAR_VALUE(testMask, saveTestMask); \ - return errCnt; \ - } + // Spawn the cepMacroMix runBadKey thread + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); -RUN_SINGLE(AES) -RUN_SINGLE(DES3) -RUN_SINGLE(DFT) -RUN_SINGLE(FIR) -RUN_SINGLE(IIR) -RUN_SINGLE(GPS) -RUN_SINGLE(MD5) -RUN_SINGLE(RSA) -RUN_SINGLE(SHA256) + return errCnt; + } // // ******************** @@ -759,7 +750,7 @@ static void cacheFlush_thr(int id) { int errCnt = 0; // cep_set_thr_function(cacheFlush_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } @@ -788,7 +779,7 @@ int run_cepLockfreeAtomic(void) { clearScratchPtr(); //bzero(scratch_ptr,cep_cache_size*scratch_blocks); cep_set_thr_function(cepLockfreeAtomic_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); //free(scratch_ptr); return errCnt; } @@ -849,7 +840,7 @@ int run_cepLrscOps(void) { int errCnt = 0; // cep_set_thr_function(cepLrscOps_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); //free(scratch_ptr); return errCnt; } @@ -874,7 +865,7 @@ int run_cepAccessTest(void) { int errCnt = 0; // cep_set_thr_function(cepAccessTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } @@ -929,33 +920,10 @@ int run_cepAtomicTest(void) { int errCnt = 0; // cep_set_thr_function(cepAtomicTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); + errCnt = run_multiThreads(GET_VAR_VALUE(cpuMask)); return errCnt; } -// -// ******************** -// CSR -// ******************** -// -#if 0 -// Not under Linux!!!! -#include "cepCsrTest.h" - -static void cepCsrTest_thr(int id) { - int errCnt = thr_waitTilLock(id, 5); - errCnt += cepCsrTest_runTest(id, 64, GET_VAR_VALUE(revCheck), GET_VAR_VALUE(seed), GET_VAR_VALUE(verbose)); - cep_set_thr_errCnt(errCnt); -} - -int run_cepCsrTest(void) { - int errCnt = 0; - // - cep_set_thr_function(cepCsrTest_thr); - errCnt = run_multiThreads(GET_VAR_VALUE(coreMask)); - return errCnt; - } -#endif // // ******************** @@ -963,16 +931,24 @@ int run_cepCsrTest(void) { // ******************** // int run_cepSrotErrTest(void) { + + // Initialize the error count to zero int errCnt = 0; - // - int id = GET_VAR_VALUE(seed) & 0x3; // - cep_srot srot(GET_VAR_VALUE(verbose)); + // Initialize the core data structures + initConfig(); + + int id = GET_VAR_VALUE(cpuMask) & 0x3; + + // Initialize the SRoT object + cep_srot srot(SROT_INDEX, CEP_VERSION_REG_INDEX, GET_VAR_VALUE(verbose)); + // Set the mask... from the seed (which we passed the parent's mask for this test) srot.SetCpuActiveMask(1 << id); + // Call the Error Test errCnt = srot.LLKI_ErrorTest(id); - // + return errCnt; } @@ -983,31 +959,46 @@ int run_cepSrotErrTest(void) { // #include "cepMultiThread.h" u_int64_t testLockBuf=0; -// + static void cepMultiThread_thr(int id) { + + // Set some parameters int errCnt = 0; int maxTest = 10; - // RSA takes too long!!! - int cryptoMask = ((1 << maxTest) -1) & ~(1 << RSA_BASE_K) & GET_VAR_VALUE(testMask); + int cpuMask = ((1 << maxTest) -1) & GET_VAR_VALUE(coreMask); int maxLoop = 5; - errCnt += cepMultiThread_runThr(id, testLockBuf, cryptoMask, maxTest, maxLoop, GET_VAR_VALUE(seed), GET_VAR_VALUE(verbose)); - cep_set_mthr_errCnt(id,errCnt); + + errCnt += cepMultiThread_runThr(id, testLockBuf, cpuMask, maxTest, maxLoop, GET_VAR_VALUE(seed), GET_VAR_VALUE(verbose)); + + // Aggregate thread's error count + cep_set_mthr_errCnt(id, errCnt); + } int run_cepMultiThread(void) { + + // Initialize the error count to zero int errCnt = 0; - // + + // Initialize the core data structures + initConfig(); + + // Set the threads function pointer cep_set_thr_function(cepMultiThread_thr); + int maxTest = 10; + #ifdef USE_ATOMIC testLockBuf = (u_int64_t)getScratchPtr(); // virtual clearScratchPtr(); #else testLockBuf = (u_int64_t)(ddr3_base_adr) + ((u_int64_t)getScratchPtr() & (u_int64_t)(ddr3_base_size-1)); // physical #endif + errCnt += cepMultiThread_setup(0, testLockBuf, maxTest, 1, GET_VAR_VALUE(verbose)) ; - // + if (!errCnt) { errCnt = run_multiThreadFloats(GET_VAR_VALUE(maxThreads)); } + return errCnt; } diff --git a/cosim/drivers/linux/cep_exports.h b/cosim/drivers/linux/cep_exports.h index 9f04f88..fd74694 100644 --- a/cosim/drivers/linux/cep_exports.h +++ b/cosim/drivers/linux/cep_exports.h @@ -1,10 +1,10 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // -// File Name: +// File Name: cep_exports.cc/.h // Program: Common Evaluation Platform (CEP) -// Description: +// Description: Exports to the Linux Diagnostics // Notes: // //************************************************************************ @@ -15,13 +15,6 @@ #include #include "cep_run.h" #include "cepregression.h" -// -// ============================ -// Function prototypes -// ============================ - -// printf("C%d", sched_getcpu(), format, ##__VA_ARGS__); -//#define eprintf(format, …) fprintf (stderr, format, ##__VA_ARGS__) /* Function protos @@ -29,13 +22,9 @@ #ifdef __cplusplus extern "C" { #endif - // - // Common/Utils - // + + int run_threadTest(void); - // - // CEP - // int cep_aWrite(void); int cep_aRead(void); int run_cepRegTest(void); @@ -44,7 +33,6 @@ extern "C" { int run_ddr3Test(void); int run_cepAllMacros(void); int run_cepMacroMix(void); - // misc int run_cepGpioTest(void); int run_cepSrotMemTest(void); int run_cepSrotMaxKeyTest(void); @@ -58,33 +46,23 @@ extern "C" { int run_cepAtomicTest(void); int run_cepSpiTest(void); int run_cepMaskromTest(void); - // int run_cepCsrTest(void); int run_cepSrotErrTest(void); - // - //int run_cepPlicPrioIntrTest(void); - // - int run_cep_AES (void); - int run_cep_DES3 (void); - int run_cep_DFT (void); - int run_cep_FIR (void); - int run_cep_IIR (void); - int run_cep_GPS (void); - int run_cep_MD5 (void); - int run_cep_RSA (void); - int run_cep_SHA256 (void); int run_cepMultiThread(void); - // - // DDR3 - // + + // + // DDR3 + // int ddr3_aWrite(void); int ddr3_aRead(void); - - // - // cores - // + + // + // Cache + // int run_dcacheCoherency(void); int run_icacheCoherency(void); int run_cacheFlush(void); + + #ifdef __cplusplus } #endif diff --git a/cosim/drivers/linux/cep_io.cc b/cosim/drivers/linux/cep_io.cc index 97f1e38..89c4fa2 100644 --- a/cosim/drivers/linux/cep_io.cc +++ b/cosim/drivers/linux/cep_io.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_io.h b/cosim/drivers/linux/cep_io.h index 3343296..6819153 100644 --- a/cosim/drivers/linux/cep_io.h +++ b/cosim/drivers/linux/cep_io.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_macro.cc b/cosim/drivers/linux/cep_macro.cc index 1fbba23..216e588 100644 --- a/cosim/drivers/linux/cep_macro.cc +++ b/cosim/drivers/linux/cep_macro.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_macro.h b/cosim/drivers/linux/cep_macro.h index b17677b..2d4ec44 100644 --- a/cosim/drivers/linux/cep_macro.h +++ b/cosim/drivers/linux/cep_macro.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_run.cc b/cosim/drivers/linux/cep_run.cc index 30b1689..20c6af0 100644 --- a/cosim/drivers/linux/cep_run.cc +++ b/cosim/drivers/linux/cep_run.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -23,6 +23,8 @@ #include #include "cep_adrMap.h" +#include "CEP.h" +#include "cep_srot_keys.h" #include "cep_io.h" #include "cep_cmds.h" #include "cep_vars.h" @@ -575,10 +577,8 @@ int cep_init_run(void) CEP_ADD_RUN(3,cepGpioTest, 0xFFFFFFFF, run_cepGpioTest, NULL, NULL, "CEP GPIO test (single core) "); CEP_ADD_RUN(3,cepSpiTest, 0xFFFFFFFF, run_cepSpiTest, NULL, NULL, "CEP SPI test (single core) "); CEP_ADD_RUN(3,cepSrotErrTest, 0xFFFFFFFF, run_cepSrotErrTest, NULL, NULL, "CEP SRoT Error Test (single core) "); -//CEP_ADD_RUN(3,cepCsrTest, 0xFFFFFFFF, run_cepCsrTest, NULL, NULL, "CEP SPI test (all cores) "); CEP_ADD_RUN(4,cepPlicTest, 0xFFFFFFFF, run_cepPlicTest, NULL, NULL, "CEP PLIC register test (all cores)"); -//CEP_ADD_RUN(4,cepPlicPrioIntrTest,0xFFFFFFFF, run_cepPlicPrioIntrTest,NULL,NULL, "CEP PLIC priority Interrupt test (all cores)"); CEP_ADD_RUN(4,cepClintTest, 0xFFFFFFFF, run_cepClintTest, NULL, NULL, "CEP CLINT register test (all cores)"); CEP_ADD_RUN(4,cepRegTest, 0xFFFFFFFF, run_cepRegTest, NULL, NULL, "CEP register tests on all cores"); CEP_ADD_RUN(4,cepLockTest, 0xFFFFFFFF, run_cepLockTest, NULL, NULL, "CEP single lock test (all cores)"); @@ -592,17 +592,7 @@ int cep_init_run(void) // CEP_ADD_RUN(5,cepMacroMix, 0xFFFFFFFF, run_cepMacroMix, NULL, NULL, "CEP Macro tests (all cores)"); CEP_ADD_RUN(5,cepMacroBadKey, 0xFFFFFFFF, run_cepMacroBadKey, NULL, NULL, "CEP Macro tests with badKey (all cores)"); - // - CEP_ADD_RUN(6,cepSrotMaxKeyTest, 0xFFFFFFFF, run_cepMacroBadKey, NULL, NULL, "CEP Macro tests with maxKey (single core)"); - CEP_ADD_RUN(6,cep_AES , 0xFFFFFFFF, run_cep_AES , NULL, NULL, "CEP AES test (single core)"); - CEP_ADD_RUN(6,cep_DES3 , 0xFFFFFFFF, run_cep_DES3 , NULL, NULL, "CEP DES3 test (single core)"); - CEP_ADD_RUN(6,cep_DFT , 0xFFFFFFFF, run_cep_DFT , NULL, NULL, "CEP DFT and IDFT test (single core)"); - CEP_ADD_RUN(6,cep_FIR , 0xFFFFFFFF, run_cep_FIR , NULL, NULL, "CEP FIR test (single core)"); - CEP_ADD_RUN(6,cep_IIR , 0xFFFFFFFF, run_cep_IIR , NULL, NULL, "CEP IIR test (single core)"); - CEP_ADD_RUN(6,cep_GPS , 0xFFFFFFFF, run_cep_GPS , NULL, NULL, "CEP GPS test (single core)"); - CEP_ADD_RUN(6,cep_MD5 , 0xFFFFFFFF, run_cep_MD5 , NULL, NULL, "CEP MD5 test (single core)"); - CEP_ADD_RUN(6,cep_RSA , 0xFFFFFFFF, run_cep_RSA , NULL, NULL, "CEP RSA test (single core)"); - CEP_ADD_RUN(6,cep_SHA256 , 0xFFFFFFFF, run_cep_SHA256 , NULL, NULL, "CEP SHA256 test (single core)"); + CEP_ADD_RUN(6,cepMultiThread , 0xFFFFFFFF, run_cepMultiThread , NULL, NULL, "CEP multi-thread per core (all cores)"); // // @@ -838,14 +828,14 @@ int thr_waitTilLock(int id, int maxTO) { } -int run_multiThreads(int coreMask) { // , cep_thread_funct_t funct) { +int run_multiThreads(int cpuMask) { // , cep_thread_funct_t funct) { int errCnt = 0; constexpr unsigned num_threads = MAX_CORES; // A mutex ensures orderly access to std::cout from multiple threads. std::mutex liomutex; std::vector threads(num_threads); for (unsigned i = 0; i < num_threads; ++i) { - if ((1 << i) & coreMask) { + if ((1 << i) & cpuMask) { _thr_errCnt[i] = 0; // clear the error threads[i] = std::thread(cep_get_thr_function(), i); std::this_thread::sleep_for(std::chrono::milliseconds(20)); // ?? need to?? @@ -870,7 +860,7 @@ int run_multiThreads(int coreMask) { // , cep_thread_funct_t funct) { } } for (unsigned i = 0; i < num_threads; ++i) { - if ((1 << i) & coreMask) { + if ((1 << i) & cpuMask) { if (threads[i].joinable()) { threads[i].join(); } diff --git a/cosim/drivers/linux/cep_run.h b/cosim/drivers/linux/cep_run.h index 99545b7..77f9176 100644 --- a/cosim/drivers/linux/cep_run.h +++ b/cosim/drivers/linux/cep_run.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -90,7 +90,6 @@ typedef enum { RUN_cepRegTest , RUN_cepLockTest , RUN_cepMultiLock , - // single thread RUN_cepGpioTest , RUN_cepSrotMemTest , RUN_cepSrotMaxKeyTest, @@ -104,20 +103,8 @@ typedef enum { RUN_cepAtomicTest, RUN_cepSpiTest, RUN_cepMaskromTest, - // RUN_cepCsrTest, RUN_cepSrotErrTest, -// RUN_cepPlicPrioIntrTest, - // - RUN_cepMacroMix , // multi-threaded - RUN_cep_AES , - RUN_cep_DES3 , - RUN_cep_DFT , - RUN_cep_FIR , - RUN_cep_IIR , - RUN_cep_GPS , - RUN_cep_MD5 , - RUN_cep_RSA , - RUN_cep_SHA256 , + RUN_cepMacroMix , RUN_cepMultiThread, // RUN_ddr3Test , @@ -196,7 +183,7 @@ extern "C" { void cep_set_thr_errCnt(int value); void cep_set_mthr_errCnt(int thrId,int value); int cep_get_thr_errCnt(void); - int run_multiThreads(int coreMask); // , cep_thread_funct_t funct); + int run_multiThreads(int cpuMask); // , cep_thread_funct_t funct); int run_multiThreadFloats(int num_threads); int thr_waitTilLock(int id, int maxTO); diff --git a/cosim/drivers/linux/cep_script.cc b/cosim/drivers/linux/cep_script.cc index 6ba43d2..cc4be85 100644 --- a/cosim/drivers/linux/cep_script.cc +++ b/cosim/drivers/linux/cep_script.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_script.h b/cosim/drivers/linux/cep_script.h index 2488bd2..f85ece6 100644 --- a/cosim/drivers/linux/cep_script.h +++ b/cosim/drivers/linux/cep_script.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_token.cc b/cosim/drivers/linux/cep_token.cc index 8cd8547..0d8bcd6 100644 --- a/cosim/drivers/linux/cep_token.cc +++ b/cosim/drivers/linux/cep_token.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_token.h b/cosim/drivers/linux/cep_token.h index 355755a..505d113 100644 --- a/cosim/drivers/linux/cep_token.h +++ b/cosim/drivers/linux/cep_token.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/drivers/linux/cep_vars.cc b/cosim/drivers/linux/cep_vars.cc index da910c3..5c4642f 100644 --- a/cosim/drivers/linux/cep_vars.cc +++ b/cosim/drivers/linux/cep_vars.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -126,32 +126,28 @@ int cep_init_vars(void) // This is where you add global control variable to CEP // ====================================================== // name isNum DefaultVaue FuncVect Description - CEP_ADD_VAR(coreMask, 1, 0xf, NULL, "Core Mask"); - CEP_ADD_VAR(noCoreLock, 1, 0x0, NULL, "no CORE Lock (default=lock)"); - // - CEP_ADD_VAR(loop, 1, 1, NULL, "number of test iterations"); + CEP_ADD_VAR(cpuMask, 1, 0xf, NULL, "Specifies which CPUs are allowed to run tests (default=0xf"); + CEP_ADD_VAR(noCoreLock, 1, 0x0, NULL, "no CORE Lock (default=lock)"); + CEP_ADD_VAR(loop, 1, 1, NULL, "number of test iterations"); CEP_ADD_VAR(mloop, 1, 1, NULL, "loop for macro/script execution"); CEP_ADD_VAR(curErrCnt, 1, 0, NULL, "current error count"); CEP_ADD_VAR(lockSeed, 1, 0, NULL, "1=seed is locked, 0=seed is random"); CEP_ADD_VAR(maxErr, 1, 1, NULL, "max number of errors before stop test"); CEP_ADD_VAR(maxThreads, 1,32, NULL, "max number of threads"); CEP_ADD_VAR(regress, 1, 0, NULL, "1=regress mode on, 0=off"); - CEP_ADD_VAR(quit, 1, 0, NULL, "1=quit cep_test"); - CEP_ADD_VAR(seed, 1, 0, NULL, "random seed uses for every test"); - CEP_ADD_VAR(verbose, 1, 0, run_verbose, "verbose level"); - CEP_ADD_VAR(skipInit, 1, 0, NULL, "1=skip the init, 0=do the init"); - CEP_ADD_VAR(prompt, 1, 0, NULL, "1=wait for user input, 0=no wait"); - CEP_ADD_VAR(step , 1, 3, NULL, "memory test increment step value"); + CEP_ADD_VAR(quit, 1, 0, NULL, "1=quit cep_test"); + CEP_ADD_VAR(seed, 1, 0, NULL, "random seed uses for every test"); + CEP_ADD_VAR(verbose, 1, 0, run_verbose, "verbose level"); + CEP_ADD_VAR(prompt, 1, 0, NULL, "1=wait for user input, 0=no wait"); CEP_ADD_VAR(revCheck, 1, 1, run_revCheck, "revision Check Enable (1), 0=don't check for revision"); CEP_ADD_VAR(longRun, 1, 0, NULL, "1=full (long) test enable"); CEP_ROA_VAR(lastDataRead, 1, 0, NULL, "data from last read"); CEP_ROA_VAR(cur_loop, 1, 0, NULL, "DONT TOUCH"); - CEP_ADD_VAR(stop_when_done, 1, 0, NULL, "1=stop PRBS generator when test done, 0=no stop"); CEP_ADD_VAR(filter, 1, -1, cep_exe_filter, "Test filter mask"); CEP_ADD_VAR(detail, 1, 0, NULL, "1=print detailed info, 0=minimal info"); CEP_ADD_VAR(xterm, 1, 0, set_stty, "xterm versus tty"); // ReadOnly - CEP_ADD_VAR(testMask, 1, -1, NULL, "test Mask to pick target to run test."); + CEP_ADD_VAR(coreMask, 1, -1, NULL, "Specifies which CEP accelerator cores to use"); // // // must do this @@ -176,17 +172,17 @@ int cep_exe_setvar(void) // check to make sure there is room if (__cep_var_curCount >= __CEP_VAR_MAX) { PRNT("%s: Sorry, no more room for new variable <%s> because it might already there\n", - __FUNCTION__,get_token(1)->ascii); + __FUNCTION__,get_token(1)->ascii); errCnt++; } else { // add to the list curVar_p = cep_var_add2idx(__cep_var_curCount, // next free one - get_token(1)->ascii, // the name - get_token(2)->isNum, // is a number? - 0, // write-able - NULL, // FIXME!! - get_token(2)->ascii, // valueStr - "dynamic variable"); + get_token(1)->ascii, // the name + get_token(2)->isNum, // is a number? + 0, // write-able + NULL, // FIXME!! + get_token(2)->ascii, // valueStr + "dynamic variable"); __cep_var_curCount++; // add to the list // resort cep_sort_vars(); @@ -204,7 +200,7 @@ int cep_exe_setvar(void) PRNT("%s: variable <%s> = <%s> is replaced\n",__FUNCTION__,get_token(1)->ascii,get_token(2)->ascii); } else { PRNT("%s: Sorry, can't create new variable <%s> because it might already there\n", - __FUNCTION__,get_token(1)->ascii); + __FUNCTION__,get_token(1)->ascii); errCnt++; } return errCnt; @@ -227,43 +223,43 @@ int cep_exe_adjvar(void) if (get_token(3)->isNum) { // only take number for now // modify the variable if (strcmp(get_token(2)->ascii,"+") == 0) { // add operation - curVar_p->value += get_token(3)->value; + curVar_p->value += get_token(3)->value; } else if (strcmp(get_token(2)->ascii,"-") == 0) { // subtract operation - curVar_p->value -= get_token(3)->value; + curVar_p->value -= get_token(3)->value; } else if (strcmp(get_token(2)->ascii,"*") == 0) { // multiply operation - curVar_p->value *= get_token(3)->value; + curVar_p->value *= get_token(3)->value; } else if (strcmp(get_token(2)->ascii,"/") == 0) { // divide operation - if (get_token(3)->value != 0) { - curVar_p->value = curVar_p->value / get_token(3)->value; - } else { - PRNT("%s: can't divide by zero\n", __FUNCTION__); - errCnt++; - return 1; - } + if (get_token(3)->value != 0) { + curVar_p->value = curVar_p->value / get_token(3)->value; + } else { + PRNT("%s: can't divide by zero\n", __FUNCTION__); + errCnt++; + return 1; + } } else if (strcmp(get_token(2)->ascii,">>") == 0) { // right rotate - tmp = ((u_int64_t)curVar_p->value << 32) >> get_token(3)->value; - curVar_p->value = (u_int32_t)(tmp>>32) | (u_int32_t)((tmp & 0xffffffff)<<32); + tmp = ((u_int64_t)curVar_p->value << 32) >> get_token(3)->value; + curVar_p->value = (u_int32_t)(tmp>>32) | (u_int32_t)((tmp & 0xffffffff)<<32); } else if (strcmp(get_token(2)->ascii,"<<") == 0) { // left rotate - tmp = (u_int64_t)curVar_p->value << get_token(3)->value; - curVar_p->value = (u_int32_t)(tmp>>32) | (u_int32_t)(tmp & 0xffffffff); + tmp = (u_int64_t)curVar_p->value << get_token(3)->value; + curVar_p->value = (u_int32_t)(tmp>>32) | (u_int32_t)(tmp & 0xffffffff); } else { - PRNT("%s: Sorry, non-supported operation <%s>\n",__FUNCTION__,get_token(2)->ascii); - errCnt++; - return 1; + PRNT("%s: Sorry, non-supported operation <%s>\n",__FUNCTION__,get_token(2)->ascii); + errCnt++; + return 1; } // must also update the valStr sprintf(curVar_p->valStr,"0x%x",(u_int32_t)curVar_p->value); // might be negative if (VERBOSE1()) { - PRNT("%s: variable <%s> is adjusted to <%s>\n",__FUNCTION__,curVar_p->name,curVar_p->valStr); + PRNT("%s: variable <%s> is adjusted to <%s>\n",__FUNCTION__,curVar_p->name,curVar_p->valStr); } // there might be a function to execute after adjustment if (curVar_p->var_vect != NULL) { - errCnt = (*curVar_p->var_vect)(); + errCnt = (*curVar_p->var_vect)(); } } else { PRNT("%s: argument#3 <%s> must be a number\n", __FUNCTION__,get_token(3)->ascii); @@ -272,22 +268,12 @@ int cep_exe_adjvar(void) } } else { PRNT("%s: Sorry, can't adjust variable <%s> because there might be multiple matches or non-supported ops\n", - __FUNCTION__,get_token(1)->ascii); + __FUNCTION__,get_token(1)->ascii); errCnt++; } return errCnt; } -int cep_exe_monitor(void) -{ - int errCnt = 0; - if (get_token(1)->isNum) { - SET_VAR_VALUE(stop_when_done,get_token(1)->value ? 0 : 1); - } - PRNT("FIX ME\n"); - return errCnt; -} - // // create/add new variable to table and prompt at the screen for its value // @@ -355,28 +341,28 @@ void cep_sort_vars(void) if (debugMe) PRNT("Working on %s\n",__cep_var_array[i].name); inserted = 0; while (cur_p != NULL) { - if (strcasecmp(__cep_var_array[i].name, cur_p->name) < 0) { // i am his little brother!! - // add it in the middle - if (last_p == NULL) { // I am now the head - __cep_var_head_p = &(__cep_var_array[i]); - } - else { - last_p->next = &(__cep_var_array[i]); - } - __cep_var_array[i].next = cur_p; // big bother - inserted = 1; - if (debugMe) PRNT("head=%s: link %s -> %s\n",__cep_var_head_p->name, last_p->name, __cep_var_array[i].name); - cur_p = NULL; // done - } else { // next - last_p = cur_p; - cur_p = cur_p->next; - if (debugMe) PRNT("last=%s cur=%s\n",last_p->name,cur_p->name); - } + if (strcasecmp(__cep_var_array[i].name, cur_p->name) < 0) { // i am his little brother!! + // add it in the middle + if (last_p == NULL) { // I am now the head + __cep_var_head_p = &(__cep_var_array[i]); + } + else { + last_p->next = &(__cep_var_array[i]); + } + __cep_var_array[i].next = cur_p; // big bother + inserted = 1; + if (debugMe) PRNT("head=%s: link %s -> %s\n",__cep_var_head_p->name, last_p->name, __cep_var_array[i].name); + cur_p = NULL; // done + } else { // next + last_p = cur_p; + cur_p = cur_p->next; + if (debugMe) PRNT("last=%s cur=%s\n",last_p->name,cur_p->name); + } } // while // must be at end of list if (!inserted) { // link to last - last_p->next = &(__cep_var_array[i]); - if (debugMe) PRNT("link to last=%s\n",last_p->name); + last_p->next = &(__cep_var_array[i]); + if (debugMe) PRNT("link to last=%s\n",last_p->name); } } // only if valid } // for @@ -397,8 +383,8 @@ cep_var_info *cep_search_var(char *varName, int *matchFound) l0 = strlen(varName); while (i < __cep_var_curCount) { if (strncasecmp(varName, __cep_var_array[i].name, - //MIN(l0,strlen(__cep_var_array[i].name))) == 0) { // found it - l0) == 0) { + //MIN(l0,strlen(__cep_var_array[i].name))) == 0) { // found it + l0) == 0) { saveP = i; *matchFound = *matchFound + 1; } @@ -427,8 +413,8 @@ void cep_search_var_and_printAll(char *varName) PRNT("Possible matching VAR(s)\n"); while (i < __cep_var_curCount) { if (strncasecmp(varName, __cep_var_array[i].name, - //MIN(l0,strlen(__cep_var_array[i].name))) == 0) { // found it - l0) == 0) { + //MIN(l0,strlen(__cep_var_array[i].name))) == 0) { // found it + l0) == 0) { cep_var_print(&__cep_var_array[i]); } i++; @@ -441,13 +427,13 @@ void cep_search_var_and_printAll(char *varName) // ==================================== // cep_var_info *cep_var_add2idx(int idx, const char *name, int isNum, int readOnly, - cep_exe_var_vect_t var_vect, - const char *strDefaultValue, const char *help) + cep_exe_var_vect_t var_vect, + const char *strDefaultValue, const char *help) { cep_var_info *tmp_p = NULL; if (idx >= __CEP_VAR_MAX) { PRNT("%s: ERROR Can't add any more variable. idx=%d exceed its limit of %d\n", - __FUNCTION__,idx,__CEP_VAR_MAX); + __FUNCTION__,idx,__CEP_VAR_MAX); return tmp_p; } // add to the current one and move to next @@ -479,7 +465,7 @@ cep_var_info *cep_var_changeFuncVec(int idx, cep_exe_var_vect_t var_vect) cep_var_info *tmp_p = NULL; if (idx >= __CEP_VAR_MAX) { PRNT("%s: ERROR Can't add any more variable. idx=%d exceed its limit of %d\n", - __FUNCTION__,idx,__CEP_VAR_MAX); + __FUNCTION__,idx,__CEP_VAR_MAX); return tmp_p; } __cep_var_array[idx].var_vect = var_vect; @@ -563,7 +549,7 @@ void cep_var_dump_all(int readOnly, int rdwr) cur_p = __cep_var_head_p; while (cur_p != NULL) { if (cur_p->readOnly) { - cep_var_print(cur_p); + cep_var_print(cur_p); } cur_p = cur_p->next; } @@ -574,7 +560,7 @@ void cep_var_dump_all(int readOnly, int rdwr) // first ReadOnly while (cur_p != NULL) { if (cur_p->readOnly == 0) { - cep_var_print(cur_p); + cep_var_print(cur_p); } cur_p = cur_p->next; } @@ -685,7 +671,7 @@ int cep_print_timeStamp(void) hours = seconds / (60 * 60); seconds = seconds - (hours * 60 * 60); minutes = seconds / 60; seconds = seconds - (minutes * 60); printf("Current timer since last reset: %d days %d hours %d minutes %d seconds %d usec (total=%d seconds)\n", - days,hours,minutes,seconds,usec, totalSeconds); + days,hours,minutes,seconds,usec, totalSeconds); #else printf("*** ADD ME **\n"); #endif diff --git a/cosim/drivers/linux/cep_vars.h b/cosim/drivers/linux/cep_vars.h index 07e3f91..061a593 100644 --- a/cosim/drivers/linux/cep_vars.h +++ b/cosim/drivers/linux/cep_vars.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) @@ -70,7 +70,7 @@ typedef enum { VAR_CEP_MARKER=-1, // ======== BEGIN (must start at 0) =========== VAR_curErrCnt, - VAR_coreMask, + VAR_cpuMask, VAR_noCoreLock, // no core lock // VAR_lockSeed, @@ -82,13 +82,10 @@ typedef enum { VAR_quit, VAR_regress, VAR_seed, - VAR_skipInit, - VAR_testMask, + VAR_coreMask, VAR_verbose, VAR_revCheck, VAR_longRun, - VAR_step, - VAR_stop_when_done, VAR_filter, VAR_detail, VAR_xterm, @@ -151,7 +148,6 @@ extern "C" { int cep_exe_setvar(void); int cep_exe_getvar(void); int cep_exe_adjvar(void); - int cep_exe_monitor(void); void cep_set_run_revCheck_func(cep_exe_var_vect_t checkFunc); void cep_search_var_and_printAll(char *varName); cep_var_info *cep_search_var(char *varName, int *matchFound); diff --git a/cosim/dvt/cep_adrMap.incl b/cosim/dvt/cep_adrMap.incl index 9bac034..abefad9 100644 --- a/cosim/dvt/cep_adrMap.incl +++ b/cosim/dvt/cep_adrMap.incl @@ -1,10 +1,13 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // -// File Name: +// File Name: cep_adrMap.incl // Program: Common Evaluation Platform (CEP) -// Description: +// Description: Miscellaneous constants and addresses related to +// CEP items that are not part of the accelerator cores +// as defined in CEP.h. Converted to cep_adrMap.h via +// a PERL script // Notes: // //************************************************************************ @@ -296,11 +299,8 @@ Generated Address Map // `define reg_base_addr 'h700F_0000 `define CEP_VERSION_REG 'h700F_0000 -/* - 04/10/21 removed, use from auto-extract from scala -`define CEP_EXPECTED_VERSION 'h20030000_00000000 -*/ -`define CEP_VERSION_MASK 'h0FFFFFFF_FFFFFFFF +`define CEP_VERSION_MASK 'h0FFFFFFF_FFFFFFFF + // // Test and Set diff --git a/cosim/dvt/cep_hierMap.incl b/cosim/dvt/cep_hierMap.incl index 35aca26..db7bade 100644 --- a/cosim/dvt/cep_hierMap.incl +++ b/cosim/dvt/cep_hierMap.incl @@ -2,9 +2,10 @@ // Copyright 2021 Massachusetts Institute of Technology // SPDX short identifier: BSD-2-Clause // -// File Name: +// File Name: cep_hierMap.incl // Program: Common Evaluation Platform (CEP) -// Description: +// Description: Defines related to the design hiearchy that increase +// readability // Notes: // //************************************************************************ diff --git a/cosim/isaTests/.DS_Store b/cosim/isaTests/.DS_Store index 67dc35f..7d2187e 100644 Binary files a/cosim/isaTests/.DS_Store and b/cosim/isaTests/.DS_Store differ diff --git a/cosim/pli/dpi_bitbang.cc b/cosim/pli/dpi_bitbang.cc index f09cf4e..8d55771 100644 --- a/cosim/pli/dpi_bitbang.cc +++ b/cosim/pli/dpi_bitbang.cc @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/pli/dpi_bitbang.h b/cosim/pli/dpi_bitbang.h index 4baa51d..5031a28 100644 --- a/cosim/pli/dpi_bitbang.h +++ b/cosim/pli/dpi_bitbang.h @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/cosim/pli/log.cc b/cosim/pli/log.cc index afcb572..f388922 100644 --- a/cosim/pli/log.cc +++ b/cosim/pli/log.cc @@ -2,7 +2,7 @@ // Copyright 2021 Massachusetts Institute of Technology // SPDX short identifier: BSD-2-Clause // -// File Name: +// File Name: log.cc // Program: Common Evaluation Platform (CEP) // Description: // Notes: @@ -18,6 +18,7 @@ // FIXME!!! int debug_mode = 0; + #include #include "VecVal.h" #include "shIpc.h" diff --git a/cosim/vBareTest/.DS_Store b/cosim/vBareTest/.DS_Store index bff31d7..3031e2b 100644 Binary files a/cosim/vBareTest/.DS_Store and b/cosim/vBareTest/.DS_Store differ diff --git a/doc/version3.4.jpg b/doc/version3.4.jpg deleted file mode 100644 index 9f37b41..0000000 Binary files a/doc/version3.4.jpg and /dev/null differ diff --git a/doc/version3.41.jpg b/doc/version3.41.jpg new file mode 100644 index 0000000..f1da7d4 Binary files /dev/null and b/doc/version3.41.jpg differ diff --git a/hdl_cores/.DS_Store b/hdl_cores/.DS_Store index b1e53d3..9d6456d 100644 Binary files a/hdl_cores/.DS_Store and b/hdl_cores/.DS_Store differ diff --git a/hdl_cores/aes/aes_192_mock_tss.sv b/hdl_cores/aes/aes_192_mock_tss.sv index 13edeba..4b2f777 100644 --- a/hdl_cores/aes/aes_192_mock_tss.sv +++ b/hdl_cores/aes/aes_192_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: aes_192_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/des3/des3_mock_tss.sv b/hdl_cores/des3/des3_mock_tss.sv index 85f811b..52ee210 100644 --- a/hdl_cores/des3/des3_mock_tss.sv +++ b/hdl_cores/des3/des3_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: des3_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/dsp/FIR_filter_mock_tss.sv b/hdl_cores/dsp/FIR_filter_mock_tss.sv index 3d4b11a..ef9befb 100644 --- a/hdl_cores/dsp/FIR_filter_mock_tss.sv +++ b/hdl_cores/dsp/FIR_filter_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: FIR_filter_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/dsp/IIR_filter_mock_tss.sv b/hdl_cores/dsp/IIR_filter_mock_tss.sv index 7b64624..2456d13 100644 --- a/hdl_cores/dsp/IIR_filter_mock_tss.sv +++ b/hdl_cores/dsp/IIR_filter_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: IIR_filter_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/dsp/dft_top_mock_tss.sv b/hdl_cores/dsp/dft_top_mock_tss.sv index e0e2c77..302e69f 100644 --- a/hdl_cores/dsp/dft_top_mock_tss.sv +++ b/hdl_cores/dsp/dft_top_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: dft_top_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/dsp/idft_top_mock_tss.sv b/hdl_cores/dsp/idft_top_mock_tss.sv index 41e1342..6b5f62f 100644 --- a/hdl_cores/dsp/idft_top_mock_tss.sv +++ b/hdl_cores/dsp/idft_top_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: idft_top_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/freedom/.DS_Store b/hdl_cores/freedom/.DS_Store index e4e1181..80e9d39 100644 Binary files a/hdl_cores/freedom/.DS_Store and b/hdl_cores/freedom/.DS_Store differ diff --git a/hdl_cores/freedom/bootrom/sdboot/sd.c b/hdl_cores/freedom/bootrom/sdboot/sd.c index b52ef0b..a55f091 100644 --- a/hdl_cores/freedom/bootrom/sdboot/sd.c +++ b/hdl_cores/freedom/bootrom/sdboot/sd.c @@ -224,7 +224,7 @@ void print_greeting() kputs(" ./+++++++++++oo+++: +oo++o++++o+o+oo+oo.- `s+++s`- "); kputs(" .--:---:-:-::-::` -::::::::::::::::::. :::::. "); kputs(" "); - kputs(" Common Evaluation Platform v3.40 "); + kputs(" Common Evaluation Platform v3.41 "); kputs(" Copyright 2021 Massachusetts Institute of Technology "); kputs(" "); kputs(" Built upon the SiFive Freedom U500 Platform using "); @@ -239,6 +239,7 @@ void print_greeting() kputs(" "); kputs(" Specific commit links available in the CEP README.md, Release Notes "); kputs(" "); + kputs(""); kprintf("BootRom Image built on %s %s\n",__DATE__,__TIME__); kputs(""); } diff --git a/hdl_cores/freedom/bootrom/sdboot/xExeHacked.c b/hdl_cores/freedom/bootrom/sdboot/xExeHacked.c index 8a36e73..cf5fda2 100644 --- a/hdl_cores/freedom/bootrom/sdboot/xExeHacked.c +++ b/hdl_cores/freedom/bootrom/sdboot/xExeHacked.c @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/freedom/mitll-blocks/src/main/scala/cep_addresses.scala b/hdl_cores/freedom/mitll-blocks/src/main/scala/cep_addresses.scala index 45fc8b4..2b6f7d4 100644 --- a/hdl_cores/freedom/mitll-blocks/src/main/scala/cep_addresses.scala +++ b/hdl_cores/freedom/mitll-blocks/src/main/scala/cep_addresses.scala @@ -34,7 +34,7 @@ import freechips.rocketchip.tilelink._ object CEPVersion { val CEP_MAJOR_VERSION = 0x03 - val CEP_MINOR_VERSION = 0x40 + val CEP_MINOR_VERSION = 0x41 } object AESAddresses { diff --git a/hdl_cores/freedom/src/main/scala/unleashed/DevKitAddresses.scala b/hdl_cores/freedom/src/main/scala/unleashed/DevKitAddresses.scala index 388909d..aeb9f32 100644 --- a/hdl_cores/freedom/src/main/scala/unleashed/DevKitAddresses.scala +++ b/hdl_cores/freedom/src/main/scala/unleashed/DevKitAddresses.scala @@ -29,12 +29,33 @@ object CEPBaseAddresses { val md5_llki_sendrecv_addr = 0x70018008L val md5_llki_depth = 0x000000ffL - val sha256_base_addr = 0x70020000L - val sha256_depth = 0x000000FFL - val sha256_llki_base_addr = 0x70028000L - val sha256_llki_ctrlsts_addr = 0x70028000L - val sha256_llki_sendrecv_addr = 0x70028008L - val sha256_llki_depth = 0x000000ffL + val sha256_0_base_addr = 0x70020000L + val sha256_0_depth = 0xFFL + val sha256_0_llki_base_addr = 0x70020800L + val sha256_0_llki_ctrlsts_addr = 0x70020800L + val sha256_0_llki_sendrecv_addr = 0x70020808L + val sha256_0_llki_depth = 0xFFL + + val sha256_1_base_addr = 0x70021000L + val sha256_1_depth = 0xFFL + val sha256_1_llki_base_addr = 0x70021800L + val sha256_1_llki_ctrlsts_addr = 0x70021800L + val sha256_1_llki_sendrecv_addr = 0x70021808L + val sha256_1_llki_depth = 0xFFL + + val sha256_2_base_addr = 0x70022000L + val sha256_2_depth = 0xFFL + val sha256_2_llki_base_addr = 0x70022800L + val sha256_2_llki_ctrlsts_addr = 0x70022800L + val sha256_2_llki_sendrecv_addr = 0x70022808L + val sha256_2_llki_depth = 0xFFL + + val sha256_3_base_addr = 0x70023000L + val sha256_3_depth = 0xFFL + val sha256_3_llki_base_addr = 0x70023800L + val sha256_3_llki_ctrlsts_addr = 0x70023800L + val sha256_3_llki_sendrecv_addr = 0x70023808L + val sha256_3_llki_depth = 0xFFL val rsa_base_addr = 0x70030000L val rsa_depth = 0x000000FFL @@ -78,12 +99,36 @@ object CEPBaseAddresses { val iir_llki_sendrecv_addr = 0x70088008L val iir_llki_depth = 0x000000ffL - val gps_base_addr = 0x70090000L - val gps_depth = 0x000000FFL - val gps_llki_base_addr = 0x70098000L - val gps_llki_ctrlsts_addr = 0x70098000L - val gps_llki_sendrecv_addr = 0x70098008L - val gps_llki_depth = 0x000000ffL + + val gps_0_base_addr = 0x70090000L + val gps_0_depth = 0xFFL + val gps_0_llki_base_addr = 0x70090800L + val gps_0_llki_ctrlsts_addr = 0x70090800L + val gps_0_llki_sendrecv_addr = 0x70090808L + val gps_0_llki_depth = 0xFFL + + val gps_1_base_addr = 0x70091000L + val gps_1_depth = 0xFFL + val gps_1_llki_base_addr = 0x70091800L + val gps_1_llki_ctrlsts_addr = 0x70091800L + val gps_1_llki_sendrecv_addr = 0x70091808L + val gps_1_llki_depth = 0xFFL + + val gps_2_base_addr = 0x70092000L + val gps_2_depth = 0xFFL + val gps_2_llki_base_addr = 0x70092800L + val gps_2_llki_ctrlsts_addr = 0x70092800L + val gps_2_llki_sendrecv_addr = 0x70092808L + val gps_2_llki_depth = 0xFFL + + val gps_3_base_addr = 0x70093000L + val gps_3_depth = 0xFFL + val gps_3_llki_base_addr = 0x70093800L + val gps_3_llki_ctrlsts_addr = 0x70093800L + val gps_3_llki_sendrecv_addr = 0x70093808L + val gps_3_llki_depth = 0xFFL + + val cep_cores_depth = 0x000FFFFFL val cepregs_base_addr = 0x700F0000L diff --git a/hdl_cores/freedom/src/main/scala/unleashed/DevKitConfigs.scala b/hdl_cores/freedom/src/main/scala/unleashed/DevKitConfigs.scala index 2c9ed28..da4e1d1 100644 --- a/hdl_cores/freedom/src/main/scala/unleashed/DevKitConfigs.scala +++ b/hdl_cores/freedom/src/main/scala/unleashed/DevKitConfigs.scala @@ -91,13 +91,44 @@ class U500DevKitPeripherals extends Config((site, here, up) => { )) case PeripheryGPSKey => List( COREParams( - slave_base_addr = BigInt(CEPBaseAddresses.gps_base_addr), - slave_depth = BigInt(CEPBaseAddresses.gps_depth), - llki_base_addr = BigInt(CEPBaseAddresses.gps_llki_base_addr), - llki_depth = BigInt(CEPBaseAddresses.gps_llki_depth), - llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_llki_ctrlsts_addr), - llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_llki_sendrecv_addr), - dev_name = s"gps" + slave_base_addr = BigInt(CEPBaseAddresses.gps_0_base_addr), + slave_depth = BigInt(CEPBaseAddresses.gps_0_depth), + llki_base_addr = BigInt(CEPBaseAddresses.gps_0_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.gps_0_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_0_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_0_llki_sendrecv_addr), + dev_name = s"gps_0", + verilog_module_name = Some(s"gps_mock_tss") + ), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.gps_1_base_addr), + slave_depth = BigInt(CEPBaseAddresses.gps_1_depth), + llki_base_addr = BigInt(CEPBaseAddresses.gps_1_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.gps_1_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_1_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_1_llki_sendrecv_addr), + dev_name = s"gps_1", + verilog_module_name = Some(s"gps_mock_tss") + ), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.gps_2_base_addr), + slave_depth = BigInt(CEPBaseAddresses.gps_2_depth), + llki_base_addr = BigInt(CEPBaseAddresses.gps_2_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.gps_2_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_2_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_2_llki_sendrecv_addr), + dev_name = s"gps_2", + verilog_module_name = Some(s"gps_mock_tss") + ), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.gps_3_base_addr), + slave_depth = BigInt(CEPBaseAddresses.gps_3_depth), + llki_base_addr = BigInt(CEPBaseAddresses.gps_3_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.gps_3_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.gps_3_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.gps_3_llki_sendrecv_addr), + dev_name = s"gps_3", + verilog_module_name = Some(s"gps_mock_tss") )) case PeripheryMD5Key => List( COREParams( @@ -131,13 +162,44 @@ class U500DevKitPeripherals extends Config((site, here, up) => { )) case PeripherySHA256Key => List( COREParams( - slave_base_addr = BigInt(CEPBaseAddresses.sha256_base_addr), - slave_depth = BigInt(CEPBaseAddresses.sha256_depth), - llki_base_addr = BigInt(CEPBaseAddresses.sha256_llki_base_addr), - llki_depth = BigInt(CEPBaseAddresses.sha256_llki_depth), - llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_llki_ctrlsts_addr), - llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_llki_sendrecv_addr), - dev_name = s"sha256" + slave_base_addr = BigInt(CEPBaseAddresses.sha256_0_base_addr), + slave_depth = BigInt(CEPBaseAddresses.sha256_0_depth), + llki_base_addr = BigInt(CEPBaseAddresses.sha256_0_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.sha256_0_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_0_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_0_llki_sendrecv_addr), + dev_name = s"sha256_0", + verilog_module_name = Some(s"sha256_mock_tss") + ), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.sha256_1_base_addr), + slave_depth = BigInt(CEPBaseAddresses.sha256_1_depth), + llki_base_addr = BigInt(CEPBaseAddresses.sha256_1_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.sha256_1_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_1_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_1_llki_sendrecv_addr), + dev_name = s"sha256_1", + verilog_module_name = Some(s"sha256_mock_tss") + ), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.sha256_2_base_addr), + slave_depth = BigInt(CEPBaseAddresses.sha256_2_depth), + llki_base_addr = BigInt(CEPBaseAddresses.sha256_2_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.sha256_2_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_2_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_2_llki_sendrecv_addr), + dev_name = s"sha256_2", + verilog_module_name = Some(s"sha256_mock_tss") + ), + COREParams( + slave_base_addr = BigInt(CEPBaseAddresses.sha256_3_base_addr), + slave_depth = BigInt(CEPBaseAddresses.sha256_3_depth), + llki_base_addr = BigInt(CEPBaseAddresses.sha256_3_llki_base_addr), + llki_depth = BigInt(CEPBaseAddresses.sha256_3_llki_depth), + llki_ctrlsts_addr = BigInt(CEPBaseAddresses.sha256_3_llki_ctrlsts_addr), + llki_sendrecv_addr = BigInt(CEPBaseAddresses.sha256_3_llki_sendrecv_addr), + dev_name = s"sha256_3", + verilog_module_name = Some(s"sha256_mock_tss") )) case PeripheryRSAKey => List( COREParams( @@ -169,17 +231,23 @@ class U500DevKitPeripherals extends Config((site, here, up) => { cep_cores_depth = BigInt(CEPBaseAddresses.cep_cores_depth), // The following array results in the creation of LLKI_CORE_INDEX_ARRAY in srot_wrapper.sv // The SRoT uses these indicies for routing keys to the appropriate core - llki_cores_array = Array( - CEPBaseAddresses.aes_llki_base_addr, // Core Index 0 - CEPBaseAddresses.md5_llki_base_addr, // Core Index 1 - CEPBaseAddresses.sha256_llki_base_addr, // Core Index 2 - CEPBaseAddresses.rsa_llki_base_addr, // Core Index 3 - CEPBaseAddresses.des3_llki_base_addr, // Core Index 4 - CEPBaseAddresses.dft_llki_base_addr, // Core Index 5 - CEPBaseAddresses.idft_llki_base_addr, // Core Index 6 - CEPBaseAddresses.fir_llki_base_addr, // Core Index 7 - CEPBaseAddresses.iir_llki_base_addr, // Core Index 8 - CEPBaseAddresses.gps_llki_base_addr // Core Index 9 + llki_cores_array = Array( + CEPBaseAddresses.aes_llki_base_addr, // Core Index 0 + CEPBaseAddresses.md5_llki_base_addr, // Core Index 1 + CEPBaseAddresses.sha256_0_llki_base_addr, // Core Index 2 + CEPBaseAddresses.sha256_1_llki_base_addr, // Core Index 3 + CEPBaseAddresses.sha256_2_llki_base_addr, // Core Index 4 + CEPBaseAddresses.sha256_3_llki_base_addr, // Core Index 5 + CEPBaseAddresses.rsa_llki_base_addr, // Core Index 6 + CEPBaseAddresses.des3_llki_base_addr, // Core Index 7 + CEPBaseAddresses.dft_llki_base_addr, // Core Index 8 + CEPBaseAddresses.idft_llki_base_addr, // Core Index 9 + CEPBaseAddresses.fir_llki_base_addr, // Core Index 10 + CEPBaseAddresses.iir_llki_base_addr, // Core Index 11 + CEPBaseAddresses.gps_0_llki_base_addr, // Core Index 12 + CEPBaseAddresses.gps_1_llki_base_addr, // Core Index 13 + CEPBaseAddresses.gps_2_llki_base_addr, // Core Index 14 + CEPBaseAddresses.gps_3_llki_base_addr // Core Index 15 ) )) }) diff --git a/hdl_cores/freedom/src/main/scala/unleashed/DevKitFPGADesign.scala b/hdl_cores/freedom/src/main/scala/unleashed/DevKitFPGADesign.scala index 8508fcc..5613c2f 100644 --- a/hdl_cores/freedom/src/main/scala/unleashed/DevKitFPGADesign.scala +++ b/hdl_cores/freedom/src/main/scala/unleashed/DevKitFPGADesign.scala @@ -66,13 +66,15 @@ class DevKitWrapper()(implicit p: Parameters) extends LazyModule childClock := core.clock val djtag = topMod.module.debug.get.systemjtag.get - djtag.jtag.TCK := jt.get.jtag.TCK - djtag.jtag.TMS := jt.get.jtag.TMS - djtag.jtag.TDI := jt.get.jtag.TDI - jt.get.jtag.TDO.data := djtag.jtag.TDO.data - - djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) - djtag.reset := core.reset + djtag.jtag.TCK := jt.get.jtag.TCK + djtag.jtag.TMS := jt.get.jtag.TMS + djtag.jtag.TDI := jt.get.jtag.TDI + jt.get.jtag.TDO := djtag.jtag.TDO + + djtag.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W) + djtag.part_number := p(JtagDTMKey).idcodePartNum.U(16.W) + djtag.version := p(JtagDTMKey).idcodeVersion.U(4.W) + djtag.reset := core.reset childReset := core.reset | topMod.module.debug.get.ndreset } diff --git a/hdl_cores/gps/gps_mock_tss.sv b/hdl_cores/gps/gps_mock_tss.sv index 0eee22f..926aee9 100644 --- a/hdl_cores/gps/gps_mock_tss.sv +++ b/hdl_cores/gps/gps_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: gps_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/llki/llki_pp_wrapper.sv b/hdl_cores/llki/llki_pp_wrapper.sv index 53312fc..3c97801 100644 --- a/hdl_cores/llki/llki_pp_wrapper.sv +++ b/hdl_cores/llki/llki_pp_wrapper.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: llki_pp_wrapper.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/llki/mock_tss_fsm.sv b/hdl_cores/llki/mock_tss_fsm.sv index 8aaa1f1..cfdc84e 100644 --- a/hdl_cores/llki/mock_tss_fsm.sv +++ b/hdl_cores/llki/mock_tss_fsm.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: mock_tss_fsm.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/llki/scratchpad_wrapper.sv b/hdl_cores/llki/scratchpad_wrapper.sv index 78c0205..0105f5d 100644 --- a/hdl_cores/llki/scratchpad_wrapper.sv +++ b/hdl_cores/llki/scratchpad_wrapper.sv @@ -175,14 +175,14 @@ module scratchpad_wrapper import tlul_pkg::*; import llki_pkg::*; #( // Perform the remaining tilelink connections always_ff @(posedge clk or posedge rst) begin if (rst) begin - slave_tl_d2h_i.d_opcode = AccessAck; - slave_tl_d2h_i.d_param = '0; - slave_tl_d2h_i.d_size = '0; - slave_tl_d2h_i.d_source = '0; - slave_tl_d2h_i.d_sink = '0; - slave_tl_d2h_i.d_user = '0; - slave_tl_d2h_i.d_error = '0; - slave_tl_d2h_i.d_valid = '0; + slave_tl_d2h_i.d_opcode <= AccessAck; + slave_tl_d2h_i.d_param <= '0; + slave_tl_d2h_i.d_size <= '0; + slave_tl_d2h_i.d_source <= '0; + slave_tl_d2h_i.d_sink <= '0; + slave_tl_d2h_i.d_user <= '0; + slave_tl_d2h_i.d_error <= '0; + slave_tl_d2h_i.d_valid <= '0; end else begin // The following assingment methodology is borrowed from the tlul_adapter_reg component if ((slave_tl_h2d_o.a_opcode == PutFullData) | (slave_tl_h2d_o.a_opcode == PutPartialData)) @@ -190,14 +190,14 @@ module scratchpad_wrapper import tlul_pkg::*; import llki_pkg::*; #( else slave_tl_d2h_i.d_opcode <= AccessAckData; - slave_tl_d2h_i.d_param = '0; - slave_tl_d2h_i.d_size = slave_tl_h2d_o.a_size; - slave_tl_d2h_i.d_source = slave_tl_h2d_o.a_source; - slave_tl_d2h_i.d_sink = '0; - slave_tl_d2h_i.d_user = '0; - slave_tl_d2h_i.d_error = tl_err; + slave_tl_d2h_i.d_param <= '0; + slave_tl_d2h_i.d_size <= slave_tl_h2d_o.a_size; + slave_tl_d2h_i.d_source <= slave_tl_h2d_o.a_source; + slave_tl_d2h_i.d_sink <= '0; + slave_tl_d2h_i.d_user <= '0; + slave_tl_d2h_i.d_error <= tl_err; // We cannot process the response if not ready - slave_tl_d2h_i.d_valid = slave_tl_h2d_o.a_valid & slave_tl_d2h_i.a_ready; + slave_tl_d2h_i.d_valid <= slave_tl_h2d_o.a_valid & slave_tl_d2h_i.a_ready; end // end if (!rst_ni) end // always_ff @(posedge clk_i or negedge rst_ni) diff --git a/hdl_cores/llki/tlul_adapter_reg.sv b/hdl_cores/llki/tlul_adapter_reg.sv index 3fc0d63..05082b5 100644 --- a/hdl_cores/llki/tlul_adapter_reg.sv +++ b/hdl_cores/llki/tlul_adapter_reg.sv @@ -105,45 +105,45 @@ module tlul_adapter_reg import tlul_pkg::*; #( // everything is being moved here always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - outstanding_read <= '0; - outstanding_write <= '0; - req_id <= '0; - req_sz <= '0; - resp_opcode <= AccessAck; - error <= '0; - d_valid <= '0; - rdata <= '0; + outstanding_read <= '0; + outstanding_write <= '0; + req_id <= '0; + req_sz <= '0; + resp_opcode <= AccessAck; + error <= '0; + d_valid <= '0; + rdata <= '0; end else begin // Queue up some of the d channel response fields // Internal errors will be detected at the time A Channel is being processed if (a_ack) begin - req_id <= tl_i.a_source; - req_sz <= tl_i.a_size; - resp_opcode <= (rd_req) ? AccessAckData : AccessAck; // Return AccessAckData regardless of error - error <= err_internal; + req_id <= tl_i.a_source; + req_sz <= tl_i.a_size; + resp_opcode <= (rd_req) ? AccessAckData : AccessAck; // Return AccessAckData regardless of error + error <= err_internal; end; // Acknowledgements (reads and writes) need to be delayed // to allow higher level (external) decode to do things if (wr_req) begin - outstanding_write <= '1; + outstanding_write <= '1; end else if (rd_req) begin - outstanding_read <= '1; + outstanding_read <= '1; end // If a read is ongoing and has been acknowleedge, time // to assert valid on the D channel (and capture rdata and or in the external error) // Adding a_ack allows for zero-cycle decode on reads if (ack_i & (outstanding_read | a_ack)) begin - d_valid <= '1; - rdata <= rdata_i; - error <= error | error_i; + d_valid <= '1; + rdata <= rdata_i; + error <= error | error_i; // If a write is ongoing, just capture the valid and or in the external error) // Adding a_ack allows for zero-cycle decode on writes end else if (ack_i & (outstanding_write | a_ack)) begin - d_valid <= '1; - error <= error | error_i; + d_valid <= '1; + error <= error | error_i; end else if (tl_i.d_ready & (outstanding_read | outstanding_write)) begin outstanding_read <= '0; outstanding_write <= '0; @@ -180,6 +180,6 @@ module tlul_adapter_reg import tlul_pkg::*; #( `ASSERT_INIT(MatchedWidthAssert, RegDw == top_pkg::TL_DW) // Ensure we don't have an error asserted - `ASSERT(tlul_size_incorrect, !tl_o.d_error, clk_i, !rst_ni) + `ASSERT(tlul_d_channel_error, !tl_o.d_error, clk_i, !rst_ni) endmodule diff --git a/hdl_cores/llki/top_pkg.sv b/hdl_cores/llki/top_pkg.sv index 6bd5703..2f544b8 100644 --- a/hdl_cores/llki/top_pkg.sv +++ b/hdl_cores/llki/top_pkg.sv @@ -4,7 +4,7 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: top_pkg.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/md5/md5_mock_tss.sv b/hdl_cores/md5/md5_mock_tss.sv index 15d463e..d3f8475 100644 --- a/hdl_cores/md5/md5_mock_tss.sv +++ b/hdl_cores/md5/md5_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: md5_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/rsa/.DS_Store b/hdl_cores/rsa/.DS_Store index 8f9af28..1129f0c 100644 Binary files a/hdl_cores/rsa/.DS_Store and b/hdl_cores/rsa/.DS_Store differ diff --git a/hdl_cores/rsa/rtl/modexp_core_mock_tss.sv b/hdl_cores/rsa/rtl/modexp_core_mock_tss.sv index 1738247..1779c92 100644 --- a/hdl_cores/rsa/rtl/modexp_core_mock_tss.sv +++ b/hdl_cores/rsa/rtl/modexp_core_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: modexp_core_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/sha256/sha256_mock_tss.sv b/hdl_cores/sha256/sha256_mock_tss.sv index 75d196d..580fb91 100644 --- a/hdl_cores/sha256/sha256_mock_tss.sv +++ b/hdl_cores/sha256/sha256_mock_tss.sv @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: sha256_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/hdl_cores/shaaa/.DS_Store b/hdl_cores/shaaa/.DS_Store index 663bbe7..0f263ab 100644 Binary files a/hdl_cores/shaaa/.DS_Store and b/hdl_cores/shaaa/.DS_Store differ diff --git a/hdl_cores/shaaa/templates/shaaa_mock_tss.svt b/hdl_cores/shaaa/templates/shaaa_mock_tss.svt index 1d010c8..5600450 100644 --- a/hdl_cores/shaaa/templates/shaaa_mock_tss.svt +++ b/hdl_cores/shaaa/templates/shaaa_mock_tss.svt @@ -1,6 +1,6 @@ //************************************************************************ // Copyright 2021 Massachusetts Institute of Technology -// SPDX License Identifier: MIT +// SPDX License Identifier: BSD-2-Clause // // File Name: {MODULE_NAME}_mock_tss.sv // Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/.DS_Store b/unit_simulation/.DS_Store index 85ea79c..80edc74 100644 Binary files a/unit_simulation/.DS_Store and b/unit_simulation/.DS_Store differ diff --git a/unit_simulation/TL_level_sim/.DS_Store b/unit_simulation/TL_level_sim/.DS_Store index 955f82c..ea2d0e3 100644 Binary files a/unit_simulation/TL_level_sim/.DS_Store and b/unit_simulation/TL_level_sim/.DS_Store differ diff --git a/unit_simulation/TL_level_sim/Makefile b/unit_simulation/TL_level_sim/Makefile index 72cf31f..76076fd 100644 --- a/unit_simulation/TL_level_sim/Makefile +++ b/unit_simulation/TL_level_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/aes_sim/Makefile b/unit_simulation/aes_sim/Makefile index c9eddf8..e9cbf24 100644 --- a/unit_simulation/aes_sim/Makefile +++ b/unit_simulation/aes_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/des3_sim/Makefile b/unit_simulation/des3_sim/Makefile index 6a64fa4..88b3b51 100644 --- a/unit_simulation/des3_sim/Makefile +++ b/unit_simulation/des3_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/dft_sim/Makefile b/unit_simulation/dft_sim/Makefile index e91bd9b..9378491 100644 --- a/unit_simulation/dft_sim/Makefile +++ b/unit_simulation/dft_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/fir_sim/Makefile b/unit_simulation/fir_sim/Makefile index 5a4a948..36297f7 100644 --- a/unit_simulation/fir_sim/Makefile +++ b/unit_simulation/fir_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/gps_sim/Makefile b/unit_simulation/gps_sim/Makefile index 9fc417e..68d4a21 100644 --- a/unit_simulation/gps_sim/Makefile +++ b/unit_simulation/gps_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/idft_sim/Makefile b/unit_simulation/idft_sim/Makefile index f64a134..27846d9 100644 --- a/unit_simulation/idft_sim/Makefile +++ b/unit_simulation/idft_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/iir_sim/Makefile b/unit_simulation/iir_sim/Makefile index 84eca7e..61b8fd9 100644 --- a/unit_simulation/iir_sim/Makefile +++ b/unit_simulation/iir_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/md5_sim/Makefile b/unit_simulation/md5_sim/Makefile index 7dd4463..a689063 100644 --- a/unit_simulation/md5_sim/Makefile +++ b/unit_simulation/md5_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/rsa_sim/Makefile b/unit_simulation/rsa_sim/Makefile index 81fe8ab..26d343d 100644 --- a/unit_simulation/rsa_sim/Makefile +++ b/unit_simulation/rsa_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP) diff --git a/unit_simulation/sha256_sim/Makefile b/unit_simulation/sha256_sim/Makefile index da1040d..6e5eb10 100644 --- a/unit_simulation/sha256_sim/Makefile +++ b/unit_simulation/sha256_sim/Makefile @@ -1,6 +1,6 @@ #//************************************************************************ #// Copyright 2021 Massachusetts Institute of Technology -#// SPDX License Identifier: MIT +#// SPDX License Identifier: BSD-2-Clause #// #// File Name: Makefile #// Program: Common Evaluation Platform (CEP)