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Roarin committed Jun 24, 2016
1 parent 6d79ee2 commit 01fcdd0
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Showing 2 changed files with 47 additions and 17 deletions.
13 changes: 7 additions & 6 deletions examples/uart_main/uart_main.c
Original file line number Diff line number Diff line change
Expand Up @@ -22,19 +22,20 @@

//Macros for generating function names
#define CREATE_FAST_UART(uart_name,tx_pin) #uart_name#tx_pin"init()"
#define SEND_FAST_UART(uart_name,tx_pin) uart_name##tx_pin##_tx
#define SEND_FAST_UART(uart_name,tx_pin) uart_name##tx_pin##_tx

//Used for setting the baud rate.
//Currently unimplemented
enum uart_baud baud;
void main(void)
{
baud = BAUD_115200;
baud = BAUD_19200;
uartX_init(baud);
baud = BAUD_19200;
uartX_set_baud(baud);
while (TRUE)
{
printf("Hello");
}
{
printf("Hello");
}
}

void putchar(char c)
Expand Down
51 changes: 40 additions & 11 deletions lib/uart/soft_uart.c
Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,11 @@
**/
#include <fx2regs.h>
#include <fx2macros.h>
#include <serial.h>
#include <uart/api.h>
#include <assert.h>



/*This is set by calling the uartX_set_baud() function.*/
unsigned char load_delay;
BOOL uartX_init(enum uart_baud rate, ...)
{
//All delay values assume a 48MHZ clock.
Expand Down Expand Up @@ -48,7 +48,7 @@ void uartX_tx(char c)
//At 12Mhz, it should be about 83.33ns
//But it appears to be about 88ns
//These numbers have been verified using an analyzer
mov r1, #0x20 //(2 cycles)
mov r1, _load_delay //(2 cycles)
0006$:
//1 bit is about 8.6us
djnz r1, 0006$ //DJNZ on Rn takes (3 cycles)
Expand All @@ -62,7 +62,7 @@ void uartX_tx(char c)
//Move the carry into the port
mov _TX_PIN, c //(2 cycles)
//Now we need to add delay for the next
mov r1, #0x1F //(2 cycles)
mov r1, _load_delay //(2 cycles)
//31*3 , 93 cycles of delay
0004$:
djnz r1, 0004$ //(3 cycles)
Expand All @@ -72,17 +72,46 @@ void uartX_tx(char c)
djnz r0, 0001$ //(3 cycles)
setb _TX_PIN //(2 cycles) This is for stop bit
//We need to delay the stop bit, otherwise we may get errors.
mov r1, #0x20 //(2 cycles)
mov r1, _load_delay//(2 cycles)
0005$:
djnz r1, 0005$ //(3 cycles) for DJNZ , Jump for 32*3 , 96 cycles
djnz r1, 0005$ //(3 cycles) for DJNZ , Jump for 32*3 , 96 cycles
nop //(NOP takes 1 cycle) 97 cycles of delay
setb _EA; //Enable back the interrupts
__endasm;
}

BOOL uartX_set_baud(enum uart_baud rate)
{
return FALSE;
switch(rate)
{
case BAUD_2400:
load_delay = 0xd0;
break;
case BAUD_4800:
break;
case BAUD_9600:
break;
case BAUD_19200:
load_delay = 0xd0;
break;
case BAUD_38400:
load_delay = 0x68;
break;
case BAUD_57600:
load_delay = 0x45;
break;
case BAUD_115200:
load_delay = 0x20;
break;
case BAUD_ANY:
break;
case BAUD_FASTEST:
break;
default:
load_delay = 0x20;
break;
}
return TRUE;
}

enum uart_baud uartX_get_baud()
Expand All @@ -98,17 +127,17 @@ BOOL uartX_tx_willblock()
char uartX_rx()
{
//This function should never be called
assert(FALSE);
return 0xFF;
}

BOOL uartX_check_rx_blocking()
{
//Doesnt really matter what we send here
return FALSE;
return TRUE;
}

BYTE uartX_check_receive_buffer()
{
//Read not implemented. Always return a 0.
//Read not implemented.No data is present in the buffer
return 0x00;
}

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