Logic BIST implementation for the cv32e40p (ex RI5CY) processor.
The circuit has been modified during synthesis to improve DfT. In particular:
- Scan chain insertion (64 scan chains with shared SI/SO signals).
- Test Point Insertion (about 3800).
The LBIST architecture is composed by:
- 64-bit LFSR, as a PRNG
- Phase Shifter, to reduce scan chain correlation and also feed the PIs
- ROM for storing Re-seeding vectors
- Space Compactor, to reduce the number of MISR's bits from 231 to 64
- 64 bit MISR
- LBIST Controller, implemented as an HLSM
The achieved Fault Coverage for this implementation is:
| Type | FC |
|---|---|
| Stuck-at Faults | 89.91% |
| Transition Delay Faults | 85.18% |
- compile_testbench.sh : compiles all the required files to run the simulation of the core with LBIST
- compile_sbst.sh : compiles the firmware that will be used when the LBIST returns OK
- run_gate_gui.sh : runs the simulation of the core with LBIST. Launches a firmware if test is OK
- run_gate_nogui.sh : same as before but only in CLI
- run_syn.sh : synthesis of the standard core
- run_scan_insertion.sh : inserts scan chains and test points
- run_syn_bist.sh : synthesys of the final core wrapper which includes all the LBIST modules and the core quipped with DfT
- simulation.sh : compiles a simple testbench with only LFSR, PHASE SHIFTER and Core to compute the test patterns. Its VCD output has to be applied to Tmax for Fault Coverage evaluation.
- run_fsim.sh : executes fault simulation on patterns generated by the previous script. Both stuck-at fault and transition delay faults. In the end, it runs incremental ATPG.
- clean_all.sh : cleans all the work files
- riscv_core_dumpports.vcd : output vcd for the fault simulation, generated from simulation.sh script
- dumpports_gate.evcd : output vcd from the Core w/ LBIST simulation, generated by the run_gate_nogui.sh/run_gate_gui.sh scripts.