Risc-V Processor

RV32I Single Cycle Processor

git clone --recursive git@github.com:mmxsrup/riscv-processor.git

Create a binary file for testing

cd ./riscv-tests/isa/
make XLEN=32
cd -

Create vivado project

make create_project

Execute simulation

make simulation

Confirm test results

more tests/testlog.txt

Provide feedback