Merge pull request #3 from georgevangelou/master

Sync with upstream

.gitattributes

@@ -0,0 +1,11 @@
+9.Zynq/Zynq_lenet/AXI_lenet_ip/hdl/* linguist-vendored  
+9.Zynq/Zynq_lenet/AXI_lenet_ip/hdl/** linguist-vendored  
+9.Zynq/Zynq_lenet/ER_lenet.sdk/ER_lenet_SDK_bsp/* linguist-vendored  
+9.Zynq/Zynq_lenet/ER_lenet.sdk/ER_lenet_SDK_bsp/** linguist-vendored  
+
+9.Zynq/Zynq_lenet/ER_lenet.sdk/webtalk/usage_statistics_ext_sdk.html -linguist-vendored  
+9.Zynq/Zynq_lenet/ER_lenet.sdk/webtalk/usage_statistics_ext_sdk.html linguist-vendored  
+9.Zynq/Zynq_lenet/ER_lenet.sdk/design_1_wrapper_hw_platform_0/ps7_init.html -linguist-vendored  
+9.Zynq/Zynq_lenet/ER_lenet.sdk/design_1_wrapper_hw_platform_0/ps7_init.html linguist-vendored  
+9.Zynq/Zynq_lenet/ER_lenet.sdk/webtalk/sdk_webtalk.tcl -linguist-vendored  
+9.Zynq/Zynq_lenet/ER_lenet.sdk/webtalk/sdk_webtalk.tcl linguist-vendored  

README.md

@@ -5,8 +5,8 @@ This framework was part of the **Diploma thesis** titled "Architectures and Impl
 The **main goal** of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.
 
 The **authors** of this thesis were (in alphabetical order):
-- George Evangelou (Dipl. Eng. Electrical and Computer Engineering Department, Univ. of Patras, Greece)
-  - Email: george_evangelou [at] windowslive.com
+- Georgios Evangelou (Dipl. Eng. Electrical and Computer Engineering Department, Univ. of Patras, Greece)
+  - Email: gevangelou [at] hotmail.com
   - [LinkedIn profile](https://www.linkedin.com/in/georgios-evangelou-2a389b167/)
 - Nick Roussos (Dipl. Eng. Electrical and Computer Engineering Department, Univ. of Patras, Greece)
   - Email: nroussos97 [at] gmail.com