Designed a basic computer that called RISCQ. RISCQ has registers, two memories, arithmetic and logic unit, control unit and bus system.
Contents
- Registers
- Memories
- Common Bus System
- Arithmetic and Logic Unit
- Instruction set and micro-operations table
- Control Unit
- Combined all components
- Compling and Running
RISCQ has 9 registers which are Address Register, Program Counter, Input Register, Output Register, Instruction Register and 4 general purpose registers.
Register Symbol | Register name | Number of bits | Function |
---|---|---|---|
AR | Address Register | 5 | Holds address for data memory. It can be cleared with related control signal. |
PC | Program Counter | 5 | Holds address of instruction. It can be cleared and increase by one with related control signals. |
IR | Instruction Register | 11 | Holds instruction code |
InpR | Input Register | 4 | Holds input data |
OutR | Output Register | 4 | Holds output data |
R0, R1, R2, R3 | General Purposed Registers | 4 | Holds operands and other data |
In RISCQ there is two memories which are instruction and data memories. Each has read enable and data inputs. Data memory has also write enable input.
- Instruction Memory (32x11)
- Data Memory (32x4)
Common bus system will be responsible for data flow and provide data transfer between register and/or memories.
So after all; Memories and Registers in the BUS system looks like that;
In ALU, arithmetic and logical operations will be held. Its block diagram like that;
The ALU supports following operations;
Actually the ALU configrated like that;
Control unit processes instructions to direct the micro-operations for computer's memories, registers and arithmetic/logic unit. Control unit consists of decoders and a number of control logic gates. It should produce operation signals and time periods for fetching, decoding and executing the instructions.
Control Unit Figure;
- Also Sequences Counter Clear
- LOAD
- READ
Theoretically Figured
When all components combined, system looks like that;