You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
This is probably the way it should technically be, but I'm unsure of a reasonable way to do it nicely.
Take the PSG for example. In reality, there is no ff880x address known to it. GLUE maps that address to the SNDCS which combines with A1 and RW to BC1 and BDIR.
Today this is done by the PSG actually receiving the entire address and reading/writing the 8 bits of the data bus it's connected to.
Maybe a sensible way is to make this into four calls:
psg_nop() - read from ff8800 (does nothing)
psg_read_reg() - read from ff8802
psg_select_reg() - write to ff8800
psg_write_reg() - write to ff8802
Will the memory map still be used, and this only being a source code construct? Should the memory map change into the address decoding done in the GLUE?
Bus error → GLUE
Shouldn't be a problem I guess
Address error → CPU
This should never leave the CPU, so I can't see how it can be handled any other way.
Persistent state.
??
Interrupts.
IPL1/2 are connected to GLUE, so in principle they should be handled that way too.
The MMU has a lot of code that probably belongs elsewhere. We should agree on what, and where.
The text was updated successfully, but these errors were encountered: