tests: samples: Align tests and samples files for nrf54l15dk target

Align all existing samples/tests/applications which
contains nrf54l15pdk/nrf54l15/cpuapp by adding
nrf54l15dk/nrf54l15/cpuapp to enable twister builds
for new target.

Related: NCSDK-28998

Signed-off-by: Katarzyna Giądła <katarzyna.giadla@nordicsemi.no>

applications/sw_io_devices/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr.conf

@@ -0,0 +1,44 @@
+# Single-threaded
+CONFIG_MULTITHREADING=n
+CONFIG_KERNEL_MEM_POOL=n
+CONFIG_LOG=n
+
+# Drivers and peripherals
+CONFIG_I2C=n
+CONFIG_WATCHDOG=n
+CONFIG_GPIO=n
+CONFIG_PINCTRL=n
+CONFIG_SPI=n
+CONFIG_SERIAL=n
+CONFIG_FLASH=n
+
+# Power management
+CONFIG_PM=n
+
+# Interrupts
+CONFIG_DYNAMIC_INTERRUPTS=n
+CONFIG_IRQ_OFFLOAD=n
+
+# Memory protection
+CONFIG_THREAD_STACK_INFO=n
+CONFIG_THREAD_CUSTOM_DATA=n
+CONFIG_FPU=n
+
+# Boot
+CONFIG_BOOT_BANNER=n
+
+# Console
+CONFIG_CONSOLE=n
+CONFIG_UART_CONSOLE=n
+CONFIG_STDOUT_CONSOLE=n
+CONFIG_PRINTK=n
+CONFIG_EARLY_CONSOLE=n
+
+# Build
+CONFIG_SIZE_OPTIMIZATIONS=y
+
+# No timer support in the kernel
+CONFIG_SYS_CLOCK_EXISTS=n
+
+CONFIG_OUTPUT_DISASSEMBLY=y
+CONFIG_COMMON_LIBC_MALLOC=n

applications/sw_io_devices/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_rx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 15>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "disabled";
+};
+
+&gpio2 {
+	status = "disabled";
+};
+
+&gpiote20 {
+	status = "disabled";
+};
+
+&gpiote30 {
+	status = "disabled";
+};
+
+&grtc {
+	status = "disabled";
+};
+
+&uart20 {
+	status = "disabled";
+};
+
+&uart30 {
+	status = "disabled";
+};
+
+&pwm20 {
+	status = "disabled";
+};

applications/sw_io_devices/gpio/sample.yaml

@@ -3,10 +3,11 @@ sample:
   description: SW-defined GPIO application
 common:
   integration_platforms:
+    - nrf54l15dk/nrf54l15/cpuflpr
     - nrf54l15pdk/nrf54l15/cpuflpr
 tests:
   applications.sw_io_devices.egpio:
     sysbuild: true
     build_only: true
-    platform_allow: nrf54l15pdk/nrf54l15/cpuflpr
+    platform_allow: nrf54l15dk/nrf54l15/cpuflpr nrf54l15pdk/nrf54l15/cpuflpr
     tags: ci_build sysbuild

boards/shields/nrf700x_nrf54l15dk/Kconfig.defconfig

@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+if SHIELD_NRF700X_NRF54L15DK
+
+config NETWORKING
+	default y
+
+config WIFI
+	default y
+
+config WIFI_NRF700X
+	default y
+
+config NRFX_GPIOTE
+	default y
+
+endif #SHIELD_NRF700X_NRF54L15DK

boards/shields/nrf700x_nrf54l15dk/Kconfig.shield

@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+DT_COMPAT_NORDIC_NRF700X_QSPI := nordic,nrf700x-qspi
+DT_COMPAT_NORDIC_NRF700X_SPI := nordic,nrf700x-spi
+
+config SHIELD_NRF700X_NRF54L15DK
+	select NRF_WIFI_COMBINED_BUCKEN_IOVDD_GPIO
+	def_bool $(shields_list_contains,nrf700x_nrf54l15dk)
+
+config NRF7002_ON_QSPI
+	def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF700X_QSPI))
+	depends on SHIELD_NRF700X_NRF54L15DK
+
+config NRF7002_ON_SPI
+	def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF700X_SPI))
+	depends on SHIELD_NRF700X_NRF54L15DK

boards/shields/nrf700x_nrf54l15dk/boards/nrf54l15dk_nrf54l15_cpuapp.conf

@@ -0,0 +1,5 @@
+# This is to get both Legacy and PSA to work, for Wi-Fi
+CONFIG_TRUSTED_STORAGE=y
+CONFIG_PSA_CRYPTO_DRIVER_OBERON=y
+CONFIG_PSA_CRYPTO_DRIVER_CRACEN=n
+CONFIG_TRUSTED_STORAGE_BACKEND_AEAD_KEY_HASH_UID=y

boards/shields/nrf700x_nrf54l15dk/nrf700x_nrf54l15dk.overlay

@@ -0,0 +1,81 @@
+/* Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include <freq.h>
+
+/ {
+	/* Wi-Fi doesn't needs this and it frees up 68K RAM */
+	/delete-node/ cpuflpr_sram;
+	nordic_wlan0: nordic_wlan0 {
+			compatible = "nordic,wlan0";
+			status = "okay";
+	};
+
+	chosen {
+		zephyr,wifi = &nordic_wlan0;
+	};
+
+	nrf70_tx_power_ceiling: nrf70_tx_power_ceiling_node {
+		status = "okay";
+		compatible = "nordic,nrf700x-tx-power-ceiling";
+		max-pwr-2g-dsss = <0x54>;
+		max-pwr-2g-mcs0 = <0x40>;
+		max-pwr-2g-mcs7 = <0x40>;
+		max-pwr-5g-low-mcs0 = <0x34>;
+		max-pwr-5g-low-mcs7 = <0x34>;
+		max-pwr-5g-mid-mcs0 = <0x34>;
+		max-pwr-5g-mid-mcs7 = <0x34>;
+		max-pwr-5g-high-mcs0 = <0x30>;
+		max-pwr-5g-high-mcs7 = <0x30>;
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+	ranges = <0x0 0x20000000 0x20040000>;
+};
+
+&pinctrl {
+	spi22_default: spi22_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 11)>,
+				<NRF_PSEL(SPIM_MISO, 1, 9)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 10)>;
+		};
+	};
+
+	spi22_sleep: spi22_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 11)>,
+				<NRF_PSEL(SPIM_MISO, 1, 9)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 10)>;
+			low-power-enable;
+		};
+	};
+};
+
+/* With P1 only SPI20/21/22 are allowed and SPI20 uses same IRQ as UART20 */
+&spi22 {
+	status = "okay";
+	cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&spi22_default>;
+	pinctrl-1 = <&spi22_sleep>;
+	pinctrl-names = "default", "sleep";
+	nrf700x: nrf7002@0 {
+		compatible = "nordic,nrf700x-spi";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(8)>;
+		bucken-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+		iovdd-ctrl-gpios = <&gpio1 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+		host-irq-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+
+&gpio1 {
+	status = "okay";
+};

boards/shields/pca63565/boards/nrf54l15dk_nrf54l15_cpuapp.overlay

@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	aliases {
+		sensor-bme688 = &i2c22;
+		accel0 = &adxl362;
+		accel-gyro = &bmi270;
+		/delete-property/ led2;
+		/delete-property/ led3;
+		/delete-property/ sw3;
+	};
+};
+
+/delete-node/ &led2;	// P1.13 is bmi270 chip select signal
+/delete-node/ &led3;	// P1.14 is adxl362 interrupt signal
+/delete-node/ &button3; // P2.10 is adxl362 chip select signal
+
+&pinctrl {
+	i2c22_default: i2c22_default {
+		group1  {
+			psels = <NRF_PSEL(TWIM_SCL, 1, 11)>,
+					<NRF_PSEL(TWIM_SDA, 1, 12)>;
+		};
+	};
+
+	i2c22_sleep: i2c22_sleep {
+		group1  {
+			psels = <NRF_PSEL(TWIM_SCL, 1, 11)>,
+					<NRF_PSEL(TWIM_SDA, 1, 12)>;
+			low-power-enable;
+		};
+	};
+
+	spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+					<NRF_PSEL(SPIM_MISO, 2, 9)>,
+					<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+		};
+	};
+
+	spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+					<NRF_PSEL(SPIM_MISO, 2, 9)>,
+					<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c22 {
+	status = "okay";
+	zephyr,concat-buf-size = <512>;
+	pinctrl-0 = <&i2c22_default>;
+	pinctrl-1 = <&i2c22_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	bme688: bme688@76 {
+		compatible = "bosch,bme680";
+		status = "okay";
+		reg = <0x76>;
+	};
+};
+
+&spi00 {
+	status = "okay";
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+	cs-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>,
+			   <&gpio2 10 GPIO_ACTIVE_LOW>;
+
+	bmi270: bmi270@0 {
+		compatible = "bosch,bmi270";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(8)>;
+	};
+
+	adxl362: adxl362@1 {
+		compatible = "adi,adxl362";
+		status = "okay";
+		reg = <1>;
+		int1-gpios = <&gpio1 14 (GPIO_ACTIVE_HIGH)>;
+		spi-max-frequency = <DT_FREQ_M(8)>;
+	};
+};