diff --git a/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.conf b/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..ce329bf1642
--- /dev/null
+++ b/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+CONFIG_GPIO_NRFE_EGPIO_BACKEND_ICBMSG=y
diff --git a/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..d690da02d0c
--- /dev/null
+++ b/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			cpuflpr_code_partition: image@165000 {
+				/* FLPR core code partition */
+				reg = <0x165000 DT_SIZE_K(96)>;
+			};
+
+			sram_rx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_tx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+
+
+		cpuflpr_sram_code_data: memory@20028000 {
+			compatible = "mmio-sram";
+			reg = <0x20028000 DT_SIZE_K(96)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x20028000 0x18000>;
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icbmsg";
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			tx-blocks = <16>;
+			rx-blocks = <18>;
+			mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(160)>;
+	ranges = <0x0 0x20000000 0x28000>;
+};
+
+&cpuflpr_vpr {
+	execution-memory = <&cpuflpr_sram_code_data>;
+	source-memory = <&cpuflpr_code_partition>;
+};
+
+&gpio2 {
+	status = "disabled";
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
+
+&egpio {
+	status = "okay";
+};
diff --git a/snippets/emulated-gpio/icbmsg/emulated-gpio.overlay b/snippets/emulated-gpio/icbmsg/emulated-gpio.overlay
new file mode 100644
index 00000000000..ebcb50a19fa
--- /dev/null
+++ b/snippets/emulated-gpio/icbmsg/emulated-gpio.overlay
@@ -0,0 +1,17 @@
+/* Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+&cpuflpr_vpr {
+    status = "okay";
+
+    egpio: gpio {
+        compatible = "nordic,nrf-egpio";
+        gpio-controller;
+        #gpio-cells = <0x2>;
+        ngpios = <0x10>;
+        status = "disabled";
+        port = <0x2>;
+    };
+};
diff --git a/snippets/emulated-gpio/icbmsg/snippet.yml b/snippets/emulated-gpio/icbmsg/snippet.yml
new file mode 100644
index 00000000000..e28faac7049
--- /dev/null
+++ b/snippets/emulated-gpio/icbmsg/snippet.yml
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+
+name: emulated-gpio-icbmsg
+append:
+  EXTRA_DTC_OVERLAY_FILE: emulated-gpio.overlay
+
+boards:
+  nrf54l15dk/nrf54l15/cpuapp:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
+      EXTRA_CONF_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.conf