diff --git a/.github/test-spec.yml b/.github/test-spec.yml new file mode 100644 index 00000000000..63a29824c11 --- /dev/null +++ b/.github/test-spec.yml @@ -0,0 +1,406 @@ +# This is the Jenkins ci variant of the .github/labler.yaml + +"CI-run-zephyr-twister": + - any: + - "!.github/**/*" + - "!doc/**/*" + - "!CODEOWNERS" + - "!LICENSE" + - "!**/*.rst" + - "!VERSION" + - "!submanifests/**/*" + - "!MAINTAINERS.yml" + - "!version.h.in" + - "!Jenkinsfile" + - "!**/*.md" + +"CI-iot-zephyr-lwm2m-test": + - "drivers/console/**/*" + - "drivers/flash/**/*" + - "subsys/dfu/boot/**/*" + - "subsys/net/ip/**/*" + - "subsys/net/lib/http/**/*" + - "subsys/net/lib/lwm2m//**/*" + - "subsys/net/**/*" + +"CI-iot-samples-test": + - "boards/nordic/nrf9160dk/**/*" + - "dts/arm/nordic/nrf9160*" + - "include/net/**/*" + - "subsys/net/lib/**/*" + +"CI-iot-libraries-test": + - "boards/nordic/nrf9160dk/**/*" + - "dts/arm/nordic/nrf9160*" + - "include/net/socket_ncs.h" + - "subsys/testsuite/ztest/**/*" + +"CI-lwm2m-test": null +# Not necessary to run tests on changes to this repo. + +"CI-boot-test": + - "subsys/mgmt/mcumgr/**/*" + - "subsys/dfu/**/*" + - "include/mgmt/mcumgr/**/*" + - "include/dfu/**/*" + - "samples/subsys/mgmt/mcumgr/smp_svr/**/*" + - "tests/boot/**/*" + - "tests/subsys/dfu/**/*" + - "tests/subsys/mgmt/mcumgr/**/*" + +"CI-tfm-test": + - "boards/nordic/nrf5340dk/**/*" + - "boards/nordic/nrf9160dk/**/*" + - "drivers/entropy/*" + - "dts/arm/nordic/nrf5340*" + - "dts/arm/nordic/nrf9160*" + - "modules/trusted-firmware-m/**/*" + - "samples/tfm_integration/**/*" + +"CI-ble-test": + - any: + - "drivers/bluetooth/**/*" + - any: + - "dts/arm/nordic/nrf5*" + - any: + - "subsys/bluetooth/**/*" + - "!subsys/bluetooth/mesh/**/*" + - "!subsys/bluetooth/audio/**/*" + - any: + - "include/zephyr/bluetooth/**/*" + - "!include/zephyr/bluetooth/mesh/**/*" + - "samples/bluetooth/hci_ipc/**/*" + +"CI-ble-samples-test": + - any: + - "drivers/bluetooth/**/*" + - any: + - "dts/arm/nordic/nrf5*" + - any: + - "subsys/bluetooth/**/*" + - "!subsys/bluetooth/mesh/**/*" + - "!subsys/bluetooth/audio/**/*" + - any: + - "include/zephyr/bluetooth/**/*" + - "!include/zephyr/bluetooth/mesh/**/*" + - "samples/bluetooth/**/*" + +"CI-mesh-test": + - "subsys/bluetooth/mesh/**/*" + - "include/zephyr/bluetooth/mesh/**/*" + - "samples/bluetooth/mesh/**/*" + - "samples/bluetooth/mesh_demo/**/*" + - "samples/bluetooth/mesh_provisioner/**/*" + - "tests/bluetooth/mesh/**/*" + - "tests/bluetooth/mesh_shell/**/*" + +"CI-zigbee-test": + - "subsys/mgmt/mcumgr/**/*" + - "subsys/dfu/**/*" + - "include/mgmt/mcumgr/**/*" + - "include/dfu/**/*" + +"CI-thingy91-test": + - "boards/nordic/nrf9160dk/**/*" + - "arch/x86/core/**/*" + - "arch/x86/include/**/*" + - "drivers/console/**/*" + - "drivers/ethernet/**/*" + - "drivers/flash/**/*" + - "drivers/hwinfo/**/*" + - "drivers/interrupt_controller/**/*" + - "drivers/net/**/*" + - "drivers/serial/**/*" + - "drivers/timer/**/*" + - "include/**/*" + - "kernel/**/*" + - "lib/libc/common/source/stdlib/**/*" + - "lib/libc/newlib/**/*" + - "lib/libc/picolibc/**/*" + - "lib/os/**/*" + - "lib/posix/**/*" + - "misc/**/*" + - "modules/mbedtls/**/*" + - "soc/x86/ia32/**/*" + - "subsys/fs/fcb/**/*" + - "subsys/logging/**/*" + - "subsys/net/**/*" + - "subsys/random/**/*" + - "subsys/settings/include/**/*" + - "subsys/settings/src/**/*" + - "subsys/stats/**/*" + - "subsys/storage/flash_map/**/*" + - "subsys/storage/stream/**/*" + - "subsys/tracing/**/*" + +"CI-desktop-test": + - "drivers/bluetooth/*" + - "subsys/bluetooth/*" + - "include/zephyr/bluetooth/*" + +"CI-crypto-test": + - "boards/nordic/nrf52840dk/**/*" + - "boards/nordic/nrf5340dk/**/*" + - "boards/nordic/nrf9160dk/**/*" + - "drivers/entropy/*" + - "drivers/serial/**/*" + - "dts/arm/nordic/nrf52840*" + - "dts/arm/nordic/nrf5340*" + - "dts/arm/nordic/nrf9160*" + - "include/drivers/serial/**/*" + - "modules/mbedtls/**/*" + +"CI-fem-test": + - "boards/nordic/**/*" + - "drivers/bluetooth/hci/**/*" + - "drivers/entropy/**/*" + - "dts/bindings/**/*" + - "include/zephyr/net/**/*" + - "include/zephyr/arch/**/*" + - "lib/libc/**/*" + - "lib/open-amp/**/*" + - "modules/hal_nordic/**/*" + - "modules/mbedtls/**/*" + - "modules/openthread/**/*" + - "modules/trusted-firmware-m/**/*" + - "samples/net/sockets/echo_*/**/*" + - "share/**/*" + - "soc/nordic/**/*" + - "subsys/net/**/*" + - "subsys/settings/**/*" + - "subsys/bluetooth/shell/**/*" + - "subsys/ipc/**/*" + - "Kconfig" + - "CMakeLists.txt" + +"CI-rs-test": + - "boards/nordic/**/*" + - "drivers/bluetooth/hci/**/*" + - "drivers/entropy/**/*" + - "dts/bindings/**/*" + - "include/zephyr/net/**/*" + - "include/zephyr/arch/**/*" + - "lib/libc/**/*" + - "lib/open-amp/**/*" + - "modules/hal_nordic/**/*" + - "modules/mbedtls/**/*" + - "modules/openthread/**/*" + - "modules/trusted-firmware-m/**/*" + - "samples/net/sockets/echo_*/**/*" + - "share/**/*" + - "soc/nordic/**/*" + - "subsys/net/**/*" + - "subsys/settings/**/*" + - "subsys/bluetooth/shell/**/*" + - "subsys/ipc/**/*" + - "Kconfig" + - "CMakeLists.txt" + +"CI-thread-test": + - "include/zephyr/net/**/*" + - "modules/mbedtls/**/*" + - "modules/openthread/**/*" + - "samples/net/openthread/**/*" + - "soc/nordic/**/*" + - "subsys/net/**/*" + - "subsys/settings/**/*" + +"CI-nfc-test": + - "drivers/bluetooth/hci/**/*" + - "drivers/entropy/**/*" + - "drivers/flash/**/*" + - "drivers/mbox/**/*" + - "drivers/spi/**/*" + - "lib/crc/**/*" + - "modules/hal_nordic/**/*" + - "soc/nordic/**/*" + - "subsys/bluetooth/**/*" + - "subsys/ipc/ipc_service/**/*" + - "subsys/fs/**/*" + - "subsys/mem_mgmt/**/*" + - "subsys/net/**/*" + - "subsys/random/**/*" + - "subsys/settings/**/*" + - "subsys/shell/**/*" + - "subsys/storage/**/*" + +"CI-matter-test": + - "include/dfu/**/*" + - "include/mgmt/mcumgr/**/*" + - "soc/nordic/**/*" + - "subsys/dfu/**/*" + - "subsys/settings/**/*" + - "subsys/net/**/*" + - "subsys/mgmt/mcumgr/**/*" + - "drivers/net/**/*" + - "samples/bluetooth/hci_ipc/**/*" + - any: + - "subsys/bluetooth/**/*" + - "!subsys/bluetooth/mesh/**/*" + - "!subsys/bluetooth/audio/**/*" + +"CI-find-my-test": + - "boards/nordic/**/*" + - "drivers/bluetooth/**/*" + - "drivers/entropy/**/*" + - "drivers/flash/**/*" + - "drivers/usb/**/*" + - "drivers/regulator/**/*" + - "soc/nordic/**/*" + - "subsys/bluetooth/**/*" + - "subsys/dfu/**/*" + - "subsys/fs/**/*" + - "subsys/ipc/**/*" + - "subsys/net/**/*" + - "subsys/random/**/*" + - "subsys/settings/**/*" + - "subsys/storage/**/*" + - "subsys/tracing/**/*" + - "subsys/usb/device/**/*" + +"CI-rpc-test": + - "subsys/ipc/ipc_service/**/*" + - "subsys/random/**/*" + - "soc/nordic/nrf53/**/*" + +"CI-modemshell-test": + - "include/net/**/*" + - "include/posix/**/*" + - "include/shell/**/*" + - "drivers/net/**/*" + - "drivers/serial/**/*" + - "drivers/wifi/**/*" + - "subsys/shell/**/*" + - "subsys/net/**/*" + - "subsys/settings/**/*" + +"CI-positioning-test": + - "include/net/**/*" + - "include/posix/**/*" + - "drivers/net/**/*" + - "drivers/wifi/**/*" + - "subsys/net/**/*" + - "subsys/settings/**/*" + +"CI-cloud-test": + - "include/zephyr/dfu/**/*" + - "include/zephyr/net/**/*" + - "include/zephyr/posix/**/*" + - "include/zephyr/settings/**/*" + - "drivers/led/**/*" + - "drivers/net/**/*" + - "drivers/sensor/**/*" + - "drivers/serial/**/*" + - "drivers/wifi/**/*" + - "lib/posix/**/*" + - "soc/nordic/**/*" + - "subsys/dfu/**/*" + - "subsys/net/**/*" + - "subsys/settings/**/*" + +"CI-wifi": + - "subsys/net/l2/wifi/**/*" + - "subsys/net/l2/ethernet/**/*" + +"CI-sidewalk-test": + - "include/dfu/**/*" + - "include/mgmt/mcumgr/**/*" + - "soc/nordic/**/*" + - "subsys/dfu/**/*" + - "subsys/settings/**/*" + - "subsys/mgmt/mcumgr/**/*" + - "samples/bluetooth/hci_ipc/**/*" + - any: + - "subsys/bluetooth/**/*" + - "!subsys/bluetooth/mesh/**/*" + - "!subsys/bluetooth/audio/**/*" + +"CI-audio-test": + - "boards/nordic/nrf5340_audio_dk/**/*" + - "drivers/flash/**/*" + - "drivers/spi/**/*" + - "drivers/gpio/**/*" + - "drivers/i2c/**/*" + - "drivers/watchdog/**/*" + - "include/dfu/**/*" + - "include/mgmt/mcumgr/**/*" + - "samples/bluetooth/hci_ipc/**/*" + - "soc/nordic/**/*" + - "subsys/bluetooth/audio/**/*" + - "subsys/bluetooth/host/**/*" + - "subsys/dfu/**/*" + - "subsys/fs/**/*" + - "subsys/mgmt/mcumgr/**/*" + - "subsys/sd/**/*" + - "subsys/storage/**/*" + - "subsys/task_wdt/**/*" + - "subsys/usb/**/*" + - "subsys/zbus/**/*" + +"CI-pmic-samples-test": + - "samples/shields/npm1300_ek/**/*" + - "boards/shields/npm1300_ek/**/*" + - "**/**npm1300**/**" + - "drivers/regulator/regulator_common.c" + - "drivers/regulator/regulator_shell.c" + - "drivers/gpio/gpio_shell.c" + - "drivers/sensor/sensor_shell.c" + +"CI-test-low-level": + - "arch/**/*" + - "boards/nordic/nrf54*/**/*" + - "drivers/**/*" + - "dts/**/*" + - "include/zephyr/**/*" + - "kernel/**/*" + - "modules/hal_nordic/**/*" + - "samples/basic/blinky_pwm/**/*" + - "samples/basic/fade_led/**/*" + - "samples/boards/nrf/**/*" + - "samples/boards/nordic/**/*" + - "samples/drivers/adc/**/*" + - "samples/drivers/jesd216/**/*" + - "samples/drivers/mbox/**/*" + - "samples/drivers/soc_flash_nrf/**/*" + - "samples/drivers/spi_flash/**/*" + - "samples/drivers/watchdog/**/*" + - "samples/hello_world/**/*" + - "samples/sensor/**/*" + - "samples/subsys/ipc/**/*" + - "samples/subsys/logging/**/*" + - "samples/subsys/settings/**/*" + - "samples/subsys/usb/cdc_acm/**/*" + - "samples/subsys/usb/mass/**/*" + - "samples/synchronization/**/*" + - "subsys/logging/**/*" + - "subsys/settings/**/*" + - "tests/arch/**/*" + - "tests/boards/nrf/**/*" + - "tests/boards/nordic/**/*" + - "tests/drivers/**/*" + - "tests/kernel/**/*" + +"CI-suit-dfu-test": + - "subsys/mgmt/mcumgr/**/*" + - "include/mgmt/mcumgr/**/*" + - "samples/subsys/mgmt/mcumgr/smp_svr/**/*" + - "subsys/bluetooth/**/*" + - "drivers/bluetooth/**/*" + - "drivers/flash/**/*" + - "drivers/spi/**/*" + - "drivers/mbox/**/*" + - "drivers/serial/**/*" + - "drivers/console/**/*" + - "dts/common/nordic/*" + - "dts/arm/nordic/nrf54h*" + - "dts/riscv/nordic/nrf54h*" + - "boards/nordic/nrf54h*" + - "soc/nordic/nrf54h/**/*" + - "include/zephyr/**/*" + - "subsys/logging/**/*" + - "subsys/tracing/**/*" + - "scripts/west_commands/build.py" + - "scripts/west_commands/flash.py" + - "scripts/west_commands/runners/nrfutil.py" + - "scripts/west_commands/runners/core.py" + - "scripts/west_commands/runners/nrf_common.py" diff --git a/.github/workflows/commit-tags.yml b/.github/workflows/commit-tags.yml new file mode 100644 index 00000000000..828f0297167 --- /dev/null +++ b/.github/workflows/commit-tags.yml @@ -0,0 +1,28 @@ +name: Commit tags + +on: + pull_request: + types: [synchronize, opened, reopened, edited, labeled, unlabeled, + milestoned, demilestoned, assigned, unassigned, ready_for_review, + review_requested] + +jobs: + commit_tags: + runs-on: ubuntu-22.04 + name: Run commit tags checks on patch series (PR) + steps: + - name: Update PATH for west + run: | + echo "$HOME/.local/bin" >> $GITHUB_PATH + + - name: Checkout the code + uses: actions/checkout@v3 + with: + ref: ${{ github.event.pull_request.head.sha }} + fetch-depth: 0 + + - name: Run the commit tags + uses: nrfconnect/action-commit-tags@main + with: + target: . + upstream: zephyrproject-rtos/zephyr/main diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 39815d8baa3..c8ffedcb77b 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -49,8 +49,8 @@ jobs: git config --global user.name "Your Name" git remote -v # Ensure there's no merge commits in the PR - [[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \ - (echo "::error ::Merge commits not allowed, rebase instead";false) + #[[ "$(git rev-list --merges --count origin/${BASE_REF}..)" == "0" ]] || \ + #(echo "::error ::Merge commits not allowed, rebase instead";false) git rebase origin/${BASE_REF} # debug git log --pretty=oneline | head -n 10 @@ -78,8 +78,8 @@ jobs: git log --pretty=oneline | head -n 10 # Increase rename limit to allow for large PRs git config diff.renameLimit 10000 - ./scripts/ci/check_compliance.py --annotate -e KconfigBasic \ - -c origin/${BASE_REF}.. + ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e Kconfig \ + -e KconfigBasicNoModules -e ModulesMaintainers -c origin/${BASE_REF}.. - name: upload-results uses: actions/upload-artifact@v4 diff --git a/.github/workflows/manifest-PR.yml b/.github/workflows/manifest-PR.yml new file mode 100644 index 00000000000..a871aa381de --- /dev/null +++ b/.github/workflows/manifest-PR.yml @@ -0,0 +1,17 @@ +name: handle manifest PR +on: + pull_request_target: + types: [opened, synchronize, closed] + branches: + - main + + +jobs: + call-manifest-pr-action: + runs-on: ubuntu-latest + steps: + - name: handle manifest PR + uses: nrfconnect/action-manifest-pr@main + with: + token: ${{ secrets.NCS_GITHUB_TOKEN }} + manifest-pr-title-details: ${{ github.event.pull_request.title }} diff --git a/CODEOWNERS b/CODEOWNERS index 4c737dc9642..8ba6e3c5b78 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -18,6 +18,7 @@ # component or code. This file is going to be deprecated and currently only had # entries that are not covered by the MAINTAINERS file. +/.github/test-spec.yml @nrfconnect/ncs-test-leads /soc/arm/aspeed/ @aspeeddylan /soc/atmel/ @nandojve /soc/arm/bcm*/ @sbranden diff --git a/Jenkinsfile b/Jenkinsfile new file mode 100644 index 00000000000..3b9cf002239 --- /dev/null +++ b/Jenkinsfile @@ -0,0 +1,5 @@ +@Library("CI_LIB") _ + +def pipeline = new ncs.sdk_zephyr.Main() + +pipeline.run(JOB_NAME) diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 425d79f4e74..f97819896d9 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -17,13 +17,13 @@ osource "${APPLICATION_SOURCE_DIR}/VERSION" # Shield defaults should have precedence over board defaults, which should have # precedence over SoC defaults, so include them in that order. # -# $ARCH and $BOARD_DIR will be glob patterns when building documentation. +# $ARCH and $KCONFIG_BOARD_DIR will be glob patterns when building documentation. # This loads custom shields defconfigs (from BOARD_ROOT) osource "$(KCONFIG_BINARY_DIR)/Kconfig.shield.defconfig" # This loads Zephyr base shield defconfigs source "boards/shields/*/Kconfig.defconfig" -osource "$(BOARD_DIR)/Kconfig.defconfig" +osource "$(KCONFIG_BOARD_DIR)/Kconfig.defconfig" # This loads Zephyr specific SoC root defconfigs source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.defconfig" diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index b4bf261ec29..cc7cb9a1411 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -975,7 +975,6 @@ Documentation: - doc/images/Zephyr-Kite-in-tree.png - doc/index-tex.rst - doc/index.rst - - doc/kconfig.rst - doc/templates/sample.tmpl - doc/templates/board.tmpl - boards/index.rst diff --git a/arch/arm/core/mpu/arm_mpu_regions.c b/arch/arm/core/mpu/arm_mpu_regions.c index 6af62f84078..cfe1230c907 100644 --- a/arch/arm/core/mpu/arm_mpu_regions.c +++ b/arch/arm/core/mpu/arm_mpu_regions.c @@ -8,6 +8,9 @@ #include #include +#if USE_PARTITION_MANAGER +#include +#endif static const struct arm_mpu_region mpu_regions[] = { /* Region 0 */ @@ -21,6 +24,14 @@ static const struct arm_mpu_region mpu_regions[] = { #endif /* Region 1 */ MPU_REGION_ENTRY("SRAM_0", +#if USE_PARTITION_MANAGER + PM_SRAM_ADDRESS, +#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) + REGION_RAM_ATTR(PM_SRAM_ADDRESS, PM_SRAM_SIZE)), +#else + REGION_RAM_ATTR(REGION_SRAM_SIZE)), +#endif +#else CONFIG_SRAM_BASE_ADDRESS, #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \ @@ -28,6 +39,8 @@ static const struct arm_mpu_region mpu_regions[] = { #else REGION_RAM_ATTR(REGION_SRAM_SIZE)), #endif + +#endif /* USE_PARTITION_MANAGER */ }; const struct arm_mpu_config mpu_config = { diff --git a/boards/Kconfig b/boards/Kconfig index 6eb9ca5916d..8f186b32caf 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -129,7 +129,7 @@ config QEMU_EXTRA_FLAGS GDBstub over serial with `-serial tcp:127.0.0.1:5678,server` # There might not be any board options, hence the optional source -osource "$(BOARD_DIR)/Kconfig" +osource "$(KCONFIG_BOARD_DIR)/Kconfig" endmenu config BOARD_HAS_TIMING_FUNCTIONS diff --git a/boards/Kconfig.v1 b/boards/Kconfig.v1 index 670e2f2376e..c98bd27d2db 100644 --- a/boards/Kconfig.v1 +++ b/boards/Kconfig.v1 @@ -2,9 +2,13 @@ # SPDX-License-Identifier: Apache-2.0 +# In HWMv1 the KCONFIG_BOARD_DIR points directly to the BOARD_DIR. +# Set the BOARD_DIR variable for backwards compatibility to legacy hardware model. +BOARD_DIR := $(KCONFIG_BOARD_DIR) + choice prompt "Board Selection" -source "$(BOARD_DIR)/Kconfig.board" +source "$(KCONFIG_BOARD_DIR)/Kconfig.board" endchoice diff --git a/boards/Kconfig.v2 b/boards/Kconfig.v2 index 47bb3ae2240..6fce9ccb99d 100644 --- a/boards/Kconfig.v2 +++ b/boards/Kconfig.v2 @@ -25,4 +25,4 @@ config BOARD_QUALIFIERS For example, if building for ``nrf5340dk/nrf5340/cpuapp`` then this will contain the value ``nrf5340/cpuapp``. -osource "$(BOARD_DIR)/Kconfig.$(BOARD)" +osource "$(KCONFIG_BOARD_DIR)/Kconfig.$(BOARD)" diff --git a/boards/native/nrf_bsim/CMakeLists.txt b/boards/native/nrf_bsim/CMakeLists.txt index d55a52e1a53..6aeb3f01634 100644 --- a/boards/native/nrf_bsim/CMakeLists.txt +++ b/boards/native/nrf_bsim/CMakeLists.txt @@ -24,6 +24,7 @@ zephyr_library_sources( cpu_wait.c argparse.c nsi_if.c + native_remap.c soc/nrfx_coredep.c common/bstests_entry.c common/cmsis/cmsis.c diff --git a/boards/native/nrf_bsim/native_remap.c b/boards/native/nrf_bsim/native_remap.c new file mode 100644 index 00000000000..d8b756a9576 --- /dev/null +++ b/boards/native/nrf_bsim/native_remap.c @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include "NHW_misc.h" + +bool native_emb_addr_remap(void **addr) +{ + return nhw_convert_RAM_addr(addr); +} diff --git a/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts b/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts index 43ca4460f25..cd8b95be664 100644 --- a/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts +++ b/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts @@ -97,8 +97,9 @@ &radio { status = "okay"; - /* This feature is not yet supported by the RADIO model */ + /* These features are not yet supported by the RADIO model */ /delete-property/ dfe-supported; + /delete-property/ cs-supported; }; &clock { diff --git a/boards/nordic/nrf54h20dk/CMakeLists.txt b/boards/nordic/nrf54h20dk/CMakeLists.txt new file mode 100644 index 00000000000..a5a06d8805a --- /dev/null +++ b/boards/nordic/nrf54h20dk/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +if(CONFIG_NRFS_MRAM_SERVICE_ENABLED) + zephyr_library_sources(board.c) +endif() diff --git a/boards/nordic/nrf54h20dk/Kconfig.defconfig b/boards/nordic/nrf54h20dk/Kconfig.defconfig index e37975f96ad..a2be74d3648 100644 --- a/boards/nordic/nrf54h20dk/Kconfig.defconfig +++ b/boards/nordic/nrf54h20dk/Kconfig.defconfig @@ -14,3 +14,11 @@ config BT_CTLR default y if BT endif # BOARD_NRF54H20DK_NRF54H20_CPURAD + +if BOARD_NRF54H20DK_NRF54H20_CPUPPR + +# As PPR has limited memory most of tests does not fit with asserts enabled. +config ASSERT + default n if ZTEST + +endif # BOARD_NRF54H20DK_NRF54H20_CPUPPR diff --git a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk index 9a260be4868..af29072fbd5 100644 --- a/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk +++ b/boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk @@ -2,9 +2,15 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_NRF54H20DK - select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP - select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD - select SOC_NRF54H20_CPUPPR if BOARD_NRF54H20DK_NRF54H20_CPUPPR || \ - BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP - select SOC_NRF54H20_CPUFLPR if BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \ - BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP + select SOC_NRF54H20_ENGB_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP && BOARD_REVISION = "0.8.0" + select SOC_NRF54H20_ENGB_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD && BOARD_REVISION = "0.8.0" + select SOC_NRF54H20_ENGB_CPUPPR if (BOARD_NRF54H20DK_NRF54H20_CPUPPR || \ + BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP) && BOARD_REVISION = "0.8.0" + select SOC_NRF54H20_ENGB_CPUFLPR if (BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \ + BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP) && BOARD_REVISION = "0.8.0" + select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP && BOARD_REVISION = "0.9.0" + select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD && BOARD_REVISION = "0.9.0" + select SOC_NRF54H20_CPUPPR if (BOARD_NRF54H20DK_NRF54H20_CPUPPR || \ + BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP) && BOARD_REVISION = "0.9.0" + select SOC_NRF54H20_CPUFLPR if (BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \ + BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP) && BOARD_REVISION = "0.9.0" diff --git a/boards/nordic/nrf54h20dk/board.c b/boards/nordic/nrf54h20dk/board.c new file mode 100644 index 00000000000..0699e93a7c3 --- /dev/null +++ b/boards/nordic/nrf54h20dk/board.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#define MODULE mram_suspend_off +#include +LOG_MODULE_REGISTER(MODULE); + +#include +#include + +#define MRAM_SUSPEND_OFF_INIT_PRIO 90 + +void mram_latency_handler(nrfs_mram_latency_evt_t const *p_evt, void *context) +{ + switch (p_evt->type) { + case NRFS_MRAM_LATENCY_REQ_APPLIED: + LOG_DBG("MRAM latency handler: response received"); + break; + case NRFS_MRAM_LATENCY_REQ_REJECTED: + LOG_ERR("MRAM latency handler - request rejected!"); + break; + default: + LOG_ERR("MRAM latency handler - unexpected event: 0x%x", p_evt->type); + break; + } +} + +static int turn_off_suspend_mram(void) +{ + /* Turn off mram automatic suspend as it causes delays in time depended code sections. */ + + nrfs_err_t err = NRFS_SUCCESS; + + /* Wait for ipc initialization */ + nrfs_backend_wait_for_connection(K_FOREVER); + + err = nrfs_mram_init(mram_latency_handler); + if (err != NRFS_SUCCESS) { + LOG_ERR("MRAM service init failed: %d", err); + } else { + LOG_DBG("MRAM service initialized"); + } + + LOG_DBG("MRAM: set latency: NOT ALLOWED"); + err = nrfs_mram_set_latency(MRAM_LATENCY_NOT_ALLOWED, NULL); + if (err) { + LOG_ERR("MRAM: set latency failed (%d)", err); + } + + return err; +} + +SYS_INIT(turn_off_suspend_mram, APPLICATION, MRAM_SUSPEND_OFF_INIT_PRIO); diff --git a/boards/nordic/nrf54h20dk/board.yml b/boards/nordic/nrf54h20dk/board.yml index 61690145d9f..7d57b61cd53 100644 --- a/boards/nordic/nrf54h20dk/board.yml +++ b/boards/nordic/nrf54h20dk/board.yml @@ -8,3 +8,9 @@ board: cpucluster: cpuppr - name: xip cpucluster: cpuflpr + revision: + format: major.minor.patch + default: "0.9.0" + revisions: + - name: "0.8.0" + - name: "0.9.0" diff --git a/boards/nordic/nrf54h20dk/doc/index.rst b/boards/nordic/nrf54h20dk/doc/index.rst index 41306357fe4..c8e95e39875 100644 --- a/boards/nordic/nrf54h20dk/doc/index.rst +++ b/boards/nordic/nrf54h20dk/doc/index.rst @@ -39,6 +39,7 @@ nRF54H20 SoC provides support for the following devices: * :abbr:`GPIO (General Purpose Input Output)` * :abbr:`GRTC (Global real-time counter)` * :abbr:`I2C (Inter-Integrated Circuit)` +* MEMCONF * MRAM * :abbr:`PWM (Pulse Width Modulation)` * RADIO (Bluetooth Low Energy and 802.15.4) @@ -70,6 +71,8 @@ hardware features: +-----------+------------+----------------------+ | I2C(M) | on-chip | i2c | +-----------+------------+----------------------+ +| MEMCONF | on-chip | retained_mem | ++-----------+------------+----------------------+ | SPI(M/S) | on-chip | spi | +-----------+------------+----------------------+ | UART | on-chip | serial | @@ -89,6 +92,8 @@ hardware features: +-----------+------------+----------------------+ | I2C(M) | on-chip | i2c | +-----------+------------+----------------------+ +| MEMCONF | on-chip | retained_mem | ++-----------+------------+----------------------+ | SPI(M/S) | on-chip | spi | +-----------+------------+----------------------+ | UART | on-chip | serial | diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_bicr.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_bicr.dtsi new file mode 100644 index 00000000000..34652755564 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_bicr.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +/ { + bicr: bicr@fff87b0 { + compatible = "nordic,nrf-bicr"; + reg = <0xfff87b0 0x48>; + + power-vddao5v0 = "external"; + power-vddao1v8 = "internal"; + power-vdd1v0 = "internal"; + power-vddrf1v0 = "shorted"; + power-vddao0v8 = "internal"; + power-vddvs0v8 = "internal"; + + inductor-present; + + ioport-power-rails = <&gpio1 2>, <&gpio2 2>, <&gpio6 2>, <&gpio7 2>, <&gpio9 4>; + ioport-drivectrls = <&gpio6 50>, <&gpio7 50>; + + lfosc-mode = "crystal"; + lfosc-loadcap = <15>; + + lfrc-autocalibration = <20 40 3>; + + hfxo-mode = "crystal"; + hfxo-loadcap = <56>; + }; +}; + +&gpio1 { + #ioport-power-rail-cells = <1>; +}; + +&gpio2 { + #ioport-power-rail-cells = <1>; +}; + +&gpio6 { + #ioport-power-rail-cells = <1>; + #ioport-drivectrl-cells = <1>; +}; + +&gpio7 { + #ioport-power-rail-cells = <1>; + #ioport-drivectrl-cells = <1>; +}; + +&gpio9 { + #ioport-power-rail-cells = <1>; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi index bf96741de22..2b2473f92b5 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi @@ -11,9 +11,7 @@ compatible = "nordic,owned-memory"; reg = <0x2f010000 DT_SIZE_K(260)>; status = "disabled"; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f010000 0x41000>; @@ -35,9 +33,7 @@ compatible = "nordic,owned-memory"; reg = <0x2f051000 DT_SIZE_K(4)>; status = "disabled"; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f051000 0x1000>; @@ -55,9 +51,7 @@ compatible = "nordic,owned-memory"; reg = <0x2f0be000 DT_SIZE_K(4)>; status = "disabled"; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f0be000 0x1000>; @@ -72,8 +66,8 @@ compatible = "nordic,owned-memory"; reg = <0x2f0bf000 DT_SIZE_K(4)>; status = "disabled"; - perm-read; - perm-write; + nordic,access = , + ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f0bf000 0x1000>; @@ -87,40 +81,32 @@ }; }; - shared_ram20_region: memory@2f88f000 { - reg = <0x2f88f000 DT_SIZE_K(4)>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f88f000 0x1000>; - - cpuapp_cpusys_ipc_shm: memory@ce0 { - reg = <0xce0 0x80>; - }; + cpuapp_cpusys_ipc_shm: memory@2f88fce0 { + reg = <0x2f88fce0 0x80>; + }; - cpusys_cpuapp_ipc_shm: memory@d60 { - reg = <0xd60 0x80>; - }; + cpusys_cpuapp_ipc_shm: memory@2f88fd60 { + reg = <0x2f88fd60 0x80>; + }; - cpurad_cpusys_ipc_shm: memory@e00 { - reg = <0xe00 0x80>; - }; + cpurad_cpusys_ipc_shm: memory@2f88fe00 { + reg = <0x2f88fe00 0x80>; + }; - cpusys_cpurad_ipc_shm: memory@e80 { - reg = <0xe80 0x80>; - }; + cpusys_cpurad_ipc_shm: memory@2f88fe80 { + reg = <0x2f88fe80 0x80>; }; /* - * NOTE: perm-execute is not required as FLPR has a direct - * bridge with RAM21, bypassing MPC. + * NOTE: FLPR has a direct bridge with RAM21 that bypasses MPC. + * This means that when this region is marked as non-executable, + * only FLPR can execute code from it. */ ram21_region: memory@2f890000 { compatible = "nordic,owned-memory"; status = "disabled"; reg = <0x2f890000 DT_SIZE_K(64)>; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f890000 0x10000>; @@ -151,9 +137,7 @@ compatible = "nordic,owned-memory"; reg = <0x2fc00000 DT_SIZE_K(64)>; status = "disabled"; - perm-read; - perm-write; - perm-execute; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2fc00000 0x10000>; @@ -171,33 +155,24 @@ }; }; - shared_ram3x_region: memory@2fc12000 { - compatible = "nordic,owned-memory"; - reg = <0x2fc12000 DT_SIZE_K(8)>; + cpuapp_dma_region: memory@2fc12000 { + compatible = "nordic,owned-memory", "zephyr,memory-region"; + reg = <0x2fc12000 DT_SIZE_K(4)>; status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2fc12000 0x2000>; - - cpuapp_dma_region: memory@e80 { - compatible = "zephyr,memory-region"; - reg = <0xe80 DT_SIZE_K(4)>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM3x_APP"; - zephyr,memory-attr = <( DT_MEM_DMA )>; - }; + #memory-region-cells = <0>; + nordic,access = ; + zephyr,memory-region = "DMA_RAM3x_APP"; + zephyr,memory-attr = <( DT_MEM_DMA )>; + }; - cpurad_dma_region: memory@1e80 { - compatible = "zephyr,memory-region"; - reg = <0x1e80 0x80>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM3x_RAD"; - zephyr,memory-attr = <( DT_MEM_DMA )>; - }; + cpurad_dma_region: memory@2fc13000 { + compatible = "nordic,owned-memory", "zephyr,memory-region"; + reg = <0x2fc13000 DT_SIZE_K(1)>; + status = "disabled"; + #memory-region-cells = <0>; + nordic,access = ; + zephyr,memory-region = "DMA_RAM3x_RAD"; + zephyr,memory-attr = <( DT_MEM_DMA )>; }; }; }; @@ -206,9 +181,7 @@ cpurad_rx_partitions: cpurad-rx-partitions { compatible = "nordic,owned-partitions", "fixed-partitions"; status = "disabled"; - perm-read; - perm-execute; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; @@ -220,9 +193,7 @@ cpuapp_rx_partitions: cpuapp-rx-partitions { compatible = "nordic,owned-partitions", "fixed-partitions"; status = "disabled"; - perm-read; - perm-execute; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; @@ -242,9 +213,7 @@ cpuapp_rw_partitions: cpuapp-rw-partitions { compatible = "nordic,owned-partitions", "fixed-partitions"; status = "disabled"; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts index 517b6ed853c..9c3556b27c4 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts @@ -8,6 +8,7 @@ #include #include "nrf54h20dk_nrf54h20-common.dtsi" +#include "nrf54h20dk_bicr.dtsi" /delete-node/ &cpurad_cpusys_ipc; /delete-node/ &cpusec_cpurad_ipc; @@ -26,6 +27,7 @@ zephyr,bt-hci = &bt_hci_ipc0; nordic,802154-spinel-ipc = &ipc0; zephyr,canbus = &can120; + zephyr,entropy = &prng; }; aliases { @@ -106,6 +108,11 @@ pwms = <&pwm130 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; }; + + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; + }; }; &cpuapp_ram0x_region { @@ -116,14 +123,6 @@ status = "okay"; }; -&cpuapp_cpurad_ram0x_region { - status = "okay"; -}; - -&shared_ram3x_region { - status = "okay"; -}; - &ram21_region { status = "okay"; }; @@ -256,7 +255,6 @@ ipc0: &cpuapp_cpurad_ipc { pinctrl-0 = <&uart136_default>; pinctrl-1 = <&uart136_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &gpio6 { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_8_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_8_0.yaml new file mode 100644 index 00000000000..01c44b51577 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_8_0.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk@0.8.0/nrf54h20/cpuapp +name: nRF54H20-DK-nRF54H20-Application (revision 0.8.0) +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 256 +flash: 296 +supported: + - adc + - can + - counter + - gpio + - i2c + - pwm + - spi + - watchdog + - usbd diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml similarity index 81% rename from boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.yaml rename to boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml index 1fb5a039875..a64f8cf6398 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 identifier: nrf54h20dk/nrf54h20/cpuapp -name: nRF54H20-DK-nRF54H20-Application +name: nRF54H20-DK-nRF54H20-Application (revision 0.9.0) type: mcu arch: arm toolchain: @@ -19,6 +19,7 @@ supported: - gpio - i2c - pwm + - retained_mem - spi - watchdog - usbd diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_0_8_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_0_8_0.yaml new file mode 100644 index 00000000000..bd60b8d2af3 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_0_8_0.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk@0.8.0/nrf54h20/cpuflpr +name: nRF54H20-DK-nRF54H20-FLPR (revision 0.8.0) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 46 +flash: 46 +supported: + - counter + - gpio + - i2c + - pwm + - spi diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_0_9_0.yaml similarity index 84% rename from boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.yaml rename to boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_0_9_0.yaml index ba7d9a93382..ff9513fd593 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_0_9_0.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 identifier: nrf54h20dk/nrf54h20/cpuflpr -name: nRF54H20-DK-nRF54H20-FLPR +name: nRF54H20-DK-nRF54H20-FLPR (revision 0.9.0) type: mcu arch: riscv toolchain: diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_0_8_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_0_8_0.yaml new file mode 100644 index 00000000000..7deaf20135f --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_0_8_0.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk@0.8.0/nrf54h20/cpuflpr/xip +name: nRF54H20-DK-nRF54H20-FLPR (MRAM XIP) (revision 0.8.0) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 46 +flash: 48 +supported: + - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_0_9_0.yaml similarity index 79% rename from boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.yaml rename to boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_0_9_0.yaml index 63c771688b4..e2880af9be3 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuflpr_xip_0_9_0.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 identifier: nrf54h20dk/nrf54h20/cpuflpr/xip -name: nRF54H20-DK-nRF54H20-FLPR (MRAM XIP) +name: nRF54H20-DK-nRF54H20-FLPR (MRAM XIP) (revision 0.9.0) type: mcu arch: riscv toolchain: diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts index 2143823239c..59b53aafcb2 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.dts @@ -48,7 +48,6 @@ pinctrl-0 = <&uart135_default>; pinctrl-1 = <&uart135_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &uart136 { diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_0_8_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_0_8_0.yaml new file mode 100644 index 00000000000..26412657070 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_0_8_0.yaml @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk@0.8.0/nrf54h20/cpuppr +name: nRF54H20-DK-nRF54H20-PPR (revision 0.8.0) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 62 +flash: 62 +supported: + - counter + - gpio + - i2c + - pwm + - spi diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_0_9_0.yaml similarity index 84% rename from boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml rename to boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_0_9_0.yaml index db1bf4fbefe..60f22350504 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_0_9_0.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 identifier: nrf54h20dk/nrf54h20/cpuppr -name: nRF54H20-DK-nRF54H20-PPR +name: nRF54H20-DK-nRF54H20-PPR (revision 0.9.0) type: mcu arch: riscv toolchain: diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_0_8_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_0_8_0.yaml new file mode 100644 index 00000000000..0ce1718cb60 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_0_8_0.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk@0.8.0/nrf54h20/cpuppr/xip +name: nRF54H20-DK-nRF54H20-PPR (MRAM XIP) (revision 0.8.0) +type: mcu +arch: riscv +toolchain: + - zephyr +sysbuild: true +ram: 62 +flash: 64 +supported: + - gpio diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_0_9_0.yaml similarity index 79% rename from boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.yaml rename to boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_0_9_0.yaml index 8cfc343647f..7198a379a9c 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuppr_xip_0_9_0.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 identifier: nrf54h20dk/nrf54h20/cpuppr/xip -name: nRF54H20-DK-nRF54H20-PPR (MRAM XIP) +name: nRF54H20-DK-nRF54H20-PPR (MRAM XIP) (revision 0.9.0) type: mcu arch: riscv toolchain: diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts index 31c345899cd..049617e6dc6 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts @@ -27,6 +27,11 @@ zephyr,ieee802154 = &cpurad_ieee802154; zephyr,bt-hci-ipc = &ipc0; nordic,802154-spinel-ipc = &ipc0; + zephyr,entropy = &prng; + }; + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; }; aliases { ipc-to-cpusys = &cpurad_cpusys_ipc; @@ -34,10 +39,6 @@ }; }; -&shared_ram3x_region { - status = "okay"; -}; - &cpuapp_cpurad_ram0x_region { status = "okay"; }; @@ -99,7 +100,6 @@ ipc0: &cpuapp_cpurad_ipc { pinctrl-0 = <&uart135_default>; pinctrl-1 = <&uart135_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &uart136 { @@ -112,3 +112,7 @@ ipc0: &cpuapp_cpurad_ipc { &cpurad_ieee802154 { status = "okay"; }; + +zephyr_udc0: &usbhs { + status = "disabled"; +}; diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_8_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_8_0.yaml new file mode 100644 index 00000000000..26df539a803 --- /dev/null +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_8_0.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +identifier: nrf54h20dk@0.8.0/nrf54h20/cpurad +name: nRF54H20-DK-nRF54H20-Radio (revision 0.8.0) +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +sysbuild: true +ram: 192 +flash: 256 +supported: + - counter + - gpio + - pwm + - spi diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml similarity index 80% rename from boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.yaml rename to boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml index 36c0fc01dce..568f6fcc18e 100644 --- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.yaml +++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml @@ -2,7 +2,7 @@ # SPDX-License-Identifier: Apache-2.0 identifier: nrf54h20dk/nrf54h20/cpurad -name: nRF54H20-DK-nRF54H20-Radio +name: nRF54H20-DK-nRF54H20-Radio (revision 0.9.0) type: mcu arch: arm toolchain: @@ -16,4 +16,5 @@ supported: - counter - gpio - pwm + - retained_mem - spi diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript index ffa1beed1ed..28010addbf1 100644 --- a/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript +++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript @@ -1,29 +1,248 @@ +// Constants specific to the application core +__constant U32 _CPUCONF_ADDR = 0x52011000; +__constant U32 _PROCESSOR_ID = 2; +__constant U32 _DOMAIN_ID = 2; +__constant U32 _NUM_OTHER_PROCESSORS = 1; +const U32 _OTHER_PROCESSOR_IDS[1] = {3}; + // Debug Halting Control and Status Register -__constant U32 _DHCSR_ADDR = 0xE000EDF0; -__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); -__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); -__constant U32 _DHCSR_C_HALT = (1 << 1); +__constant U32 _DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); +__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); +__constant U32 _DHCSR_C_HALT = (1 << 1); // Debug Exception and Monitor Control Register -__constant U32 _DEMCR_ADDR = 0xE000EDFC; -__constant U32 _DEMCR_VC_CORERESET = (1 << 0); -__constant U32 _DEMCR_TRCENA = (1 << 24); +__constant U32 _DEMCR_ADDR = 0xE000EDFC; +__constant U32 _DEMCR_VC_CORERESET = (1 << 0); +__constant U32 _DEMCR_TRCENA = (1 << 24); // CPU wait enable register -__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5201150C; +__constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C; + +// CTRL-AP +__constant U32 _CTRLAP_ID = 4; +__constant U32 _CTRLAP_READY_BANK = 0; +__constant U32 _CTRLAP_READY_OFFSET = 1; +__constant U32 _CTRLAP_READY = 0; +__constant U32 _CTRLAP_MAILBOX_BANK = 1; +__constant U32 _CTRLAP_MAILBOX_TXDATA_OFFSET = 0; +__constant U32 _CTRLAP_MAILBOX_TXSTATUS_OFFSET = 1; +__constant U32 _CTRLAP_MAILBOX_RXDATA_OFFSET = 2; +__constant U32 _CTRLAP_MAILBOX_RXSTATUS_OFFSET = 3; +__constant U32 _CTRLAP_MAILBOX_NO_DATA_PENDING = 0; +__constant U32 _CTRLAP_MAILBOX_DATA_PENDING = 1; +__constant int _CTRLAP_TIMEOUT_MS = 500; + +// ADAC transaction buffers +static U32 _adacTx[20]; +static U32 _adacRx[20]; + +// Failed to send to the CTRL-AP MAILBOX +__constant int _ERR_TX = -1; +// Failed to receive from the CTRL-AP MAILBOX +__constant int _ERR_RX = -2; +// ADAC command returned an error +__constant int _ERR_REPLY = -3; + +// Wait for an AP register read to return the expected value. +int _WaitForDataStatus(U32 regOffset, int expectedStatus) +{ + int status; + int ret; + int start; + int elapsed; + + status = 0; + start = JLINK_GetTime(); + elapsed = 0; + + do { + ret = JLINK_CORESIGHT_ReadDAP(regOffset, 1, &status); + elapsed = JLINK_GetTime() - start; + } while ((ret < 0 || status != expectedStatus) && (elapsed < _CTRLAP_TIMEOUT_MS)); + + if (ret < 0) { + return ret; + } + + return status; +} + +// Continuously read from the CTRL-AP MAILBOX until there is no more pending data. +void _DrainMailbox(void) +{ + int ret; + int status; + int data; + + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, 1, &status); + while (ret >= 0 && status == _CTRLAP_MAILBOX_DATA_PENDING) { + JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXDATA_OFFSET, 1, &data); + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, 1, &status); + } +} + +// Perform an ADAC transaction by: +// * writing the given sequence of words to MAILBOX.TXDATATA, waiting for MAILBOX.TXSTATUS +// readiness before each write. +// * reading a sequence of words from MAILBOX.RXDATA, waiting for MAILBOX.RXSTATUS readiness before +// each read. +// +// The message to send is read from _adacTx and the reply is written to _adacRx. +// Optionally checks if a single data word is returned and returns an error if it is non-zero. +// +// Assumes that the correct AP and AP bank for CTRL-AP MAILBOX has been selected in the DP. +int _DoAdacTransaction(int checkReplyStatus) +{ + int numWords; + int ret; + int data; + int i; + + i = 0; + numWords = 2 + (_adacTx[1] >> 2); // Length based on the length field of the message + + while (i < numWords) { + ret = _WaitForDataStatus(_CTRLAP_MAILBOX_TXSTATUS_OFFSET, + _CTRLAP_MAILBOX_NO_DATA_PENDING); + if (ret != _CTRLAP_MAILBOX_NO_DATA_PENDING) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP TX readiness - result: ", + ret); + return _ERR_TX; + } + + ret = JLINK_CORESIGHT_WriteDAP(_CTRLAP_MAILBOX_TXDATA_OFFSET, 1, _adacTx[i]); + if (ret < 0) { + JLINK_SYS_Report1("Failed to write CTRL-AP TX data - result: ", ret); + return _ERR_TX; + } + + i += 1; + } + + i = 0; + numWords = 2; // Minimum message length + + while (i < numWords) { + ret = _WaitForDataStatus(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, + _CTRLAP_MAILBOX_DATA_PENDING); + if (ret != _CTRLAP_MAILBOX_DATA_PENDING) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP RX data - result: ", ret); + return _ERR_RX; + } + + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXDATA_OFFSET, 1, &data); + if (ret < 0) { + JLINK_SYS_Report1("Failed to read CTRL-AP RX data - result: ", ret); + return _ERR_RX; + } + + if (i == 1) { + // Update total length based on the message length field + numWords = 2 + (data >> 2); + } + + _adacRx[i] = data; + i += 1; + } + + if (checkReplyStatus && _adacRx[1] == 4 && _adacRx[2] != 0) { + JLINK_SYS_Report1("ADAC command failed with status: ", _adacRx[2]); + return _ERR_REPLY; + } + + return 0; +} + +int ResetTarget(void) +{ + int err; + U32 adacMajorVersion; + U32 i; + + // Select CTRL-AP bank 0, used for the READY register + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, + (_CTRLAP_ID << 24) | (_CTRLAP_READY_BANK << 4)); + + // Wait for the READY register to indicate that the AP can be used. + err = _WaitForDataStatus(_CTRLAP_READY_OFFSET, _CTRLAP_READY); + if (err < 0) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP readiness - result: ", err); + return -1; + } + + // Select CTRL-AP bank 1, used for the MAILBOX registers for ADAC communication + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, + (_CTRLAP_ID << 24) | (_CTRLAP_MAILBOX_BANK << 4)); + + // Extract any pre-existing data from the mailbox in case there was previously + // an aborted transaction. + _DrainMailbox(); + + // Read the ADAC version + _adacTx[0] = 0xA3000000; // Command VERSION + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000; // Type 0 (ADAC version) + err = _DoAdacTransaction(0); + if (err < 0) { + return -1; + } + + adacMajorVersion = (_adacRx[2] >> 24) & 0xff; + JLINK_SYS_Report1("ADAC major version: ", adacMajorVersion); + + if (adacMajorVersion >= 2) { + // There is a very small chance that this command fails if the domain reset itself + // at the exact same time the command was issued. Therefore we retry a few times. + i = 0; + while (i < 3) { + // Reset non-essential domains + _adacTx[0] = 0xA30A0000; // Command RESET + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000; // (reserved) + err = _DoAdacTransaction(1); + if (err >= 0) { + break; + } else if (err != _ERR_REPLY) { + return -1; + } + + i = i + 1; + } + + // Start the core in halted mode + _adacTx[0] = 0xA3090000; // Command START + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x01000000 | (_PROCESSOR_ID << 16); // Own processor, Flags HALT + err = _DoAdacTransaction(1); + if (err < 0) { + return -1; + } -int ResetTarget(void) { - // ADAC reset - JLINK_CORESIGHT_WriteDP(2, 0x04000010); - JLINK_CORESIGHT_WriteAP(0, 0xA3030000); - JLINK_CORESIGHT_WriteAP(0, 0x00000004); - JLINK_CORESIGHT_WriteAP(0, 0x01020000); + // Start other cores normally (will fail silently if no firmware is present) + i = 0; + while (i < _NUM_OTHER_PROCESSORS) { + _adacTx[0] = 0xA3090000; // Command START + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000 | + (_OTHER_PROCESSOR_IDS[i] << 16); // Other processor, No flags + err = _DoAdacTransaction(0); + if (err < 0 && err != _ERR_REPLY) { + return -1; + } - JLINK_SYS_Sleep(100); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); + i = i + 1; + } + } else { + // Reset single domain via legacy implementation + _adacTx[0] = 0xA3030000; // Command RESET + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x01000000 | (_DOMAIN_ID << 16); // Own domain, Mode HALT + err = _DoAdacTransaction(1); + if (err < 0) { + return -1; + } + } // Halt the CPU JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN)); @@ -32,7 +251,7 @@ int ResetTarget(void) { JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA)); // Disable CPU wait - JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0); + JLINK_MEM_WriteU32(_CPUCONF_ADDR + _CPUCONF_CPUWAIT_OFFSET, 0); // Clear vector catch stuff JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA); diff --git a/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript b/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript index 2f1802801c1..5c2065307ff 100644 --- a/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript +++ b/boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript @@ -1,36 +1,256 @@ +// Constants specific to the radio core +__constant U32 _CPUCONF_ADDR = 0x53011000; +__constant U32 _PROCESSOR_ID = 3; +__constant U32 _DOMAIN_ID = 3; +__constant U32 _NUM_OTHER_PROCESSORS = 1; +const U32 _OTHER_PROCESSOR_IDS[1] = {2}; + // Debug Halting Control and Status Register -__constant U32 _DHCSR_ADDR = 0xE000EDF0; -__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); -__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); -__constant U32 _DHCSR_C_HALT = (1 << 1); +__constant U32 _DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); +__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); +__constant U32 _DHCSR_C_HALT = (1 << 1); // Debug Exception and Monitor Control Register -__constant U32 _DEMCR_ADDR = 0xE000EDFC; -__constant U32 _DEMCR_VC_CORERESET = (1 << 0); -__constant U32 _DEMCR_TRCENA = (1 << 24); +__constant U32 _DEMCR_ADDR = 0xE000EDFC; +__constant U32 _DEMCR_VC_CORERESET = (1 << 0); +__constant U32 _DEMCR_TRCENA = (1 << 24); // CPU wait enable register -__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5301150C; +__constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C; + +// CTRL-AP +__constant U32 _CTRLAP_ID = 4; +__constant U32 _CTRLAP_READY_BANK = 0; +__constant U32 _CTRLAP_READY_OFFSET = 1; +__constant U32 _CTRLAP_READY = 0; +__constant U32 _CTRLAP_MAILBOX_BANK = 1; +__constant U32 _CTRLAP_MAILBOX_TXDATA_OFFSET = 0; +__constant U32 _CTRLAP_MAILBOX_TXSTATUS_OFFSET = 1; +__constant U32 _CTRLAP_MAILBOX_RXDATA_OFFSET = 2; +__constant U32 _CTRLAP_MAILBOX_RXSTATUS_OFFSET = 3; +__constant U32 _CTRLAP_MAILBOX_NO_DATA_PENDING = 0; +__constant U32 _CTRLAP_MAILBOX_DATA_PENDING = 1; +__constant int _CTRLAP_TIMEOUT_MS = 500; + +// ADAC transaction buffers +static U32 _adacTx[20]; +static U32 _adacRx[20]; + +// Failed to send to the CTRL-AP MAILBOX +__constant int _ERR_TX = -1; +// Failed to receive from the CTRL-AP MAILBOX +__constant int _ERR_RX = -2; +// ADAC command returned an error +__constant int _ERR_REPLY = -3; + +// Wait for an AP register read to return the expected value. +int _WaitForDataStatus(U32 regOffset, int expectedStatus) +{ + int status; + int ret; + int start; + int elapsed; + + status = 0; + start = JLINK_GetTime(); + elapsed = 0; + + do { + ret = JLINK_CORESIGHT_ReadDAP(regOffset, 1, &status); + elapsed = JLINK_GetTime() - start; + } while ((ret < 0 || status != expectedStatus) && (elapsed < _CTRLAP_TIMEOUT_MS)); + + if (ret < 0) { + return ret; + } + + return status; +} + +// Continuously read from the CTRL-AP MAILBOX until there is no more pending data. +void _DrainMailbox(void) +{ + int ret; + int status; + int data; + + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, 1, &status); + while (ret >= 0 && status == _CTRLAP_MAILBOX_DATA_PENDING) { + JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXDATA_OFFSET, 1, &data); + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, 1, &status); + } +} + +// Perform an ADAC transaction by: +// * writing the given sequence of words to MAILBOX.TXDATATA, waiting for MAILBOX.TXSTATUS +// readiness before each write. +// * reading a sequence of words from MAILBOX.RXDATA, waiting for MAILBOX.RXSTATUS readiness before +// each read. +// +// The message to send is read from _adacTx and the reply is written to _adacRx. +// Optionally checks if a single data word is returned and returns an error if it is non-zero. +// +// Assumes that the correct AP and AP bank for CTRL-AP MAILBOX has been selected in the DP. +int _DoAdacTransaction(int checkReplyStatus) +{ + int numWords; + int ret; + int data; + int i; + + i = 0; + numWords = 2 + (_adacTx[1] >> 2); // Length based on the length field of the message + + while (i < numWords) { + ret = _WaitForDataStatus(_CTRLAP_MAILBOX_TXSTATUS_OFFSET, + _CTRLAP_MAILBOX_NO_DATA_PENDING); + if (ret != _CTRLAP_MAILBOX_NO_DATA_PENDING) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP TX readiness - result: ", + ret); + return _ERR_TX; + } + + ret = JLINK_CORESIGHT_WriteDAP(_CTRLAP_MAILBOX_TXDATA_OFFSET, 1, _adacTx[i]); + if (ret < 0) { + JLINK_SYS_Report1("Failed to write CTRL-AP TX data - result: ", ret); + return _ERR_TX; + } + + i += 1; + } + + i = 0; + numWords = 2; // Minimum message length -int ConfigTargetSettings(void) { + while (i < numWords) { + ret = _WaitForDataStatus(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, + _CTRLAP_MAILBOX_DATA_PENDING); + if (ret != _CTRLAP_MAILBOX_DATA_PENDING) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP RX data - result: ", ret); + return _ERR_RX; + } + + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXDATA_OFFSET, 1, &data); + if (ret < 0) { + JLINK_SYS_Report1("Failed to read CTRL-AP RX data - result: ", ret); + return _ERR_RX; + } + + if (i == 1) { + // Update total length based on the message length field + numWords = 2 + (data >> 2); + } + + _adacRx[i] = data; + i += 1; + } + + if (checkReplyStatus && _adacRx[1] == 4 && _adacRx[2] != 0) { + JLINK_SYS_Report1("ADAC command failed with status: ", _adacRx[2]); + return _ERR_REPLY; + } + + return 0; +} + +int ConfigTargetSettings(void) +{ JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP"); CORESIGHT_IndexAHBAPToUse = 1; return 0; } -int ResetTarget(void) { - // ADAC reset - JLINK_CORESIGHT_WriteDP(2, 0x04000010); - JLINK_CORESIGHT_WriteAP(0, 0xA3030000); - JLINK_CORESIGHT_WriteAP(0, 0x00000004); - JLINK_CORESIGHT_WriteAP(0, 0x01030000); +int ResetTarget(void) +{ + int err; + U32 adacMajorVersion; + U32 i; + + // Select CTRL-AP bank 0, used for the READY register + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, + (_CTRLAP_ID << 24) | (_CTRLAP_READY_BANK << 4)); + + // Wait for the READY register to indicate that the AP can be used. + err = _WaitForDataStatus(_CTRLAP_READY_OFFSET, _CTRLAP_READY); + if (err < 0) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP readiness - result: ", err); + return -1; + } + + // Select CTRL-AP bank 1, used for the MAILBOX registers for ADAC communication + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, + (_CTRLAP_ID << 24) | (_CTRLAP_MAILBOX_BANK << 4)); + + // Extract any pre-existing data from the mailbox in case there was previously + // an aborted transaction. + _DrainMailbox(); + + // Read the ADAC version + _adacTx[0] = 0xA3000000; // Command VERSION + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000; // Type 0 (ADAC version) + err = _DoAdacTransaction(0); + if (err < 0) { + return -1; + } + + adacMajorVersion = (_adacRx[2] >> 24) & 0xff; + JLINK_SYS_Report1("ADAC major version: ", adacMajorVersion); + + if (adacMajorVersion >= 2) { + // There is a very small chance that this command fails if the domain reset itself + // at the exact same time the command was issued. Therefore we retry a few times. + i = 0; + while (i < 3) { + // Reset non-essential domains + _adacTx[0] = 0xA30A0000; // Command RESET + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000; // (reserved) + err = _DoAdacTransaction(1); + if (err >= 0) { + break; + } else if (err != _ERR_REPLY) { + return -1; + } + + i = i + 1; + } + + // Start the core in halted mode + _adacTx[0] = 0xA3090000; // Command START + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x01000000 | (_PROCESSOR_ID << 16); // Own processor, Flags HALT + err = _DoAdacTransaction(1); + if (err < 0) { + return -1; + } + + // Start other cores normally (will fail silently if no firmware is present) + i = 0; + while (i < _NUM_OTHER_PROCESSORS) { + _adacTx[0] = 0xA3090000; // Command START + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000 | + (_OTHER_PROCESSOR_IDS[i] << 16); // Other processor, No flags + err = _DoAdacTransaction(0); + if (err < 0 && err != _ERR_REPLY) { + return -1; + } - JLINK_SYS_Sleep(100); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); + i = i + 1; + } + } else { + // Reset single domain via legacy implementation + _adacTx[0] = 0xA3030000; // Command RESET + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x01000000 | (_DOMAIN_ID << 16); // Own domain, Mode HALT + err = _DoAdacTransaction(1); + if (err < 0) { + return -1; + } + } // Halt the CPU JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN)); @@ -39,7 +259,7 @@ int ResetTarget(void) { JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA)); // Disable CPU wait - JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0); + JLINK_MEM_WriteU32(_CPUCONF_ADDR + _CPUCONF_CPUWAIT_OFFSET, 0); // Clear vector catch stuff JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA); diff --git a/boards/nordic/nrf54l15dk/Kconfig b/boards/nordic/nrf54l15dk/Kconfig new file mode 100644 index 00000000000..c8890bc4498 --- /dev/null +++ b/boards/nordic/nrf54l15dk/Kconfig @@ -0,0 +1,34 @@ +# nRF54L15 DK board configuration + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS + +config NRF_MPC_REGION_SIZE + hex + default 0x1000 + help + Region size for the Memory Protection Controller (MPC) in bytes. + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default NRF_MPC_REGION_SIZE + help + This defines the flash region size from the TRUSTZONE perspective. + It is used when configuring the TRUSTZONE and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TRUSTZONE without depending + on peripheral specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default NRF_MPC_REGION_SIZE + help + This defines the RAM region size from the TRUSTZONE perspective. + It is used when configuring the TRUSTZONE and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TRUSTZONE without depending + on peripheral specific symbols. + +endif #BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS diff --git a/boards/nordic/nrf54l15dk/Kconfig.defconfig b/boards/nordic/nrf54l15dk/Kconfig.defconfig index 2b753df3515..dbc4a9f04d9 100644 --- a/boards/nordic/nrf54l15dk/Kconfig.defconfig +++ b/boards/nordic/nrf54l15dk/Kconfig.defconfig @@ -7,6 +7,39 @@ config BT_CTLR default BT config ROM_START_OFFSET + default 0 if PARTITION_MANAGER_ENABLED default 0x800 if BOOTLOADER_MCUBOOT endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP + +# What MCUboot requires is here +if MCUBOOT + +# Within sdk-nrf NRF security is default +config NRF_SECURITY + default y + select NRF_OBERON + +# NRF_SECURITY enforces PSA crypt +config MBEDTLS + default n + +endif # MCUBOOT + +if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS + +config BT_CTLR + default BT + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + default y + depends on BUILD_WITH_TFM + +endif #BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS diff --git a/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk b/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk index e385ef84f89..5f511b618d6 100644 --- a/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk +++ b/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk @@ -2,6 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_NRF54L15DK - select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP + select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \ BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP diff --git a/boards/nordic/nrf54l15dk/board.cmake b/boards/nordic/nrf54l15dk/board.cmake index 1fd92b7fced..784a16d8978 100644 --- a/boards/nordic/nrf54l15dk/board.cmake +++ b/boards/nordic/nrf54l15dk/board.cmake @@ -7,5 +7,13 @@ elseif(CONFIG_SOC_NRF54L15_CPUFLPR) board_runner_args(jlink "--speed=4000") endif() +if(BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l15dk/board.yml b/boards/nordic/nrf54l15dk/board.yml index 7a8bf2f5cf1..c1df4a588cb 100644 --- a/boards/nordic/nrf54l15dk/board.yml +++ b/boards/nordic/nrf54l15dk/board.yml @@ -6,3 +6,5 @@ board: variants: - name: xip cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp diff --git a/boards/nordic/nrf54l15dk/doc/index.rst b/boards/nordic/nrf54l15dk/doc/index.rst index 7d450912661..f7b927bdc86 100644 --- a/boards/nordic/nrf54l15dk/doc/index.rst +++ b/boards/nordic/nrf54l15dk/doc/index.rst @@ -19,6 +19,7 @@ nRF54L15 Arm Cortex-M33 CPU and the following devices: * RRAM * :abbr:`GPIO (General Purpose Input Output)` * :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` +* MEMCONF * :abbr:`MPU (Memory Protection Unit)` * :abbr:`NVIC (Nested Vectored Interrupt Controller)` * :abbr:`PWM (Pulse Width Modulation)` @@ -60,6 +61,8 @@ hardware features: +-----------+------------+----------------------+ | GRTC | on-chip | counter | +-----------+------------+----------------------+ +| MEMCONF | on-chip | retained_mem | ++-----------+------------+----------------------+ | MPU | on-chip | arch/arm | +-----------+------------+----------------------+ | NVIC | on-chip | arch/arm | diff --git a/boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi b/boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi index 4292e9a1523..191babb632f 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l15dk/nrf54l15_cpuapp_common.dtsi @@ -87,7 +87,6 @@ &uart20 { status = "okay"; - hw-flow-control; }; &gpio0 { diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.dts new file mode 100644 index 00000000000..21d3e100c0f --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include "nrf54l15_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf54l15dk_nrf54l15-cpuapp"; + model = "Nordic nRF54L15 DK nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; + + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.yaml new file mode 100644 index 00000000000..56b8e9618c0 --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: nrf54l15dk/nrf54l15/cpuapp/ns +name: nRF54l15-DK-nRF54l15-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 256 +flash: 1524 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns_defconfig new file mode 100644 index 00000000000..70f01d7c9ba --- /dev/null +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns_defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts index a608941514e..472e3f2b8d3 100644 --- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts +++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuflpr.dts @@ -48,7 +48,6 @@ &uart30 { status = "okay"; - hw-flow-control; }; &gpio0 { diff --git a/boards/nordic/nrf54l15pdk/Kconfig b/boards/nordic/nrf54l15pdk/Kconfig new file mode 100644 index 00000000000..8c937c8c890 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/Kconfig @@ -0,0 +1,34 @@ +# nRF54L15 PDK board configuration + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS + +config NRF_MPC_REGION_SIZE + hex + default 0x1000 + help + Region size for the Memory Protection Controller (MPC) in bytes. + +config NRF_TRUSTZONE_FLASH_REGION_SIZE + hex + default NRF_MPC_REGION_SIZE + help + This defines the flash region size from the TRUSTZONE perspective. + It is used when configuring the TRUSTZONE and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TRUSTZONE without depending + on peripheral specific symbols. + +config NRF_TRUSTZONE_RAM_REGION_SIZE + hex + default NRF_MPC_REGION_SIZE + help + This defines the RAM region size from the TRUSTZONE perspective. + It is used when configuring the TRUSTZONE and when setting alignments + requirements for the partitions. + This abstraction allows us to configure TRUSTZONE without depending + on peripheral specific symbols. + +endif #BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS diff --git a/boards/nordic/nrf54l15pdk/Kconfig.defconfig b/boards/nordic/nrf54l15pdk/Kconfig.defconfig index 1c83abbb020..819ddf25aba 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig.defconfig +++ b/boards/nordic/nrf54l15pdk/Kconfig.defconfig @@ -7,6 +7,33 @@ config BT_CTLR default BT config ROM_START_OFFSET + default 0 if PARTITION_MANAGER_ENABLED default 0x800 if BOOTLOADER_MCUBOOT endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP + +if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS + +config BT_CTLR + default BT + +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y if BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + default y + depends on BUILD_WITH_TFM + +endif #BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS + +if BOARD_NRF54L15PDK_NRF54L15_CPUFLPR || BOARD_NRF54L15PDK_NRF54L15_CPUFLPR_XIP + +# As FLPR has limited memory most of tests does not fit with asserts enabled. +config ASSERT + default n if ZTEST + +endif # BOARD_NRF54L15PDK_NRF54L15_CPUFLPR || BOARD_NRF54L15PDK_NRF54L15_CPUFLPR_XIP diff --git a/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk index d5116bd50c6..09afebc2e09 100644 --- a/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk +++ b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk @@ -2,6 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 config BOARD_NRF54L15PDK - select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP + select SOC_NRF54L15_ENGA_CPUAPP if BOARD_NRF54L15PDK_NRF54L15_CPUAPP || BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS select SOC_NRF54L15_ENGA_CPUFLPR if BOARD_NRF54L15PDK_NRF54L15_CPUFLPR || \ BOARD_NRF54L15PDK_NRF54L15_CPUFLPR_XIP diff --git a/boards/nordic/nrf54l15pdk/board.cmake b/boards/nordic/nrf54l15pdk/board.cmake index 4a6a86a8f8a..46a6f896e0c 100644 --- a/boards/nordic/nrf54l15pdk/board.cmake +++ b/boards/nordic/nrf54l15pdk/board.cmake @@ -7,6 +7,14 @@ elseif (CONFIG_SOC_NRF54L15_ENGA_CPUFLPR) board_runner_args(jlink "--speed=4000") endif() +if(BOARD_NRF54L15PDK_NRF54L15_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf54l15pdk/board.yml b/boards/nordic/nrf54l15pdk/board.yml index e692040f7bd..5df0270abe3 100644 --- a/boards/nordic/nrf54l15pdk/board.yml +++ b/boards/nordic/nrf54l15pdk/board.yml @@ -6,6 +6,8 @@ board: variants: - name: xip cpucluster: cpuflpr + - name: ns + cpucluster: cpuapp revision: format: major.minor.patch default: "0.3.0" diff --git a/boards/nordic/nrf54l15pdk/doc/index.rst b/boards/nordic/nrf54l15pdk/doc/index.rst index dc6e69b65e5..3fae82b713c 100644 --- a/boards/nordic/nrf54l15pdk/doc/index.rst +++ b/boards/nordic/nrf54l15pdk/doc/index.rst @@ -20,6 +20,7 @@ the following devices: * RRAM * :abbr:`GPIO (General Purpose Input Output)` * :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` +* MEMCONF * :abbr:`MPU (Memory Protection Unit)` * :abbr:`NVIC (Nested Vectored Interrupt Controller)` * :abbr:`PWM (Pulse Width Modulation)` @@ -65,6 +66,8 @@ hardware features: +-----------+------------+----------------------+ | TWIM | on-chip | i2c | +-----------+------------+----------------------+ +| MEMCONF | on-chip | retained_mem | ++-----------+------------+----------------------+ | MPU | on-chip | arch/arm | +-----------+------------+----------------------+ | NVIC | on-chip | arch/arm | diff --git a/boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi b/boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi index 1327d48f5bd..474874d110c 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l15pdk/nrf54l15_cpuapp_common.dtsi @@ -87,7 +87,6 @@ &uart20 { status = "okay"; - hw-flow-control; }; &gpio0 { diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.dts new file mode 100644 index 00000000000..6e05c69c5f9 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.dts @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#define USE_NON_SECURE_ADDRESS_MAP 1 + +#include "nrf54l15_cpuapp_common.dtsi" + +/ { + compatible = "nordic,nrf54l15pdk_nrf54l15-cpuapp"; + model = "Nordic nRF54L15 PDK nRF54L15 Application MCU"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,sram = &cpuapp_sram; + }; +}; + +&uart30 { + /* Disable so that TF-M can use this UART */ + status = "disabled"; + + current-speed = <115200>; + pinctrl-0 = <&uart30_default>; + pinctrl-1 = <&uart30_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.yaml new file mode 100644 index 00000000000..460803eaa53 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns.yaml @@ -0,0 +1,22 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +identifier: nrf54l15pdk/nrf54l15/cpuapp/ns +name: nRF54l15-PDK-nRF54l15-Application-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 256 +flash: 1524 +supported: + - adc + - gpio + - i2c + - spi + - counter + - watchdog + - adc + - i2s diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig new file mode 100644 index 00000000000..70f01d7c9ba --- /dev/null +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_ns_defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Don't enable the cache in the non-secure image as it is a +# secure-only peripheral on 54l +CONFIG_CACHE_MANAGEMENT=n +CONFIG_EXTERNAL_CACHE=n + +CONFIG_UART_CONSOLE=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Start SYSCOUNTER on driver init +CONFIG_NRF_GRTC_START_SYSCOUNTER=y diff --git a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr.dts index 2b80a45c4e1..c8ed4abb79f 100644 --- a/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr.dts +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuflpr.dts @@ -48,7 +48,6 @@ &uart30 { status = "okay"; - hw-flow-control; }; &gpio0 { diff --git a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi index cdf6d62a30a..ed9d76a6b19 100644 --- a/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi +++ b/boards/nordic/nrf54l20pdk/nrf54l20_cpuapp_common.dtsi @@ -18,7 +18,7 @@ zephyr,bt-c2h-uart = &uart20; zephyr,flash-controller = &rram_controller; zephyr,flash = &cpuapp_rram; - zephyr,bt-hci = &bt_hci_controller; + zephyr,bt-hci = &bt_hci_sdc; zephyr,ieee802154 = &ieee802154; }; }; @@ -108,7 +108,7 @@ status = "okay"; }; -&bt_hci_controller { +&bt_hci_sdc { status = "okay"; }; diff --git a/boards/nordic/nrf7002dk/Kconfig b/boards/nordic/nrf7002dk/Kconfig index 4bd84612e7a..1e2a7d09c93 100644 --- a/boards/nordic/nrf7002dk/Kconfig +++ b/boards/nordic/nrf7002dk/Kconfig @@ -23,8 +23,6 @@ config HEAP_MEM_POOL_ADD_SIZE_BOARD config BOARD_ENABLE_CPUNET bool "nRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) help This option enables releasing the Network 'force off' signal, which as a consequence will power up the Network MCU during system boot. diff --git a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi index ce11dbcb61d..cff6e54fd5d 100644 --- a/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi +++ b/boards/nordic/nrf7002dk/nrf5340_cpuapp_common.dtsi @@ -173,7 +173,6 @@ arduino_i2c: &i2c1 { cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; mx25r64: mx25r6435f@0 { compatible = "jedec,spi-nor"; - status = "disabled"; reg = <0>; spi-max-frequency = <33000000>; jedec-id = [c2 28 17]; diff --git a/boards/nordic/nrf9131ek/Kconfig.defconfig b/boards/nordic/nrf9131ek/Kconfig.defconfig index b63e7ef8d34..8e0e1d02d1d 100644 --- a/boards/nordic/nrf9131ek/Kconfig.defconfig +++ b/boards/nordic/nrf9131ek/Kconfig.defconfig @@ -5,6 +5,21 @@ if BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS +# By default, if we build for a Non-Secure version of the board, +# enable building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y if BOARD_NRF9131EK_NRF9131_NS + +if BUILD_WITH_TFM + +# By default, if we build with TF-M, instruct build system to +# flash the combined TF-M (Secure) & Zephyr (Non Secure) image +config TFM_FLASH_MERGED_BINARY + bool + default y + +endif # BUILD_WITH_TFM + # For the secure version of the board the firmware is linked at the beginning # of the flash, or into the code-partition defined in DT if it is intended to # be loaded by MCUboot. If the secure firmware is to be combined with a non- diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi index 78e3be8825f..0127998509e 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280-memory_map.dtsi @@ -15,9 +15,7 @@ compatible = "nordic,owned-memory"; reg = <0x2f011000 DT_SIZE_K(4)>; status = "disabled"; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f011000 0x1000>; @@ -35,9 +33,7 @@ compatible = "nordic,owned-memory"; reg = <0x2f012000 DT_SIZE_K(516)>; status = "disabled"; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f012000 0x81000>; @@ -59,8 +55,8 @@ compatible = "nordic,owned-memory"; reg = <0x2f0cf000 DT_SIZE_K(4)>; status = "disabled"; - perm-read; - perm-write; + nordic,access = , + ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f0cf000 0x1000>; @@ -75,8 +71,11 @@ }; cpuapp_cpucell_ram0x_region: memory@2f0d0000 { + compatible = "nordic,owned-memory"; reg = <0x2f0d0000 DT_SIZE_K(36)>; status = "disabled"; + nordic,access = , + ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f0d0000 0x9000>; @@ -99,61 +98,27 @@ }; }; - /* Shared memory ownership. - * TODO: - * remove these two after https://github.com/zephyrproject-rtos/zephyr/pull/72273 - * and let cpuapp_cpucell_ram0x_region use the `access` binding to describe - * the shared memory ownership. - */ - - cpuapp_cpucell_ipc_shm: memory@2 { - compatible = "nordic,owned-memory"; - reg = <0x2f0d0000 DT_SIZE_K(36)>; - owner-id = <2>; - perm-read; - perm-write; - status = "disabled"; + cpuapp_cpusys_ipc_shm: memory@2f88fce0 { + reg = <0x2f88fce0 0x80>; }; - cpucell_cpuapp_ipc_shm: memory@4 { - compatible = "nordic,owned-memory"; - reg = <0x2f0d0000 DT_SIZE_K(36)>; - owner-id = <4>; - perm-read; - perm-write; - status = "disabled"; + cpusys_cpuapp_ipc_shm: memory@2f88fd60 { + reg = <0x2f88fd60 0x80>; }; - shared_ram20_region: memory@2f88f000 { - reg = <0x2f88f000 DT_SIZE_K(4)>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2f88f000 0x1000>; - - cpuapp_cpusys_ipc_shm: memory@ce0 { - reg = <0xce0 0x80>; - }; - - cpusys_cpuapp_ipc_shm: memory@d60 { - reg = <0xd60 0x80>; - }; - - cpurad_cpusys_ipc_shm: memory@e00 { - reg = <0xe00 0x80>; - }; + cpurad_cpusys_ipc_shm: memory@2f88fe00 { + reg = <0x2f88fe00 0x80>; + }; - cpusys_cpurad_ipc_shm: memory@e80 { - reg = <0xe80 0x80>; - }; + cpusys_cpurad_ipc_shm: memory@2f88fe80 { + reg = <0x2f88fe80 0x80>; }; ram21_region: memory@2f890000 { compatible = "nordic,owned-memory"; status = "disabled"; reg = <0x2f890000 DT_SIZE_K(32)>; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2f890000 0x8000>; @@ -172,9 +137,7 @@ compatible = "nordic,owned-memory"; reg = <0x2fc00000 DT_SIZE_K(24)>; status = "disabled"; - perm-read; - perm-write; - perm-execute; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x2fc00000 0x6000>; @@ -192,33 +155,24 @@ }; }; - shared_ram3x_region: memory@2fc06000 { - compatible = "nordic,owned-memory"; - reg = <0x2fc06000 DT_SIZE_K(8)>; + cpuapp_dma_region: memory@2fc06000 { + compatible = "nordic,owned-memory", "zephyr,memory-region"; + reg = <0x2fc06000 DT_SIZE_K(4)>; status = "disabled"; - perm-read; - perm-write; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x2fc06000 0x4000>; - - cpuapp_dma_region: memory@0 { - compatible = "zephyr,memory-region"; - reg = <0x0 DT_SIZE_K(4)>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM3x_APP"; - zephyr,memory-attr = <( DT_MEM_DMA )>; - }; + #memory-region-cells = <0>; + nordic,access = ; + zephyr,memory-region = "DMA_RAM3x_APP"; + zephyr,memory-attr = <( DT_MEM_DMA )>; + }; - cpurad_dma_region: memory@1000 { - compatible = "zephyr,memory-region"; - reg = <0x1000 0x80>; - status = "disabled"; - #memory-region-cells = <0>; - zephyr,memory-region = "DMA_RAM3x_RAD"; - zephyr,memory-attr = <( DT_MEM_DMA )>; - }; + cpurad_dma_region: memory@2fc07000 { + compatible = "nordic,owned-memory", "zephyr,memory-region"; + reg = <0x2fc07000 DT_SIZE_K(1)>; + status = "disabled"; + #memory-region-cells = <0>; + nordic,access = ; + zephyr,memory-region = "DMA_RAM3x_RAD"; + zephyr,memory-attr = <( DT_MEM_DMA )>; }; }; }; @@ -227,9 +181,7 @@ cpurad_rx_partitions: cpurad-rx-partitions { compatible = "nordic,owned-partitions", "fixed-partitions"; status = "disabled"; - perm-read; - perm-execute; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; @@ -241,9 +193,7 @@ cpuapp_rx_partitions: cpuapp-rx-partitions { compatible = "nordic,owned-partitions", "fixed-partitions"; status = "disabled"; - perm-read; - perm-execute; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; @@ -259,9 +209,7 @@ cpuapp_rw_partitions: cpuapp-rw-partitions { compatible = "nordic,owned-partitions", "fixed-partitions"; status = "disabled"; - perm-read; - perm-write; - perm-secure; + nordic,access = ; #address-cells = <1>; #size-cells = <1>; diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts index ceb4ddc3ff1..2ce9b912269 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.dts @@ -28,6 +28,7 @@ zephyr,bt-hci = &bt_hci_ipc0; nordic,802154-spinel-ipc = &ipc0; zephyr,canbus = &can120; + zephyr,entropy = &prng; }; aliases { @@ -108,25 +109,18 @@ pwms = <&pwm130 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; }; }; -}; - -&cpuapp_ram0x_region { - status = "okay"; -}; - -&cpuapp_cpurad_ram0x_region { - status = "okay"; -}; -&cpuapp_cpucell_ipc_shm { - status = "okay"; + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; + }; }; -&cpucell_cpuapp_ipc_shm { +&cpuapp_ram0x_region { status = "okay"; }; -&shared_ram3x_region { +&cpuapp_cpucell_ram0x_region { status = "okay"; }; @@ -252,7 +246,6 @@ ipc0: &cpuapp_cpurad_ipc { pinctrl-0 = <&uart136_default>; pinctrl-1 = <&uart136_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &gpio6 { diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts index 5da976ef70d..10942796ff3 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuppr.dts @@ -49,7 +49,6 @@ pinctrl-0 = <&uart135_default>; pinctrl-1 = <&uart135_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &uart136 { diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts index 1235f53df2b..f1f3af54132 100644 --- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts +++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.dts @@ -28,6 +28,11 @@ zephyr,ieee802154 = &cpurad_ieee802154; zephyr,bt-hci-ipc = &ipc0; nordic,802154-spinel-ipc = &ipc0; + zephyr,entropy = &prng; + }; + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; }; aliases { ipc-to-cpusys = &cpurad_cpusys_ipc; @@ -35,10 +40,6 @@ }; }; -&shared_ram3x_region { - status = "okay"; -}; - &cpuapp_cpurad_ram0x_region { status = "okay"; }; @@ -104,7 +105,6 @@ ipc0: &cpuapp_cpurad_ipc { pinctrl-0 = <&uart135_default>; pinctrl-1 = <&uart135_sleep>; pinctrl-names = "default", "sleep"; - hw-flow-control; }; &uart136 { diff --git a/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript b/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript index ffa1beed1ed..5791a7bed9b 100644 --- a/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript +++ b/boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript @@ -1,29 +1,248 @@ +// Constants specific to the application core +__constant U32 _CPUCONF_ADDR = 0x52011000; +__constant U32 _PROCESSOR_ID = 2; +__constant U32 _DOMAIN_ID = 2; +__constant U32 _NUM_OTHER_PROCESSORS = 2; +const U32 _OTHER_PROCESSOR_IDS[2] = {4, 3}; + // Debug Halting Control and Status Register -__constant U32 _DHCSR_ADDR = 0xE000EDF0; -__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); -__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); -__constant U32 _DHCSR_C_HALT = (1 << 1); +__constant U32 _DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); +__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); +__constant U32 _DHCSR_C_HALT = (1 << 1); // Debug Exception and Monitor Control Register -__constant U32 _DEMCR_ADDR = 0xE000EDFC; -__constant U32 _DEMCR_VC_CORERESET = (1 << 0); -__constant U32 _DEMCR_TRCENA = (1 << 24); +__constant U32 _DEMCR_ADDR = 0xE000EDFC; +__constant U32 _DEMCR_VC_CORERESET = (1 << 0); +__constant U32 _DEMCR_TRCENA = (1 << 24); // CPU wait enable register -__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5201150C; +__constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C; + +// CTRL-AP +__constant U32 _CTRLAP_ID = 4; +__constant U32 _CTRLAP_READY_BANK = 0; +__constant U32 _CTRLAP_READY_OFFSET = 1; +__constant U32 _CTRLAP_READY = 0; +__constant U32 _CTRLAP_MAILBOX_BANK = 1; +__constant U32 _CTRLAP_MAILBOX_TXDATA_OFFSET = 0; +__constant U32 _CTRLAP_MAILBOX_TXSTATUS_OFFSET = 1; +__constant U32 _CTRLAP_MAILBOX_RXDATA_OFFSET = 2; +__constant U32 _CTRLAP_MAILBOX_RXSTATUS_OFFSET = 3; +__constant U32 _CTRLAP_MAILBOX_NO_DATA_PENDING = 0; +__constant U32 _CTRLAP_MAILBOX_DATA_PENDING = 1; +__constant int _CTRLAP_TIMEOUT_MS = 500; + +// ADAC transaction buffers +static U32 _adacTx[20]; +static U32 _adacRx[20]; + +// Failed to send to the CTRL-AP MAILBOX +__constant int _ERR_TX = -1; +// Failed to receive from the CTRL-AP MAILBOX +__constant int _ERR_RX = -2; +// ADAC command returned an error +__constant int _ERR_REPLY = -3; + +// Wait for an AP register read to return the expected value. +int _WaitForDataStatus(U32 regOffset, int expectedStatus) +{ + int status; + int ret; + int start; + int elapsed; + + status = 0; + start = JLINK_GetTime(); + elapsed = 0; + + do { + ret = JLINK_CORESIGHT_ReadDAP(regOffset, 1, &status); + elapsed = JLINK_GetTime() - start; + } while ((ret < 0 || status != expectedStatus) && (elapsed < _CTRLAP_TIMEOUT_MS)); + + if (ret < 0) { + return ret; + } + + return status; +} + +// Continuously read from the CTRL-AP MAILBOX until there is no more pending data. +void _DrainMailbox(void) +{ + int ret; + int status; + int data; + + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, 1, &status); + while (ret >= 0 && status == _CTRLAP_MAILBOX_DATA_PENDING) { + JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXDATA_OFFSET, 1, &data); + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, 1, &status); + } +} + +// Perform an ADAC transaction by: +// * writing the given sequence of words to MAILBOX.TXDATATA, waiting for MAILBOX.TXSTATUS +// readiness before each write. +// * reading a sequence of words from MAILBOX.RXDATA, waiting for MAILBOX.RXSTATUS readiness before +// each read. +// +// The message to send is read from _adacTx and the reply is written to _adacRx. +// Optionally checks if a single data word is returned and returns an error if it is non-zero. +// +// Assumes that the correct AP and AP bank for CTRL-AP MAILBOX has been selected in the DP. +int _DoAdacTransaction(int checkReplyStatus) +{ + int numWords; + int ret; + int data; + int i; + + i = 0; + numWords = 2 + (_adacTx[1] >> 2); // Length based on the length field of the message + + while (i < numWords) { + ret = _WaitForDataStatus(_CTRLAP_MAILBOX_TXSTATUS_OFFSET, + _CTRLAP_MAILBOX_NO_DATA_PENDING); + if (ret != _CTRLAP_MAILBOX_NO_DATA_PENDING) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP TX readiness - result: ", + ret); + return _ERR_TX; + } + + ret = JLINK_CORESIGHT_WriteDAP(_CTRLAP_MAILBOX_TXDATA_OFFSET, 1, _adacTx[i]); + if (ret < 0) { + JLINK_SYS_Report1("Failed to write CTRL-AP TX data - result: ", ret); + return _ERR_TX; + } + + i += 1; + } + + i = 0; + numWords = 2; // Minimum message length + + while (i < numWords) { + ret = _WaitForDataStatus(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, + _CTRLAP_MAILBOX_DATA_PENDING); + if (ret != _CTRLAP_MAILBOX_DATA_PENDING) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP RX data - result: ", ret); + return _ERR_RX; + } + + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXDATA_OFFSET, 1, &data); + if (ret < 0) { + JLINK_SYS_Report1("Failed to read CTRL-AP RX data - result: ", ret); + return _ERR_RX; + } + + if (i == 1) { + // Update total length based on the message length field + numWords = 2 + (data >> 2); + } + + _adacRx[i] = data; + i += 1; + } + + if (checkReplyStatus && _adacRx[1] == 4 && _adacRx[2] != 0) { + JLINK_SYS_Report1("ADAC command failed with status: ", _adacRx[2]); + return _ERR_REPLY; + } + + return 0; +} + +int ResetTarget(void) +{ + int err; + U32 adacMajorVersion; + U32 i; + + // Select CTRL-AP bank 0, used for the READY register + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, + (_CTRLAP_ID << 24) | (_CTRLAP_READY_BANK << 4)); + + // Wait for the READY register to indicate that the AP can be used. + err = _WaitForDataStatus(_CTRLAP_READY_OFFSET, _CTRLAP_READY); + if (err < 0) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP readiness - result: ", err); + return -1; + } + + // Select CTRL-AP bank 1, used for the MAILBOX registers for ADAC communication + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, + (_CTRLAP_ID << 24) | (_CTRLAP_MAILBOX_BANK << 4)); + + // Extract any pre-existing data from the mailbox in case there was previously + // an aborted transaction. + _DrainMailbox(); + + // Read the ADAC version + _adacTx[0] = 0xA3000000; // Command VERSION + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000; // Type 0 (ADAC version) + err = _DoAdacTransaction(0); + if (err < 0) { + return -1; + } + + adacMajorVersion = (_adacRx[2] >> 24) & 0xff; + JLINK_SYS_Report1("ADAC major version: ", adacMajorVersion); + + if (adacMajorVersion >= 2) { + // There is a very small chance that this command fails if the domain reset itself + // at the exact same time the command was issued. Therefore we retry a few times. + i = 0; + while (i < 3) { + // Reset non-essential domains + _adacTx[0] = 0xA30A0000; // Command RESET + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000; // (reserved) + err = _DoAdacTransaction(1); + if (err >= 0) { + break; + } else if (err != _ERR_REPLY) { + return -1; + } + + i = i + 1; + } + + // Start the core in halted mode + _adacTx[0] = 0xA3090000; // Command START + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x01000000 | (_PROCESSOR_ID << 16); // Own processor, Flags HALT + err = _DoAdacTransaction(1); + if (err < 0) { + return -1; + } -int ResetTarget(void) { - // ADAC reset - JLINK_CORESIGHT_WriteDP(2, 0x04000010); - JLINK_CORESIGHT_WriteAP(0, 0xA3030000); - JLINK_CORESIGHT_WriteAP(0, 0x00000004); - JLINK_CORESIGHT_WriteAP(0, 0x01020000); + // Start other cores normally (will fail silently if no firmware is present) + i = 0; + while (i < _NUM_OTHER_PROCESSORS) { + _adacTx[0] = 0xA3090000; // Command START + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000 | + (_OTHER_PROCESSOR_IDS[i] << 16); // Other processor, No flags + err = _DoAdacTransaction(0); + if (err < 0 && err != _ERR_REPLY) { + return -1; + } - JLINK_SYS_Sleep(100); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); + i = i + 1; + } + } else { + // Reset single domain via legacy implementation + _adacTx[0] = 0xA3030000; // Command RESET + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x01000000 | (_DOMAIN_ID << 16); // Own domain, Mode HALT + err = _DoAdacTransaction(1); + if (err < 0) { + return -1; + } + } // Halt the CPU JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN)); @@ -32,7 +251,7 @@ int ResetTarget(void) { JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA)); // Disable CPU wait - JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0); + JLINK_MEM_WriteU32(_CPUCONF_ADDR + _CPUCONF_CPUWAIT_OFFSET, 0); // Clear vector catch stuff JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA); diff --git a/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript b/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript index 2f1802801c1..02b84dcc970 100644 --- a/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript +++ b/boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript @@ -1,36 +1,256 @@ +// Constants specific to the radio core +__constant U32 _CPUCONF_ADDR = 0x53011000; +__constant U32 _PROCESSOR_ID = 3; +__constant U32 _DOMAIN_ID = 3; +__constant U32 _NUM_OTHER_PROCESSORS = 2; +const U32 _OTHER_PROCESSOR_IDS[2] = {4, 2}; + // Debug Halting Control and Status Register -__constant U32 _DHCSR_ADDR = 0xE000EDF0; -__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); -__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); -__constant U32 _DHCSR_C_HALT = (1 << 1); +__constant U32 _DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DHCSR_DBGKEY = (0xA05F << 16); +__constant U32 _DHCSR_C_DEBUGEN = (1 << 0); +__constant U32 _DHCSR_C_HALT = (1 << 1); // Debug Exception and Monitor Control Register -__constant U32 _DEMCR_ADDR = 0xE000EDFC; -__constant U32 _DEMCR_VC_CORERESET = (1 << 0); -__constant U32 _DEMCR_TRCENA = (1 << 24); +__constant U32 _DEMCR_ADDR = 0xE000EDFC; +__constant U32 _DEMCR_VC_CORERESET = (1 << 0); +__constant U32 _DEMCR_TRCENA = (1 << 24); // CPU wait enable register -__constant U32 _CPUCONF_CPUWAIT_ADDR = 0x5301150C; +__constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C; + +// CTRL-AP +__constant U32 _CTRLAP_ID = 4; +__constant U32 _CTRLAP_READY_BANK = 0; +__constant U32 _CTRLAP_READY_OFFSET = 1; +__constant U32 _CTRLAP_READY = 0; +__constant U32 _CTRLAP_MAILBOX_BANK = 1; +__constant U32 _CTRLAP_MAILBOX_TXDATA_OFFSET = 0; +__constant U32 _CTRLAP_MAILBOX_TXSTATUS_OFFSET = 1; +__constant U32 _CTRLAP_MAILBOX_RXDATA_OFFSET = 2; +__constant U32 _CTRLAP_MAILBOX_RXSTATUS_OFFSET = 3; +__constant U32 _CTRLAP_MAILBOX_NO_DATA_PENDING = 0; +__constant U32 _CTRLAP_MAILBOX_DATA_PENDING = 1; +__constant int _CTRLAP_TIMEOUT_MS = 500; + +// ADAC transaction buffers +static U32 _adacTx[20]; +static U32 _adacRx[20]; + +// Failed to send to the CTRL-AP MAILBOX +__constant int _ERR_TX = -1; +// Failed to receive from the CTRL-AP MAILBOX +__constant int _ERR_RX = -2; +// ADAC command returned an error +__constant int _ERR_REPLY = -3; + +// Wait for an AP register read to return the expected value. +int _WaitForDataStatus(U32 regOffset, int expectedStatus) +{ + int status; + int ret; + int start; + int elapsed; + + status = 0; + start = JLINK_GetTime(); + elapsed = 0; + + do { + ret = JLINK_CORESIGHT_ReadDAP(regOffset, 1, &status); + elapsed = JLINK_GetTime() - start; + } while ((ret < 0 || status != expectedStatus) && (elapsed < _CTRLAP_TIMEOUT_MS)); + + if (ret < 0) { + return ret; + } + + return status; +} + +// Continuously read from the CTRL-AP MAILBOX until there is no more pending data. +void _DrainMailbox(void) +{ + int ret; + int status; + int data; + + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, 1, &status); + while (ret >= 0 && status == _CTRLAP_MAILBOX_DATA_PENDING) { + JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXDATA_OFFSET, 1, &data); + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, 1, &status); + } +} + +// Perform an ADAC transaction by: +// * writing the given sequence of words to MAILBOX.TXDATATA, waiting for MAILBOX.TXSTATUS +// readiness before each write. +// * reading a sequence of words from MAILBOX.RXDATA, waiting for MAILBOX.RXSTATUS readiness before +// each read. +// +// The message to send is read from _adacTx and the reply is written to _adacRx. +// Optionally checks if a single data word is returned and returns an error if it is non-zero. +// +// Assumes that the correct AP and AP bank for CTRL-AP MAILBOX has been selected in the DP. +int _DoAdacTransaction(int checkReplyStatus) +{ + int numWords; + int ret; + int data; + int i; + + i = 0; + numWords = 2 + (_adacTx[1] >> 2); // Length based on the length field of the message + + while (i < numWords) { + ret = _WaitForDataStatus(_CTRLAP_MAILBOX_TXSTATUS_OFFSET, + _CTRLAP_MAILBOX_NO_DATA_PENDING); + if (ret != _CTRLAP_MAILBOX_NO_DATA_PENDING) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP TX readiness - result: ", + ret); + return _ERR_TX; + } + + ret = JLINK_CORESIGHT_WriteDAP(_CTRLAP_MAILBOX_TXDATA_OFFSET, 1, _adacTx[i]); + if (ret < 0) { + JLINK_SYS_Report1("Failed to write CTRL-AP TX data - result: ", ret); + return _ERR_TX; + } + + i += 1; + } + + i = 0; + numWords = 2; // Minimum message length -int ConfigTargetSettings(void) { + while (i < numWords) { + ret = _WaitForDataStatus(_CTRLAP_MAILBOX_RXSTATUS_OFFSET, + _CTRLAP_MAILBOX_DATA_PENDING); + if (ret != _CTRLAP_MAILBOX_DATA_PENDING) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP RX data - result: ", ret); + return _ERR_RX; + } + + ret = JLINK_CORESIGHT_ReadDAP(_CTRLAP_MAILBOX_RXDATA_OFFSET, 1, &data); + if (ret < 0) { + JLINK_SYS_Report1("Failed to read CTRL-AP RX data - result: ", ret); + return _ERR_RX; + } + + if (i == 1) { + // Update total length based on the message length field + numWords = 2 + (data >> 2); + } + + _adacRx[i] = data; + i += 1; + } + + if (checkReplyStatus && _adacRx[1] == 4 && _adacRx[2] != 0) { + JLINK_SYS_Report1("ADAC command failed with status: ", _adacRx[2]); + return _ERR_REPLY; + } + + return 0; +} + +int ConfigTargetSettings(void) +{ JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP"); CORESIGHT_IndexAHBAPToUse = 1; return 0; } -int ResetTarget(void) { - // ADAC reset - JLINK_CORESIGHT_WriteDP(2, 0x04000010); - JLINK_CORESIGHT_WriteAP(0, 0xA3030000); - JLINK_CORESIGHT_WriteAP(0, 0x00000004); - JLINK_CORESIGHT_WriteAP(0, 0x01030000); +int ResetTarget(void) +{ + int err; + U32 adacMajorVersion; + U32 i; + + // Select CTRL-AP bank 0, used for the READY register + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, + (_CTRLAP_ID << 24) | (_CTRLAP_READY_BANK << 4)); + + // Wait for the READY register to indicate that the AP can be used. + err = _WaitForDataStatus(_CTRLAP_READY_OFFSET, _CTRLAP_READY); + if (err < 0) { + JLINK_SYS_Report1("Timed out waiting for CTRL-AP readiness - result: ", err); + return -1; + } + + // Select CTRL-AP bank 1, used for the MAILBOX registers for ADAC communication + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_DP_REG_SELECT, 0, + (_CTRLAP_ID << 24) | (_CTRLAP_MAILBOX_BANK << 4)); + + // Extract any pre-existing data from the mailbox in case there was previously + // an aborted transaction. + _DrainMailbox(); + + // Read the ADAC version + _adacTx[0] = 0xA3000000; // Command VERSION + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000; // Type 0 (ADAC version) + err = _DoAdacTransaction(0); + if (err < 0) { + return -1; + } + + adacMajorVersion = (_adacRx[2] >> 24) & 0xff; + JLINK_SYS_Report1("ADAC major version: ", adacMajorVersion); + + if (adacMajorVersion >= 2) { + // There is a very small chance that this command fails if the domain reset itself + // at the exact same time the command was issued. Therefore we retry a few times. + i = 0; + while (i < 3) { + // Reset non-essential domains + _adacTx[0] = 0xA30A0000; // Command RESET + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000; // (reserved) + err = _DoAdacTransaction(1); + if (err >= 0) { + break; + } else if (err != _ERR_REPLY) { + return -1; + } + + i = i + 1; + } + + // Start the core in halted mode + _adacTx[0] = 0xA3090000; // Command START + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x01000000 | (_PROCESSOR_ID << 16); // Own processor, Flags HALT + err = _DoAdacTransaction(1); + if (err < 0) { + return -1; + } + + // Start other cores normally (will fail silently if no firmware is present) + i = 0; + while (i < _NUM_OTHER_PROCESSORS) { + _adacTx[0] = 0xA3090000; // Command START + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x00000000 | + (_OTHER_PROCESSOR_IDS[i] << 16); // Other processor, No flags + err = _DoAdacTransaction(0); + if (err < 0 && err != _ERR_REPLY) { + return -1; + } - JLINK_SYS_Sleep(100); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); - JLINK_CORESIGHT_ReadAP(2); + i = i + 1; + } + } else { + // Reset single domain via legacy implementation + _adacTx[0] = 0xA3030000; // Command RESET + _adacTx[1] = 0x00000004; // Data length 4 bytes + _adacTx[2] = 0x01000000 | (_DOMAIN_ID << 16); // Own domain, Mode HALT + err = _DoAdacTransaction(1); + if (err < 0) { + return -1; + } + } // Halt the CPU JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN)); @@ -39,7 +259,7 @@ int ResetTarget(void) { JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA)); // Disable CPU wait - JLINK_MEM_WriteU32(_CPUCONF_CPUWAIT_ADDR, 0); + JLINK_MEM_WriteU32(_CPUCONF_ADDR + _CPUCONF_CPUWAIT_OFFSET, 0); // Clear vector catch stuff JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA); diff --git a/boards/nordic/thingy53/Kconfig.defconfig b/boards/nordic/thingy53/Kconfig.defconfig index 92eac11503d..31ac0093ba2 100644 --- a/boards/nordic/thingy53/Kconfig.defconfig +++ b/boards/nordic/thingy53/Kconfig.defconfig @@ -5,6 +5,12 @@ if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS +config BOOTLOADER_MCUBOOT + default y if !MCUBOOT + +config BOARD_ENABLE_CPUNET + default y if !MCUBOOT + # Code Partition: # # For the secure version of the board the firmware is linked at the beginning @@ -132,6 +138,16 @@ endif # LOG endif # BOARD_SERIAL_BACKEND_CDC_ACM +# By default, a USB CDC ACM instance is already enabled in the board's DTS. +# It is not necessary for nRF Connect SDK to add another instance if MCUBoot +# bootloader is built as a child image. +config MCUBOOT_USB_SUPPORT + bool + default n + +config NORDIC_QSPI_NOR + default y + endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS if BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/nordic/thingy53/Kconfig.sysbuild b/boards/nordic/thingy53/Kconfig.sysbuild new file mode 100644 index 00000000000..df489c1dd54 --- /dev/null +++ b/boards/nordic/thingy53/Kconfig.sysbuild @@ -0,0 +1,29 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice MCUBOOT_MODE + default MCUBOOT_MODE_OVERWRITE_ONLY +endchoice + +config SECURE_BOOT_NETCORE + default y + +config NETCORE_APP_UPDATE + default y if SECURE_BOOT_NETCORE + +config NRF_DEFAULT_EMPTY + default y if SECURE_BOOT_NETCORE + +config MCUBOOT_USE_ALL_AVAILABLE_RAM + default y if BOARD_THINGY53_NRF5340_CPUAPP_NS && BOOTLOADER_MCUBOOT + +endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +config PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY + default y if BOOTLOADER_MCUBOOT diff --git a/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp.yml b/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp.yml new file mode 100644 index 00000000000..7a48d51ec33 --- /dev/null +++ b/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp.yml @@ -0,0 +1,55 @@ +app: + address: 0x10200 + region: flash_primary + size: 0xdfe00 +mcuboot: + address: 0x0 + region: flash_primary + size: 0x10000 +mcuboot_pad: + address: 0x10000 + region: flash_primary + size: 0x200 +mcuboot_primary: + address: 0x10000 + orig_span: &id001 + - mcuboot_pad + - app + region: flash_primary + size: 0xe0000 + span: *id001 +mcuboot_primary_app: + address: 0x10200 + orig_span: &id002 + - app + region: flash_primary + size: 0xdfe00 + span: *id002 +settings_storage: + address: 0xf0000 + region: flash_primary + size: 0x10000 +mcuboot_primary_1: + address: 0x0 + size: 0x40000 + device: flash_ctrl + region: ram_flash +mcuboot_secondary: + address: 0x00000 + size: 0xe0000 + device: MX25R64 + region: external_flash +mcuboot_secondary_1: + address: 0xe0000 + size: 0x40000 + device: MX25R64 + region: external_flash +external_flash: + address: 0x120000 + size: 0x6e0000 + device: MX25R64 + region: external_flash +pcd_sram: + address: 0x20000000 + size: 0x2000 + region: sram_primary diff --git a/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp_ns.yml b/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp_ns.yml new file mode 100644 index 00000000000..70ffe6d9c12 --- /dev/null +++ b/boards/nordic/thingy53/pm_static_thingy53_nrf5340_cpuapp_ns.yml @@ -0,0 +1,73 @@ +mcuboot: + address: 0x0 + region: flash_primary + size: 0x10000 +mcuboot_pad: + address: 0x10000 + region: flash_primary + size: 0x200 +tfm_secure: + address: 0x10000 + size: 0xc000 + span: [mcuboot_pad, tfm] +tfm_nonsecure: + address: 0x1c000 + size: 0xd4000 + span: [app] +tfm: + address: 0x10200 + region: flash_primary + size: 0xbe00 +app: + address: 0x1c000 + region: flash_primary + size: 0xd4000 +mcuboot_primary: + address: 0x10000 + orig_span: &id001 + - mcuboot_pad + - tfm + - app + region: flash_primary + size: 0xe0000 + span: *id001 +mcuboot_primary_app: + address: 0x10200 + orig_span: &id002 + - tfm + - app + region: flash_primary + size: 0xdfe00 + span: *id002 +nonsecure_storage: + address: 0xf0000 + size: 0x10000 + span: [settings_storage] +settings_storage: + address: 0xf0000 + region: flash_primary + size: 0x10000 +mcuboot_primary_1: + address: 0x0 + size: 0x40000 + device: flash_ctrl + region: ram_flash +mcuboot_secondary: + address: 0x00000 + size: 0xe0000 + device: MX25R64 + region: external_flash +mcuboot_secondary_1: + address: 0xe0000 + size: 0x40000 + device: MX25R64 + region: external_flash +external_flash: + address: 0x120000 + size: 0x6e0000 + device: MX25R64 + region: external_flash +pcd_sram: + address: 0x20000000 + size: 0x2000 + region: sram_primary diff --git a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi index 13a58443871..e4028edfc94 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi @@ -18,6 +18,7 @@ zephyr,bt-hci = &bt_hci_ipc0; nordic,802154-spinel-ipc = &ipc0; zephyr,ieee802154 = &ieee802154; + nordic,pm-ext-flash = &mx25r64; }; buttons { @@ -131,6 +132,18 @@ }; }; + /* Disabled by default as SPI lines are shared with peripherals on application core */ + spi_fwd: nrf-spi-forwarder { + compatible = "nordic,nrf-gpio-forwarder"; + status = "disabled"; + fem-spi-if { + gpios = <&gpio0 24 0>, + <&gpio0 29 0>, + <&gpio0 27 0>, + <&gpio0 28 0>; + }; + }; + aliases { sw0 = &button0; sw1 = &button1; diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi index 940d3afedc7..76d1fd8bad5 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi @@ -23,4 +23,20 @@ }; }; + spi0_default: spi0_default { + group1 { + psels = , + , + ; + }; + }; + + spi0_sleep: spi0_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; }; diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts index 89e9f8c64e5..aa4d4df909c 100644 --- a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts @@ -63,6 +63,7 @@ mode-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; pdn-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; tx-en-gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; + spi-if = <&nrf_radio_fem_spi>; supply-voltage-mv = <3000>; }; @@ -111,6 +112,27 @@ pinctrl-names = "default", "sleep"; }; +/* Disabled by default as shares same GPIO lines as SPI peripherals on application core */ +fem_spi: &spi0 { + status = "disabled"; + cs-gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; + + nrf_radio_fem_spi: nrf21540_fem_spi@0 { + compatible = "nordic,nrf21540-fem-spi"; + status = "disabled"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&radio { + /* Uncomment to enable SPI interface for FEM */ + /* fem = <&nrf_radio_fem>; */ +}; + &flash1 { partitions { diff --git a/boards/shields/nrf7002eb/Kconfig.shield b/boards/shields/nrf7002eb/Kconfig.shield new file mode 100644 index 00000000000..e369cfe3de4 --- /dev/null +++ b/boards/shields/nrf7002eb/Kconfig.shield @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SHIELD_NRF7002EB + def_bool $(shields_list_contains,nrf7002eb) + +config SHIELD_NRF7002EB_COEX + def_bool $(shields_list_contains,nrf7002eb_coex) diff --git a/boards/shields/nrf7002eb/boards/thingy53_nrf5340_cpuapp.overlay b/boards/shields/nrf7002eb/boards/thingy53_nrf5340_cpuapp.overlay new file mode 100644 index 00000000000..ee052ec68ae --- /dev/null +++ b/boards/shields/nrf7002eb/boards/thingy53_nrf5340_cpuapp.overlay @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * This uses gpio0 pin 8 which conflicts with STATUS pin of Wi-Fi SR coex + */ +&npm1100_force_pwm_mode { + status = "disabled"; +}; + +/* + * Pins P0.9, P0.10, P0.11, P0.12 conflict with SPI4 and nrf7002 host irq + */ +&uart0 { + status = "disabled"; +}; diff --git a/boards/shields/nrf7002eb/doc/index.rst b/boards/shields/nrf7002eb/doc/index.rst new file mode 100644 index 00000000000..e93c778f87c --- /dev/null +++ b/boards/shields/nrf7002eb/doc/index.rst @@ -0,0 +1,72 @@ +.. _nrf7002eb: + +nRF7002 EB +########## + +Overview +******** + +The nRF7002 EB is a versatile evaluation kit in the form of a thumbstick shield which connects to +compatible Nordic host boards, like the Thingy53, using the Nordic edge-connector. + +The nRF7002 EB unlocks low-power Wi-Fi 6 capabilities for your host device. It support dual-band Wi-Fi +2.4GHz and 5GHz, and is based on the nRF7002 SoC. +Seamlessly connect to Wi-Fi networks and leverage Wi-Fi-based locationing, enabling advanced +features such as SSID sniffing of local Wi-Fi hubs + +.. figure:: nrf7002eb.jpg + :alt: nRF7002 EB + :align: center + + nRF7002 EB + +Requirements +************ + +The nRF7002 EB board is designed to fit straight into a Nordic edge-connector and uses SPI as the +communication interface. Any host board that supports the Nordic edge-connector can be used with +the nRF7002 EB. + +Prerequisites +------------- + +the nRF70 driver requires firmware binary blobs for Wi-Fi operation. Run the command +below to retrieve those files. + +.. code-block:: console + + west update + west blobs fetch hal_nordic + +Usage +***** + +The shield can be used in any application by setting ``--shield nrf7002eb`` when invoking ``west build``. + +Shield Variants +############### + +The nRF7002 EK has a variant which includes the COEX pins. These pins are not be routed to the +edge-connector on some boards, like earlier revisions of the Thingy53 than v1.0.0. + +- ``nrf7002ek``: The default variant. +- ``nrf7002ek_coex``: Variant which includes the COEX pins. + +SR Co-existence +############### + +The nRF7002 EK supports SR co-existence provided the host board supports it. The SR co-existence +pins are connected to the host board's GPIO pins. + +Two Kconfig options are available to enable SR co-existence: + +- :kconfig:option:`CONFIG_NRF70_SR_COEX`: Enables SR co-existence. +- :kconfig:option:`CONFIG_NRF70_SR_COEX_RF_SWITCH`: Control SR side RF switch. + +References +********** + +- `Developing with nRF7002 EB `_ +- `nRF7002 EB product specification `_ +- `nRF7002 product specification `_ +- `nRF7002 Co-existence `_ diff --git a/boards/shields/nrf7002eb/doc/nrf7002eb.jpg b/boards/shields/nrf7002eb/doc/nrf7002eb.jpg new file mode 100644 index 00000000000..a8afd674135 Binary files /dev/null and b/boards/shields/nrf7002eb/doc/nrf7002eb.jpg differ diff --git a/boards/shields/nrf7002eb/nrf7002eb.overlay b/boards/shields/nrf7002eb/nrf7002eb.overlay new file mode 100644 index 00000000000..d580a2efb8c --- /dev/null +++ b/boards/shields/nrf7002eb/nrf7002eb.overlay @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + chosen { + zephyr,wifi = &wlan0; + }; +}; + +&edge_connector_spi { + status = "okay"; + + nrf70: nrf7002@0 { + compatible = "nordic,nrf7002-spi"; + status = "okay"; + reg = <0>; + spi-max-frequency = ; + + bucken-gpios = <&edge_connector 9 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + iovdd-ctrl-gpios = <&edge_connector 9 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + host-irq-gpios = <&edge_connector 19 GPIO_ACTIVE_HIGH>; + + wlan0: wlan0 { + compatible = "nordic,wlan"; + }; + + wifi-max-tx-pwr-2g-dsss = <21>; + wifi-max-tx-pwr-2g-mcs0 = <16>; + wifi-max-tx-pwr-2g-mcs7 = <16>; + wifi-max-tx-pwr-5g-low-mcs0 = <13>; + wifi-max-tx-pwr-5g-low-mcs7 = <13>; + wifi-max-tx-pwr-5g-mid-mcs0 = <13>; + wifi-max-tx-pwr-5g-mid-mcs7 = <13>; + wifi-max-tx-pwr-5g-high-mcs0 = <12>; + wifi-max-tx-pwr-5g-high-mcs7 = <12>; + }; +}; diff --git a/boards/shields/nrf7002eb/nrf7002eb_coex.overlay b/boards/shields/nrf7002eb/nrf7002eb_coex.overlay new file mode 100644 index 00000000000..a8925c25567 --- /dev/null +++ b/boards/shields/nrf7002eb/nrf7002eb_coex.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "nrf7002eb.overlay" + +&nrf70 { + status0-gpios = <&edge_connector 5 GPIO_ACTIVE_HIGH>; + req-gpios = <&edge_connector 6 GPIO_ACTIVE_HIGH>; + grant-gpios = <&edge_connector 15 (GPIO_PULL_DOWN | GPIO_ACTIVE_LOW)>; +}; diff --git a/cmake/linker/ld/target.cmake b/cmake/linker/ld/target.cmake index 8c18fce0e9a..ed29e88aa16 100644 --- a/cmake/linker/ld/target.cmake +++ b/cmake/linker/ld/target.cmake @@ -80,6 +80,7 @@ macro(configure_linker_script linker_script_gen linker_pass_define) ${current_includes} ${soc_linker_script_includes} ${template_script_defines} + -DUSE_PARTITION_MANAGER=$,$,$> -E ${LINKER_SCRIPT} -P # Prevent generation of debug `#line' directives. -o ${linker_script_gen} diff --git a/cmake/linker_script/common/common-ram.cmake b/cmake/linker_script/common/common-ram.cmake index 091da6ff541..48e0c6010aa 100644 --- a/cmake/linker_script/common/common-ram.cmake +++ b/cmake/linker_script/common/common-ram.cmake @@ -18,10 +18,10 @@ zephyr_linker_section_configure(SECTION device_states ) if(CONFIG_PM_DEVICE) - zephyr_iterable_section(NAME pm_device_slots GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME pm_device_slots GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() -zephyr_iterable_section(NAME log_dynamic GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME log_dynamic GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) if(CONFIG_USERSPACE) # All kernel objects within are assumed to be either completely @@ -32,35 +32,35 @@ if(CONFIG_USERSPACE) # _static_kernel_objects_begin = .; endif() -zephyr_iterable_section(NAME k_timer GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_mem_slab GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_heap GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_mutex GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_stack GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_msgq GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_mbox GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_pipe GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_sem GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_queue GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_condvar GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_event GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) -zephyr_iterable_section(NAME k_fifo GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME k_timer GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_mem_slab GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_heap GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_mutex GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_stack GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_msgq GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_mbox GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_pipe GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_sem GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_queue GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_condvar GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_event GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) +zephyr_iterable_section(NAME k_fifo GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME net_buf_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME net_buf_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) if(CONFIG_NETWORKING) - zephyr_iterable_section(NAME net_if GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME net_if_dev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME net_l2 GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME eth_bridge GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME net_if GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME net_if_dev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME net_l2 GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME eth_bridge GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_ARM_SCMI) - zephyr_iterable_section(NAME scmi_protocol GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME scmi_protocol GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_SENSING) - zephyr_iterable_section(NAME sensing_sensor GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME sensing_sensor GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_USB_DEVICE_STACK) @@ -83,8 +83,8 @@ if(CONFIG_USB_DEVICE_BOS) endif() if(CONFIG_RTIO) - zephyr_iterable_section(NAME rtio GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME rtio_iodev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME rtio GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME rtio_iodev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() #if(CONFIG_USERSPACE) @@ -93,11 +93,11 @@ endif() # if(CONFIG_ZTEST) - zephyr_iterable_section(NAME ztest_suite_node GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME ztest_suite_stats GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME ztest_unit_test GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME ztest_test_rule GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME ztest_expected_result_entry GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME ztest_suite_node GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME ztest_suite_stats GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME ztest_unit_test GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME ztest_test_rule GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME ztest_expected_result_entry GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_ZBUS) @@ -105,31 +105,31 @@ if(CONFIG_ZBUS) endif() if(CONFIG_UVB) - zephyr_iterable_section(NAME uvb_node GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME uvb_node GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_LOG) - zephyr_iterable_section(NAME log_mpsc_pbuf GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME log_msg_ptr GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME log_mpsc_pbuf GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME log_msg_ptr GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_PCIE) - zephyr_iterable_section(NAME pcie_dev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME pcie_dev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_USB_DEVICE_STACK OR CONFIG_USB_DEVICE_STACK_NEXT) - zephyr_iterable_section(NAME usb_cfg_data GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME usbd_context GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME usbd_class_fs GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME usbd_class_hs GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME usb_cfg_data GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME usbd_context GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME usbd_class_fs GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME usbd_class_hs GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_USB_HOST_STACK) - zephyr_iterable_section(NAME usbh_contex GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME usbh_class_data GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME usbh_contex GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME usbh_class_data GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_DEVICE_MUTABLE) - zephyr_iterable_section(NAME device_mutable GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME device_mutable GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() diff --git a/cmake/linker_script/common/common-rom.cmake b/cmake/linker_script/common/common-rom.cmake index 2fd4fcedb47..868e9f382d9 100644 --- a/cmake/linker_script/common/common-rom.cmake +++ b/cmake/linker_script/common/common-rom.cmake @@ -11,7 +11,7 @@ zephyr_linker_section_obj_level(SECTION init LEVEL SMP) zephyr_linker_section(NAME deferred_init_list KVMA RAM_REGION GROUP RODATA_REGION) zephyr_linker_section_configure(SECTION deferred_init_list INPUT ".z_deferred_init*" KEEP SORT NAME) -zephyr_iterable_section(NAME device NUMERIC KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME device NUMERIC KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) if(CONFIG_GEN_SW_ISR_TABLE AND NOT CONFIG_DYNAMIC_INTERRUPTS) # ld align has been changed to subalign to provide identical behavior scatter vs. ld. @@ -92,98 +92,98 @@ zephyr_linker_section_configure( ) if(CONFIG_NET_SOCKETS) - zephyr_iterable_section(NAME net_socket_register KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME net_socket_register KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_NET_L2_PPP) - zephyr_iterable_section(NAME ppp_protocol_handler KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME ppp_protocol_handler KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() -zephyr_iterable_section(NAME bt_l2cap_fixed_chan KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME bt_l2cap_fixed_chan KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) if(CONFIG_BT_CLASSIC) - zephyr_iterable_section(NAME bt_l2cap_br_fixed_chan KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME bt_l2cap_br_fixed_chan KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_BT_CONN) - zephyr_iterable_section(NAME bt_conn_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME bt_conn_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() -zephyr_iterable_section(NAME bt_gatt_service_static KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME bt_gatt_service_static KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) if(CONFIG_BT_MESH) - zephyr_iterable_section(NAME bt_mesh_subnet_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME bt_mesh_app_key_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME bt_mesh_subnet_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME bt_mesh_app_key_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) - zephyr_iterable_section(NAME bt_mesh_hb_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME bt_mesh_hb_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_BT_MESH_FRIEND) - zephyr_iterable_section(NAME bt_mesh_friend_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME bt_mesh_friend_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_BT_MESH_LOW_POWER) - zephyr_iterable_section(NAME bt_mesh_lpn_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME bt_mesh_lpn_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_BT_MESH_PROXY) - zephyr_iterable_section(NAME bt_mesh_proxy_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME bt_mesh_proxy_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_EC_HOST_CMD) - zephyr_iterable_section(NAME ec_host_cmd_handler KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME ec_host_cmd_handler KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_SETTINGS) - zephyr_iterable_section(NAME settings_handler_static KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME settings_handler_static KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_SENSING) - zephyr_iterable_section(NAME sensing_sensor_info KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME sensing_sensor_info KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_SENSOR_INFO) - zephyr_iterable_section(NAME sensor_info KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME sensor_info KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_SENSOR_ASYNC_API) - zephyr_iterable_section(NAME sensor_decoder_api KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME sensor_decoder_api KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_MCUMGR) - zephyr_iterable_section(NAME mcumgr_handler KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME mcumgr_handler KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() -zephyr_iterable_section(NAME k_p4wq_initparam KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME k_p4wq_initparam KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) if(CONFIG_EMUL) - zephyr_iterable_section(NAME emul KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME emul KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_DNS_SD) - zephyr_iterable_section(NAME dns_sd_rec KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME dns_sd_rec KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_PCIE) - zephyr_iterable_section(NAME irq_alloc KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME irq_alloc KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() -zephyr_iterable_section(NAME log_strings KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME log_strings KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME log_const KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME log_const KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME shell KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME shell KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME shell_root_cmds KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME shell_root_cmds KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME shell_subcmds KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME shell_subcmds KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME shell_dynamic_subcmds KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME shell_dynamic_subcmds KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME cfb_font KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME cfb_font KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) -zephyr_iterable_section(NAME tracing_backend KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME tracing_backend KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) zephyr_linker_section(NAME zephyr_dbg_info KVMA RAM_REGION GROUP RODATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT}) zephyr_linker_section_configure(SECTION zephyr_dbg_info INPUT ".zephyr_dbg_info" KEEP) @@ -199,15 +199,15 @@ if (CONFIG_DEVICE_DEPS) zephyr_linker_section_configure(SECTION device_deps INPUT .__device_deps_pass2* KEEP SORT NAME PASS NOT LINKER_DEVICE_DEPS_PASS1) endif() -zephyr_iterable_section(NAME _static_thread_data KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) +zephyr_iterable_section(NAME _static_thread_data KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) if (CONFIG_BT_IAS) - zephyr_iterable_section(NAME bt_ias_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME bt_ias_cb KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if (CONFIG_LOG) - zephyr_iterable_section(NAME log_link KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME log_backend KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME log_link KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME log_backend KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if (CONFIG_MULTI_LEVEL_INTERRUPTS) @@ -215,35 +215,35 @@ if (CONFIG_MULTI_LEVEL_INTERRUPTS) endif() if (CONFIG_HTTP_SERVER) - zephyr_iterable_section(NAME http_service_desc KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME http_service_desc KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if (CONFIG_COAP_SERVER) - zephyr_iterable_section(NAME coap_service KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME coap_service KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if (CONFIG_NET_MGMT) - zephyr_iterable_section(NAME net_mgmt_event_static_handler KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME net_mgmt_event_static_handler KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_INPUT) - zephyr_iterable_section(NAME input_callback KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME input_callback KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_USBD_MSC_CLASS) - zephyr_iterable_section(NAME usbd_msc_lun KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME usbd_msc_lun KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_ZBUS) - zephyr_iterable_section(NAME zbus_channel KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME zbus_observer KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) - zephyr_iterable_section(NAME zbus_channel_observation KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME zbus_channel KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME zbus_observer KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) + zephyr_iterable_section(NAME zbus_channel_observation KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_GNSS) - zephyr_iterable_section(NAME gnss_data_callback KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME gnss_data_callback KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() if(CONFIG_GNSS_SATELLITES) - zephyr_iterable_section(NAME gnss_satellites_callback KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN) + zephyr_iterable_section(NAME gnss_satellites_callback KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN}) endif() diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index d2c0666f2c5..d13e0a16f2d 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -185,9 +185,7 @@ set(format_str "{NAME}\;{DIR}\;{HWM}\;") set(format_str "${format_str}{REVISION_FORMAT}\;{REVISION_DEFAULT}\;{REVISION_EXACT}\;") set(format_str "${format_str}{REVISIONS}\;{SOCS}\;{QUALIFIERS}") -if(BOARD_DIR) - set(board_dir_arg "--board-dir=${BOARD_DIR}") -endif() +list(TRANSFORM BOARD_DIRECTORIES PREPEND "--board-dir=" OUTPUT_VARIABLE board_dir_arg) execute_process(${list_boards_commands} --board=${BOARD} ${board_dir_arg} --cmakeformat=${format_str} OUTPUT_VARIABLE ret_board @@ -200,29 +198,15 @@ endif() if(NOT "${ret_board}" STREQUAL "") string(STRIP "${ret_board}" ret_board) - string(FIND "${ret_board}" "\n" idx REVERSE) - if(idx GREATER -1) - while(TRUE) - math(EXPR start "${idx} + 1") - string(SUBSTRING "${ret_board}" ${start} -1 line) - string(SUBSTRING "${ret_board}" 0 ${idx} ret_board) - - cmake_parse_arguments(LIST_BOARD "" "DIR" "" ${line}) - set(board_dirs "${board_dirs}\n${LIST_BOARD_DIR}") - - if(idx EQUAL -1) - break() - endif() - string(FIND "${ret_board}" "\n" idx REVERSE) - endwhile() - message(FATAL_ERROR "Multiple boards named '${BOARD}' found in:${board_dirs}") - endif() - - set(single_val "NAME;DIR;HWM;REVISION_FORMAT;REVISION_DEFAULT;REVISION_EXACT") - set(multi_val "REVISIONS;SOCS;QUALIFIERS") + set(single_val "NAME;HWM;REVISION_FORMAT;REVISION_DEFAULT;REVISION_EXACT") + set(multi_val "DIR;REVISIONS;SOCS;QUALIFIERS") cmake_parse_arguments(LIST_BOARD "" "${single_val}" "${multi_val}" ${ret_board}) - set(BOARD_DIR ${LIST_BOARD_DIR} CACHE PATH "Board directory for board (${BOARD})" FORCE) - set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${BOARD_DIR}/board.yml) + list(GET LIST_BOARD_DIR 0 BOARD_DIR) + set(BOARD_DIR ${BOARD_DIR} CACHE PATH "Main board directory for board (${BOARD})" FORCE) + set(BOARD_DIRECTORIES ${LIST_BOARD_DIR} CACHE INTERNAL "List of board directories for board (${BOARD})" FORCE) + foreach(dir ${BOARD_DIRECTORIES}) + set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${dir}/board.yml) + endforeach() # Create two CMake variables identifying the hw model. # CMake variable: HWM=[v1,v2] diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake index ec0999d366b..82c5a302fbc 100644 --- a/cmake/modules/dts.cmake +++ b/cmake/modules/dts.cmake @@ -70,9 +70,9 @@ find_package(Dtc 1.4.6) # # Optional variables: # - BOARD: board name to use when looking for DTS_SOURCE -# - BOARD_DIR: board directory to use when looking for DTS_SOURCE +# - BOARD_DIRECTORIES: list of board directories to use when looking for DTS_SOURCE # - BOARD_REVISION_STRING: used when looking for a board revision's -# devicetree overlay file in BOARD_DIR +# devicetree overlay file in one of the BOARD_DIRECTORIES # - DTC_OVERLAY_FILE: list of devicetree overlay files which will be # used to modify or extend the base devicetree. # - EXTRA_DTC_OVERLAY_FILE: list of extra devicetree overlay files. @@ -86,7 +86,7 @@ find_package(Dtc 1.4.6) # C preprocessor when generating the devicetree from DTS_SOURCE # - DTS_SOURCE: the devicetree source file to use may be pre-set # with this variable; otherwise, it defaults to -# ${BOARD_DIR}/${BOARD}.dts +# ${BOARD_DIRECTORIES}/.dts # # Variables set by this module and not mentioned above are for internal # use only, and may be removed, renamed, or re-purposed without prior notice. @@ -117,6 +117,8 @@ set(GEN_DTS_CMAKE_SCRIPT ${DT_SCRIPTS}/gen_dts_cmake.py) # The generated information itself, which we include() after # creating it. set(DTS_CMAKE ${PROJECT_BINARY_DIR}/dts.cmake) +# The CMake target to be initialized by including ${DTS_CMAKE}. +set(DEVICETREE_TARGET devicetree_target) # The location of a file containing known vendor prefixes, relative to # each element of DTS_ROOT. Users can define their own in their own @@ -127,28 +129,30 @@ if(NOT DEFINED DTS_SOURCE) zephyr_build_string(board_string SHORT shortened_board_string BOARD ${BOARD} BOARD_QUALIFIERS ${BOARD_QUALIFIERS} ) - if(EXISTS ${BOARD_DIR}/${shortened_board_string}.dts AND NOT BOARD_${BOARD}_SINGLE_SOC) - message(FATAL_ERROR "Board ${ZFILE_BOARD} defines multiple SoCs.\nShortened file name " - "(${shortened_board_string}.dts) not allowed, use '_.dts' naming" - ) - elseif(EXISTS ${BOARD_DIR}/${board_string}.dts AND EXISTS ${BOARD_DIR}/${shortened_board_string}.dts) - message(FATAL_ERROR "Conflicting file names discovered. Cannot use both " - "${board_string}.dts and ${shortened_board_string}.dts. " - "Please choose one naming style, ${board_string}.dts is recommended." - ) - elseif(EXISTS ${BOARD_DIR}/${board_string}.dts) - set(DTS_SOURCE ${BOARD_DIR}/${board_string}.dts) - elseif(EXISTS ${BOARD_DIR}/${shortened_board_string}.dts) - set(DTS_SOURCE ${BOARD_DIR}/${shortened_board_string}.dts) - endif() + foreach(dir ${BOARD_DIRECTORIES}) + if(EXISTS ${dir}/${shortened_board_string}.dts AND NOT BOARD_${BOARD}_SINGLE_SOC) + message(FATAL_ERROR "Board ${ZFILE_BOARD} defines multiple SoCs.\nShortened file name " + "(${shortened_board_string}.dts) not allowed, use '_.dts' naming" + ) + elseif(EXISTS ${dir}/${board_string}.dts AND EXISTS ${dir}/${shortened_board_string}.dts) + message(FATAL_ERROR "Conflicting file names discovered. Cannot use both " + "${board_string}.dts and ${shortened_board_string}.dts. " + "Please choose one naming style, ${board_string}.dts is recommended." + ) + elseif(EXISTS ${dir}/${board_string}.dts) + set(DTS_SOURCE ${dir}/${board_string}.dts) + elseif(EXISTS ${dir}/${shortened_board_string}.dts) + set(DTS_SOURCE ${dir}/${shortened_board_string}.dts) + endif() + endforeach() endif() if(EXISTS ${DTS_SOURCE}) # We found a devicetree. Append all relevant dts overlays we can find... - zephyr_file(CONF_FILES ${BOARD_DIR} DTS DTS_SOURCE) + zephyr_file(CONF_FILES ${BOARD_DIRECTORIES} DTS DTS_SOURCE) zephyr_file( - CONF_FILES ${BOARD_DIR} + CONF_FILES ${BOARD_DIRECTORIES} DTS no_rev_suffix_dts_board_overlays BOARD ${BOARD} BOARD_QUALIFIERS ${BOARD_QUALIFIERS} diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index 4d8422a3ced..b9812d84379 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -3611,6 +3611,9 @@ endfunction() # alias at the beginning of a path interchangeably with the full # path to the aliased node in these functions. The usage comments # will make this clear in each case. +# +# - Each of these methods also has a sysbuild_dt_* counterpart. +# See share/sysbuild/cmake/modules/sysbuild_extensions.cmake. # Usage: # dt_nodelabel( NODELABEL