+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @defgroup BasicAbs Vector Absolute Value
+
+ Computes the absolute value of a vector on an element-by-element basis.
+
+
+ pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
+
+
+ The functions support in-place computation allowing the source and
+ destination pointers to reference the same memory buffer.
+ There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup BasicAbs
+ @{
+ */
+
+/**
+ @brief Floating-point vector absolute value.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_abs_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ float32x4_t vec1;
+ float32x4_t res;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute values and then store the results in the destination buffer. */
+ vec1 = vld1q_f32(pSrc);
+ res = vabsq_f32(vec1);
+ vst1q_f32(pDst, res);
+
+ /* Increment pointers */
+ pSrc += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute and store result in destination buffer. */
+ *pDst++ = fabsf(*pSrc++);
+
+ *pDst++ = fabsf(*pSrc++);
+
+ *pDst++ = fabsf(*pSrc++);
+
+ *pDst++ = fabsf(*pSrc++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute and store result in destination buffer. */
+ *pDst++ = fabsf(*pSrc++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicAbs group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c
new file mode 100644
index 000000000..eb944ced9
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_abs_q15.c
+ * Description: Q15 vector absolute value
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicAbs
+ @{
+ */
+
+/**
+ @brief Q15 vector absolute value.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_abs_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q15_t in; /* Temporary input variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicAbs group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c
new file mode 100644
index 000000000..bf7608bd7
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_abs_q31.c
+ * Description: Q31 vector absolute value
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicAbs
+ @{
+ */
+
+/**
+ @brief Q31 vector absolute value.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_abs_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t in; /* Temporary variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicAbs group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c
new file mode 100644
index 000000000..a6c4a6cb6
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_abs_q7.c
+ * Description: Q7 vector absolute value
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicAbs
+ @{
+ */
+
+/**
+ @brief Q7 vector absolute value.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Conditions for optimum performance
+ Input and output buffers should be aligned by 32-bit
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_abs_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q7_t in; /* Temporary input variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q7_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q7_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q7_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q7_t)__QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = |A| */
+
+ /* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (in > 0) ? in : (q7_t) __QSUB(0, in);
+#else
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicAbs group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c
new file mode 100644
index 000000000..1c66a24cb
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_add_f32.c
+ * Description: Floating-point vector addition
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @defgroup BasicAdd Vector Addition
+
+ Element-by-element addition of two vectors.
+
+
+ pDst[n] = pSrcA[n] + pSrcB[n], 0 <= n < blockSize.
+
+
+ There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup BasicAdd
+ @{
+ */
+
+/**
+ @brief Floating-point vector addition.
+ @param[in] pSrcA points to first input vector
+ @param[in] pSrcB points to second input vector
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_add_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ float32x4_t vec1;
+ float32x4_t vec2;
+ float32x4_t res;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+ /* Add and then store the results in the destination buffer. */
+ vec1 = vld1q_f32(pSrcA);
+ vec2 = vld1q_f32(pSrcB);
+ res = vaddq_f32(vec1, vec2);
+ vst1q_f32(pDst, res);
+
+ /* Increment pointers */
+ pSrcA += 4;
+ pSrcB += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+ /* Add and store result in destination buffer. */
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+ /* Add and store result in destination buffer. */
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicAdd group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c
new file mode 100644
index 000000000..bc629370f
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c
@@ -0,0 +1,126 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_add_q15.c
+ * Description: Q15 vector addition
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicAdd
+ @{
+ */
+
+/**
+ @brief Q15 vector addition.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+ */
+
+void arm_add_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q31_t inA1, inA2;
+ q31_t inB1, inB2;
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+#if defined (ARM_MATH_DSP)
+ /* read 2 times 2 samples at a time from sourceA */
+ inA1 = read_q15x2_ia ((q15_t **) &pSrcA);
+ inA2 = read_q15x2_ia ((q15_t **) &pSrcA);
+ /* read 2 times 2 samples at a time from sourceB */
+ inB1 = read_q15x2_ia ((q15_t **) &pSrcB);
+ inB2 = read_q15x2_ia ((q15_t **) &pSrcB);
+
+ /* Add and store 2 times 2 samples at a time */
+ write_q15x2_ia (&pDst, __QADD16(inA1, inB1));
+ write_q15x2_ia (&pDst, __QADD16(inA2, inB2));
+#else
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+ /* Add and store result in destination buffer. */
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
+#else
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ + *pSrcB++), 16);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicAdd group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c
new file mode 100644
index 000000000..3c1cbc24b
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c
@@ -0,0 +1,108 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_add_q31.c
+ * Description: Q31 vector addition
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicAdd
+ @{
+ */
+
+/**
+ @brief Q31 vector addition.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
+ */
+
+void arm_add_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+ /* Add and store result in destination buffer. */
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+ /* Add and store result in destination buffer. */
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicAdd group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c
new file mode 100644
index 000000000..f9c4a95ec
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_add_q7.c
+ * Description: Q7 vector addition
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicAdd
+ @{
+ */
+
+/**
+ @brief Q7 vector addition.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
+ */
+
+void arm_add_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+#if defined (ARM_MATH_DSP)
+ /* Add and store result in destination buffer (4 samples at a time). */
+ write_q7x4_ia (&pDst, __QADD8 (read_q7x4_ia ((q7_t **) &pSrcA), read_q7x4_ia ((q7_t **) &pSrcB)));
+#else
+ *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8);
+ *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8);
+ *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8);
+ *pDst++ = (q7_t) __SSAT ((q15_t) *pSrcA++ + *pSrcB++, 8);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + B */
+
+ /* Add and store result in destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicAdd group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c
new file mode 100644
index 000000000..3eee3b97a
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dot_prod_f32.c
+ * Description: Floating-point dot product
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @defgroup BasicDotProd Vector Dot Product
+
+ Computes the dot product of two vectors.
+ The vectors are multiplied element-by-element and then summed.
+
+
+ sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+
+
+ There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup BasicDotProd
+ @{
+ */
+
+/**
+ @brief Dot product of floating-point vectors.
+ @param[in] pSrcA points to the first input vector.
+ @param[in] pSrcB points to the second input vector.
+ @param[in] blockSize number of samples in each vector.
+ @param[out] result output result returned here.
+ @return none
+ */
+
+void arm_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t sum = 0.0f; /* Temporary return variable */
+
+#if defined(ARM_MATH_NEON)
+ float32x4_t vec1;
+ float32x4_t vec2;
+ float32x4_t res;
+ float32x4_t accum = vdupq_n_f32(0);
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ vec1 = vld1q_f32(pSrcA);
+ vec2 = vld1q_f32(pSrcB);
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]*B[0] + A[1]*B[1] + A[2]*B[2] + ... + A[blockSize-1]*B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+
+ accum = vmlaq_f32(accum, vec1, vec2);
+
+ /* Increment pointers */
+ pSrcA += 4;
+ pSrcB += 4;
+
+ vec1 = vld1q_f32(pSrcA);
+ vec2 = vld1q_f32(pSrcB);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#if __aarch64__
+ sum = vpadds_f32(vpadd_f32(vget_low_f32(accum), vget_high_f32(accum)));
+#else
+ sum = (vpadd_f32(vget_low_f32(accum), vget_high_f32(accum)))[0] + (vpadd_f32(vget_low_f32(accum), vget_high_f32(accum)))[1];
+#endif
+
+ /* Tail */
+ blkCnt = blockSize & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+
+ /* Calculate dot product and store result in a temporary buffer. */
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+
+ /* Calculate dot product and store result in a temporary buffer. */
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store result in destination buffer */
+ *result = sum;
+}
+
+/**
+ @} end of BasicDotProd group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c
new file mode 100644
index 000000000..e303b090d
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dot_prod_q15.c
+ * Description: Q15 dot product
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicDotProd
+ @{
+ */
+
+/**
+ @brief Dot product of Q15 vectors.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] blockSize number of samples in each vector
+ @param[out] result output result returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these
+ results are added to a 64-bit accumulator in 34.30 format.
+ Nonsaturating additions are used and given that there are 33 guard bits in the accumulator
+ there is no risk of overflow.
+ The return result is in 34.30 format.
+ */
+
+void arm_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t sum = 0; /* Temporary return variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+
+#if defined (ARM_MATH_DSP)
+ /* Calculate dot product and store result in a temporary buffer. */
+ sum = __SMLALD(read_q15x2_ia ((q15_t **) &pSrcA), read_q15x2_ia ((q15_t **) &pSrcB), sum);
+ sum = __SMLALD(read_q15x2_ia ((q15_t **) &pSrcA), read_q15x2_ia ((q15_t **) &pSrcB), sum);
+#else
+ sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++);
+ sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++);
+ sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++);
+ sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+
+ /* Calculate dot product and store result in a temporary buffer. */
+//#if defined (ARM_MATH_DSP)
+// sum = __SMLALD(*pSrcA++, *pSrcB++, sum);
+//#else
+ sum += (q63_t)((q31_t) *pSrcA++ * *pSrcB++);
+//#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store result in destination buffer in 34.30 format */
+ *result = sum;
+}
+
+/**
+ @} end of BasicDotProd group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c
new file mode 100644
index 000000000..76cd5776f
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dot_prod_q31.c
+ * Description: Q31 dot product
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicDotProd
+ @{
+ */
+
+/**
+ @brief Dot product of Q31 vectors.
+ @param[in] pSrcA points to the first input vector.
+ @param[in] pSrcB points to the second input vector.
+ @param[in] blockSize number of samples in each vector.
+ @param[out] result output result returned here.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these
+ are truncated to 2.48 format by discarding the lower 14 bits.
+ The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ There are 15 guard bits in the accumulator and there is no risk of overflow as long as
+ the length of the vectors is less than 2^16 elements.
+ The return result is in 16.48 format.
+ */
+
+void arm_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t sum = 0; /* Temporary return variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+
+ /* Calculate dot product and store result in a temporary buffer. */
+ sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U;
+
+ sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U;
+
+ sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U;
+
+ sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+
+ /* Calculate dot product and store result in a temporary buffer. */
+ sum += ((q63_t) *pSrcA++ * *pSrcB++) >> 14U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store result in destination buffer in 16.48 format */
+ *result = sum;
+}
+
+/**
+ @} end of BasicDotProd group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c
new file mode 100644
index 000000000..8e18a7397
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dot_prod_q7.c
+ * Description: Q7 dot product
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicDotProd
+ @{
+ */
+
+/**
+ @brief Dot product of Q7 vectors.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] blockSize number of samples in each vector
+ @param[out] result output result returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these
+ results are added to an accumulator in 18.14 format.
+ Nonsaturating additions are used and there is no danger of wrap around as long as
+ the vectors are less than 2^18 elements long.
+ The return result is in 18.14 format.
+ */
+
+void arm_dot_prod_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t sum = 0; /* Temporary return variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q31_t input1, input2; /* Temporary variables */
+ q31_t inA1, inA2, inB1, inB2; /* Temporary variables */
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+
+#if defined (ARM_MATH_DSP)
+ /* read 4 samples at a time from sourceA */
+ input1 = read_q7x4_ia ((q7_t **) &pSrcA);
+ /* read 4 samples at a time from sourceB */
+ input2 = read_q7x4_ia ((q7_t **) &pSrcB);
+
+ /* extract two q7_t samples to q15_t samples */
+ inA1 = __SXTB16(__ROR(input1, 8));
+ /* extract reminaing two samples */
+ inA2 = __SXTB16(input1);
+ /* extract two q7_t samples to q15_t samples */
+ inB1 = __SXTB16(__ROR(input2, 8));
+ /* extract reminaing two samples */
+ inB2 = __SXTB16(input2);
+
+ /* multiply and accumulate two samples at a time */
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+#else
+ sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++);
+ sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++);
+ sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++);
+ sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+
+ /* Calculate dot product and store result in a temporary buffer. */
+//#if defined (ARM_MATH_DSP)
+// sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
+//#else
+ sum += (q31_t) ((q15_t) *pSrcA++ * *pSrcB++);
+//#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store result in destination buffer in 18.14 format */
+ *result = sum;
+}
+
+/**
+ @} end of BasicDotProd group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c
new file mode 100644
index 000000000..53ad73c81
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mult_f32.c
+ * Description: Floating-point vector multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @defgroup BasicMult Vector Multiplication
+
+ Element-by-element multiplication of two vectors.
+
+
+ pDst[n] = pSrcA[n] * pSrcB[n], 0 <= n < blockSize.
+
+
+ There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup BasicMult
+ @{
+ */
+
+/**
+ @brief Floating-point vector multiplication.
+ @param[in] pSrcA points to the first input vector.
+ @param[in] pSrcB points to the second input vector.
+ @param[out] pDst points to the output vector.
+ @param[in] blockSize number of samples in each vector.
+ @return none
+ */
+
+void arm_mult_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ float32x4_t vec1;
+ float32x4_t vec2;
+ float32x4_t res;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ vec1 = vld1q_f32(pSrcA);
+ vec2 = vld1q_f32(pSrcB);
+ res = vmulq_f32(vec1, vec2);
+ vst1q_f32(pDst, res);
+
+ /* Increment pointers */
+ pSrcA += 4;
+ pSrcB += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+
+ /* Multiply inputs and store result in destination buffer. */
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+
+ /* Multiply input and store result in destination buffer. */
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicMult group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c
new file mode 100644
index 000000000..5587ce5e3
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mult_q7.c
+ * Description: Q7 vector multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicMult
+ @{
+ */
+
+/**
+ @brief Q7 vector multiplication
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
+ */
+
+void arm_mult_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q7_t out1, out2, out3, out4; /* Temporary output variables */
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+
+#if defined (ARM_MATH_DSP)
+ /* Multiply inputs and store results in temporary variables */
+ out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Pack and store result in destination buffer (in single write) */
+ write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4));
+#else
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * B */
+
+ /* Multiply input and store result in destination buffer. */
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicMult group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c
new file mode 100644
index 000000000..f807112c1
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_negate_f32.c
+ * Description: Negates floating-point vectors
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @defgroup BasicNegate Vector Negate
+
+ Negates the elements of a vector.
+
+
+ pDst[n] = -pSrc[n], 0 <= n < blockSize.
+
+
+ The functions support in-place computation allowing the source and
+ destination pointers to reference the same memory buffer.
+ There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup BasicNegate
+ @{
+ */
+
+/**
+ @brief Negates the elements of a floating-point vector.
+ @param[in] pSrc points to input vector.
+ @param[out] pDst points to output vector.
+ @param[in] blockSize number of samples in each vector.
+ @return none
+ */
+
+void arm_negate_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+ float32x4_t vec1;
+ float32x4_t res;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+ /* Negate and then store the results in the destination buffer. */
+ vec1 = vld1q_f32(pSrc);
+ res = vnegq_f32(vec1);
+ vst1q_f32(pDst, res);
+
+ /* Increment pointers */
+ pSrc += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+ /* Negate and store result in destination buffer. */
+ *pDst++ = -*pSrc++;
+
+ *pDst++ = -*pSrc++;
+
+ *pDst++ = -*pSrc++;
+
+ *pDst++ = -*pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+ /* Negate and store result in destination buffer. */
+ *pDst++ = -*pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicNegate group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c
new file mode 100644
index 000000000..267e4cc90
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c
@@ -0,0 +1,126 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_negate_q15.c
+ * Description: Negates Q15 vectors
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicNegate
+ @{
+ */
+
+/**
+ @brief Negates the elements of a Q15 vector.
+ @param[in] pSrc points to the input vector.
+ @param[out] pDst points to the output vector.
+ @param[in] blockSize number of samples in each vector.
+ @return none
+
+ @par Conditions for optimum performance
+ Input and output buffers should be aligned by 32-bit
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_negate_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q15_t in; /* Temporary input variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q31_t in1; /* Temporary input variables */
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+#if defined (ARM_MATH_DSP)
+ /* Negate and store result in destination buffer (2 samples at a time). */
+ in1 = read_q15x2_ia ((q15_t **) &pSrc);
+ write_q15x2_ia (&pDst, __QSUB16(0, in1));
+
+ in1 = read_q15x2_ia ((q15_t **) &pSrc);
+ write_q15x2_ia (&pDst, __QSUB16(0, in1));
+#else
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in;
+
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in;
+
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in;
+
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in;
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+ /* Negate and store result in destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicNegate group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c
new file mode 100644
index 000000000..645fb0ac0
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_negate_q31.c
+ * Description: Negates Q31 vectors
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicNegate
+ @{
+ */
+
+/**
+ @brief Negates the elements of a Q31 vector.
+ @param[in] pSrc points to the input vector.
+ @param[out] pDst points to the output vector.
+ @param[in] blockSize number of samples in each vector.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_negate_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t in; /* Temporary input variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+ /* Negate and store result in destination buffer. */
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+ /* Negate and store result in destination buffer. */
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicNegate group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c
new file mode 100644
index 000000000..40a373e06
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c
@@ -0,0 +1,126 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_negate_q7.c
+ * Description: Negates Q7 vectors
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicNegate
+ @{
+ */
+
+/**
+ @brief Negates the elements of a Q7 vector.
+ @param[in] pSrc points to the input vector.
+ @param[out] pDst points to the output vector.
+ @param[in] blockSize number of samples in each vector.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ The Q7 value -1 (0x80) is saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_negate_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q7_t in; /* Temporary input variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q31_t in1; /* Temporary input variable */
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+#if defined (ARM_MATH_DSP)
+ /* Negate and store result in destination buffer (4 samples at a time). */
+ in1 = read_q7x4_ia ((q7_t **) &pSrc);
+ write_q7x4_ia (&pDst, __QSUB8(0, in1));
+#else
+ in = *pSrc++;
+ *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in;
+
+ in = *pSrc++;
+ *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in;
+
+ in = *pSrc++;
+ *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in;
+
+ in = *pSrc++;
+ *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in;
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = -A */
+
+ /* Negate and store result in destination buffer. */
+ in = *pSrc++;
+
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (q7_t) __QSUB(0, in);
+#else
+ *pDst++ = (in == (q7_t) 0x80) ? (q7_t) 0x7f : -in;
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicNegate group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c
new file mode 100644
index 000000000..b10e3f1d4
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c
@@ -0,0 +1,147 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_offset_f32.c
+ * Description: Floating-point vector offset
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @defgroup BasicOffset Vector Offset
+
+ Adds a constant offset to each element of a vector.
+
+
+ pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
+
+
+ The functions support in-place computation allowing the source and
+ destination pointers to reference the same memory buffer.
+ There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup BasicOffset
+ @{
+ */
+
+/**
+ @brief Adds a constant offset to a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] offset is the offset to be added
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_offset_f32(
+ const float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+ float32x4_t vec1;
+ float32x4_t res;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+ /* Add offset and then store the results in the destination buffer. */
+ vec1 = vld1q_f32(pSrc);
+ res = vaddq_f32(vec1,vdupq_n_f32(offset));
+ vst1q_f32(pDst, res);
+
+ /* Increment pointers */
+ pSrc += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+ /* Add offset and store result in destination buffer. */
+ *pDst++ = (*pSrc++) + offset;
+
+ *pDst++ = (*pSrc++) + offset;
+
+ *pDst++ = (*pSrc++) + offset;
+
+ *pDst++ = (*pSrc++) + offset;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+ /* Add offset and store result in destination buffer. */
+ *pDst++ = (*pSrc++) + offset;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicOffset group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c
new file mode 100644
index 000000000..cd2f22b58
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_offset_q15.c
+ * Description: Q15 vector offset
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicOffset
+ @{
+ */
+
+/**
+ @brief Adds a constant offset to a Q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] offset is the offset to be added
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+ */
+
+void arm_offset_q15(
+ const q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PKHBT(offset, offset, 16);
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+#if defined (ARM_MATH_DSP)
+ /* Add offset and store result in destination buffer (2 samples at a time). */
+ write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia ((q15_t **) &pSrc), offset_packed));
+ write_q15x2_ia (&pDst, __QADD16(read_q15x2_ia ((q15_t **) &pSrc), offset_packed));
+#else
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+ /* Add offset and store result in destination buffer. */
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
+#else
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrc++ + offset), 16);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicOffset group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c
new file mode 100644
index 000000000..5de36b4b4
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c
@@ -0,0 +1,128 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_offset_q31.c
+ * Description: Q31 vector offset
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicOffset
+ @{
+ */
+
+/**
+ @brief Adds a constant offset to a Q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] offset is the offset to be added
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
+ */
+
+void arm_offset_q31(
+ const q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+ /* Add offset and store result in destination buffer. */
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QADD(*pSrc++, offset);
+#else
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+#endif
+
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QADD(*pSrc++, offset);
+#else
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+#endif
+
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QADD(*pSrc++, offset);
+#else
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+#endif
+
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QADD(*pSrc++, offset);
+#else
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+ /* Add offset and store result in destination buffer. */
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QADD(*pSrc++, offset);
+#else
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicOffset group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c
new file mode 100644
index 000000000..f67db4565
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_offset_q7.c
+ * Description: Q7 vector offset
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicOffset
+ @{
+ */
+
+/**
+ @brief Adds a constant offset to a Q7 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] offset is the offset to be added
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
+ */
+
+void arm_offset_q7(
+ const q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PACKq7(offset, offset, offset, offset);
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+#if defined (ARM_MATH_DSP)
+ /* Add offset and store result in destination buffer (4 samples at a time). */
+ write_q7x4_ia (&pDst, __QADD8(read_q7x4_ia ((q7_t **) &pSrc), offset_packed));
+#else
+ *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+ *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+ *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+ *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A + offset */
+
+ /* Add offset and store result in destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) *pSrc++ + offset, 8);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicOffset group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c
new file mode 100644
index 000000000..72ecbe5cb
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_scale_f32.c
+ * Description: Multiplies a floating-point vector by a scalar
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @defgroup BasicScale Vector Scale
+
+ Multiply a vector by a scalar value. For floating-point data, the algorithm used is:
+
+
+ pDst[n] = pSrc[n] * scale, 0 <= n < blockSize.
+
+
+ In the fixed-point Q7, Q15, and Q31 functions, scale is represented by
+ a fractional multiplication scaleFract and an arithmetic shift shift.
+ The shift allows the gain of the scaling operation to exceed 1.0.
+ The algorithm used with fixed-point data is:
+
+
+ pDst[n] = (pSrc[n] * scaleFract) << shift, 0 <= n < blockSize.
+
+
+ The overall scale factor applied to the fixed-point data is
+
+ scale = scaleFract * 2^shift.
+
+
+ The functions support in-place computation allowing the source and destination
+ pointers to reference the same memory buffer.
+ */
+
+/**
+ @addtogroup BasicScale
+ @{
+ */
+
+/**
+ @brief Multiplies a floating-point vector by a scalar.
+ @param[in] pSrc points to the input vector
+ @param[in] scale scale factor to be applied
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_scale_f32(
+ const float32_t *pSrc,
+ float32_t scale,
+ float32_t *pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+ float32x4_t vec1;
+ float32x4_t res;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale the input and then store the results in the destination buffer. */
+ vec1 = vld1q_f32(pSrc);
+ res = vmulq_f32(vec1, vdupq_n_f32(scale));
+ vst1q_f32(pDst, res);
+
+ /* Increment pointers */
+ pSrc += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale input and store result in destination buffer. */
+ *pDst++ = (*pSrc++) * scale;
+
+ *pDst++ = (*pSrc++) * scale;
+
+ *pDst++ = (*pSrc++) * scale;
+
+ *pDst++ = (*pSrc++) * scale;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON_EXPERIMENTAL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale input and store result in destination buffer. */
+ *pDst++ = (*pSrc++) * scale;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicScale group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c
new file mode 100644
index 000000000..039b93dd6
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c
@@ -0,0 +1,144 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_scale_q15.c
+ * Description: Multiplies a Q15 vector by a scalar
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicScale
+ @{
+ */
+
+/**
+ @brief Multiplies a Q15 vector by a scalar.
+ @param[in] pSrc points to the input vector
+ @param[in] scaleFract fractional portion of the scale value
+ @param[in] shift number of bits to shift the result by
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The input data *pSrc and scaleFract are in 1.15 format.
+ These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+void arm_scale_q15(
+ const q15_t *pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t *pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ int8_t kShift = 15 - shift; /* Shift to apply after scaling */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+#if defined (ARM_MATH_DSP)
+ q31_t inA1, inA2;
+ q31_t out1, out2, out3, out4; /* Temporary output variables */
+ q15_t in1, in2, in3, in4; /* Temporary input variables */
+#endif
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+#if defined (ARM_MATH_DSP)
+ /* read 2 times 2 samples at a time from source */
+ inA1 = read_q15x2_ia ((q15_t **) &pSrc);
+ inA2 = read_q15x2_ia ((q15_t **) &pSrc);
+
+ /* Scale inputs and store result in temporary variables
+ * in single cycle by packing the outputs */
+ out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+ out2 = (q31_t) ((q15_t) (inA1 ) * scaleFract);
+ out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+ out4 = (q31_t) ((q15_t) (inA2 ) * scaleFract);
+
+ /* apply shifting */
+ out1 = out1 >> kShift;
+ out2 = out2 >> kShift;
+ out3 = out3 >> kShift;
+ out4 = out4 >> kShift;
+
+ /* saturate the output */
+ in1 = (q15_t) (__SSAT(out1, 16));
+ in2 = (q15_t) (__SSAT(out2, 16));
+ in3 = (q15_t) (__SSAT(out3, 16));
+ in4 = (q15_t) (__SSAT(out4, 16));
+
+ /* store result to destination */
+ write_q15x2_ia (&pDst, __PKHBT(in2, in1, 16));
+ write_q15x2_ia (&pDst, __PKHBT(in4, in3, 16));
+#else
+ *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16));
+ *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16));
+ *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16));
+ *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16));
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale input and store result in destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((q31_t) *pSrc++ * scaleFract) >> kShift, 16));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicScale group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c
new file mode 100644
index 000000000..d762ca7c7
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c
@@ -0,0 +1,191 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_scale_q31.c
+ * Description: Multiplies a Q31 vector by a scalar
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicScale
+ @{
+ */
+
+/**
+ @brief Multiplies a Q31 vector by a scalar.
+ @param[in] pSrc points to the input vector
+ @param[in] scaleFract fractional portion of the scale value
+ @param[in] shift number of bits to shift the result by
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The input data *pSrc and scaleFract are in 1.31 format.
+ These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+void arm_scale_q31(
+ const q31_t *pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t *pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t in, out; /* Temporary variables */
+ int8_t kShift = shift + 1; /* Shift to apply after scaling */
+ int8_t sign = (kShift & 0x80);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ if (sign == 0U)
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale input and store result in destination buffer. */
+ in = *pSrc++; /* read input from source */
+ in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */
+ out = in << kShift; /* apply shifting */
+ if (in != (out >> kShift)) /* saturate the result */
+ out = 0x7FFFFFFF ^ (in >> 31);
+ *pDst++ = out; /* Store result destination */
+
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+ out = in << kShift;
+ if (in != (out >> kShift))
+ out = 0x7FFFFFFF ^ (in >> 31);
+ *pDst++ = out;
+
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+ out = in << kShift;
+ if (in != (out >> kShift))
+ out = 0x7FFFFFFF ^ (in >> 31);
+ *pDst++ = out;
+
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+ out = in << kShift;
+ if (in != (out >> kShift))
+ out = 0x7FFFFFFF ^ (in >> 31);
+ *pDst++ = out;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale input and store result in destination buffer. */
+ in = *pSrc++; /* read four inputs from source */
+ in = ((q63_t) in * scaleFract) >> 32; /* multiply input with scaler value */
+ out = in >> -kShift; /* apply shifting */
+ *pDst++ = out; /* Store result destination */
+
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+ out = in >> -kShift;
+ *pDst++ = out;
+
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+ out = in >> -kShift;
+ *pDst++ = out;
+
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+ out = in >> -kShift;
+ *pDst++ = out;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ if (sign == 0U)
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale input and store result in destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+ out = in << kShift;
+ if (in != (out >> kShift))
+ out = 0x7FFFFFFF ^ (in >> 31);
+ *pDst++ = out;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale input and store result in destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+ out = in >> -kShift;
+ *pDst++ = out;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+}
+
+/**
+ @} end of BasicScale group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c
new file mode 100644
index 000000000..cb967d280
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_scale_q7.c
+ * Description: Multiplies a Q7 vector by a scalar
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicScale
+ @{
+ */
+
+/**
+ @brief Multiplies a Q7 vector by a scalar.
+ @param[in] pSrc points to the input vector
+ @param[in] scaleFract fractional portion of the scale value
+ @param[in] shift number of bits to shift the result by
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The input data *pSrc and scaleFract are in 1.7 format.
+ These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.
+ */
+
+void arm_scale_q7(
+ const q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ int8_t kShift = 7 - shift; /* Shift to apply after scaling */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q7_t in1, in2, in3, in4; /* Temporary input variables */
+ q7_t out1, out2, out3, out4; /* Temporary output variables */
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+#if defined (ARM_MATH_DSP)
+ /* Reading 4 inputs from memory */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ /* Scale inputs and store result in the temporary variable. */
+ out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
+ out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
+ out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
+ out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
+
+ /* Pack and store result in destination buffer (in single write) */
+ write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4));
+#else
+ *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8));
+ *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8));
+ *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8));
+ *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8));
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * scale */
+
+ /* Scale input and store result in destination buffer. */
+ *pDst++ = (q7_t) (__SSAT((((q15_t) *pSrc++ * scaleFract) >> kShift), 8));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicScale group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c
new file mode 100644
index 000000000..c4163fc87
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c
@@ -0,0 +1,175 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_shift_q7.c
+ * Description: Processing function for the Q7 Shifting
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicShift
+ @{
+ */
+
+/**
+ @brief Shifts the elements of a Q7 vector a specified number of bits
+ @param[in] pSrc points to the input vector
+ @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par onditions for optimum performance
+ Input and output buffers should be aligned by 32-bit
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
+ */
+
+void arm_shift_q7(
+ const q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q7_t in1, in2, in3, in4; /* Temporary input variables */
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ /* If the shift value is positive then do right shift else left shift */
+ if (sign == 0U)
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A << shiftBits */
+
+#if defined (ARM_MATH_DSP)
+ /* Read 4 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ /* Pack and store result in destination buffer (in single write) */
+ write_q7x4_ia (&pDst, __PACKq7(__SSAT((in1 << shiftBits), 8),
+ __SSAT((in2 << shiftBits), 8),
+ __SSAT((in3 << shiftBits), 8),
+ __SSAT((in4 << shiftBits), 8) ));
+#else
+ *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8);
+ *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8);
+ *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8);
+ *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A >> shiftBits */
+
+#if defined (ARM_MATH_DSP)
+ /* Read 4 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ /* Pack and store result in destination buffer (in single write) */
+ write_q7x4_ia (&pDst, __PACKq7((in1 >> -shiftBits),
+ (in2 >> -shiftBits),
+ (in3 >> -shiftBits),
+ (in4 >> -shiftBits) ));
+#else
+ *pDst++ = (*pSrc++ >> -shiftBits);
+ *pDst++ = (*pSrc++ >> -shiftBits);
+ *pDst++ = (*pSrc++ >> -shiftBits);
+ *pDst++ = (*pSrc++ >> -shiftBits);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* If the shift value is positive then do right shift else left shift */
+ if (sign == 0U)
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A << shiftBits */
+
+ /* Shift input and store result in destination buffer. */
+ *pDst++ = (q7_t) __SSAT(((q15_t) *pSrc++ << shiftBits), 8);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ while (blkCnt > 0U)
+ {
+ /* C = A >> shiftBits */
+
+ /* Shift input and store result in destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+}
+
+/**
+ @} end of BasicShift group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c
new file mode 100644
index 000000000..4c97af307
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sub_f32.c
+ * Description: Floating-point vector subtraction
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @defgroup BasicSub Vector Subtraction
+
+ Element-by-element subtraction of two vectors.
+
+
+ pDst[n] = pSrcA[n] - pSrcB[n], 0 <= n < blockSize.
+
+
+ There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup BasicSub
+ @{
+ */
+
+/**
+ @brief Floating-point vector subtraction.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_sub_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ float32x4_t vec1;
+ float32x4_t vec2;
+ float32x4_t res;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+ /* Subtract and then store the results in the destination buffer. */
+ vec1 = vld1q_f32(pSrcA);
+ vec2 = vld1q_f32(pSrcB);
+ res = vsubq_f32(vec1, vec2);
+ vst1q_f32(pDst, res);
+
+ /* Increment pointers */
+ pSrcA += 4;
+ pSrcB += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = blockSize & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+ /* Subtract and store result in destination buffer. */
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+ /* Subtract and store result in destination buffer. */
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicSub group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c
new file mode 100644
index 000000000..835917e5f
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c
@@ -0,0 +1,126 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sub_q15.c
+ * Description: Q15 vector subtraction
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicSub
+ @{
+ */
+
+/**
+ @brief Q15 vector subtraction.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+ */
+
+void arm_sub_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q31_t inA1, inA2;
+ q31_t inB1, inB2;
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+#if defined (ARM_MATH_DSP)
+ /* read 2 times 2 samples at a time from sourceA */
+ inA1 = read_q15x2_ia ((q15_t **) &pSrcA);
+ inA2 = read_q15x2_ia ((q15_t **) &pSrcA);
+ /* read 2 times 2 samples at a time from sourceB */
+ inB1 = read_q15x2_ia ((q15_t **) &pSrcB);
+ inB2 = read_q15x2_ia ((q15_t **) &pSrcB);
+
+ /* Subtract and store 2 times 2 samples at a time */
+ write_q15x2_ia (&pDst, __QSUB16(inA1, inB1));
+ write_q15x2_ia (&pDst, __QSUB16(inA2, inB2));
+#else
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16);
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+ /* Subtract and store result in destination buffer. */
+#if defined (ARM_MATH_DSP)
+ *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
+#else
+ *pDst++ = (q15_t) __SSAT(((q31_t) *pSrcA++ - *pSrcB++), 16);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicSub group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c
new file mode 100644
index 000000000..bac1927bd
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c
@@ -0,0 +1,108 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sub_q31.c
+ * Description: Q31 vector subtraction
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicSub
+ @{
+ */
+
+/**
+ @brief Q31 vector subtraction.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
+ */
+
+void arm_sub_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+ /* Subtract and store result in destination buffer. */
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+ /* Subtract and store result in destination buffer. */
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicSub group
+ */
diff --git a/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c b/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c
new file mode 100644
index 000000000..a55a8fd71
--- /dev/null
+++ b/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sub_q7.c
+ * Description: Q7 vector subtraction
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMath
+ */
+
+/**
+ @addtogroup BasicSub
+ @{
+ */
+
+/**
+ @brief Q7 vector subtraction.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[out] pDst points to the output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_sub_q7(
+ const q7_t * pSrcA,
+ const q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+#if defined (ARM_MATH_DSP)
+ /* Subtract and store result in destination buffer (4 samples at a time). */
+ write_q7x4_ia (&pDst, __QSUB8(read_q7x4_ia ((q7_t **) &pSrcA), read_q7x4_ia ((q7_t **) &pSrcB)));
+#else
+ *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8);
+ *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8);
+ *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8);
+ *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A - B */
+
+ /* Subtract and store result in destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) *pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of BasicSub group
+ */
diff --git a/CMSIS/DSP/Source/CommonTables/CommonTables.c b/CMSIS/DSP/Source/CommonTables/CommonTables.c
new file mode 100644
index 000000000..acda9f88a
--- /dev/null
+++ b/CMSIS/DSP/Source/CommonTables/CommonTables.c
@@ -0,0 +1,31 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: CommonTables.c
+ * Description: Combination of all common table source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_common_tables.c"
+#include "arm_const_structs.c"
+
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c b/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c
new file mode 100644
index 000000000..221053337
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c
@@ -0,0 +1,46 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: CompexMathFunctions.c
+ * Description: Combination of all comlex math function source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_cmplx_conj_f32.c"
+#include "arm_cmplx_conj_q15.c"
+#include "arm_cmplx_conj_q31.c"
+#include "arm_cmplx_dot_prod_f32.c"
+#include "arm_cmplx_dot_prod_q15.c"
+#include "arm_cmplx_dot_prod_q31.c"
+#include "arm_cmplx_mag_f32.c"
+#include "arm_cmplx_mag_q15.c"
+#include "arm_cmplx_mag_q31.c"
+#include "arm_cmplx_mag_squared_f32.c"
+#include "arm_cmplx_mag_squared_q15.c"
+#include "arm_cmplx_mag_squared_q31.c"
+#include "arm_cmplx_mult_cmplx_f32.c"
+#include "arm_cmplx_mult_cmplx_q15.c"
+#include "arm_cmplx_mult_cmplx_q31.c"
+#include "arm_cmplx_mult_real_f32.c"
+#include "arm_cmplx_mult_real_q15.c"
+#include "arm_cmplx_mult_real_q31.c"
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
new file mode 100644
index 000000000..df5db0037
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_conj_f32.c
+ * Description: Floating-point complex conjugate
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @defgroup cmplx_conj Complex Conjugate
+
+ Conjugates the elements of a complex data vector.
+
+ The pSrc points to the source data and
+ pDst points to the destination data where the result should be written.
+ numSamples specifies the number of complex samples
+ and the data in each array is stored in an interleaved fashion
+ (real, imag, real, imag, ...).
+ Each array has a total of 2*numSamples values.
+
+ The underlying algorithm is used:
+
+ for (n = 0; n < numSamples; n++) {
+ pDst[(2*n) ] = pSrc[(2*n) ]; // real part
+ pDst[(2*n)+1] = -pSrc[(2*n)+1]; // imag part
+ }
+
+
+ There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup cmplx_conj
+ @{
+ */
+
+/**
+ @brief Floating-point complex conjugate.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+ */
+
+
+void arm_cmplx_conj_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined(ARM_MATH_NEON)
+ float32x4_t zero;
+ float32x4x2_t vec;
+
+ zero = vdupq_n_f32(0.0);
+
+ /* Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0]+jC[1] = A[0]+(-1)*jA[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ vec = vld2q_f32(pSrc);
+ vec.val[1] = vsubq_f32(zero,vec.val[1]);
+ vst2q_f32(pDst,vec);
+
+ /* Increment pointers */
+ pSrc += 8;
+ pDst += 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = numSamples & 0x3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] + jC[1] = A[0]+ j(-1)A[1] */
+
+ /* Calculate Complex Conjugate and store result in destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined (ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] + jC[1] = A[0]+ j(-1)A[1] */
+
+ /* Calculate Complex Conjugate and store result in destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_conj group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 000000000..073a337c1
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_conj_q15.c
+ * Description: Q15 complex conjugate
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup cmplx_conj
+ @{
+ */
+
+/**
+ @brief Q15 complex conjugate.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ The Q15 value -1 (0x8000) is saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_cmplx_conj_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t in1; /* Temporary input variable */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in2, in3, in4; /* Temporary input variables */
+#endif
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] + jC[1] = A[0]+ j(-1)A[1] */
+
+ /* Calculate Complex Conjugate and store result in destination buffer. */
+
+ #if defined (ARM_MATH_DSP)
+ in1 = read_q15x2_ia ((q15_t **) &pSrc);
+ in2 = read_q15x2_ia ((q15_t **) &pSrc);
+ in3 = read_q15x2_ia ((q15_t **) &pSrc);
+ in4 = read_q15x2_ia ((q15_t **) &pSrc);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ in1 = __QASX(0, in1);
+ in2 = __QASX(0, in2);
+ in3 = __QASX(0, in3);
+ in4 = __QASX(0, in4);
+#else
+ in1 = __QSAX(0, in1);
+ in2 = __QSAX(0, in2);
+ in3 = __QSAX(0, in3);
+ in4 = __QSAX(0, in4);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
+ in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
+ in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
+ in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
+
+ write_q15x2_ia (&pDst, in1);
+ write_q15x2_ia (&pDst, in2);
+ write_q15x2_ia (&pDst, in3);
+ write_q15x2_ia (&pDst, in4);
+#else
+ *pDst++ = *pSrc++;
+ in1 = *pSrc++;
+ *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1;
+
+ *pDst++ = *pSrc++;
+ in1 = *pSrc++;
+ *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1;
+
+ *pDst++ = *pSrc++;
+ in1 = *pSrc++;
+ *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1;
+
+ *pDst++ = *pSrc++;
+ in1 = *pSrc++;
+ *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] + jC[1] = A[0]+ j(-1)A[1] */
+
+ /* Calculate Complex Conjugate and store result in destination buffer. */
+ *pDst++ = *pSrc++;
+ in1 = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __SSAT(-in1, 16);
+#else
+ *pDst++ = (in1 == (q15_t) 0x8000) ? (q15_t) 0x7fff : -in1;
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_conj group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 000000000..6ef1ddb03
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_conj_q31.c
+ * Description: Q31 complex conjugate
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup cmplx_conj
+ @{
+ */
+
+/**
+ @brief Q31 complex conjugate.
+ @param[in] pSrc points to the input vector
+ @param[out] pDst points to the output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ The Q31 value -1 (0x80000000) is saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_cmplx_conj_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t in; /* Temporary input variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] + jC[1] = A[0]+ j(-1)A[1] */
+
+ /* Calculate Complex Conjugate and store result in destination buffer. */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] + jC[1] = A[0]+ j(-1)A[1] */
+
+ /* Calculate Complex Conjugate and store result in destination buffer. */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+#if defined (ARM_MATH_DSP)
+ *pDst++ = __QSUB(0, in);
+#else
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_conj group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 000000000..06f1bfa13
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,233 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_dot_prod_f32.c
+ * Description: Floating-point complex dot product
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @defgroup cmplx_dot_prod Complex Dot Product
+
+ Computes the dot product of two complex vectors.
+ The vectors are multiplied element-by-element and then summed.
+
+ The pSrcA points to the first complex input vector and
+ pSrcB points to the second complex input vector.
+ numSamples specifies the number of complex samples
+ and the data in each array is stored in an interleaved fashion
+ (real, imag, real, imag, ...).
+ Each array has a total of 2*numSamples values.
+
+ The underlying algorithm is used:
+
+
+ realResult = 0;
+ imagResult = 0;
+ for (n = 0; n < numSamples; n++) {
+ realResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+ imagResult += pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+ }
+
+
+ There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup cmplx_dot_prod
+ @{
+ */
+
+/**
+ @brief Floating-point complex dot product.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] numSamples number of samples in each vector
+ @param[out] realResult real part of the result returned here
+ @param[out] imagResult imaginary part of the result returned here
+ @return none
+ */
+
+void arm_cmplx_dot_prod_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result variables */
+ float32_t a0,b0,c0,d0;
+
+#if defined(ARM_MATH_NEON)
+ float32x4x2_t vec1,vec2,vec3,vec4;
+ float32x4_t accR,accI;
+ float32x2_t accum = vdup_n_f32(0);
+
+ accR = vdupq_n_f32(0.0);
+ accI = vdupq_n_f32(0.0);
+
+ /* Loop unrolling: Compute 8 outputs at a time */
+ blkCnt = numSamples >> 3U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0]+jA[1])*(B[0]+jB[1]) + ... */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+
+ vec1 = vld2q_f32(pSrcA);
+ vec2 = vld2q_f32(pSrcB);
+
+ /* Increment pointers */
+ pSrcA += 8;
+ pSrcB += 8;
+
+ /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */
+ accR = vmlaq_f32(accR,vec1.val[0],vec2.val[0]);
+ accR = vmlsq_f32(accR,vec1.val[1],vec2.val[1]);
+
+ /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */
+ accI = vmlaq_f32(accI,vec1.val[1],vec2.val[0]);
+ accI = vmlaq_f32(accI,vec1.val[0],vec2.val[1]);
+
+ vec3 = vld2q_f32(pSrcA);
+ vec4 = vld2q_f32(pSrcB);
+
+ /* Increment pointers */
+ pSrcA += 8;
+ pSrcB += 8;
+
+ /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */
+ accR = vmlaq_f32(accR,vec3.val[0],vec4.val[0]);
+ accR = vmlsq_f32(accR,vec3.val[1],vec4.val[1]);
+
+ /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */
+ accI = vmlaq_f32(accI,vec3.val[1],vec4.val[0]);
+ accI = vmlaq_f32(accI,vec3.val[0],vec4.val[1]);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ accum = vpadd_f32(vget_low_f32(accR), vget_high_f32(accR));
+ real_sum += accum[0] + accum[1];
+
+ accum = vpadd_f32(vget_low_f32(accI), vget_high_f32(accI));
+ imag_sum += accum[0] + accum[1];
+
+ /* Tail */
+ blkCnt = numSamples & 0x7;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += a0 * c0;
+ imag_sum += a0 * d0;
+ real_sum -= b0 * d0;
+ imag_sum += b0 * c0;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store real and imaginary result in destination buffer. */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ @} end of cmplx_dot_prod group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 000000000..2ecd80144
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_dot_prod_q15.c
+ * Description: Processing function for the Q15 Complex Dot product
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup cmplx_dot_prod
+ @{
+ */
+
+/**
+ @brief Q15 complex dot product.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] numSamples number of samples in each vector
+ @param[out] realResult real part of the result returned here
+ @param[out] imagResult imaginary part of the result returned her
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.
+ These are accumulated in a 64-bit accumulator with 34.30 precision.
+ As a final step, the accumulators are converted to 8.24 format.
+ The return results realResult and imagResult are in 8.24 format.
+ */
+
+void arm_cmplx_dot_prod_q15(
+ const q15_t * pSrcA,
+ const q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */
+ q15_t a0,b0,c0,d0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += (q31_t)a0 * c0;
+ imag_sum += (q31_t)a0 * d0;
+ real_sum -= (q31_t)b0 * d0;
+ imag_sum += (q31_t)b0 * c0;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store real and imaginary result in 8.24 format */
+ /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+ *realResult = (q31_t) (real_sum >> 6);
+ /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+ *imagResult = (q31_t) (imag_sum >> 6);
+}
+
+/**
+ @} end of cmplx_dot_prod group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 000000000..d715d98f1
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_dot_prod_q31.c
+ * Description: Q31 complex dot product
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup cmplx_dot_prod
+ @{
+ */
+
+/**
+ @brief Q31 complex dot product.
+ @param[in] pSrcA points to the first input vector
+ @param[in] pSrcB points to the second input vector
+ @param[in] numSamples number of samples in each vector
+ @param[out] realResult real part of the result returned here
+ @param[out] imagResult imaginary part of the result returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
+ The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
+ Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.
+ The return results realResult and imagResult are in 16.48 format.
+ Input down scaling is not required.
+ */
+
+void arm_cmplx_dot_prod_q31(
+ const q31_t * pSrcA,
+ const q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result variables */
+ q31_t a0,b0,c0,d0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ a0 = *pSrcA++;
+ b0 = *pSrcA++;
+ c0 = *pSrcB++;
+ d0 = *pSrcB++;
+
+ real_sum += ((q63_t)a0 * c0) >> 14;
+ imag_sum += ((q63_t)a0 * d0) >> 14;
+ real_sum -= ((q63_t)b0 * d0) >> 14;
+ imag_sum += ((q63_t)b0 * c0) >> 14;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store real and imaginary result in 16.48 format */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ @} end of cmplx_dot_prod group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 000000000..84812dcf3
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_f32.c
+ * Description: Floating-point complex magnitude
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @defgroup cmplx_mag Complex Magnitude
+
+ Computes the magnitude of the elements of a complex data vector.
+
+ The pSrc points to the source data and
+ pDst points to the where the result should be written.
+ numSamples specifies the number of complex samples
+ in the input array and the data is stored in an interleaved fashion
+ (real, imag, real, imag, ...).
+ The input array has a total of 2*numSamples values;
+ the output array has a total of numSamples values.
+
+ The underlying algorithm is used:
+
+
+ for (n = 0; n < numSamples; n++) {
+ pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+ }
+
+
+ There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup cmplx_mag
+ @{
+ */
+
+/**
+ @brief Floating-point complex magnitude.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+ */
+
+void arm_cmplx_mag_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+ float32_t real, imag; /* Temporary variables to hold input values */
+
+#if defined(ARM_MATH_NEON)
+
+ float32x4x2_t vecA;
+ float32x4_t vRealA;
+ float32x4_t vImagA;
+ float32x4_t vMagSqA;
+
+ float32x4x2_t vecB;
+ float32x4_t vRealB;
+ float32x4_t vImagB;
+ float32x4_t vMagSqB;
+
+ /* Loop unrolling: Compute 8 outputs at a time */
+ blkCnt = numSamples >> 3;
+
+ while (blkCnt > 0U)
+ {
+ /* out = sqrt((real * real) + (imag * imag)) */
+
+ vecA = vld2q_f32(pSrc);
+ pSrc += 8;
+
+ vecB = vld2q_f32(pSrc);
+ pSrc += 8;
+
+ vRealA = vmulq_f32(vecA.val[0], vecA.val[0]);
+ vImagA = vmulq_f32(vecA.val[1], vecA.val[1]);
+ vMagSqA = vaddq_f32(vRealA, vImagA);
+
+ vRealB = vmulq_f32(vecB.val[0], vecB.val[0]);
+ vImagB = vmulq_f32(vecB.val[1], vecB.val[1]);
+ vMagSqB = vaddq_f32(vRealB, vImagB);
+
+ /* Store the result in the destination buffer. */
+ vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqA));
+ pDst += 4;
+
+ vst1q_f32(pDst, __arm_vec_sqrt_f32_neon(vMagSqB));
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ blkCnt = numSamples & 7;
+
+#else
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ /* store result in destination buffer. */
+ arm_sqrt_f32((real * real) + (imag * imag), pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ arm_sqrt_f32((real * real) + (imag * imag), pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ arm_sqrt_f32((real * real) + (imag * imag), pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ arm_sqrt_f32((real * real) + (imag * imag), pDst++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ /* store result in destination buffer. */
+ arm_sqrt_f32((real * real) + (imag * imag), pDst++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_mag group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 000000000..a49327448
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_q15.c
+ * Description: Q15 complex magnitude
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup cmplx_mag
+ @{
+ */
+
+/**
+ @brief Q15 complex magnitude.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.
+ */
+
+void arm_cmplx_mag_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_DSP)
+ q31_t in;
+ q31_t acc0; /* Accumulators */
+#else
+ q15_t real, imag; /* Temporary input variables */
+ q31_t acc0, acc1; /* Accumulators */
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+
+#if defined (ARM_MATH_DSP)
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+ /* store result in 2.14 format in destination buffer. */
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+#else
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+
+ /* store result in 2.14 format in destination buffer. */
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+
+#if defined (ARM_MATH_DSP)
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+
+ /* store result in 2.14 format in destination buffer. */
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+#else
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+
+ /* store result in 2.14 format in destination buffer. */
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_mag group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 000000000..873e566cc
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_q31.c
+ * Description: Q31 complex magnitude
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup cmplx_mag
+ @{
+ */
+
+/**
+ @brief Q31 complex magnitude.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.
+ Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t real, imag; /* Temporary input variables */
+ q31_t acc0, acc1; /* Accumulators */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+
+ /* store result in 2.30 format in destination buffer. */
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+
+ /* store result in 2.30 format in destination buffer. */
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_mag group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 000000000..99f051c3f
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,184 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_squared_f32.c
+ * Description: Floating-point complex magnitude squared
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @defgroup cmplx_mag_squared Complex Magnitude Squared
+
+ Computes the magnitude squared of the elements of a complex data vector.
+
+ The pSrc points to the source data and
+ pDst points to the where the result should be written.
+ numSamples specifies the number of complex samples
+ in the input array and the data is stored in an interleaved fashion
+ (real, imag, real, imag, ...).
+ The input array has a total of 2*numSamples values;
+ the output array has a total of numSamples values.
+
+ The underlying algorithm is used:
+
+
+ for (n = 0; n < numSamples; n++) {
+ pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+ }
+
+
+ There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup cmplx_mag_squared
+ @{
+ */
+
+/**
+ @brief Floating-point complex magnitude squared.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+ */
+
+void arm_cmplx_mag_squared_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t real, imag; /* Temporary input variables */
+
+#if defined(ARM_MATH_NEON)
+ float32x4x2_t vecA;
+ float32x4_t vRealA;
+ float32x4_t vImagA;
+ float32x4_t vMagSqA;
+
+ float32x4x2_t vecB;
+ float32x4_t vRealB;
+ float32x4_t vImagB;
+ float32x4_t vMagSqB;
+
+ /* Loop unrolling: Compute 8 outputs at a time */
+ blkCnt = numSamples >> 3;
+
+ while (blkCnt > 0U)
+ {
+ /* out = sqrt((real * real) + (imag * imag)) */
+
+ vecA = vld2q_f32(pSrc);
+ pSrc += 8;
+
+ vRealA = vmulq_f32(vecA.val[0], vecA.val[0]);
+ vImagA = vmulq_f32(vecA.val[1], vecA.val[1]);
+ vMagSqA = vaddq_f32(vRealA, vImagA);
+
+ vecB = vld2q_f32(pSrc);
+ pSrc += 8;
+
+ vRealB = vmulq_f32(vecB.val[0], vecB.val[0]);
+ vImagB = vmulq_f32(vecB.val[1], vecB.val[1]);
+ vMagSqB = vaddq_f32(vRealB, vImagB);
+
+ /* Store the result in the destination buffer. */
+ vst1q_f32(pDst, vMagSqA);
+ pDst += 4;
+
+ vst1q_f32(pDst, vMagSqB);
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ blkCnt = numSamples & 7;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ *pDst++ = (real * real) + (imag * imag);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ *pDst++ = (real * real) + (imag * imag);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ *pDst++ = (real * real) + (imag * imag);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ *pDst++ = (real * real) + (imag * imag);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ /* store result in destination buffer. */
+ *pDst++ = (real * real) + (imag * imag);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_mag_squared group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 000000000..fa5f4e6e1
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_squared_q15.c
+ * Description: Q15 complex magnitude squared
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup cmplx_mag_squared
+ @{
+ */
+
+/**
+ @brief Q15 complex magnitude squared.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mag_squared_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_DSP)
+ q31_t in;
+ q31_t acc0; /* Accumulators */
+#else
+ q15_t real, imag; /* Temporary input variables */
+ q31_t acc0, acc1; /* Accumulators */
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+
+#if defined (ARM_MATH_DSP)
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+ /* store result in 3.13 format in destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+ *pDst++ = (q15_t) (acc0 >> 17);
+
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+ *pDst++ = (q15_t) (acc0 >> 17);
+
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+ *pDst++ = (q15_t) (acc0 >> 17);
+#else
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+ /* store result in 3.13 format in destination buffer. */
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+
+#if defined (ARM_MATH_DSP)
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ acc0 = __SMUAD(in, in);
+
+ /* store result in 3.13 format in destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+#else
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = ((q31_t) real * real);
+ acc1 = ((q31_t) imag * imag);
+
+ /* store result in 3.13 format in destination buffer. */
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_mag_squared group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 000000000..54863efc4
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mag_squared_q31.c
+ * Description: Q31 complex magnitude squared
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup cmplx_mag_squared
+ @{
+ */
+
+/**
+ @brief Q31 complex magnitude squared.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_squared_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t real, imag; /* Temporary input variables */
+ q31_t acc0, acc1; /* Accumulators */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+
+ /* store result in 3.29 format in destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of cmplx_mag_squared group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 000000000..8d1482164
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,194 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_cmplx_f32.c
+ * Description: Floating-point complex-by-complex multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication
+
+ Multiplies a complex vector by another complex vector and generates a complex result.
+ The data in the complex arrays is stored in an interleaved fashion
+ (real, imag, real, imag, ...).
+ The parameter numSamples represents the number of complex
+ samples processed. The complex arrays have a total of 2*numSamples
+ real values.
+
+ The underlying algorithm is used:
+
+
+ for (n = 0; n < numSamples; n++) {
+ pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+ pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+ }
+
+
+ There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup CmplxByCmplxMult
+ @{
+ */
+
+/**
+ @brief Floating-point complex-by-complex multiplication.
+ @param[in] pSrcA points to first input vector
+ @param[in] pSrcB points to second input vector
+ @param[out] pDst points to output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+ const float32_t * pSrcA,
+ const float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+
+#if defined(ARM_MATH_NEON)
+ float32x4x2_t va, vb;
+ float32x4_t real, imag;
+ float32x4x2_t outCplx;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ va = vld2q_f32(pSrcA); // load & separate real/imag pSrcA (de-interleave 2)
+ vb = vld2q_f32(pSrcB); // load & separate real/imag pSrcB
+
+ /* Increment pointers */
+ pSrcA += 8;
+ pSrcB += 8;
+
+ /* Re{C} = Re{A}*Re{B} - Im{A}*Im{B} */
+ outCplx.val[0] = vmulq_f32(va.val[0], vb.val[0]);
+ outCplx.val[0] = vmlsq_f32(outCplx.val[0], va.val[1], vb.val[1]);
+
+ /* Im{C} = Re{A}*Im{B} + Im{A}*Re{B} */
+ outCplx.val[1] = vmulq_f32(va.val[0], vb.val[1]);
+ outCplx.val[1] = vmlaq_f32(outCplx.val[1], va.val[1], vb.val[0]);
+
+ vst2q_f32(pDst, outCplx);
+
+ /* Increment pointer */
+ pDst += 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = numSamples & 3;
+
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+ /* store result in destination buffer. */
+ *pDst++ = (a * c) - (b * d);
+ *pDst++ = (a * d) + (b * c);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+ *pDst++ = (a * c) - (b * d);
+ *pDst++ = (a * d) + (b * c);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+ *pDst++ = (a * c) - (b * d);
+ *pDst++ = (a * d) + (b * c);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+ *pDst++ = (a * c) - (b * d);
+ *pDst++ = (a * d) + (b * c);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i ] = A[2 * i] * B[2 * i ] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i ]. */
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store result in destination buffer. */
+ *pDst++ = (a * c) - (b * d);
+ *pDst++ = (a * d) + (b * c);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of CmplxByCmplxMult group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 000000000..9651999e3
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_real_f32.c
+ * Description: Floating-point complex by real multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @defgroup CmplxByRealMult Complex-by-Real Multiplication
+
+ Multiplies a complex vector by a real vector and generates a complex result.
+ The data in the complex arrays is stored in an interleaved fashion
+ (real, imag, real, imag, ...).
+ The parameter numSamples represents the number of complex
+ samples processed. The complex arrays have a total of 2*numSamples
+ real values while the real array has a total of numSamples
+ real values.
+
+ The underlying algorithm is used:
+
+
+ for (n = 0; n < numSamples; n++) {
+ pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+ pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+ }
+
+
+ There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ @addtogroup CmplxByRealMult
+ @{
+ */
+
+/**
+ @brief Floating-point complex-by-real multiplication.
+ @param[in] pSrcCmplx points to complex input vector
+ @param[in] pSrcReal points to real input vector
+ @param[out] pCmplxDst points to complex output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+ */
+
+void arm_cmplx_mult_real_f32(
+ const float32_t * pSrcCmplx,
+ const float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t in; /* Temporary variable */
+
+#if defined(ARM_MATH_NEON)
+ float32x4_t r;
+ float32x4x2_t ab,outCplx;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ ab = vld2q_f32(pSrcCmplx); // load & separate real/imag pSrcA (de-interleave 2)
+ r = vld1q_f32(pSrcReal); // load & separate real/imag pSrcB
+
+ /* Increment pointers */
+ pSrcCmplx += 8;
+ pSrcReal += 4;
+
+ outCplx.val[0] = vmulq_f32(ab.val[0], r);
+ outCplx.val[1] = vmulq_f32(ab.val[1], r);
+
+ vst2q_f32(pCmplxDst, outCplx);
+ pCmplxDst += 8;
+
+ blkCnt--;
+ }
+
+ /* Tail */
+ blkCnt = numSamples & 3;
+#else
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i ] = A[2 * i ] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+
+ in = *pSrcReal++;
+ /* store result in destination buffer. */
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+
+ in = *pSrcReal++;
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+
+ in = *pSrcReal++;
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+
+ in = *pSrcReal++;
+ *pCmplxDst++ = *pSrcCmplx++* in;
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+#endif /* #if defined(ARM_MATH_NEON) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i ] = A[2 * i ] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+
+ in = *pSrcReal++;
+ /* store result in destination buffer. */
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+ *pCmplxDst++ = *pSrcCmplx++ * in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of CmplxByRealMult group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 000000000..4877d208f
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,182 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_real_q15.c
+ * Description: Q15 complex by real multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup CmplxByRealMult
+ @{
+ */
+
+/**
+ @brief Q15 complex-by-real multiplication.
+ @param[in] pSrcCmplx points to complex input vector
+ @param[in] pSrcReal points to real input vector
+ @param[out] pCmplxDst points to complex output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+ */
+
+void arm_cmplx_mult_real_q15(
+ const q15_t * pSrcCmplx,
+ const q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q15_t in; /* Temporary variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+#if defined (ARM_MATH_DSP)
+ q31_t inA1, inA2; /* Temporary variables to hold input data */
+ q31_t inB1; /* Temporary variables to hold input data */
+ q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */
+#endif
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i ] = A[2 * i ] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+
+#if defined (ARM_MATH_DSP)
+ /* read 2 complex numbers both real and imaginary from complex input buffer */
+ inA1 = read_q15x2_ia ((q15_t **) &pSrcCmplx);
+ inA2 = read_q15x2_ia ((q15_t **) &pSrcCmplx);
+ /* read 2 real values at a time from real input buffer */
+ inB1 = read_q15x2_ia ((q15_t **) &pSrcReal);
+
+ /* multiply complex number with real numbers */
+#ifndef ARM_MATH_BIG_ENDIAN
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+#else
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* saturate the result */
+ out1 = (q15_t) __SSAT(mul1 >> 15U, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15U, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15U, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15U, 16);
+
+ /* pack real and imaginary outputs and store them to destination */
+ write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16));
+ write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16));
+
+ inA1 = read_q15x2_ia ((q15_t **) &pSrcCmplx);
+ inA2 = read_q15x2_ia ((q15_t **) &pSrcCmplx);
+ inB1 = read_q15x2_ia ((q15_t **) &pSrcReal);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+#else
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ out1 = (q15_t) __SSAT(mul1 >> 15U, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15U, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15U, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15U, 16);
+
+ write_q15x2_ia (&pCmplxDst, __PKHBT(out1, out2, 16));
+ write_q15x2_ia (&pCmplxDst, __PKHBT(out3, out4, 16));
+#else
+ in = *pSrcReal++;
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+
+ in = *pSrcReal++;
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+
+ in = *pSrcReal++;
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+
+ in = *pSrcReal++;
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i ] = A[2 * i ] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+ *pCmplxDst++ = (q15_t) __SSAT((((q31_t) *pSrcCmplx++ * in) >> 15), 16);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of CmplxByRealMult group
+ */
diff --git a/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 000000000..906410f36
--- /dev/null
+++ b/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mult_real_q31.c
+ * Description: Q31 complex by real multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupCmplxMath
+ */
+
+/**
+ @addtogroup CmplxByRealMult
+ @{
+ */
+
+/**
+ @brief Q31 complex-by-real multiplication.
+ @param[in] pSrcCmplx points to complex input vector
+ @param[in] pSrcReal points to real input vector
+ @param[out] pCmplxDst points to complex output vector
+ @param[in] numSamples number of samples in each vector
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated.
+ */
+
+void arm_cmplx_mult_real_q31(
+ const q31_t * pSrcCmplx,
+ const q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t in; /* Temporary variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = numSamples >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i ] = A[2 * i ] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+
+ in = *pSrcReal++;
+#if defined (ARM_MATH_DSP)
+ /* store saturated result in 1.31 format to destination buffer */
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+#else
+ /* store result in destination buffer. */
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+#endif
+
+ in = *pSrcReal++;
+#if defined (ARM_MATH_DSP)
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+#else
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+#endif
+
+ in = *pSrcReal++;
+#if defined (ARM_MATH_DSP)
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+#else
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+#endif
+
+ in = *pSrcReal++;
+#if defined (ARM_MATH_DSP)
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+#else
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numSamples % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C[2 * i ] = A[2 * i ] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+
+ in = *pSrcReal++;
+#if defined (ARM_MATH_DSP)
+ /* store saturated result in 1.31 format to destination buffer */
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+ *pCmplxDst++ = (__SSAT((q31_t) (((q63_t) *pSrcCmplx++ * in) >> 32), 31) << 1);
+#else
+ /* store result in destination buffer. */
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+ *pCmplxDst++ = (q31_t) clip_q63_to_q31(((q63_t) *pSrcCmplx++ * in) >> 31);
+#endif
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of CmplxByRealMult group
+ */
diff --git a/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c b/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c
new file mode 100644
index 000000000..51720bcc1
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c
@@ -0,0 +1,37 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: ControllerFunctions.c
+ * Description: Combination of all controller function source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_pid_init_f32.c"
+#include "arm_pid_init_q15.c"
+#include "arm_pid_init_q31.c"
+#include "arm_pid_reset_f32.c"
+#include "arm_pid_reset_q15.c"
+#include "arm_pid_reset_q31.c"
+#include "arm_sin_cos_f32.c"
+#include "arm_sin_cos_q31.c"
+
diff --git a/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 000000000..433a65a2b
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,75 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_init_f32.c
+ * Description: Floating-point PID Control initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @addtogroup PID
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point PID Control.
+ @param[in,out] S points to an instance of the PID structure
+ @param[in] resetStateFlag
+ - value = 0: no change in state
+ - value = 1: reset state
+ @return none
+
+ @par Details
+ The resetStateFlag specifies whether to set state to zero or not. \n
+ The function computes the structure fields: A0, A1 A2
+ using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag)
+{
+ /* Derived coefficient A0 */
+ S->A0 = S->Kp + S->Ki + S->Kd;
+
+ /* Derived coefficient A1 */
+ S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if (resetStateFlag)
+ {
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(float32_t));
+ }
+
+}
+
+/**
+ @} end of PID group
+ */
diff --git a/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 000000000..c88a3d909
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_init_q15.c
+ * Description: Q15 PID Control initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @addtogroup PID
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q15 PID Control.
+ @param[in,out] S points to an instance of the Q15 PID structure
+ @param[in] resetStateFlag
+ - value = 0: no change in state
+ - value = 1: reset state
+ @return none
+
+ @par Details
+ The resetStateFlag specifies whether to set state to zero or not. \n
+ The function computes the structure fields: A0, A1 A2
+ using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag)
+{
+
+#if defined (ARM_MATH_DSP)
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficients and pack into A1 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+#else
+ S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+#endif
+
+#else
+
+ q31_t temp; /* to store the sum */
+
+ /* Derived coefficient A0 */
+ temp = S->Kp + S->Ki + S->Kd;
+ S->A0 = (q15_t) __SSAT(temp, 16);
+
+ /* Derived coefficients and pack into A1 */
+ temp = -(S->Kd + S->Kd + S->Kp);
+ S->A1 = (q15_t) __SSAT(temp, 16);
+ S->A2 = S->Kd;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Check whether state needs reset or not */
+ if (resetStateFlag)
+ {
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q15_t));
+ }
+
+}
+
+/**
+ @} end of PID group
+ */
diff --git a/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 000000000..1625a5f2f
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_init_q31.c
+ * Description: Q31 PID Control initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @addtogroup PID
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q31 PID Control.
+ @param[in,out] S points to an instance of the Q31 PID structure
+ @param[in] resetStateFlag
+ - value = 0: no change in state
+ - value = 1: reset state
+ @return none
+
+ @par Details
+ The resetStateFlag specifies whether to set state to zero or not. \n
+ The function computes the structure fields: A0, A1 A2
+ using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag)
+{
+
+#if defined (ARM_MATH_DSP)
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficient A1 */
+ S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+#else
+
+ q31_t temp; /* to store the sum */
+
+ /* Derived coefficient A0 */
+ temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+ S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+ /* Derived coefficient A1 */
+ temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+ S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if (resetStateFlag)
+ {
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q31_t));
+ }
+
+}
+
+/**
+ @} end of PID group
+ */
diff --git a/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 000000000..d839e55ea
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_reset_f32.c
+ * Description: Floating-point PID Control reset function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @addtogroup PID
+ @{
+ */
+
+/**
+ @brief Reset function for the floating-point PID Control.
+ @param[in,out] S points to an instance of the floating-point PID structure
+ @return none
+
+ @par Details
+ The function resets the state buffer to zeros.
+ */
+
+void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S)
+{
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(float32_t));
+}
+
+/**
+ @} end of PID group
+ */
diff --git a/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 000000000..256fd8cae
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_reset_q15.c
+ * Description: Q15 PID Control reset function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @addtogroup PID
+ @{
+ */
+
+/**
+ @brief Reset function for the Q15 PID Control.
+ @param[in,out] S points to an instance of the Q15 PID structure
+ @return none
+
+ @par Details
+ The function resets the state buffer to zeros.
+ */
+
+void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S)
+{
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q15_t));
+}
+
+/**
+ @} end of PID group
+ */
diff --git a/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 000000000..2aa391c04
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_pid_reset_q31.c
+ * Description: Q31 PID Control reset function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @addtogroup PID
+ @{
+ */
+
+/**
+ @brief Reset function for the Q31 PID Control.
+ @param[in,out] S points to an instance of the Q31 PID structure
+ @return none
+
+ @par Details
+ The function resets the state buffer to zeros.
+ */
+
+void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S)
+{
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3U * sizeof(q31_t));
+}
+
+/**
+ @} end of PID group
+ */
diff --git a/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c b/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 000000000..12a1c83b1
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sin_cos_f32.c
+ * Description: Sine and Cosine calculation for floating-point values
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ @ingroup groupController
+ */
+
+/**
+ @defgroup SinCos Sine Cosine
+
+ Computes the trigonometric sine and cosine values using a combination of table lookup
+ and linear interpolation.
+ There are separate functions for Q31 and floating-point data types.
+ The input to the floating-point version is in degrees while the
+ fixed-point Q31 have a scaled input with the range
+ [-1 0.9999] mapping to [-180 +180] degrees.
+
+ The floating point function also allows values that are out of the usual range. When this happens, the function will
+ take extra time to adjust the input value to the range of [-180 180].
+
+ The result is accurate to 5 digits after the decimal point.
+
+ The implementation is based on table lookup using 360 values together with linear interpolation.
+ The steps used are:
+ -# Calculation of the nearest integer table index.
+ -# Compute the fractional portion (fract) of the input.
+ -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.
+ -# Sine value is computed as *psinVal = y0 + (fract * (y1 - y0)).
+ -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.
+ -# Cosine value is computed as *pcosVal = y0 + (fract * (y1 - y0)).
+ */
+
+/**
+ @addtogroup SinCos
+ @{
+ */
+
+/**
+ @brief Floating-point sin_cos function.
+ @param[in] theta input value in degrees
+ @param[out] pSinVal points to processed sine output
+ @param[out] pCosVal points to processed cosine output
+ @return none
+ */
+
+void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal)
+{
+ float32_t fract, in; /* Temporary input, output variables */
+ uint16_t indexS, indexC; /* Index variable */
+ float32_t f1, f2, d1, d2; /* Two nearest output values */
+ float32_t Dn, Df;
+ float32_t temp, findex;
+
+ /* input x is in degrees */
+ /* Scale input, divide input by 360, for cosine add 0.25 (pi/2) to read sine table */
+ in = theta * 0.00277777777778f;
+
+ if (in < 0.0f)
+ {
+ in = -in;
+ }
+
+ in = in - (int32_t)in;
+
+ /* Calculate the nearest index */
+ findex = (float32_t)FAST_MATH_TABLE_SIZE * in;
+ indexS = ((uint16_t)findex) & 0x1ff;
+ indexC = (indexS + (FAST_MATH_TABLE_SIZE / 4)) & 0x1ff;
+
+ /* Calculation of fractional value */
+ fract = findex - (float32_t) indexS;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_f32[indexC ];
+ f2 = sinTable_f32[indexC+1];
+ d1 = -sinTable_f32[indexS ];
+ d2 = -sinTable_f32[indexS+1];
+
+ temp = (1.0f - fract) * f1 + fract * f2;
+
+ Dn = 0.0122718463030f; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */
+ Df = f2 - f1; /* delta between the values of the functions */
+
+ temp = Dn * (d1 + d2) - 2 * Df;
+ temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn);
+ temp = fract * temp + d1 * Dn;
+
+ /* Calculation of cosine value */
+ *pCosVal = fract * temp + f1;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_f32[indexS ];
+ f2 = sinTable_f32[indexS+1];
+ d1 = sinTable_f32[indexC ];
+ d2 = sinTable_f32[indexC+1];
+
+ temp = (1.0f - fract) * f1 + fract * f2;
+
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn * (d1 + d2) - 2 * Df;
+ temp = fract * temp + (3 * Df - (d2 + 2 * d1) * Dn);
+ temp = fract * temp + d1 * Dn;
+
+ /* Calculation of sine value */
+ *pSinVal = fract * temp + f1;
+
+ if (theta < 0.0f)
+ {
+ *pSinVal = -*pSinVal;
+ }
+}
+
+/**
+ @} end of SinCos group
+ */
diff --git a/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c b/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 000000000..84ee3d2ca
--- /dev/null
+++ b/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_sin_cos_q31.c
+ * Description: Cosine & Sine calculation for Q31 values
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ @ingroup groupController
+ */
+
+/**
+ @addtogroup SinCos
+ @{
+ */
+
+/**
+ @brief Q31 sin_cos function.
+ @param[in] theta scaled input value in degrees
+ @param[out] pSinVal points to processed sine output
+ @param[out] pCosVal points to processed cosine output
+ @return none
+
+ The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].
+ */
+
+void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal)
+{
+ q31_t fract; /* Temporary input, output variables */
+ uint16_t indexS, indexC; /* Index variable */
+ q31_t f1, f2, d1, d2; /* Two nearest output values */
+ q31_t Dn, Df;
+ q63_t temp;
+
+ /* Calculate the nearest index */
+ indexS = (uint32_t)theta >> CONTROLLER_Q31_SHIFT;
+ indexC = (indexS + 128) & 0x1ff;
+
+ /* Calculation of fractional value */
+ fract = (theta - (indexS << CONTROLLER_Q31_SHIFT)) << 8;
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_q31[indexC ];
+ f2 = sinTable_q31[indexC+1];
+ d1 = -sinTable_q31[indexS ];
+ d2 = -sinTable_q31[indexS+1];
+
+ Dn = 0x1921FB5; /* delta between the two points (fixed), in this case 2*pi/FAST_MATH_TABLE_SIZE */
+ Df = f2 - f1; /* delta between the values of the functions */
+
+ temp = Dn * ((q63_t)d1 + d2);
+ temp = temp - ((q63_t)Df << 32);
+ temp = (q63_t)fract * (temp >> 31);
+ temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn);
+ temp = (q63_t)fract * (temp >> 31);
+ temp = temp + (q63_t)d1 * Dn;
+ temp = (q63_t)fract * (temp >> 31);
+
+ /* Calculation of cosine value */
+ *pCosVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+
+ /* Read two nearest values of input value from the cos & sin tables */
+ f1 = sinTable_q31[indexS ];
+ f2 = sinTable_q31[indexS+1];
+ d1 = sinTable_q31[indexC ];
+ d2 = sinTable_q31[indexC+1];
+
+ Df = f2 - f1; // delta between the values of the functions
+ temp = Dn * ((q63_t)d1 + d2);
+ temp = temp - ((q63_t)Df << 32);
+ temp = (q63_t)fract * (temp >> 31);
+ temp = temp + ((3 * (q63_t)Df << 31) - (d2 + ((q63_t)d1 << 1)) * Dn);
+ temp = (q63_t)fract * (temp >> 31);
+ temp = temp + (q63_t)d1 * Dn;
+ temp = (q63_t)fract * (temp >> 31);
+
+ /* Calculation of sine value */
+ *pSinVal = clip_q63_to_q31((temp >> 31) + (q63_t)f1);
+}
+
+/**
+ @} end of SinCos group
+ */
diff --git a/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c b/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c
new file mode 100644
index 000000000..abd919e0a
--- /dev/null
+++ b/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c
@@ -0,0 +1,37 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: FastMathFunctions.c
+ * Description: Combination of all fast math function source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_cos_f32.c"
+#include "arm_cos_q15.c"
+#include "arm_cos_q31.c"
+#include "arm_sin_f32.c"
+#include "arm_sin_q15.c"
+#include "arm_sin_q31.c"
+#include "arm_sqrt_q15.c"
+#include "arm_sqrt_q31.c"
+
diff --git a/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c b/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c
new file mode 100644
index 000000000..7ce0cdbb7
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: FilteringFunctions.c
+ * Description: Combination of all filtering function source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_biquad_cascade_df1_32x64_init_q31.c"
+#include "arm_biquad_cascade_df1_32x64_q31.c"
+#include "arm_biquad_cascade_df1_f32.c"
+#include "arm_biquad_cascade_df1_fast_q15.c"
+#include "arm_biquad_cascade_df1_fast_q31.c"
+#include "arm_biquad_cascade_df1_init_f32.c"
+#include "arm_biquad_cascade_df1_init_q15.c"
+#include "arm_biquad_cascade_df1_init_q31.c"
+#include "arm_biquad_cascade_df1_q15.c"
+#include "arm_biquad_cascade_df1_q31.c"
+#include "arm_biquad_cascade_df2T_f32.c"
+#include "arm_biquad_cascade_df2T_f64.c"
+#include "arm_biquad_cascade_df2T_init_f32.c"
+#include "arm_biquad_cascade_df2T_init_f64.c"
+#include "arm_biquad_cascade_stereo_df2T_f32.c"
+#include "arm_biquad_cascade_stereo_df2T_init_f32.c"
+#include "arm_conv_f32.c"
+#include "arm_conv_fast_opt_q15.c"
+#include "arm_conv_fast_q15.c"
+#include "arm_conv_fast_q31.c"
+#include "arm_conv_opt_q15.c"
+#include "arm_conv_opt_q7.c"
+#include "arm_conv_partial_f32.c"
+#include "arm_conv_partial_fast_opt_q15.c"
+#include "arm_conv_partial_fast_q15.c"
+#include "arm_conv_partial_fast_q31.c"
+#include "arm_conv_partial_opt_q15.c"
+#include "arm_conv_partial_opt_q7.c"
+#include "arm_conv_partial_q15.c"
+#include "arm_conv_partial_q31.c"
+#include "arm_conv_partial_q7.c"
+#include "arm_conv_q15.c"
+#include "arm_conv_q31.c"
+#include "arm_conv_q7.c"
+#include "arm_correlate_f32.c"
+#include "arm_correlate_fast_opt_q15.c"
+#include "arm_correlate_fast_q15.c"
+#include "arm_correlate_fast_q31.c"
+#include "arm_correlate_opt_q15.c"
+#include "arm_correlate_opt_q7.c"
+#include "arm_correlate_q15.c"
+#include "arm_correlate_q31.c"
+#include "arm_correlate_q7.c"
+#include "arm_fir_decimate_f32.c"
+#include "arm_fir_decimate_fast_q15.c"
+#include "arm_fir_decimate_fast_q31.c"
+#include "arm_fir_decimate_init_f32.c"
+#include "arm_fir_decimate_init_q15.c"
+#include "arm_fir_decimate_init_q31.c"
+#include "arm_fir_decimate_q15.c"
+#include "arm_fir_decimate_q31.c"
+#include "arm_fir_f32.c"
+#include "arm_fir_fast_q15.c"
+#include "arm_fir_fast_q31.c"
+#include "arm_fir_init_f32.c"
+#include "arm_fir_init_q15.c"
+#include "arm_fir_init_q31.c"
+#include "arm_fir_init_q7.c"
+#include "arm_fir_interpolate_f32.c"
+#include "arm_fir_interpolate_init_f32.c"
+#include "arm_fir_interpolate_init_q15.c"
+#include "arm_fir_interpolate_init_q31.c"
+#include "arm_fir_interpolate_q15.c"
+#include "arm_fir_interpolate_q31.c"
+#include "arm_fir_lattice_f32.c"
+#include "arm_fir_lattice_init_f32.c"
+#include "arm_fir_lattice_init_q15.c"
+#include "arm_fir_lattice_init_q31.c"
+#include "arm_fir_lattice_q15.c"
+#include "arm_fir_lattice_q31.c"
+#include "arm_fir_q15.c"
+#include "arm_fir_q31.c"
+#include "arm_fir_q7.c"
+#include "arm_fir_sparse_f32.c"
+#include "arm_fir_sparse_init_f32.c"
+#include "arm_fir_sparse_init_q15.c"
+#include "arm_fir_sparse_init_q31.c"
+#include "arm_fir_sparse_init_q7.c"
+#include "arm_fir_sparse_q15.c"
+#include "arm_fir_sparse_q31.c"
+#include "arm_fir_sparse_q7.c"
+#include "arm_iir_lattice_f32.c"
+#include "arm_iir_lattice_init_f32.c"
+#include "arm_iir_lattice_init_q15.c"
+#include "arm_iir_lattice_init_q31.c"
+#include "arm_iir_lattice_q15.c"
+#include "arm_iir_lattice_q31.c"
+#include "arm_lms_f32.c"
+#include "arm_lms_init_f32.c"
+#include "arm_lms_init_q15.c"
+#include "arm_lms_init_q31.c"
+#include "arm_lms_norm_f32.c"
+#include "arm_lms_norm_init_f32.c"
+#include "arm_lms_norm_init_q15.c"
+#include "arm_lms_norm_init_q31.c"
+#include "arm_lms_norm_q15.c"
+#include "arm_lms_norm_q31.c"
+#include "arm_lms_q15.c"
+#include "arm_lms_q31.c"
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 000000000..ac2313fbb
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_32x64_init_q31.c
+ * Description: High precision Q31 Biquad cascade filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1_32x64
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q31 Biquad cascade 32x64 filter.
+ @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure
+ @param[in] numStages number of 2nd order stages in the filter
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format
+ @return none
+
+ @par Coefficient and State Ordering
+ The coefficients are stored in the array pCoeffs in the following order:
+
+ {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ where b1x and a1x are the coefficients for the first stage,
+ b2x and a2x are the coefficients for the second stage,
+ and so on. The pCoeffs array contains a total of 5*numStages values.
+ @par
+ The pState points to state variables array and size of each state variable is 1.63 format.
+ Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ The state variables are arranged in the state array as:
+
+ {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ The state array has a total length of 4*numStages values.
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q63_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 000000000..9a284b8a9
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,458 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_32x64_q31.c
+ * Description: High precision Q31 Biquad cascade filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter
+
+ This function implements a high precision Biquad cascade filter which operates on
+ Q31 data values. The filter coefficients are in 1.31 format and the state variables
+ are in 1.63 format. The double precision state variables reduce quantization noise
+ in the filter and provide a cleaner output.
+ These filters are particularly useful when implementing filters in which the
+ singularities are close to the unit circle. This is common for low pass or high
+ pass filters with very low cutoff frequencies.
+
+ The function operates on blocks of input and output data
+ and each call to the function processes blockSize samples through
+ the filter. pSrc and pDst points to input and output arrays
+ containing blockSize Q31 values.
+
+ @par Algorithm
+ Each Biquad stage implements a second order filter using the difference equation:
+
+ y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ \image html Biquad.gif "Single Biquad filter stage"
+ Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
+ Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+ Pay careful attention to the sign of the feedback coefficients.
+ Some design tools use the difference equation
+
+ y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+ @par
+ Higher order filters are realized as a cascade of second order sections.
+ numStages refers to the number of second order stages used.
+ For example, an 8th order filter would be realized with numStages=4 second order stages.
+ \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ A 9th order filter would be realized with numStages=5 second order stages
+ with the coefficients for one of the stages configured as a first order filter
+ (b2=0 and a2=0).
+ @par
+ The pState points to state variables array.
+ Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.
+ The state variables are arranged in the array as:
+
+ {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ @par
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ The state array has a total length of 4*numStages values of data in 1.63 format.
+ The state variables are updated after each block of data is processed, the coefficients are untouched.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter.
+ Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+
+ @par Init Function
+ There is also an associated initialization function which performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
+
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ Set the values in the state buffer to zeros before static initialization.
+ For example, to statically initialize the filter instance structure use
+
+ arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter;
+ pState is the address of the state buffer;
+ pCoeffs is the address of the coefficient buffer;
+ postShift shift to be applied which is described in detail below.
+ @par Fixed-Point Behavior
+ Care must be taken while using Biquad Cascade 32x64 filter function.
+ Following issues must be considered:
+ - Scaling of coefficients
+ - Filter gain
+ - Overflow and saturation
+
+ @par
+ Filter coefficients are represented as fractional values and
+ restricted to lie in the range [-1 +1).
+ The processing function has an additional scaling parameter postShift
+ which allows the filter coefficients to exceed the range [+1 -1).
+ At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ This essentially scales the filter coefficients by 2^postShift.
+ For example, to realize the coefficients
+
+ {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the Coefficient array to:
+
+ {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1
+ @par
+ The second thing to keep in mind is the gain through the filter.
+ The frequency response of a Biquad filter is a function of its coefficients.
+ It is possible for the gain through the filter to exceed 1.0 meaning that the
+ filter increases the amplitude of certain frequencies.
+ This means that an input signal with amplitude < 1.0 may result in an output > 1.0
+ and these are saturated or overflowed based on the implementation of the filter.
+ To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0
+ or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ @par
+ The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.
+ This is described in the function specific documentation below.
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1_32x64
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 Biquad cascade 32x64 filter.
+ @param[in] S points to an instance of the high precision Q31 Biquad cascade filter
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Details
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to
+ 1.31 format by discarding the low 32 bits.
+ @par
+ Two related functions are provided in the CMSIS DSP library.
+ - \ref arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.
+ - \ref arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q63_t *pState = S->pState; /* state pointer initialization */
+ const q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q63_t acc; /* accumulator */
+ q31_t Xn1, Xn2; /* Input Filter state variables */
+ q63_t Yn1, Yn2; /* Output Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+ q31_t acc_l, acc_h; /* temporary output */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = (q31_t) (pState[0]);
+ Xn2 = (q31_t) (pState[1]);
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* Variable acc hold output value that is being computed and stored in destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ sample = blockSize >> 2U;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn * b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 * b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 * b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut = acc_h;
+
+ /* Read the second input into Xn2, to reuse the value */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc += b1 * x[n-1] */
+ acc = (q63_t) Xn * b1;
+
+ /* acc = b0 * x[n] */
+ acc += (q63_t) Xn2 * b0;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn1 * b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Read the third input into Xn1, to reuse the value */
+ Xn1 = *pIn++;
+
+ /* The result is converted to 1.31 */
+ /* Store the output in the destination buffer. */
+ *(pOut + 1U) = acc_h;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn1 * b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn2 * b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn * b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 2U) = acc_h;
+
+ /* Read the fourth input into Xn, to reuse the value */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn * b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 * b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 * b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 3U) = acc_h;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* update output pointer */
+ pOut += 4U;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ sample = blockSize & 0x3U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ sample = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn * b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 * b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 * b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+ /* Yn1 = acc << shift; */
+
+ /* Store the output in the destination buffer in 1.31 format. */
+/* *pOut++ = (q31_t) (acc >> (32 - shift)); */
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+
+}
+
+/**
+ @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 000000000..d28509d4c
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,495 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_f32.c
+ * Description: Processing function for the floating-point Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure
+
+ This set of functions implements arbitrary order recursive (IIR) filters.
+ The filters are implemented as a cascade of second order Biquad sections.
+ The functions support Q15, Q31 and floating-point data types.
+ Fast version of Q15 and Q31 also available.
+
+ The functions operate on blocks of input and output data and each call to the function
+ processes blockSize samples through the filter.
+ pSrc points to the array of input data and
+ pDst points to the array of output data.
+ Both arrays contain blockSize values.
+
+ @par Algorithm
+ Each Biquad stage implements a second order filter using the difference equation:
+
+ y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+
+ A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ \image html Biquad.gif "Single Biquad filter stage"
+ Coefficients b0, b1 and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
+ Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+ Pay careful attention to the sign of the feedback coefficients.
+ Some design tools use the difference equation
+
+ y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+
+ In this case the feedback coefficients a1 and a2
+ must be negated when used with the CMSIS DSP Library.
+
+ @par
+ Higher order filters are realized as a cascade of second order sections.
+ numStages refers to the number of second order stages used.
+ For example, an 8th order filter would be realized with numStages=4 second order stages.
+ \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+
+ @par
+ The pState points to state variables array.
+ Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ The state variables are arranged in the pState array as:
+
+ {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+
+ @par
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ The state array has a total length of 4*numStages values.
+ The state variables are updated after each block of data is processed, the coefficients are untouched.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter.
+ Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ There are separate instance structure declarations for each of the 3 supported data types.
+
+ @par Init Function
+ There is also an associated initialization function for each data type.
+ The initialization function performs following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ Set the values in the state buffer to zeros before static initialization.
+ The code below statically initializes each of the 3 different data type filter instance structures
+
+ arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+ arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+ arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+
+ where numStages is the number of Biquad stages in the filter;
+ pState is the address of the state buffer;
+ pCoeffs is the address of the coefficient buffer;
+ postShift shift to be applied.
+
+ @par Fixed-Point Behavior
+ Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.
+ Following issues must be considered:
+ - Scaling of coefficients
+ - Filter gain
+ - Overflow and saturation
+
+ @par Scaling of coefficients
+ Filter coefficients are represented as fractional values and
+ coefficients are restricted to lie in the range [-1 +1).
+ The fixed-point functions have an additional scaling parameter postShift
+ which allow the filter coefficients to exceed the range [+1 -1).
+ At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ This essentially scales the filter coefficients by 2^postShift.
+ For example, to realize the coefficients
+
+ {1.5, -0.8, 1.2, 1.6, -0.9}
+
+ set the pCoeffs array to:
+
+ {0.75, -0.4, 0.6, 0.8, -0.45}
+
+ and set postShift=1
+
+ @par Filter gain
+ The frequency response of a Biquad filter is a function of its coefficients.
+ It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+
+ @par Overflow and saturation
+ For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point Biquad cascade filter.
+ @param[in] S points to an instance of the floating-point Biquad cascade structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+#if defined(ARM_MATH_NEON)
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+
+ const float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* pState pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc; /* Simulates the accumulator */
+
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+ float32x4_t Xn;
+ float32x2_t Yn;
+ float32x2_t a;
+ float32x4_t b;
+
+ float32x4_t x,tmp;
+ float32x2_t t;
+ float32x2x2_t y;
+
+ float32_t Xns;
+
+ while (stage > 0U)
+ {
+ /* Reading the coefficients */
+ Xn = vld1q_f32(pState);
+ Yn = vld1_f32(pState + 2);
+
+ b = vld1q_f32(pCoeffs);
+ b = vrev64q_f32(b);
+ b = vcombine_f32(vget_high_f32(b), vget_low_f32(b));
+
+ a = vld1_f32(pCoeffs + 3);
+ a = vrev64_f32(a);
+ b[0] = 0.0;
+ pCoeffs += 5;
+
+ /* Reading the pState values */
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ sample = blockSize >> 2U;
+
+ while (sample > 0U)
+ {
+ /* Read the first 4 inputs */
+ x = vld1q_f32(pIn);
+
+ pIn += 4;
+
+ tmp = vextq_f32(Xn, x, 1);
+ t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp));
+ t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp));
+ t = vmla_f32(t, a, Yn);
+ t = vpadd_f32(t, t);
+ Yn = vext_f32(Yn, t, 1);
+
+ tmp = vextq_f32(Xn, x, 2);
+ t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp));
+ t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp));
+ t = vmla_f32(t, a, Yn);
+ t = vpadd_f32(t, t);
+ Yn = vext_f32(Yn, t, 1);
+
+ y.val[0] = Yn;
+
+ tmp = vextq_f32(Xn, x, 3);
+ t = vmul_f32(vget_high_f32(b), vget_high_f32(tmp));
+ t = vmla_f32(t, vget_low_f32(b), vget_low_f32(tmp));
+ t = vmla_f32(t, a, Yn);
+ t = vpadd_f32(t, t);
+ Yn = vext_f32(Yn, t, 1);
+
+ Xn = x;
+ t = vmul_f32(vget_high_f32(b), vget_high_f32(Xn));
+ t = vmla_f32(t, vget_low_f32(b), vget_low_f32(Xn));
+ t = vmla_f32(t, a, Yn);
+ t = vpadd_f32(t, t);
+ Yn = vext_f32(Yn, t, 1);
+
+ y.val[1] = Yn;
+
+ tmp = vcombine_f32(y.val[0], y.val[1]);
+
+ /* Store the 4 outputs and increment the pointer */
+ vst1q_f32(pOut, tmp);
+ pOut += 4;
+
+ /* Decrement the loop counter */
+ sample--;
+ }
+
+ /* If the block size is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = blockSize & 0x3U;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xns = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b[1] * Xn[2]) + (b[2] * Xn[3]) + (b[3] * Xns) + (a[0] * Yn[0]) + (a[1] * Yn[1]);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn[2] = Xn[3];
+ Xn[3] = Xns;
+ Yn[0] = Yn[1];
+ Yn[1] = acc;
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ vst1q_f32(pState,vcombine_f32(vrev64_f32(vget_high_f32(Xn)),vrev64_f32(Yn)));
+ pState += 4;
+ /* Store the updated state variables back into the pState array */
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Decrement the loop counter */
+ stage--;
+ }
+}
+
+#else
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ const float32_t *pIn = pSrc; /* Source pointer */
+ float32_t *pOut = pDst; /* Destination pointer */
+ float32_t *pState = S->pState; /* pState pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t acc; /* Accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
+ float32_t Xn; /* Temporary input */
+ uint32_t sample, stage = S->numStages; /* Loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* Variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ sample = blockSize >> 2U;
+
+ while (sample > 0U)
+ {
+ /* Read the first input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store output in destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store output in destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store output in destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store output in destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ sample = blockSize & 0x3U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ sample = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store output in destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset output pointer */
+ pOut = pDst;
+
+ /* decrement loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+}
+
+#endif /* #if defined(ARM_MATH_NEON) */
+/**
+ @} end of BiquadCascadeDF1 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 000000000..1a568d70d
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,250 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_fast_q15.c
+ * Description: Fast processing function for the Q15 Biquad cascade filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1
+ @{
+ */
+
+/**
+ @brief Processing function for the Q15 Biquad cascade filter (fast variant).
+ @param[in] S points to an instance of the Q15 Biquad cascade structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process per call
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This fast version uses a 32-bit accumulator with 2.30 format.
+ The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around and distorts the result.
+ In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).
+ The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.
+ @remark
+ Refer to \ref arm_biquad_cascade_df1_q15() for a slower implementation of this function
+ which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ Use the function \ref arm_biquad_cascade_df1_init_q15() to initialize the filter structure.
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ const q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t acc; /* Accumulator */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */
+ uint32_t sample, stage = S->numStages; /* Loop counters */
+
+ do
+ {
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = read_q15x2_ia ((q15_t **) &pCoeffs);
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = read_q15x2_ia ((q15_t **) &pCoeffs);
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = read_q15x2_ia ((q15_t **) &pCoeffs);
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = read_q15x2_ia (&pState);
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = read_q15x2_da (&pState);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* Variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ /* Loop unrolling: Compute 2 outputs at a time */
+ sample = blockSize >> 1U;
+
+ while (sample > 0U)
+ {
+
+ /* Read the input */
+ in = read_q15x2_ia ((q15_t **) &pIn);
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+ /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+#else
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Store the output in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef ARM_MATH_BIG_ENDIAN
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+#else
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement loop counter */
+ sample--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ sample = (blockSize & 0x1U);
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ sample = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+#ifndef ARM_MATH_BIG_ENDIAN
+ out = __SMUAD(b0, in);
+#else
+ out = __SMUADX(b0, in);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef ARM_MATH_BIG_ENDIAN
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+#else
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent (numStages - 1) occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ write_q15x2_ia(&pState, state_in);
+ write_q15x2_ia(&pState, state_out);
+
+ /* Decrement loop counter */
+ stage--;
+
+ } while (stage > 0U);
+}
+
+/**
+ @} end of BiquadCascadeDF1 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 000000000..586296b32
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,296 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_fast_q31.c
+ * Description: Processing function for the Q31 Fast Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 Biquad cascade filter (fast variant).
+ @param[in] S points to an instance of the Q31 Biquad cascade structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process per call
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ These intermediate results are added to a 2.30 accumulator.
+ Finally, the accumulator is saturated and converted to a 1.31 result.
+ The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function
+ arm_biquad_cascade_df1_init_q31() to initialize filter structure.
+ @remark
+ Refer to \ref arm_biquad_cascade_df1_q31() for a slower implementation of this function
+ which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ Use the function \ref arm_biquad_cascade_df1_init_q31() to initialize the filter structure.
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ const q31_t *pIn = pSrc; /* Source pointer */
+ q31_t *pOut = pDst; /* Destination pointer */
+ q31_t *pState = S->pState; /* pState pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t acc = 0; /* Accumulator */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
+ q31_t Xn; /* Temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* Loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* Variables acc ... acc3 hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ sample = blockSize >> 2U;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /* acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);*/
+ mult_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b1 * x[n-1] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b[2] * x[n-2] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the second input */
+ Xn2 = *(pIn + 1U);
+
+ /* Store the output in the destination buffer. */
+ *pOut = Yn2;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /* acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);*/
+ mult_32x32_keep32_R(acc, b0, Xn2);
+ /* acc += b1 * x[n-1] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b1, Xn);
+ /* acc += b[2] * x[n-2] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn1);
+ /* acc += a1 * y[n-1] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Read the third input */
+ Xn1 = *(pIn + 2U);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 1U) = Yn1;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /* acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);*/
+ mult_32x32_keep32_R(acc, b0, Xn1);
+ /* acc += b1 * x[n-1] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b1, Xn2);
+ /* acc += b[2] * x[n-2] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn);
+ /* acc += a1 * y[n-1] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the forth input */
+ Xn = *(pIn + 3U);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 2U) = Yn2;
+ pIn += 4U;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ /*acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ Xn2 = Xn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Xn1 = Xn */
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 3U) = Yn1;
+ pOut += 4U;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ sample = (blockSize & 0x3U);
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ sample = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ /* acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);*/
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ /* acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);*/
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 */
+ acc = acc << shift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = acc;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+}
+
+/**
+ @} end of BiquadCascadeDF1 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 000000000..f51c26214
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,91 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_init_f32.c
+ * Description: Floating-point Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point Biquad cascade filter.
+ @param[in,out] S points to an instance of the floating-point Biquad cascade structure.
+ @param[in] numStages number of 2nd order stages in the filter.
+ @param[in] pCoeffs points to the filter coefficients.
+ @param[in] pState points to the state buffer.
+ @return none
+
+ @par Coefficient and State Ordering
+ The coefficients are stored in the array pCoeffs in the following order:
+
+ {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+
+ @par
+ where b1x and a1x are the coefficients for the first stage,
+ b2x and a2x are the coefficients for the second stage,
+ and so on. The pCoeffs array contains a total of 5*numStages values.
+ @par
+ The pState is a pointer to state array.
+ Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ The state variables are arranged in the pState array as:
+
+ {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ The state array has a total length of 4*numStages values.
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of BiquadCascadeDF1 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 000000000..c2e542c43
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_init_q15.c
+ * Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q15 Biquad cascade filter.
+ @param[in,out] S points to an instance of the Q15 Biquad cascade structure.
+ @param[in] numStages number of 2nd order stages in the filter.
+ @param[in] pCoeffs points to the filter coefficients.
+ @param[in] pState points to the state buffer.
+ @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format
+ @return none
+
+ @par Coefficient and State Ordering
+ The coefficients are stored in the array pCoeffs in the following order:
+
+ {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+
+ @par
+ where b1x and a1x are the coefficients for the first stage,
+ b2x and a2x are the coefficients for the second stage,
+ and so on. The pCoeffs array contains a total of 6*numStages values.
+ The zero coefficient between b1 and b2 facilities use of 16-bit SIMD instructions on the Cortex-M4.
+ @par
+ The state variables are stored in the array pState.
+ Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ The state variables are arranged in the pState array as:
+
+ {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ The state array has a total length of 4*numStages values.
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of BiquadCascadeDF1 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 000000000..8637889b5
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_init_q31.c
+ * Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q31 Biquad cascade filter.
+ @param[in,out] S points to an instance of the Q31 Biquad cascade structure.
+ @param[in] numStages number of 2nd order stages in the filter.
+ @param[in] pCoeffs points to the filter coefficients.
+ @param[in] pState points to the state buffer.
+ @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format
+ @return none
+
+ @par Coefficient and State Ordering
+ The coefficients are stored in the array pCoeffs in the following order:
+
+ {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par
+ where b1x and a1x are the coefficients for the first stage,
+ b2x and a2x are the coefficients for the second stage,
+ and so on. The pCoeffs array contains a total of 5*numStages values.
+ @par
+ The pState points to state variables array.
+ Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].
+ The state variables are arranged in the pState array as:
+
+ {x[n-1], x[n-2], y[n-1], y[n-2]}
+
+ The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ The state array has a total length of 4*numStages values.
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of BiquadCascadeDF1 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 000000000..9e23897d6
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,363 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_q15.c
+ * Description: Processing function for the Q15 Biquad cascade DirectFormI(DF1) filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1
+ @{
+ */
+
+/**
+ @brief Processing function for the Q15 Biquad cascade filter.
+ @param[in] S points to an instance of the Q15 Biquad cascade structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the location where the output result is written
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.
+ Finally, the result is saturated to 1.15 format.
+ @remark
+ Refer to \ref arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter.
+ */
+
+void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+
+
+#if defined (ARM_MATH_DSP)
+
+ const q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc_l, acc_h;
+ q63_t acc; /* Accumulator */
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+ int32_t uShift = (32 - lShift);
+
+ do
+ {
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = read_q15x2_ia ((q15_t **) &pCoeffs);
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = read_q15x2_ia ((q15_t **) &pCoeffs);
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = read_q15x2_ia ((q15_t **) &pCoeffs);
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = read_q15x2_ia (&pState);
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = read_q15x2_da (&pState);
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1U;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while (sample > 0U)
+ {
+
+ /* Read the input */
+ in = read_q15x2_ia ((q15_t **) &pIn);
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+#else
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT(state_out, out, 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT(out, state_out >> 16, 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef ARM_MATH_BIG_ENDIAN
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+#else
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if ((blockSize & 0x1U) != 0U)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+#ifndef ARM_MATH_BIG_ENDIAN
+ out = __SMUAD(b0, in);
+#else
+ out = __SMUADX(b0, in);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef ARM_MATH_BIG_ENDIAN
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+#else
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ }
+
+ /* The first stage goes from the input wire to the output wire. */
+ /* Subsequent numStages occur in-place in the output wire */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ write_q15x2_ia (&pState, state_in);
+ write_q15x2_ia (&pState, state_out);
+
+ /* Decrement loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+#else
+
+ const q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q15_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q15_t Xn; /* temporary input */
+ q63_t acc; /* Accumulator */
+ int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ pCoeffs++; // skip the 0 coefficient
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q31_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q31_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q31_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q31_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q31_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q15_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while (--stage);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ @} end of BiquadCascadeDF1 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 000000000..011e21dfe
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,247 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df1_q31.c
+ * Description: Processing function for the Q31 Biquad cascade filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF1
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 Biquad cascade filter.
+ @param[in] S points to an instance of the Q31 Biquad cascade structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to
+ 1.31 format by discarding the low 32 bits.
+ @remark
+ Refer to \ref arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter.
+ */
+
+void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ const q31_t *pIn = pSrc; /* Source pointer */
+ q31_t *pOut = pDst; /* Destination pointer */
+ q31_t *pState = S->pState; /* pState pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q63_t acc; /* Accumulator */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
+ q31_t Xn; /* Temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc_l, acc_h; /* temporary output variables */
+#endif
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* Variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ sample = blockSize >> 2U;
+
+ while (sample > 0U)
+ {
+ /* Read the first input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2);
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+ acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */
+ acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store output in destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = ((q63_t) b0 * Xn2) + ((q63_t) b1 * Xn) + ((q63_t) b2 * Xn1) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1);
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */
+ acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store output in destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = ((q63_t) b0 * Xn1) + ((q63_t) b1 * Xn2) + ((q63_t) b2 * Xn) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2);
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */
+ acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store output in destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn2) + ((q63_t) a2 * Yn1);
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ acc_l = (acc ) & 0xffffffff; /* Calc lower part of acc */
+ acc_h = (acc >> 32) & 0xffffffff; /* Calc upper part of acc */
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store output in destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ sample = blockSize & 0x3U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ sample = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (sample > 0U)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = ((q63_t) b0 * Xn) + ((q63_t) b1 * Xn1) + ((q63_t) b2 * Xn2) + ((q63_t) a1 * Yn1) + ((q63_t) a2 * Yn2);
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Store output in destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset output pointer */
+ pOut = pDst;
+
+ /* decrement loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+}
+
+/**
+ @} end of BiquadCascadeDF1 group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
new file mode 100644
index 000000000..a8af8cec5
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c
@@ -0,0 +1,443 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df2T_f64.c
+ * Description: Processing function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+*/
+
+/**
+ @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+
+ This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+ The filters are implemented as a cascade of second order Biquad sections.
+ These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+ Only floating-point data is supported.
+
+ This function operate on blocks of input and output data and each call to the function
+ processes blockSize samples through the filter.
+ pSrc points to the array of input data and
+ pDst points to the array of output data.
+ Both arrays contain blockSize values.
+
+ @par Algorithm
+ Each Biquad stage implements a second order filter using the difference equation:
+
+ y[n] = b0 * x[n] + d1
+ d1 = b1 * x[n] + a1 * y[n] + d2
+ d2 = b2 * x[n] + a2 * y[n]
+
+ where d1 and d2 represent the two state values.
+ @par
+ A Biquad filter using a transposed Direct Form II structure is shown below.
+ \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+ Coefficients b0, b1, and b2 multiply the input signal x[n] and are referred to as the feedforward coefficients.
+ Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.
+ Pay careful attention to the sign of the feedback coefficients.
+ Some design tools flip the sign of the feedback coefficients:
+
+ y[n] = b0 * x[n] + d1;
+ d1 = b1 * x[n] - a1 * y[n] + d2;
+ d2 = b2 * x[n] - a2 * y[n];
+
+ In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.
+ @par
+ Higher order filters are realized as a cascade of second order sections.
+ numStages refers to the number of second order stages used.
+ For example, an 8th order filter would be realized with numStages=4 second order stages.
+ A 9th order filter would be realized with numStages=5 second order stages with the
+ coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).
+ @par
+ pState points to the state variable array.
+ Each Biquad stage has 2 state variables d1 and d2.
+ The state variables are arranged in the pState array as:
+
+ {d11, d12, d21, d22, ...}
+
+ where d1x refers to the state variables for the first Biquad and
+ d2x refers to the state variables for the second Biquad.
+ The state array has a total length of 2*numStages values.
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+ @par
+ The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+ The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+ That is why the Direct Form I structure supports Q15 and Q31 data types.
+ The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.
+ Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+ The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter.
+ Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+
+ @par Init Functions
+ There is also an associated initialization function.
+ The initialization function performs following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ Set the values in the state buffer to zeros before static initialization.
+ For example, to statically initialize the instance structure use
+
+ arm_biquad_cascade_df2T_instance_f64 S1 = {numStages, pState, pCoeffs};
+ arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+
+ where numStages is the number of Biquad stages in the filter;
+ pState is the address of the state buffer.
+ pCoeffs is the address of the coefficient buffer;
+*/
+
+/**
+ @addtogroup BiquadCascadeDF2T
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ @param[in] S points to an instance of the filter data structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize)
+{
+
+ float64_t *pIn = pSrc; /* Source pointer */
+ float64_t *pOut = pDst; /* Destination pointer */
+ float64_t *pState = S->pState; /* State pointer */
+ float64_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float64_t acc1; /* Accumulator */
+ float64_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float64_t Xn1; /* Temporary input */
+ float64_t d1, d2; /* State variables */
+ uint32_t sample, stage = S->numStages; /* Loop counters */
+
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = pCoeffs[0];
+ b1 = pCoeffs[1];
+ b2 = pCoeffs[2];
+ a1 = pCoeffs[3];
+ a2 = pCoeffs[4];
+
+ /* Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ pCoeffs += 5U;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 16 outputs at a time */
+ sample = blockSize >> 4U;
+
+ while (sample > 0U) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+/* 1 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+
+/* 2 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 3 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 4 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 5 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 6 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 7 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 8 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 9 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 10 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 11 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 12 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 13 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 14 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 15 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+/* 16 */
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ sample = blockSize & 0xFU;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ sample = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (sample > 0U) {
+ Xn1 = *pIn++;
+
+ acc1 = b0 * Xn1 + d1;
+
+ d1 = b1 * Xn1 + d2;
+ d1 += a1 * acc1;
+
+ d2 = b2 * Xn1;
+ d2 += a2 * acc1;
+
+ *pOut++ = acc1;
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ pState[0] = d1;
+ pState[1] = d2;
+
+ pState += 2U;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /* Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ @} end of BiquadCascadeDF2T group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
new file mode 100644
index 000000000..fe6901edf
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c
@@ -0,0 +1,86 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_df2T_init_f64.c
+ * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF2T
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ @param[in,out] S points to an instance of the filter data structure
+ @param[in] numStages number of 2nd order stages in the filter
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @return none
+
+ @par Coefficient and State Ordering
+ The coefficients are stored in the array pCoeffs in the following order:
+
+ {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par
+ where b1x and a1x are the coefficients for the first stage,
+ b2x and a2x are the coefficients for the second stage,
+ and so on. The pCoeffs array contains a total of 5*numStages values.
+ @par
+ The pState is a pointer to state array.
+ Each Biquad stage has 2 state variables d1, and d2.
+ The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ The state array has a total length of 2*numStages values.
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 2 * numStages */
+ memset(pState, 0, (2U * (uint32_t) numStages) * sizeof(float64_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of BiquadCascadeDF2T group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
new file mode 100644
index 000000000..14ae008b8
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c
@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_stereo_df2T_f32.c
+ * Description: Processing function for floating-point transposed direct form II Biquad cascade filter. 2 channels
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+*/
+
+/**
+ @addtogroup BiquadCascadeDF2T
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ @param[in] S points to an instance of the filter data structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ const float32_t *pIn = pSrc; /* Source pointer */
+ float32_t *pOut = pDst; /* Destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t acc1a, acc1b; /* Accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1a, Xn1b; /* Temporary input */
+ float32_t d1a, d2a, d1b, d2b; /* State variables */
+ uint32_t sample, stage = S->numStages; /* Loop counters */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = pCoeffs[0];
+ b1 = pCoeffs[1];
+ b2 = pCoeffs[2];
+ a1 = pCoeffs[3];
+ a2 = pCoeffs[4];
+
+ /* Reading the state values */
+ d1a = pState[0];
+ d2a = pState[1];
+ d1b = pState[2];
+ d2b = pState[3];
+
+ pCoeffs += 5U;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 8 outputs at a time */
+ sample = blockSize >> 3U;
+
+ while (sample > 0U) {
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+/* 1 */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+/* 2 */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+/* 3 */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+/* 4 */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+/* 5 */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+/* 6 */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+/* 7 */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+/* 8 */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ sample = blockSize & 0x7U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ sample = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (sample > 0U) {
+ /* Read the input */
+ Xn1a = *pIn++; /* Channel a */
+ Xn1b = *pIn++; /* Channel b */
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1a = (b0 * Xn1a) + d1a;
+ acc1b = (b0 * Xn1b) + d1b;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1a;
+ *pOut++ = acc1b;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1a = ((b1 * Xn1a) + (a1 * acc1a)) + d2a;
+ d1b = ((b1 * Xn1b) + (a1 * acc1b)) + d2b;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2a = (b2 * Xn1a) + (a2 * acc1a);
+ d2b = (b2 * Xn1b) + (a2 * acc1b);
+
+ /* decrement loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ pState[0] = d1a;
+ pState[1] = d2a;
+
+ pState[2] = d1b;
+ pState[3] = d2b;
+
+ pState += 4U;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /* Reset the output working pointer */
+ pOut = pDst;
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while (stage > 0U);
+
+}
+LOW_OPTIMIZATION_EXIT
+/**
+ @} end of BiquadCascadeDF2T group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
new file mode 100644
index 000000000..d398f1817
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c
@@ -0,0 +1,86 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_biquad_cascade_stereo_df2T_init_f32.c
+ * Description: Initialization function for floating-point transposed direct form II Biquad cascade filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup BiquadCascadeDF2T
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ @param[in,out] S points to an instance of the filter data structure.
+ @param[in] numStages number of 2nd order stages in the filter.
+ @param[in] pCoeffs points to the filter coefficients.
+ @param[in] pState points to the state buffer.
+ @return none
+
+ @par Coefficient and State Ordering
+ The coefficients are stored in the array pCoeffs in the following order:
+
+ {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+
+ @par
+ where b1x and a1x are the coefficients for the first stage,
+ b2x and a2x are the coefficients for the second stage,
+ and so on. The pCoeffs array contains a total of 5*numStages values.
+ @par
+ The pState is a pointer to state array.
+ Each Biquad stage has 2 state variables d1, and d2 for each channel.
+ The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ The state array has a total length of 2*numStages values.
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4U * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of BiquadCascadeDF2T group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
new file mode 100644
index 000000000..ed2aea940
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c
@@ -0,0 +1,366 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_fast_opt_q15.c
+ * Description: Fast Q15 Convolution
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Conv
+ @{
+ */
+
+/**
+ @brief Convolution of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1
+ @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2
+ @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This fast version uses a 32-bit accumulator with 2.30 format.
+ The accumulator maintains full precision of the intermediate multiplication results
+ but provides only a single guard bit. There is no saturation on intermediate additions.
+ Thus, if the accumulator overflows it wraps around and distorts the result.
+ The input signals should be scaled down to avoid intermediate overflows.
+ Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+
+ @remark
+ Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q31_t acc0; /* Accumulators */
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ q15_t *pOut = pDst; /* Output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ const q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* Loop counter */
+ uint32_t tapCnt; /* Loop count */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc1, acc2, acc3; /* Accumulators */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+#endif
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1U) zeros in scratch1 buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia ((q15_t **) &pIn2);
+ y2 = read_q15x2_ia ((q15_t **) &pIn2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (srcALen + srcBLen - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+ }
+
+}
+
+/**
+ @} end of Conv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 000000000..3102a05cd
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,663 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_fast_q15.c
+ * Description: Fast Q15 Convolution
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Conv
+ @{
+ */
+
+/**
+ @brief Convolution of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This fast version uses a 32-bit accumulator with 2.30 format.
+ The accumulator maintains full precision of the intermediate multiplication results
+ but provides only a single guard bit. There is no saturation on intermediate additions.
+ Thus, if the accumulator overflows it wraps around and distorts the result.
+ The input signals should be scaled down to avoid intermediate overflows.
+ Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+
+ @remark
+ Refer to \ref arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ q15_t *pOut = pDst; /* Output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ const q15_t *px; /* Intermediate inputA pointer */
+ const q15_t *py; /* Intermediate inputB pointer */
+ const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ uint32_t j, k, count, blkCnt; /* Loop counters */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1U);
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = read_q15x2 ((q15_t *) px);
+ /* read x[1], x[2] samples */
+ x1 = read_q15x2 ((q15_t *) px + 1);
+ px += 2U;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = read_q15x2_da ((q15_t **) &py);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[3], x[4] */
+ x3 = read_q15x2 ((q15_t *) px + 1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = read_q15x2_da ((q15_t **) &py);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = read_q15x2 ((q15_t *) px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = read_q15x2 ((q15_t *) px + 3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+ c0 = c0 << 16U;
+#else
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = read_q15x2 ((q15_t *) px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = read_q15x2 ((q15_t *) py);
+
+ /* Read x[7], x[8] */
+ x3 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[9] */
+ x2 = read_q15x2 ((q15_t *) px + 1);
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = read_q15x2 ((q15_t *) py);
+
+ /* Read x[7], x[8] */
+ x3 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[9] */
+ x2 = read_q15x2 ((q15_t *) px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+ c0 = c0 << 16U;
+#else
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = read_q15x2 ((q15_t *) px + 2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT((acc0 >> 15), (acc1 >> 15), 16));
+ write_q15x2_ia (&pOut, __PKHBT((acc2 >> 15), (acc3 >> 15), 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT((acc1 >> 15), (acc0 >> 15), 16));
+ write_q15x2_ia (&pOut, __PKHBT((acc3 >> 15), (acc2 >> 15), 16));
+#endif /*#ifndef ARM_MATH_BIG_ENDIAN*/
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) *px++ * *py--);
+ sum += ((q31_t) *px++ * *py--);
+ sum += ((q31_t) *px++ * *py--);
+ sum += ((q31_t) *px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) *px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) *px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ @} end of Conv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 000000000..e87eddc73
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,558 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_fast_q31.c
+ * Description: Fast Q31 Convolution
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Conv
+ @{
+ */
+
+/**
+ @brief Convolution of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence.
+ @param[in] srcALen length of the first input sequence.
+ @param[in] pSrcB points to the second input sequence.
+ @param[in] srcBLen length of the second input sequence.
+ @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ Finally, the accumulator is saturated and converted to a 1.31 result.
+ @par
+ The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ In order to avoid overflows completely the input signals must be scaled down.
+ Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ @remark
+ Refer to \ref arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_conv_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ const q31_t *pIn1; /* InputA pointer */
+ const q31_t *pIn2; /* InputB pointer */
+ q31_t *pOut = pDst; /* Output pointer */
+ const q31_t *px; /* Intermediate inputA pointer */
+ const q31_t *py; /* Intermediate inputB pointer */
+ const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ uint32_t j, k, count, blkCnt; /* Loop counters */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *py--;
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *py--;
+ /* Read x[4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *py--;
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *py--;
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *py--;
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ @} end of Conv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
new file mode 100644
index 000000000..6ad34cdc6
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c
@@ -0,0 +1,362 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_opt_q15.c
+ * Description: Convolution of Q15 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Conv
+ @{
+ */
+
+/**
+ @brief Convolution of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ This approach provides 33 guard bits and there is no risk of overflow.
+ The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ @remark
+ Refer to \ref arm_conv_fast_q15() for a faster but less precise version of this function.
+ */
+
+void arm_conv_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q63_t acc0; /* Accumulators */
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ q15_t *pOut = pDst; /* Output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ const q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* Loop counter */
+ uint32_t tapCnt; /* Loop count */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q63_t acc1, acc2, acc3; /* Accumulators */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+#endif
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1U) zeros in scratch1 buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia ((q15_t **) &pIn2);
+ y2 = read_q15x2_ia ((q15_t **) &pIn2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (srcALen + srcBLen - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+ }
+
+}
+
+/**
+ @} end of Conv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
new file mode 100644
index 000000000..fb9e2eccf
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c
@@ -0,0 +1,360 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_opt_q7.c
+ * Description: Convolution of Q7 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Conv
+ @{
+ */
+
+/**
+ @brief Convolution of Q7 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ */
+
+void arm_conv_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */
+ q15_t x4; /* Temporary input variable */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* Loop counter */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ const q7_t *px; /* Temporary input1 pointer */
+ q7_t *pOut = pDst; /* Output pointer */
+ q7_t out0, out1, out2, out3; /* Temporary variables */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2U;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia (&pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia (&pScr2);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7U, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7U, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+ write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4U;
+ }
+
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1U;
+ }
+
+}
+
+/**
+ @} end of Conv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 000000000..e25f9ab3a
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,676 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_f32.c
+ * Description: Partial convolution of floating-point sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup PartialConv Partial Convolution
+
+ Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.
+ Each function has two additional arguments.
+ firstIndex specifies the starting index of the subset of output samples.
+ numPoints is the number of output samples to compute.
+ The function computes the output in the range
+ [firstIndex, ..., firstIndex+numPoints-1].
+ The output array pDst contains numPoints values.
+
+ The allowable range of output indices is [0 srcALen+srcBLen-2].
+ If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.
+ Otherwise the functions return ARM_MATH_SUCCESS.
+ \note Refer to \ref arm_conv_f32() for details on fixed point behavior.
+
+ @par Fast Versions
+ Fast versions are supported for Q31 and Q15 of partial convolution.
+ Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
+ the input signals should be scaled down to avoid intermediate overflows.
+
+ @par Opt Versions
+ Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ These versions are optimised in cycles and consumes more memory (Scratch memory) compared to Q15 and Q7 versions of partial convolution
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of floating-point sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+ */
+
+arm_status arm_conv_partial_f32(
+ const float32_t * pSrcA,
+ uint32_t srcALen,
+ const float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+ const float32_t *pIn1 = pSrcA; /* InputA pointer */
+ const float32_t *pIn2 = pSrcB; /* InputB pointer */
+ float32_t *pOut = pDst; /* Output pointer */
+ const float32_t *px; /* Intermediate inputA pointer */
+ const float32_t *py; /* Intermediate inputB pointer */
+ const float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum; /* Accumulator */
+ uint32_t j, k, count, blkCnt, check;
+ int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ float32_t acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables */
+#endif
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0;
+ blockSize2 = ((int32_t) check - blockSize3) - (blockSize1 + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + firstIndex;
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc1;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ pSrc1 = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ pSrc1 = pIn1;
+ }
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *py--;
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *py--;
+ /* Read x[4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *py--;
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *py--;
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *py--;
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize2;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ const float32_t *pIn1 = pSrcA; /* InputA pointer */
+ const float32_t *pIn2 = pSrcB; /* InputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ( pIn1[j] * pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+
+ /* Set status as ARM_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
new file mode 100644
index 000000000..7166b577c
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
@@ -0,0 +1,387 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_fast_opt_q15.c
+ * Description: Fast Q15 Partial convolution
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2
+ @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen)
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+
+ @remark
+ Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+arm_status arm_conv_partial_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q15_t *pOut = pDst; /* Output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0; /* Accumulator */
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ const q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* Loop counter */
+ uint32_t tapCnt; /* Loop count */
+ arm_status status; /* Status variable */
+ q31_t x1; /* Temporary variables to hold state and coefficient values */
+ q31_t y1; /* State variables */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc1, acc2, acc3; /* Accumulator */
+ q31_t x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y2; /* State variables */
+#endif
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (numPoints) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia ((q15_t **) &pIn2);
+ y2 = read_q15x2_ia ((q15_t **) &pIn2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc3 = __SMLADX(x3, y2, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numPoints & 0x3;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numPoints;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read two samples from smaller buffer */
+ y1 = read_q15x2_ia ((q15_t **) &pIn2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 000000000..535fbc793
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,700 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_fast_q15.c
+ * Description: Fast Q15 Partial convolution
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+ @remark
+ Refer to \ref arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+arm_status arm_conv_partial_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ q15_t *pOut = pDst; /* Output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ const q15_t *px; /* Intermediate inputA pointer */
+ const q15_t *py; /* Intermediate inputB pointer */
+ const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary input variables */
+ uint32_t j, k, count, blkCnt, check;
+ int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1U;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ pSrc1 = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ pSrc1 = pIn1;
+ }
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = read_q15x2 ((q15_t *) px);
+ /* read x[1], x[2] samples */
+ x1 = read_q15x2 ((q15_t *) px + 1);
+ px += 2U;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = read_q15x2_da ((q15_t **) &py);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[3], x[4] */
+ x3 = read_q15x2 ((q15_t *) px + 1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = read_q15x2_da ((q15_t **) &py);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = read_q15x2 ((q15_t *) px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = read_q15x2 ((q15_t *) px + 3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py + 1);
+#ifdef ARM_MATH_BIG_ENDIAN
+ c0 = c0 << 16U;
+#else
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = read_q15x2 ((q15_t *) px);
+ px++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD (x0, c0, acc0);
+ acc1 = __SMLAD (x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = read_q15x2 ((q15_t *) py);
+
+ /* Read x[7], x[8] */
+ x3 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[9] */
+ x2 = read_q15x2 ((q15_t *) px + 1);
+ px += 2U;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = read_q15x2 ((q15_t *) py);
+
+ /* Read x[7], x[8] */
+ x3 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[9] */
+ x2 = read_q15x2 ((q15_t *) px + 1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+ c0 = c0 << 16U;
+#else
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = read_q15x2 ((q15_t *) px + 2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD (x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT(acc0 >> 15, acc1 >> 15, 16));
+ write_q15x2_ia (&pOut, __PKHBT(acc2 >> 15, acc3 >> 15, 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT(acc1 >> 15, acc0 >> 15, 16));
+ write_q15x2_ia (&pOut, __PKHBT(acc3 >> 15, acc2 >> 15, 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) *px++ * *py--);
+ sum += ((q31_t) *px++ * *py--);
+ sum += ((q31_t) *px++ * *py--);
+ sum += ((q31_t) *px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) *px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) *px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 000000000..f232d51f0
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,618 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_fast_q31.c
+ * Description: Fast Q31 Partial convolution
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+
+ @remark
+ Refer to \ref arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ */
+
+arm_status arm_conv_partial_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ const q31_t *pIn1; /* InputA pointer */
+ const q31_t *pIn2; /* InputB pointer */
+ q31_t *pOut = pDst; /* Output pointer */
+ const q31_t *px; /* Intermediate inputA pointer */
+ const q31_t *py; /* Intermediate inputB pointer */
+ const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum; /* Accumulators */
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0;
+#endif
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ pSrc1 = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ pSrc1 = pIn1;
+ }
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *py--;
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *py--;
+ /* Read x[4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *py--;
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *py--;
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *py--;
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize2;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py--))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
new file mode 100644
index 000000000..21999d2d9
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c
@@ -0,0 +1,386 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_opt_q15.c
+ * Description: Partial convolution of Q15 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+
+ @remark
+ Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function.
+ */
+
+arm_status arm_conv_partial_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* Output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0; /* Accumulator */
+ q31_t x1; /* Temporary variables to hold state and coefficient values */
+ q31_t y1; /* State variables */
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ const q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* Loop counter */
+ uint32_t tapCnt; /* Loop count */
+ arm_status status; /* Status variable */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q63_t acc1, acc2, acc3; /* Accumulator */
+ q31_t x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y2; /* State variables */
+#endif
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (numPoints) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia ((q15_t **) &pIn2);
+ y2 = read_q15x2_ia ((q15_t **) &pIn2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4U;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = numPoints & 0x3;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numPoints;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read two samples from smaller buffer */
+ y1 = read_q15x2_ia ((q15_t **) &pIn2);
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1U;
+
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
new file mode 100644
index 000000000..811f386ee
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c
@@ -0,0 +1,390 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_opt_q7.c
+ * Description: Partial convolution of Q7 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of Q7 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+ */
+
+arm_status arm_conv_partial_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* Loop counter */
+ const q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ arm_status status;
+ q7_t *pOut = pDst; /* Output pointer */
+ q7_t out0, out1, out2, out3; /* Temporary variables */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) *px--;
+ *pScr2++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialize temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumulators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia (&pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia (&pScr2);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7U, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7U, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+ write_q7x4_ia (&pOut, __PACKq7(out0, out1, out2, out3));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4U;
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read two samples from smaller buffer */
+ y1 = read_q15x2_ia (&pScr2);
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1U;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 000000000..55272eadf
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,752 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_q15.c
+ * Description: Partial convolution of Q15 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+
+ @remark
+ Refer to \ref arm_conv_partial_fast_q15() for a faster but less precise version of this function.
+ @remark
+ Refer to \ref arm_conv_partial_opt_q15() for a faster implementation of this function using scratch buffers.
+ */
+
+arm_status arm_conv_partial_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+#if defined (ARM_MATH_DSP)
+
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ q15_t *pOut = pDst; /* Output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ const q15_t *px; /* Intermediate inputA pointer */
+ const q15_t *py; /* Intermediate inputB pointer */
+ const q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary input variables to hold state and coefficient values */
+ int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ uint32_t j, k, count, blkCnt, check;
+ arm_status status; /* Status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while ((count < 4U) && (blockSize1 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1U;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ pSrc1 = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ pSrc1 = pIn1;
+ }
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ py = py - 1U;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = read_q15x2 ((q15_t *) px);
+ /* read x[1], x[2] samples */
+ x1 = read_q15x2 ((q15_t *) px + 1);
+ px += 2U;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = read_q15x2_da ((q15_t **) &py);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[3], x[4] */
+ x3 = read_q15x2 ((q15_t *) px + 1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = read_q15x2_da ((q15_t **) &py);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = read_q15x2 ((q15_t *) px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = read_q15x2 ((q15_t *) px + 3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+#ifdef ARM_MATH_BIG_ENDIAN
+ c0 = c0 << 16U;
+#else
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = read_q15x2 ((q15_t *) px);
+ px++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD (x0, c0, acc0);
+ acc1 = __SMLALD (x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = read_q15x2 ((q15_t *) py);
+
+ /* Read x[7], x[8] */
+ x3 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[9] */
+ x2 = read_q15x2 ((q15_t *) px + 1);
+ px += 2U;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = read_q15x2 ((q15_t *) py);
+
+ /* Read x[7], x[8] */
+ x3 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[9] */
+ x2 = read_q15x2 ((q15_t *) px + 1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+ c0 = c0 << 16U;
+#else
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = read_q15x2 ((q15_t *) px + 2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD (x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16));
+ write_q15x2_ia (&pOut, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) *px++ * *py--);
+ sum += (q63_t) ((q31_t) *px++ * *py--);
+ sum += (q63_t) ((q31_t) *px++ * *py--);
+ sum += (q63_t) ((q31_t) *px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) *px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) *px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ pIn2 = pSrc2 - 1U;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2U;
+
+ while ((j > 0U) && (blockSize3 > 0U))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(read_q15x2_ia ((q15_t **) &px), read_q15x2_da ((q15_t **) &py), sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1U;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement MAC count */
+ count--;
+
+ /* Decrement loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1U;
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+ const q15_t *pIn1 = pSrcA; /* InputA pointer */
+ const q15_t *pIn2 = pSrcB; /* InputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15U), 16U);
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 000000000..d0f0122d1
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,634 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_q31.c
+ * Description: Partial convolution of Q31 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of Q31 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+
+ @remark
+ Refer to \ref arm_conv_partial_fast_q31() for a faster but less precise implementation of this function.
+ */
+
+arm_status arm_conv_partial_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+ const q31_t *pIn1; /* InputA pointer */
+ const q31_t *pIn2; /* InputB pointer */
+ q31_t *pOut = pDst; /* Output pointer */
+ const q31_t *px; /* Intermediate inputA pointer */
+ const q31_t *py; /* Intermediate inputB pointer */
+ const q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum; /* Accumulator */
+ uint32_t j, k, count, blkCnt, check;
+ int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q63_t acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0; /* Temporary variables */
+#endif
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) *px++ * (*py--);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) *px++ * (*py--);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) *px++ * (*py--);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) *px++ * (*py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) *px++ * (*py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ pSrc1 = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ pSrc1 = pIn1;
+ }
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unroll over blkCnt */
+ blkCnt = blockSize2 / 3;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *px++;
+ x1 = *px++;
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[2] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += (q63_t) x0 * c0;
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += (q63_t) x1 * c0;
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += (q63_t) x2 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1U);
+
+ /* Read x[3] sample */
+ x0 = *(px + 1U);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += (q63_t) x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += (q63_t) x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += (q63_t) x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2U);
+
+ /* Read x[4] sample */
+ x1 = *(px + 2U);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += (q63_t) x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += (q63_t) x0 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += (q63_t) x1 * c0;
+
+
+ px += 3U;
+
+ py -= 3U;
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *py--;
+ /* Read x[7] sample */
+ x2 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += (q63_t) x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += (q63_t) x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += (q63_t) x2 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize2;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) *px++ * (*py--);
+ sum += (q63_t) *px++ * (*py--);
+ sum += (q63_t) *px++ * (*py--);
+ sum += (q63_t) *px++ * (*py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += (q63_t) *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += (q63_t) *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += (q63_t) *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += (q63_t) *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += (q63_t) *px++ * *py--;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ const q31_t *pIn1 = pSrcA; /* InputA pointer */
+ const q31_t *pIn2 = pSrcB; /* InputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31U);
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 000000000..9b0228cb6
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,753 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_partial_q7.c
+ * Description: Partial convolution of Q7 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup PartialConv
+ @{
+ */
+
+/**
+ @brief Partial convolution of Q7 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written
+ @param[in] firstIndex is the first output sample to start with
+ @param[in] numPoints is the number of output points to be computed
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : requested subset is not in the range [0 srcALen+srcBLen-2]
+
+ @remark
+ Refer to \ref arm_conv_partial_opt_q7() for a faster implementation of this function.
+ */
+
+arm_status arm_conv_partial_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+ const q7_t *pIn1; /* InputA pointer */
+ const q7_t *pIn2; /* InputB pointer */
+ q7_t *pOut = pDst; /* Output pointer */
+ const q7_t *px; /* Intermediate inputA pointer */
+ const q7_t *py; /* Intermediate inputB pointer */
+ const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum; /* Accumulator */
+ uint32_t j, k, count, blkCnt, check; /* Loop counters */
+ int32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2; /* Temporary input variables */
+ q15_t in1, in2; /* Temporary input variables */
+ q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */
+#endif
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t)check > (int32_t)srcALen) ? (int32_t)check - (int32_t)srcALen : 0;
+ blockSize3 = ((int32_t)firstIndex > (int32_t)srcALen - 1) ? blockSize3 - (int32_t)firstIndex + (int32_t)srcALen : blockSize3;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1U)) ? blockSize1 : (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1U + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ if ((int32_t)firstIndex - (int32_t)srcBLen + 1 > 0)
+ {
+ pSrc1 = pIn1 + firstIndex - srcBLen + 1;
+ }
+ else
+ {
+ pSrc1 = pIn1;
+ }
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = ((uint32_t) blockSize2 >> 2U);
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *py--;
+ /* Read y[srcBLen - 2] sample */
+ c1 = *py--;
+
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *px++;
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *py--;
+ /* Read y[srcBLen - 4] sample */
+ c1 = *py--;
+
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *py--;
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q31_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q31_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q31_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q31_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (uint32_t) blockSize2 % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize2;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ while (k > 0U)
+ {
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulate */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulate */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pSrc1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ const q7_t *pIn1 = pSrcA; /* InputA pointer */
+ const q7_t *pIn2 = pSrcB; /* InputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* Loop counters */
+ arm_status status; /* Status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if ((firstIndex + numPoints) > ((srcALen + (srcBLen - 1U))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U);
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of PartialConv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 000000000..bdd1cab89
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,700 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_conv_q7.c
+ * Description: Convolution of Q7 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Conv
+ @{
+ */
+
+/**
+ @brief Convolution of Q7 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ @remark
+ Refer to \ref arm_conv_opt_q7() for a faster implementation of this function.
+ */
+
+void arm_conv_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+ const q7_t *pIn1; /* InputA pointer */
+ const q7_t *pIn2; /* InputB pointer */
+ q7_t *pOut = pDst; /* Output pointer */
+ const q7_t *px; /* Intermediate inputA pointer */
+ const q7_t *py; /* Intermediate inputB pointer */
+ const q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum; /* Accumulators */
+ uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ uint32_t j, k, count, blkCnt; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t input1, input2; /* Temporary input variables */
+ q15_t in1, in2; /* Temporary input variables */
+ q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */
+#endif
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) *px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *py--;
+ /* Read y[srcBLen - 2] sample */
+ c1 = *py--;
+
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *px++;
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *py--;
+ /* Read y[srcBLen - 4] sample */
+ c1 = *py--;
+
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *py--;
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7U, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7U, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize2 % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize2;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ while (k > 0U)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Perform the multiply-accumulate */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Perform the multiply-accumulate */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) *px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) *px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1U));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1U);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = blockSize3 >> 2U;
+
+ while (k > 0U)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) *py--;
+ in2 = (q15_t) *py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = blockSize3 % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = blockSize3;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q15_t) *px++ * *py--);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7U, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement loop counter */
+ blockSize3--;
+ }
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ const q7_t *pIn1 = pSrcA; /* InputA pointer */
+ const q7_t *pIn2 = pSrcB; /* InputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* Loop counters */
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i < (srcALen + srcBLen - 1U); i++)
+ {
+ /* Initialize sum with zero to carry out MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7U), 8U);
+ }
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of Conv group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
new file mode 100644
index 000000000..13661cbf2
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c
@@ -0,0 +1,345 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_fast_opt_q15.c
+ * Description: Fast Q15 Correlation
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Corr
+ @{
+ */
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence.
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This fast version uses a 32-bit accumulator with 2.30 format.
+ The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ There is no saturation on intermediate additions.
+ Thus, if the accumulator overflows it wraps around and distorts the result.
+ The input signals should be scaled down to avoid intermediate overflows.
+ Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+
+ @remark
+ Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ q31_t acc0; /* Accumulators */
+ q15_t *pOut = pDst; /* Output pointer */
+ q15_t *pScr1 = pScratch; /* Temporary pointer for scratch */
+ const q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, blkCnt, outBlockSize; /* Loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ uint32_t tapCnt; /* Loop count */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc1, acc2, acc3; /* Accumulators */
+ q31_t x1, x2, x3; /* Temporary variables for holding input and coefficient values */
+ q31_t y1, y2; /* State variables */
+#endif
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+ }
+
+ pScr1 = pScratch;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia ((q15_t **) &pIn2);
+ y2 = read_q15x2_ia ((q15_t **) &pIn2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15U, 16));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4U;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (srcALen + srcBLen - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch buffer */
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1U;
+ }
+
+}
+
+/**
+ @} end of Corr group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 000000000..6898618f4
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,614 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_fast_q15.c
+ * Description: Fast Q15 Correlation
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Corr
+ @{
+ */
+
+/**
+ @brief Correlation of Q15 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This fast version uses a 32-bit accumulator with 2.30 format.
+ The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ There is no saturation on intermediate additions.
+ Thus, if the accumulator overflows it wraps around and distorts the result.
+ The input signals should be scaled down to avoid intermediate overflows.
+ Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+
+ @remark
+ Refer to \ref arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ q15_t *pOut = pDst; /* Output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ const q15_t *px; /* Intermediate inputA pointer */
+ const q15_t *py; /* Intermediate inputB pointer */
+ const q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ uint32_t j, k, count, blkCnt; /* Loop counters */
+ uint32_t outBlockSize;
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1U);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum);
+ /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+ sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = read_q15x2 ((q15_t *) px);
+ /* read x[1], x[2] samples */
+ x1 = read_q15x2 ((q15_t *) px + 1);
+ px += 2U;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ c0 = read_q15x2_ia ((q15_t **) &py);
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[3], x[4] */
+ x3 = read_q15x2 ((q15_t *) px + 1);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ c0 = read_q15x2_ia ((q15_t **) &py);
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = read_q15x2 ((q15_t *) px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = read_q15x2 ((q15_t *) px + 3);
+ px += 4U;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while (--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ if (k == 1U)
+ {
+ /* Read y[4] */
+ c0 = *py;
+
+#ifdef ARM_MATH_BIG_ENDIAN
+ c0 = c0 << 16U;
+#else
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = read_q15x2 ((q15_t *) px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD (x0, c0, acc0);
+ acc1 = __SMLAD (x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if (k == 2U)
+ {
+ /* Read y[4], y[5] */
+ c0 = read_q15x2 ((q15_t *) py);
+
+ /* Read x[7], x[8] */
+ x3 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[9] */
+ x2 = read_q15x2 ((q15_t *) px + 1);
+ px += 2U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if (k == 3U)
+ {
+ /* Read y[4], y[5] */
+ c0 = read_q15x2_ia ((q15_t **) &py);
+
+ /* Read x[7], x[8] */
+ x3 = read_q15x2 ((q15_t *) px);
+
+ /* Read x[9] */
+ x2 = read_q15x2 ((q15_t *) px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+ c0 = c0 << 16U;
+#else
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = read_q15x2 ((q15_t *) px + 2);
+ px += 3U;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD (x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) *px++ * *py++);
+ sum += ((q31_t) *px++ * *py++);
+ sum += ((q31_t) *px++ * *py++);
+ sum += ((q31_t) *px++ * *py++);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) *px++ * *py++);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1U);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = __SMLAD(read_q15x2_ia ((q15_t **) &px), read_q15x2_ia ((q15_t **) &py), sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ @} end of Corr group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 000000000..a5840b733
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,601 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_fast_q31.c
+ * Description: Fast Q31 Correlation
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Corr
+ @{
+ */
+
+/**
+ @brief Correlation of Q31 sequences (fast version).
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ Finally, the accumulator is saturated and converted to a 1.31 result.
+ @par
+ The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ In order to avoid overflows completely the input signals must be scaled down.
+ The input signals should be scaled down to avoid intermediate overflows.
+ Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ maximum of min(srcALen, srcBLen) number of additions is carried internally.
+
+ @remark
+ Refer to \ref arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_correlate_fast_q31(
+ const q31_t * pSrcA,
+ uint32_t srcALen,
+ const q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ const q31_t *pIn1; /* InputA pointer */
+ const q31_t *pIn2; /* InputB pointer */
+ q31_t *pOut = pDst; /* Output pointer */
+ const q31_t *px; /* Intermediate inputA pointer */
+ const q31_t *py; /* Intermediate inputB pointer */
+ const q31_t *pSrc1; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables for holding input and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ uint32_t j, k, count, blkCnt; /* Loop counters */
+ uint32_t outBlockSize;
+ int32_t inc = 1; /* Destination address modifier */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1U);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* x[1] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* x[2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* x[3] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *py++;
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[1] * y[0] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[2] * y[0] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[3] * y[0] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+
+ /* Read y[1] sample */
+ c0 = *py++;
+ /* Read x[4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+
+ /* Read y[2] sample */
+ c0 = *py++;
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+
+ /* Read y[3] sample */
+ c0 = *py++;
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[4] sample */
+ c0 = *py++;
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (acc0 << 1);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q31_t) (acc1 << 1);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc2 << 1);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc3 << 1);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4U;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1U;
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) *px++ * (*py++))) >> 32);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement MAC count */
+ count--;
+
+ /* Decrement loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ @} end of Corr group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c
new file mode 100644
index 000000000..d46d9a0e5
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c
@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_opt_q15.c
+ * Description: Correlation of Q15 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Corr
+ @{
+ */
+
+/**
+ @brief Correlation of Q15 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ This approach provides 33 guard bits and there is no risk of overflow.
+ The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+
+ @remark
+ Refer to \ref arm_correlate_fast_q15() for a faster but less precise version of this function.
+ */
+
+void arm_correlate_opt_q15(
+ const q15_t * pSrcA,
+ uint32_t srcALen,
+ const q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q63_t acc0; /* Accumulators */
+ q15_t *pOut = pDst; /* Output pointer */
+ q15_t *pScr1; /* Temporary pointer for scratch1 */
+ const q15_t *pIn1; /* InputA pointer */
+ const q15_t *pIn2; /* InputB pointer */
+ const q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, blkCnt, outBlockSize; /* Loop counter */
+ int32_t inc = 1; /* Output pointer increment */
+ uint32_t tapCnt;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q63_t acc1, acc2, acc3; /* Accumulators */
+ q31_t x1, x2, x3; /* Temporary variables for holding input1 and input2 values */
+ q31_t y1, y2; /* State variables */
+#endif
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (srcALen * 2U) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+ }
+
+ pScr1 = pScratch;
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia ((q15_t **) &pIn2);
+ y2 = read_q15x2_ia ((q15_t **) &pIn2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15U, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15U, 16));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4U;
+ }
+
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (srcALen + srcBLen - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ Then store the output in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1U;
+ }
+
+}
+
+/**
+ @} end of Corr group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c
new file mode 100644
index 000000000..035bfba38
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c
@@ -0,0 +1,388 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_opt_q7.c
+ * Description: Correlation of Q7 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Corr
+ @{
+ */
+
+/**
+ @brief Correlation of Q7 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ */
+
+void arm_correlate_opt_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */
+ q15_t x4; /* Temporary input variable */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ const q7_t *pIn1, *pIn2; /* InputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* Loop counter */
+ int32_t inc = 1; /* Output pointer increment */
+ uint32_t outBlockSize; /* Loop counter */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ q7_t *pOut = pDst; /* Output pointer */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (srcALen * 2U) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+ }
+
+
+ /* Copy (srcBLen) samples in scratch buffer */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) *pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) *pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) *pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) *pIn2++;
+ *pScr2++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) *pIn2++;
+ *pScr2++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1U) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2U;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ a second loop below copies for the remaining 1 to 3 samples. */
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) *pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ No loop unrolling is used. */
+ k = srcALen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1U) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1U));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1U);
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pScr2 pointer */
+ pScr2 = pScratch2;
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1U) >> 2;
+
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = read_q15x2_ia (&pScr1);
+
+ tapCnt = (srcBLen) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia (&pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = read_q15x2_ia (&pScr1);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = read_q15x2_ia (&pScr2);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = read_q15x2_ia (&pScr1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3U;
+
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc1 >> 7U, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc2 >> 7U, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc3 >> 7U, 8));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4U;
+ }
+
+ blkCnt = (srcALen + srcBLen - 1U) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while (blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1U;
+
+ while (tapCnt > 0U)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1U;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while (tapCnt > 0U)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7U, 8));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1U;
+ }
+
+}
+
+/**
+ @} end of Corr group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
index 000000000..e5881acec
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,800 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_correlate_q7.c
+ * Description: Correlation of Q7 sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup Corr
+ @{
+ */
+
+/**
+ @brief Correlation of Q7 sequences.
+ @param[in] pSrcA points to the first input sequence
+ @param[in] srcALen length of the first input sequence
+ @param[in] pSrcB points to the second input sequence
+ @param[in] srcBLen length of the second input sequence
+ @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.
+ The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+
+ @remark
+ Refer to \ref arm_correlate_opt_q7() for a faster implementation of this function.
+ */
+
+void arm_correlate_q7(
+ const q7_t * pSrcA,
+ uint32_t srcALen,
+ const q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+ const q7_t *pIn1; /* InputA pointer */
+ const q7_t *pIn2; /* InputB pointer */
+ q7_t *pOut = pDst; /* Output pointer */
+ const q7_t *px; /* Intermediate inputA pointer */
+ const q7_t *py; /* Intermediate inputB pointer */
+ const q7_t *pSrc1; /* Intermediate pointers */
+ q31_t sum; /* Accumulators */
+ uint32_t blockSize1, blockSize2, blockSize3; /* Loop counters */
+ uint32_t j, k, count, blkCnt; /* Loop counters */
+ uint32_t outBlockSize;
+ int32_t inc = 1;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t input1, input2; /* Temporary input variables */
+ q15_t in1, in2; /* Temporary input variables */
+ q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables for holding input and coefficient values */
+#endif
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if (srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2U * srcALen) - 1U;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1U));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2U);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+ }
+
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1U;
+ blockSize2 = srcALen - (srcBLen - 1U);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1U;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1U);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while (blockSize1 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 4] , y[srcBLen - 3] */
+ in1 = (q15_t) *py++;
+ in2 = (q15_t) *py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 4] */
+ /* x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 2] , y[srcBLen - 1] */
+ in1 = (q15_t) *py++;
+ in2 = (q15_t) *py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 2] */
+ /* x[3] * y[srcBLen - 1] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize k with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q31_t) ((q15_t) *px++ * *py++);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7U, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment MAC count */
+ count++;
+
+ /* Decrement loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0U;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if (srcBLen >= 4U)
+ {
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize2 >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *py++;
+ /* Read y[1] sample */
+ c1 = *py++;
+
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[0] and y[1] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *px++;
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[2] sample */
+ c0 = *py++;
+ /* Read y[3] sample */
+ c1 = *py++;
+
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[2] and y[3] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while (--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4U;
+
+ while (k > 0U)
+ {
+ /* Read y[4] sample */
+ c0 = *py++;
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[4] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[4] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[4] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+ pOut += inc;
+
+ count += 4U;
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize2 % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize2;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = srcBLen >> 2U;
+
+ while (k > 0U)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) *py++;
+ in2 = (q15_t) *py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Perform the multiply-accumulate */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) *py++;
+ in2 = (q15_t) *py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* Perform the multiply-accumulate */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = srcBLen % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = srcBLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) *px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7U, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while (blkCnt > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) *px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7U, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1U;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1U));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while (blockSize3 > 0U)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ k = count >> 2U;
+
+ while (k > 0U)
+ {
+ /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[0] , y[1] */
+ in1 = (q15_t) *py++;
+ in2 = (q15_t) *py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+ in1 = (q15_t) *px++;
+ in2 = (q15_t) *px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* y[2] , y[3] */
+ in1 = (q15_t) *py++;
+ in2 = (q15_t) *py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16U);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ k = count % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ k = count;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (k > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) *px++ * *py++);
+
+ /* Decrement loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7U, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement MAC count */
+ count--;
+
+ /* Decrement loop counter */
+ blockSize3--;
+ }
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ const q7_t *pIn1 = pSrcA; /* InputA pointer */
+ const q7_t *pIn2 = pSrcB + (srcBLen - 1U); /* InputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i = 0U, j; /* Loop counters */
+ uint32_t inv = 0U; /* Reverse order flag */
+ uint32_t tot = 0U; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2U);
+
+ if (srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if (srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1U);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0U; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry out MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0U; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if (((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ if (inv == 1)
+ *pDst-- = (q7_t) __SSAT((sum >> 7U), 8U);
+ else
+ *pDst++ = (q7_t) __SSAT((sum >> 7U), 8U);
+ }
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of Corr group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
index 000000000..218ca34f2
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,703 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_decimate_f32.c
+ * Description: FIR decimation for floating-point sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator
+
+ These functions combine an FIR filter together with a decimator.
+ They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.
+ Conceptually, the functions are equivalent to the block diagram below:
+ \image html FIRDecimator.gif "Components included in the FIR Decimator functions"
+ When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized
+ cutoff frequency of 1/M in order to prevent aliasing distortion.
+ The user of the function is responsible for providing the filter coefficients.
+
+ The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.
+ Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the
+ samples output by the decimator are computed.
+ The functions operate on blocks of input and output data.
+ pSrc points to an array of blockSize input values and
+ pDst points to an array of blockSize/M output values.
+ In order to have an integer number of output samples blockSize
+ must always be a multiple of the decimation factor M.
+
+ The library provides separate functions for Q15, Q31 and floating-point data types.
+
+ @par Algorithm:
+ The FIR portion of the algorithm uses the standard form filter:
+
+ y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+ where, b[n] are the filter coefficients.
+ @par
+ The pCoeffs points to a coefficient array of size numTaps.
+ Coefficients are stored in time reversed order.
+ @par
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par
+ pState points to a state array of size numTaps + blockSize - 1.
+ Samples in the state buffer are stored in the order:
+ @par
+
+ {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ The state variables are updated after each block of data is processed, the coefficients are untouched.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter.
+ Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ There are separate instance structure declarations for each of the 3 supported data types.
+
+ @par Initialization Functions
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ - Checks to make sure that the size of the input is a multiple of the decimation factor.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero.
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ The code below statically initializes each of the 3 different data type filter instance structures
+
+ arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+ arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+ arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+
+ where M is the decimation factor; numTaps is the number of filter coefficients in the filter;
+ pCoeffs is the address of the coefficient buffer;
+ pState is the address of the state buffer.
+ Be sure to set the values in the state buffer to zeros when doing static initialization.
+
+ @par Fixed-Point Behavior
+ Care must be taken when using the fixed-point versions of the FIR decimate filter functions.
+ In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ @addtogroup FIR_decimate
+ @{
+ */
+
+/**
+ @brief Processing function for floating-point FIR decimator.
+ @param[in] S points to an instance of the floating-point FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+#if defined(ARM_MATH_NEON)
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px; /* Temporary pointer for state buffer */
+ const float32_t *pb; /* Temporary pointer for coefficient buffer */
+ float32_t sum0; /* Accumulator */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+ uint32_t blkCntN4;
+ float32_t *px0, *px1, *px2, *px3;
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x1, x2, x3;
+
+ float32x4_t accv,acc0v,acc1v,acc2v,acc3v;
+ float32x4_t x0v, x1v, x2v, x3v;
+ float32x4_t c0v;
+ float32x2_t temp;
+ float32x4_t sum0v;
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1U);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 4;
+ blkCntN4 = outBlockSize - (4 * blkCnt);
+
+ while (blkCnt > 0U)
+ {
+ /* Copy 4 * decimation factor number of new input samples into the state buffer */
+ i = 4 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulators to zero */
+ acc0v = vdupq_n_f32(0.0);
+ acc1v = vdupq_n_f32(0.0);
+ acc2v = vdupq_n_f32(0.0);
+ acc3v = vdupq_n_f32(0.0);
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+ px2 = pState + 2 * S->M;
+ px3 = pState + 3 * S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0v = vld1q_f32(pb);
+ pb += 4;
+
+ /* Read x[n-numTaps-1] sample for acc0 */
+ x0v = vld1q_f32(px0);
+ x1v = vld1q_f32(px1);
+ x2v = vld1q_f32(px2);
+ x3v = vld1q_f32(px3);
+
+ px0 += 4;
+ px1 += 4;
+ px2 += 4;
+ px3 += 4;
+
+ acc0v = vmlaq_f32(acc0v, x0v, c0v);
+ acc1v = vmlaq_f32(acc1v, x1v, c0v);
+ acc2v = vmlaq_f32(acc2v, x2v, c0v);
+ acc3v = vmlaq_f32(acc3v, x3v, c0v);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ temp = vpadd_f32(vget_low_f32(acc0v),vget_high_f32(acc0v));
+ accv[0] = temp[0] + temp[1];
+
+ temp = vpadd_f32(vget_low_f32(acc1v),vget_high_f32(acc1v));
+ accv[1] = temp[0] + temp[1];
+
+ temp = vpadd_f32(vget_low_f32(acc2v),vget_high_f32(acc2v));
+ accv[2] = temp[0] + temp[1];
+
+ temp = vpadd_f32(vget_low_f32(acc3v),vget_high_f32(acc3v));
+ accv[3] = temp[0] + temp[1];
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch state variables for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ accv[0] += x0 * c0;
+ accv[1] += x1 * c0;
+ accv[2] += x2 * c0;
+ accv[3] += x3 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + 4 * S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ vst1q_f32(pDst,accv);
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while (blkCntN4 > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0v = vdupq_n_f32(0.0);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while (tapCnt > 0U)
+ {
+ c0v = vld1q_f32(pb);
+ pb += 4;
+
+ x0v = vld1q_f32(px);
+ px += 4;
+
+ sum0v = vmlaq_f32(sum0v, x0v, c0v);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ temp = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v));
+ sum0 = temp[0] + temp[1];
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement the loop counter */
+ blkCntN4--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1U) >> 2;
+
+ /* Copy data */
+ while (i > 0U)
+ {
+ sum0v = vld1q_f32(pState);
+ vst1q_f32(pStateCurnt,sum0v);
+ pState += 4;
+ pStateCurnt += 4;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1U) % 0x04U;
+
+ /* Copy data */
+ while (i > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+#else
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCur; /* Points to the current sample of the state */
+ float32_t *px0; /* Temporary pointer for state buffer */
+ const float32_t *pb; /* Temporary pointer for coefficient buffer */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ float32_t acc0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ float32_t *px1, *px2, *px3;
+ float32_t x1, x2, x3;
+ float32_t acc1, acc2, acc3;
+#endif
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (numTaps - 1U);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 samples at a time */
+ blkCnt = outBlockSize >> 2U;
+
+ /* Samples loop unrolled by 4 */
+ while (blkCnt > 0U)
+ {
+ /* Copy 4 * decimation factor number of new input samples into the state buffer */
+ i = S->M * 4;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+ px2 = pState + 2 * S->M;
+ px3 = pState + 3 * S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample for acc0 */
+ x0 = *(px0++);
+ /* Read x[n-numTaps-1] sample for acc1 */
+ x1 = *(px1++);
+ /* Read x[n-numTaps-1] sample for acc2 */
+ x2 = *(px2++);
+ /* Read x[n-numTaps-1] sample for acc3 */
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch state variables for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 4;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = acc0;
+ *pDst++ = acc1;
+ *pDst++ = acc2;
+ *pDst++ = acc3;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining samples */
+ blkCnt = outBlockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = outBlockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0.0f;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = acc0;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x04U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of FIR_decimate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
index 000000000..948b15c2d
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,595 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_decimate_fast_q15.c
+ * Description: Fast Q15 FIR Decimator
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_decimate
+ @{
+ */
+
+/**
+ @brief Processing function for the Q15 FIR decimator (fast variant).
+ @param[in] S points to an instance of the Q15 FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of input samples to process per call
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This fast version uses a 32-bit accumulator with 2.30 format.
+ The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around and distorts the result.
+ In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).
+ The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ @remark
+ Refer to \ref arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ Both the slow and the fast versions use the same instance structure.
+ Use function \ref arm_fir_decimate_init_q15() to initialize the filter structure.
+ */
+
+#if defined (ARM_MATH_DSP)
+
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCur; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ const q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulators */
+ q31_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t c1; /* Temporary variables to hold state and coefficient values */
+#endif
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (numTaps - 1U);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while (blkCnt > 0U)
+ {
+ /* Copy 2 * decimation factor number of new input samples into the state buffer */
+ i = S->M * 2;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = read_q15x2_ia (&px0);
+ x1 = read_q15x2_ia (&px1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = read_q15x2_ia (&px0);
+ x1 = read_q15x2_ia (&px1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch state variables for acc0, acc1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ while (blkCntN3 > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */
+ x0 = read_q15x2_ia (&px);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficients */
+ c1 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c0, sum0);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = read_q15x2_ia (&px);
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c1, sum0);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c0, sum0);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+ i = (numTaps - 1U) >> 2U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState));
+ write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState));
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1U) % 0x04U;
+
+ /* Copy data */
+ while (i > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+}
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCur; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ const q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulators */
+ q31_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (numTaps - 1U);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while (blkCnt > 0U)
+ {
+ /* Copy 2 * decimation factor number of new input samples into the state buffer */
+ i = S->M * 2;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+ px1 = pState + S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ while (blkCntN3 > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+ i = (numTaps - 1U) >> 2U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1U) % 0x04U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+}
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+/**
+ @} end of FIR_decimate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
index 000000000..2c3a28aca
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,390 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_decimate_fast_q31.c
+ * Description: Fast Q31 FIR Decimator
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_decimate
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 FIR decimator (fast variant).
+ @param[in] S points to an instance of the Q31 FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ These intermediate results are added to a 2.30 accumulator.
+ Finally, the accumulator is saturated and converted to a 1.31 result.
+ The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+
+ @remark
+ Refer to \ref arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ Both the slow and the fast versions use the same instance structure.
+ Use function \ref arm_fir_decimate_init_q31() to initialize the filter structure.
+ */
+
+void arm_fir_decimate_fast_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCur; /* Points to the current sample of the state */
+ q31_t *px0; /* Temporary pointer for state buffer */
+ const q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t acc0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t *px1, *px2, *px3;
+ q31_t x1, x2, x3;
+ q63_t acc1, acc2, acc3;
+#endif
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (numTaps - 1U);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 samples at a time */
+ blkCnt = outBlockSize >> 2U;
+
+ /* Samples loop unrolled by 4 */
+ while (blkCnt > 0U)
+ {
+ /* Copy 4 * decimation factor number of new input samples into the state buffer */
+ i = S->M * 4;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+ px2 = pState + 2 * S->M;
+ px3 = pState + 3 * S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample for acc0 */
+ x0 = *(px0++);
+ /* Read x[n-numTaps-1] sample for acc1 */
+ x1 = *(px1++);
+ /* Read x[n-numTaps-1] sample for acc2 */
+ x2 = *(px2++);
+ /* Read x[n-numTaps-1] sample for acc3 */
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch state variables for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 4;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+ *pDst++ = (q31_t) (acc1 << 1);
+ *pDst++ = (q31_t) (acc2 << 1);
+ *pDst++ = (q31_t) (acc3 << 1);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining samples */
+ blkCnt = outBlockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = outBlockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x04U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR_decimate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
index 000000000..9382f099d
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,105 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_decimate_init_f32.c
+ * Description: Floating-point FIR Decimator initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_decimate
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point FIR decimator.
+ @param[in,out] S points to an instance of the floating-point FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par
+ pState points to the array of state variables.
+ pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().
+ M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if ((blockSize % M) != 0U)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation Factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ @} end of FIR_decimate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
index 000000000..f583a037d
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_decimate_init_q15.c
+ * Description: Initialization function for the Q15 FIR Decimator
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_decimate
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q15 FIR decimator.
+ @param[in,out] S points to an instance of the Q15 FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par
+ pState points to the array of state variables.
+ pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples
+ to the call arm_fir_decimate_q15().
+ M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if ((blockSize % M) != 0U)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation Factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ @} end of FIR_decimate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
index 000000000..5ee69c6e1
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,105 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_decimate_init_q31.c
+ * Description: Initialization function for Q31 FIR Decimation filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_decimate
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q31 FIR decimator.
+ @param[in,out] S points to an instance of the Q31 FIR decimator structure
+ @param[in] numTaps number of coefficients in the filter
+ @param[in] M decimation factor
+ @param[in] pCoeffs points to the filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par
+ pState points to the array of state variables.
+ pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().
+ M is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if ((blockSize % M) != 0U)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation Factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ @} end of FIR_decimate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
index 000000000..f9d92c0f2
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,595 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_decimate_q15.c
+ * Description: Q15 FIR Decimator
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_decimate
+ @{
+ */
+
+/**
+ @brief Processing function for the Q15 FIR decimator.
+ @param[in] S points to an instance of the Q15 FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of input samples to process per call
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+
+ @remark
+ Refer to \ref arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function.
+ */
+
+#if defined (ARM_MATH_DSP)
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCur; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ const q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ q63_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t c1; /* Temporary variables to hold state and coefficient values */
+#endif
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (numTaps - 1U);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while (blkCnt > 0U)
+ {
+ /* Copy 2 * decimation factor number of new input samples into the state buffer */
+ i = S->M * 2;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = read_q15x2_ia (&px0);
+ x1 = read_q15x2_ia (&px1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = read_q15x2_ia (&px0);
+ x1 = read_q15x2_ia (&px1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch state variables for acc0, acc1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ while (blkCntN3 > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2] sample */
+ x0 = read_q15x2_ia (&px);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficients */
+ c1 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c0, sum0);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = read_q15x2_ia (&px);
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c1, sum0);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c0, sum0);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+ i = (numTaps - 1U) >> 2U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState));
+ write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState));
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1U) % 0x04U;
+
+ /* Copy data */
+ while (i > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+}
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCur; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ const q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ q63_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (numTaps - 1U);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while (blkCnt > 0U)
+ {
+ /* Copy 2 * decimation factor number of new input samples into the state buffer */
+ i = S->M * 2;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+ px1 = pState + S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ while (blkCntN3 > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+ i = (numTaps - 1U) >> 2U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1U) % 0x04U;
+
+ /* copy data */
+ while (i > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+}
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+/**
+ @} end of FIR_decimate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
index 000000000..7af8a44e2
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,387 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_decimate_q31.c
+ * Description: Q31 FIR Decimator
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_decimate
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 FIR decimator.
+ @param[in] S points to an instance of the Q31 FIR decimator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+
+ @remark
+ Refer to \ref arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function.
+ */
+
+void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCur; /* Points to the current sample of the state */
+ q31_t *px0; /* Temporary pointer for state buffer */
+ const q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t acc0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t *px1, *px2, *px3;
+ q31_t x1, x2, x3;
+ q63_t acc1, acc2, acc3;
+#endif
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (numTaps - 1U);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 samples at a time */
+ blkCnt = outBlockSize >> 2U;
+
+ /* Samples loop unrolled by 4 */
+ while (blkCnt > 0U)
+ {
+ /* Copy 4 * decimation factor number of new input samples into the state buffer */
+ i = S->M * 4;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+ px2 = pState + 2 * S->M;
+ px3 = pState + 3 * S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample for acc0 */
+ x0 = *(px0++);
+ /* Read x[n-numTaps-1] sample for acc1 */
+ x1 = *(px1++);
+ /* Read x[n-numTaps-1] sample for acc2 */
+ x2 = *(px2++);
+ /* Read x[n-numTaps-1] sample for acc3 */
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch state variables for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 4;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 >> 31);
+ *pDst++ = (q31_t) (acc1 >> 31);
+ *pDst++ = (q31_t) (acc2 >> 31);
+ *pDst++ = (q31_t) (acc3 >> 31);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining samples */
+ blkCnt = outBlockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = outBlockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCur++ = *pSrc++;
+
+ } while (--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 >> 31);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x04U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR_decimate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
index 000000000..5f8df9542
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,332 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_fast_q15.c
+ * Description: Q15 Fast FIR filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR
+ @{
+ */
+
+/**
+ @brief Processing function for the Q15 FIR filter (fast version).
+ @param[in] S points to an instance of the Q15 FIR filter structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This fast version uses a 32-bit accumulator with 2.30 format.
+ The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around and distorts the result.
+ In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+
+ @remark
+ Refer to \ref arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ Use function \ref arm_fir_init_q15() to initialize the filter structure.
+ */
+
+void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ const q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */
+#endif
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy 4 new input samples into the state buffer. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+ px = pState;
+
+ /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = read_q15x2_ia (&px);
+
+ /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+ x2 = read_q15x2_ia (&px);
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* pack x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = read_q15x2_ia (&px);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* Read state x[n-N-6], x[n-N-7] with offset */
+ x2 = read_q15x2_ia (&px);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ /* Decrement tap count */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ This is always be 2 taps since the filter length is even. */
+ if ((numTaps & 0x3U) != 0U)
+ {
+ /* Read last two coefficients */
+ c0 = read_q15x2_ia ((q15_t **) &pb);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read last state variables */
+ x0 = read_q15x2 (px);
+
+ /* Perform the multiply-accumulates */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* Perform the multiply-accumulates */
+ acc3 = __SMLADX(x1, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ Then store the 4 outputs in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16));
+ write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16));
+#else
+ write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16));
+ write_q15x2_ia (&pDst, __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining output samples */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of taps */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Use SIMD to hold states and coefficients */
+ px = pState;
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1U;
+
+ do
+ {
+ acc0 += (q31_t) *px++ * *pb++;
+ acc0 += (q31_t) *px++ * *pb++;
+
+ tapCnt--;
+ }
+ while (tapCnt > 0U);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy remaining data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
index 000000000..513cb7280
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,324 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_fast_q31.c
+ * Description: Processing function for the Q31 Fast FIR filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 FIR filter (fast version).
+ @param[in] S points to an instance of the Q31 structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ These intermediate results are added to a 2.30 accumulator.
+ Finally, the accumulator is saturated and converted to a 1.31 result.
+ The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+
+ @remark
+ Refer to \ref arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ Use function \ref arm_fir_init_q31() to initialize the filter structure.
+ */
+
+IAR_ONLY_LOW_OPTIMIZATION_ENTER
+void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *px; /* Temporary pointer for state buffer */
+ const q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+#endif
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy 4 new input samples into the state buffer. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first 3 samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ Repeat until we've computed numTaps-4 coefficients. */
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *pb;
+
+ /* Read x[n-numTaps-3] sample */
+ x3 = *px;
+
+ /* acc0 += b[numTaps] * x[n-numTaps] */
+ multAcc_32x32_keep32_R(acc0, x0, c0);
+
+ /* acc1 += b[numTaps] * x[n-numTaps-1] */
+ multAcc_32x32_keep32_R(acc1, x1, c0);
+
+ /* acc2 += b[numTaps] * x[n-numTaps-2] */
+ multAcc_32x32_keep32_R(acc2, x2, c0);
+
+ /* acc3 += b[numTaps] * x[n-numTaps-3] */
+ multAcc_32x32_keep32_R(acc3, x3, c0);
+
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb + 1U);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px + 1U);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x1, c0);
+ multAcc_32x32_keep32_R(acc1, x2, c0);
+ multAcc_32x32_keep32_R(acc2, x3, c0);
+ multAcc_32x32_keep32_R(acc3, x0, c0);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb + 2U);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px + 2U);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x2, c0);
+ multAcc_32x32_keep32_R(acc1, x3, c0);
+ multAcc_32x32_keep32_R(acc2, x0, c0);
+ multAcc_32x32_keep32_R(acc3, x1, c0);
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *(pb + 3U);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px + 3U);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x3, c0);
+ multAcc_32x32_keep32_R(acc1, x0, c0);
+ multAcc_32x32_keep32_R(acc2, x1, c0);
+ multAcc_32x32_keep32_R(acc3, x2, c0);
+
+ /* update coefficient pointer */
+ pb += 4U;
+ px += 4U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x0, c0);
+ multAcc_32x32_keep32_R(acc1, x1, c0);
+ multAcc_32x32_keep32_R(acc2, x2, c0);
+ multAcc_32x32_keep32_R(acc3, x3, c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31
+ Then store the 4 outputs in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+ *pDst++ = (q31_t) (acc1 << 1);
+ *pDst++ = (q31_t) (acc2 << 1);
+ *pDst++ = (q31_t) (acc3 << 1);
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining output samples */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of taps */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ multAcc_32x32_keep32_R(acc0, (*px++), (*pb++));
+ i--;
+ } while (i > 0U);
+
+ /* The result is in 2.30 format. Convert to 1.31
+ Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy remaining data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+IAR_ONLY_LOW_OPTIMIZATION_EXIT
+/**
+ @} end of FIR group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
index 000000000..f96d25090
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,81 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_init_q7.c
+ * Description: Q7 FIR filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q7 FIR filter.
+ @param[in,out] S points to an instance of the Q7 FIR filter structure
+ @param[in] numTaps number of filter coefficients in the filter
+ @param[in] pCoeffs points to the filter coefficients buffer
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of samples processed
+ @return none
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par
+ pState points to the array of state variables.
+ pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().
+ */
+
+void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q7_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of FIR group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
index 000000000..ee0ed270f
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,914 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_interpolate_f32.c
+ * Description: Floating-point FIR interpolation sequences
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator
+
+ These functions combine an upsampler (zero stuffer) and an FIR filter.
+ They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.
+ Conceptually, the functions are equivalent to the block diagram below:
+ \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"
+ After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized
+ cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.
+ The user of the function is responsible for providing the filter coefficients.
+
+ The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.
+ The upsampler inserts L-1 zeros between each sample.
+ Instead of multiplying by these zero values, the FIR filter is designed to skip them.
+ This leads to an efficient implementation without any wasted effort.
+ The functions operate on blocks of input and output data.
+ pSrc points to an array of blockSize input values and
+ pDst points to an array of blockSize*L output values.
+
+ The library provides separate functions for Q15, Q31, and floating-point data types.
+
+ @par Algorithm
+ The functions use a polyphase filter structure:
+
+ y[n] = b[0] * x[n] + b[L] * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+ y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+ ...
+ y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+
+ This approach is more efficient than straightforward upsample-then-filter algorithms.
+ With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.
+ @par
+ pCoeffs points to a coefficient array of size numTaps.
+ numTaps must be a multiple of the interpolation factor L and this is checked by the
+ initialization functions.
+ Internally, the function divides the FIR filter's impulse response into shorter filters of length
+ phaseLength=numTaps/L.
+ Coefficients are stored in time reversed order.
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par
+ pState points to a state array of size blockSize + phaseLength - 1.
+ Samples in the state buffer are stored in the order:
+
+ {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par
+ The state variables are updated after each block of data is processed, the coefficients are untouched.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter.
+ Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ There are separate instance structure declarations for each of the 3 supported data types.
+
+ @par Initialization Functions
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ - Checks to make sure that the length of the filter is a multiple of the interpolation factor.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero.
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ The code below statically initializes each of the 3 different data type filter instance structures
+
+ arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+ arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+ arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+
+ @par
+ where L is the interpolation factor; phaseLength=numTaps/L is the
+ length of each of the shorter FIR filters used internally,
+ pCoeffs is the address of the coefficient buffer;
+ pState is the address of the state buffer.
+ Be sure to set the values in the state buffer to zeros when doing static initialization.
+
+ @par Fixed-Point Behavior
+ Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.
+ In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ @addtogroup FIR_Interpolate
+ @{
+ */
+
+/**
+ @brief Processing function for floating-point FIR interpolator.
+ @param[in] S points to an instance of the floating-point FIR interpolator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+#if defined(ARM_MATH_NEON)
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *ptr1; /* Temporary pointers for state buffer */
+ const float32_t *ptr2; /* Temporary pointers for coefficient buffer */
+ float32_t sum0; /* Accumulators */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x1, x2, x3;
+ uint32_t blkCntN4;
+ float32_t c1, c2, c3;
+
+ float32x4_t sum0v;
+ float32x4_t accV,accV0,accV1;
+ float32x4_t x0v,x1v,x2v,xa,xb;
+ uint32x4_t x0v_u,x1v_u,x2v_u,xa_u,xb_u;
+ float32x2_t tempV;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1U);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize >> 3;
+ blkCntN4 = blockSize & 7;
+
+ /* Loop unrolling */
+ while (blkCnt > 0U)
+ {
+ /* Copy new input samples into the state buffer */
+ sum0v = vld1q_f32(pSrc);
+ vst1q_f32(pStateCurnt,sum0v);
+ pSrc += 4;
+ pStateCurnt += 4;
+
+ sum0v = vld1q_f32(pSrc);
+ vst1q_f32(pStateCurnt,sum0v);
+ pSrc += 4;
+ pStateCurnt += 4;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1U;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ accV0 = vdupq_n_f32(0.0);
+ accV1 = vdupq_n_f32(0.0);
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2U;
+
+ x0v = vld1q_f32(ptr1);
+ x1v = vld1q_f32(ptr1 + 4);
+
+ while (tapCnt > 0U)
+ {
+ /* Read the input samples */
+ x2v = vld1q_f32(ptr1 + 8);
+
+ /* Read the coefficients */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ accV0 = vmlaq_n_f32(accV0,x0v,c0);
+ accV1 = vmlaq_n_f32(accV1,x1v,c0);
+
+ /* Read the coefficients, inputs and perform multiply-accumulate */
+ c1 = *(ptr2 + S->L);
+
+ xa = vextq_f32(x0v,x1v,1);
+ xb = vextq_f32(x1v,x2v,1);
+
+ accV0 = vmlaq_n_f32(accV0,xa,c1);
+ accV1 = vmlaq_n_f32(accV1,xb,c1);
+
+ /* Read the coefficients, inputs and perform multiply-accumulate */
+ c2 = *(ptr2 + S->L * 2);
+
+ xa = vextq_f32(x0v,x1v,2);
+ xb = vextq_f32(x1v,x2v,2);
+
+ accV0 = vmlaq_n_f32(accV0,xa,c2);
+ accV1 = vmlaq_n_f32(accV1,xb,c2);
+
+ /* Read the coefficients, inputs and perform multiply-accumulate */
+ c3 = *(ptr2 + S->L * 3);
+
+ xa = vextq_f32(x0v,x1v,3);
+ xb = vextq_f32(x1v,x2v,3);
+
+ accV0 = vmlaq_n_f32(accV0,xa,c3);
+ accV1 = vmlaq_n_f32(accV1,xb,c3);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+ ptr1 += 4;
+ x0v = x1v;
+ x1v = x2v;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4U;
+
+ x2v = vld1q_f32(ptr1 + 8);
+
+ switch (tapCnt)
+ {
+ case 3:
+ c0 = *(ptr2);
+ accV0 = vmlaq_n_f32(accV0,x0v,c0);
+ accV1 = vmlaq_n_f32(accV1,x1v,c0);
+ ptr2 += S->L;
+
+ c0 = *(ptr2);
+
+ xa = vextq_f32(x0v,x1v,1);
+ xb = vextq_f32(x1v,x2v,1);
+
+ accV0 = vmlaq_n_f32(accV0,xa,c0);
+ accV1 = vmlaq_n_f32(accV1,xb,c0);
+ ptr2 += S->L;
+
+ c0 = *(ptr2);
+
+ xa = vextq_f32(x0v,x1v,2);
+ xb = vextq_f32(x1v,x2v,2);
+
+ accV0 = vmlaq_n_f32(accV0,xa,c0);
+ accV1 = vmlaq_n_f32(accV1,xb,c0);
+ ptr2 += S->L;
+
+ break;
+
+ case 2:
+ c0 = *(ptr2);
+ accV0 = vmlaq_n_f32(accV0,x0v,c0);
+ accV1 = vmlaq_n_f32(accV1,x1v,c0);
+ ptr2 += S->L;
+
+ c0 = *(ptr2);
+
+ xa = vextq_f32(x0v,x1v,1);
+ xb = vextq_f32(x1v,x2v,1);
+
+ accV0 = vmlaq_n_f32(accV0,xa,c0);
+ accV1 = vmlaq_n_f32(accV1,xb,c0);
+ ptr2 += S->L;
+
+ break;
+
+ case 1:
+ c0 = *(ptr2);
+ accV0 = vmlaq_n_f32(accV0,x0v,c0);
+ accV1 = vmlaq_n_f32(accV1,x1v,c0);
+ ptr2 += S->L;
+
+ break;
+
+ default:
+ break;
+
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = accV0[0];
+ *(pDst + S->L) = accV0[1];
+ *(pDst + 2 * S->L) = accV0[2];
+ *(pDst + 3 * S->L) = accV0[3];
+
+ *(pDst + 4 * S->L) = accV1[0];
+ *(pDst + 5 * S->L) = accV1[1];
+ *(pDst + 6 * S->L) = accV1[2];
+ *(pDst + 7 * S->L) = accV1[3];
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 8;
+
+ pDst += S->L * 7;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ while (blkCntN4 > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1U;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum0v = vdupq_n_f32(0.0);
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the coefficient */
+ x1v[0] = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0v = vld1q_f32(ptr1);
+ ptr1 += 4;
+
+ /* Read the coefficient */
+ x1v[1] = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the coefficient */
+ x1v[2] = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the coefficient */
+ x1v[3] = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ sum0v = vmlaq_f32(sum0v,x0v,x1v);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tempV = vpadd_f32(vget_low_f32(sum0v),vget_high_f32(sum0v));
+ sum0 = tempV[0] + tempV[1];
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += *(ptr1++) * (*ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCntN4--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (phaseLen - 1U) >> 2U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ sum0v = vld1q_f32(pState);
+ vst1q_f32(pStateCurnt,sum0v);
+ pState += 4;
+ pStateCurnt += 4;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (phaseLen - 1U) % 0x04U;
+
+ /* copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+#else
+
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+ float32_t *pState = S->pState; /* State pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCur; /* Points to the current sample of the state */
+ float32_t *ptr1; /* Temporary pointer for state buffer */
+ const float32_t *ptr2; /* Temporary pointer for coefficient buffer */
+ float32_t sum0; /* Accumulators */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+ uint32_t j;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x0, x1, x2, x3;
+ float32_t c0, c1, c2, c3;
+#endif
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (phaseLen - 1U);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1U;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2U;
+
+ x0 = *(ptr1++);
+ x1 = *(ptr1++);
+ x2 = *(ptr1++);
+
+ while (tapCnt > 0U)
+ {
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the coefficient */
+ c1 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x1 * c1;
+ acc1 += x2 * c1;
+ acc2 += x3 * c1;
+ acc3 += x0 * c1;
+
+ /* Read the coefficient */
+ c2 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x2 * c2;
+ acc1 += x3 * c2;
+ acc2 += x0 * c2;
+ acc3 += x1 * c2;
+
+ /* Read the coefficient */
+ c3 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x2 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x3 * c3;
+ acc1 += x0 * c3;
+ acc2 += x1 * c3;
+ acc3 += x2 * c3;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *(pDst ) = acc0;
+ *(pDst + S->L) = acc1;
+ *(pDst + 2 * S->L) = acc2;
+ *(pDst + 3 * S->L) = acc3;
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 4;
+
+ pDst += S->L * 3;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1U;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length.
+ Repeat until we've computed numTaps-(4*S->L) coefficients. */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ tapCnt = phaseLen >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += *ptr1++ * *ptr2;
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ sum0 += *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ sum0 += *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ sum0 += *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ tapCnt = phaseLen % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = phaseLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += *ptr1++ * *ptr2;
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ tapCnt = (phaseLen - 1U) >> 2U;
+
+ /* copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ tapCnt = (phaseLen - 1U) % 0x04U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (phaseLen - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ float32_t *pState = S->pState; /* State pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCur; /* Points to the current sample of the state */
+ float32_t *ptr1; /* Temporary pointer for state buffer */
+ const float32_t *ptr2; /* Temporary pointer for coefficient buffer */
+ float32_t sum0; /* Accumulators */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (phaseLen - 1U);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1U);
+
+ /* Loop over the polyPhase length */
+ tapCnt = phaseLen;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += *ptr1++ * *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+ tapCnt = phaseLen - 1U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of FIR_Interpolate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
index 000000000..287d3471b
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_interpolate_init_f32.c
+ * Description: Floating-point FIR interpolator initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Interpolate
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point FIR interpolator.
+ @param[in,out] S points to an instance of the floating-point FIR interpolator structure
+ @param[in] L upsample factor
+ @param[in] numTaps number of filter coefficients in the filter
+ @param[in] pCoeffs points to the filter coefficient buffer
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ @par
+ The length of the filter numTaps must be a multiple of the interpolation factor L.
+ @par
+ pState points to the array of state variables.
+ pState is of length (numTaps/L)+blockSize-1 words
+ where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if ((numTaps % L) != 0U)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+}
+
+/**
+ @} end of FIR_Interpolate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
index 000000000..7f43bbfa0
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_interpolate_init_q15.c
+ * Description: Q15 FIR interpolator initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Interpolate
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q15 FIR interpolator.
+ @param[in,out] S points to an instance of the Q15 FIR interpolator structure
+ @param[in] L upsample factor
+ @param[in] numTaps number of filter coefficients in the filter
+ @param[in] pCoeffs points to the filter coefficient buffer
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L
+
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L.
+ @par
+ pState points to the array of state variables.
+ pState is of length (numTaps/L)+blockSize-1 words
+ where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if ((numTaps % L) != 0U)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+}
+
+/**
+ @} end of FIR_Interpolate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
index 000000000..973e71594
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,105 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_interpolate_init_q31.c
+ * Description: Q31 FIR interpolator initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Interpolate
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q31 FIR interpolator.
+ @param[in,out] S points to an instance of the Q31 FIR interpolator structure
+ @param[in] L upsample factor
+ @param[in] numTaps number of filter coefficients in the filter
+ @param[in] pCoeffs points to the filter coefficient buffer
+ @param[in] pState points to the state buffer
+ @param[in] blockSize number of input samples to process per call
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : filter length numTaps is not a multiple of the interpolation factor L
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+
+ The length of the filter numTaps must be a multiple of the interpolation factor L.
+ @par
+ pState points to the array of state variables.
+ pState is of length (numTaps/L)+blockSize-1 words
+ where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if ((numTaps % L) != 0U)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0, (blockSize + ((uint32_t) S->phaseLength - 1U)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+}
+
+/**
+ @} end of FIR_Interpolate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
index 000000000..7efec9420
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,479 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_interpolate_q15.c
+ * Description: Q15 FIR interpolation
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Interpolate
+ @{
+ */
+
+/**
+ @brief Processing function for the Q15 FIR interpolator.
+ @param[in] S points to an instance of the Q15 FIR interpolator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCur; /* Points to the current sample of the state */
+ q15_t *ptr1; /* Temporary pointer for state buffer */
+ const q15_t *ptr2; /* Temporary pointer for coefficient buffer */
+ q63_t sum0; /* Accumulators */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+ uint32_t j;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q63_t acc0, acc1, acc2, acc3;
+ q15_t x0, x1, x2, x3;
+ q15_t c0, c1, c2, c3;
+#endif
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (phaseLen - 1U);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1U;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2U;
+
+ x0 = *(ptr1++);
+ x1 = *(ptr1++);
+ x2 = *(ptr1++);
+
+ while (tapCnt > 0U)
+ {
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Read the coefficient */
+ c1 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 * c1;
+ acc1 += (q63_t) x2 * c1;
+ acc2 += (q63_t) x3 * c1;
+ acc3 += (q63_t) x0 * c1;
+
+ /* Read the coefficient */
+ c2 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x2 * c2;
+ acc1 += (q63_t) x3 * c2;
+ acc2 += (q63_t) x0 * c2;
+ acc3 += (q63_t) x1 * c2;
+
+ /* Read the coefficient */
+ c3 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x2 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x3 * c3;
+ acc1 += (q63_t) x0 * c3;
+ acc2 += (q63_t) x1 * c3;
+ acc3 += (q63_t) x2 * c3;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *(pDst ) = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
+ *(pDst + 2 * S->L) = (q15_t) (__SSAT((acc2 >> 15), 16));
+ *(pDst + 3 * S->L) = (q15_t) (__SSAT((acc3 >> 15), 16));
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 4;
+
+ pDst += S->L * 3;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1U;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length.
+ Repeat until we've computed numTaps-(4*S->L) coefficients. */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ tapCnt = phaseLen >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ tapCnt = phaseLen % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = phaseLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ tapCnt = (phaseLen - 1U) >> 2U;
+
+ /* copy data */
+ while (tapCnt > 0U)
+ {
+ write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState));
+ write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState));
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ tapCnt = (phaseLen - 1U) % 0x04U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (phaseLen - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCur; /* Points to the current sample of the state */
+ q15_t *ptr1; /* Temporary pointer for state buffer */
+ const q15_t *ptr2; /* Temporary pointer for coefficient buffer */
+ q63_t sum0; /* Accumulators */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (phaseLen - 1U);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1U);
+
+ /* Loop over the polyPhase length */
+ tapCnt = phaseLen;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += ((q63_t) *ptr1++ * *ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Store the result after converting to 1.15 format in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+ tapCnt = phaseLen - 1U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of FIR_Interpolate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
index 000000000..d6a8ca33a
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,481 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_interpolate_q31.c
+ * Description: Q31 FIR interpolation
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Interpolate
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 FIR interpolator.
+ @param[in] S points to an instance of the Q31 FIR interpolator structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).
+ since numTaps/L additions occur per output sample.
+ After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+ q31_t *pState = S->pState; /* State pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCur; /* Points to the current sample of the state */
+ q31_t *ptr1; /* Temporary pointer for state buffer */
+ const q31_t *ptr2; /* Temporary pointer for coefficient buffer */
+ q63_t sum0; /* Accumulators */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+ uint32_t j;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q63_t acc0, acc1, acc2, acc3;
+ q31_t x0, x1, x2, x3;
+ q31_t c0, c1, c2, c3;
+#endif
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (phaseLen - 1U);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+ *pStateCur++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1U;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2U;
+
+ x0 = *(ptr1++);
+ x1 = *(ptr1++);
+ x2 = *(ptr1++);
+
+ while (tapCnt > 0U)
+ {
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Read the coefficient */
+ c1 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 * c1;
+ acc1 += (q63_t) x2 * c1;
+ acc2 += (q63_t) x3 * c1;
+ acc3 += (q63_t) x0 * c1;
+
+ /* Read the coefficient */
+ c2 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x2 * c2;
+ acc1 += (q63_t) x3 * c2;
+ acc2 += (q63_t) x0 * c2;
+ acc3 += (q63_t) x1 * c2;
+
+ /* Read the coefficient */
+ c3 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x2 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x3 * c3;
+ acc1 += (q63_t) x0 * c3;
+ acc2 += (q63_t) x1 * c3;
+ acc3 += (q63_t) x2 * c3;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 * c0;
+ acc1 += (q63_t) x1 * c0;
+ acc2 += (q63_t) x2 * c0;
+ acc3 += (q63_t) x3 * c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *(pDst ) = (q31_t) (acc0 >> 31);
+ *(pDst + S->L) = (q31_t) (acc1 >> 31);
+ *(pDst + 2 * S->L) = (q31_t) (acc2 >> 31);
+ *(pDst + 3 * S->L) = (q31_t) (acc3 >> 31);
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 4;
+
+ pDst += S->L * 3;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1U;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length.
+ Repeat until we've computed numTaps-(4*S->L) coefficients. */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ tapCnt = phaseLen >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+ ptr2 += S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ tapCnt = phaseLen % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = phaseLen;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) *ptr1++ * *ptr2;
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ tapCnt = (phaseLen - 1U) >> 2U;
+
+ /* copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ tapCnt = (phaseLen - 1U) % 0x04U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (phaseLen - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ q31_t *pState = S->pState; /* State pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCur; /* Points to the current sample of the state */
+ q31_t *ptr1; /* Temporary pointer for state buffer */
+ const q31_t *ptr2; /* Temporary pointer for coefficient buffer */
+ q63_t sum0; /* Accumulators */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint32_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCur points to the location where the new input data should be written */
+ pStateCur = S->pState + (phaseLen - 1U);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while (blkCnt > 0U)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCur++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while (i > 0U)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1U);
+
+ /* Loop over the polyPhase length */
+ tapCnt = phaseLen;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += ((q63_t) *ptr1++ * *ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Decrement loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCur = S->pState;
+
+ tapCnt = phaseLen - 1U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of FIR_Interpolate group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
index 000000000..a3d95c1ae
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,453 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_lattice_f32.c
+ * Description: Processing function for floating-point FIR Lattice filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters
+
+ This set of functions implements Finite Impulse Response (FIR) lattice filters
+ for Q15, Q31 and floating-point data types. Lattice filters are used in a
+ variety of adaptive filter applications. The filter structure is feedforward and
+ the net impulse response is finite length.
+ The functions operate on blocks
+ of input and output data and each call to the function processes
+ blockSize samples through the filter. pSrc and
+ pDst point to input and output arrays containing blockSize values.
+
+ @par Algorithm
+ \image html FIRLattice.gif "Finite Impulse Response Lattice filter"
+ The following difference equation is implemented:
+ @par
+
+ f0[n] = g0[n] = x[n]
+ fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+ gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+ y[n] = fM[n]
+
+ @par
+ pCoeffs points to tha array of reflection coefficients of size numStages.
+ Reflection Coefficients are stored in the following order.
+ @par
+
+ {k1, k2, ..., kM}
+
+ where M is number of stages
+ @par
+ pState points to a state array of size numStages.
+ The state variables (g values) hold previous inputs and are stored in the following order.
+
+ {g0[n], g1[n], g2[n] ...gM-1[n]}
+
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter.
+ Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ There are separate instance structure declarations for each of the 3 supported data types.
+
+ @par Initialization Functions
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+
+ arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+ arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+ arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+
+ @par
+ where numStages is the number of stages in the filter;
+ pState is the address of the state buffer;
+ pCoeffs is the address of the coefficient buffer.
+
+ @par Fixed-Point Behavior
+ Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.
+ In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ @addtogroup FIR_Lattice
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point FIR lattice filter.
+ @param[in] S points to an instance of the floating-point FIR lattice structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* Temporary state pointer */
+ const float32_t *pk; /* Temporary coefficient pointer */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* Loop counters */
+ float32_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ float32_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */
+ float32_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */
+ float32_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */
+#endif
+
+ gcurr0 = 0.0f;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurr0 = *pSrc++;
+ fcurr1 = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* Read g0(n-1) from state buffer */
+ gcurr0 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (gcurr0 * (*pk)) + fcurr0;
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext0 = (fcurr0 * (*pk)) + gcurr0;
+
+ /* Process second sample for first tap */
+ fnext1 = (fcurr0 * (*pk)) + fcurr1;
+ gnext1 = (fcurr1 * (*pk)) + fcurr0;
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurr2 = *pSrc++;
+ fcurr3 = *pSrc++;
+
+ /* Process third sample for first tap */
+ fnext2 = (fcurr1 * (*pk)) + fcurr2;
+ gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+ /* Process fourth sample for first tap */
+ fnext3 = (fcurr2 * (*pk )) + fcurr3;
+ gnext3 = (fcurr3 * (*pk++)) + fcurr2;
+
+ /* Copy only last input sample into the state buffer
+ which will be used for next samples processing */
+ *px++ = fcurr3;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr0 = fnext0;
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1U) >> 2U;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while (stageCnt > 0U)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext3;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext0 = (gcurr0 * (*pk)) + fcurr0;
+
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext1 = (gnext0 * (*pk)) + fcurr1;
+
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext2 = (gnext1 * (*pk)) + fcurr2;
+
+ /* Process fourth sample for 2nd, 6th .. tap */
+ fnext3 = (gnext2 * (*pk)) + fcurr3;
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ /* Calculation of state values for next stage */
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+
+ gnext1 = (fcurr1 * (*pk)) + gnext0;
+
+ gnext0 = (fcurr0 * (*pk++)) + gcurr0;
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g2(n) in state buffer */
+ *px++ = gnext3;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurr0 = (gcurr0 * (*pk)) + fnext0;
+
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurr1 = (gnext0 * (*pk)) + fnext1;
+
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurr2 = (gnext1 * (*pk)) + fnext2;
+
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurr3 = (gnext2 * (*pk)) + fnext3;
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext3 = (fnext3 * (*pk)) + gnext2;
+
+ gnext2 = (fnext2 * (*pk)) + gnext1;
+
+ gnext1 = (fnext1 * (*pk)) + gnext0;
+
+ gnext0 = (fnext0 * (*pk++)) + gcurr0;
+
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g3(n) in state buffer */
+ *px++ = gnext3;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext0 = (gcurr0 * (*pk)) + fcurr0;
+
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext1 = (gnext0 * (*pk)) + fcurr1;
+
+ /* Process third sample for 4th, 8th .. tap */
+ fnext2 = (gnext1 * (*pk)) + fcurr2;
+
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext3 = (gnext2 * (*pk)) + fcurr3;
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+
+ gnext1 = (fcurr1 * (*pk)) + gnext0;
+
+ gnext0 = (fcurr0 * (*pk++)) + gcurr0;
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = gnext3;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurr0 = (gcurr0 * (*pk)) + fnext0;
+
+ /* Process second sample for 5th, 9th .. tap */
+ fcurr1 = (gnext0 * (*pk)) + fnext1;
+
+ /* Process third sample for 5th, 9th .. tap */
+ fcurr2 = (gnext1 * (*pk)) + fnext2;
+
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurr3 = (gnext2 * (*pk)) + fnext3;
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext3 = (fnext3 * (*pk)) + gnext2;
+
+ gnext2 = (fnext2 * (*pk)) + gnext1;
+
+ gnext1 = (fnext1 * (*pk)) + gnext0;
+
+ gnext0 = (fnext0 * (*pk++)) + gcurr0;
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1U) % 0x4U;
+
+ while (stageCnt > 0U)
+ {
+ gcurr0 = *px;
+
+ /* save g value in state buffer */
+ *px++ = gnext3;
+
+ /* Process four samples for last three taps here */
+ fnext0 = (gcurr0 * (*pk)) + fcurr0;
+
+ fnext1 = (gnext0 * (*pk)) + fcurr1;
+
+ fnext2 = (gnext1 * (*pk)) + fcurr2;
+
+ fnext3 = (gnext2 * (*pk)) + fcurr3;
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+
+ gnext1 = (fcurr1 * (*pk)) + gnext0;
+
+ gnext0 = (fcurr0 * (*pk++)) + gcurr0;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr0 = fnext0;
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+
+ stageCnt--;
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr0;
+ *pDst++ = fcurr1;
+ *pDst++ = fcurr2;
+ *pDst++ = fcurr3;
+
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* f0(n) = x(n) */
+ fcurr0 = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* read g2(n) from state buffer */
+ gcurr0 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (gcurr0 * (*pk)) + fcurr0;
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext0 = (fcurr0 * (*pk++)) + gcurr0;
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr0;
+
+ /* f1(n) is saved in fcurr0 for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt = (numStages - 1U);
+
+ /* stage loop */
+ while (stageCnt > 0U)
+ {
+ /* read g2(n) from state buffer */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext0;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext0 = (gcurr0 * (*pk)) + fcurr0;
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext0 = (fcurr0 * (*pk++)) + gcurr0;
+
+ /* f1(n) is saved in fcurr0 for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt--;
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr0;
+
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
index 000000000..7929629a4
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,70 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_lattice_init_f32.c
+ * Description: Floating-point FIR Lattice filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Lattice
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point FIR lattice filter.
+ @param[in] S points to an instance of the floating-point FIR lattice structure
+ @param[in] numStages number of filter stages
+ @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages
+ @param[in] pState points to the state buffer. The array is of length numStages
+ @return none
+ */
+
+void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ const float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of FIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
index 000000000..5c80dff60
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,70 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_lattice_init_q15.c
+ * Description: Q15 FIR Lattice filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Lattice
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q15 FIR lattice filter.
+ @param[in] S points to an instance of the Q15 FIR lattice structure
+ @param[in] numStages number of filter stages
+ @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages
+ @param[in] pState points to the state buffer. The array is of length numStages
+ @return none
+ */
+
+void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ const q15_t * pCoeffs,
+ q15_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of FIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
index 000000000..476296d60
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,70 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_lattice_init_q31.c
+ * Description: Q31 FIR lattice filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Lattice
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q31 FIR lattice filter.
+ @param[in] S points to an instance of the Q31 FIR lattice structure
+ @param[in] numStages number of filter stages
+ @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages
+ @param[in] pState points to the state buffer. The array is of length numStages
+ @return none
+ */
+
+void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ const q31_t * pCoeffs,
+ q31_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of FIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
index 000000000..42e7c0d48
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,506 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_lattice_q15.c
+ * Description: Q15 FIR lattice filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Lattice
+ @{
+ */
+
+/**
+ @brief Processing function for Q15 FIR lattice filter.
+ @param[in] S points to an instance of the Q15 FIR lattice structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* Temporary state pointer */
+ const q15_t *pk; /* Temporary coefficient pointer */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* Loop counters */
+ q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */
+
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */
+ q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */
+ q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */
+#endif
+
+ gcurr0 = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurr0 = *pSrc++;
+ fcurr1 = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* Read g0(n-1) from state buffer */
+ gcurr0 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0;
+ fnext0 = __SSAT(fnext0, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext0 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ /* Process second sample for first tap */
+ fnext1 = (q31_t) ((fcurr0 * (*pk)) >> 15U) + fcurr1;
+ fnext1 = __SSAT(fnext1, 16);
+ gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr0;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurr2 = *pSrc++;
+ fcurr3 = *pSrc++;
+
+ /* Process third sample for first tap */
+ fnext2 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + fcurr2;
+ fnext2 = __SSAT(fnext2, 16);
+ gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + fcurr1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ /* Process fourth sample for first tap */
+ fnext3 = (q31_t) ((fcurr2 * (*pk )) >> 15U) + fcurr3;
+ fnext3 = __SSAT(fnext3, 16);
+ gnext3 = (q31_t) ((fcurr3 * (*pk++)) >> 15U) + fcurr2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ /* Copy only last input sample into the state buffer
+ which will be used for next samples processing */
+ *px++ = (q15_t) fcurr3;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr0 = fnext0;
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1U) >> 2U;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while (stageCnt > 0U)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext3;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0;
+ fnext0 = __SSAT(fnext0, 16);
+
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ /* Process fourth sample for 2nd, 6th .. tap */
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ /* Calculation of state values for next stage */
+ gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0;
+ gnext1 = __SSAT(gnext1, 16);
+
+ gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext3;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0;
+ fcurr0 = __SSAT(fcurr0, 16);
+
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1;
+ fcurr1 = __SSAT(fcurr1, 16);
+
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2;
+ fcurr2 = __SSAT(fcurr2, 16);
+
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3;
+ fcurr3 = __SSAT(fcurr3, 16);
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0;
+ gnext1 = __SSAT(gnext1, 16);
+
+ gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext3;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0;
+ fnext0 = __SSAT(fnext0, 16);
+
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* Process third sample for 4th, 8th .. tap */
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0;
+ gnext1 = __SSAT(gnext1, 16);
+
+ gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = (q15_t) gnext3;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurr0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fnext0;
+ fcurr0 = __SSAT(fcurr0, 16);
+
+ /* Process second sample for 5th, 9th .. tap */
+ fcurr1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fnext1;
+ fcurr1 = __SSAT(fcurr1, 16);
+
+ /* Process third sample for 5th, 9th .. tap */
+ fcurr2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fnext2;
+ fcurr2 = __SSAT(fcurr2, 16);
+
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurr3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fnext3;
+ fcurr3 = __SSAT(fcurr3, 16);
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15U) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15U) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fnext1 * (*pk)) >> 15U) + gnext0;
+ gnext1 = __SSAT(gnext1, 16);
+
+ gnext0 = (q31_t) ((fnext0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1U) % 0x4U;
+
+ while (stageCnt > 0U)
+ {
+ gcurr0 = *px;
+
+ /* save g value in state buffer */
+ *px++ = (q15_t) gnext3;
+
+ /* Process four samples for last three taps here */
+ fnext0 = (q31_t) ((gcurr0 * (*pk)) >> 15U) + fcurr0;
+ fnext0 = __SSAT(fnext0, 16);
+
+ fnext1 = (q31_t) ((gnext0 * (*pk)) >> 15U) + fcurr1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15U) + fcurr2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15U) + fcurr3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext3 = (q31_t) ((fcurr3 * (*pk)) >> 15U) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurr2 * (*pk)) >> 15U) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fcurr1 * (*pk)) >> 15U) + gnext0;
+ gnext1 = __SSAT(gnext1, 16);
+
+ gnext0 = (q31_t) ((fcurr0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ /* Update of f values for next coefficient set processing */
+ fcurr0 = fnext0;
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+
+ stageCnt--;
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pDst, __PKHBT(fcurr0, fcurr1, 16));
+ write_q15x2_ia (&pDst, __PKHBT(fcurr2, fcurr3, 16));
+#else
+ write_q15x2_ia (&pDst, __PKHBT(fcurr1, fcurr0, 16));
+ write_q15x2_ia (&pDst, __PKHBT(fcurr3, fcurr2, 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* f0(n) = x(n) */
+ fcurr0 = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* read g2(n) from state buffer */
+ gcurr0 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0;
+ fnext0 = __SSAT(fnext0, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) fcurr0;
+
+ /* f1(n) is saved in fcurr0 for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt = (numStages - 1U);
+
+ /* stage loop */
+ while (stageCnt > 0U)
+ {
+ /* read g2(n) from state buffer */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext0;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext0 = (((q31_t) gcurr0 * (*pk)) >> 15U) + fcurr0;
+ fnext0 = __SSAT(fnext0, 16);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext0 = (((q31_t) fcurr0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ /* f1(n) is saved in fcurr0 for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt--;
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = __SSAT(fcurr0, 16);
+
+ blkCnt--;
+ }
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* f0(n) = x(n) */
+ fcurr0 = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* read g0(n-1) from state buffer */
+ gcurr0 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0;
+ fnext0 = __SSAT(fnext, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ /* save f0(n) in state buffer */
+ *px++ = (q15_t) fcurr0;
+
+ /* f1(n) is saved in fcurr for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt = (numStages - 1U);
+
+ /* stage loop */
+ while (stageCnt > 0U)
+ {
+ /* read g1(n-1) from state buffer */
+ gcurr0 = *px;
+
+ /* save g0(n-1) in state buffer */
+ *px++ = (q15_t) gnext0;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext0 = ((gcurr0 * (*pk)) >> 15U) + fcurr0;
+ fnext0 = __SSAT(fnext0, 16);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext0 = ((fcurr0 * (*pk++)) >> 15U) + gcurr0;
+ gnext0 = __SSAT(gnext0, 16);
+
+ /* f1(n) is saved in fcurr0 for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt--;
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = __SSAT(fcurr0, 16);
+
+ blkCnt--;
+ }
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of FIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
index 000000000..c8d28d7c7
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,505 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_lattice_q31.c
+ * Description: Q31 FIR lattice filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Lattice
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 FIR lattice filter.
+ @param[in] S points to an instance of the Q31 FIR lattice structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.
+ */
+
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* Temporary state pointer */
+ const q31_t *pk; /* Temporary coefficient pointer */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* Loop counters */
+ q31_t fcurr0, fnext0, gnext0, gcurr0; /* Temporary variables */
+
+#if (1)
+//#if !defined(ARM_MATH_CM0_FAMILY)
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t fcurr1, fnext1, gnext1; /* Temporary variables for second sample in loop unrolling */
+ q31_t fcurr2, fnext2, gnext2; /* Temporary variables for third sample in loop unrolling */
+ q31_t fcurr3, fnext3, gnext3; /* Temporary variables for fourth sample in loop unrolling */
+#endif
+
+ gcurr0 = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurr0 = *pSrc++;
+ fcurr1 = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* Read g0(n-1) from state buffer */
+ gcurr0 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fnext0 = (fnext0 << 1U) + fcurr0;
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ /* Process second sample for first tap */
+ fnext1 = (q31_t) (((q63_t) fcurr0 * (*pk)) >> 32U);
+ fnext1 = (fnext1 << 1U) + fcurr1;
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U);
+ gnext1 = (gnext1 << 1U) + fcurr0;
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurr2 = *pSrc++;
+ fcurr3 = *pSrc++;
+
+ /* Process third sample for first tap */
+ fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U);
+ fnext2 = (fnext2 << 1U) + fcurr2;
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U);
+ gnext2 = (gnext2 << 1U) + fcurr1;
+
+ /* Process fourth sample for first tap */
+ fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk )) >> 32U);
+ fnext3 = (fnext3 << 1U) + fcurr3;
+ gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk++)) >> 32U);
+ gnext3 = (gnext3 << 1U) + fcurr2;
+
+ /* Copy only last input sample into the state buffer
+ which will be used for next samples processing */
+ *px++ = fcurr3;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr0 = fnext0;
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1U) >> 2U;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while (stageCnt > 0U)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext3;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fnext0 = (fnext0 << 1U) + fcurr0;
+
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U);
+ fnext1 = (fnext1 << 1U) + fcurr1;
+
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U);
+ fnext2 = (fnext2 << 1U) + fcurr2;
+
+ /* Process fourth sample for 2nd, 6th .. tap */
+ fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U);
+ fnext3 = (fnext3 << 1U) + fcurr3;
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ /* Calculation of state values for next stage */
+ gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U);
+ gnext3 = (gnext3 << 1U) + gnext2;
+
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U);
+ gnext2 = (gnext2 << 1U) + gnext1;
+
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U);
+ gnext1 = (gnext1 << 1U) + gnext0;
+
+ gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext3;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fcurr0 = (fcurr0 << 1U) + fnext0;
+
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U);
+ fcurr1 = (fcurr1 << 1U) + fnext1;
+
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U);
+ fcurr2 = (fcurr2 << 1U) + fnext2;
+
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U);
+ fcurr3 = (fcurr3 << 1U) + fnext3;
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U);
+ gnext3 = (gnext3 << 1U) + gnext2;
+
+ gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U);
+ gnext2 = (gnext2 << 1U) + gnext1;
+
+ gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U);
+ gnext1 = (gnext1 << 1U) + gnext0;
+
+ gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext3;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fnext0 = (fnext0 << 1U) + fcurr0;
+
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U);
+ fnext1 = (fnext1 << 1U) + fcurr1;
+
+ /* Process third sample for 4th, 8th .. tap */
+ fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U);
+ fnext2 = (fnext2 << 1U) + fcurr2;
+
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U);
+ fnext3 = (fnext3 << 1U) + fcurr3;
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U);
+ gnext3 = (gnext3 << 1U) + gnext2;
+
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U);
+ gnext2 = (gnext2 << 1U) + gnext1;
+
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U);
+ gnext1 = (gnext1 << 1U) + gnext0;
+
+ gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr0 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = gnext3;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurr0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fcurr0 = (fcurr0 << 1U) + fnext0;
+
+ /* Process second sample for 5th, 9th .. tap */
+ fcurr1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U);
+ fcurr1 = (fcurr1 << 1U) + fnext1;
+
+ /* Process third sample for 5th, 9th .. tap */
+ fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U);
+ fcurr2 = (fcurr2 << 1U) + fnext2;
+
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U);
+ fcurr3 = (fcurr3 << 1U) + fnext3;
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 32U);
+ gnext3 = (gnext3 << 1U) + gnext2;
+
+ gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 32U);
+ gnext2 = (gnext2 << 1U) + gnext1;
+
+ gnext1 = (q31_t) (((q63_t) fnext1 * (*pk)) >> 32U);
+ gnext1 = (gnext1 << 1U) + gnext0;
+
+ gnext0 = (q31_t) (((q63_t) fnext0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1U) % 0x4U;
+
+ while (stageCnt > 0U)
+ {
+ gcurr0 = *px;
+
+ /* save g value in state buffer */
+ *px++ = gnext3;
+
+ /* Process four samples for last three taps here */
+ fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fnext0 = (fnext0 << 1U) + fcurr0;
+
+ fnext1 = (q31_t) (((q63_t) gnext0 * (*pk)) >> 32U);
+ fnext1 = (fnext1 << 1U) + fcurr1;
+
+ fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 32U);
+ fnext2 = (fnext2 << 1U) + fcurr2;
+
+ fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 32U);
+ fnext3 = (fnext3 << 1U) + fcurr3;
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 32U);
+ gnext3 = (gnext3 << 1U) + gnext2;
+
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 32U);
+ gnext2 = (gnext2 << 1U) + gnext1;
+
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 32U);
+ gnext1 = (gnext1 << 1U) + gnext0;
+
+ gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr0 = fnext0;
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+
+ stageCnt--;
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr0;
+ *pDst++ = fcurr1;
+ *pDst++ = fcurr2;
+ *pDst++ = fcurr3;
+
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* f0(n) = x(n) */
+ fcurr0 = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* read g2(n) from state buffer */
+ gcurr0 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fnext0 = (fnext0 << 1U) + fcurr0;
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr0;
+
+ /* f1(n) is saved in fcurr0 for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt = (numStages - 1U);
+
+ /* stage loop */
+ while (stageCnt > 0U)
+ {
+ /* read g2(n) from state buffer */
+ gcurr0 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext0;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fnext0 = (fnext0 << 1U) + fcurr0;
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ /* f1(n) is saved in fcurr0 for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt--;
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr0;
+
+ blkCnt--;
+ }
+
+#else
+/* alternate version for CM0_FAMILY */
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* f0(n) = x(n) */
+ fcurr0 = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* read g0(n-1) from state buffer */
+ gcurr0 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fnext0 = (fnext << 1U) + fcurr0;
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ /* save f0(n) in state buffer */
+ *px++ = fcurr0;
+
+ /* f1(n) is saved in fcurr for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt = (numStages - 1U);
+
+ /* stage loop */
+ while (stageCnt > 0U)
+ {
+ /* read g1(n-1) from state buffer */
+ gcurr0 = *px;
+
+ /* save g0(n-1) in state buffer */
+ *px++ = gnext0;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext0 = (q31_t) (((q63_t) gcurr0 * (*pk)) >> 32U);
+ fnext0 = (fnext0 << 1U) + fcurr0;
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext0 = (q31_t) (((q63_t) fcurr0 * (*pk++)) >> 32U);
+ gnext0 = (gnext0 << 1U) + gcurr0;
+
+ /* f1(n) is saved in fcurr0 for next stage processing */
+ fcurr0 = fnext0;
+
+ stageCnt--;
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr0;
+
+ blkCnt--;
+ }
+
+#endif /* #if !defined(ARM_MATH_CM0_FAMILY) */
+
+}
+
+/**
+ @} end of FIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c
new file mode 100644
index 000000000..5f6d354c9
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,323 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_q7.c
+ * Description: Q7 FIR filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR
+ @{
+ */
+
+/**
+ @brief Processing function for Q7 FIR filter.
+ @param[in] S points to an instance of the Q7 FIR filter structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ The accumulator is converted to 18.7 format by discarding the low 7 bits.
+ Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pState = S->pState; /* State pointer */
+ const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *pStateCurnt; /* Points to the current sample of the state */
+ q7_t *px; /* Temporary pointer for state buffer */
+ const q7_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t acc1, acc2, acc3; /* Accumulators */
+ q7_t x0, x1, x2, x3, c0; /* Temporary variables to hold state */
+#endif
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy 4 new input samples into the state buffer. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first 3 samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ Repeat until we've computed numTaps-4 coefficients. */
+ while (tapCnt > 0U)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *pb;
+
+ /* Read x[n-numTaps-3] sample */
+ x3 = *px;
+
+ /* acc0 += b[numTaps] * x[n-numTaps] */
+ acc0 += ((q15_t) x0 * c0);
+
+ /* acc1 += b[numTaps] * x[n-numTaps-1] */
+ acc1 += ((q15_t) x1 * c0);
+
+ /* acc2 += b[numTaps] * x[n-numTaps-2] */
+ acc2 += ((q15_t) x2 * c0);
+
+ /* acc3 += b[numTaps] * x[n-numTaps-3] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb + 1U);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px + 1U);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x1 * c0);
+ acc1 += ((q15_t) x2 * c0);
+ acc2 += ((q15_t) x3 * c0);
+ acc3 += ((q15_t) x0 * c0);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb + 2U);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px + 2U);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x2 * c0);
+ acc1 += ((q15_t) x3 * c0);
+ acc2 += ((q15_t) x0 * c0);
+ acc3 += ((q15_t) x1 * c0);
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *(pb + 3U);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px + 3U);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x3 * c0);
+ acc1 += ((q15_t) x0 * c0);
+ acc2 += ((q15_t) x1 * c0);
+ acc3 += ((q15_t) x2 * c0);
+
+ /* update coefficient pointer */
+ pb += 4U;
+ px += 4U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x0 * c0);
+ acc1 += ((q15_t) x1 * c0);
+ acc2 += ((q15_t) x2 * c0);
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31
+ Then store the 4 outputs in the destination buffer. */
+ acc0 = __SSAT((acc0 >> 7U), 8);
+ *pDst++ = acc0;
+ acc1 = __SSAT((acc1 >> 7U), 8);
+ *pDst++ = acc1;
+ acc2 = __SSAT((acc2 >> 7U), 8);
+ *pDst++ = acc2;
+ acc3 = __SSAT((acc3 >> 7U), 8);
+ *pDst++ = acc3;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining output samples */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of taps */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += (q15_t) * (px++) * (*(pb++));
+ i--;
+ } while (i > 0U);
+
+ /* The result is in 2.14 format. Convert to 1.7
+ Then store the output in the destination buffer. */
+ *pDst++ = __SSAT((acc0 >> 7U), 8);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of taps */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ /* Copy remaining data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
index 000000000..f44f037ff
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_sparse_f32.c
+ * Description: Floating-point sparse FIR filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters
+
+ This group of functions implements sparse FIR filters.
+ Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.
+ Sparse filters are used for simulating reflections in communications and audio applications.
+
+ There are separate functions for Q7, Q15, Q31, and floating-point data types.
+ The functions operate on blocks of input and output data and each call to the function processes
+ blockSize samples through the filter. pSrc and
+ pDst points to input and output arrays respectively containing blockSize values.
+
+ @par Algorithm
+ The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.
+ This is in addition to the coefficient array b.
+ The implementation essentially skips the multiplications by zero and leads to an efficient realization.
+
+ y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+
+ @par
+ \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients"
+ @par
+ pCoeffs points to a coefficient array of size numTaps;
+ pTapDelay points to an array of nonzero indices and is also of size numTaps;
+ pState points to a state array of size maxDelay + blockSize, where
+ maxDelay is the largest offset value that is ever used in the pTapDelay array.
+ Some of the processing functions also require temporary working buffers.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter.
+ Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.
+ There are separate instance structure declarations for each of the 4 supported data types.
+
+ @par Initialization Functions
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero.
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ Set the values in the state buffer to zeros before static initialization.
+ The code below statically initializes each of the 4 different data type filter instance structures
+
+ arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ arm_fir_sparse_instance_q7 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+
+
+ @par Fixed-Point Behavior
+ Care must be taken when using the fixed-point versions of the sparse FIR filter functions.
+ In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ @addtogroup FIR_Sparse
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point sparse FIR filter.
+ @param[in] S points to an instance of the floating-point sparse FIR structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] pScratchIn points to a temporary buffer of size blockSize
+ @param[in] blockSize number of input samples to process
+ @return none
+ */
+
+void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ const float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* Scratch buffer pointer */
+ float32_t *py = pState; /* Temporary pointers for state buffer */
+ float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ float32_t *pOut; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ float32_t coeff = *pCoeffs++; /* Read the first coefficient value */
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1, (int32_t *) pSrc, 1, blockSize);
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ *pOut++ = *px++ * coeff;
+
+ *pOut++ = *px++ * coeff;
+
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiplication and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ *pOut++ += *px++ * coeff;
+
+ *pOut++ += *px++ * coeff;
+
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR_Sparse group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
index 000000000..7745e716c
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_sparse_init_f32.c
+ * Description: Floating-point sparse FIR filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Sparse
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point sparse FIR filter.
+ @param[in,out] S points to an instance of the floating-point sparse FIR structure
+ @param[in] numTaps number of nonzero coefficients in the filter
+ @param[in] pCoeffs points to the array of filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] pTapDelay points to the array of offset times
+ @param[in] maxDelay maximum offset time supported
+ @param[in] blockSize number of samples that will be processed per block
+ @return none
+
+ @par Details
+ pCoeffs holds the filter coefficients and has length numTaps.
+ pState holds the filter's state variables and must be of length
+ maxDelay + blockSize, where maxDelay
+ is the maximum number of delay line values.
+ blockSize is the
+ number of samples processed by the arm_fir_sparse_f32() function.
+ */
+
+void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ const float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0U;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of FIR_Sparse group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
index 000000000..d07d61197
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_sparse_init_q15.c
+ * Description: Q15 sparse FIR filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Sparse
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q15 sparse FIR filter.
+ @param[in,out] S points to an instance of the Q15 sparse FIR structure
+ @param[in] numTaps number of nonzero coefficients in the filter
+ @param[in] pCoeffs points to the array of filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] pTapDelay points to the array of offset times
+ @param[in] maxDelay maximum offset time supported
+ @param[in] blockSize number of samples that will be processed per block
+ @return none
+
+ @par Details
+ pCoeffs holds the filter coefficients and has length numTaps.
+ pState holds the filter's state variables and must be of length
+ maxDelay + blockSize, where maxDelay
+ is the maximum number of delay line values.
+ blockSize is the
+ number of words processed by arm_fir_sparse_q15() function.
+ */
+
+void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ const q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0U;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of FIR_Sparse group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
index 000000000..7c32cea11
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_sparse_init_q31.c
+ * Description: Q31 sparse FIR filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Sparse
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q31 sparse FIR filter.
+ @param[in,out] S points to an instance of the Q31 sparse FIR structure
+ @param[in] numTaps number of nonzero coefficients in the filter
+ @param[in] pCoeffs points to the array of filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] pTapDelay points to the array of offset times
+ @param[in] maxDelay maximum offset time supported
+ @param[in] blockSize number of samples that will be processed per block
+ @return none
+
+ @par Details
+ pCoeffs holds the filter coefficients and has length numTaps.
+ pState holds the filter's state variables and must be of length
+ maxDelay + blockSize, where maxDelay
+ is the maximum number of delay line values.
+ blockSize is the number of words processed by arm_fir_sparse_q31() function.
+ */
+
+void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ const q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0U;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of FIR_Sparse group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
index 000000000..98153f321
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_sparse_init_q7.c
+ * Description: Q7 sparse FIR filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Sparse
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q7 sparse FIR filter.
+ @param[in,out] S points to an instance of the Q7 sparse FIR structure
+ @param[in] numTaps number of nonzero coefficients in the filter
+ @param[in] pCoeffs points to the array of filter coefficients
+ @param[in] pState points to the state buffer
+ @param[in] pTapDelay points to the array of offset times
+ @param[in] maxDelay maximum offset time supported
+ @param[in] blockSize number of samples that will be processed per block
+ @return none
+
+ @par Details
+ pCoeffs holds the filter coefficients and has length numTaps.
+ pState holds the filter's state variables and must be of length
+ maxDelay + blockSize, where maxDelay
+ is the maximum number of delay line values.
+ blockSize is the
+ number of samples processed by the arm_fir_sparse_q7() function.
+ */
+
+void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ const q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0U;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of FIR_Sparse group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
index 000000000..9cea93e2d
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_sparse_q15.c
+ * Description: Q15 sparse FIR filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Sparse
+ @{
+ */
+
+/**
+ @brief Processing function for the Q15 sparse FIR filter.
+ @param[in] S points to an instance of the Q15 sparse FIR structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] pScratchIn points to a temporary buffer of size blockSize
+ @param[in] pScratchOut points to a temporary buffer of size blockSize
+ @param[in] blockSize number of input samples to process per call
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.
+ Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.
+ If the accumulator result overflows it will wrap around rather than saturate.
+ After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.
+ In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ const q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* Temporary pointers for scratch buffer */
+ q15_t *py = pState; /* Temporary pointers for state buffer */
+ q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q15_t *pOut = pDst; /* Working pointer for output */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */
+ q15_t coeff = *pCoeffs++; /* Read the first coefficient value */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t in1, in2; /* Temporary variables */
+#endif
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q15(py, (int32_t) delaySize, &S->stateIndex, 1,pSrc, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1,
+ pb, pb, (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1,
+ pb, pb, (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, (int32_t) delaySize, &readIndex, 1,
+ pb, pb, (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) *px++ * coeff;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ in1 = *pScr2++;
+ in2 = *pScr2++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pScr2++;
+ in2 = *pScr2++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16), 16));
+#else
+ write_q15x2_ia (&pOut, __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16), 16));
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR_Sparse group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
index 000000000..86d3e1db0
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,357 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_sparse_q31.c
+ * Description: Q31 sparse FIR filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Sparse
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 sparse FIR filter.
+ @param[in] S points to an instance of the Q31 sparse FIR structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] pScratchIn points to a temporary buffer of size blockSize
+ @param[in] blockSize number of input samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 32-bit accumulator.
+ The 1.31 x 1.31 multiplications are truncated to 2.30 format.
+ This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.
+ If the accumulator result overflows, it wraps around rather than saturate.
+ In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ const q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* Scratch buffer pointer */
+ q31_t *py = pState; /* Temporary pointers for state buffer */
+ q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q31_t *pOut; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q31_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t in;
+ q63_t out; /* Temporary output variable */
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32);
+
+ *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32);
+
+ *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32);
+
+ *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiplication and store in destination buffer */
+ *pOut++ = (q31_t) (((q63_t) *px++ * coeff) >> 32);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) *px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) *px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) *px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) *px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) *px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement tap loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) *px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Working output pointer is updated */
+ pOut = pDst;
+
+ /* Output is converted into 1.31 format. */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR_Sparse group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
index 000000000..7a2b57f18
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,341 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fir_sparse_q7.c
+ * Description: Q7 sparse FIR filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup FIR_Sparse
+ @{
+ */
+
+/**
+ @brief Processing function for the Q7 sparse FIR filter.
+ @param[in] S points to an instance of the Q7 sparse FIR structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] pScratchIn points to a temporary buffer of size blockSize
+ @param[in] pScratchOut points to a temporary buffer of size blockSize
+ @param[in] blockSize number of input samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ The accumulator is then converted to 18.7 format by discarding the low 7 bits.
+ Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ const q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+ q7_t *pState = S->pState; /* State pointer */
+ const q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *px; /* Scratch buffer pointer */
+ q7_t *py = pState; /* Temporary pointers for state buffer */
+ q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q7_t *pOut = pDst; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */
+ q31_t in;
+ q7_t coeff = *pCoeffs++; /* Read the coefficient value */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q7_t in1, in2, in3, in4;
+#endif
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1,
+ pb, pb, (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) *px++ * coeff);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1,
+ pb, pb, (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) *px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if (readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Compute last tap without the final read of pTapDelay */
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1,
+ pb, pb, (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) *px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) *px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) *px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) *px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) *px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time. */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ write_q7x4_ia (&pOut, __PACKq7(in1, in2, in3, in4));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of FIR_Sparse group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
index 000000000..c48efe30e
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,354 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_iir_lattice_f32.c
+ * Description: Floating-point IIR Lattice filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters
+
+ This set of functions implements lattice filters
+ for Q15, Q31 and floating-point data types. Lattice filters are used in a
+ variety of adaptive filter applications. The filter structure has feedforward and
+ feedback components and the net impulse response is infinite length.
+ The functions operate on blocks
+ of input and output data and each call to the function processes
+ blockSize samples through the filter. pSrc and
+ pDst point to input and output arrays containing blockSize values.
+
+ @par Algorithm
+ \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"
+ @par
+
+ fN(n) = x(n)
+ fm-1(n) = fm(n) - km * gm-1(n-1) for m = N, N-1, ..., 1
+ gm(n) = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ..., 1
+ y(n) = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+
+ @par
+ pkCoeffs points to array of reflection coefficients of size numStages.
+ Reflection Coefficients are stored in time-reversed order.
+ @par
+
+ {kN, kN-1, ..., k1}
+
+ @par
+ pvCoeffs points to the array of ladder coefficients of size (numStages+1).
+ Ladder coefficients are stored in time-reversed order.
+
+ {vN, vN-1, ..., v0}
+
+ @par
+ pState points to a state array of size numStages + blockSize.
+ The state variables shown in the figure above (the g values) are stored in the pState array.
+ The state variables are updated after each block of data is processed; the coefficients are untouched.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter.
+ Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ There are separate instance structure declarations for each of the 3 supported data types.
+
+ @par Initialization Functions
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero.
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+
+ arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+
+ @par
+ where numStages is the number of stages in the filter; pState points to the state buffer array;
+ pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.
+
+ @par Fixed-Point Behavior
+ Care must be taken when using the fixed-point versions of the IIR lattice filter functions.
+ In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ @addtogroup IIR_Lattice
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point IIR lattice filter.
+ @param[in] S points to an instance of the floating-point IIR lattice structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pStateCur; /* State current pointer */
+ float32_t acc; /* Accumlator */
+ float32_t fnext1, fnext2, gcurr1, gnext; /* Temporary variables for lattice stages */
+ float32_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* Number of stages */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ float32_t gcurr2; /* Temporary variables for lattice stages */
+ float32_t k1, k2;
+ float32_t v1, v2, v3, v4;
+#endif
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ /* Sample processing */
+ while (blkCnt > 0U)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fnext2 = *pSrc++;
+
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Initialize state read pointer */
+ px1 = pState;
+
+ /* Initialize state write pointer */
+ px2 = pState;
+
+ /* Set accumulator to zero */
+ acc = 0.0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numStages) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Read gN-1(n-1) from state buffer */
+ gcurr1 = *px1;
+
+ /* read reflection coefficient kN */
+ k1 = *pk;
+
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext1 = fnext2 - (k1 * gcurr1);
+
+ /* read ladder coefficient vN */
+ v1 = *pv;
+
+ /* read next reflection coefficient kN-1 */
+ k2 = *(pk + 1U);
+
+ /* Read gN-2(n-1) from state buffer */
+ gcurr2 = *(px1 + 1U);
+
+ /* read next ladder coefficient vN-1 */
+ v2 = *(pv + 1U);
+
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext2 = fnext1 - (k2 * gcurr2);
+
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = gcurr1 + (k1 * fnext1);
+
+ /* read reflection coefficient kN-2 */
+ k1 = *(pk + 2U);
+
+ /* write gN(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Read gN-3(n-1) from state buffer */
+ gcurr1 = *(px1 + 2U);
+
+ /* y(n) += gN(n) * vN */
+ acc += (gnext * v1);
+
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fnext1 = fnext2 - (k1 * gcurr1);
+
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = gcurr2 + (k2 * fnext2);
+
+ /* Read gN-4(n-1) from state buffer */
+ gcurr2 = *(px1 + 3U);
+
+ /* y(n) += gN-1(n) * vN-1 */
+ acc += (gnext * v2);
+
+ /* read reflection coefficient kN-3 */
+ k2 = *(pk + 3U);
+
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext2 = fnext1 - (k2 * gcurr2);
+
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = gcurr1 + (k1 * fnext1);
+
+ /* read ladder coefficient vN-2 */
+ v3 = *(pv + 2U);
+
+ /* y(n) += gN-2(n) * vN-2 */
+ acc += (gnext * v3);
+
+ /* write gN-2(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* update pointer */
+ pk += 4U;
+
+ /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+ gnext = (fnext2 * k2) + gcurr2;
+
+ /* read next ladder coefficient vN-3 */
+ v4 = *(pv + 3U);
+
+ /* y(n) += gN-4(n) * vN-4 */
+ acc += (gnext * v4);
+
+ /* write gN-3(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* update pointers */
+ px1 += 4U;
+ pv += 4U;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numStages % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numStages;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ gcurr1 = *px1++;
+ /* Process sample for last taps */
+ fnext1 = fnext2 - ((*pk) * gcurr1);
+ gnext = (fnext1 * (*pk++)) + gcurr1;
+ /* Output samples for last taps */
+ acc += (gnext * (*pv++));
+ *px2++ = gnext;
+ fnext2 = fnext1;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (fnext2 * (*pv));
+
+ *px2++ = fnext2;
+
+ /* write out into pDst */
+ *pDst++ = acc;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCur = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ /* Copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numStages >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numStages % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ tapCnt = numStages;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of IIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
index 000000000..bd9f9338a
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,77 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_iir_lattice_init_f32.c
+ * Description: Floating-point IIR lattice filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup IIR_Lattice
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point IIR lattice filter.
+ @param[in] S points to an instance of the floating-point IIR lattice structure
+ @param[in] numStages number of stages in the filter
+ @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages
+ @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1
+ @param[in] pState points to state buffer. The array is of length numStages+blockSize
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of IIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
index 000000000..01abf48e7
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,77 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_iir_lattice_init_q15.c
+ * Description: Q15 IIR lattice filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup IIR_Lattice
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q15 IIR lattice filter.
+ @param[in] S points to an instance of the Q15 IIR lattice structure
+ @param[in] numStages number of stages in the filter
+ @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages
+ @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1
+ @param[in] pState points to state buffer. The array is of length numStages+blockSize
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of IIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
index 000000000..b472f6ce6
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,77 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_iir_lattice_init_q31.c
+ * Description: Initialization function for the Q31 IIR lattice filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup IIR_Lattice
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q31 IIR lattice filter.
+ @param[in] S points to an instance of the Q31 IIR lattice structure
+ @param[in] numStages number of stages in the filter
+ @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages
+ @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1
+ @param[in] pState points to state buffer. The array is of length numStages+blockSize
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ @} end of IIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
index 000000000..9dbea8119
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,396 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_iir_lattice_q15.c
+ * Description: Q15 IIR Lattice filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup IIR_Lattice
+ @{
+ */
+
+/**
+ @brief Processing function for the Q15 IIR lattice filter.
+ @param[in] S points to an instance of the Q15 IIR lattice structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pStateCur; /* State current pointer */
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q63_t acc; /* Accumlator */
+ q15_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* Number of stages */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q15_t out; /* Temporary variable for output */
+
+#if defined (ARM_MATH_DSP) && defined (ARM_MATH_LOOPUNROLL)
+ q15_t gnext1, gnext2; /* Temporary variables for lattice stages */
+ q31_t v; /* Temporary variable for ladder coefficient */
+#endif
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+#if defined (ARM_MATH_DSP)
+
+ /* Sample processing */
+ while (blkCnt > 0U)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Initialize state read pointer */
+ px1 = pState;
+
+ /* Initialize state write pointer */
+ px2 = pState;
+
+ /* Set accumulator to zero */
+ acc = 0;
+
+ /* Process sample for first tap */
+ gcurr = *px1++;
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numStages - 1U) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Process sample for 2nd, 6th ...taps */
+ /* Read gN-2(n-1) from state buffer */
+ gcurr = *px1++;
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext1 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext1;
+
+ /* Process sample for 3nd, 7th ...taps */
+ /* Read gN-3(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 3rd, 7th .. taps */
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+ fcurr = __SSAT(fcurr, 16);
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+ gnext2 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-2(n) into state */
+ *px2++ = (q15_t) gnext2;
+
+ /* Read vN-1 and vN-2 at a time */
+ v = read_q15x2_ia (&pv);
+
+ /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ gnext = __PKHBT(gnext1, gnext2, 16);
+#else
+ gnext = __PKHBT(gnext2, gnext1, 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* y(n) += gN-1(n) * vN-1 */
+ /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+ /* y(n) += gN-2(n) * vN-2 */
+ /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+ acc = __SMLALD(gnext, v, acc);
+
+ /* Process sample for 4th, 8th ...taps */
+ /* Read gN-4(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 4th, 8th .. taps */
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext1 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-3(n) for the next sample process */
+ *px2++ = (q15_t) gnext1;
+
+ /* Process sample for 5th, 9th ...taps */
+ /* Read gN-5(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 5th, 9th .. taps */
+ /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+ fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+ fcurr = __SSAT(fcurr, 16);
+ /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+ gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+ gnext2 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-4(n) for the next sample process */
+ *px2++ = (q15_t) gnext2;
+
+ /* Read vN-3 and vN-4 at a time */
+ v = read_q15x2_ia (&pv);
+
+ /* Pack gN-3(n) and gN-4(n) */
+#ifndef ARM_MATH_BIG_ENDIAN
+ gnext = __PKHBT(gnext1, gnext2, 16);
+#else
+ gnext = __PKHBT(gnext2, gnext1, 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* y(n) += gN-4(n) * vN-4 */
+ /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+ /* y(n) += gN-3(n) * vN-3 */
+ /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+ acc = __SMLALD(gnext, v, acc);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ fnext = fcurr;
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numStages - 1U) % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ tapCnt = (numStages - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+
+ /* Output samples for last taps */
+ acc += (q31_t) (((q31_t) gnext * (*pv++)));
+ *px2++ = (q15_t) gnext;
+ fcurr = fnext;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+ out = (q15_t) __SSAT(acc >> 15, 16);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCur = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ /* copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numStages >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState));
+ write_q15x2_ia (&pStateCur, read_q15x2_ia (&pState));
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numStages % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ tapCnt = (numStages - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+ /* Sample processing */
+ while (blkCnt > 0U)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Initialize state read pointer */
+ px1 = pState;
+
+ /* Initialize state write pointer */
+ px2 = pState;
+
+ /* Set accumulator to zero */
+ acc = 0;
+
+ tapCnt = numStages;
+
+ while (tapCnt > 0U)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - ((gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) ((fnext * (*pv++)));
+
+ out = (q15_t) __SSAT(acc >> 15, 16);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCur = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ @} end of IIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
index 000000000..c4b9a7626
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,356 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_iir_lattice_q31.c
+ * Description: Q31 IIR Lattice filter processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup IIR_Lattice
+ @{
+ */
+
+/**
+ @brief Processing function for the Q31 IIR lattice filter.
+ @param[in] S points to an instance of the Q31 IIR lattice structure
+ @param[in] pSrc points to the block of input data
+ @param[out] pDst points to the block of output data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.
+ After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.
+ */
+
+void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pStateCur; /* State current pointer */
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q63_t acc; /* Accumlator */
+ q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* Number of stages */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+#if defined (ARM_MATH_DSP)
+
+ /* Sample processing */
+ while (blkCnt > 0U)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Initialize state read pointer */
+ px1 = pState;
+
+ /* Initialize state write pointer */
+ px2 = pState;
+
+ /* Set accumulator to zero */
+ acc = 0;
+
+ /* Process sample for first tap */
+ gcurr = *px1++;
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31));
+
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numStages - 1U) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Process sample for 2nd, 6th ...taps */
+ /* Read gN-2(n-1) from state buffer */
+ gcurr = *px1++;
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31));
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* y(n) += gN-1(n) * vN-1 */
+ /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Process sample for 3nd, 7th ...taps */
+ /* Read gN-3(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 3rd, 7th .. taps */
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31));
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+ /* y(n) += gN-2(n) * vN-2 */
+ /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-2(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Process sample for 4th, 8th ...taps */
+ /* Read gN-4(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 4th, 8th .. taps */
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31));
+ /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* y(n) += gN-3(n) * vN-3 */
+ /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-3(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Process sample for 5th, 9th ...taps */
+ /* Read gN-5(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 5th, 9th .. taps */
+ /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+ fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk )) >> 31));
+ /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+ /* y(n) += gN-4(n) * vN-4 */
+ /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+ acc += ((q63_t) gnext * *pv++);
+
+ /* write gN-4(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ fnext = fcurr;
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numStages - 1U) % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ tapCnt = (numStages - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk )) >> 31));
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+
+ /* Output samples for last taps */
+ acc += ((q63_t) gnext * *pv++);
+ *px2++ = gnext;
+ fcurr = fnext;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += ((q63_t) fnext * *pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31U);
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCur = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ /* Copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numStages >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numStages % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ tapCnt = (numStages - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+ /* Sample processing */
+ while (blkCnt > 0U)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Initialize state read pointer */
+ px1 = pState;
+
+ /* Initialize state write pointer */
+ px2 = pState;
+
+ /* Set accumulator to zero */
+ acc = 0;
+
+ tapCnt = numStages;
+
+ while (tapCnt > 0U)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = clip_q63_to_q31(((q63_t) fcurr - ((q31_t) (((q63_t) gcurr * (*pk )) >> 31))));
+
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = clip_q63_to_q31(((q63_t) gcurr + ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += ((q63_t) fnext * *pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31U);
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCur = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy data */
+ while (tapCnt > 0U)
+ {
+ *pStateCur++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+/**
+ @} end of IIR_Lattice group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c
new file mode 100644
index 000000000..4fc6e7e29
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,533 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_f32.c
+ * Description: Processing function for the floating-point LMS filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup LMS Least Mean Square (LMS) Filters
+
+ LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.
+ LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.
+ Adaptive filters are often used in communication systems, equalizers, and noise removal.
+ The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.
+
+ An LMS filter consists of two components as shown below.
+ The first component is a standard transversal or FIR filter.
+ The second component is a coefficient update mechanism.
+ The LMS filter has two input signals.
+ The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ This "error signal" tends towards zero as the filter adapts.
+ The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ \image html LMS.gif "Internal structure of the Least Mean Square filter"
+
+ The functions operate on blocks of data and each call to the function processes
+ blockSize samples through the filter.
+ pSrc points to input signal, pRef points to reference signal,
+ pOut points to output signal and pErr points to error signal.
+ All arrays contain blockSize values.
+
+ The functions operate on a block-by-block basis.
+ Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.
+ The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+
+ @par Algorithm
+ The output signal y[n] is computed by a standard FIR filter:
+
+ y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+
+ @par
+ The error signal equals the difference between the reference signal d[n] and the filter output:
+
+ e[n] = d[n] - y[n].
+
+
+ @par
+ After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:
+
+ b[k] = b[k] + e[n] * mu * x[n-k], for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence.
+ @par
+ In the APIs, pCoeffs points to a coefficient array of size numTaps.
+ Coefficients are stored in time reversed order.
+ @par
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par
+ pState points to a state array of size numTaps + blockSize - 1.
+ Samples in the state buffer are stored in the order:
+ @par
+
+ {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par
+ Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.
+ The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ to be avoided and yields a significant speed improvement.
+ The state variables are updated after each block of data is processed.
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter and
+ coefficient and state arrays cannot be shared among instances.
+ There are separate instance structure declarations for each of the 3 supported data types.
+
+ @par Initialization Functions
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero.
+
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ Set the values in the state buffer to zeros before static initialization.
+ The code below statically initializes each of the 3 different data type filter instance structures
+
+ arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+ arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+ arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+
+ where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;
+ pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.
+
+ @par Fixed-Point Behavior
+ Care must be taken when using the Q15 and Q31 versions of the LMS filter.
+ The following issues must be considered:
+ - Scaling of coefficients
+ - Overflow and saturation
+
+ @par Scaling of Coefficients
+ Filter coefficients are represented as fractional values and
+ coefficients are restricted to lie in the range [-1 +1).
+ The fixed-point functions have an additional scaling parameter postShift.
+ At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ This essentially scales the filter coefficients by 2^postShift and
+ allows the filter coefficients to exceed the range [+1 -1).
+ The value of postShift is set by the user based on the expected gain through the system being modeled.
+
+ @par Overflow and Saturation
+ Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ described separately as part of the function specific documentation below.
+ */
+
+/**
+ @addtogroup LMS
+ @{
+ */
+
+/**
+ @brief Processing function for floating-point LMS filter.
+ @param[in] S points to an instance of the floating-point LMS filter structure
+ @param[in] pSrc points to the block of input data
+ @param[in] pRef points to the block of reference data
+ @param[out] pOut points to the block of output data
+ @param[out] pErr points to the block of error data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+#if defined(ARM_MATH_NEON)
+void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w = 0.0f; /* weight factor */
+
+ float32x4_t tempV, sumV, xV, bV;
+ float32x2_t tempV2;
+
+ e = 0.0f;
+ d = 0.0f;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+ sumV = vdupq_n_f32(0.0);
+
+ /* Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ xV = vld1q_f32(px);
+ bV = vld1q_f32(pb);
+ sumV = vmlaq_f32(sumV, xV, bV);
+
+ px += 4;
+ pb += 4;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+ tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV));
+ sum = tempV2[0] + tempV2[1];
+
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator, store in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for the updating filter coefficients */
+ w = e * mu;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ xV = vld1q_f32(px);
+ bV = vld1q_f32(pb);
+ px += 4;
+ bV = vmlaq_n_f32(bV,xV,w);
+
+ vst1q_f32(pb,bV);
+ pb += 4;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Process 4 taps at a time for (numTaps - 1U) samples copy */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ /* copy data */
+ while (tapCnt > 0U)
+ {
+ tempV = vld1q_f32(pState);
+ vst1q_f32(pStateCurnt,tempV);
+ pState += 4;
+ pStateCurnt += 4;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+ /* Copy the remaining q31_t data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+}
+#else
+void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ float32_t acc, e; /* Accumulator, error */
+ float32_t w; /* Weight factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+ /* Initializations of error, difference, Coefficient update */
+ e = 0.0f;
+ w = 0.0f;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (*px++) * (*pb++);
+
+ acc += (*px++) * (*pb++);
+
+ acc += (*px++) * (*pb++);
+
+ acc += (*px++) * (*pb++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = acc;
+
+ /* Compute and store error */
+ e = (float32_t) *pRef++ - acc;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ w = e * mu;
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ /* Update filter coefficients */
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of LMS group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
index 000000000..f418f4610
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,81 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_init_f32.c
+ * Description: Floating-point LMS filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @addtogroup LMS
+ @{
+ */
+
+/**
+ @brief Initialization function for floating-point LMS filter.
+ @param[in] S points to an instance of the floating-point LMS filter structure
+ @param[in] numTaps number of filter coefficients
+ @param[in] pCoeffs points to coefficient buffer
+ @param[in] pState points to state buffer
+ @param[in] mu step size that controls filter coefficient updates
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter.
+ pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().
+ */
+
+void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps */
+ memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+}
+
+/**
+ @} end of LMS group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
index 000000000..fe0a5c516
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_init_q15.c
+ * Description: Q15 LMS filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup LMS
+ @{
+ */
+
+/**
+ @brief Initialization function for the Q15 LMS filter.
+ @param[in] S points to an instance of the Q15 LMS filter structure.
+ @param[in] numTaps number of filter coefficients.
+ @param[in] pCoeffs points to coefficient buffer.
+ @param[in] pState points to state buffer.
+ @param[in] mu step size that controls filter coefficient updates.
+ @param[in] blockSize number of samples to process.
+ @param[in] postShift bit shift applied to coefficients.
+ @return none
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter.
+ pState points to the array of state variables and size of array is
+ numTaps+blockSize-1 samples, where blockSize is the number of
+ input samples processed by each call to arm_lms_q15().
+ */
+
+void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Assign postShift value to be applied */
+ S->postShift = postShift;
+}
+
+/**
+ @} end of LMS group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
index 000000000..3410b9f21
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_init_q31.c
+ * Description: Q31 LMS filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup LMS
+ @{
+ */
+
+/**
+ @brief Initialization function for Q31 LMS filter.
+ @param[in] S points to an instance of the Q31 LMS filter structure
+ @param[in] numTaps number of filter coefficients
+ @param[in] pCoeffs points to coefficient buffer
+ @param[in] pState points to state buffer
+ @param[in] mu step size that controls filter coefficient updates
+ @param[in] blockSize number of samples to process
+ @param[in] postShift bit shift applied to coefficients
+ @return none
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter.
+ pState points to an array of length numTaps+blockSize-1 samples,
+ where blockSize is the number of input samples processed by each call to
+ arm_lms_q31().
+ */
+
+void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Assign postShift value to be applied */
+ S->postShift = postShift;
+}
+
+/**
+ @} end of LMS group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
index 000000000..28ab04a29
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,564 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_norm_f32.c
+ * Description: Processing function for the floating-point NLMS filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @defgroup LMS_NORM Normalized LMS Filters
+
+ This set of functions implements a commonly used adaptive filter.
+ It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization
+ factor which increases the adaptation rate of the filter.
+ The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.
+
+ A normalized least mean square (NLMS) filter consists of two components as shown below.
+ The first component is a standard transversal or FIR filter.
+ The second component is a coefficient update mechanism.
+ The NLMS filter has two input signals.
+ The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ This "error signal" tends towards zero as the filter adapts.
+ The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ \image html LMS.gif "Internal structure of the NLMS adaptive filter"
+
+ The functions operate on blocks of data and each call to the function processes
+ blockSize samples through the filter.
+ pSrc points to input signal, pRef points to reference signal,
+ pOut points to output signal and pErr points to error signal.
+ All arrays contain blockSize values.
+
+ The functions operate on a block-by-block basis.
+ Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.
+ The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+
+ @par Algorithm
+ The output signal y[n] is computed by a standard FIR filter:
+
+ y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+
+
+ @par
+ The error signal equals the difference between the reference signal d[n] and the filter output:
+
+ e[n] = d[n] - y[n].
+
+
+ @par
+ After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:
+
+ E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+
+ The filter coefficients b[k] are then updated on a sample-by-sample basis:
+
+ b[k] = b[k] + e[n] * (mu/E) * x[n-k], for k=0, 1, ..., numTaps-1
+
+ where mu is the step size and controls the rate of coefficient convergence.
+ @par
+ In the APIs, pCoeffs points to a coefficient array of size numTaps.
+ Coefficients are stored in time reversed order.
+ @par
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ @par
+ pState points to a state array of size numTaps + blockSize - 1.
+ Samples in the state buffer are stored in the order:
+ @par
+
+ {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+
+ @par
+ Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.
+ The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ to be avoided and yields a significant speed improvement.
+ The state variables are updated after each block of data is processed.
+
+ @par Instance Structure
+ The coefficients and state variables for a filter are stored together in an instance data structure.
+ A separate instance structure must be defined for each filter and
+ coefficient and state arrays cannot be shared among instances.
+ There are separate instance structure declarations for each of the 3 supported data types.
+
+ @par Initialization Functions
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Zeros out the values in the state buffer.
+ To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero.
+ For Q7, Q15, and Q31 the following fields must also be initialized;
+ recipTable, postShift
+ @par
+ Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ @par Fixed-Point Behavior
+ Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.
+ The following issues must be considered:
+ - Scaling of coefficients
+ - Overflow and saturation
+
+ @par Scaling of Coefficients
+ Filter coefficients are represented as fractional values and
+ coefficients are restricted to lie in the range [-1 +1).
+ The fixed-point functions have an additional scaling parameter postShift.
+ At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.
+ This essentially scales the filter coefficients by 2^postShift and
+ allows the filter coefficients to exceed the range [+1 -1).
+ The value of postShift is set by the user based on the expected gain through the system being modeled.
+
+ @par Overflow and Saturation
+ Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ described separately as part of the function specific documentation below.
+ */
+
+/**
+ @addtogroup LMS_NORM
+ @{
+ */
+
+/**
+ @brief Processing function for floating-point normalized LMS filter.
+ @param[in] S points to an instance of the floating-point normalized LMS filter structure
+ @param[in] pSrc points to the block of input data
+ @param[in] pRef points to the block of reference data
+ @param[out] pOut points to the block of output data
+ @param[out] pErr points to the block of error data
+ @param[in] blockSize number of samples to process
+ @return none
+ */
+
+#if defined(ARM_MATH_NEON)
+void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t energy; /* Energy of the input */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */
+
+ float32x4_t tempV, sumV, xV, bV;
+ float32x2_t tempV2;
+
+ /* Initializations of error, difference, Coefficient update */
+ e = 0.0f;
+ d = 0.0f;
+ w = 0.0f;
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+ sumV = vdupq_n_f32(0.0);
+
+ /* Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ xV = vld1q_f32(px);
+ bV = vld1q_f32(pb);
+ sumV = vmlaq_f32(sumV, xV, bV);
+
+ px += 4;
+ pb += 4;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+ tempV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV));
+ sum = tempV2[0] + tempV2[1];
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator, store in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = (e * mu) / (energy + 0.000000119209289f);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ xV = vld1q_f32(px);
+ bV = vld1q_f32(pb);
+ px += 4;
+ bV = vmlaq_n_f32(bV,xV,w);
+
+ vst1q_f32(pb,bV);
+ pb += 4;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Process 4 taps at a time for (numTaps - 1U)/4 samples copy */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ /* copy data */
+ while (tapCnt > 0U)
+ {
+ tempV = vld1q_f32(pState);
+ vst1q_f32(pStateCurnt,tempV);
+ pState += 4;
+ pStateCurnt += 4;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+ /* Copy the remaining q31_t data */
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+#else
+void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ const float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ float32_t acc, e; /* Accumulator, error */
+ float32_t w; /* Weight factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t energy; /* Energy of the input */
+ float32_t x0, in; /* Temporary variable to hold input sample and state */
+
+ /* Initializations of error, difference, Coefficient update */
+ e = 0.0f;
+ w = 0.0f;
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (*px++) * (*pb++);
+
+ acc += (*px++) * (*pb++);
+
+ acc += (*px++) * (*pb++);
+
+ acc += (*px++) * (*pb++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = acc;
+
+ /* Compute and store error */
+ e = (float32_t) *pRef++ - acc;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = (e * mu) / (energy + 0.000000119209289f);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ /* Update filter coefficients */
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+/**
+ @} end of LMS_NORM group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
index 000000000..543dc7258
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,92 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_norm_init_f32.c
+ * Description: Floating-point NLMS filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup LMS_NORM
+ @{
+ */
+
+/**
+ @brief Initialization function for floating-point normalized LMS filter.
+ @param[in] S points to an instance of the floating-point LMS filter structure
+ @param[in] numTaps number of filter coefficients
+ @param[in] pCoeffs points to coefficient buffer
+ @param[in] pState points to state buffer
+ @param[in] mu step size that controls filter coefficient updates
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter.
+ pState points to an array of length numTaps+blockSize-1 samples,
+ where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().
+ */
+
+void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialise Energy to zero */
+ S->energy = 0.0f;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0.0f;
+}
+
+/**
+ @} end of LMS_NORM group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
index 000000000..d581ac18e
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_norm_init_q15.c
+ * Description: Q15 NLMS filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ @addtogroup LMS_NORM
+ @{
+ */
+
+/**
+ @brief Initialization function for Q15 normalized LMS filter.
+ @param[in] S points to an instance of the Q15 normalized LMS filter structure.
+ @param[in] numTaps number of filter coefficients.
+ @param[in] pCoeffs points to coefficient buffer.
+ @param[in] pState points to state buffer.
+ @param[in] mu step size that controls filter coefficient updates.
+ @param[in] blockSize number of samples to process.
+ @param[in] postShift bit shift applied to coefficients.
+ @return none
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter.
+ pState points to the array of state variables and size of array is
+ numTaps+blockSize-1 samples, where blockSize is the number of input samples processed
+ by each call to arm_lms_norm_q15().
+ */
+
+void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q15_t));
+
+ /* Assign post Shift value applied to coefficients */
+ S->postShift = postShift;
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialize reciprocal pointer table */
+ S->recipTable = (q15_t *) armRecipTableQ15;
+
+ /* Initialise Energy to zero */
+ S->energy = 0;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0;
+}
+
+/**
+ @} end of LMS_NORM group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
index 000000000..30e78ec42
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,97 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_norm_init_q31.c
+ * Description: Q31 NLMS filter initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ @addtogroup LMS_NORM
+ @{
+ */
+
+/**
+ @brief Initialization function for Q31 normalized LMS filter.
+ @param[in] S points to an instance of the Q31 normalized LMS filter structure.
+ @param[in] numTaps number of filter coefficients.
+ @param[in] pCoeffs points to coefficient buffer.
+ @param[in] pState points to state buffer.
+ @param[in] mu step size that controls filter coefficient updates.
+ @param[in] blockSize number of samples to process.
+ @param[in] postShift bit shift applied to coefficients.
+ @return none
+
+ @par Details
+ pCoeffs points to the array of filter coefficients stored in time reversed order:
+
+ {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+
+ The initial filter coefficients serve as a starting point for the adaptive filter.
+ pState points to an array of length numTaps+blockSize-1 samples,
+ where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().
+ */
+
+void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1U)) * sizeof(q31_t));
+
+ /* Assign post Shift value applied to coefficients */
+ S->postShift = postShift;
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialize reciprocal pointer table */
+ S->recipTable = (q31_t *) armRecipTableQ31;
+
+ /* Initialise Energy to zero */
+ S->energy = 0;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0;
+}
+
+/**
+ @} end of LMS_NORM group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
index 000000000..c15ad5eb4
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,297 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_norm_q15.c
+ * Description: Processing function for Q15 normalized LMS filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup LMS_NORM
+ @{
+ */
+
+/**
+ @brief Processing function for Q15 normalized LMS filter.
+ @param[in] S points to an instance of the Q15 normalized LMS filter structure
+ @param[in] pSrc points to the block of input data
+ @param[in] pRef points to the block of reference data
+ @param[out] pOut points to the block of output data
+ @param[out] pErr points to the block of error data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ Both coefficients and state variables are represented in 1.15 format and
+ multiplications yield a 2.30 result. The 2.30 intermediate results are
+ accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full
+ precision of intermediate multiplications is preserved. After all additions
+ have been performed, the accumulator is truncated to 34.15 format by
+ discarding low 15 bits. Lastly, the accumulator is saturated to yield a
+ result in 1.15 format.
+ @par
+ In this filter, filter coefficients are updated for each sample and the
+ updation of filter cofficients are saturted.
+ */
+
+void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q15_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q31_t energy; /* Energy of the input */
+ q15_t e = 0, d = 0; /* Error, reference data sample */
+ q15_t w = 0, in; /* Weight factor and state */
+ q15_t x0; /* Temporary variable to hold input sample */
+ q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Temporary variable for coefficient */
+ q31_t acc_l, acc_h; /* Temporary input */
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ int32_t uShift = (32 - lShift);
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= (((q31_t) x0 * (x0)) >> 15);
+ energy += (((q31_t) in * (in)) >> 15);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc);
+ acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16U);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q15_t) acc;
+ *pErr++ = e;
+
+ /* Calculation of 1/energy */
+ postShift = arm_recip_q15((q15_t) energy + DELTA_Q15, &oneByEnergy, S->recipTable);
+
+ /* Calculation of e * mu value */
+ errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+ /* Calculation of (e * mu) * (1/energy) value */
+ acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+ /* Weighting factor for the normalized version */
+ w = (q15_t) __SSAT((q31_t) acc, 16);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ /* Update filter coefficients */
+ while (tapCnt > 0U)
+ {
+ coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT(coef, 16);
+
+ coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT(coef, 16);
+
+ coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT(coef, 16);
+
+ coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT(coef, 16);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT(coef, 16);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q15_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState));
+ write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState));
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of LMS_NORM group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
index 000000000..e26219ed3
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,311 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_norm_q31.c
+ * Description: Processing function for the Q31 NLMS filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup LMS_NORM
+ @{
+ */
+
+/**
+ @brief Processing function for Q31 normalized LMS filter.
+ @param[in] S points to an instance of the Q31 normalized LMS filter structure
+ @param[in] pSrc points to the block of input data
+ @param[in] pRef points to the block of reference data
+ @param[out] pOut points to the block of output data
+ @param[out] pErr points to the block of error data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate
+ multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clip.
+ In order to avoid overflows completely the input signal must be scaled down by
+ log2(numTaps) bits. The reference signal should not be scaled down.
+ After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+ and saturated to 1.31 format to yield the final result.
+ The output signal and error signal are in 1.31 format.
+ @par
+ In this filter, filter coefficients are updated for each sample and the
+ updation of filter cofficients are saturted.
+ */
+
+void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q31_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q63_t energy; /* Energy of the input */
+ q31_t e = 0; /* Error data sample */
+ q31_t w = 0, in; /* Weight factor and state */
+ q31_t x0; /* Temporary variable to hold input sample */
+ q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* Temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy = (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+ energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* acc += b[N] * x[n-N] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-1] * x[n-N-1] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-2] * x[n-N-2] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-3] * x[n-N-3] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t) acc;
+ *pErr++ = e;
+
+ /* Calculates the reciprocal of energy */
+ postShift = arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+ /* Calculation of product of (e * mu) */
+ errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Weighting factor for the normalized version */
+ w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ /* Update filter coefficients */
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ pb++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ pb++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q31_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of LMS_NORM group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c
new file mode 100644
index 000000000..0fc98783a
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,262 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_q15.c
+ * Description: Processing function for Q15 LMS filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup LMS
+ @{
+ */
+
+/**
+ @brief Processing function for Q15 LMS filter.
+ @param[in] S points to an instance of the Q15 LMS filter structure
+ @param[in] pSrc points to the block of input data
+ @param[in] pRef points to the block of reference data
+ @param[out] pOut points to the block of output data
+ @param[out] pErr points to the block of error data
+ @param[in] blockSize number of samples to process
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ @par
+ In this filter, filter coefficients are updated for each sample and
+ the updation of filter cofficients are saturted.
+ */
+
+void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ const q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q15_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0; /* Error of data sample */
+ q15_t alpha; /* Intermediate constant for taps update */
+ q31_t coef; /* Temporary variable for coefficient */
+ q31_t acc_l, acc_h; /* Temporary input */
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ int32_t uShift = (32 - lShift);
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc);
+ acc = __SMLALD(read_q15x2_ia (&px), read_q15x2_ia (&pb), acc);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16U);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q15_t) acc;
+ *pErr++ = (q15_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ /* Update filter coefficients */
+ while (tapCnt > 0U)
+ {
+ coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) *pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState));
+ write_q15x2_ia (&pStateCurnt, read_q15x2_ia (&pState));
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of LMS group
+ */
diff --git a/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c
new file mode 100644
index 000000000..b0c0e2759
--- /dev/null
+++ b/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_lms_q31.c
+ * Description: Processing function for the Q31 LMS filter
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupFilters
+ */
+
+/**
+ @addtogroup LMS
+ @{
+ */
+
+/**
+ @brief Processing function for Q31 LMS filter.
+ @param[in] S points to an instance of the Q31 LMS filter structure.
+ @param[in] pSrc points to the block of input data.
+ @param[in] pRef points to the block of reference data.
+ @param[out] pOut points to the block of output data.
+ @param[out] pErr points to the block of error data.
+ @param[in] blockSize number of samples to process.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate
+ multiplication results but provides only a single guard bit.
+ Thus, if the accumulator result overflows it wraps around rather than clips.
+ In order to avoid overflows completely the input signal must be scaled down by
+ log2(numTaps) bits.
+ The reference signal should not be scaled down.
+ After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+ and saturated to 1.31 format to yield the final result.
+ The output signal and error signal are in 1.31 format.
+ @par
+ In this filter, filter coefficients are updated for each sample and
+ the updation of filter cofficients are saturted.
+ */
+
+void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ const q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q31_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0; /* Error of data sample */
+ q31_t alpha; /* Intermediate constant for taps update */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* Temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1U);
+ uint32_t lShift = 32U - uShift; /* Shift to be applied to the output */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1U)]);
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ while (blkCnt > 0U)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ /* acc += b[N] * x[n-N] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-1] * x[n-N-1] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-2] * x[n-N-2] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-3] * x[n-N-3] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t) acc;
+ *pErr++ = e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = numTaps >> 2U;
+
+ /* Update filter coefficients */
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ pb++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = numTaps % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = numTaps;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1U));
+ pb++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ Now copy the last numTaps - 1 samples to the start of the state buffer.
+ This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy data */
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 taps at a time. */
+ tapCnt = (numTaps - 1U) >> 2U;
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining taps */
+ tapCnt = (numTaps - 1U) % 0x4U;
+
+#else
+
+ /* Initialize tapCnt with number of samples */
+ tapCnt = (numTaps - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (tapCnt > 0U)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ @} end of LMS group
+ */
diff --git a/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c b/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c
new file mode 100644
index 000000000..da721fe67
--- /dev/null
+++ b/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: MatrixFunctions.c
+ * Description: Combination of all matrix function source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_mat_add_f32.c"
+#include "arm_mat_add_q15.c"
+#include "arm_mat_add_q31.c"
+#include "arm_mat_cmplx_mult_f32.c"
+#include "arm_mat_cmplx_mult_q15.c"
+#include "arm_mat_cmplx_mult_q31.c"
+#include "arm_mat_init_f32.c"
+#include "arm_mat_init_q15.c"
+#include "arm_mat_init_q31.c"
+#include "arm_mat_inverse_f32.c"
+#include "arm_mat_inverse_f64.c"
+#include "arm_mat_mult_f32.c"
+#include "arm_mat_mult_fast_q15.c"
+#include "arm_mat_mult_fast_q31.c"
+#include "arm_mat_mult_q15.c"
+#include "arm_mat_mult_q31.c"
+#include "arm_mat_scale_f32.c"
+#include "arm_mat_scale_q15.c"
+#include "arm_mat_scale_q31.c"
+#include "arm_mat_sub_f32.c"
+#include "arm_mat_sub_q15.c"
+#include "arm_mat_sub_q31.c"
+#include "arm_mat_trans_f32.c"
+#include "arm_mat_trans_q15.c"
+#include "arm_mat_trans_q31.c"
diff --git a/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
new file mode 100644
index 000000000..8e2af3172
--- /dev/null
+++ b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c
@@ -0,0 +1,631 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mat_cmplx_mult_f32.c
+ * Description: Floating-point matrix multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMatrix
+ */
+
+/**
+ @defgroup CmplxMatrixMult Complex Matrix Multiplication
+
+ Complex Matrix multiplication is only defined if the number of columns of the
+ first matrix equals the number of rows of the second matrix.
+ Multiplying an M x N matrix with an N x P matrix results
+ in an M x P matrix.
+ @par
+ When matrix size checking is enabled, the functions check:
+ - that the inner dimensions of pSrcA and pSrcB are equal;
+ - that the size of the output matrix equals the outer dimensions of pSrcA and pSrcB.
+ */
+
+
+/**
+ @addtogroup CmplxMatrixMult
+ @{
+ */
+
+/**
+ @brief Floating-point Complex matrix multiplication.
+ @param[in] pSrcA points to first input complex matrix structure
+ @param[in] pSrcB points to second input complex matrix structure
+ @param[out] pDst points to output complex matrix structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
+ */
+#if defined(ARM_MATH_NEON)
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ float32_t sumReal1, sumImag1; /* accumulator */
+ float32_t a0, b0, c0, d0;
+ float32_t a1, a1B,b1, b1B, c1, d1;
+ float32_t sumReal2, sumImag2; /* accumulator */
+
+
+ float32x4x2_t a0V, a1V;
+ float32x4_t accR0,accI0, accR1,accI1,tempR, tempI;
+ float32x2_t accum = vdup_n_f32(0);
+ float32_t *pIn1B = pSrcA->pData;
+
+ uint16_t col, i = 0U, j, rowCnt, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+ float32_t sumReal1B, sumImag1B;
+ float32_t sumReal2B, sumImag2B;
+ float32_t *pxB;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if ((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+
+ rowCnt = row >> 1;
+
+ /* Row loop */
+ while (rowCnt > 0U)
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + 2 * i;
+ pxB = px + 2 * numColsB;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0U;
+
+ /* Column loop */
+ while (col > 0U)
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sumReal1 = 0.0f;
+ sumImag1 = 0.0f;
+ sumReal1B = 0.0f;
+ sumImag1B = 0.0f;
+
+ sumReal2 = 0.0f;
+ sumImag2 = 0.0f;
+ sumReal2B = 0.0f;
+ sumImag2B = 0.0f;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pIn1 = pInA;
+ pIn1B = pIn1 + 2*numColsA;
+
+ accR0 = vdupq_n_f32(0.0);
+ accI0 = vdupq_n_f32(0.0);
+ accR1 = vdupq_n_f32(0.0);
+ accI1 = vdupq_n_f32(0.0);
+
+ /* Compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* Matrix multiplication */
+ while (colCnt > 0U)
+ {
+ /* Reading real part of complex matrix A */
+ a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2)
+ a1V = vld2q_f32(pIn1B); // load & separate real/imag pSrcA (de-interleave 2)
+
+ pIn1 += 8;
+ pIn1B += 8;
+
+ tempR[0] = *pIn2;
+ tempI[0] = *(pIn2 + 1U);
+ pIn2 += 2 * numColsB;
+
+ tempR[1] = *pIn2;
+ tempI[1] = *(pIn2 + 1U);
+ pIn2 += 2 * numColsB;
+
+ tempR[2] = *pIn2;
+ tempI[2] = *(pIn2 + 1U);
+ pIn2 += 2 * numColsB;
+
+ tempR[3] = *pIn2;
+ tempI[3] = *(pIn2 + 1U);
+ pIn2 += 2 * numColsB;
+
+ accR0 = vmlaq_f32(accR0,a0V.val[0],tempR);
+ accR0 = vmlsq_f32(accR0,a0V.val[1],tempI);
+
+ accI0 = vmlaq_f32(accI0,a0V.val[1],tempR);
+ accI0 = vmlaq_f32(accI0,a0V.val[0],tempI);
+
+ accR1 = vmlaq_f32(accR1,a1V.val[0],tempR);
+ accR1 = vmlsq_f32(accR1,a1V.val[1],tempI);
+
+ accI1 = vmlaq_f32(accI1,a1V.val[1],tempR);
+ accI1 = vmlaq_f32(accI1,a1V.val[0],tempI);
+
+ /* Decrement the loop count */
+ colCnt--;
+ }
+
+ accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0));
+ sumReal1 += accum[0] + accum[1];
+
+ accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0));
+ sumImag1 += accum[0] + accum[1];
+
+ accum = vpadd_f32(vget_low_f32(accR1), vget_high_f32(accR1));
+ sumReal1B += accum[0] + accum[1];
+
+ accum = vpadd_f32(vget_low_f32(accI1), vget_high_f32(accI1));
+ sumImag1B += accum[0] + accum[1];
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA & 3;
+
+ while (colCnt > 0U)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */
+ a1 = *pIn1;
+ a1B = *pIn1B;
+
+ c1 = *pIn2;
+
+ b1 = *(pIn1 + 1U);
+ b1B = *(pIn1B + 1U);
+
+ d1 = *(pIn2 + 1U);
+
+ sumReal1 += a1 * c1;
+ sumImag1 += b1 * c1;
+
+ sumReal1B += a1B * c1;
+ sumImag1B += b1B * c1;
+
+ pIn1 += 2U;
+ pIn1B += 2U;
+ pIn2 += 2 * numColsB;
+
+ sumReal2 -= b1 * d1;
+ sumImag2 += a1 * d1;
+
+ sumReal2B -= b1B * d1;
+ sumImag2B += a1B * d1;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ sumReal1 += sumReal2;
+ sumImag1 += sumImag2;
+
+ sumReal1B += sumReal2B;
+ sumImag1B += sumImag2B;
+
+ /* Store the result in the destination buffer */
+ *px++ = sumReal1;
+ *px++ = sumImag1;
+ *pxB++ = sumReal1B;
+ *pxB++ = sumImag1B;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + 2U * j;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* Update the pointer pInA to point to the starting address of the next 2 row */
+ i = i + 2*numColsB;
+ pInA = pInA + 4 * numColsA;
+
+ /* Decrement the row loop counter */
+ rowCnt--;
+ }
+
+ rowCnt = row & 1;
+ while (rowCnt > 0U)
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + 2 * i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0U;
+
+ /* Column loop */
+ while (col > 0U)
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sumReal1 = 0.0f;
+ sumImag1 = 0.0f;
+
+ sumReal2 = 0.0f;
+ sumImag2 = 0.0f;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pIn1 = pInA;
+
+ accR0 = vdupq_n_f32(0.0);
+ accI0 = vdupq_n_f32(0.0);
+
+ /* Compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* Matrix multiplication */
+ while (colCnt > 0U)
+ {
+ /* Reading real part of complex matrix A */
+ a0V = vld2q_f32(pIn1); // load & separate real/imag pSrcA (de-interleave 2)
+ pIn1 += 8;
+
+ tempR[0] = *pIn2;
+ tempI[0] = *(pIn2 + 1U);
+ pIn2 += 2 * numColsB;
+
+ tempR[1] = *pIn2;
+ tempI[1] = *(pIn2 + 1U);
+ pIn2 += 2 * numColsB;
+
+ tempR[2] = *pIn2;
+ tempI[2] = *(pIn2 + 1U);
+ pIn2 += 2 * numColsB;
+
+ tempR[3] = *pIn2;
+ tempI[3] = *(pIn2 + 1U);
+ pIn2 += 2 * numColsB;
+
+ accR0 = vmlaq_f32(accR0,a0V.val[0],tempR);
+ accR0 = vmlsq_f32(accR0,a0V.val[1],tempI);
+
+ accI0 = vmlaq_f32(accI0,a0V.val[1],tempR);
+ accI0 = vmlaq_f32(accI0,a0V.val[0],tempI);
+
+ /* Decrement the loop count */
+ colCnt--;
+ }
+
+ accum = vpadd_f32(vget_low_f32(accR0), vget_high_f32(accR0));
+ sumReal1 += accum[0] + accum[1];
+
+ accum = vpadd_f32(vget_low_f32(accI0), vget_high_f32(accI0));
+ sumImag1 += accum[0] + accum[1];
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA & 3;
+
+ while (colCnt > 0U)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2)*b(2,1) + ... + a(m,p)*b(p,n) */
+ a1 = *pIn1;
+ c1 = *pIn2;
+
+ b1 = *(pIn1 + 1U);
+ d1 = *(pIn2 + 1U);
+
+ sumReal1 += a1 * c1;
+ sumImag1 += b1 * c1;
+
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ sumReal2 -= b1 * d1;
+ sumImag2 += a1 * d1;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ sumReal1 += sumReal2;
+ sumImag1 += sumImag2;
+
+ /* Store the result in the destination buffer */
+ *px++ = sumReal1;
+ *px++ = sumImag1;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + 2U * j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ }
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + 2 * numColsA;
+
+ /* Decrement the row loop counter */
+ rowCnt--;
+
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+#else
+arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */
+ float32_t *pInA = pSrcA->pData; /* Input data matrix pointer A */
+ float32_t *pOut = pDst->pData; /* Output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */
+ float32_t sumReal, sumImag; /* Accumulator */
+ float32_t a1, b1, c1, d1;
+ uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ float32_t a0, b0, c0, d0;
+#endif
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if ((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) ||
+ (pSrcB->numCols != pDst->numCols) )
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + 2 * i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0U;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sumReal = 0.0f;
+ sumImag = 0.0f;
+
+ /* Initiate pointer pIn1 to point to starting address of column being processed */
+ pIn1 = pInA;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2U;
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+
+ /* Reading real part of complex matrix A */
+ a0 = *pIn1;
+
+ /* Reading real part of complex matrix B */
+ c0 = *pIn2;
+
+ /* Reading imaginary part of complex matrix A */
+ b0 = *(pIn1 + 1U);
+
+ /* Reading imaginary part of complex matrix B */
+ d0 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += a0 * c0;
+ sumImag += b0 * c0;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= b0 * d0;
+ sumImag += a0 * d0;
+
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ a1 = *(pIn1 );
+ c1 = *(pIn2 );
+ b1 = *(pIn1 + 1U);
+ d1 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += a1 * c1;
+ sumImag += b1 * c1;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= b1 * d1;
+ sumImag += a1 * d1;
+
+ a0 = *(pIn1 );
+ c0 = *(pIn2 );
+ b0 = *(pIn1 + 1U);
+ d0 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += a0 * c0;
+ sumImag += b0 * c0;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= b0 * d0;
+ sumImag += a0 * d0;
+
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+
+ a1 = *(pIn1 );
+ c1 = *(pIn2 );
+ b1 = *(pIn1 + 1U);
+ d1 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += a1 * c1;
+ sumImag += b1 * c1;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= b1 * d1;
+ sumImag += a1 * d1;
+
+ /* Decrement loop count */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ colCnt = numColsA;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (colCnt > 0U)
+ {
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+ a1 = *(pIn1 );
+ c1 = *(pIn2 );
+ b1 = *(pIn1 + 1U);
+ d1 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += a1 * c1;
+ sumImag += b1 * c1;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= b1 * d1;
+ sumImag += a1 * d1;
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ /* Store result in destination buffer */
+ *px++ = sumReal;
+ *px++ = sumImag;
+
+ /* Update pointer pIn2 to point to starting address of next column */
+ j++;
+ pIn2 = pSrcB->pData + 2U * j;
+
+ /* Decrement column loop counter */
+ col--;
+
+ } while (col > 0U);
+
+ /* Update pointer pInA to point to starting address of next row */
+ i = i + numColsB;
+ pInA = pInA + 2 * numColsA;
+
+ /* Decrement row loop counter */
+ row--;
+
+ } while (row > 0U);
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of MatrixMult group
+ */
diff --git a/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
new file mode 100644
index 000000000..4c5a45b72
--- /dev/null
+++ b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c
@@ -0,0 +1,340 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cmplx_mat_mult_q15.c
+ * Description: Q15 complex matrix multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMatrix
+ */
+
+/**
+ @addtogroup CmplxMatrixMult
+ @{
+ */
+
+/**
+ @brief Q15 Complex matrix multiplication.
+ @param[in] pSrcA points to first input complex matrix structure
+ @param[in] pSrcB points to second input complex matrix structure
+ @param[out] pDst points to output complex matrix structure
+ @param[in] pScratch points to an array for storing intermediate results
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
+
+ @par Conditions for optimum performance
+ Input, output and state buffers should be aligned by 32-bit
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator. The inputs to the
+ multiplications are in 1.15 format and multiplications yield a 2.30 result.
+ The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ This approach provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
+ truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ */
+
+arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pSrcBT = pScratch; /* input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
+ q63_t sumReal, sumImag; /* accumulator */
+ uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */
+ arm_status status; /* Status of matrix multiplication */
+
+#if defined (ARM_MATH_DSP)
+ q31_t prod1, prod2;
+ q31_t pSourceA, pSourceB;
+#else
+ q15_t a, b, c, d;
+#endif /* #if defined (ARM_MATH_DSP) */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if ((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) ||
+ (pSrcB->numCols != pDst->numCols) )
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* The pointer px is set to starting address of column being processed */
+ px = pSrcBT + i;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = numColsB >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ a second loop below computes the remaining 1 to 3 samples. */
+ while (col > 0U)
+ {
+ /* Read two elements from row */
+ write_q15x2 (px, read_q15x2_ia (&pInB));
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB * 2;
+
+ /* Read two elements from row */
+ write_q15x2 (px, read_q15x2_ia (&pInB));
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB * 2;
+
+ /* Read two elements from row */
+ write_q15x2 (px, read_q15x2_ia (&pInB));
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB * 2;
+
+ /* Read two elements from row */
+ write_q15x2 (px, read_q15x2_ia (&pInB));
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB * 2;
+
+ /* Decrement column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ col = numColsB;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (col > 0U)
+ {
+ /* Read two elements from row */
+ write_q15x2 (px, read_q15x2_ia (&pInB));
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB * 2;
+
+ /* Decrement column loop counter */
+ col--;
+ }
+
+ i = i + 2U;
+
+ /* Decrement row loop counter */
+ row--;
+
+ } while (row > 0U);
+
+ /* Reset variables for usage in following multiplication process */
+ row = numRowsA;
+ i = 0U;
+ px = pDst->pData;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* For every row wise process, column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */
+ pInB = pSrcBT;
+
+ /* column loop */
+ do
+ {
+ /* Set variable sum, that acts as accumulator, to zero */
+ sumReal = 0;
+ sumImag = 0;
+
+ /* Initiate pointer pInA to point to starting address of column being processed */
+ pInA = pSrcA->pData + i * 2;
+
+ /* Apply loop unrolling and compute 2 MACs simultaneously. */
+ colCnt = numColsA >> 1U;
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+
+#if defined (ARM_MATH_DSP)
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA = read_q15x2_ia ((q15_t **) &pInA);
+ pSourceB = read_q15x2_ia ((q15_t **) &pInB);
+
+ /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+ prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+ prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+ prod2 = __SMUADX(pSourceA, pSourceB);
+ sumReal += (q63_t) prod1;
+ sumImag += (q63_t) prod2;
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA = read_q15x2_ia ((q15_t **) &pInA);
+ pSourceB = read_q15x2_ia ((q15_t **) &pInB);
+
+ /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+ prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+ prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+ prod2 = __SMUADX(pSourceA, pSourceB);
+ sumReal += (q63_t) prod1;
+ sumImag += (q63_t) prod2;
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+ /* read real and imag values from pSrcA buffer */
+ a = *pInA;
+ b = *(pInA + 1U);
+ /* read real and imag values from pSrcB buffer */
+ c = *pInB;
+ d = *(pInB + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += (q31_t) a *c;
+ sumImag += (q31_t) a *d;
+ sumReal -= (q31_t) b *d;
+ sumImag += (q31_t) b *c;
+
+ /* read next real and imag values from pSrcA buffer */
+ a = *(pInA + 2U);
+ b = *(pInA + 3U);
+ /* read next real and imag values from pSrcB buffer */
+ c = *(pInB + 2U);
+ d = *(pInB + 3U);
+
+ /* update pointer */
+ pInA += 4U;
+
+ /* Multiply and Accumlates */
+ sumReal += (q31_t) a * c;
+ sumImag += (q31_t) a * d;
+ sumReal -= (q31_t) b * d;
+ sumImag += (q31_t) b * c;
+ /* update pointer */
+ pInB += 4U;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ /* process odd column samples */
+ if ((numColsA & 0x1U) > 0U)
+ {
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+
+#if defined (ARM_MATH_DSP)
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA = read_q15x2_ia ((q15_t **) &pInA);
+ pSourceB = read_q15x2_ia ((q15_t **) &pInB);
+
+ /* Multiply and Accumlates */
+#ifdef ARM_MATH_BIG_ENDIAN
+ prod1 = -__SMUSD(pSourceA, pSourceB);
+#else
+ prod1 = __SMUSD(pSourceA, pSourceB);
+#endif
+ prod2 = __SMUADX(pSourceA, pSourceB);
+ sumReal += (q63_t) prod1;
+ sumImag += (q63_t) prod2;
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ a = *pInA++;
+ b = *pInA++;
+ c = *pInB++;
+ d = *pInB++;
+
+ /* Multiply and Accumlates */
+ sumReal += (q31_t) a * c;
+ sumImag += (q31_t) a * d;
+ sumReal -= (q31_t) b * d;
+ sumImag += (q31_t) b * c;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ }
+
+ /* Saturate and store result in destination buffer */
+ *px++ = (q15_t) (__SSAT(sumReal >> 15, 16));
+ *px++ = (q15_t) (__SSAT(sumImag >> 15, 16));
+
+ /* Decrement column loop counter */
+ col--;
+
+ } while (col > 0U);
+
+ i = i + numColsA;
+
+ /* Decrement row loop counter */
+ row--;
+
+ } while (row > 0U);
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ @} end of MatrixMult group
+ */
diff --git a/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
new file mode 100644
index 000000000..7b458f92b
--- /dev/null
+++ b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mat_cmplx_mult_q31.c
+ * Description: Floating-point matrix multiplication
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMatrix
+ */
+
+/**
+ @addtogroup CmplxMatrixMult
+ @{
+ */
+
+/**
+ @brief Q31 Complex matrix multiplication.
+ @param[in] pSrcA points to first input complex matrix structure
+ @param[in] pSrcB points to second input complex matrix structure
+ @param[out] pDst points to output complex matrix structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The accumulator has a 2.62 format and maintains full precision of the intermediate
+ multiplication results but provides only a single guard bit. There is no saturation
+ on intermediate additions. Thus, if the accumulator overflows it wraps around and
+ distorts the result. The input signals should be scaled down to avoid intermediate
+ overflows. The input is thus scaled down by log2(numColsA) bits
+ to avoid overflows, as a total of numColsA additions are performed internally.
+ The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ */
+
+arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* Input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* Input data matrix pointer B */
+ q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */
+ q31_t *pOut = pDst->pData; /* Output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */
+ q63_t sumReal, sumImag; /* Accumulator */
+ q31_t a1, b1, c1, d1;
+ uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t a0, b0, c0, d0;
+#endif
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if ((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) ||
+ (pSrcB->numCols != pDst->numCols) )
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + 2 * i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0U;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sumReal = 0.0;
+ sumImag = 0.0;
+
+ /* Initiate pointer pIn1 to point to starting address of column being processed */
+ pIn1 = pInA;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2U;
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+
+ /* Reading real part of complex matrix A */
+ a0 = *pIn1;
+
+ /* Reading real part of complex matrix B */
+ c0 = *pIn2;
+
+ /* Reading imaginary part of complex matrix A */
+ b0 = *(pIn1 + 1U);
+
+ /* Reading imaginary part of complex matrix B */
+ d0 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += (q63_t) a0 * c0;
+ sumImag += (q63_t) b0 * c0;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= (q63_t) b0 * d0;
+ sumImag += (q63_t) a0 * d0;
+
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ a1 = *(pIn1 );
+ c1 = *(pIn2 );
+ b1 = *(pIn1 + 1U);
+ d1 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += (q63_t) a1 * c1;
+ sumImag += (q63_t) b1 * c1;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= (q63_t) b1 * d1;
+ sumImag += (q63_t) a1 * d1;
+
+ a0 = *(pIn1 );
+ c0 = *(pIn2 );
+ b0 = *(pIn1 + 1U);
+ d0 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += (q63_t) a0 * c0;
+ sumImag += (q63_t) b0 * c0;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= (q63_t) b0 * d0;
+ sumImag += (q63_t) a0 * d0;
+
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+
+ a1 = *(pIn1 );
+ c1 = *(pIn2 );
+ b1 = *(pIn1 + 1U);
+ d1 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += (q63_t) a1 * c1;
+ sumImag += (q63_t) b1 * c1;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= (q63_t) b1 * d1;
+ sumImag += (q63_t) a1 * d1;
+
+ /* Decrement loop count */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ colCnt = numColsA;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (colCnt > 0U)
+ {
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+ a1 = *(pIn1 );
+ c1 = *(pIn2 );
+ b1 = *(pIn1 + 1U);
+ d1 = *(pIn2 + 1U);
+
+ /* Multiply and Accumlates */
+ sumReal += (q63_t) a1 * c1;
+ sumImag += (q63_t) b1 * c1;
+
+ /* update pointers */
+ pIn1 += 2U;
+ pIn2 += 2 * numColsB;
+
+ /* Multiply and Accumlates */
+ sumReal -= (q63_t) b1 * d1;
+ sumImag += (q63_t) a1 * d1;
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ /* Store result in destination buffer */
+ *px++ = (q31_t) clip_q63_to_q31(sumReal >> 31);
+ *px++ = (q31_t) clip_q63_to_q31(sumImag >> 31);
+
+ /* Update pointer pIn2 to point to starting address of next column */
+ j++;
+ pIn2 = pSrcB->pData + 2U * j;
+
+ /* Decrement column loop counter */
+ col--;
+
+ } while (col > 0U);
+
+ /* Update pointer pInA to point to starting address of next row */
+ i = i + numColsB;
+ pInA = pInA + 2 * numColsA;
+
+ /* Decrement row loop counter */
+ row--;
+
+ } while (row > 0U);
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ @} end of MatrixMult group
+ */
diff --git a/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c
new file mode 100644
index 000000000..4607e075a
--- /dev/null
+++ b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c
@@ -0,0 +1,673 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mat_inverse_f64.c
+ * Description: Floating-point matrix inverse
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMatrix
+ */
+
+
+/**
+ @addtogroup MatrixInv
+ @{
+ */
+
+/**
+ @brief Floating-point (64 bit) matrix inverse.
+ @param[in] pSrc points to input matrix structure
+ @param[out] pDst points to output matrix structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
+ - \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible)
+ */
+
+arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * pSrc,
+ arm_matrix_instance_f64 * pDst)
+{
+ float64_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float64_t *pOut = pDst->pData; /* output data matrix pointer */
+ float64_t *pInT1, *pInT2; /* Temporary input data matrix pointer */
+ float64_t *pOutT1, *pOutT2; /* Temporary output data matrix pointer */
+ float64_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */
+ uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */
+ uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */
+
+#if defined (ARM_MATH_DSP)
+ float64_t maxC; /* maximum value in the column */
+
+ float64_t Xchg, in = 0.0, in1; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if ((pSrc->numRows != pSrc->numCols) ||
+ (pDst->numRows != pDst->numCols) ||
+ (pSrc->numRows != pDst->numRows) )
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _
+ * | a11 a12 | 1 0 | | X11 X12 |
+ * | | | = | |
+ * |_ a21 a22 | 0 1 _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for column i is the greatest of the column.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is not the most significant of the columns, exchange that row with a row
+ * below it that does contain the most significant value in column i. If the most
+ * significant value of the column is zero, then an inverse to that matrix does not exist.
+ * The most significant value of the column is the absolute maximum.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
+ * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pOutT1 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while (rowCnt > 0U)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while (j > 0U)
+ {
+ *pOutT1++ = 0.0;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pOutT1++ = 1.0;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1U;
+ while (j > 0U)
+ {
+ *pOutT1++ = 0.0;
+ j--;
+ }
+
+ /* Decrement loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0U;
+
+ while (loopCnt > 0U)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pOutT1 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Grab the most significant value from column l */
+ maxC = 0;
+ for (i = l; i < numRows; i++)
+ {
+ maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+ pInT1 += numCols;
+ }
+
+ /* Update the status if the matrix is singular */
+ if (maxC == 0.0)
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Restore pInT1 */
+ pInT1 = pIn;
+
+ /* Destination pointer modifier */
+ k = 1U;
+
+ /* Check if the pivot element is the most significant of the column */
+ if ( (in > 0.0 ? in : -in) != maxC)
+ {
+ /* Loop over the number rows present below */
+ i = numRows - (l + 1U);
+
+ while (i > 0U)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pOutT2 = pOutT1 + (numCols * k);
+
+ /* Look for the most significant element to
+ * replace in the rows below */
+ if ((*pInT2 > 0.0 ? *pInT2: -*pInT2) == maxC)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = numCols - l;
+
+ while (j > 0U)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while (j > 0U)
+ {
+ /* Exchange the row elements of the destination matrix */
+ Xchg = *pOutT2;
+ *pOutT2++ = *pOutT1;
+ *pOutT1++ = Xchg;
+
+ /* Decrement loop counter */
+ j--;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1U;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+
+ /* Decrement loop counter */
+ i--;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if ((flag != 1U) && (in == 0.0))
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pInT2 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *pPivotRowIn;
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = (numCols - l);
+
+ while (j > 0U)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ in1 = *pInT1;
+ *pInT1++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while (j > 0U)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ in1 = *pInT2;
+ *pInT2++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pInT2 = pOut;
+
+ /* index used to check for pivot element */
+ i = 0U;
+
+ /* Loop over number of rows */
+ /* to be replaced by the sum of that row and a multiple of row i */
+ k = numRows;
+
+ while (k > 0U)
+ {
+ /* Check for the pivot element */
+ if (i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+
+ pInT2 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ j = (numCols - l);
+
+ while (j > 0U)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT1;
+ *pInT1++ = in1 - (in * *pPRT_in++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ j = numCols;
+
+ while (j > 0U)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT2;
+ *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+ /* Decrement loop counter */
+ j--;
+ }
+
+ }
+
+ /* Increment temporary input pointer */
+ pInT1 = pInT1 + l;
+
+ /* Decrement loop counter */
+ k--;
+
+ /* Increment pivot index */
+ i++;
+ }
+
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#else
+
+ float64_t Xchg, in = 0.0; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0U, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if ((pSrc->numRows != pSrc->numCols) ||
+ (pDst->numRows != pDst->numCols) ||
+ (pSrc->numRows != pDst->numRows) )
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _ _ _ _ _
+ * | | a11 a12 | | | 1 0 | | | X11 X12 |
+ * | | | | | | | = | |
+ * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for row i is zero.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is zero, exchange that row with a row below it that does not
+ * contain a zero in column i. If this is not possible, then an inverse
+ * to that matrix does not exist.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, src).
+ * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pOutT1 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while (rowCnt > 0U)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while (j > 0U)
+ {
+ *pOutT1++ = 0.0;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pOutT1++ = 1.0;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1U;
+ while (j > 0U)
+ {
+ *pOutT1++ = 0.0;
+ j--;
+ }
+
+ /* Decrement loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0U;
+
+ while (loopCnt > 0U)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pOutT1 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Destination pointer modifier */
+ k = 1U;
+
+ /* Check if the pivot element is zero */
+ if (*pInT1 == 0.0)
+ {
+ /* Loop over the number rows present below */
+ for (i = (l + 1U); i < numRows; i++)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pOutT2 = pOutT1 + (numCols * k);
+
+ /* Check if there is a non zero pivot element to
+ * replace in the rows below */
+ if (*pInT2 != 0.0)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0U; j < (numCols - l); j++)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+ }
+
+ for (j = 0U; j < numCols; j++)
+ {
+ Xchg = *pOutT2;
+ *pOutT2++ = *pOutT1;
+ *pOutT1++ = Xchg;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1U;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if ((flag != 1U) && (in == 0.0))
+ {
+ return ARM_MATH_SINGULAR;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pOutT1 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *(pIn + (l * numCols));
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0U; j < (numCols - l); j++)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ *pInT1 = *pInT1 / in;
+ pInT1++;
+ }
+ for (j = 0U; j < numCols; j++)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ *pOutT1 = *pOutT1 / in;
+ pOutT1++;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pOutT1 = pOut;
+
+ for (i = 0U; i < numRows; i++)
+ {
+ /* Check for the pivot element */
+ if (i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+ pOutT1 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ for (j = 0U; j < (numCols - l); j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pInT1 = *pInT1 - (in * *pPRT_in++);
+ pInT1++;
+ }
+
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ for (j = 0U; j < numCols; j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pOutT1 = *pOutT1 - (in * *pPRT_pDst++);
+ pOutT1++;
+ }
+
+ }
+
+ /* Increment temporary input pointer */
+ pInT1 = pInT1 + l;
+ }
+
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+
+ /* Increment the index modifier */
+ l++;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ if ((flag != 1U) && (in == 0.0))
+ {
+ pIn = pSrc->pData;
+ for (i = 0; i < numRows * numCols; i++)
+ {
+ if (pIn[i] != 0.0)
+ break;
+ }
+
+ if (i == numRows * numCols)
+ status = ARM_MATH_SINGULAR;
+ }
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ @} end of MatrixInv group
+ */
diff --git a/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
index 000000000..670ace1f4
--- /dev/null
+++ b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,483 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mat_mult_fast_q15.c
+ * Description: Q15 matrix multiplication (fast variant)
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMatrix
+ */
+
+/**
+ @addtogroup MatrixMult
+ @{
+ */
+
+/**
+ @brief Q15 matrix multiplication (fast variant).
+ @param[in] pSrcA points to the first input matrix structure
+ @param[in] pSrcB points to the second input matrix structure
+ @param[out] pDst points to output matrix structure
+ @param[in] pState points to the array for storing intermediate results
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
+
+ @par Scaling and Overflow Behavior
+ The difference between the function \ref arm_mat_mult_q15() and this fast variant is that
+ the fast variant use a 32-bit rather than a 64-bit accumulator.
+ The result of each 1.15 x 1.15 multiplication is truncated to
+ 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ format. Finally, the accumulator is saturated and converted to a 1.15 result.
+ @par
+ The fast version has the same overflow behavior as the standard version but provides
+ less precision since it discards the low 16 bits of each multiplication result.
+ In order to avoid overflows completely the input signals must be scaled down.
+ Scale down one of the input matrices by log2(numColsA) bits to avoid overflows,
+ as a total of numColsA additions are computed internally for each output element.
+ @remark
+ Refer to \ref arm_mat_mult_q15() for a slower implementation of this function
+ which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState)
+{
+ q31_t sum; /* Accumulator */
+ q15_t *pSrcBT = pState; /* Input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* Input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* Input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* Number of rows of input matrix A */
+ uint32_t col, i = 0U, row = numRowsB, colCnt; /* Loop counters */
+ arm_status status; /* Status of matrix multiplication */
+
+#if defined (ARM_MATH_DSP)
+ q31_t in; /* Temporary variable to hold the input value */
+ q31_t inA1, inB1, inA2, inB2;
+ q31_t sum2, sum3, sum4;
+ q15_t *pInA2, *pInB2, *px2;
+ uint32_t j = 0;
+#else
+ q15_t in; /* Temporary variable to hold the input value */
+ q15_t inA1, inB1, inA2, inB2;
+#endif /* #if defined (ARM_MATH_DSP) */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if ((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) ||
+ (pSrcB->numCols != pDst->numCols) )
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* The pointer px is set to starting address of column being processed */
+ px = pSrcBT + i;
+
+ /* Apply loop unrolling and exchange columns with row elements */
+ col = numColsB >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (col > 0U)
+ {
+
+#if defined (ARM_MATH_DSP)
+
+ /* Read two elements from row */
+ in = read_q15x2_ia ((q15_t **) &pInB);
+
+ /* Unpack and store one element in destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+ *px = (q15_t) in;
+#else
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store second element in destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+#else
+ *px = (q15_t) in;
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB;
+
+ in = read_q15x2_ia ((q15_t **) &pInB);
+#ifndef ARM_MATH_BIG_ENDIAN
+ *px = (q15_t) in;
+#else
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += numRowsB;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+#else
+ *px = (q15_t) in;
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += numRowsB;
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+ /* Read one element from row */
+ in = *pInB++;
+
+ /* Store one element in destination */
+ *px = in;
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB;
+
+ in = *pInB++;
+ *px = in;
+ px += numRowsB;
+
+ in = *pInB++;
+ *px = in;
+ px += numRowsB;
+
+ in = *pInB++;
+ *px = in;
+ px += numRowsB;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4U;
+
+ while (col > 0U)
+ {
+ /* Read and store input element in destination */
+ *px = *pInB++;
+
+ /* Update pointer px to point to next row of transposed matrix */
+ px += numRowsB;
+
+ /* Decrement column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement row loop counter */
+ row--;
+
+ } while (row > 0U);
+
+ /* Reset variables for usage in following multiplication process */
+ row = numRowsA;
+ i = 0U;
+ px = pDst->pData;
+
+#if defined (ARM_MATH_DSP)
+ /* Process two rows from matrix A at a time and output two rows at a time */
+ row = row >> 1U;
+ px2 = px + numColsB;
+#endif
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ while (row > 0U)
+ {
+ /* For every row wise process, column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, pIn2 pointer is set to starting address of transposed pSrcB data */
+ pInB = pSrcBT;
+
+#if defined (ARM_MATH_DSP)
+ /* Process two (transposed) columns from matrix B at a time */
+ col = col >> 1U;
+ j = 0;
+#endif
+
+ /* column loop */
+ while (col > 0U)
+ {
+ /* Set variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate pointer pInA to point to starting address of column being processed */
+ pInA = pSrcA->pData + i;
+
+#if defined (ARM_MATH_DSP)
+ sum2 = 0;
+ sum3 = 0;
+ sum4 = 0;
+ pInB = pSrcBT + j;
+ pInA2 = pInA + numColsA;
+ pInB2 = pInB + numRowsB;
+
+ /* Read in two elements at once - alows dual MAC instruction */
+ colCnt = numColsA >> 1U;
+#else
+ colCnt = numColsA >> 2U;
+#endif
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+
+#if defined (ARM_MATH_DSP)
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ inA1 = read_q15x2_ia ((q15_t **) &pInA);
+ inB1 = read_q15x2_ia ((q15_t **) &pInB);
+
+ inA2 = read_q15x2_ia ((q15_t **) &pInA2);
+ inB2 = read_q15x2_ia ((q15_t **) &pInB2);
+
+ /* Multiply and Accumlates */
+ sum = __SMLAD(inA1, inB1, sum);
+ sum2 = __SMLAD(inA1, inB2, sum2);
+ sum3 = __SMLAD(inA2, inB1, sum3);
+ sum4 = __SMLAD(inA2, inB2, sum4);
+#else
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ /* Multiply and Accumlates */
+ sum += inA1 * inB1;
+
+ inA2 = *pInA++;
+ inB2 = *pInB++;
+ sum += inA2 * inB2;
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ sum += inA1 * inB1;
+
+ inA2 = *pInA++;
+ inB2 = *pInB++;
+ sum += inA2 * inB2;
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ /* process odd column samples */
+#if defined (ARM_MATH_DSP)
+ if (numColsA & 1U) {
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ inA2 = *pInA2++;
+ inB2 = *pInB2++;
+ sum += inA1 * inB1;
+ sum2 += inA1 * inB2;
+ sum3 += inA2 * inB1;
+ sum4 += inA2 * inB2;
+ }
+#else
+ colCnt = numColsA % 0x4U;
+
+ while (colCnt > 0U)
+ {
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+ sum += (q31_t) *pInA++ * *pInB++;
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Saturate and store result in destination buffer */
+ *px++ = (q15_t) (sum >> 15);
+
+#if defined (ARM_MATH_DSP)
+ *px++ = (q15_t) (sum2 >> 15);
+ *px2++ = (q15_t) (sum3 >> 15);
+ *px2++ = (q15_t) (sum4 >> 15);
+ j += numRowsB * 2;
+#endif
+
+ /* Decrement column loop counter */
+ col--;
+
+ }
+
+ i = i + numColsA;
+
+#if defined (ARM_MATH_DSP)
+ i = i + numColsA;
+ px = px2 + (numColsB & 1U);
+ px2 = px + numColsB;
+#endif
+
+ /* Decrement row loop counter */
+ row--;
+
+ }
+
+ /* Compute any remaining odd row/column below */
+
+#if defined (ARM_MATH_DSP)
+
+ /* Compute remaining output column */
+ if (numColsB & 1U) {
+
+ /* Avoid redundant computation of last element */
+ row = numRowsA & (~0x1);
+
+ /* Point to remaining unfilled column in output matrix */
+ px = pDst->pData + numColsB-1;
+ pInA = pSrcA->pData;
+
+ /* row loop */
+ while (row > 0)
+ {
+
+ /* point to last column in matrix B */
+ pInB = pSrcBT + numRowsB * (numColsB-1);
+
+ /* Set variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Compute 4 columns at once */
+ colCnt = numColsA >> 2U;
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+ inA1 = read_q15x2_ia ((q15_t **) &pInA);
+ inA2 = read_q15x2_ia ((q15_t **) &pInA);
+ inB1 = read_q15x2_ia ((q15_t **) &pInB);
+ inB2 = read_q15x2_ia ((q15_t **) &pInB);
+
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ colCnt = numColsA & 3U;
+ while (colCnt > 0U) {
+ sum += (q31_t) (*pInA++) * (*pInB++);
+ colCnt--;
+ }
+
+ /* Store result in destination buffer */
+ *px = (q15_t) (sum >> 15);
+ px += numColsB;
+
+ /* Decrement row loop counter */
+ row--;
+ }
+ }
+
+ /* Compute remaining output row */
+ if (numRowsA & 1U) {
+
+ /* point to last row in output matrix */
+ px = pDst->pData + (numColsB) * (numRowsA-1);
+
+ pInB = pSrcBT;
+ col = numColsB;
+ i = 0U;
+
+ /* col loop */
+ while (col > 0)
+ {
+ /* point to last row in matrix A */
+ pInA = pSrcA->pData + (numRowsA-1) * numColsA;
+
+ /* Set variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Compute 4 columns at once */
+ colCnt = numColsA >> 2U;
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+ inA1 = read_q15x2_ia ((q15_t **) &pInA);
+ inA2 = read_q15x2_ia ((q15_t **) &pInA);
+ inB1 = read_q15x2_ia ((q15_t **) &pInB);
+ inB2 = read_q15x2_ia ((q15_t **) &pInB);
+
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ colCnt = numColsA % 4U;
+ while (colCnt > 0U) {
+ sum += (q31_t) (*pInA++) * (*pInB++);
+
+ colCnt--;
+ }
+
+ /* Store result in destination buffer */
+ *px++ = (q15_t) (sum >> 15);
+
+ /* Decrement column loop counter */
+ col--;
+ }
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ @} end of MatrixMult group
+ */
diff --git a/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
index 000000000..011959adb
--- /dev/null
+++ b/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,374 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mat_mult_fast_q31.c
+ * Description: Q31 matrix multiplication (fast variant)
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupMatrix
+ */
+
+/**
+ @addtogroup MatrixMult
+ @{
+ */
+
+/**
+ @brief Q31 matrix multiplication (fast variant).
+ @param[in] pSrcA points to the first input matrix structure
+ @param[in] pSrcB points to the second input matrix structure
+ @param[out] pDst points to output matrix structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
+
+ @par Scaling and Overflow Behavior
+ The difference between the function \ref arm_mat_mult_q31() and this fast variant is that
+ the fast variant use a 32-bit rather than a 64-bit accumulator.
+ The result of each 1.31 x 1.31 multiplication is truncated to
+ 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ format. Finally, the accumulator is saturated and converted to a 1.31 result.
+ @par
+ The fast version has the same overflow behavior as the standard version but provides
+ less precision since it discards the low 32 bits of each multiplication result.
+ In order to avoid overflows completely the input signals must be scaled down.
+ Scale down one of the input matrices by log2(numColsA) bits to avoid overflows,
+ as a total of numColsA additions are computed internally for each output element.
+ @remark
+ Refer to \ref arm_mat_mult_q31() for a slower implementation of this function
+ which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pInA = pSrcA->pData; /* Input data matrix pointer A */
+ q31_t *pInB = pSrcB->pData; /* Input data matrix pointer B */
+ q31_t *pInA2;
+ q31_t *px; /* Temporary output data matrix pointer */
+ q31_t *px2;
+ q31_t sum1, sum2, sum3, sum4; /* Accumulator */
+ q31_t inA1, inA2, inB1, inB2;
+ uint16_t numRowsA = pSrcA->numRows; /* Number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* Number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* Number of columns of input matrix A */
+ uint32_t col, i = 0U, j, row = numRowsA, colCnt; /* Loop counters */
+ arm_status status; /* Status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if ((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) ||
+ (pSrcB->numCols != pDst->numCols) )
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ px = pDst->pData;
+
+ row = row >> 1U;
+ px2 = px + numColsB;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ while (row > 0U)
+ {
+ /* For every row wise process, column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, pIn2 pointer is set to starting address of pSrcB data */
+ pInB = pSrcB->pData;
+
+ j = 0U;
+
+ col = col >> 1U;
+
+ /* column loop */
+ while (col > 0U)
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum1 = 0;
+ sum2 = 0;
+ sum3 = 0;
+ sum4 = 0;
+
+ /* Initiate data pointers */
+ pInA = pSrcA->pData + i;
+ pInB = pSrcB->pData + j;
+ pInA2 = pInA + numColsA;
+
+ colCnt = numColsA;
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+ /* c(m,n) = a(1,1) * b(1,1) + a(1,2) * b(2,1) + .... + a(m,p) * b(p,n) */
+
+ inA1 = *pInA++;
+ inB1 = pInB[0];
+ inA2 = *pInA2++;
+ inB2 = pInB[1];
+ pInB += numColsB;
+
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(inA1, inB1, sum1);
+ sum2 = __SMMLA(inA1, inB2, sum2);
+ sum3 = __SMMLA(inA2, inB1, sum3);
+ sum4 = __SMMLA(inA2, inB2, sum4);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32);
+ sum2 = (q31_t) ((((q63_t) sum2 << 32) + ((q63_t) inA1 * inB2)) >> 32);
+ sum3 = (q31_t) ((((q63_t) sum3 << 32) + ((q63_t) inA2 * inB1)) >> 32);
+ sum4 = (q31_t) ((((q63_t) sum4 << 32) + ((q63_t) inA2 * inB2)) >> 32);
+#endif
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+ *px++ = sum1 << 1;
+ *px++ = sum2 << 1;
+ *px2++ = sum3 << 1;
+ *px2++ = sum4 << 1;
+
+ j += 2;
+
+ /* Decrement column loop counter */
+ col--;
+ }
+
+ i = i + (numColsA << 1U);
+ px = px2 + (numColsB & 1U);
+ px2 = px + numColsB;
+
+ /* Decrement row loop counter */
+ row--;
+ }
+
+ /* Compute any remaining odd row/column below */
+
+ /* Compute remaining output column */
+ if (numColsB & 1U) {
+
+ /* Avoid redundant computation of last element */
+ row = numRowsA & (~1U);
+
+ /* Point to remaining unfilled column in output matrix */
+ px = pDst->pData + numColsB-1;
+ pInA = pSrcA->pData;
+
+ /* row loop */
+ while (row > 0)
+ {
+
+ /* point to last column in matrix B */
+ pInB = pSrcB->pData + numColsB-1;
+
+ /* Set variable sum1, that acts as accumulator, to zero */
+ sum1 = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 columns at a time. */
+ colCnt = numColsA >> 2U;
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(*pInA++, *pInB, sum1);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32);
+#endif
+ pInB += numColsB;
+
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(*pInA++, *pInB, sum1);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32);
+#endif
+ pInB += numColsB;
+
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(*pInA++, *pInB, sum1);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32);
+#endif
+ pInB += numColsB;
+
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(*pInA++, *pInB, sum1);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32);
+#endif
+ pInB += numColsB;
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining column */
+ colCnt = numColsA % 4U;
+
+#else
+
+ /* Initialize colCnt with number of columns */
+ colCnt = numColsA;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (colCnt > 0U) {
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(*pInA++, *pInB, sum1);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32);
+#endif
+ pInB += numColsB;
+
+ colCnt--;
+ }
+
+ /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+ *px = sum1 << 1;
+ px += numColsB;
+
+ /* Decrement row loop counter */
+ row--;
+ }
+ }
+
+ /* Compute remaining output row */
+ if (numRowsA & 1U) {
+
+ /* point to last row in output matrix */
+ px = pDst->pData + (numColsB) * (numRowsA-1);
+
+ col = numColsB;
+ i = 0U;
+
+ /* col loop */
+ while (col > 0)
+ {
+
+ /* point to last row in matrix A */
+ pInA = pSrcA->pData + (numRowsA-1) * numColsA;
+ pInB = pSrcB->pData + i;
+
+ /* Set variable sum1, that acts as accumulator, to zero */
+ sum1 = 0;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 columns at a time. */
+ colCnt = numColsA >> 2U;
+
+ /* matrix multiplication */
+ while (colCnt > 0U)
+ {
+ inA1 = *pInA++;
+ inA2 = *pInA++;
+ inB1 = *pInB;
+ pInB += numColsB;
+ inB2 = *pInB;
+ pInB += numColsB;
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(inA1, inB1, sum1);
+ sum1 = __SMMLA(inA2, inB2, sum1);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32);
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32);
+#endif
+
+ inA1 = *pInA++;
+ inA2 = *pInA++;
+ inB1 = *pInB;
+ pInB += numColsB;
+ inB2 = *pInB;
+ pInB += numColsB;
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(inA1, inB1, sum1);
+ sum1 = __SMMLA(inA2, inB2, sum1);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA1 * inB1)) >> 32);
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) inA2 * inB2)) >> 32);
+#endif
+
+ /* Decrement loop counter */
+ colCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining column */
+ colCnt = numColsA % 4U;
+
+#else
+
+ /* Initialize colCnt with number of columns */
+ colCnt = numColsA;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (colCnt > 0U) {
+#if defined (ARM_MATH_DSP)
+ sum1 = __SMMLA(*pInA++, *pInB, sum1);
+#else
+ sum1 = (q31_t) ((((q63_t) sum1 << 32) + ((q63_t) *pInA++ * *pInB)) >> 32);
+#endif
+ pInB += numColsB;
+
+ colCnt--;
+ }
+
+ /* Saturate and store the result in the destination buffer */
+ *px++ = sum1 << 1;
+ i++;
+
+ /* Decrement col loop counter */
+ col--;
+ }
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ @} end of MatrixMult group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c b/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c
new file mode 100644
index 000000000..4f86aa4c8
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: StatisticsFunctions.c
+ * Description: Combination of all statistics function source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_max_f32.c"
+#include "arm_max_q15.c"
+#include "arm_max_q31.c"
+#include "arm_max_q7.c"
+#include "arm_mean_f32.c"
+#include "arm_mean_q15.c"
+#include "arm_mean_q31.c"
+#include "arm_mean_q7.c"
+#include "arm_min_f32.c"
+#include "arm_min_q15.c"
+#include "arm_min_q31.c"
+#include "arm_min_q7.c"
+#include "arm_power_f32.c"
+#include "arm_power_q15.c"
+#include "arm_power_q31.c"
+#include "arm_power_q7.c"
+#include "arm_rms_f32.c"
+#include "arm_rms_q15.c"
+#include "arm_rms_q31.c"
+#include "arm_std_f32.c"
+#include "arm_std_q15.c"
+#include "arm_std_q31.c"
+#include "arm_var_f32.c"
+#include "arm_var_q15.c"
+#include "arm_var_q31.c"
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c
new file mode 100644
index 000000000..cd54e2a18
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,271 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_max_f32.c
+ * Description: Maximum value of a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#if defined(ARM_MATH_NEON)
+#include
+#endif
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @defgroup Max Maximum
+
+ Computes the maximum value of an array of data.
+ The function returns both the maximum value and its position within the array.
+ There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup Max
+ @{
+ */
+
+/**
+ @brief Maximum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @param[out] pIndex index of maximum value returned here
+ @return none
+ */
+#if defined(ARM_MATH_NEON)
+void arm_max_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+ float32_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ float32x4_t outV, srcV;
+ float32x2_t outV2;
+
+ uint32x4_t idxV;
+ uint32x4_t maxIdx={ULONG_MAX,ULONG_MAX,ULONG_MAX,ULONG_MAX};
+ uint32x4_t index={4,5,6,7};
+ uint32x4_t delta={4,4,4,4};
+ uint32x4_t countV={0,1,2,3};
+ uint32x2_t countV2;
+
+ /* Initialise the count value. */
+ count = 0U;
+
+ /* Initialise the index value to zero. */
+ outIndex = 0U;
+
+ /* Load first input value that act as reference value for comparison */
+ if (blockSize <= 3)
+ {
+ out = *pSrc++;
+
+ blkCnt = blockSize - 1;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ outV = vld1q_f32(pSrc);
+ pSrc += 4;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = (blockSize - 4 ) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ srcV = vld1q_f32(pSrc);
+ pSrc += 4;
+
+ idxV = vcgtq_f32(srcV, outV);
+ outV = vbslq_f32(idxV, srcV, outV );
+ countV = vbslq_u32(idxV, index,countV );
+
+ index = vaddq_u32(index,delta);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ outV2 = vpmax_f32(vget_low_f32(outV),vget_high_f32(outV));
+ outV2 = vpmax_f32(outV2,outV2);
+ out = outV2[0];
+
+ idxV = vceqq_f32(outV, vdupq_n_f32(out));
+ countV = vbslq_u32(idxV, countV,maxIdx);
+
+ countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV));
+ countV2 = vpmin_u32(countV2,countV2);
+ outIndex = countV2[0];
+
+ /* if (blockSize - 1U) is not multiple of 4 */
+ blkCnt = (blockSize - 4 ) % 4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt ;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+#else
+void arm_max_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+ float32_t maxVal, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ uint32_t index; /* index of maximum value */
+#endif
+
+ /* Initialise index value to zero. */
+ outIndex = 0U;
+
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ /* Initialise index of maximum value. */
+ index = 0U;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (blockSize - 1U) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to next consecutive values one by one */
+ maxVal = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal;
+ outIndex = index + 1U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 2U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 3U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 4U;
+ }
+
+ index += 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (blockSize - 1U) % 4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+/**
+ @} end of Max group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c
new file mode 100644
index 000000000..329b0c8d8
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_max_q15.c
+ * Description: Maximum value of a Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup Max
+ @{
+ */
+
+/**
+ @brief Maximum value of a Q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @param[out] pIndex index of maximum value returned here
+ @return none
+ */
+
+void arm_max_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+ q15_t maxVal, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ uint32_t index; /* index of maximum value */
+#endif
+
+ /* Initialise index value to zero. */
+ outIndex = 0U;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ /* Initialise index of maximum value. */
+ index = 0U;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (blockSize - 1U) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to next consecutive values one by one */
+ maxVal = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal;
+ outIndex = index + 1U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 2U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 3U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 4U;
+ }
+
+ index += 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (blockSize - 1U) % 4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ @} end of Max group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c
new file mode 100644
index 000000000..99de13e13
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_max_q31.c
+ * Description: Maximum value of a Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup Max
+ @{
+ */
+
+/**
+ @brief Maximum value of a Q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @param[out] pIndex index of maximum value returned here
+ @return none
+ */
+
+void arm_max_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+ q31_t maxVal, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ uint32_t index; /* index of maximum value */
+#endif
+
+ /* Initialise index value to zero. */
+ outIndex = 0U;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ /* Initialise index of maximum value. */
+ index = 0U;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (blockSize - 1U) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to next consecutive values one by one */
+ maxVal = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal;
+ outIndex = index + 1U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 2U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 3U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 4U;
+ }
+
+ index += 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (blockSize - 1U) % 4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ @} end of Max group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c
new file mode 100644
index 000000000..9c8b6d392
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_max_q7.c
+ * Description: Maximum value of a Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup Max
+ @{
+ */
+
+/**
+ @brief Maximum value of a Q7 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult maximum value returned here
+ @param[out] pIndex index of maximum value returned here
+ @return none
+ */
+
+void arm_max_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+ q7_t maxVal, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ uint32_t index; /* index of maximum value */
+#endif
+
+ /* Initialise index value to zero. */
+ outIndex = 0U;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ /* Initialise index of maximum value. */
+ index = 0U;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (blockSize - 1U) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to next consecutive values one by one */
+ maxVal = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal;
+ outIndex = index + 1U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 2U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 3U;
+ }
+
+ maxVal = *pSrc++;
+ if (out < maxVal)
+ {
+ out = maxVal;
+ outIndex = index + 4U;
+ }
+
+ index += 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (blockSize - 1U) % 4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out < maxVal)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ @} end of Max group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
index 000000000..63d965257
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,166 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mean_f32.c
+ * Description: Mean value of a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @defgroup mean Mean
+
+ Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.
+ The underlying algorithm is used:
+
+
+ Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+
+
+ There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup mean
+ @{
+ */
+
+/**
+ @brief Mean value of a floating-point vector.
+ @param[in] pSrc points to the input vector.
+ @param[in] blockSize number of samples in input vector.
+ @param[out] pResult mean value returned here.
+ @return none
+ */
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+void arm_mean_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */
+ float32x2_t sumV2;
+
+ uint32_t blkCnt; /* Loop counter */
+
+ float32_t in1, in2, in3, in4;
+ float32x4_t inV;
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ inV = vld1q_f32(pSrc);
+ sumV = vaddq_f32(sumV, inV);
+
+ pSrc += 4;
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV));
+ sum = sumV2[0] + sumV2[1];
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 3;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = sum / (float32_t) blockSize;
+}
+#else
+void arm_mean_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t sum = 0.0f; /* Temporary result storage */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ sum += *pSrc++;
+
+ sum += *pSrc++;
+
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store result to destination */
+ *pResult = (sum / blockSize);
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of mean group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
index 000000000..463aa84ec
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mean_q15.c
+ * Description: Mean value of a Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup mean
+ @{
+ */
+
+/**
+ @brief Mean value of a Q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ The input is represented in 1.15 format and is accumulated in a 32-bit
+ accumulator in 17.15 format.
+ There is no risk of internal overflow with this approach, and the
+ full precision of intermediate result is preserved.
+ Finally, the accumulator is truncated to yield a result of 1.15 format.
+ */
+
+void arm_mean_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t sum = 0; /* Temporary result storage */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t in;
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ sum += ((in << 16U) >> 16U);
+ sum += (in >> 16U);
+
+ in = read_q15x2_ia ((q15_t **) &pSrc);
+ sum += ((in << 16U) >> 16U);
+ sum += (in >> 16U);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store result to destination */
+ *pResult = (q15_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ @} end of mean group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
index 000000000..4b0ed6e99
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mean_q31.c
+ * Description: Mean value of a Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup mean
+ @{
+ */
+
+/**
+ @brief Mean value of a Q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ The input is represented in 1.31 format and is accumulated in a 64-bit
+ accumulator in 33.31 format.
+ There is no risk of internal overflow with this approach, and the
+ full precision of intermediate result is preserved.
+ Finally, the accumulator is truncated to yield a result of 1.31 format.
+ */
+
+void arm_mean_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t sum = 0; /* Temporary result storage */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ sum += *pSrc++;
+
+ sum += *pSrc++;
+
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store result to destination */
+ *pResult = (q31_t) (sum / blockSize);
+}
+
+/**
+ @} end of mean group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
index 000000000..8f52211ad
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,112 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_mean_q7.c
+ * Description: Mean value of a Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup mean
+ @{
+ */
+
+/**
+ @brief Mean value of a Q7 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult mean value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ The input is represented in 1.7 format and is accumulated in a 32-bit
+ accumulator in 25.7 format.
+ There is no risk of internal overflow with this approach, and the
+ full precision of intermediate result is preserved.
+ Finally, the accumulator is truncated to yield a result of 1.7 format.
+ */
+
+void arm_mean_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t sum = 0; /* Temporary result storage */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t in;
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in = read_q7x4_ia ((q7_t **) &pSrc);
+ sum += ((in << 24U) >> 24U);
+ sum += ((in << 16U) >> 24U);
+ sum += ((in << 8U) >> 24U);
+ sum += (in >> 24U);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store result to destination */
+ *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ @} end of mean group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c
new file mode 100644
index 000000000..6e9ff4b5d
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,268 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_min_f32.c
+ * Description: Minimum value of a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @defgroup Min Minimum
+
+ Computes the minimum value of an array of data.
+ The function returns both the minimum value and its position within the array.
+ There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup Min
+ @{
+ */
+
+/**
+ @brief Minimum value of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @param[out] pIndex index of minimum value returned here
+ @return none
+ */
+#if defined(ARM_MATH_NEON)
+void arm_min_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+ float32_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ float32x4_t outV, srcV;
+ float32x2_t outV2;
+
+ uint32x4_t idxV;
+ uint32x4_t maxIdx={ULONG_MAX,ULONG_MAX,ULONG_MAX,ULONG_MAX};
+ uint32x4_t index={4,5,6,7};
+ uint32x4_t delta={4,4,4,4};
+ uint32x4_t countV={0,1,2,3};
+ uint32x2_t countV2;
+
+ /* Initialise the count value. */
+ count = 0U;
+
+ /* Initialise the index value to zero. */
+ outIndex = 0U;
+
+ /* Load first input value that act as reference value for comparison */
+ if (blockSize <= 3)
+ {
+ out = *pSrc++;
+
+ blkCnt = blockSize - 1;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out > maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ outV = vld1q_f32(pSrc);
+ pSrc += 4;
+
+ /* Compute 4 outputs at a time */
+ blkCnt = (blockSize - 4 ) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ srcV = vld1q_f32(pSrc);
+ pSrc += 4;
+
+ idxV = vcltq_f32(srcV, outV);
+ outV = vbslq_f32(idxV, srcV, outV );
+ countV = vbslq_u32(idxV, index,countV );
+
+ index = vaddq_u32(index,delta);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ outV2 = vpmin_f32(vget_low_f32(outV),vget_high_f32(outV));
+ outV2 = vpmin_f32(outV2,outV2);
+ out = outV2[0];
+
+ idxV = vceqq_f32(outV, vdupq_n_f32(out));
+ countV = vbslq_u32(idxV, countV,maxIdx);
+
+ countV2 = vpmin_u32(vget_low_u32(countV),vget_high_u32(countV));
+ countV2 = vpmin_u32(countV2,countV2);
+ outIndex = countV2[0];
+
+ /* if (blockSize - 1U) is not multiple of 4 */
+ blkCnt = (blockSize - 4 ) % 4U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if (out > maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt ;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+#else
+void arm_min_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+ float32_t minVal, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ uint32_t index; /* index of maximum value */
+#endif
+
+ /* Initialise index value to zero. */
+ outIndex = 0U;
+
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ /* Initialise index of maximum value. */
+ index = 0U;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (blockSize - 1U) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize minVal to next consecutive values one by one */
+ minVal = *pSrc++;
+
+ /* compare for the minimum value */
+ if (out > minVal)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal;
+ outIndex = index + 1U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 2U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 3U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 4U;
+ }
+
+ index += 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (blockSize - 1U) % 4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal = *pSrc++;
+
+ /* compare for the minimum value */
+ if (out > minVal)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store the minimum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of Min group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c
new file mode 100644
index 000000000..94503837e
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_min_q15.c
+ * Description: Minimum value of a Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+
+/**
+ @addtogroup Min
+ @{
+ */
+
+/**
+ @brief Minimum value of a Q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @param[out] pIndex index of minimum value returned here
+ @return none
+ */
+
+void arm_min_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+ q15_t minVal, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ uint32_t index; /* index of maximum value */
+#endif
+
+ /* Initialise index value to zero. */
+ outIndex = 0U;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ /* Initialise index of maximum value. */
+ index = 0U;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (blockSize - 1U) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize minVal to next consecutive values one by one */
+ minVal = *pSrc++;
+
+ /* compare for the minimum value */
+ if (out > minVal)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal;
+ outIndex = index + 1U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 2U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 3U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 4U;
+ }
+
+ index += 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (blockSize - 1U) % 4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal = *pSrc++;
+
+ /* compare for the minimum value */
+ if (out > minVal)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store the minimum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ @} end of Min group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c
new file mode 100644
index 000000000..e25eb47ef
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_min_q31.c
+ * Description: Minimum value of a Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+
+/**
+ @addtogroup Min
+ @{
+ */
+
+/**
+ @brief Minimum value of a Q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @param[out] pIndex index of minimum value returned here
+ @return none
+ */
+
+void arm_min_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+ q31_t minVal, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ uint32_t index; /* index of maximum value */
+#endif
+
+ /* Initialise index value to zero. */
+ outIndex = 0U;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ /* Initialise index of maximum value. */
+ index = 0U;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (blockSize - 1U) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize minVal to next consecutive values one by one */
+ minVal = *pSrc++;
+
+ /* compare for the minimum value */
+ if (out > minVal)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal;
+ outIndex = index + 1U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 2U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 3U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 4U;
+ }
+
+ index += 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (blockSize - 1U) % 4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal = *pSrc++;
+
+ /* compare for the minimum value */
+ if (out > minVal)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store the minimum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ @} end of Min group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c
new file mode 100644
index 000000000..2b171f0a4
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_min_q7.c
+ * Description: Minimum value of a Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+
+/**
+ @addtogroup Min
+ @{
+ */
+
+/**
+ @brief Minimum value of a Q7 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult minimum value returned here
+ @param[out] pIndex index of minimum value returned here
+ @return none
+ */
+
+void arm_min_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+ q7_t minVal, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ uint32_t index; /* index of maximum value */
+#endif
+
+ /* Initialise index value to zero. */
+ outIndex = 0U;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ /* Initialise index of maximum value. */
+ index = 0U;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = (blockSize - 1U) >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize minVal to next consecutive values one by one */
+ minVal = *pSrc++;
+
+ /* compare for the minimum value */
+ if (out > minVal)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal;
+ outIndex = index + 1U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 2U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 3U;
+ }
+
+ minVal = *pSrc++;
+ if (out > minVal)
+ {
+ out = minVal;
+ outIndex = index + 4U;
+ }
+
+ index += 4U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = (blockSize - 1U) % 4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (blockSize - 1U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal = *pSrc++;
+
+ /* compare for the minimum value */
+ if (out > minVal)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store the minimum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ @} end of Min group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c
new file mode 100644
index 000000000..a4825a531
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,175 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_power_f32.c
+ * Description: Sum of the squares of the elements of a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @defgroup power Power
+
+ Calculates the sum of the squares of the elements in the input vector.
+ The underlying algorithm is used:
+
+
+ Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+
+
+ There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup power
+ @{
+ */
+
+/**
+ @brief Sum of the squares of the elements of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult sum of the squares value returned here
+ @return none
+ */
+#if defined(ARM_MATH_NEON)
+void arm_power_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* accumulator */
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+ float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */
+ float32x2_t sumV2;
+ float32x4_t inV;
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ inV = vld1q_f32(pSrc);
+ sumV = vmlaq_f32(sumV, inV, inV);
+ pSrc += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV));
+ sum = sumV2[0] + sumV2[1];
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* compute power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result to the destination */
+ *pResult = sum;
+}
+#else
+void arm_power_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute Power and store result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+
+ in = *pSrc++;
+ sum += in * in;
+
+ in = *pSrc++;
+ sum += in * in;
+
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute Power and store result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store result to destination */
+ *pResult = sum;
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of power group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c
new file mode 100644
index 000000000..12f524db5
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_power_q15.c
+ * Description: Sum of the squares of the elements of a Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup power
+ @{
+ */
+
+/**
+ @brief Sum of the squares of the elements of a Q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult sum of the squares value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ The input is represented in 1.15 format.
+ Intermediate multiplication yields a 2.30 format, and this
+ result is added without saturation to a 64-bit accumulator in 34.30 format.
+ With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ full precision of the intermediate multiplication is preserved.
+ Finally, the return result is in 34.30 format.
+ */
+
+void arm_power_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t sum = 0; /* Temporary result storage */
+ q15_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in32; /* Temporary variable to store packed input value */
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute Power and store result in a temporary variable, sum. */
+#if defined (ARM_MATH_DSP)
+ in32 = read_q15x2_ia ((q15_t **) &pSrc);
+ sum = __SMLALD(in32, in32, sum);
+
+ in32 = read_q15x2_ia ((q15_t **) &pSrc);
+ sum = __SMLALD(in32, in32, sum);
+#else
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute Power and store result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store result in 34.30 format */
+ *pResult = sum;
+}
+
+/**
+ @} end of power group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c
new file mode 100644
index 000000000..1e193b326
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_power_q31.c
+ * Description: Sum of the squares of the elements of a Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup power
+ @{
+ */
+
+/**
+ @brief Sum of the squares of the elements of a Q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult sum of the squares value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ The input is represented in 1.31 format.
+ Intermediate multiplication yields a 2.62 format, and this
+ result is truncated to 2.48 format by discarding the lower 14 bits.
+ The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ With 15 guard bits in the accumulator, there is no risk of overflow, and the
+ full precision of the intermediate multiplication is preserved.
+ Finally, the return result is in 16.48 format.
+ */
+
+void arm_power_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t sum = 0; /* Temporary result storage */
+ q31_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and store result in a temporary variable sum, providing 15 guard bits. */
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14U;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14U;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14U;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute Power and store result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14U;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store results in 16.48 format */
+ *pResult = sum;
+}
+
+/**
+ @} end of power group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c
new file mode 100644
index 000000000..47405cd40
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_power_q7.c
+ * Description: Sum of the squares of the elements of a Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup power
+ @{
+ */
+
+/**
+ @brief Sum of the squares of the elements of a Q7 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult sum of the squares value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 32-bit internal accumulator.
+ The input is represented in 1.7 format.
+ Intermediate multiplication yields a 2.14 format, and this
+ result is added without saturation to an accumulator in 18.14 format.
+ With 17 guard bits in the accumulator, there is no risk of overflow, and the
+ full precision of the intermediate multiplication is preserved.
+ Finally, the return result is in 18.14 format.
+ */
+
+void arm_power_q7(
+ const q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t sum = 0; /* Temporary result storage */
+ q7_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in32; /* Temporary variable to store packed input value */
+ q31_t in1, in2; /* Temporary variables to store input value */
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute Power and store result in a temporary variable, sum. */
+#if defined (ARM_MATH_DSP)
+ in32 = read_q7x4_ia ((q7_t **) &pSrc);
+
+ in1 = __SXTB16(__ROR(in32, 8));
+ in2 = __SXTB16(in32);
+
+ /* calculate power and accumulate to accumulator */
+ sum = __SMLAD(in1, in1, sum);
+ sum = __SMLAD(in2, in2, sum);
+#else
+ in = *pSrc++;
+ sum += ((q15_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q15_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q15_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q15_t) in * in);
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute Power and store result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q15_t) in * in);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Store result in 18.14 format */
+ *pResult = sum;
+}
+
+/**
+ @} end of power group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
index 000000000..454651075
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_rms_f32.c
+ * Description: Root mean square value of the elements of a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @defgroup RMS Root mean square (RMS)
+
+ Calculates the Root Mean Square of the elements in the input vector.
+ The underlying algorithm is used:
+
+
+ Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+
+
+ There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ @addtogroup RMS
+ @{
+ */
+
+/**
+ @brief Root Mean Square of the elements of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult root mean square value returned here
+ @return none
+ */
+#if defined(ARM_MATH_NEON)
+void arm_rms_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* accumulator */
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+ float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */
+ float32x2_t sumV2;
+ float32x4_t inV;
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ inV = vld1q_f32(pSrc);
+ sumV = vmlaq_f32(sumV, inV, inV);
+ pSrc += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV));
+ sum = sumV2[0] + sumV2[1];
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* compute power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Rms and store the result in the destination */
+ arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+#else
+void arm_rms_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable, sum. */
+ sum += in * in;
+
+ in = *pSrc++;
+ sum += in * in;
+
+ in = *pSrc++;
+ sum += in * in;
+
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable. */
+ sum += ( in * in);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Rms and store result in destination */
+ arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of RMS group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
index 000000000..9fcd964e5
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_rms_q15.c
+ * Description: Root Mean Square of the elements of a Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup RMS
+ @{
+ */
+
+/**
+ @brief Root Mean Square of the elements of a Q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult root mean square value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ The input is represented in 1.15 format.
+ Intermediate multiplication yields a 2.30 format, and this
+ result is added without saturation to a 64-bit accumulator in 34.30 format.
+ With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ full precision of the intermediate multiplication is preserved.
+ Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ 15 bits, and then saturated to yield a result in 1.15 format.
+ */
+
+void arm_rms_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t sum = 0; /* Temporary result storage */
+ q15_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in32; /* Temporary variable to store input value */
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ /* Compute sum of squares and store result in a temporary variable. */
+#if defined (ARM_MATH_DSP)
+ in32 = read_q15x2_ia ((q15_t **) &pSrc);
+ sum = __SMLALD(in32, in32, sum);
+
+ in32 = read_q15x2_ia ((q15_t **) &pSrc);
+ sum = __SMLALD(in32, in32, sum);
+#else
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable. */
+ sum += ((q31_t) in * in);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Truncating and saturating the accumulator to 1.15 format */
+ /* Store result in destination */
+ arm_sqrt_q15(__SSAT((sum / (q63_t)blockSize) >> 15, 16), pResult);
+}
+
+/**
+ @} end of RMS group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
index 000000000..5a3e8f35d
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,124 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_rms_q31.c
+ * Description: Root Mean Square of the elements of a Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup RMS
+ @{
+ */
+
+/**
+ @brief Root Mean Square of the elements of a Q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult root mean square value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The input is represented in 1.31 format, and intermediate multiplication
+ yields a 2.62 format.
+ The accumulator maintains full precision of the intermediate multiplication results,
+ but provides only a single guard bit.
+ There is no saturation on intermediate additions.
+ If the accumulator overflows, it wraps around and distorts the result.
+ In order to avoid overflows completely, the input signal must be scaled down by
+ log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ */
+
+void arm_rms_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ uint64_t sum = 0; /* Temporary result storage (can get never negative. changed type from q63 to uint64 */
+ q31_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable, sum. */
+ sum += ((q63_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in);
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable. */
+ sum += ((q63_t) in * in);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
+ /* Compute Rms and store result in destination vector */
+ arm_sqrt_q31(clip_q63_to_q31((sum / (q63_t) blockSize) >> 31), pResult);
+}
+
+/**
+ @} end of RMS group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c
new file mode 100644
index 000000000..e1e6577a0
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_std_f32.c
+ * Description: Standard deviation of the elements of a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @defgroup STD Standard deviation
+
+ Calculates the standard deviation of the elements in the input vector.
+ The underlying algorithm is used:
+
+
+ Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))
+
+ sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+ sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+
+
+ There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ @addtogroup STD
+ @{
+ */
+
+/**
+ @brief Standard deviation of the elements of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult standard deviation value returned here
+ @return none
+ */
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+void arm_std_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t var;
+ arm_var_f32(pSrc,blockSize,&var);
+ arm_sqrt_f32(var, pResult);
+}
+#else
+void arm_std_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t sumOfSquares = 0.0f; /* Sum of squares */
+ float32_t in; /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ float32_t meanOfSquares, mean, squareOfMean; /* Temporary variables */
+#else
+ float32_t squareOfSum; /* Square of Sum */
+ float32_t var; /* Temporary varaince storage */
+#endif
+
+ if (blockSize <= 1U)
+ {
+ *pResult = 0;
+ return;
+ }
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ sumOfSquares += in * in;
+ /* Compute sum and store result in a temporary variable, sum. */
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += in * in;
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += in * in;
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += in * in;
+ sum += in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ sumOfSquares += ( in * in);
+ /* Compute sum and store result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+ /* Compute mean of all input values */
+ mean = sum / (float32_t) blockSize;
+
+ /* Compute square of mean */
+ squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+ ((float32_t) blockSize - 1.0f));
+
+ /* Compute standard deviation and store result to destination */
+ arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+ /* Run the below code for Cortex-M0 */
+
+ /* Compute square of sum */
+ squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+ /* Compute variance */
+ var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+ /* Compute standard deviation and store result in destination */
+ arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of STD group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c
new file mode 100644
index 000000000..8e5c0426b
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_std_q15.c
+ * Description: Standard deviation of an array of Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup STD
+ @{
+ */
+
+/**
+ @brief Standard deviation of the elements of a Q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult standard deviation value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ The input is represented in 1.15 format.
+ Intermediate multiplication yields a 2.30 format, and this
+ result is added without saturation to a 64-bit accumulator in 34.30 format.
+ With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ full precision of the intermediate multiplication is preserved.
+ Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ 15 bits, and then saturated to yield a result in 1.15 format.
+ */
+
+void arm_std_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */
+ q63_t sumOfSquares = 0; /* Sum of squares */
+ q15_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in32; /* Temporary variable to store input value */
+#endif
+
+ if (blockSize <= 1U)
+ {
+ *pResult = 0;
+ return;
+ }
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ /* Compute sum and store result in a temporary variable, sum. */
+#if defined (ARM_MATH_DSP)
+ in32 = read_q15x2_ia ((q15_t **) &pSrc);
+ sumOfSquares = __SMLALD(in32, in32, sumOfSquares);
+ sum += ((in32 << 16U) >> 16U);
+ sum += (in32 >> 16U);
+
+ in32 = read_q15x2_ia ((q15_t **) &pSrc);
+ sumOfSquares = __SMLALD(in32, in32, sumOfSquares);
+ sum += ((in32 << 16U) >> 16U);
+ sum += (in32 >> 16U);
+#else
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+ sum += in;
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ sumOfSquares += (in * in);
+ /* Compute sum and store result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */
+ meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U));
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U)));
+
+ /* mean of squares minus the square of mean. */
+ /* Compute standard deviation and store result in destination */
+ arm_sqrt_q15(__SSAT((meanOfSquares - squareOfMean) >> 15U, 16U), pResult);
+}
+
+/**
+ @} end of STD group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c
new file mode 100644
index 000000000..cfb6cb8b6
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,147 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_std_q31.c
+ * Description: Standard deviation of the elements of a Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup STD
+ @{
+ */
+
+/**
+ @brief Standard deviation of the elements of a Q31 vector.
+ @param[in] pSrc points to the input vector.
+ @param[in] blockSize number of samples in input vector.
+ @param[out] pResult standard deviation value returned here.
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The input is represented in 1.31 format, which is then downshifted by 8 bits
+ which yields 1.23, and intermediate multiplication yields a 2.46 format.
+ The accumulator maintains full precision of the intermediate multiplication results,
+ but provides only a 16 guard bits.
+ There is no saturation on intermediate additions.
+ If the accumulator overflows it wraps around and distorts the result.
+ In order to avoid overflows completely the input signal must be scaled down by
+ log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.
+ After division, internal variables should be Q18.46
+ Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.
+ */
+
+void arm_std_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t sum = 0; /* Accumulator */
+ q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */
+ q63_t sumOfSquares = 0; /* Sum of squares */
+ q31_t in; /* Temporary variable to store input value */
+
+ if (blockSize <= 1U)
+ {
+ *pResult = 0;
+ return;
+ }
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ in = *pSrc++ >> 8U;
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ sumOfSquares += ((q63_t) (in) * (in));
+ /* Compute sum and store result in a temporary variable, sum. */
+ sum += in;
+
+ in = *pSrc++ >> 8U;
+ sumOfSquares += ((q63_t) (in) * (in));
+ sum += in;
+
+ in = *pSrc++ >> 8U;
+ sumOfSquares += ((q63_t) (in) * (in));
+ sum += in;
+
+ in = *pSrc++ >> 8U;
+ sumOfSquares += ((q63_t) (in) * (in));
+ sum += in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ in = *pSrc++ >> 8U;
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ sumOfSquares += ((q63_t) (in) * (in));
+ /* Compute sum and store result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */
+ meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U));
+
+ /* Compute square of mean */
+ squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U)));
+
+ /* Compute standard deviation and store result in destination */
+ arm_sqrt_q31((meanOfSquares - squareOfMean) >> 15U, pResult);
+}
+
+/**
+ @} end of STD group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c
new file mode 100644
index 000000000..3c325b135
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_var_f32.c
+ * Description: Variance of the elements of a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @defgroup variance Variance
+
+ Calculates the variance of the elements in the input vector.
+ The underlying algorithm used is the direct method sometimes referred to as the two-pass method:
+
+
+ Result = sum(element - meanOfElements)^2) / numElement - 1
+
+ meanOfElements = ( pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] ) / blockSize
+
+
+ There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ @addtogroup variance
+ @{
+ */
+
+/**
+ @brief Variance of the elements of a floating-point vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult variance value returned here
+ @return none
+ */
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+void arm_var_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t mean;
+
+ float32_t sum = 0.0f; /* accumulator */
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+ float32x4_t sumV = vdupq_n_f32(0.0f); /* Temporary result storage */
+ float32x2_t sumV2;
+ float32x4_t inV;
+ float32x4_t avg;
+
+ arm_mean_f32(pSrc,blockSize,&mean);
+ avg = vdupq_n_f32(mean);
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ inV = vld1q_f32(pSrc);
+ inV = vsubq_f32(inV, avg);
+ sumV = vmlaq_f32(sumV, inV, inV);
+ pSrc += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ sumV2 = vpadd_f32(vget_low_f32(sumV),vget_high_f32(sumV));
+ sum = sumV2[0] + sumV2[1];
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* compute power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ in = in - mean;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Variance */
+ *pResult = sum / (float32_t)(blockSize - 1.0f);
+
+}
+
+#else
+void arm_var_f32(
+ const float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t fSum = 0.0f;
+ float32_t fMean, fValue;
+ const float32_t * pInput = pSrc;
+
+ if (blockSize <= 1U)
+ {
+ *pResult = 0;
+ return;
+ }
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+
+ sum += *pInput++;
+ sum += *pInput++;
+ sum += *pInput++;
+ sum += *pInput++;
+
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+
+ sum += *pInput++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ fMean = sum / (float32_t) blockSize;
+
+ pInput = pSrc;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ fValue = *pInput++ - fMean;
+ fSum += fValue * fValue;
+
+ fValue = *pInput++ - fMean;
+ fSum += fValue * fValue;
+
+ fValue = *pInput++ - fMean;
+ fSum += fValue * fValue;
+
+ fValue = *pInput++ - fMean;
+ fSum += fValue * fValue;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ fValue = *pInput++ - fMean;
+ fSum += fValue * fValue;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Variance */
+ *pResult = fSum / (float32_t)(blockSize - 1.0f);
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of variance group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c
new file mode 100644
index 000000000..259e76beb
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,164 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_var_q15.c
+ * Description: Variance of an array of Q15 type
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup variance
+ @{
+ */
+
+/**
+ @brief Variance of the elements of a Q15 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult variance value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using a 64-bit internal accumulator.
+ The input is represented in 1.15 format.
+ Intermediate multiplication yields a 2.30 format, and this
+ result is added without saturation to a 64-bit accumulator in 34.30 format.
+ With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ full precision of the intermediate multiplication is preserved.
+ Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ 15 bits, and then saturated to yield a result in 1.15 format.
+ */
+
+void arm_var_q15(
+ const q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q31_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */
+ q63_t sumOfSquares = 0; /* Sum of squares */
+ q15_t in; /* Temporary variable to store input value */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in32; /* Temporary variable to store input value */
+#endif
+
+ if (blockSize <= 1U)
+ {
+ *pResult = 0;
+ return;
+ }
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ /* Compute sum and store result in a temporary variable, sum. */
+#if defined (ARM_MATH_DSP)
+ in32 = read_q15x2_ia ((q15_t **) &pSrc);
+ sumOfSquares = __SMLALD(in32, in32, sumOfSquares);
+ sum += ((in32 << 16U) >> 16U);
+ sum += (in32 >> 16U);
+
+ in32 = read_q15x2_ia ((q15_t **) &pSrc);
+ sumOfSquares = __SMLALD(in32, in32, sumOfSquares);
+ sum += ((in32 << 16U) >> 16U);
+ sum += (in32 >> 16U);
+#else
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+ sum += in;
+
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+ sum += in;
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ in = *pSrc++;
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+#if defined (ARM_MATH_DSP)
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+#else
+ sumOfSquares += (in * in);
+#endif /* #if defined (ARM_MATH_DSP) */
+ /* Compute sum and store result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */
+ meanOfSquares = (q31_t) (sumOfSquares / (q63_t)(blockSize - 1U));
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t) ((q63_t) sum * sum / (q63_t)(blockSize * (blockSize - 1U)));
+
+ /* mean of squares minus the square of mean. */
+ *pResult = (meanOfSquares - squareOfMean) >> 15U;
+}
+
+/**
+ @} end of variance group
+ */
diff --git a/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c b/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c
new file mode 100644
index 000000000..558332f96
--- /dev/null
+++ b/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,147 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_var_q31.c
+ * Description: Variance of an array of Q31 type
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupStats
+ */
+
+/**
+ @addtogroup variance
+ @{
+ */
+
+/**
+ @brief Variance of the elements of a Q31 vector.
+ @param[in] pSrc points to the input vector
+ @param[in] blockSize number of samples in input vector
+ @param[out] pResult variance value returned here
+ @return none
+
+ @par Scaling and Overflow Behavior
+ The function is implemented using an internal 64-bit accumulator.
+ The input is represented in 1.31 format, which is then downshifted by 8 bits
+ which yields 1.23, and intermediate multiplication yields a 2.46 format.
+ The accumulator maintains full precision of the intermediate multiplication results,
+ but provides only a 16 guard bits.
+ There is no saturation on intermediate additions.
+ If the accumulator overflows it wraps around and distorts the result.
+ In order to avoid overflows completely the input signal must be scaled down by
+ log2(blockSize)-8 bits, as a total of blockSize additions are performed internally.
+ After division, internal variables should be Q18.46
+ Finally, the 18.46 accumulator is right shifted by 15 bits to yield a 1.31 format value.
+ */
+
+void arm_var_q31(
+ const q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ uint32_t blkCnt; /* Loop counter */
+ q63_t sum = 0; /* Temporary result storage */
+ q63_t meanOfSquares, squareOfMean; /* Square of mean and mean of square */
+ q63_t sumOfSquares = 0; /* Sum of squares */
+ q31_t in; /* Temporary variable to store input value */
+
+ if (blockSize <= 1U)
+ {
+ *pResult = 0;
+ return;
+ }
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ in = *pSrc++ >> 8U;
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ sumOfSquares += ((q63_t) (in) * (in));
+ /* Compute sum and store result in a temporary variable, sum. */
+ sum += in;
+
+ in = *pSrc++ >> 8U;
+ sumOfSquares += ((q63_t) (in) * (in));
+ sum += in;
+
+ in = *pSrc++ >> 8U;
+ sumOfSquares += ((q63_t) (in) * (in));
+ sum += in;
+
+ in = *pSrc++ >> 8U;
+ sumOfSquares += ((q63_t) (in) * (in));
+ sum += in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* C = A[0] + A[1] + ... + A[blockSize-1] */
+
+ in = *pSrc++ >> 8U;
+ /* Compute sum of squares and store result in a temporary variable, sumOfSquares. */
+ sumOfSquares += ((q63_t) (in) * (in));
+ /* Compute sum and store result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares and store result in a temporary variable, meanOfSquares. */
+ meanOfSquares = (sumOfSquares / (q63_t)(blockSize - 1U));
+
+ /* Compute square of mean */
+ squareOfMean = ( sum * sum / (q63_t)(blockSize * (blockSize - 1U)));
+
+ /* Compute variance and store result in destination */
+ *pResult = (meanOfSquares - squareOfMean) >> 15U;
+}
+
+/**
+ @} end of variance group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c b/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c
new file mode 100644
index 000000000..4deb19bc6
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c
@@ -0,0 +1,48 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: SupportFunctions.c
+ * Description: Combination of all support function source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_copy_f32.c"
+#include "arm_copy_q15.c"
+#include "arm_copy_q31.c"
+#include "arm_copy_q7.c"
+#include "arm_fill_f32.c"
+#include "arm_fill_q15.c"
+#include "arm_fill_q31.c"
+#include "arm_fill_q7.c"
+#include "arm_float_to_q15.c"
+#include "arm_float_to_q31.c"
+#include "arm_float_to_q7.c"
+#include "arm_q15_to_float.c"
+#include "arm_q15_to_q31.c"
+#include "arm_q15_to_q7.c"
+#include "arm_q31_to_float.c"
+#include "arm_q31_to_q15.c"
+#include "arm_q31_to_q7.c"
+#include "arm_q7_to_float.c"
+#include "arm_q7_to_q15.c"
+#include "arm_q7_to_q31.c"
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c
new file mode 100644
index 000000000..707adc4cc
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_copy_f32.c
+ * Description: Copies the elements of a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @defgroup copy Vector Copy
+
+ Copies sample by sample from source vector to destination vector.
+
+
+ pDst[n] = pSrc[n]; 0 <= n < blockSize.
+
+
+ There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup copy
+ @{
+ */
+
+/**
+ @brief Copies the elements of a floating-point vector.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+void arm_copy_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+ float32x4_t inV;
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ inV = vld1q_f32(pSrc);
+ vst1q_f32(pDst, inV);
+ pSrc += 4;
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 3;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+#else
+void arm_copy_f32(
+ const float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+
+ /* Copy and store result in destination buffer */
+ *pDst++ = *pSrc++;
+ *pDst++ = *pSrc++;
+ *pDst++ = *pSrc++;
+ *pDst++ = *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+
+ /* Copy and store result in destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+/**
+ @} end of BasicCopy group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c b/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c
new file mode 100644
index 000000000..d8da1130d
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_copy_q15.c
+ * Description: Copies the elements of a Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup copy
+ @{
+ */
+
+/**
+ @brief Copies the elements of a Q15 vector.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_copy_q15(
+ const q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+
+ /* read 2 times 2 samples at a time */
+ write_q15x2_ia (&pDst, read_q15x2_ia ((q15_t **) &pSrc));
+ write_q15x2_ia (&pDst, read_q15x2_ia ((q15_t **) &pSrc));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+
+ /* Copy and store result in destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of BasicCopy group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c b/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c
new file mode 100644
index 000000000..e342a32ae
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_copy_q31.c
+ * Description: Copies the elements of a Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup copy
+ @{
+ */
+
+/**
+ @brief Copies the elements of a Q31 vector.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_copy_q31(
+ const q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+
+ /* Copy and store result in destination buffer */
+ *pDst++ = *pSrc++;
+ *pDst++ = *pSrc++;
+ *pDst++ = *pSrc++;
+ *pDst++ = *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+
+ /* Copy and store result in destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of BasicCopy group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c b/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c
new file mode 100644
index 000000000..77da8ca26
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,95 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_copy_q7.c
+ * Description: Copies the elements of a Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup copy
+ @{
+ */
+
+/**
+ @brief Copies the elements of a Q7 vector.
+ @param[in] pSrc points to input vector
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_copy_q7(
+ const q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+
+ /* read 4 samples at a time */
+ write_q7x4_ia (&pDst, read_q7x4_ia ((q7_t **) &pSrc));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A */
+
+ /* Copy and store result in destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of BasicCopy group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c b/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c
new file mode 100644
index 000000000..29f628628
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fill_f32.c
+ * Description: Fills a constant value into a floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @defgroup Fill Vector Fill
+
+ Fills the destination vector with a constant value.
+
+
+ pDst[n] = value; 0 <= n < blockSize.
+
+
+ There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ @addtogroup Fill
+ @{
+ */
+
+/**
+ @brief Fills a constant value into a floating-point vector.
+ @param[in] value input value to be filled
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+ float32x4_t inV = vdupq_n_f32(value);
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ vst1q_f32(pDst, inV);
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 3;
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+#else
+void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+
+ /* Fill value in destination buffer */
+ *pDst++ = value;
+ *pDst++ = value;
+ *pDst++ = value;
+ *pDst++ = value;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+
+ /* Fill value in destination buffer */
+ *pDst++ = value;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+/**
+ @} end of Fill group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c b/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c
new file mode 100644
index 000000000..d8c0f8d0b
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,100 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fill_q15.c
+ * Description: Fills a constant value into a Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Fill
+ @{
+ */
+
+/**
+ @brief Fills a constant value into a Q15 vector.
+ @param[in] value input value to be filled
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t packedValue; /* value packed to 32 bits */
+
+ /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+ packedValue = __PKHBT(value, value, 16U);
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+
+ /* fill 2 times 2 samples at a time */
+ write_q15x2_ia (&pDst, packedValue);
+ write_q15x2_ia (&pDst, packedValue);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+
+ /* Fill value in destination buffer */
+ *pDst++ = value;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Fill group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c b/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c
new file mode 100644
index 000000000..e17488944
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fill_q31.c
+ * Description: Fills a constant value into a Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Fill
+ @{
+ */
+
+/**
+ @brief Fills a constant value into a Q31 vector.
+ @param[in] value input value to be filled
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+
+ /* Fill value in destination buffer */
+ *pDst++ = value;
+ *pDst++ = value;
+ *pDst++ = value;
+ *pDst++ = value;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+
+ /* Fill value in destination buffer */
+ *pDst++ = value;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Fill group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c b/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c
new file mode 100644
index 000000000..bca32674a
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_fill_q7.c
+ * Description: Fills a constant value into a Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup Fill
+ @{
+ */
+
+/**
+ @brief Fills a constant value into a Q7 vector.
+ @param[in] value input value to be filled
+ @param[out] pDst points to output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+ */
+
+void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t packedValue; /* value packed to 32 bits */
+
+ /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+ packedValue = __PACKq7(value, value, value, value);
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+
+ /* fill 4 samples at a time */
+ write_q7x4_ia (&pDst, packedValue);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = value */
+
+ /* Fill value in destination buffer */
+ *pDst++ = value;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ @} end of Fill group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c b/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c
new file mode 100644
index 000000000..68c1ad09f
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,244 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_float_to_q15.c
+ * Description: Converts the elements of the floating-point vector to Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup float_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the floating-point vector to Q15 vector.
+ @param[in] pSrc points to the floating-point input vector
+ @param[out] pDst points to the Q15 output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (q15_t)(pSrc[n] * 32768); 0 <= n < blockSize.
+
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+
+ @note
+ In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ defined in the preprocessor section of project options.
+ */
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+void arm_float_to_q15(
+ const float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ const float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+ float32_t in;
+ float32x4_t inV;
+ #ifdef ARM_MATH_ROUNDING
+ float32x4_t zeroV = vdupq_n_f32(0.0f);
+ float32x4_t pHalf = vdupq_n_f32(0.5f / 32768.0f);
+ float32x4_t mHalf = vdupq_n_f32(-0.5f / 32768.0f);
+ float32x4_t r;
+ uint32x4_t cmp;
+ #endif
+
+ int32x4_t cvt;
+ int16x4_t outV;
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* Convert from float to q15 and then store the results in the destination buffer */
+ inV = vld1q_f32(pIn);
+ cmp = vcgtq_f32(inV,zeroV);
+ r = vbslq_f32(cmp,pHalf,mHalf);
+ inV = vaddq_f32(inV, r);
+
+ pIn += 4;
+
+ cvt = vcvtq_n_s32_f32(inV,15);
+ outV = vqmovn_s32(cvt);
+
+ vst1_s16(pDst, outV);
+ pDst += 4;
+
+#else
+
+ /* C = A * 32768 */
+ /* Convert from float to q15 and then store the results in the destination buffer */
+ inV = vld1q_f32(pIn);
+
+ cvt = vcvtq_n_s32_f32(inV,15);
+ outV = vqmovn_s32(cvt);
+
+ vst1_s16(pDst, outV);
+ pDst += 4;
+ pIn += 4;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 3;
+
+ while (blkCnt > 0U)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* Convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* Convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+#else
+void arm_float_to_q15(
+ const float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const float32_t *pIn = pSrc; /* Source pointer */
+
+#ifdef ARM_MATH_ROUNDING
+ float32_t in;
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * 32768 */
+
+ /* convert from float to Q15 and store result in destination buffer */
+#ifdef ARM_MATH_ROUNDING
+
+ in = (*pIn++ * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = (*pIn++ * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = (*pIn++ * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = (*pIn++ * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * 32768 */
+
+ /* convert from float to Q15 and store result in destination buffer */
+#ifdef ARM_MATH_ROUNDING
+
+ in = (*pIn++ * 32768.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* Convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of float_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c b/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c
new file mode 100644
index 000000000..479f8c5b8
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,252 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_float_to_q31.c
+ * Description: Converts the elements of the floating-point vector to Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ * @defgroup float_to_x Convert 32-bit floating point value
+ */
+
+/**
+ @addtogroup float_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the floating-point vector to Q31 vector.
+ @param[in] pSrc points to the floating-point input vector
+ @param[out] pDst points to the Q31 output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (q31_t)(pSrc[n] * 2147483648); 0 <= n < blockSize.
+
+
+ @par Scaling and Overflow Behavior
+ The function uses saturating arithmetic.
+ Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] are saturated.
+
+ @note
+ In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ defined in the preprocessor section of project options.
+ */
+
+#if defined(ARM_MATH_NEON)
+void arm_float_to_q31(
+ const float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ const float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+ float32_t in;
+ float32x4_t inV;
+ #ifdef ARM_MATH_ROUNDING
+ float32x4_t zeroV = vdupq_n_f32(0.0f);
+ float32x4_t pHalf = vdupq_n_f32(0.5f / 2147483648.0f);
+ float32x4_t mHalf = vdupq_n_f32(-0.5f / 2147483648.0f);
+ float32x4_t r;
+ uint32x4_t cmp;
+ #endif
+
+ int32x4_t outV;
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 32768 */
+ /* Convert from float to Q31 and then store the results in the destination buffer */
+ inV = vld1q_f32(pIn);
+ cmp = vcgtq_f32(inV,zeroV);
+ r = vbslq_f32(cmp,pHalf,mHalf);
+ inV = vaddq_f32(inV, r);
+
+ pIn += 4;
+
+ outV = vcvtq_n_s32_f32(inV,31);
+
+ vst1q_s32(pDst, outV);
+ pDst += 4;
+
+#else
+
+ /* C = A * 2147483648 */
+ /* Convert from float to Q31 and then store the results in the destination buffer */
+ inV = vld1q_f32(pIn);
+
+ outV = vcvtq_n_s32_f32(inV,31);
+
+ vst1q_s32(pDst, outV);
+ pDst += 4;
+ pIn += 4;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 3;
+
+ while (blkCnt > 0U)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 2147483648 */
+ /* Convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* Convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+}
+#else
+void arm_float_to_q31(
+ const float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const float32_t *pIn = pSrc; /* Source pointer */
+
+#ifdef ARM_MATH_ROUNDING
+ float32_t in;
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * 2147483648 */
+
+ /* convert from float to Q31 and store result in destination buffer */
+#ifdef ARM_MATH_ROUNDING
+
+ in = (*pIn++ * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = (*pIn++ * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = (*pIn++ * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = (*pIn++ * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* Convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * 2147483648 */
+
+ /* convert from float to Q31 and store result in destination buffer */
+#ifdef ARM_MATH_ROUNDING
+
+ in = (*pIn++ * 2147483648.0f);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* Convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of float_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c b/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c
new file mode 100644
index 000000000..5f2a7eb02
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,253 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_float_to_q7.c
+ * Description: Converts the elements of the floating-point vector to Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup float_to_x
+ @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ *
+ * pDst[n] = (q7_t)(pSrc[n] * 128); 0 <= n < blockSize.
+ *
+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+#if defined(ARM_MATH_NEON)
+void arm_float_to_q7(
+ const float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ const float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+ float32_t in;
+ float32x4_t inV;
+ #ifdef ARM_MATH_ROUNDING
+ float32x4_t zeroV = vdupq_n_f32(0.0f);
+ float32x4_t pHalf = vdupq_n_f32(0.5f / 128.0f);
+ float32x4_t mHalf = vdupq_n_f32(-0.5f / 128.0f);
+ float32x4_t r;
+ uint32x4_t cmp;
+ #endif
+
+ int32x4_t cvt;
+ int16x4_t cvt1,cvt2;
+ int8x8_t outV;
+
+ blkCnt = blockSize >> 3U;
+
+ /* Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while (blkCnt > 0U)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* Convert from float to q7 and then store the results in the destination buffer */
+ inV = vld1q_f32(pIn);
+ cmp = vcgtq_f32(inV,zeroV);
+ r = vbslq_f32(cmp,pHalf,mHalf);
+ inV = vaddq_f32(inV, r);
+ cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7));
+ pIn += 4;
+
+ inV = vld1q_f32(pIn);
+ cmp = vcgtq_f32(inV,zeroV);
+ r = vbslq_f32(cmp,pHalf,mHalf);
+ inV = vaddq_f32(inV, r);
+ cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7));
+ pIn += 4;
+
+ outV = vqmovn_s16(vcombine_s16(cvt1,cvt2));
+ vst1_s8(pDst, outV);
+ pDst += 8;
+
+#else
+
+ /* C = A * 128 */
+ /* Convert from float to q7 and then store the results in the destination buffer */
+ inV = vld1q_f32(pIn);
+ cvt1 = vqmovn_s32(vcvtq_n_s32_f32(inV,7));
+ pIn += 4;
+
+ inV = vld1q_f32(pIn);
+ cvt2 = vqmovn_s32(vcvtq_n_s32_f32(inV,7));
+ pIn += 4;
+
+ outV = vqmovn_s16(vcombine_s16(cvt1,cvt2));
+
+ vst1_s8(pDst, outV);
+ pDst += 8;
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 7;
+
+ while (blkCnt > 0U)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* Convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* Convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+#else
+void arm_float_to_q7(
+ const float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const float32_t *pIn = pSrc; /* Source pointer */
+
+#ifdef ARM_MATH_ROUNDING
+ float32_t in;
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * 128 */
+
+ /* Convert from float to q7 and store result in destination buffer */
+#ifdef ARM_MATH_ROUNDING
+
+ in = (*pIn++ * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = (*pIn++ * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = (*pIn++ * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = (*pIn++ * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = A * 128 */
+
+ /* Convert from float to q7 and store result in destination buffer */
+#ifdef ARM_MATH_ROUNDING
+
+ in = (*pIn++ * 128);
+ in += in > 0.0f ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of float_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c b/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c
new file mode 100644
index 000000000..f49d9b77a
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,166 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q15_to_float.c
+ * Description: Converts the elements of the Q15 vector to floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q15_to_x Convert 16-bit Integer value
+ */
+
+/**
+ @addtogroup q15_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q15 vector to floating-point vector.
+ @param[in] pSrc points to the Q15 input vector
+ @param[out] pDst points to the floating-point output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (float32_t) pSrc[n] / 32768; 0 <= n < blockSize.
+
+ */
+
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+void arm_q15_to_float(
+ const q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ const q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+ int16x8_t inV;
+ int32x4_t inV0, inV1;
+ float32x4_t outV;
+
+ blkCnt = blockSize >> 3U;
+
+ /* Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 32768 */
+ /* convert from q15 to float and then store the results in the destination buffer */
+ inV = vld1q_s16(pIn);
+ pIn += 8;
+
+ inV0 = vmovl_s16(vget_low_s16(inV));
+ inV1 = vmovl_s16(vget_high_s16(inV));
+
+ outV = vcvtq_n_f32_s32(inV0,15);
+ vst1q_f32(pDst, outV);
+ pDst += 4;
+
+ outV = vcvtq_n_f32_s32(inV1,15);
+ vst1q_f32(pDst, outV);
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 7;
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 32768 */
+ /* convert from q15 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+#else
+void arm_q15_to_float(
+ const q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const q15_t *pIn = pSrc; /* Source pointer */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 32768 */
+
+ /* Convert from q15 to float and store result in destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 32768 */
+
+ /* Convert from q15 to float and store result in destination buffer */
+ *pDst++ = ((float32_t) *pIn++ / 32768.0f);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of q15_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c b/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
index 000000000..1afd48940
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,138 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q15_to_q31.c
+ * Description: Converts the elements of the Q15 vector to Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup q15_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q15 vector to Q31 vector.
+ @param[in] pSrc points to the Q15 input vector
+ @param[out] pDst points to the Q31 output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (q31_t) pSrc[n] << 16; 0 <= n < blockSize.
+
+ */
+
+void arm_q15_to_q31(
+ const q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const q15_t *pIn = pSrc; /* Source pointer */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+ q31_t in1, in2;
+ q31_t out1, out2, out3, out4;
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q31_t)A << 16 */
+
+ /* Convert from q15 to q31 and store result in destination buffer */
+ in1 = read_q15x2_ia ((q15_t **) &pIn);
+ in2 = read_q15x2_ia ((q15_t **) &pIn);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* extract lower 16 bits to 32 bit result */
+ out1 = in1 << 16U;
+ /* extract upper 16 bits to 32 bit result */
+ out2 = in1 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out3 = in2 << 16U;
+ /* extract upper 16 bits to 32 bit result */
+ out4 = in2 & 0xFFFF0000;
+
+#else
+
+ /* extract upper 16 bits to 32 bit result */
+ out1 = in1 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out2 = in1 << 16U;
+ /* extract upper 16 bits to 32 bit result */
+ out3 = in2 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out4 = in2 << 16U;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ *pDst++ = out1;
+ *pDst++ = out2;
+ *pDst++ = out3;
+ *pDst++ = out4;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q31_t) A << 16 */
+
+ /* Convert from q15 to q31 and store result in destination buffer */
+ *pDst++ = (q31_t) *pIn++ << 16;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of q15_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c b/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
index 000000000..d118b762b
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q15_to_q7.c
+ * Description: Converts the elements of the Q15 vector to Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup q15_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q15 vector to Q7 vector.
+ @param[in] pSrc points to the Q15 input vector
+ @param[out] pDst points to the Q7 output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (q7_t) pSrc[n] >> 8; 0 <= n < blockSize.
+
+ */
+
+void arm_q15_to_q7(
+ const q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const q15_t *pIn = pSrc; /* Source pointer */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in1, in2;
+ q31_t out1, out2;
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q7_t) A >> 8 */
+
+ /* Convert from q15 to q7 and store result in destination buffer */
+#if defined (ARM_MATH_DSP)
+
+ in1 = read_q15x2_ia ((q15_t **) &pIn);
+ in2 = read_q15x2_ia ((q15_t **) &pIn);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __PKHTB(in2, in1, 16);
+ out2 = __PKHBT(in2, in1, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHBT(in1, in2, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* rotate packed value by 24 */
+ out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
+
+ /* anding with 0xff00ff00 to get two 8 bit values */
+ out1 = out1 & 0xFF00FF00;
+ /* anding with 0x00ff00ff to get two 8 bit values */
+ out2 = out2 & 0x00FF00FF;
+
+ /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
+ out1 = out1 | out2;
+
+ /* store 4 samples at a time to destiantion buffer */
+ write_q7x4_ia (&pDst, out1);
+
+#else
+
+ *pDst++ = (q7_t) (*pIn++ >> 8);
+ *pDst++ = (q7_t) (*pIn++ >> 8);
+ *pDst++ = (q7_t) (*pIn++ >> 8);
+ *pDst++ = (q7_t) (*pIn++ >> 8);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q7_t) A >> 8 */
+
+ /* Convert from q15 to q7 and store result in destination buffer */
+ *pDst++ = (q7_t) (*pIn++ >> 8);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of q15_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c b/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c
new file mode 100644
index 000000000..03e7ec6f2
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q31_to_float.c
+ * Description: Converts the elements of the Q31 vector to floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q31_to_x Convert 32-bit Integer value
+ */
+
+/**
+ @addtogroup q31_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q31 vector to floating-point vector.
+ @param[in] pSrc points to the Q31 input vector
+ @param[out] pDst points to the floating-point output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (float32_t) pSrc[n] / 2147483648; 0 <= n < blockSize.
+
+ */
+
+#if defined(ARM_MATH_NEON_EXPERIMENTAL)
+void arm_q31_to_float(
+ const q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ const q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+ int32x4_t inV;
+ float32x4_t outV;
+
+ blkCnt = blockSize >> 2U;
+
+ /* Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 2147483648 */
+ /* Convert from q31 to float and then store the results in the destination buffer */
+ inV = vld1q_s32(pIn);
+ pIn += 4;
+
+ outV = vcvtq_n_f32_s32(inV,31);
+
+ vst1q_f32(pDst, outV);
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 3;
+
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 2147483648 */
+ /* Convert from q31 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+#else
+void arm_q31_to_float(
+ const q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ const q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 2147483648 */
+
+ /* Convert from q31 to float and store result in destination buffer */
+ *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 2147483648 */
+
+ /* Convert from q31 to float and store result in destination buffer */
+ *pDst++ = ((float32_t) *pIn++ / 2147483648.0f);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of q31_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c b/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
index 000000000..8d82c28aa
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q31_to_q15.c
+ * Description: Converts the elements of the Q31 vector to Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup q31_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q31 vector to Q15 vector.
+ @param[in] pSrc points to the Q31 input vector
+ @param[out] pDst points to the Q15 output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (q15_t) pSrc[n] >> 16; 0 <= n < blockSize.
+
+ */
+
+void arm_q31_to_q15(
+ const q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const q31_t *pIn = pSrc; /* Source pointer */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in1, in2, in3, in4;
+ q31_t out1, out2;
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q15_t) (A >> 16) */
+
+ /* Convert from q31 to q15 and store result in destination buffer */
+#if defined (ARM_MATH_DSP)
+
+ in1 = *pIn++;
+ in2 = *pIn++;
+ in3 = *pIn++;
+ in4 = *pIn++;
+
+ /* pack two higher 16-bit values from two 32-bit values */
+#ifndef ARM_MATH_BIG_ENDIAN
+ out1 = __PKHTB(in2, in1, 16);
+ out2 = __PKHTB(in4, in3, 16);
+#else
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHTB(in3, in4, 16);
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ write_q15x2_ia (&pDst, out1);
+ write_q15x2_ia (&pDst, out2);
+
+#else
+
+ *pDst++ = (q15_t) (*pIn++ >> 16);
+ *pDst++ = (q15_t) (*pIn++ >> 16);
+ *pDst++ = (q15_t) (*pIn++ >> 16);
+ *pDst++ = (q15_t) (*pIn++ >> 16);
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q15_t) (A >> 16) */
+
+ /* Convert from q31 to q15 and store result in destination buffer */
+ *pDst++ = (q15_t) (*pIn++ >> 16);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of q31_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c b/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
index 000000000..c7d1b4cec
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q31_to_q7.c
+ * Description: Converts the elements of the Q31 vector to Q7 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup q31_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q31 vector to Q7 vector.
+ @param[in] pSrc points to the Q31 input vector
+ @param[out] pDst points to the Q7 output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (q7_t) pSrc[n] >> 24; 0 <= n < blockSize.
+
+ */
+
+void arm_q31_to_q7(
+ const q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const q31_t *pIn = pSrc; /* Source pointer */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ q7_t out1, out2, out3, out4;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q7_t) (A >> 24) */
+
+ /* Convert from q31 to q7 and store result in destination buffer */
+
+ out1 = (q7_t) (*pIn++ >> 24);
+ out2 = (q7_t) (*pIn++ >> 24);
+ out3 = (q7_t) (*pIn++ >> 24);
+ out4 = (q7_t) (*pIn++ >> 24);
+ write_q7x4_ia (&pDst, __PACKq7(out1, out2, out3, out4));
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q7_t) (A >> 24) */
+
+ /* Convert from q31 to q7 and store result in destination buffer */
+ *pDst++ = (q7_t) (*pIn++ >> 24);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of q31_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c b/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c
new file mode 100644
index 000000000..6bd86bfeb
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,179 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q7_to_float.c
+ * Description: Converts the elements of the Q7 vector to floating-point vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q7_to_x Convert 8-bit Integer value
+ */
+
+/**
+ @addtogroup q7_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q7 vector to floating-point vector.
+ @param[in] pSrc points to the Q7 input vector
+ @param[out] pDst points to the floating-point output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (float32_t) pSrc[n] / 128; 0 <= n < blockSize.
+
+ */
+
+#if defined(ARM_MATH_NEON)
+void arm_q7_to_float(
+ const q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ const q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+ int8x16_t inV;
+ int16x8_t inVLO, inVHI;
+ int32x4_t inVLL, inVLH, inVHL, inVHH;
+ float32x4_t outV;
+
+ blkCnt = blockSize >> 4U;
+
+ /* Compute 16 outputs at a time.
+ ** a second loop below computes the remaining 1 to 15 samples. */
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 128 */
+ /* Convert from q7 to float and then store the results in the destination buffer */
+ inV = vld1q_s8(pIn);
+ pIn += 16;
+
+ inVLO = vmovl_s8(vget_low_s8(inV));
+ inVHI = vmovl_s8(vget_high_s8(inV));
+
+ inVLL = vmovl_s16(vget_low_s16(inVLO));
+ inVLH = vmovl_s16(vget_high_s16(inVLO));
+ inVHL = vmovl_s16(vget_low_s16(inVHI));
+ inVHH = vmovl_s16(vget_high_s16(inVHI));
+
+ outV = vcvtq_n_f32_s32(inVLL,7);
+ vst1q_f32(pDst, outV);
+ pDst += 4;
+
+ outV = vcvtq_n_f32_s32(inVLH,7);
+ vst1q_f32(pDst, outV);
+ pDst += 4;
+
+ outV = vcvtq_n_f32_s32(inVHL,7);
+ vst1q_f32(pDst, outV);
+ pDst += 4;
+
+ outV = vcvtq_n_f32_s32(inVHH,7);
+ vst1q_f32(pDst, outV);
+ pDst += 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 16, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize & 0xF;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 128 */
+ /* Convert from q7 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+#else
+void arm_q7_to_float(
+ const q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const q7_t *pIn = pSrc; /* Source pointer */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 128 */
+
+ /* Convert from q7 to float and store result in destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (float32_t) A / 128 */
+
+ /* Convert from q7 to float and store result in destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+#endif /* #if defined(ARM_MATH_NEON) */
+
+/**
+ @} end of q7_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c b/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
index 000000000..89afd10a8
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q7_to_q15.c
+ * Description: Converts the elements of the Q7 vector to Q15 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup q7_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q7 vector to Q15 vector.
+ @param[in] pSrc points to the Q7 input vector
+ @param[out] pDst points to the Q15 output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (q15_t) pSrc[n] << 8; 0 <= n < blockSize.
+
+ */
+
+void arm_q7_to_q15(
+ const q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const q7_t *pIn = pSrc; /* Source pointer */
+
+#if defined (ARM_MATH_LOOPUNROLL) && defined (ARM_MATH_DSP)
+ q31_t in;
+ q31_t in1, in2;
+ q31_t out1, out2;
+#endif
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q15_t) A << 8 */
+
+ /* Convert from q7 to q15 and store result in destination buffer */
+#if defined (ARM_MATH_DSP)
+
+ in = read_q7x4_ia ((q7_t **) &pIn);
+
+ /* rotatate in by 8 and extend two q7_t values to q15_t values */
+ in1 = __SXTB16(__ROR(in, 8));
+
+ /* extend remainig two q7_t values to q15_t values */
+ in2 = __SXTB16(in);
+
+ in1 = in1 << 8U;
+ in2 = in2 << 8U;
+
+ in1 = in1 & 0xFF00FF00;
+ in2 = in2 & 0xFF00FF00;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ out2 = __PKHTB(in1, in2, 16);
+ out1 = __PKHBT(in2, in1, 16);
+#else
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHBT(in2, in1, 16);
+#endif
+
+ write_q15x2_ia (&pDst, out1);
+ write_q15x2_ia (&pDst, out2);
+
+#else
+
+ *pDst++ = (q15_t) *pIn++ << 8;
+ *pDst++ = (q15_t) *pIn++ << 8;
+ *pDst++ = (q15_t) *pIn++ << 8;
+ *pDst++ = (q15_t) *pIn++ << 8;
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q15_t) A << 8 */
+
+ /* Convert from q7 to q15 and store result in destination buffer */
+ *pDst++ = (q15_t) * pIn++ << 8;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of q7_to_x group
+ */
diff --git a/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c b/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
index 000000000..641c02d89
--- /dev/null
+++ b/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_q7_to_q31.c
+ * Description: Converts the elements of the Q7 vector to Q31 vector
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupSupport
+ */
+
+/**
+ @addtogroup q7_to_x
+ @{
+ */
+
+/**
+ @brief Converts the elements of the Q7 vector to Q31 vector.
+ @param[in] pSrc points to the Q7 input vector
+ @param[out] pDst points to the Q31 output vector
+ @param[in] blockSize number of samples in each vector
+ @return none
+
+ @par Details
+ The equation used for the conversion process is:
+
+ pDst[n] = (q31_t) pSrc[n] << 24; 0 <= n < blockSize.
+
+ */
+
+void arm_q7_to_q31(
+ const q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* Loop counter */
+ const q7_t *pIn = pSrc; /* Source pointer */
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ q31_t in;
+
+ /* Loop unrolling: Compute 4 outputs at a time */
+ blkCnt = blockSize >> 2U;
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q31_t) A << 24 */
+
+ /* Convert from q7 to q31 and store result in destination buffer */
+ in = read_q7x4_ia ((q7_t **) &pIn);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+ *pDst++ = (in & 0xFF000000);
+
+#else
+
+ *pDst++ = (in & 0xFF000000);
+ *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+ /* Loop unrolling: Compute remaining outputs */
+ blkCnt = blockSize % 0x4U;
+
+#else
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+ while (blkCnt > 0U)
+ {
+ /* C = (q31_t) A << 24 */
+
+ /* Convert from q7 to q31 and store result in destination buffer */
+ *pDst++ = (q31_t) * pIn++ << 24;
+
+ /* Decrement loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ @} end of q7_to_x group
+ */
diff --git a/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c b/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c
new file mode 100644
index 000000000..d0f7ce46d
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c
@@ -0,0 +1,60 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: TransformFunctions.c
+ * Description: Combination of all transform function source files.
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.0.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_bitreversal.c"
+#include "arm_bitreversal2.c"
+#include "arm_cfft_f32.c"
+#include "arm_cfft_q15.c"
+#include "arm_cfft_q31.c"
+#include "arm_cfft_radix2_f32.c"
+#include "arm_cfft_radix2_init_f32.c"
+#include "arm_cfft_radix2_init_q15.c"
+#include "arm_cfft_radix2_init_q31.c"
+#include "arm_cfft_radix2_q15.c"
+#include "arm_cfft_radix2_q31.c"
+#include "arm_cfft_radix4_f32.c"
+#include "arm_cfft_radix4_init_f32.c"
+#include "arm_cfft_radix4_init_q15.c"
+#include "arm_cfft_radix4_init_q31.c"
+#include "arm_cfft_radix4_q15.c"
+#include "arm_cfft_radix4_q31.c"
+#include "arm_cfft_radix8_f32.c"
+#include "arm_dct4_f32.c"
+#include "arm_dct4_init_f32.c"
+#include "arm_dct4_init_q15.c"
+#include "arm_dct4_init_q31.c"
+#include "arm_dct4_q15.c"
+#include "arm_dct4_q31.c"
+#include "arm_rfft_f32.c"
+#include "arm_rfft_fast_f32.c"
+#include "arm_rfft_fast_init_f32.c"
+#include "arm_rfft_init_f32.c"
+#include "arm_rfft_init_q15.c"
+#include "arm_rfft_init_q31.c"
+#include "arm_rfft_q15.c"
+#include "arm_rfft_q31.c"
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S b/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S
new file mode 100644
index 000000000..c16091b15
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S
@@ -0,0 +1,216 @@
+;/* ----------------------------------------------------------------------
+; * Project: CMSIS DSP Library
+; * Title: arm_bitreversal2.S
+; * Description: arm_bitreversal_32 function done in assembly for maximum speed.
+; * Called after doing an fft to reorder the output.
+; * The function is loop unrolled by 2. arm_bitreversal_16 as well.
+; *
+; * $Date: 18. March 2019
+; * $Revision: V1.5.2
+; *
+; * Target Processor: Cortex-M cores
+; * -------------------------------------------------------------------- */
+;/*
+; * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+; *
+; * SPDX-License-Identifier: Apache-2.0
+; *
+; * Licensed under the Apache License, Version 2.0 (the License); you may
+; * not use this file except in compliance with the License.
+; * You may obtain a copy of the License at
+; *
+; * www.apache.org/licenses/LICENSE-2.0
+; *
+; * Unless required by applicable law or agreed to in writing, software
+; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+; * See the License for the specific language governing permissions and
+; * limitations under the License.
+; */
+
+#if defined ( __CC_ARM ) /* Keil */
+ #define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
+ #define LABEL
+#elif defined ( __IASMARM__ ) /* IAR */
+ #define CODESECT SECTION `.text`:CODE
+ #define PROC
+ #define LABEL
+ #define ENDP
+ #define EXPORT PUBLIC
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #define CODESECT switch .text
+ #define THUMB
+ #define EXPORT xdef
+ #define PROC :
+ #define LABEL :
+ #define ENDP
+ #define arm_bitreversal_32 _arm_bitreversal_32
+#elif defined ( __TI_ARM__ ) /* TI ARM */
+ #define THUMB .thumb
+ #define CODESECT .text
+ #define EXPORT .global
+ #define PROC : .asmfunc
+ #define LABEL :
+ #define ENDP .endasmfunc
+ #define END
+#elif defined ( __GNUC__ ) /* GCC */
+ #define THUMB .thumb
+ #define CODESECT .section .text
+ #define EXPORT .global
+ #define PROC :
+ #define LABEL :
+ #define ENDP
+ #define END
+
+ .syntax unified
+#endif
+
+ CODESECT
+ THUMB
+
+;/**
+; @brief In-place bit reversal function.
+; @param[in,out] pSrc points to the in-place buffer of unknown 32-bit data type
+; @param[in] bitRevLen bit reversal table length
+; @param[in] pBitRevTab points to bit reversal table
+; @return none
+; */
+ EXPORT arm_bitreversal_32
+ EXPORT arm_bitreversal_16
+
+#if defined ( __CC_ARM ) /* Keil */
+#elif defined ( __IASMARM__ ) /* IAR */
+#elif defined ( __CSMC__ ) /* Cosmic */
+#elif defined ( __TI_ARM__ ) /* TI ARM */
+#elif defined ( __GNUC__ ) /* GCC */
+ .type arm_bitreversal_16, %function
+ .type arm_bitreversal_32, %function
+#endif
+
+#if defined (ARM_MATH_CM0_FAMILY)
+
+arm_bitreversal_32 PROC
+ ADDS r3,r1,#1
+ PUSH {r4-r6}
+ ADDS r1,r2,#0
+ LSRS r3,r3,#1
+arm_bitreversal_32_0 LABEL
+ LDRH r2,[r1,#2]
+ LDRH r6,[r1,#0]
+ ADD r2,r0,r2
+ ADD r6,r0,r6
+ LDR r5,[r2,#0]
+ LDR r4,[r6,#0]
+ STR r5,[r6,#0]
+ STR r4,[r2,#0]
+ LDR r5,[r2,#4]
+ LDR r4,[r6,#4]
+ STR r5,[r6,#4]
+ STR r4,[r2,#4]
+ ADDS r1,r1,#4
+ SUBS r3,r3,#1
+ BNE arm_bitreversal_32_0
+ POP {r4-r6}
+ BX lr
+ ENDP
+
+arm_bitreversal_16 PROC
+ ADDS r3,r1,#1
+ PUSH {r4-r6}
+ ADDS r1,r2,#0
+ LSRS r3,r3,#1
+arm_bitreversal_16_0 LABEL
+ LDRH r2,[r1,#2]
+ LDRH r6,[r1,#0]
+ LSRS r2,r2,#1
+ LSRS r6,r6,#1
+ ADD r2,r0,r2
+ ADD r6,r0,r6
+ LDR r5,[r2,#0]
+ LDR r4,[r6,#0]
+ STR r5,[r6,#0]
+ STR r4,[r2,#0]
+ ADDS r1,r1,#4
+ SUBS r3,r3,#1
+ BNE arm_bitreversal_16_0
+ POP {r4-r6}
+ BX lr
+ ENDP
+
+#else
+
+arm_bitreversal_32 PROC
+ ADDS r3,r1,#1
+ CMP r3,#1
+ IT LS
+ BXLS lr
+ PUSH {r4-r9}
+ ADDS r1,r2,#2
+ LSRS r3,r3,#2
+arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
+ LDRH r8,[r1,#4]
+ LDRH r9,[r1,#2]
+ LDRH r2,[r1,#0]
+ LDRH r12,[r1,#-2]
+ ADD r8,r0,r8
+ ADD r9,r0,r9
+ ADD r2,r0,r2
+ ADD r12,r0,r12
+ LDR r7,[r9,#0]
+ LDR r6,[r8,#0]
+ LDR r5,[r2,#0]
+ LDR r4,[r12,#0]
+ STR r6,[r9,#0]
+ STR r7,[r8,#0]
+ STR r5,[r12,#0]
+ STR r4,[r2,#0]
+ LDR r7,[r9,#4]
+ LDR r6,[r8,#4]
+ LDR r5,[r2,#4]
+ LDR r4,[r12,#4]
+ STR r6,[r9,#4]
+ STR r7,[r8,#4]
+ STR r5,[r12,#4]
+ STR r4,[r2,#4]
+ ADDS r1,r1,#8
+ SUBS r3,r3,#1
+ BNE arm_bitreversal_32_0
+ POP {r4-r9}
+ BX lr
+ ENDP
+
+arm_bitreversal_16 PROC
+ ADDS r3,r1,#1
+ CMP r3,#1
+ IT LS
+ BXLS lr
+ PUSH {r4-r9}
+ ADDS r1,r2,#2
+ LSRS r3,r3,#2
+arm_bitreversal_16_0 LABEL ;/* loop unrolled by 2 */
+ LDRH r8,[r1,#4]
+ LDRH r9,[r1,#2]
+ LDRH r2,[r1,#0]
+ LDRH r12,[r1,#-2]
+ ADD r8,r0,r8,LSR #1
+ ADD r9,r0,r9,LSR #1
+ ADD r2,r0,r2,LSR #1
+ ADD r12,r0,r12,LSR #1
+ LDR r7,[r9,#0]
+ LDR r6,[r8,#0]
+ LDR r5,[r2,#0]
+ LDR r4,[r12,#0]
+ STR r6,[r9,#0]
+ STR r7,[r8,#0]
+ STR r5,[r12,#0]
+ STR r4,[r2,#0]
+ ADDS r1,r1,#8
+ SUBS r3,r3,#1
+ BNE arm_bitreversal_16_0
+ POP {r4-r9}
+ BX lr
+ ENDP
+
+#endif
+
+ END
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c
new file mode 100644
index 000000000..2fff61cab
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c
@@ -0,0 +1,629 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cfft_f32.c
+ * Description: Combined Radix Decimation in Frequency CFFT Floating point processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern void arm_radix8_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+ uint32_t * pSrc,
+ const uint16_t bitRevLen,
+ const uint16_t * pBitRevTable);
+
+/**
+ @ingroup groupTransforms
+ */
+
+/**
+ @defgroup ComplexFFT Complex FFT Functions
+
+ @par
+ The Fast Fourier Transform (FFT) is an efficient algorithm for computing the
+ Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster
+ than the DFT, especially for long lengths.
+ The algorithms described in this section
+ operate on complex data. A separate set of functions is devoted to handling
+ of real sequences.
+ @par
+ There are separate algorithms for handling floating-point, Q15, and Q31 data
+ types. The algorithms available for each data type are described next.
+ @par
+ The FFT functions operate in-place. That is, the array holding the input data
+ will also be used to hold the corresponding result. The input data is complex
+ and contains 2*fftLen interleaved values as shown below.
+ {real[0], imag[0], real[1], imag[1], ...}
+ The FFT result will be contained in the same array and the frequency domain
+ values will have the same interleaving.
+
+ @par Floating-point
+ The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8
+ stages are performed along with a single radix-2 or radix-4 stage, as needed.
+ The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+ a different twiddle factor table.
+ @par
+ The function uses the standard FFT definition and output values may grow by a
+ factor of fftLen when computing the forward transform. The
+ inverse transform includes a scale of 1/fftLen as part of the
+ calculation and this matches the textbook definition of the inverse FFT.
+ @par
+ Pre-initialized data structures containing twiddle factors and bit reversal
+ tables are provided and defined in arm_const_structs.h. Include
+ this header in your function and then pass one of the constant structures as
+ an argument to arm_cfft_f32. For example:
+ @par
+ arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)
+ @par
+ computes a 64-point inverse complex FFT including bit reversal.
+ The data structures are treated as constant data and not modified during the
+ calculation. The same data structure can be reused for multiple transforms
+ including mixing forward and inverse transforms.
+ @par
+ Earlier releases of the library provided separate radix-2 and radix-4
+ algorithms that operated on floating-point data. These functions are still
+ provided but are deprecated. The older functions are slower and less general
+ than the new functions.
+ @par
+ An example of initialization of the constants for the arm_cfft_f32 function follows:
+ @code
+ const static arm_cfft_instance_f32 *S;
+ ...
+ switch (length) {
+ case 16:
+ S = &arm_cfft_sR_f32_len16;
+ break;
+ case 32:
+ S = &arm_cfft_sR_f32_len32;
+ break;
+ case 64:
+ S = &arm_cfft_sR_f32_len64;
+ break;
+ case 128:
+ S = &arm_cfft_sR_f32_len128;
+ break;
+ case 256:
+ S = &arm_cfft_sR_f32_len256;
+ break;
+ case 512:
+ S = &arm_cfft_sR_f32_len512;
+ break;
+ case 1024:
+ S = &arm_cfft_sR_f32_len1024;
+ break;
+ case 2048:
+ S = &arm_cfft_sR_f32_len2048;
+ break;
+ case 4096:
+ S = &arm_cfft_sR_f32_len4096;
+ break;
+ }
+ @endcode
+ @par Q15 and Q31
+ The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-4
+ stages are performed along with a single radix-2 stage, as needed.
+ The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+ a different twiddle factor table.
+ @par
+ The function uses the standard FFT definition and output values may grow by a
+ factor of fftLen when computing the forward transform. The
+ inverse transform includes a scale of 1/fftLen as part of the
+ calculation and this matches the textbook definition of the inverse FFT.
+ @par
+ Pre-initialized data structures containing twiddle factors and bit reversal
+ tables are provided and defined in arm_const_structs.h. Include
+ this header in your function and then pass one of the constant structures as
+ an argument to arm_cfft_q31. For example:
+ @par
+ arm_cfft_q31(arm_cfft_sR_q31_len64, pSrc, 1, 1)
+ @par
+ computes a 64-point inverse complex FFT including bit reversal.
+ The data structures are treated as constant data and not modified during the
+ calculation. The same data structure can be reused for multiple transforms
+ including mixing forward and inverse transforms.
+ @par
+ Earlier releases of the library provided separate radix-2 and radix-4
+ algorithms that operated on floating-point data. These functions are still
+ provided but are deprecated. The older functions are slower and less general
+ than the new functions.
+ @par
+ An example of initialization of the constants for the arm_cfft_q31 function follows:
+ @code
+ const static arm_cfft_instance_q31 *S;
+ ...
+ switch (length) {
+ case 16:
+ S = &arm_cfft_sR_q31_len16;
+ break;
+ case 32:
+ S = &arm_cfft_sR_q31_len32;
+ break;
+ case 64:
+ S = &arm_cfft_sR_q31_len64;
+ break;
+ case 128:
+ S = &arm_cfft_sR_q31_len128;
+ break;
+ case 256:
+ S = &arm_cfft_sR_q31_len256;
+ break;
+ case 512:
+ S = &arm_cfft_sR_q31_len512;
+ break;
+ case 1024:
+ S = &arm_cfft_sR_q31_len1024;
+ break;
+ case 2048:
+ S = &arm_cfft_sR_q31_len2048;
+ break;
+ case 4096:
+ S = &arm_cfft_sR_q31_len4096;
+ break;
+ }
+ @endcode
+
+ */
+
+void arm_cfft_radix8by2_f32 (arm_cfft_instance_f32 * S, float32_t * p1)
+{
+ uint32_t L = S->fftLen;
+ float32_t * pCol1, * pCol2, * pMid1, * pMid2;
+ float32_t * p2 = p1 + L;
+ const float32_t * tw = (float32_t *) S->pTwiddle;
+ float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;
+ float32_t m0, m1, m2, m3;
+ uint32_t l;
+
+ pCol1 = p1;
+ pCol2 = p2;
+
+ /* Define new length */
+ L >>= 1;
+
+ /* Initialize mid pointers */
+ pMid1 = p1 + L;
+ pMid2 = p2 + L;
+
+ /* do two dot Fourier transform */
+ for (l = L >> 2; l > 0; l-- )
+ {
+ t1[0] = p1[0];
+ t1[1] = p1[1];
+ t1[2] = p1[2];
+ t1[3] = p1[3];
+
+ t2[0] = p2[0];
+ t2[1] = p2[1];
+ t2[2] = p2[2];
+ t2[3] = p2[3];
+
+ t3[0] = pMid1[0];
+ t3[1] = pMid1[1];
+ t3[2] = pMid1[2];
+ t3[3] = pMid1[3];
+
+ t4[0] = pMid2[0];
+ t4[1] = pMid2[1];
+ t4[2] = pMid2[2];
+ t4[3] = pMid2[3];
+
+ *p1++ = t1[0] + t2[0];
+ *p1++ = t1[1] + t2[1];
+ *p1++ = t1[2] + t2[2];
+ *p1++ = t1[3] + t2[3]; /* col 1 */
+
+ t2[0] = t1[0] - t2[0];
+ t2[1] = t1[1] - t2[1];
+ t2[2] = t1[2] - t2[2];
+ t2[3] = t1[3] - t2[3]; /* for col 2 */
+
+ *pMid1++ = t3[0] + t4[0];
+ *pMid1++ = t3[1] + t4[1];
+ *pMid1++ = t3[2] + t4[2];
+ *pMid1++ = t3[3] + t4[3]; /* col 1 */
+
+ t4[0] = t4[0] - t3[0];
+ t4[1] = t4[1] - t3[1];
+ t4[2] = t4[2] - t3[2];
+ t4[3] = t4[3] - t3[3]; /* for col 2 */
+
+ twR = *tw++;
+ twI = *tw++;
+
+ /* multiply by twiddle factors */
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ /* R = R * Tr - I * Ti */
+ *p2++ = m0 + m1;
+ /* I = I * Tr + R * Ti */
+ *p2++ = m2 - m3;
+
+ /* use vertical symmetry */
+ /* 0.9988 - 0.0491i <==> -0.0491 - 0.9988i */
+ m0 = t4[0] * twI;
+ m1 = t4[1] * twR;
+ m2 = t4[1] * twI;
+ m3 = t4[0] * twR;
+
+ *pMid2++ = m0 - m1;
+ *pMid2++ = m2 + m3;
+
+ twR = *tw++;
+ twI = *tw++;
+
+ m0 = t2[2] * twR;
+ m1 = t2[3] * twI;
+ m2 = t2[3] * twR;
+ m3 = t2[2] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+
+ m0 = t4[2] * twI;
+ m1 = t4[3] * twR;
+ m2 = t4[3] * twI;
+ m3 = t4[2] * twR;
+
+ *pMid2++ = m0 - m1;
+ *pMid2++ = m2 + m3;
+ }
+
+ /* first col */
+ arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 2U);
+
+ /* second col */
+ arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 2U);
+}
+
+void arm_cfft_radix8by4_f32 (arm_cfft_instance_f32 * S, float32_t * p1)
+{
+ uint32_t L = S->fftLen >> 1;
+ float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;
+ const float32_t *tw2, *tw3, *tw4;
+ float32_t * p2 = p1 + L;
+ float32_t * p3 = p2 + L;
+ float32_t * p4 = p3 + L;
+ float32_t t2[4], t3[4], t4[4], twR, twI;
+ float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;
+ float32_t m0, m1, m2, m3;
+ uint32_t l, twMod2, twMod3, twMod4;
+
+ pCol1 = p1; /* points to real values by default */
+ pCol2 = p2;
+ pCol3 = p3;
+ pCol4 = p4;
+ pEnd1 = p2 - 1; /* points to imaginary values by default */
+ pEnd2 = p3 - 1;
+ pEnd3 = p4 - 1;
+ pEnd4 = pEnd3 + L;
+
+ tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;
+
+ L >>= 1;
+
+ /* do four dot Fourier transform */
+
+ twMod2 = 2;
+ twMod3 = 4;
+ twMod4 = 6;
+
+ /* TOP */
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+
+ /* col 2 */
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ /* col 3 */
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ /* col 4 */
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ /* col 1 */
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ /* Twiddle factors are ones */
+ *p2++ = t2[0];
+ *p2++ = t2[1];
+ *p3++ = t3[0];
+ *p3++ = t3[1];
+ *p4++ = t4[0];
+ *p4++ = t4[1];
+
+ tw2 += twMod2;
+ tw3 += twMod3;
+ tw4 += twMod4;
+
+ for (l = (L - 2) >> 1; l > 0; l-- )
+ {
+ /* TOP */
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+ /* col 2 */
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ /* col 3 */
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ /* col 4 */
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ /* col 1 - top */
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ /* BOTTOM */
+ p1ap3_1 = pEnd1[-1] + pEnd3[-1];
+ p1sp3_1 = pEnd1[-1] - pEnd3[-1];
+ p1ap3_0 = pEnd1[ 0] + pEnd3[0];
+ p1sp3_0 = pEnd1[ 0] - pEnd3[0];
+ /* col 2 */
+ t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1;
+ t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];
+ /* col 3 */
+ t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];
+ t3[3] = p1ap3_0 - pEnd2[ 0] - pEnd4[ 0];
+ /* col 4 */
+ t4[2] = pEnd2[ 0] - pEnd4[ 0] - p1sp3_1;
+ t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;
+ /* col 1 - Bottom */
+ *pEnd1-- = p1ap3_0 + pEnd2[ 0] + pEnd4[ 0];
+ *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];
+
+ /* COL 2 */
+ /* read twiddle factors */
+ twR = *tw2++;
+ twI = *tw2++;
+ /* multiply by twiddle factors */
+ /* let Z1 = a + i(b), Z2 = c + i(d) */
+ /* => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d) */
+
+ /* Top */
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+ /* use vertical symmetry col 2 */
+ /* 0.9997 - 0.0245i <==> 0.0245 - 0.9997i */
+ /* Bottom */
+ m0 = t2[3] * twI;
+ m1 = t2[2] * twR;
+ m2 = t2[2] * twI;
+ m3 = t2[3] * twR;
+
+ *pEnd2-- = m0 - m1;
+ *pEnd2-- = m2 + m3;
+
+ /* COL 3 */
+ twR = tw3[0];
+ twI = tw3[1];
+ tw3 += twMod3;
+ /* Top */
+ m0 = t3[0] * twR;
+ m1 = t3[1] * twI;
+ m2 = t3[1] * twR;
+ m3 = t3[0] * twI;
+
+ *p3++ = m0 + m1;
+ *p3++ = m2 - m3;
+ /* use vertical symmetry col 3 */
+ /* 0.9988 - 0.0491i <==> -0.9988 - 0.0491i */
+ /* Bottom */
+ m0 = -t3[3] * twR;
+ m1 = t3[2] * twI;
+ m2 = t3[2] * twR;
+ m3 = t3[3] * twI;
+
+ *pEnd3-- = m0 - m1;
+ *pEnd3-- = m3 - m2;
+
+ /* COL 4 */
+ twR = tw4[0];
+ twI = tw4[1];
+ tw4 += twMod4;
+ /* Top */
+ m0 = t4[0] * twR;
+ m1 = t4[1] * twI;
+ m2 = t4[1] * twR;
+ m3 = t4[0] * twI;
+
+ *p4++ = m0 + m1;
+ *p4++ = m2 - m3;
+ /* use vertical symmetry col 4 */
+ /* 0.9973 - 0.0736i <==> -0.0736 + 0.9973i */
+ /* Bottom */
+ m0 = t4[3] * twI;
+ m1 = t4[2] * twR;
+ m2 = t4[2] * twI;
+ m3 = t4[3] * twR;
+
+ *pEnd4-- = m0 - m1;
+ *pEnd4-- = m2 + m3;
+ }
+
+ /* MIDDLE */
+ /* Twiddle factors are */
+ /* 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i */
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+
+ /* col 2 */
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ /* col 3 */
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ /* col 4 */
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ /* col 1 - Top */
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ /* COL 2 */
+ twR = tw2[0];
+ twI = tw2[1];
+
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+ /* COL 3 */
+ twR = tw3[0];
+ twI = tw3[1];
+
+ m0 = t3[0] * twR;
+ m1 = t3[1] * twI;
+ m2 = t3[1] * twR;
+ m3 = t3[0] * twI;
+
+ *p3++ = m0 + m1;
+ *p3++ = m2 - m3;
+ /* COL 4 */
+ twR = tw4[0];
+ twI = tw4[1];
+
+ m0 = t4[0] * twR;
+ m1 = t4[1] * twI;
+ m2 = t4[1] * twR;
+ m3 = t4[0] * twI;
+
+ *p4++ = m0 + m1;
+ *p4++ = m2 - m3;
+
+ /* first col */
+ arm_radix8_butterfly_f32 (pCol1, L, (float32_t *) S->pTwiddle, 4U);
+
+ /* second col */
+ arm_radix8_butterfly_f32 (pCol2, L, (float32_t *) S->pTwiddle, 4U);
+
+ /* third col */
+ arm_radix8_butterfly_f32 (pCol3, L, (float32_t *) S->pTwiddle, 4U);
+
+ /* fourth col */
+ arm_radix8_butterfly_f32 (pCol4, L, (float32_t *) S->pTwiddle, 4U);
+}
+
+/**
+ @addtogroup ComplexFFT
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point complex FFT.
+ @param[in] S points to an instance of the floating-point CFFT structure
+ @param[in,out] p1 points to the complex data buffer of size 2*fftLen. Processing occurs in-place
+ @param[in] ifftFlag flag that selects transform direction
+ - value = 0: forward transform
+ - value = 1: inverse transform
+ @param[in] bitReverseFlag flag that enables / disables bit reversal of output
+ - value = 0: disables bit reversal of output
+ - value = 1: enables bit reversal of output
+ @return none
+ */
+
+void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ uint32_t L = S->fftLen, l;
+ float32_t invL, * pSrc;
+
+ if (ifftFlag == 1U)
+ {
+ /* Conjugate input data */
+ pSrc = p1 + 1;
+ for (l = 0; l < L; l++)
+ {
+ *pSrc = -*pSrc;
+ pSrc += 2;
+ }
+ }
+
+ switch (L)
+ {
+ case 16:
+ case 128:
+ case 1024:
+ arm_cfft_radix8by2_f32 ( (arm_cfft_instance_f32 *) S, p1);
+ break;
+ case 32:
+ case 256:
+ case 2048:
+ arm_cfft_radix8by4_f32 ( (arm_cfft_instance_f32 *) S, p1);
+ break;
+ case 64:
+ case 512:
+ case 4096:
+ arm_radix8_butterfly_f32 ( p1, L, (float32_t *) S->pTwiddle, 1);
+ break;
+ }
+
+ if ( bitReverseFlag )
+ arm_bitreversal_32 ((uint32_t*) p1, S->bitRevLength, S->pBitRevTable);
+
+ if (ifftFlag == 1U)
+ {
+ invL = 1.0f / (float32_t)L;
+
+ /* Conjugate and scale output data */
+ pSrc = p1;
+ for (l= 0; l < L; l++)
+ {
+ *pSrc++ *= invL ;
+ *pSrc = -(*pSrc) * invL;
+ pSrc++;
+ }
+ }
+}
+
+/**
+ @} end of ComplexFFT group
+ */
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c
new file mode 100644
index 000000000..f75e32909
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c
@@ -0,0 +1,470 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cfft_radix2_f32.c
+ * Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ const uint16_t * pBitRevTab);
+
+/**
+ @ingroup groupTransforms
+ */
+
+/**
+ @addtogroup ComplexFFT
+ @{
+ */
+
+/**
+ @brief Radix-2 CFFT/CIFFT.
+ @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future
+ @param[in] S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure
+ @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place
+ @return none
+ */
+
+void arm_cfft_radix2_f32(
+const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc)
+{
+
+ if (S->ifftFlag == 1U)
+ {
+ /* Complex IFFT radix-2 */
+ arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier, S->onebyfftLen);
+ }
+ else
+ {
+ /* Complex FFT radix-2 */
+ arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if (S->bitReverseFlag == 1U)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+
+/**
+ @} end of ComplexFFT group
+ */
+
+
+
+/* ----------------------------------------------------------------------
+ ** Internal helper function used by the FFTs
+ ** ------------------------------------------------------------------- */
+
+/**
+ brief Core function for the floating-point CFFT butterfly process.
+ param[in,out] pSrc points to in-place buffer of floating-point data type
+ param[in] fftLen length of the FFT
+ param[in] pCoef points to twiddle coefficient buffer
+ param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table
+ return none
+ */
+
+void arm_radix2_butterfly_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+
+ uint32_t i, j, k, l;
+ uint32_t n1, n2, ia;
+ float32_t xt, yt, cosVal, sinVal;
+ float32_t p0, p1, p2, p3;
+ float32_t a0, a1;
+
+#if defined (ARM_MATH_DSP)
+
+ /* Initializations for the first stage */
+ n2 = fftLen >> 1;
+ ia = 0;
+ i = 0;
+
+ // loop for groups
+ for (k = n2; k > 0; k--)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ /* Twiddle coefficients index modifier */
+ ia += twidCoefModifier;
+
+ /* index calculation for the input as, */
+ /* pSrc[i + 0], pSrc[i + fftLen/1] */
+ l = i + n2;
+
+ /* Butterfly implementation */
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i++;
+ } // groups loop end
+
+ twidCoefModifier <<= 1U;
+
+ // loop for stage
+ for (k = n2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i += n1;
+ } while ( i < fftLen ); // butterfly loop end
+ j++;
+ } while ( j < n2); // groups loop end
+ twidCoefModifier <<= 1U;
+ } // stages loop end
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += 2)
+ {
+ a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+ xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+ a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+ pSrc[2 * i + 2] = xt;
+ pSrc[2 * i + 3] = yt;
+ } // groups loop end
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+ n2 = fftLen;
+
+ // loop for stage
+ for (k = fftLen; k > 1; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i += n1;
+ } while (i < fftLen);
+ j++;
+ } while (j < n2);
+ twidCoefModifier <<= 1U;
+ }
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
+
+
+void arm_radix2_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen)
+{
+
+ uint32_t i, j, k, l;
+ uint32_t n1, n2, ia;
+ float32_t xt, yt, cosVal, sinVal;
+ float32_t p0, p1, p2, p3;
+ float32_t a0, a1;
+
+#if defined (ARM_MATH_DSP)
+
+ n2 = fftLen >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+ } // groups loop end
+
+ twidCoefModifier <<= 1U;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+
+ i += n1;
+ } while ( i < fftLen ); // butterfly loop end
+ j++;
+ } while (j < n2); // groups loop end
+
+ twidCoefModifier <<= 1U;
+ } // stages loop end
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += 2)
+ {
+ a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+ xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+ a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+ yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+
+ p0 = a0 * onebyfftLen;
+ p2 = xt * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p3 = yt * onebyfftLen;
+
+ pSrc[2 * i] = p0;
+ pSrc[2 * i + 1] = p1;
+ pSrc[2 * i + 2] = p2;
+ pSrc[2 * i + 3] = p3;
+ } // butterfly loop end
+
+#else /* #if defined (ARM_MATH_DSP) */
+
+ n2 = fftLen;
+
+ // loop for stage
+ for (k = fftLen; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+
+ i += n1;
+ } while ( i < fftLen ); // butterfly loop end
+ j++;
+ } while ( j < n2 ); // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1U;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+
+ p0 = a0 * onebyfftLen;
+ p2 = xt * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p3 = yt * onebyfftLen;
+
+ pSrc[2 * i] = p0;
+ pSrc[2 * l] = p2;
+
+ pSrc[2 * i + 1] = p1;
+ pSrc[2 * l + 1] = p3;
+ } // butterfly loop end
+
+#endif /* #if defined (ARM_MATH_DSP) */
+
+}
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
new file mode 100644
index 000000000..417ad9170
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c
@@ -0,0 +1,197 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cfft_radix2_init_f32.c
+ * Description: Radix-2 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ @ingroup groupTransforms
+ */
+
+/**
+ @addtogroup ComplexFFT
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point CFFT/CIFFT.
+ @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future.
+ @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure
+ @param[in] fftLen length of the FFT
+ @param[in] ifftFlag flag that selects transform direction
+ - value = 0: forward transform
+ - value = 1: inverse transform
+ @param[in] bitReverseFlag flag that enables / disables bit reversal of output
+ - value = 0: disables bit reversal of output
+ - value = 1: enables bit reversal of output
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length
+
+ @par Details
+ The parameter ifftFlag controls whether a forward or inverse transform is computed.
+ Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+ @par
+ The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+ Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+ @par
+ The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+ @par
+ This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+
+ case 4096U:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1U;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1U;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.000244140625;
+ break;
+
+ case 2048U:
+ /* Initializations of structure parameters for 2048 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2U;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2U;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.00048828125;
+ break;
+
+ case 1024U:
+ /* Initializations of structure parameters for 1024 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4U;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4U;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.0009765625f;
+ break;
+
+ case 512U:
+ /* Initializations of structure parameters for 512 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 8U;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 8U;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.001953125;
+ break;
+
+ case 256U:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16U;
+ S->bitRevFactor = 16U;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ S->onebyfftLen = 0.00390625f;
+ break;
+
+ case 128U:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32U;
+ S->bitRevFactor = 32U;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+ S->onebyfftLen = 0.0078125;
+ break;
+
+ case 64U:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64U;
+ S->bitRevFactor = 64U;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ S->onebyfftLen = 0.015625f;
+ break;
+
+ case 32U:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 128U;
+ S->bitRevFactor = 128U;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+ S->onebyfftLen = 0.03125;
+ break;
+
+ case 16U:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256U;
+ S->bitRevFactor = 256U;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ S->onebyfftLen = 0.0625f;
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ @} end of ComplexFFT group
+ */
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
index 000000000..96291458e
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1200 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cfft_radix4_f32.c
+ * Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ const uint16_t * pBitRevTab);
+
+void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+
+/**
+ @ingroup groupTransforms
+ */
+
+/**
+ @addtogroup ComplexFFT
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.
+ @deprecated Do not use this function. It has been superseded by \ref arm_cfft_f32 and will be removed in the future.
+ @param[in] S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure
+ @param[in,out] pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place
+ @return none
+ */
+
+void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc)
+{
+ if (S->ifftFlag == 1U)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier, S->onebyfftLen);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle, S->twidCoefModifier);
+ }
+
+ if (S->bitReverseFlag == 1U)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+ @} end of ComplexFFT group
+ */
+
+/* ----------------------------------------------------------------------
+ * Internal helper function used by the FFTs
+ * ---------------------------------------------------------------------- */
+
+/**
+ brief Core function for the floating-point CFFT butterfly process.
+ param[in,out] pSrc points to the in-place buffer of floating-point data type
+ param[in] fftLen length of the FFT
+ param[in] pCoef points to the twiddle coefficient buffer
+ param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table
+ return none
+ */
+
+void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+ float32_t co1, co2, co3, si1, si2, si3;
+ uint32_t ia1, ia2, ia3;
+ uint32_t i0, i1, i2, i3;
+ uint32_t n1, n2, j, k;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+ float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+ Ybminusd;
+ float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+ float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+ float32_t *ptr1;
+ float32_t p0,p1,p2,p3,p4,p5;
+ float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2U;
+ i0 = 0U;
+ ia1 = 0U;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2U * i0)];
+ yaIn = pSrc[(2U * i0) + 1U];
+
+ xbIn = pSrc[(2U * i1)];
+ ybIn = pSrc[(2U * i1) + 1U];
+
+ xcIn = pSrc[(2U * i2)];
+ ycIn = pSrc[(2U * i2) + 1U];
+
+ xdIn = pSrc[(2U * i3)];
+ ydIn = pSrc[(2U * i3) + 1U];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ co2 = pCoef[ia2 * 2U];
+ si2 = pCoef[(ia2 * 2U) + 1U];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* xb - xd */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* yb - yd */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[(2U * i0)] = Xaplusc + Xbplusd;
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd;
+
+ /* (xa - xc) + (yb - yd) */
+ Xb12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc - Xbminusd);
+ /* (xa + xc) - (xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) - (yb - yd) */
+ Xd12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yd12C_out = (Xbminusd + Yaminusc);
+
+ co1 = pCoef[ia1 * 2U];
+ si1 = pCoef[(ia1 * 2U) + 1U];
+
+ /* index calculation for the coefficients */
+ ia3 = ia2 + ia1;
+ co3 = pCoef[ia3 * 2U];
+ si3 = pCoef[(ia3 * 2U) + 1U];
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out += p0;
+ Yb12_out -= p1;
+ Xc12_out += p2;
+ Yc12_out -= p3;
+ Xd12_out += p4;
+ Yd12_out -= p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2U * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2U * i1) + 1U] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2U * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2U * i2) + 1U] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2U * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2U * i3) + 1U] = Yd12_out;
+
+ /* Twiddle coefficients index modifier */
+ ia1 += twidCoefModifier;
+
+ /* Updating input index */
+ i0++;
+
+ }
+ while (--j);
+
+ twidCoefModifier <<= 2U;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen >> 2U; k > 4U; k >>= 2U)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2U;
+ ia1 = 0U;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[(ia1 * 2U)];
+ si1 = pCoef[(ia1 * 2U) + 1U];
+ co2 = pCoef[(ia2 * 2U)];
+ si2 = pCoef[(ia2 * 2U) + 1U];
+ co3 = pCoef[(ia3 * 2U)];
+ si3 = pCoef[(ia3 * 2U) + 1U];
+
+ /* Twiddle coefficients index modifier */
+ ia1 += twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2U * i0)];
+ yaIn = pSrc[(2U * i0) + 1U];
+
+ xbIn = pSrc[(2U * i1)];
+ ybIn = pSrc[(2U * i1) + 1U];
+
+ xcIn = pSrc[(2U * i2)];
+ ycIn = pSrc[(2U * i2) + 1U];
+
+ xdIn = pSrc[(2U * i3)];
+ ydIn = pSrc[(2U * i3) + 1U];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* (xb - xd) */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* (yb - yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xa - xc) + (yb - yd) */
+ Xb12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yb12C_out = (Yaminusc - Xbminusd);
+ /* xa + xc -(xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) - (yb - yd) */
+ Xd12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yd12C_out = (Xbminusd + Yaminusc);
+
+ pSrc[(2U * i0)] = Xaplusc + Xbplusd;
+ pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd;
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out += p0;
+ Yb12_out -= p1;
+ Xc12_out += p2;
+ Yc12_out -= p3;
+ Xd12_out += p4;
+ Yd12_out -= p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2U * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2U * i1) + 1U] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2U * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2U * i2) + 1U] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2U * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2U * i3) + 1U] = Yd12_out;
+
+ i0 += n1;
+ } while (i0 < fftLen);
+ j++;
+ } while (j <= (n2 - 1U));
+ twidCoefModifier <<= 2U;
+ }
+
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+ xaIn = ptr1[0];
+ yaIn = ptr1[1];
+ xbIn = ptr1[2];
+ ybIn = ptr1[3];
+ xcIn = ptr1[4];
+ ycIn = ptr1[5];
+ xdIn = ptr1[6];
+ ydIn = ptr1[7];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xb-xd) */
+ Xbminusd = xbIn - xdIn;
+
+ /* (yb-yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ a0 = (Xaplusc + Xbplusd);
+ /* ya' = ya + yb + yc + yd */
+ a1 = (Yaplusc + Ybplusd);
+ /* xc' = (xa-xb+xc-xd) */
+ a2 = (Xaplusc - Xbplusd);
+ /* yc' = (ya-yb+yc-yd) */
+ a3 = (Yaplusc - Ybplusd);
+ /* xb' = (xa+yb-xc-yd) */
+ a4 = (Xaminusc + Ybminusd);
+ /* yb' = (ya-xb-yc+xd) */
+ a5 = (Yaminusc - Xbminusd);
+ /* xd' = (xa-yb-xc+yd)) */
+ a6 = (Xaminusc - Ybminusd);
+ /* yd' = (ya+xb-yc-xd) */
+ a7 = (Xbminusd + Yaminusc);
+
+ ptr1[0] = a0;
+ ptr1[1] = a1;
+ ptr1[2] = a2;
+ ptr1[3] = a3;
+ ptr1[4] = a4;
+ ptr1[5] = a5;
+ ptr1[6] = a6;
+ ptr1[7] = a7;
+
+ /* increment pointer by 8 */
+ ptr1 += 8U;
+ } while (--j);
+
+#else
+
+ float32_t t1, t2, r1, r2, s1, s2;
+
+ /* Initializations for the fft calculation */
+ n2 = fftLen;
+ n1 = n2;
+ for (k = fftLen; k > 1U; k >>= 2U)
+ {
+ /* Initializations for the fft calculation */
+ n1 = n2;
+ n2 >>= 2U;
+ ia1 = 0U;
+
+ /* FFT Calculation */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2U];
+ si1 = pCoef[(ia1 * 2U) + 1U];
+ co2 = pCoef[ia2 * 2U];
+ si2 = pCoef[(ia2 * 2U) + 1U];
+ co3 = pCoef[ia3 * 2U];
+ si3 = pCoef[(ia3 * 2U) + 1U];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* xa + xc */
+ r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)];
+
+ /* xa - xc */
+ r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)];
+
+ /* ya + yc */
+ s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U];
+
+ /* ya - yc */
+ s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U];
+
+ /* xb + xd */
+ t1 = pSrc[2U * i1] + pSrc[2U * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2U * i0] = r1 + t1;
+
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2U * i0) + 1U] = s1 + t2;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U];
+
+ /* (xb - xd) */
+ t2 = pSrc[2U * i1] - pSrc[2U * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2U * i1] = (r1 * co2) + (s1 * si2);
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2U * i1) + 1U] = (s1 * co2) - (r1 * si2);
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2U * i2] = (r1 * co1) + (s1 * si1);
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2U * i2) + 1U] = (s1 * co1) - (r1 * si1);
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2U * i3] = (r2 * co3) + (s2 * si3);
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2U * i3) + 1U] = (s2 * co3) - (r2 * si3);
+
+ i0 += n1;
+ } while ( i0 < fftLen);
+ j++;
+ } while (j <= (n2 - 1U));
+ twidCoefModifier <<= 2U;
+ }
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+}
+
+/**
+ brief Core function for the floating-point CIFFT butterfly process.
+ param[in,out] pSrc points to the in-place buffer of floating-point data type
+ param[in] fftLen length of the FFT
+ param[in] pCoef points to twiddle coefficient buffer
+ param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ param[in] onebyfftLen value of 1/fftLen
+ return none
+ */
+
+void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen)
+{
+ float32_t co1, co2, co3, si1, si2, si3;
+ uint32_t ia1, ia2, ia3;
+ uint32_t i0, i1, i2, i3;
+ uint32_t n1, n2, j, k;
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+ float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+ Ybminusd;
+ float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+ float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+ float32_t *ptr1;
+ float32_t p0,p1,p2,p3,p4,p5,p6,p7;
+ float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2U;
+ i0 = 0U;
+ ia1 = 0U;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ xaIn = pSrc[(2U * i0)];
+ yaIn = pSrc[(2U * i0) + 1U];
+
+ xcIn = pSrc[(2U * i2)];
+ ycIn = pSrc[(2U * i2) + 1U];
+
+ xbIn = pSrc[(2U * i1)];
+ ybIn = pSrc[(2U * i1) + 1U];
+
+ xdIn = pSrc[(2U * i3)];
+ ydIn = pSrc[(2U * i3) + 1U];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ co2 = pCoef[ia2 * 2U];
+ si2 = pCoef[(ia2 * 2U) + 1U];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* xb - xd */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* yb - yd */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[(2U * i0)] = Xaplusc + Xbplusd;
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd;
+
+ /* (xa - xc) - (yb - yd) */
+ Xb12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc + Xbminusd);
+ /* (xa + xc) - (xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) + (yb - yd) */
+ Xd12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yd12C_out = (Yaminusc - Xbminusd);
+
+ co1 = pCoef[ia1 * 2U];
+ si1 = pCoef[(ia1 * 2U) + 1U];
+
+ /* index calculation for the coefficients */
+ ia3 = ia2 + ia1;
+ co3 = pCoef[ia3 * 2U];
+ si3 = pCoef[(ia3 * 2U) + 1U];
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out -= p0;
+ Yb12_out += p1;
+ Xc12_out -= p2;
+ Yc12_out += p3;
+ Xd12_out -= p4;
+ Yd12_out += p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2U * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2U * i1) + 1U] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2U * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2U * i2) + 1U] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2U * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2U * i3) + 1U] = Yd12_out;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1U;
+
+ } while (--j);
+
+ twidCoefModifier <<= 2U;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen >> 2U; k > 4U; k >>= 2U)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2U;
+ ia1 = 0U;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2U];
+ si1 = pCoef[(ia1 * 2U) + 1U];
+ co2 = pCoef[ia2 * 2U];
+ si2 = pCoef[(ia2 * 2U) + 1U];
+ co3 = pCoef[ia3 * 2U];
+ si3 = pCoef[(ia3 * 2U) + 1U];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2U * i0)];
+ yaIn = pSrc[(2U * i0) + 1U];
+
+ xbIn = pSrc[(2U * i1)];
+ ybIn = pSrc[(2U * i1) + 1U];
+
+ xcIn = pSrc[(2U * i2)];
+ ycIn = pSrc[(2U * i2) + 1U];
+
+ xdIn = pSrc[(2U * i3)];
+ ydIn = pSrc[(2U * i3) + 1U];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* (xb - xd) */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* (yb - yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xa - xc) - (yb - yd) */
+ Xb12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc + Xbminusd);
+ /* xa + xc -(xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) + (yb - yd) */
+ Xd12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yd12C_out = (Yaminusc - Xbminusd);
+
+ pSrc[(2U * i0)] = Xaplusc + Xbplusd;
+ pSrc[(2U * i0) + 1U] = Yaplusc + Ybplusd;
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out -= p0;
+ Yb12_out += p1;
+ Xc12_out -= p2;
+ Yc12_out += p3;
+ Xd12_out -= p4;
+ Yd12_out += p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2U * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2U * i1) + 1U] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2U * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2U * i2) + 1U] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2U * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2U * i3) + 1U] = Yd12_out;
+
+ i0 += n1;
+ } while (i0 < fftLen);
+ j++;
+ } while (j <= (n2 - 1U));
+ twidCoefModifier <<= 2U;
+ }
+ /* Initializations of last stage */
+
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+ xaIn = ptr1[0];
+ yaIn = ptr1[1];
+ xbIn = ptr1[2];
+ ybIn = ptr1[3];
+ xcIn = ptr1[4];
+ ycIn = ptr1[5];
+ xdIn = ptr1[6];
+ ydIn = ptr1[7];
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xb-xd) */
+ Xbminusd = xbIn - xdIn;
+
+ /* (yb-yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+ a0 = (Xaplusc + Xbplusd);
+ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+ a1 = (Yaplusc + Ybplusd);
+ /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+ a2 = (Xaplusc - Xbplusd);
+ /* yc' = (ya-yb+yc-yd) * onebyfftLen */
+ a3 = (Yaplusc - Ybplusd);
+ /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+ a4 = (Xaminusc - Ybminusd);
+ /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+ a5 = (Yaminusc + Xbminusd);
+ /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+ a6 = (Xaminusc + Ybminusd);
+ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+ a7 = (Yaminusc - Xbminusd);
+
+ p0 = a0 * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p2 = a2 * onebyfftLen;
+ p3 = a3 * onebyfftLen;
+ p4 = a4 * onebyfftLen;
+ p5 = a5 * onebyfftLen;
+ p6 = a6 * onebyfftLen;
+ p7 = a7 * onebyfftLen;
+
+ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+ ptr1[0] = p0;
+ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+ ptr1[1] = p1;
+ /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+ ptr1[2] = p2;
+ /* yc' = (ya-yb+yc-yd) * onebyfftLen */
+ ptr1[3] = p3;
+ /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+ ptr1[4] = p4;
+ /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+ ptr1[5] = p5;
+ /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+ ptr1[6] = p6;
+ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+ ptr1[7] = p7;
+
+ /* increment source pointer by 8 for next calculations */
+ ptr1 = ptr1 + 8U;
+
+ } while (--j);
+
+#else
+
+ float32_t t1, t2, r1, r2, s1, s2;
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* Calculation of first stage */
+ for (k = fftLen; k > 4U; k >>= 2U)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2U;
+ ia1 = 0U;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2U];
+ si1 = pCoef[(ia1 * 2U) + 1U];
+ co2 = pCoef[ia2 * 2U];
+ si2 = pCoef[(ia2 * 2U) + 1U];
+ co3 = pCoef[ia3 * 2U];
+ si3 = pCoef[(ia3 * 2U) + 1U];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* xa + xc */
+ r1 = pSrc[(2U * i0)] + pSrc[(2U * i2)];
+
+ /* xa - xc */
+ r2 = pSrc[(2U * i0)] - pSrc[(2U * i2)];
+
+ /* ya + yc */
+ s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U];
+
+ /* ya - yc */
+ s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U];
+
+ /* xb + xd */
+ t1 = pSrc[2U * i1] + pSrc[2U * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2U * i0] = r1 + t1;
+
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2U * i0) + 1U] = s1 + t2;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U];
+
+ /* (xb - xd) */
+ t2 = pSrc[2U * i1] - pSrc[2U * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2U * i1] = (r1 * co2) - (s1 * si2);
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2U * i1) + 1U] = (s1 * co2) + (r1 * si2);
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2U * i2] = (r1 * co1) - (s1 * si1);
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2U * i2) + 1U] = (s1 * co1) + (r1 * si1);
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2U * i3] = (r2 * co3) - (s2 * si3);
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2U * i3) + 1U] = (s2 * co3) + (r2 * si3);
+
+ i0 += n1;
+ } while ( i0 < fftLen);
+ j++;
+ } while (j <= (n2 - 1U));
+ twidCoefModifier <<= 2U;
+ }
+ /* Initializations of last stage */
+ n1 = n2;
+ n2 >>= 2U;
+
+ /* Calculations of last stage */
+ for (i0 = 0U; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2U * i0] + pSrc[2U * i2];
+
+ /* xa - xc */
+ r2 = pSrc[2U * i0] - pSrc[2U * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2U * i0) + 1U] + pSrc[(2U * i2) + 1U];
+
+ /* ya - yc */
+ s2 = pSrc[(2U * i0) + 1U] - pSrc[(2U * i2) + 1U];
+
+ /* xc + xd */
+ t1 = pSrc[2U * i1] + pSrc[2U * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2U * i0] = (r1 + t1) * onebyfftLen;
+
+ /* (xa + xb) - (xc + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2U * i1) + 1U] + pSrc[(2U * i3) + 1U];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2U * i0) + 1U] = (s1 + t2) * onebyfftLen;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb-yd) */
+ t1 = pSrc[(2U * i1) + 1U] - pSrc[(2U * i3) + 1U];
+
+ /* (xb-xd) */
+ t2 = pSrc[2U * i1] - pSrc[2U * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2U * i1] = r1 * onebyfftLen;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2U * i1) + 1U] = s1 * onebyfftLen;
+
+ /* (xa - xc) - (yb-yd) */
+ r1 = r2 - t1;
+
+ /* (xa - xc) + (yb-yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb-xd) */
+ s1 = s2 + t2;
+
+ /* (ya - yc) - (xb-xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2U * i2] = r1 * onebyfftLen;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2U * i2) + 1U] = s1 * onebyfftLen;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2U * i3] = r2 * onebyfftLen;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2U * i3) + 1U] = s2 * onebyfftLen;
+ }
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+}
+
+
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
index 000000000..930c2c1e1
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cfft_radix4_init_f32.c
+ * Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ @ingroup groupTransforms
+ */
+
+/**
+ @addtogroup ComplexFFT
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point CFFT/CIFFT.
+ @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed in the future.
+ @param[in,out] S points to an instance of the floating-point CFFT/CIFFT structure
+ @param[in] fftLen length of the FFT
+ @param[in] ifftFlag flag that selects transform direction
+ - value = 0: forward transform
+ - value = 1: inverse transform
+ @param[in] bitReverseFlag flag that enables / disables bit reversal of output
+ - value = 0: disables bit reversal of output
+ - value = 1: enables bit reversal of output
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length
+
+ @par Details
+ The parameter ifftFlag controls whether a forward or inverse transform is computed.
+ Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+ @par
+ The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+ Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+ @par
+ The parameter fftLen Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+ @par
+ This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+ */
+
+arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+
+ case 4096U:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1U;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1U;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.000244140625;
+ break;
+
+ case 1024U:
+ /* Initializations of structure parameters for 1024 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4U;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4U;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.0009765625f;
+ break;
+
+
+ case 256U:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16U;
+ S->bitRevFactor = 16U;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ S->onebyfftLen = 0.00390625f;
+ break;
+
+ case 64U:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64U;
+ S->bitRevFactor = 64U;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ S->onebyfftLen = 0.015625f;
+ break;
+
+ case 16U:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256U;
+ S->bitRevFactor = 256U;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ S->onebyfftLen = 0.0625f;
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ @} end of ComplexFFT group
+ */
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c
new file mode 100644
index 000000000..50048f67d
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c
@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cfft_radix8_f32.c
+ * Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+
+/* ----------------------------------------------------------------------
+ * Internal helper function used by the FFTs
+ * -------------------------------------------------------------------- */
+
+/**
+ brief Core function for the floating-point CFFT butterfly process.
+ param[in,out] pSrc points to the in-place buffer of floating-point data type.
+ param[in] fftLen length of the FFT.
+ param[in] pCoef points to the twiddle coefficient buffer.
+ param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ return none
+*/
+
+void arm_radix8_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+ uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;
+ uint32_t i1, i2, i3, i4, i5, i6, i7, i8;
+ uint32_t id;
+ uint32_t n1, n2, j;
+
+ float32_t r1, r2, r3, r4, r5, r6, r7, r8;
+ float32_t t1, t2;
+ float32_t s1, s2, s3, s4, s5, s6, s7, s8;
+ float32_t p1, p2, p3, p4;
+ float32_t co2, co3, co4, co5, co6, co7, co8;
+ float32_t si2, si3, si4, si5, si6, si7, si8;
+ const float32_t C81 = 0.70710678118f;
+
+ n2 = fftLen;
+
+ do
+ {
+ n1 = n2;
+ n2 = n2 >> 3;
+ i1 = 0;
+
+ do
+ {
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+ i4 = i3 + n2;
+ i5 = i4 + n2;
+ i6 = i5 + n2;
+ i7 = i6 + n2;
+ i8 = i7 + n2;
+ r1 = pSrc[2 * i1] + pSrc[2 * i5];
+ r5 = pSrc[2 * i1] - pSrc[2 * i5];
+ r2 = pSrc[2 * i2] + pSrc[2 * i6];
+ r6 = pSrc[2 * i2] - pSrc[2 * i6];
+ r3 = pSrc[2 * i3] + pSrc[2 * i7];
+ r7 = pSrc[2 * i3] - pSrc[2 * i7];
+ r4 = pSrc[2 * i4] + pSrc[2 * i8];
+ r8 = pSrc[2 * i4] - pSrc[2 * i8];
+ t1 = r1 - r3;
+ r1 = r1 + r3;
+ r3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1] = r1 + r2;
+ pSrc[2 * i5] = r1 - r2;
+ r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+ s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+ r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+ s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+ s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+ s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+ r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+ s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+ t2 = r1 - s3;
+ r1 = r1 + s3;
+ s3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1 + 1] = r1 + r2;
+ pSrc[2 * i5 + 1] = r1 - r2;
+ pSrc[2 * i3] = t1 + s3;
+ pSrc[2 * i7] = t1 - s3;
+ pSrc[2 * i3 + 1] = t2 - r3;
+ pSrc[2 * i7 + 1] = t2 + r3;
+ r1 = (r6 - r8) * C81;
+ r6 = (r6 + r8) * C81;
+ r2 = (s6 - s8) * C81;
+ s6 = (s6 + s8) * C81;
+ t1 = r5 - r1;
+ r5 = r5 + r1;
+ r8 = r7 - r6;
+ r7 = r7 + r6;
+ t2 = s5 - r2;
+ s5 = s5 + r2;
+ s8 = s7 - s6;
+ s7 = s7 + s6;
+ pSrc[2 * i2] = r5 + s7;
+ pSrc[2 * i8] = r5 - s7;
+ pSrc[2 * i6] = t1 + s8;
+ pSrc[2 * i4] = t1 - s8;
+ pSrc[2 * i2 + 1] = s5 - r7;
+ pSrc[2 * i8 + 1] = s5 + r7;
+ pSrc[2 * i6 + 1] = t2 - r8;
+ pSrc[2 * i4 + 1] = t2 + r8;
+
+ i1 += n1;
+ } while (i1 < fftLen);
+
+ if (n2 < 8)
+ break;
+
+ ia1 = 0;
+ j = 1;
+
+ do
+ {
+ /* index calculation for the coefficients */
+ id = ia1 + twidCoefModifier;
+ ia1 = id;
+ ia2 = ia1 + id;
+ ia3 = ia2 + id;
+ ia4 = ia3 + id;
+ ia5 = ia4 + id;
+ ia6 = ia5 + id;
+ ia7 = ia6 + id;
+
+ co2 = pCoef[2 * ia1];
+ co3 = pCoef[2 * ia2];
+ co4 = pCoef[2 * ia3];
+ co5 = pCoef[2 * ia4];
+ co6 = pCoef[2 * ia5];
+ co7 = pCoef[2 * ia6];
+ co8 = pCoef[2 * ia7];
+ si2 = pCoef[2 * ia1 + 1];
+ si3 = pCoef[2 * ia2 + 1];
+ si4 = pCoef[2 * ia3 + 1];
+ si5 = pCoef[2 * ia4 + 1];
+ si6 = pCoef[2 * ia5 + 1];
+ si7 = pCoef[2 * ia6 + 1];
+ si8 = pCoef[2 * ia7 + 1];
+
+ i1 = j;
+
+ do
+ {
+ /* index calculation for the input */
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+ i4 = i3 + n2;
+ i5 = i4 + n2;
+ i6 = i5 + n2;
+ i7 = i6 + n2;
+ i8 = i7 + n2;
+ r1 = pSrc[2 * i1] + pSrc[2 * i5];
+ r5 = pSrc[2 * i1] - pSrc[2 * i5];
+ r2 = pSrc[2 * i2] + pSrc[2 * i6];
+ r6 = pSrc[2 * i2] - pSrc[2 * i6];
+ r3 = pSrc[2 * i3] + pSrc[2 * i7];
+ r7 = pSrc[2 * i3] - pSrc[2 * i7];
+ r4 = pSrc[2 * i4] + pSrc[2 * i8];
+ r8 = pSrc[2 * i4] - pSrc[2 * i8];
+ t1 = r1 - r3;
+ r1 = r1 + r3;
+ r3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1] = r1 + r2;
+ r2 = r1 - r2;
+ s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+ s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+ s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+ s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+ s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+ s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+ s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+ s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+ t2 = s1 - s3;
+ s1 = s1 + s3;
+ s3 = s2 - s4;
+ s2 = s2 + s4;
+ r1 = t1 + s3;
+ t1 = t1 - s3;
+ pSrc[2 * i1 + 1] = s1 + s2;
+ s2 = s1 - s2;
+ s1 = t2 - r3;
+ t2 = t2 + r3;
+ p1 = co5 * r2;
+ p2 = si5 * s2;
+ p3 = co5 * s2;
+ p4 = si5 * r2;
+ pSrc[2 * i5] = p1 + p2;
+ pSrc[2 * i5 + 1] = p3 - p4;
+ p1 = co3 * r1;
+ p2 = si3 * s1;
+ p3 = co3 * s1;
+ p4 = si3 * r1;
+ pSrc[2 * i3] = p1 + p2;
+ pSrc[2 * i3 + 1] = p3 - p4;
+ p1 = co7 * t1;
+ p2 = si7 * t2;
+ p3 = co7 * t2;
+ p4 = si7 * t1;
+ pSrc[2 * i7] = p1 + p2;
+ pSrc[2 * i7 + 1] = p3 - p4;
+ r1 = (r6 - r8) * C81;
+ r6 = (r6 + r8) * C81;
+ s1 = (s6 - s8) * C81;
+ s6 = (s6 + s8) * C81;
+ t1 = r5 - r1;
+ r5 = r5 + r1;
+ r8 = r7 - r6;
+ r7 = r7 + r6;
+ t2 = s5 - s1;
+ s5 = s5 + s1;
+ s8 = s7 - s6;
+ s7 = s7 + s6;
+ r1 = r5 + s7;
+ r5 = r5 - s7;
+ r6 = t1 + s8;
+ t1 = t1 - s8;
+ s1 = s5 - r7;
+ s5 = s5 + r7;
+ s6 = t2 - r8;
+ t2 = t2 + r8;
+ p1 = co2 * r1;
+ p2 = si2 * s1;
+ p3 = co2 * s1;
+ p4 = si2 * r1;
+ pSrc[2 * i2] = p1 + p2;
+ pSrc[2 * i2 + 1] = p3 - p4;
+ p1 = co8 * r5;
+ p2 = si8 * s5;
+ p3 = co8 * s5;
+ p4 = si8 * r5;
+ pSrc[2 * i8] = p1 + p2;
+ pSrc[2 * i8 + 1] = p3 - p4;
+ p1 = co6 * r6;
+ p2 = si6 * s6;
+ p3 = co6 * s6;
+ p4 = si6 * r6;
+ pSrc[2 * i6] = p1 + p2;
+ pSrc[2 * i6 + 1] = p3 - p4;
+ p1 = co4 * t1;
+ p2 = si4 * t2;
+ p3 = co4 * t2;
+ p4 = si4 * t1;
+ pSrc[2 * i4] = p1 + p2;
+ pSrc[2 * i4 + 1] = p3 - p4;
+
+ i1 += n1;
+ } while (i1 < fftLen);
+
+ j++;
+ } while (j < n2);
+
+ twidCoefModifier <<= 3;
+ } while (n2 > 7);
+}
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c
new file mode 100644
index 000000000..87455dc0f
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,448 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dct4_f32.c
+ * Description: Processing function of DCT4 & IDCT4 F32
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/**
+ @ingroup groupTransforms
+ */
+
+/**
+ @defgroup DCT4_IDCT4 DCT Type IV Functions
+
+ Representation of signals by minimum number of values is important for storage and transmission.
+ The possibility of large discontinuity between the beginning and end of a period of a signal
+ in DFT can be avoided by extending the signal so that it is even-symmetric.
+ Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the
+ spectrum and is very widely used in signal and image coding applications.
+ The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.
+ DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.
+
+ DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.
+ Reordering of the input data makes the computation of DCT just a problem of
+ computing the DFT of a real signal with a few additional operations.
+ This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.
+
+ DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.
+ DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.
+ DCT2 implementation can be described in the following steps:
+ - Re-ordering input
+ - Calculating Real FFT
+ - Multiplication of weights and Real FFT output and getting real part from the product.
+
+ This process is explained by the block diagram below:
+ \image html DCT4.gif "Discrete Cosine Transform - type-IV"
+
+ @par Algorithm
+ The N-point type-IV DCT is defined as a real, linear transformation by the formula:
+ \image html DCT4Equation.gif
+ where k = 0, 1, 2, ..., N-1
+ @par
+ Its inverse is defined as follows:
+ \image html IDCT4Equation.gif
+ where n = 0, 1, 2, ..., N-1
+ @par
+ The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).
+ The symmetry of the transform matrix indicates that the fast algorithms for the forward
+ and inverse transform computation are identical.
+ Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.
+
+ @par Lengths supported by the transform:
+ As DCT4 internally uses Real FFT, it supports all the lengths 128, 512, 2048 and 8192.
+ The library provides separate functions for Q15, Q31, and floating-point data types.
+
+ @par Instance Structure
+ The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.
+ A separate instance structure must be defined for each transform.
+ There are separate instance structure declarations for each of the 3 supported data types.
+
+ @par Initialization Functions
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Initializes Real FFT as its process function is used internally in DCT4, by calling \ref arm_rfft_init_f32().
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ To place an instance structure into a const data section, the instance structure must be manually initialized.
+ Manually initialize the instance structure as follows:
+
+ arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+
+ where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;
+ \c normalize is normalizing factor used and is equal to sqrt(2/N);
+ \c pTwiddle points to the twiddle factor table;
+ \c pCosFactor points to the cosFactor table;
+ \c pRfft points to the real FFT instance;
+ \c pCfft points to the complex FFT instance;
+ The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()
+ and arm_rfft_f32() respectively for details regarding static initialization.
+
+ @par Fixed-Point Behavior
+ Care must be taken when using the fixed-point versions of the DCT4 transform functions.
+ In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ @addtogroup DCT4_IDCT4
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point DCT4/IDCT4.
+ @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure
+ @param[in] pState points to state buffer
+ @param[in,out] pInlineBuffer points to the in-place input and output buffer
+ @return none
+ */
+
+void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer)
+{
+ const float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ const float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ float32_t in; /* Temporary variable */
+ uint32_t i; /* Loop counter */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+ arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1U);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+
+#if defined (ARM_MATH_LOOPUNROLL)
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = S->Nby2 >> 2U;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement loop counter */
+ i--;
+ } while (i > 0U);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = S->N >> 2U;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while (i > 0U);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_f32 (S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = (S->N - 1U) >> 2U;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ * (float32_t) 0.5;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while (i > 0U);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = (S->N - 1U) % 0x4U;
+
+ while (i > 0U)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = S->N >> 2U;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ /* Decrement the loop counter */
+ i--;
+ } while (i > 0U);
+
+
+#else
+
+ /* Initializing the loop counter to N/2 */
+ i = S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while (i > 0U);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while (i > 0U);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_f32 (S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_f32 (pState, weights, pState, S->N);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ * (float32_t) 0.5;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* Initializing the loop counter */
+ i = (S->N - 1U);
+
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement loop counter */
+ i--;
+ } while (i > 0U);
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing loop counter */
+ i = S->N;
+
+ /* pbuff initialized to the pInlineBuffer (now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ /* Decrement loop counter */
+ i--;
+ } while (i > 0U);
+
+#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
+
+}
+
+/**
+ @} end of DCT4_IDCT4 group
+ */
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
index 000000000..3fd70e926
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_dct4_init_f32.c
+ * Description: Initialization function of DCT-4 & IDCT4 F32
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ @ingroup DCT4_IDCT4
+ */
+
+
+/**
+ @addtogroup DCT4_IDCT4
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point DCT4/IDCT4.
+ @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure
+ @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure
+ @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure
+ @param[in] N length of the DCT4
+ @param[in] Nby2 half of the length of the DCT4
+ @param[in] normalize normalizing factor.
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : N is not a supported transform length
+
+ @par Normalizing factor
+ The normalizing factor is sqrt(2/N), which depends on the size of transform N.
+ Floating-point normalizing factors are mentioned in the table below for different DCT sizes:
+
+ \image html dct4NormalizingF32Table.gif
+ */
+
+arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize)
+{
+ /* Initialize the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
+ /* Initialize the table modifier values */
+ case 8192U:
+ S->pTwiddle = Weights_8192;
+ S->pCosFactor = cos_factors_8192;
+ break;
+ #endif
+
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
+ case 2048U:
+ S->pTwiddle = Weights_2048;
+ S->pCosFactor = cos_factors_2048;
+ break;
+ #endif
+
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
+ case 512U:
+ S->pTwiddle = Weights_512;
+ S->pCosFactor = cos_factors_512;
+ break;
+ #endif
+
+ #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
+ case 128U:
+ S->pTwiddle = Weights_128;
+ S->pCosFactor = cos_factors_128;
+ break;
+ #endif
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT Function */
+ arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0U, 1U);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ @} end of DCT4_IDCT4 group
+ */
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c
new file mode 100644
index 000000000..b5d0a662b
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,309 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_rfft_f32.c
+ * Description: RFFT & RIFFT Floating point process function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+/* ----------------------------------------------------------------------
+ * Internal functions prototypes
+ * -------------------------------------------------------------------- */
+
+extern void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ const uint16_t * pBitRevTab);
+
+void arm_split_rfft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ const float32_t * pATable,
+ const float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier);
+
+void arm_split_rifft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ const float32_t * pATable,
+ const float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier);
+
+/**
+ @ingroup groupTransforms
+ */
+
+/**
+ @addtogroup RealFFT
+ @{
+ */
+
+/**
+ @brief Processing function for the floating-point RFFT/RIFFT.
+ @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed in the future.
+ @param[in] S points to an instance of the floating-point RFFT/RIFFT structure
+ @param[in] pSrc points to the input buffer
+ @param[out] pDst points to the output buffer
+ @return none
+ */
+
+void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst)
+{
+ const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+ /* Calculation of Real IFFT of input */
+ if (S->ifftFlagR == 1U)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+ /* Complex radix-4 IFFT process */
+ arm_radix4_butterfly_inverse_f32 (pDst, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier, S_CFFT->onebyfftLen);
+
+ /* Bit reversal process */
+ if (S->bitReverseFlagR == 1U)
+ {
+ arm_bitreversal_f32 (pDst, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+
+ /* Complex radix-4 FFT process */
+ arm_radix4_butterfly_f32 (pSrc, S_CFFT->fftLen, S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if (S->bitReverseFlagR == 1U)
+ {
+ arm_bitreversal_f32 (pSrc, S_CFFT->fftLen, S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+
+ /* Real FFT core process */
+ arm_split_rfft_f32 (pSrc, S->fftLenBy2, S->pTwiddleAReal, S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+
+}
+
+/**
+ @} end of RealFFT group
+ */
+
+/**
+ @brief Core Real FFT process
+ @param[in] pSrc points to input buffer
+ @param[in] fftLen length of FFT
+ @param[in] pATable points to twiddle Coef A buffer
+ @param[in] pBTable points to twiddle Coef B buffer
+ @param[out] pDst points to output buffer
+ @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table
+ @return none
+ */
+
+void arm_split_rfft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ const float32_t * pATable,
+ const float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ float32_t outR, outI; /* Temporary variables for output */
+ const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4U * fftLen) - 1U]; /* temp pointers for output buffer */
+ float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2U * fftLen) - 1U]; /* temp pointers for input buffer */
+
+ /* Init coefficient pointers */
+ pCoefA = &pATable[modifier * 2];
+ pCoefB = &pBTable[modifier * 2];
+
+ i = fftLen - 1U;
+
+ while (i > 0U)
+ {
+ /*
+ outR = ( pSrc[2 * i] * pATable[2 * i]
+ - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i]
+ + pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = ( pIn[2 * i + 1] * pATable[2 * i]
+ + pIn[2 * i] * pATable[2 * i + 1]
+ + pIn[2 * n - 2 * i] * pBTable[2 * i + 1]
+ - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+ /* read pATable[2 * i] */
+ CoefA1 = *pCoefA++;
+ /* pATable[2 * i + 1] */
+ CoefA2 = *pCoefA;
+
+ /* pSrc[2 * i] * pATable[2 * i] */
+ outR = *pSrc1 * CoefA1;
+ /* pSrc[2 * i] * CoefA2 */
+ outI = *pSrc1++ * CoefA2;
+
+ /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+ outR -= (*pSrc1 + *pSrc2) * CoefA2;
+ /* pSrc[2 * i + 1] * CoefA1 */
+ outI += *pSrc1++ * CoefA1;
+
+ CoefB1 = *pCoefB;
+
+ /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+ outI -= *pSrc2-- * CoefB1;
+ /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+ outI -= *pSrc2 * CoefA2;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+ outR += *pSrc2-- * CoefB1;
+
+ /* write output */
+ *pDst1++ = outR;
+ *pDst1++ = outI;
+
+ /* write complex conjugate output */
+ *pDst2-- = -outI;
+ *pDst2-- = outR;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2U);
+ pCoefA = pCoefA + ((modifier * 2U) - 1U);
+
+ i--;
+
+ }
+
+ pDst[2U * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2U * fftLen) + 1U] = 0.0f;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0.0f;
+
+}
+
+
+/**
+ @brief Core Real IFFT process
+ @param[in] pSrc points to input buffer
+ @param[in] fftLen length of FFT
+ @param[in] pATable points to twiddle Coef A buffer
+ @param[in] pBTable points to twiddle Coef B buffer
+ @param[out] pDst points to output buffer
+ @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table
+ @return none
+ */
+
+void arm_split_rifft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ const float32_t * pATable,
+ const float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier)
+{
+ float32_t outR, outI; /* Temporary variables for output */
+ const float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2U * fftLen) + 1U];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ while (fftLen > 0U)
+ {
+ /*
+ outR = ( pIn[2 * i] * pATable[2 * i]
+ + pIn[2 * i + 1] * pATable[2 * i + 1]
+ + pIn[2 * n - 2 * i] * pBTable[2 * i]
+ - pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = ( pIn[2 * i + 1] * pATable[2 * i]
+ - pIn[2 * i] * pATable[2 * i + 1]
+ - pIn[2 * n - 2 * i] * pBTable[2 * i + 1]
+ - pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pSrc[2 * i] * CoefA1 */
+ outR = *pSrc1 * CoefA1;
+
+ /* - pSrc[2 * i] * CoefA2 */
+ outI = -(*pSrc1++) * CoefA2;
+
+ /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+ outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+ /* pSrc[2 * i + 1] * CoefA1 */
+ outI += (*pSrc1++) * CoefA1;
+
+ CoefB1 = *pCoefB;
+
+ /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+ outI -= *pSrc2-- * CoefB1;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+ outR += *pSrc2 * CoefB1;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+ outI += *pSrc2-- * CoefA2;
+
+ /* write output */
+ *pDst++ = outR;
+ *pDst++ = outI;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2);
+ pCoefA = pCoefA + (modifier * 2 - 1);
+
+ /* Decrement loop count */
+ fftLen--;
+ }
+
+}
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c
new file mode 100644
index 000000000..7a1af1461
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c
@@ -0,0 +1,320 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_rfft_f32.c
+ * Description: RFFT & RIFFT Floating point process function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+
+void stage_rfft_f32(
+ const arm_rfft_fast_instance_f32 * S,
+ float32_t * p,
+ float32_t * pOut)
+{
+ uint32_t k; /* Loop Counter */
+ float32_t twR, twI; /* RFFT Twiddle coefficients */
+ const float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
+ float32_t *pA = p; /* increasing pointer */
+ float32_t *pB = p; /* decreasing pointer */
+ float32_t xAR, xAI, xBR, xBI; /* temporary variables */
+ float32_t t1a, t1b; /* temporary variables */
+ float32_t p0, p1, p2, p3; /* temporary variables */
+
+
+ k = (S->Sint).fftLen - 1;
+
+ /* Pack first and last sample of the frequency domain together */
+
+ xBR = pB[0];
+ xBI = pB[1];
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++ ;
+ twI = *pCoeff++ ;
+
+ // U1 = XA(1) + XB(1); % It is real
+ t1a = xBR + xAR ;
+
+ // U2 = XB(1) - XA(1); % It is imaginary
+ t1b = xBI + xAI ;
+
+ // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+ // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+ *pOut++ = 0.5f * ( t1a + t1b );
+ *pOut++ = 0.5f * ( t1a - t1b );
+
+ // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) ));
+ pB = p + 2*k;
+ pA += 2;
+
+ do
+ {
+ /*
+ function X = my_split_rfft(X, ifftFlag)
+ % X is a series of real numbers
+ L = length(X);
+ XC = X(1:2:end) +i*X(2:2:end);
+ XA = fft(XC);
+ XB = conj(XA([1 end:-1:2]));
+ TW = i*exp(-2*pi*i*[0:L/2-1]/L).';
+ for l = 2:L/2
+ XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));
+ end
+ XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));
+ X = XA;
+ */
+
+ xBI = pB[1];
+ xBR = pB[0];
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++;
+ twI = *pCoeff++;
+
+ t1a = xBR - xAR ;
+ t1b = xBI + xAI ;
+
+ // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+ // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+ p0 = twR * t1a;
+ p1 = twI * t1a;
+ p2 = twR * t1b;
+ p3 = twI * t1b;
+
+ *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR
+ *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI
+
+ pA += 2;
+ pB -= 2;
+ k--;
+ } while (k > 0U);
+}
+
+/* Prepares data for inverse cfft */
+void merge_rfft_f32(
+ const arm_rfft_fast_instance_f32 * S,
+ float32_t * p,
+ float32_t * pOut)
+{
+ uint32_t k; /* Loop Counter */
+ float32_t twR, twI; /* RFFT Twiddle coefficients */
+ const float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
+ float32_t *pA = p; /* increasing pointer */
+ float32_t *pB = p; /* decreasing pointer */
+ float32_t xAR, xAI, xBR, xBI; /* temporary variables */
+ float32_t t1a, t1b, r, s, t, u; /* temporary variables */
+
+ k = (S->Sint).fftLen - 1;
+
+ xAR = pA[0];
+ xAI = pA[1];
+
+ pCoeff += 2 ;
+
+ *pOut++ = 0.5f * ( xAR + xAI );
+ *pOut++ = 0.5f * ( xAR - xAI );
+
+ pB = p + 2*k ;
+ pA += 2 ;
+
+ while (k > 0U)
+ {
+ /* G is half of the frequency complex spectrum */
+ //for k = 2:N
+ // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));
+ xBI = pB[1] ;
+ xBR = pB[0] ;
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++;
+ twI = *pCoeff++;
+
+ t1a = xAR - xBR ;
+ t1b = xAI + xBI ;
+
+ r = twR * t1a;
+ s = twI * t1b;
+ t = twI * t1a;
+ u = twR * t1b;
+
+ // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);
+ // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);
+ *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR
+ *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI
+
+ pA += 2;
+ pB -= 2;
+ k--;
+ }
+
+}
+
+/**
+ @ingroup groupTransforms
+*/
+
+/**
+ @defgroup RealFFT Real FFT Functions
+
+ @par
+ The CMSIS DSP library includes specialized algorithms for computing the
+ FFT of real data sequences. The FFT is defined over complex data but
+ in many applications the input is real. Real FFT algorithms take advantage
+ of the symmetry properties of the FFT and have a speed advantage over complex
+ algorithms of the same length.
+ @par
+ The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.
+ @par
+ The real length N forward FFT of a sequence is computed using the steps shown below.
+ @par
+ \image html RFFT.gif "Real Fast Fourier Transform"
+ @par
+ The real sequence is initially treated as if it were complex to perform a CFFT.
+ Later, a processing stage reshapes the data to obtain half of the frequency spectrum
+ in complex format. Except the first complex number that contains the two real numbers
+ X[0] and X[N/2] all the data is complex. In other words, the first complex sample
+ contains two real values packed.
+ @par
+ The input for the inverse RFFT should keep the same format as the output of the
+ forward RFFT. A first processing stage pre-process the data to later perform an
+ inverse CFFT.
+ @par
+ \image html RIFFT.gif "Real Inverse Fast Fourier Transform"
+ @par
+ The algorithms for floating-point, Q15, and Q31 data are slightly different
+ and we describe each algorithm in turn.
+ @par Floating-point
+ The main functions are \ref arm_rfft_fast_f32() and \ref arm_rfft_fast_init_f32().
+ The older functions \ref arm_rfft_f32() and \ref arm_rfft_init_f32() have been deprecated
+ but are still documented.
+ @par
+ The FFT of a real N-point sequence has even symmetry in the frequency domain.
+ The second half of the data equals the conjugate of the first half flipped in frequency.
+ Looking at the data, we see that we can uniquely represent the FFT using only N/2 complex numbers.
+ These are packed into the output array in alternating real and imaginary components:
+ @par
+ X = { real[0], imag[0], real[1], imag[1], real[2], imag[2] ...
+ real[(N/2)-1], imag[(N/2)-1 }
+ @par
+ It happens that the first complex number (real[0], imag[0]) is actually
+ all real. real[0] represents the DC offset, and imag[0] should be 0.
+ (real[1], imag[1]) is the fundamental frequency, (real[2], imag[2]) is
+ the first harmonic and so on.
+ @par
+ The real FFT functions pack the frequency domain data in this fashion.
+ The forward transform outputs the data in this form and the inverse
+ transform expects input data in this form. The function always performs
+ the needed bitreversal so that the input and output data is always in
+ normal order. The functions support lengths of [32, 64, 128, ..., 4096]
+ samples.
+ @par Q15 and Q31
+ The real algorithms are defined in a similar manner and utilize N/2 complex
+ transforms behind the scenes.
+ @par
+ The complex transforms used internally include scaling to prevent fixed-point
+ overflows. The overall scaling equals 1/(fftLen/2).
+ @par
+ A separate instance structure must be defined for each transform used but
+ twiddle factor and bit reversal tables can be reused.
+ @par
+ There is also an associated initialization function for each data type.
+ The initialization function performs the following operations:
+ - Sets the values of the internal structure fields.
+ - Initializes twiddle factor table and bit reversal table pointers.
+ - Initializes the internal complex FFT data structure.
+ @par
+ Use of the initialization function is optional.
+ However, if the initialization function is used, then the instance structure
+ cannot be placed into a const data section. To place an instance structure
+ into a const data section, the instance structure should be manually
+ initialized as follows:
+
+ arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+
+ where fftLenReal is the length of the real transform;
+ fftLenBy2 length of the internal complex transform.
+ ifftFlagR Selects forward (=0) or inverse (=1) transform.
+ bitReverseFlagR Selects bit reversed output (=0) or normal order
+ output (=1).
+ twidCoefRModifier stride modifier for the twiddle factor table.
+ The value is based on the FFT length;
+ pTwiddleARealpoints to the A array of twiddle coefficients;
+ pTwiddleBRealpoints to the B array of twiddle coefficients;
+ pCfft points to the CFFT Instance structure. The CFFT structure
+ must also be initialized. Refer to arm_cfft_radix4_f32() for details regarding
+ static initialization of the complex FFT instance structure.
+ */
+
+/**
+ @addtogroup RealFFT
+ @{
+*/
+
+/**
+ @brief Processing function for the floating-point real FFT.
+ @param[in] S points to an arm_rfft_fast_instance_f32 structure
+ @param[in] p points to input buffer
+ @param[in] pOut points to output buffer
+ @param[in] ifftFlag
+ - value = 0: RFFT
+ - value = 1: RIFFT
+ @return none
+*/
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p,
+ float32_t * pOut,
+ uint8_t ifftFlag)
+{
+ arm_cfft_instance_f32 * Sint = &(S->Sint);
+ Sint->fftLen = S->fftLenRFFT / 2;
+
+ /* Calculation of Real FFT */
+ if (ifftFlag)
+ {
+ /* Real FFT compression */
+ merge_rfft_f32(S, p, pOut);
+
+ /* Complex radix-4 IFFT process */
+ arm_cfft_f32( Sint, pOut, ifftFlag, 1);
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+ arm_cfft_f32( Sint, p, ifftFlag, 1);
+
+ /* Real FFT extraction */
+ stage_rfft_f32(S, p, pOut);
+ }
+}
+
+/**
+* @} end of RealFFT group
+*/
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c
new file mode 100644
index 000000000..58fbfdba7
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c
@@ -0,0 +1,344 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_cfft_init_f32.c
+ * Description: Split Radix Decimation in Frequency CFFT Floating point processing function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ @ingroup groupTransforms
+ */
+
+/**
+ @addtogroup RealFFT
+ @{
+ */
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32))
+
+/**
+ @brief Initialization function for the 32pt floating-point real FFT.
+ @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected
+ */
+
+arm_status arm_rfft_32_fast_init_f32( arm_rfft_fast_instance_f32 * S ) {
+
+ arm_cfft_instance_f32 * Sint;
+
+ if( !S ) return ARM_MATH_ARGUMENT_ERROR;
+
+ Sint = &(S->Sint);
+ Sint->fftLen = 16U;
+ S->fftLenRFFT = 32U;
+
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_16_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_16;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_32;
+
+ return ARM_MATH_SUCCESS;
+}
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64))
+
+/**
+ @brief Initialization function for the 64pt floating-point real FFT.
+ @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected
+ */
+
+arm_status arm_rfft_64_fast_init_f32( arm_rfft_fast_instance_f32 * S ) {
+
+ arm_cfft_instance_f32 * Sint;
+
+ if( !S ) return ARM_MATH_ARGUMENT_ERROR;
+
+ Sint = &(S->Sint);
+ Sint->fftLen = 32U;
+ S->fftLenRFFT = 64U;
+
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_32_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_32;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_64;
+
+ return ARM_MATH_SUCCESS;
+}
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128))
+
+/**
+ @brief Initialization function for the 128pt floating-point real FFT.
+ @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected
+ */
+
+arm_status arm_rfft_128_fast_init_f32( arm_rfft_fast_instance_f32 * S ) {
+
+ arm_cfft_instance_f32 * Sint;
+
+ if( !S ) return ARM_MATH_ARGUMENT_ERROR;
+
+ Sint = &(S->Sint);
+ Sint->fftLen = 64U;
+ S->fftLenRFFT = 128U;
+
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_64_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_64;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_128;
+
+ return ARM_MATH_SUCCESS;
+}
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256))
+
+/**
+ @brief Initialization function for the 256pt floating-point real FFT.
+ @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected
+*/
+
+arm_status arm_rfft_256_fast_init_f32( arm_rfft_fast_instance_f32 * S ) {
+
+ arm_cfft_instance_f32 * Sint;
+
+ if( !S ) return ARM_MATH_ARGUMENT_ERROR;
+
+ Sint = &(S->Sint);
+ Sint->fftLen = 128U;
+ S->fftLenRFFT = 256U;
+
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_128;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_256;
+
+ return ARM_MATH_SUCCESS;
+}
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512))
+
+/**
+ @brief Initialization function for the 512pt floating-point real FFT.
+ @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected
+ */
+
+arm_status arm_rfft_512_fast_init_f32( arm_rfft_fast_instance_f32 * S ) {
+
+ arm_cfft_instance_f32 * Sint;
+
+ if( !S ) return ARM_MATH_ARGUMENT_ERROR;
+
+ Sint = &(S->Sint);
+ Sint->fftLen = 256U;
+ S->fftLenRFFT = 512U;
+
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_256;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_512;
+
+ return ARM_MATH_SUCCESS;
+}
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024))
+/**
+ @brief Initialization function for the 1024pt floating-point real FFT.
+ @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected
+ */
+
+arm_status arm_rfft_1024_fast_init_f32( arm_rfft_fast_instance_f32 * S ) {
+
+ arm_cfft_instance_f32 * Sint;
+
+ if( !S ) return ARM_MATH_ARGUMENT_ERROR;
+
+ Sint = &(S->Sint);
+ Sint->fftLen = 512U;
+ S->fftLenRFFT = 1024U;
+
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_512;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_1024;
+
+ return ARM_MATH_SUCCESS;
+}
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048))
+/**
+ @brief Initialization function for the 2048pt floating-point real FFT.
+ @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected
+ */
+arm_status arm_rfft_2048_fast_init_f32( arm_rfft_fast_instance_f32 * S ) {
+
+ arm_cfft_instance_f32 * Sint;
+
+ if( !S ) return ARM_MATH_ARGUMENT_ERROR;
+
+ Sint = &(S->Sint);
+ Sint->fftLen = 1024U;
+ S->fftLenRFFT = 2048U;
+
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_1024_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_1024;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_2048;
+
+ return ARM_MATH_SUCCESS;
+}
+#endif
+
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096))
+/**
+* @brief Initialization function for the 4096pt floating-point real FFT.
+* @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : an error is detected
+ */
+
+arm_status arm_rfft_4096_fast_init_f32( arm_rfft_fast_instance_f32 * S ) {
+
+ arm_cfft_instance_f32 * Sint;
+
+ if( !S ) return ARM_MATH_ARGUMENT_ERROR;
+
+ Sint = &(S->Sint);
+ Sint->fftLen = 2048U;
+ S->fftLenRFFT = 4096U;
+
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_2048_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;
+ Sint->pTwiddle = (float32_t *) twiddleCoef_2048;
+ S->pTwiddleRFFT = (float32_t *) twiddleCoef_rfft_4096;
+
+ return ARM_MATH_SUCCESS;
+}
+#endif
+
+/**
+ @brief Initialization function for the floating-point real FFT.
+ @param[in,out] S points to an arm_rfft_fast_instance_f32 structure
+ @param[in] fftLen length of the Real Sequence
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : fftLen is not a supported length
+
+ @par Description
+ The parameter fftLen specifies the length of RFFT/CIFFT process.
+ Supported FFT Lengths are 32, 64, 128, 256, 512, 1024, 2048, 4096.
+ @par
+ This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+ */
+
+arm_status arm_rfft_fast_init_f32(
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen)
+{
+ typedef arm_status(*fft_init_ptr)( arm_rfft_fast_instance_f32 *);
+ fft_init_ptr fptr = 0x0;
+
+ switch (fftLen)
+ {
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048) && defined(ARM_TABLE_TWIDDLECOEF_F32_2048) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096))
+ case 4096U:
+ fptr = arm_rfft_4096_fast_init_f32;
+ break;
+#endif
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024) && defined(ARM_TABLE_TWIDDLECOEF_F32_1024) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048))
+ case 2048U:
+ fptr = arm_rfft_2048_fast_init_f32;
+ break;
+#endif
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_BITREVIDX_FLT_512) && defined(ARM_TABLE_TWIDDLECOEF_F32_512) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024))
+ case 1024U:
+ fptr = arm_rfft_1024_fast_init_f32;
+ break;
+#endif
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_BITREVIDX_FLT_256) && defined(ARM_TABLE_TWIDDLECOEF_F32_256) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512))
+ case 512U:
+ fptr = arm_rfft_512_fast_init_f32;
+ break;
+#endif
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_BITREVIDX_FLT_128) && defined(ARM_TABLE_TWIDDLECOEF_F32_128) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256))
+ case 256U:
+ fptr = arm_rfft_256_fast_init_f32;
+ break;
+#endif
+#if (defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_BITREVIDX_FLT_64) && defined(ARM_TABLE_TWIDDLECOEF_F32_64) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128))
+ case 128U:
+ fptr = arm_rfft_128_fast_init_f32;
+ break;
+#endif
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_BITREVIDX_FLT_32) && defined(ARM_TABLE_TWIDDLECOEF_F32_32) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64))
+ case 64U:
+ fptr = arm_rfft_64_fast_init_f32;
+ break;
+#endif
+#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_BITREVIDX_FLT_16) && defined(ARM_TABLE_TWIDDLECOEF_F32_16) && defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32))
+ case 32U:
+ fptr = arm_rfft_32_fast_init_f32;
+ break;
+#endif
+ default:
+ return ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ if( ! fptr ) return ARM_MATH_ARGUMENT_ERROR;
+ return fptr( S );
+
+}
+
+/**
+ @} end of RealFFT group
+ */
diff --git a/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c b/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
index 000000000..141f8b62c
--- /dev/null
+++ b/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+ * Project: CMSIS DSP Library
+ * Title: arm_rfft_init_f32.c
+ * Description: RFFT & RIFFT Floating point initialisation function
+ *
+ * $Date: 18. March 2019
+ * $Revision: V1.6.0
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**
+ @addtogroup RealFFT
+ @{
+ */
+
+/**
+ @brief Initialization function for the floating-point RFFT/RIFFT.
+ @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed in the future.
+ @param[in,out] S points to an instance of the floating-point RFFT/RIFFT structure
+ @param[in,out] S_CFFT points to an instance of the floating-point CFFT/CIFFT structure
+ @param[in] fftLenReal length of the FFT.
+ @param[in] ifftFlagR flag that selects transform direction
+ - value = 0: forward transform
+ - value = 1: inverse transform
+ @param[in] bitReverseFlag flag that enables / disables bit reversal of output
+ - value = 0: disables bit reversal of output
+ - value = 1: enables bit reversal of output
+ @return execution status
+ - \ref ARM_MATH_SUCCESS : Operation successful
+ - \ref ARM_MATH_ARGUMENT_ERROR : fftLenReal is not a supported length
+
+ @par Description
+ The parameter fftLenRealspecifies length of RFFT/RIFFT Process.
+ Supported FFT Lengths are 128, 512, 2048.
+ @par
+ The parameter ifftFlagR controls whether a forward or inverse transform is computed.
+ Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+ @par
+ The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.
+ Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+ @par
+ This function also initializes Twiddle factor table.
+ */
+
+arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Complex FFT length */
+ S->fftLenBy2 = (uint16_t) fftLenReal / 2U;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (float32_t *) realCoefA;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (float32_t *) realCoefB;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ /* Init table modifier value */
+ case 8192U:
+ S->twidCoefRModifier = 1U;
+ break;
+ case 2048U:
+ S->twidCoefRModifier = 4U;
+ break;
+ case 512U:
+ S->twidCoefRModifier = 16U;
+ break;
+ case 128U:
+ S->twidCoefRModifier = 64U;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* Init Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ if (S->ifftFlagR)
+ {
+ /* Initializes the CIFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1U, 0U);
+ }
+ else
+ {
+ /* Initializes the CFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0U, 0U);
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+
+}
+
+/**
+ @} end of RealFFT group
+ */
diff --git a/LA_OPT_NXP_Software_License.txt b/LA_OPT_NXP_Software_License.txt
index e42834d37..d52d4e4cf 100644
--- a/LA_OPT_NXP_Software_License.txt
+++ b/LA_OPT_NXP_Software_License.txt
@@ -1,2 +1,2 @@
-LA_OPT_NXP_Software_License v17 October 2020Â
IMPORTANT.  Read the following NXP Software License Agreement ("Agreement") completely. By selecting the "I Accept" button at the end of this page, or by downloading, installing, or using the Licensed Software, you indicate that you accept the terms of the Agreement and you acknowledge that you have the authority, for yourself or on behalf of your company, to bind your company to these terms. You may then download or install the file. In the event of a conflict between the terms of this Agreement and any license terms and conditions for NXP's proprietary software embedded anywhere in the Licensed Software file, the terms of this Agreement shall control. If a separate license agreement for the Licensed Software has been signed by you and NXP, then that agreement shall govern your use of the Licensed Software and shall supersede this Agreement.
NXP SOFTWARE LICENSE AGREEMENT
This is a legal agreement between your employer, of which you are an authorized representative, or, if you have no employer, you as an individual ("you" or "Licensee"), and NXP B.V. ("NXP"). It concerns your rights to use the software provided to you in binary or source code form and any accompanying written materials (the "Licensed Software"). The Licensed Software may include any updates or error corrections or documentation relating to the Licensed Software provided to you by NXP under this Agreement. In consideration for NXP allowing you to access the Licensed Software, you are agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download or install the Licensed Software. If you change your mind later, stop using the Licensed Software and delete all copies of the Licensed Software in your possession or control. Any copies of the Licensed Software that you have already distributed, where permitted, and do not destroy will continue to be governed by this Agreement. Your prior use will also continue to be governed by this Agreement.
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1.7Â Â Â Â Â "Third Party Software" means, any software included in the Licensed Software that is not NXP proprietary software, and is not open source software, and to which different license terms may apply.Â
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13.  GOVERNMENT CONTRACT COMPLIANCE
13.1.     If you sell Authorized Systems directly to any government or public entity, including U.S., state, local, foreign or international governments or public entities, or indirectly via a prime contractor or subcontractor of such governments or entities, NXP makes no representations, certifications, or warranties whatsoever about compliance with government or public entity acquisition statutes or regulations, including, without limitation, statutes or regulations that may relate to pricing, quality, origin or content.
13.2.     The Licensed Software has been developed at private expense and is a "Commercial Item" as defined in 48 C.F.R. Section 2.101, consisting of "Commercial Computer Software", and/or "Commercial Computer Software Documentation," as such terms are used in 48 C.F.R. Section 12.212 (or 48 C.F.R. Section 227.7202, as applicable) and may only be licensed to or shared with U.S. Government end users in object code form as part of, or embedded within, Authorized Systems. Any agreement pursuant to which you share the Licensed Software will include a provision that reiterates the limitations of this document and requires all sub-agreements to similarly contain such limitations.Â
14.       CRITICAL APPLICATIONS. In some cases, NXP may promote certain software for use in the development of, or for incorporation into, products or services (a) used in applications requiring fail-safe performance or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (these products and services are referred to as "Critical Applications"). NXP's goal is to educate customers so that they can design their own end-product solutions to meet applicable functional safety standards and requirements. Licensee makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, Licensee assumes all risk related to use of the Licensed Software in Critical Applications and NXP SHALL NOT BE LIABLE FOR ANY SUCH USE IN CRITICAL APPLICATIONS BY LICENSEE. Accordingly, Licensee will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys' fees) that NXP may incur related to Licensee’s incorporation of the Licensed Software in a Critical Application.
15.       CHOICE OF LAW; VENUE. This Agreement will be governed by, construed, and enforced in accordance with the laws of The Netherlands, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Licensed Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the courts of Amsterdam, The Netherlands. The United Nations Convention on Contracts for the International Sale of Goods will not apply to this document.Â
16.       CONFIDENTIAL INFORMATION. Subject to the license grants and restrictions contained herein, you must treat the Licensed Software as confidential information and you agree to retain the Licensed Software in confidence perpetually. You may not disclose any part of the Licensed Software to anyone other than distributees in accordance with Section 2.3 and employees, or subcontractors in accordance with Section 2.5, who have a need to know of the Licensed Software and who have executed written agreements obligating them to protect such Licensed Software to at least the same degree of confidentiality as in this Agreement. You agree to use the same degree of care, but no less than a reasonable degree of care, with the Licensed Software as you do with your own confidential information. You may disclose Licensed Software to the extent required by a court or under operation of law or order provided that you notify NXP of such requirement prior to disclosure, which you only disclose the minimum of the required information, and that you allow NXP the opportunity to object to such court or other legal body requiring such disclosure.
17.       TRADEMARKS. You are not authorized to use any NXP trademarks, brand names, or logos.
18.       ENTIRE AGREEMENT. This Agreement constitutes the entire agreement between you and NXP regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any. This Agreement may only be amended in written form, signed by you and NXP.
19.       SEVERABILITY. If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or NXP of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision.
20.       NO WAIVER. The waiver by NXP of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision.
21.       AUDIT. You will keep full, clear and accurate records with respect to your compliance with the limited license rights granted under this Agreement for three years following expiration or termination of this Agreement. NXP will have the right, either itself or through an independent certified public accountant to examine and audit, at NXP's expense, not more than once a year, and during normal business hours, all such records that may bear upon your compliance with the limited license rights granted above. You must make prompt adjustment to compensate for any errors and/or omissions disclosed by such examination or audit.
22.       NOTICES.            All notices and communications under this Agreement will be made in writing, and will be effective when received at the following addresses:Â
         NXP:      NXP B.V.
                      High Tech Campus 60
                        5656 AG Eindhoven
                        The Netherlands
                   ATTN: Legal Department
Â
You:Â Â Â Â Â Â Â Â Â Â Â Â Â Â The address provided at registration will be used.
23.       RELATIONSHIP OF THE PARTIES.    The parties are independent contractors. Nothing in this Agreement will be construed to create any partnership, joint venture, or similar relationship. Neither party is authorized to bind the other to any obligations with third parties.
24.       SUCCESSION AND ASSIGNMENT.  This Agreement will be binding upon and inure to the benefit of the parties and their permitted successors and assigns. You may not assign this Agreement, or any part of this Agreement, without the prior written approval of NXP, which approval will not be unreasonably withheld or delayed. NXP may assign this Agreement, or any part of this Agreement, in its sole discretion.
25. PRIVACY. By agreeing to this Agreement and/or utilizing the Licensed Software, Licensee consents to use of certain personal information, including but not limited to name, email address, and location, for the purpose of NXP’s internal analysis regarding future software offerings. NXP’s complete Privacy Statement can be found at: https://www.nxp.com/company/our-company/about-nxp/privacy-statement:PRIVACYPRACTICES.
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APPENDIX A
Other License Grants and Restrictions:
The Licensed Software may include some or all of the following software, which is either 1) Third Party Software or 2) NXP proprietary software subject to different terms than those in the Agreement. If the Software Content Register that accompanies the Licensed Software identifies any of the following Third Party Software or specific components of the NXP proprietary software, the following terms apply to the extent they deviate from the terms in the Agreement:
Amazon: Use of the Amazon software constitutes your acceptance of the terms of the Amazon Program Materials License Agreement (including the AVS Component Schedule, if applicable), located at https://developer.amazon.com/support/legal/pml. All Amazon software is hereby designated "Amazon confidential". Amazon is a third-party beneficiary to this Agreement with respect to the Amazon software.
Amphion Semiconductor Ltd.: Distribution of Amphion software must be a part of, or embedded within, Authorized Systems that include an Amphion Video Decoder.
Aquantia Corp.: You may use Aquantia's API binaries solely to flash the API software to an NXP Product which mates with an Aquantia device.
Atheros: Use of Atheros software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Atheros.
ATI (AMD): Distribution of ATI software must be a part of, or embedded within, Authorized Systems that include a ATI graphics processor core.
Broadcom Corporation: Your use of Broadcom Corporation software is restricted to Authorized Systems that incorporate a compatible integrated circuit device manufactured or sold by Broadcom.
Cadence Design Systems: Use of Cadence audio codec software is limited to distribution only of one copy per single NXP Product. The license granted herein to the Cadence Design Systems HiFi aacPlus Audio Decoder software does not include a license to the AAC family of technologies which you or your customer may need to obtain. Configuration tool outputs may only be distributed by licensees of the relevant Cadence SDK and distribution is limited to distribution of one copy embedded in a single NXP Product.
Cirque Corporation: Use of Cirque Corporation technology is limited to evaluation, demonstration, or certification testing only. Permitted distributions must be similarly limited. Further rights, including but not limited to ANY commercial distribution rights, must be obtained directly from Cirque Corporation.
Coding Technologies (Dolby Labs): Use of CTS software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Dolby Laboratories.
CSR: Use of Cambridge Silicon Radio, Inc. ("CSR") software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from CSR.
Crank: Use of Crank Software Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Crank Software Inc.
Cypress Semiconductor Corporation: WWD RTOS source code may only be used in accordance with the Cypress IOT Community License Agreement located at https://community.cypress.com/terms-and-conditions!input.jspa?displayOnly=true.
Embedded Systems Academy GmbH (EmSA): Any use of Micro CANopen Plus is subject to the acceptance of the license conditions described in the LICENSE.INFO file distributed with all example projects and in the documentation and the additional clause described below.
Clause 1: Micro CANopen Plus may not be used for any competitive or comparative purpose, including the publication of any form of run time or compile time metric, without the express permission of EmSA.
Future Technology Devices International Ltd.: Future Technology Devices International software must be used consistent with the terms found here: http://www.ftdichip.com/Drivers/FTDriverLicenceTerms.htm
Global Locate (Broadcom Corporation): Use of Global Locate, Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Global Locate.
Microsoft: Except for Microsoft PlayReady software, if the Licensed Software includes software owned by Microsoft Corporation ("Microsoft"), it is subject to the terms of your license with Microsoft (the "Microsoft Underlying Licensed Software") and as such, NXP grants no license to you, beyond evaluation and demonstration in connection with NXP processors, in the Microsoft Underlying Licensed Software. You must separately obtain rights beyond evaluation and demonstration in connection with the Microsoft Underlying Licensed Software from Microsoft. Microsoft does not provide support services for the components provided to you through this Agreement. If you have any questions or require technical assistance, please contact NXP. Microsoft Corporation is a third party beneficiary to this Agreement with the right to enforce the terms of this Agreement. TO THE MAXIMUM EXTENT PERMITTED BY LAW, MICROSOFT AND ITS AFFILIATES DISCLAIM ANY WARRANTIES FOR THE MICROSOFT UNDERLYING LICENSED SOFTWARE. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NEITHER MICROSOFT NOR ITS AFFILIATES WILL BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY DIRECT, INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, ARISING FROM THE FROM THE USE OF THE MICROSOFT UNDERLYING LICENSED SOFTWARE. With respect to the Microsoft PlayReady software, you will have the license rights granted in Section 2, provided that you may not use the Microsoft PlayReady software unless you have entered into a Microsoft PlayReady Master Agreement and license directly with Microsoft.
MindTree: Notwithstanding the terms contained in Section 2.3 (a), if the Licensed Software includes proprietary software of MindTree in source code format, Licensee may make modifications and create derivative works only to the extent necessary for debugging of the Licensed Software.
MM SOLUTIONS AD: Use of MM SOLUTIONS AEC (Auto Exposure Control) and AWB (Auto White Balance) software is limited to demonstration, testing, and evaluation only. In no event may Licensee distribute or sublicense the MM SOLUTIONS software. Further rights must be obtained directly from MM SOLUTIONS.
MPEG LA: Use of MPEG LA audio or video codec technology is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from MPEG LA.
MQX RTOS Code: MQX RTOS source code may not be re-distributed by any NXP Licensee under any circumstance, even by a signed written amendment to this Agreement.
NXP Wireless Charging Library: License to the Software is limited to use in inductive coupling or wireless charging applications
Opus: Use of Opus software must be consistent with the terms of the Opus license which can be found at: http://www.opus-codec.org/license/
Oracle JRE (Java): The Oracle JRE must be used consistent with terms found here: http://java.com/license
P&E Micro: P&E Software must be used consistent with the terms found here: http://www.pemicro.com/licenses/gdbserver/license_gdb.pdf
Pro Design Electronic: Licensee may not modify, create derivative works based on, or copy the Pro Design software, documentation, hardware execution key or the accompanying materials. Licensee shall not use Pro Design's or any of its licensors names, logos or trademarks to market the Authorized System. Only NXP customers and distributors are permitted to further redistribute the Pro Design software and only as part of an Authorized System which contains the Pro Design software.
Qualcomm Atheros, Inc.: Notwithstanding anything in this Agreement, Qualcomm Atheros, Inc. Wi-Fi software must be used strictly in accordance with the Qualcomm Atheros, Inc. Technology License Agreement that accompanies such software. Any other use is expressly prohibited.
Real Networks - GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code: Use of the GStreamer Optimized Real Format Client Code, or OpenMax Optimized Real Format Client code is restricted to applications in the automotive market. Licensee must be a final manufacturer in good standing with a current license with Real Networks for the commercial use and distribution of products containing the GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code
RivieraWaves SAS (a member of the CEVA, Inc. family of companies): You may not use the RivieraWaves intellectual property licensed under this Agreement if you develop, market, and/or license products similar to such RivieraWaves intellectual property. Such use constitutes a breach of this Agreement. Any such use rights must be obtained directly from RivieraWaves.
SanDisk Corporation: If the Licensed Software includes software developed by SanDisk Corporation ("SanDisk"), you must separately obtain the rights to reproduce and distribute this software in source code form from SanDisk. Please follow these easy steps to obtain the license and software:
(1) Contact your local SanDisk sales representative to obtain the SanDisk License Agreement.
(2) Sign the license agreement. Fax the signed agreement to SanDisk USA marketing department at 408-542-0403. The license will be valid when fully executed by SanDisk.
(3) If you have specific questions, please send an email to sales@sandisk.com
You may only use the SanDisk Corporation Licensed Software on products compatible with a SanDisk Secure Digital Card. You may not use the SanDisk Corporation Licensed Software on any memory device product. SanDisk retains all rights to any modifications or derivative works to the SanDisk Corporation Licensed Software that you may create.
SEGGER Microcontroller - emWin Software: Your use of SEGGER emWin software and components is restricted for development of NXP ARM7, ARM9, Cortex-M0, Cortex-M3, Cortex-M4, Cortex-M33, Cortex-M7, and Cortex-A7 based products only.
SEGGER Microcontroller - J-Link/J-Trace Software: Segger software must be used consistent with the terms found here: http://www.segger.com/jlink-software.html
Synopsys/Target Compiler Technologies: Your use of the Synopsys/Target Compiler Technologies Licensed Software and related documentation is subject to the following:
(1) Duration of the license for the Licensed Software is limited to 12 months, unless otherwise specified in the license file.
(2) The Licensed Software is usable by one user at a time on a single designated computer, unless otherwise agreed by Synopsys.
(3) Licensed Software and documentation are to be used only on a designated computer at the designated physical address provided by you on the APEX license form.
(4) The Licensed Software is not sub-licensable.
TARA Systems: Use of TARA Systems GUI technology Embedded Wizard is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from TARA Systems.
Texas Instruments: Your use of Texas Instruments Inc. WiLink8 Licensed Software is restricted to NXP SoC based systems that include a compatible connectivity device manufactured by TI.
TES Electronic Solutions Germany (TES): TES 3D Surround View software and associated data and documentation may only be used for evaluation purposes and for demonstration to third parties in integrated form on a board package containing an NXP S32V234 device. Licensee may not distribute or sublicense the TES software. Your license to the TES software may be terminated at any time upon notice.
Vivante: Distribution of Vivante software must be a part of, or embedded within, Authorized Systems that include a Vivante Graphics Processing Unit.
\ No newline at end of file
+LA_OPT_NXP_Software_License v11 February 2020
IMPORTANT. Read the following NXP Software License Agreement ("Agreement") completely. By selecting the "I Accept" button at the end of this page, or by downloading, installing, or using the Licensed Software, you indicate that you accept the terms of the Agreement and you acknowledge that you have the authority, for yourself or on behalf of your company, to bind your company to these terms. You may then download or install the file. In the event of a conflict between the terms of this Agreement and any license terms and conditions for NXP's proprietary software embedded anywhere in the Licensed Software file, the terms of this Agreement shall control. If a separate license agreement for the Licensed Software has been signed by you and NXP, then that agreement shall govern your use of the Licensed Software and shall supersede this Agreement.
NXP SOFTWARE LICENSE AGREEMENT
This is a legal agreement between your employer, of which you are an authorized representative, or, if you have no employer, you as an individual ("you" or "Licensee"), and NXP B.V. ("NXP"). It concerns your rights to use the software provided to you in binary or source code form and any accompanying written materials (the "Licensed Software"). The Licensed Software may include any updates or error corrections or documentation relating to the Licensed Software provided to you by NXP under this Agreement. In consideration for NXP allowing you to access the Licensed Software, you are agreeing to be bound by the terms of this Agreement. If you do not agree to all of the terms of this Agreement, do not download or install the Licensed Software. If you change your mind later, stop using the Licensed Software and delete all copies of the Licensed Software in your possession or control. Any copies of the Licensed Software that you have already distributed, where permitted, and do not destroy will continue to be governed by this Agreement. Your prior use will also continue to be governed by this Agreement.
1. DEFINITIONS
1.1. "Affiliate" means, with respect to a party, any corporation or other legal entity that now or hereafter Controls, is Controlled by or is under common Control with such party; where "Control" means the direct or indirect ownership of greater than fifty percent (50%) of the shares or similar interests entitled to vote for the election of directors or other persons performing similar functions. An entity is considered an Affiliate only so long as such Control exists.
1.2 "Authorized System" means either (i) Licensee's hardware product which incorporates an NXP Product or (ii) Licensee's software program which is used exclusively in connection with an NXP Product and with which the Licensed Software will be integrated.
1.3. "Derivative Work" means a work based upon one or more pre-existing works. A work consisting of editorial revisions, annotations, elaborations, or other modifications which, as a whole, represent an original work of authorship, is a Derivative Work.
1.4 "Intellectual Property Rights" means any and all rights under statute, common law or equity in and under copyrights, trade secrets, and patents (including utility models), and analogous rights throughout the world, including any applications for and the right to apply for, any of the foregoing.
1.5 "NXP Product" means a programmable processing unit (e.g. a microprocessor, microcontroller, sensor or digital signal processor) supplied directly or indirectly from NXP or an NXP Affiliate.
1.6 "Software Content Register" means the documentation which may accompany the Licensed Software which identifies the contents of the Licensed Software, including but not limited to identification of any Third Party Software, if any, and may also contain other related information as whether the license in 2.3 is applicable.
1.7 "Third Party Software" means, any software included in the Licensed Software that is not NXP proprietary software, and is not open source software, and to which different license terms may apply.
2. LICENSE GRANT.
2.1. If you are not expressly granted the production use license in Section 2.3 in the Software Content Register, then you are only granted the rights in Section 2.2 and not in 2.3. If you are expressly granted the production use license in Section 2.3 in the Software Content Register, then you are granted the rights in both Section 2.2 and 2.3.
2.2. Internal Use License. Subject to the terms and conditions of this Agreement, NXP grants you a worldwide, personal, non-transferable, non-exclusive, non-sublicensable license, solely for the development of an Authorized System:
(a) to use and reproduce the Licensed Software (and its Derivative Works prepared under the license in Section 2.2(b)); and
(b) for Licensed Software provided to you in source code form (human readable), to prepare Derivative Works of the Licensed Software.
You may not distribute or sublicense the Licensed Software to others under the license granted in this Section 2.2.
2.3. Production Use License. If expressly authorized in the Software Content Register, subject to the terms and conditions of this Agreement, NXP grants you a worldwide, personal, non-transferable, non-exclusive, non-sublicensable license solely in connection with your manufacturing and distribution of an Authorized System:
(a) to manufacture (or have manufactured), distribute, and market the Licensed Software (and its Derivative Works prepared under the license in 2.2(b)) in object code (machine readable format) only as part of, or embedded within, Authorized Systems and not on a standalone basis. Notwithstanding the foregoing, those files marked as .h files ("Header files") may be distributed in source or object code form, but only as part of, or embedded within Authorized Systems; and
(b) to copy and distribute as needed, solely in connection with an Authorized System, non-confidential NXP information provided as part of the Licensed Software for the purpose of maintaining and supporting Authorized Systems with which the Licensed Software is integrated.
2.4 Separate license grants to Third Party Software, or other terms applicable to the Licensed Software if different from those granted in this Section 2, are contained in Appendix A. The Licensed Software may be accompanied by a Software Content Register which will identify that portion of the Licensed Software, if any, that is subject to the different terms in Appendix A.
2.5. You may use subcontractors on your premises to exercise your rights under Section 2.2 and Section 2.3, if any, so long as you have an agreement in place with the subcontractor containing confidentiality restrictions no less stringent than those contained in this Agreement. You will remain liable for your subcontractors' adherence to the terms of this Agreement and for any and all acts and omissions of such subcontractors with respect to this Agreement and the Licensed Software.
3. LICENSE LIMITATIONS AND RESTRICTIONS.
3.1. The licenses granted above in Section 2 only extend to NXP Intellectual Property Rights that would be infringed by the unmodified Licensed Software prior to your preparation of any Derivative Work.
3.2. The Licensed Software is licensed to you, not sold. Title to Licensed Software delivered hereunder remains vested in NXP or NXP's licensor and cannot be assigned or transferred. You are expressly forbidden from selling or otherwise distributing the Licensed Software, or any portion thereof, except as expressly permitted herein. This Agreement does not grant to you any implied rights under any NXP or third party Intellectual Property Rights.
3.3. You may not translate, reverse engineer, decompile, or disassemble the Licensed Software except to the extent applicable law specifically prohibits such restriction. You must prohibit your subcontractors or customers (if distribution is permitted) from translating, reverse engineering, decompiling, or disassembling the Licensed Software except to the extent applicable law specifically prohibits such restriction.
3.4. You must reproduce any and all of NXP's (or its third-party licensor's) copyright notices and other proprietary legends on copies of Licensed Software.
3.5. If you distribute the Licensed Software to the United States Government, then the Licensed Software is "restricted computer software" and is subject to FAR 52.227-19.
3.6. You grant to NXP a non-exclusive, non-transferable, irrevocable, perpetual, worldwide, royalty-free, sub-licensable license under your Intellectual Property Rights to use without restriction and for any purpose any suggestion, comment or other feedback related to the Licensed Software (including, but not limited to, error corrections and bug fixes).
3.7. You will not take or fail to take any action that could subject the Licensed Software to an Excluded License. An Excluded License means any license that requires, as a condition of use, modification or distribution of software subject to the Excluded License, that such software or other software combined and/or distributed with the software be (i) disclosed or distributed in source code form; (ii) licensed for the purpose of making Derivative Works; or (iii) redistributable at no charge.
3.8. You may not publish or distribute information, results or data associated with the use of the Licensed Software to anyone other than NXP; however, you must advise NXP of any results obtained including any problems or suggested improvements thereof. NXP retains the right to use such results and related information in any manner it deems appropriate
4. OPEN SOURCE. Open source software included in the Licensed Software is not licensed under the terms of this Agreement but is instead licensed under the terms of the applicable open source license(s), such as the BSD License, Apache License or the GNU Lesser General Public License. Your use of the open source software is subject to the terms of each applicable license. You must agree to the terms of each applicable license, or you cannot use the open source software.
5. INTELLECTUAL PROPERTY RIGHTS. Your modifications to the Licensed Software, and all Intellectual Property Rights associated with, and title thereto, will be the property of NXP. Upon request, you must provide NXP the source code of any derivative of the Licensed Software. You agree to assign all, and hereby do assign all rights, title, and interest to any such modifications to the Licensed Software to NXP and agree to provide all assistance reasonably requested by NXP to establish, preserve or enforce such right. Further, you agree to waive all moral rights relating to your modifications to the Licensed Software, including, without limitation, all rights of identification of authorship and all rights of approval, restriction, or limitation on use or subsequent modification. Notwithstanding the foregoing, you will have the license rights granted in Section 2 hereto to any such modifications made by you or your subcontractor.
6. ESSENTIAL PATENTS. NXP has no obligation to identify or obtain any license to any Intellectual Property Right of a third-party that may be necessary for use in connection with technology that is incorporated into the Authorized System (whether or not as part of the Licensed Software).
7. TERM AND TERMINATION. This Agreement will remain in effect unless terminated as provided in this Section.
7.1. You may terminate this Agreement immediately upon written notice to NXP at the address provided below.
7.2. Either party may terminate this Agreement if the other party is in default of any of the terms and conditions of this Agreement, and termination is effective if the defaulting party fails to correct such default within 30 days after written notice thereof by the non-defaulting party to the defaulting party at the address below.
7.3. Notwithstanding the foregoing, NXP may terminate this Agreement immediately upon written notice if you: breach any of your confidentiality obligations or the license restrictions under this Agreement; become bankrupt, insolvent, or file a petition for bankruptcy or insolvency; make an assignment for the benefit of its creditors; enter proceedings for winding up or dissolution; are dissolved; or are nationalized or become subject to the expropriation of all or substantially all of your business or assets.
7.4. Upon termination of this Agreement, all licenses granted under Section 2 will expire.
7.5. After termination of this Agreement by either party you will destroy all parts of Licensed Software and its Derivative Works (if any) and will provide to NXP a statement certifying the same.
7.6. Notwithstanding the termination of this Agreement for any reason, the terms of Sections 1 and 3 through 24 will survive.
8. SUPPORT. NXP is not obligated to provide any support, upgrades or new releases of the Licensed Software under this Agreement. If you wish, you may contact NXP and report problems and provide suggestions regarding the Licensed Software. NXP has no obligation to respond to such a problem report or suggestion. NXP may make changes to the Licensed Software at any time, without any obligation to notify or provide updated versions of the Licensed Software to you.
9. NO WARRANTY. To the maximum extent permitted by law, NXP expressly disclaims any warranty for the Licensed Software. The Licensed Software is provided "AS IS", without warranty of any kind, either express or implied, including without limitation the implied warranties of merchantability, fitness for a particular purpose, or non-infringement. You assume the entire risk arising out of the use or performance of the licensed software, or any systems you design using the licensed software (if any).
10. INDEMNITY. You agree to fully defend and indemnify NXP from all claims, liabilities, and costs (including reasonable attorney's fees) related to (1) your use (including your subcontractor's or distributee's use, if permitted) of the Licensed Software or (2) your violation of the terms and conditions of this Agreement.
11. LIMITATION OF LIABILITY. EXCLUDING LIABILITY FOR A BREACH OF SECTION 2 (LICENSE GRANTS), SECTION 3 (LICENSE LIMITATIONS AND RESTRICTIONS), SECTION 16 (CONFIDENTIAL INFORMATION), OR CLAIMS UNDER SECTION 10 (INDEMNITY), IN NO EVENT WILL EITHER PARTY BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, TO THE FULL EXTENT SUCH MAY BE DISCLAIMED BY LAW. NXP'S TOTAL LIABILITY FOR ALL COSTS, DAMAGES, CLAIMS, OR LOSSES WHATSOEVER ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT OR PRODUCT(S) SUPPLIED UNDER THIS AGREEMENT IS LIMITED TO THE AGGREGATE AMOUNT PAID BY YOU TO NXP IN CONNECTION WITH THE LICENSED SOFTWARE PROVIDED UNDER THIS AGREEMENT TO WHICH LOSSES OR DAMAGES ARE CLAIMED.
12. EXPORT COMPLIANCE. Each party shall comply with all applicable export and import control laws and regulations including but not limited to the US Export Administration Regulation (including prohibited party lists issued by other federal governments), Catch-all regulations and all national and international embargoes. Each party further agrees that it will not knowingly transfer, divert, export or re-export, directly or indirectly, any product, software, including software source code, or technology restricted by such regulations or by other applicable national regulations, received from the other party under this Agreement, or any direct product of such software or technical data to any person, firm, entity, country or destination to which such transfer, diversion, export or re-export is restricted or prohibited, without obtaining prior written authorization from the applicable competent government authorities to the extent required by those laws.
13. GOVERNMENT CONTRACT COMPLIANCE
13.1. If you sell Authorized Systems directly to any government or public entity, including U.S., state, local, foreign or international governments or public entities, or indirectly via a prime contractor or subcontractor of such governments or entities, NXP makes no representations, certifications, or warranties whatsoever about compliance with government or public entity acquisition statutes or regulations, including, without limitation, statutes or regulations that may relate to pricing, quality, origin or content.
13.2. The Licensed Software has been developed at private expense and is a "Commercial Item" as defined in 48 C.F.R. Section 2.101, consisting of "Commercial Computer Software", and/or "Commercial Computer Software Documentation," as such terms are used in 48 C.F.R. Section 12.212 (or 48 C.F.R. Section 227.7202, as applicable) and may only be licensed to or shared with U.S. Government end users in object code form as part of, or embedded within, Authorized Systems. Any agreement pursuant to which you share the Licensed Software will include a provision that reiterates the limitations of this document and requires all sub-agreements to similarly contain such limitations.
14. CRITICAL APPLICATIONS. In some cases, NXP may promote certain software for use in the development of, or for incorporation into, products or services (a) used in applications requiring fail-safe performance or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (these products and services are referred to as "Critical Applications"). NXP's goal is to educate customers so that they can design their own end-product solutions to meet applicable functional safety standards and requirements. Licensee makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, Licensee assumes all risk related to use of the Licensed Software in Critical Applications and NXP SHALL NOT BE LIABLE FOR ANY SUCH USE IN CRITICAL APPLICATIONS BY LICENSEE. Accordingly, Licensee will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys' fees) that NXP may incur related to Licensee's incorporation of the Licensed Software in a Critical Application.
15. CHOICE OF LAW; VENUE. This Agreement will be governed by, construed, and enforced in accordance with the laws of The Netherlands, without regard to conflicts of laws principles, will apply to all matters relating to this Agreement or the Licensed Software, and you agree that any litigation will be subject to the exclusive jurisdiction of the courts of Amsterdam, The Netherlands. The United Nations Convention on Contracts for the International Sale of Goods will not apply to this document.
16. CONFIDENTIAL INFORMATION. Subject to the license grants and restrictions contained herein, you must treat the Licensed Software as confidential information and you agree to retain the Licensed Software in confidence perpetually. You may not disclose any part of the Licensed Software to anyone other than distributees in accordance with Section 2.3 and employees, or subcontractors in accordance with Section 2.5, who have a need to know of the Licensed Software and who have executed written agreements obligating them to protect such Licensed Software to at least the same degree of confidentiality as in this Agreement. You agree to use the same degree of care, but no less than a reasonable degree of care, with the Licensed Software as you do with your own confidential information. You may disclose Licensed Software to the extent required by a court or under operation of law or order provided that you notify NXP of such requirement prior to disclosure, which you only disclose the minimum of the required information, and that you allow NXP the opportunity to object to such court or other legal body requiring such disclosure.
17. TRADEMARKS. You are not authorized to use any NXP trademarks, brand names, or logos.
18. ENTIRE AGREEMENT. This Agreement constitutes the entire agreement between you and NXP regarding the subject matter of this Agreement, and supersedes all prior communications, negotiations, understandings, agreements or representations, either written or oral, if any. This Agreement may only be amended in written form, signed by you and NXP.
19. SEVERABILITY. If any provision of this Agreement is held for any reason to be invalid or unenforceable, then the remaining provisions of this Agreement will be unimpaired and, unless a modification or replacement of the invalid or unenforceable provision is further held to deprive you or NXP of a material benefit, in which case the Agreement will immediately terminate, the invalid or unenforceable provision will be replaced with a provision that is valid and enforceable and that comes closest to the intention underlying the invalid or unenforceable provision.
20. NO WAIVER. The waiver by NXP of any breach of any provision of this Agreement will not operate or be construed as a waiver of any other or a subsequent breach of the same or a different provision.
21. AUDIT. You will keep full, clear and accurate records with respect to your compliance with the limited license rights granted under this Agreement for three years following expiration or termination of this Agreement. NXP will have the right, either itself or through an independent certified public accountant to examine and audit, at NXP's expense, not more than once a year, and during normal business hours, all such records that may bear upon your compliance with the limited license rights granted above. You must make prompt adjustment to compensate for any errors and/or omissions disclosed by such examination or audit.
22. NOTICES. All notices and communications under this Agreement will be made in writing, and will be effective when received at the following addresses:
NXP: NXP B.V.
High Tech Campus 60
5656 AG Eindhoven
The Netherlands
ATTN: Legal Department
You: The address provided at registration will be used.
23. RELATIONSHIP OF THE PARTIES. The parties are independent contractors. Nothing in this Agreement will be construed to create any partnership, joint venture, or similar relationship. Neither party is authorized to bind the other to any obligations with third parties.
24. SUCCESSION AND ASSIGNMENT. This Agreement will be binding upon and inure to the benefit of the parties and their permitted successors and assigns. You may not assign this Agreement, or any part of this Agreement, without the prior written approval of NXP, which approval will not be unreasonably withheld or delayed. NXP may assign this Agreement, or any part of this Agreement, in its sole discretion.
+
APPENDIX A
Other License Grants and Restrictions:
The Licensed Software may include some or all of the following software, which is either 1) Third Party Software or 2) NXP proprietary software subject to different terms than those in the Agreement. If the Software Content Register that accompanies the Licensed Software identifies any of the following Third Party Software or specific components of the NXP proprietary software, the following terms apply to the extent they deviate from the terms in the Agreement:
Amazon: Use of the Amazon software constitutes your acceptance of the terms of the Amazon Program Materials License Agreement (including the AVS Component Schedule, if applicable), located at https://developer.amazon.com/support/legal/pml. All Amazon software is hereby designated "Amazon confidential". Amazon is a third-party beneficiary to this Agreement with respect to the Amazon software.
Amphion Semiconductor Ltd.: Distribution of Amphion software must be a part of, or embedded within, Authorized Systems that include an Amphion Video Decoder.
Aquantia Corp.: You may use Aquantia's API binaries solely to flash the API software to an NXP Product which mates with an Aquantia device.
Atheros: Use of Atheros software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Atheros.
ATI (AMD): Distribution of ATI software must be a part of, or embedded within, Authorized Systems that include a ATI graphics processor core.
Broadcom Corporation: Your use of Broadcom Corporation software is restricted to Authorized Systems that incorporate a compatible integrated circuit device manufactured or sold by Broadcom.
Cadence Design Systems: Use of Cadence audio codec software is limited to distribution only of one copy per single NXP Product. The license granted herein to the Cadence Design Systems HiFi aacPlus Audio Decoder software does not include a license to the AAC family of technologies which you or your customer may need to obtain. Configuration tool outputs may only be distributed by licensees of the relevant Cadence SDK and distribution is limited to distribution of one copy embedded in a single NXP Product.
Cirque Corporation: Use of Cirque Corporation technology is limited to evaluation, demonstration, or certification testing only. Permitted distributions must be similarly limited. Further rights, including but not limited to ANY commercial distribution rights, must be obtained directly from Cirque Corporation.
Coding Technologies (Dolby Labs): Use of CTS software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Dolby Laboratories.
CSR: Use of Cambridge Silicon Radio, Inc. ("CSR") software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from CSR.
Crank: Use of Crank Software Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from Crank Software Inc.
Cypress Semiconductor Corporation: WWD RTOS source code may only be used in accordance with the Cypress IOT Community License Agreement located at https://community.cypress.com/terms-and-conditions!input.jspa?displayOnly=true.
Embedded Systems Academy GmbH (EmSA): Any use of Micro CANopen Plus is subject to the acceptance of the license conditions described in the LICENSE.INFO file distributed with all example projects and in the documentation and the additional clause described below.
Clause 1: Micro CANopen Plus may not be used for any competitive or comparative purpose, including the publication of any form of run time or compile time metric, without the express permission of EmSA.
Future Technology Devices International Ltd.: Future Technology Devices International software must be used consistent with the terms found here: http://www.ftdichip.com/Drivers/FTDriverLicenceTerms.htm
Global Locate (Broadcom Corporation): Use of Global Locate, Inc. software is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained from Global Locate.
Microsoft: Except for Microsoft PlayReady software, if the Licensed Software includes software owned by Microsoft Corporation ("Microsoft"), it is subject to the terms of your license with Microsoft (the "Microsoft Underlying Licensed Software") and as such, NXP grants no license to you, beyond evaluation and demonstration in connection with NXP processors, in the Microsoft Underlying Licensed Software. You must separately obtain rights beyond evaluation and demonstration in connection with the Microsoft Underlying Licensed Software from Microsoft. Microsoft does not provide support services for the components provided to you through this Agreement. If you have any questions or require technical assistance, please contact NXP. Microsoft Corporation is a third party beneficiary to this Agreement with the right to enforce the terms of this Agreement. TO THE MAXIMUM EXTENT PERMITTED BY LAW, MICROSOFT AND ITS AFFILIATES DISCLAIM ANY WARRANTIES FOR THE MICROSOFT UNDERLYING LICENSED SOFTWARE. TO THE MAXIMUM EXTENT PERMITTED BY LAW, NEITHER MICROSOFT NOR ITS AFFILIATES WILL BE LIABLE, WHETHER IN CONTRACT, TORT, OR OTHERWISE, FOR ANY DIRECT, INCIDENTAL, SPECIAL, INDIRECT, CONSEQUENTIAL OR PUNITIVE DAMAGES, INCLUDING, BUT NOT LIMITED TO, DAMAGES FOR ANY LOSS OF USE, LOSS OF TIME, INCONVENIENCE, COMMERCIAL LOSS, OR LOST PROFITS, SAVINGS, OR REVENUES, ARISING FROM THE FROM THE USE OF THE MICROSOFT UNDERLYING LICENSED SOFTWARE. With respect to the Microsoft PlayReady software, you will have the license rights granted in Section 2, provided that you may not use the Microsoft PlayReady software unless you have entered into a Microsoft PlayReady Master Agreement and license directly with Microsoft.
MindTree: Notwithstanding the terms contained in Section 2.3 (a), if the Licensed Software includes proprietary software of MindTree in source code format, Licensee may make modifications and create derivative works only to the extent necessary for debugging of the Licensed Software.
MM SOLUTIONS AD: Use of MM SOLUTIONS AEC (Auto Exposure Control) and AWB (Auto White Balance) software is limited to demonstration, testing, and evaluation only. In no event may Licensee distribute or sublicense the MM SOLUTIONS software. Further rights must be obtained directly from MM SOLUTIONS.
MPEG LA: Use of MPEG LA audio or video codec technology is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from MPEG LA.
MQX RTOS Code: MQX RTOS source code may not be re-distributed by any NXP Licensee under any circumstance, even by a signed written amendment to this Agreement.
NXP Wireless Charging Library: License to the Software is limited to use in inductive coupling or wireless charging applications
Opus: Use of Opus software must be consistent with the terms of the Opus license which can be found at: http://www.opus-codec.org/license/
Oracle JRE (Java): The Oracle JRE must be used consistent with terms found here: http://java.com/license
P&E Micro: P&E Software must be used consistent with the terms found here: http://www.pemicro.com/licenses/gdbserver/license_gdb.pdf
Pro Design Electronic: Licensee may not modify, create derivative works based on, or copy the Pro Design software, documentation, hardware execution key or the accompanying materials. Licensee shall not use Pro Design's or any of its licensors names, logos or trademarks to market the Authorized System. Only NXP customers and distributors are permitted to further redistribute the Pro Design software and only as part of an Authorized System which contains the Pro Design software.
Qualcomm Atheros, Inc.: Notwithstanding anything in this Agreement, Qualcomm Atheros, Inc. Wi-Fi software must be used strictly in accordance with the Qualcomm Atheros, Inc. Technology License Agreement that accompanies such software. Any other use is expressly prohibited.
Real Networks - GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code: Use of the GStreamer Optimized Real Format Client Code, or OpenMax Optimized Real Format Client code is restricted to applications in the automotive market. Licensee must be a final manufacturer in good standing with a current license with Real Networks for the commercial use and distribution of products containing the GStreamer Optimized Real Format Client Code implementation or OpenMax Optimized Real Format Client Code
Real Time Engineers Ltd.: Any FreeRTOS source code, whether modified or in its original release form, or whether in whole or in part, can only be distributed by you under the terms of version 2 of the GNU General Public License plus this exception. An independent module is a module which is not derived from or based on FreeRTOS.
Clause 1: Linking FreeRTOS with other modules is making a combined work based on FreeRTOS. Thus, the terms and conditions of the GNU General Public License V2 cover the whole combination.
As a special exception, the copyright holders of FreeRTOS give you permission to link FreeRTOS with independent modules to produce a statically linked executable, regardless of the license terms of these independent modules, and to copy and distribute the resulting executable under terms of your choice, provided that you also meet, for each linked independent module, the terms and conditions of the license of that module. An independent module is a module which is not derived from or based on FreeRTOS.
Clause 2: FreeRTOS may not be used for any competitive or comparative purpose, including the publication of any form of run time or compile time metric, without the express permission of Real Time Engineers Ltd. (this is the norm within the industry and is intended to ensure information accuracy).
RivieraWaves SAS (a member of the CEVA, Inc. family of companies): You may not use the RivieraWaves intellectual property licensed under this Agreement if you develop, market, and/or license products similar to such RivieraWaves intellectual property. Such use constitutes a breach of this Agreement. Any such use rights must be obtained directly from RivieraWaves.
SanDisk Corporation: If the Licensed Software includes software developed by SanDisk Corporation ("SanDisk"), you must separately obtain the rights to reproduce and distribute this software in source code form from SanDisk. Please follow these easy steps to obtain the license and software:
(1) Contact your local SanDisk sales representative to obtain the SanDisk License Agreement.
(2) Sign the license agreement. Fax the signed agreement to SanDisk USA marketing department at 408-542-0403. The license will be valid when fully executed by SanDisk.
(3) If you have specific questions, please send an email to sales@sandisk.com
You may only use the SanDisk Corporation Licensed Software on products compatible with a SanDisk Secure Digital Card. You may not use the SanDisk Corporation Licensed Software on any memory device product. SanDisk retains all rights to any modifications or derivative works to the SanDisk Corporation Licensed Software that you may create.
SEGGER Microcontroller - emWin Software: Your use of SEGGER emWin software and components is restricted for development of NXP ARM7, ARM9, Cortex-M0, Cortex-M3, Cortex-M4, Cortex-M33, Cortex-M7, and Cortex-A7 based products only.
SEGGER Microcontroller - J-Link/J-Trace Software: Segger software must be used consistent with the terms found here: http://www.segger.com/jlink-software.html
Synopsys/Target Compiler Technologies: Your use of the Synopsys/Target Compiler Technologies Licensed Software and related documentation is subject to the following:
(1) Duration of the license for the Licensed Software is limited to 12 months, unless otherwise specified in the license file.
(2) The Licensed Software is usable by one user at a time on a single designated computer, unless otherwise agreed by Synopsys.
(3) Licensed Software and documentation are to be used only on a designated computer at the designated physical address provided by you on the APEX license form.
(4) The Licensed Software is not sub-licensable.
TARA Systems: Use of TARA Systems GUI technology Embedded Wizard is limited to evaluation and demonstration only. Permitted distributions must be similarly limited. Further rights must be obtained directly from TARA Systems.
Texas Instruments: Your use of Texas Instruments Inc. WiLink8 Licensed Software is restricted to NXP SoC based systems that include a compatible connectivity device manufactured by TI.
TES Electronic Solutions Germany (TES): TES 3D Surround View software and associated data and documentation may only be used for evaluation purposes and for demonstration to third parties in integrated form on a board package containing an NXP S32V234 device. Licensee may not distribute or sublicense the TES software. Your license to the TES software may be terminated at any time upon notice.
Vivante: Distribution of Vivante software must be a part of, or embedded within, Authorized Systems that include a Vivante Graphics Processing Unit.
\ No newline at end of file
diff --git a/SW-Content-Register.txt b/SW-Content-Register.txt
index 677abd4dd..d8dacd794 100644
--- a/SW-Content-Register.txt
+++ b/SW-Content-Register.txt
@@ -1,6 +1,6 @@
Release Name: MCUXpresso Software Development Kit (SDK)
-Release Version: 2.9.0
-Package License: LA_OPT_NXP_Software_License.txt - Additional Distribution License granted, license in Section 2.3 applies
+Release Version: 2.9.4
+Package License: LA_OPT_NXP_Software_License.txt - Additional Distribution License, Section 2.3 applies
SDK_Peripheral_Driver Name: SDK Peripheral Driver
Version: 2.x.x
@@ -49,16 +49,6 @@ cmsis Name: CMSIS
https://github.com/ARM-software/CMSIS_5/releases/t
ag/5.6.0
-cmsis_gpio Name: CMSIS GPIO Interface
- Version: 2.0.0
- Outgoing License: BSD-3-Clause
- License File: COPYING-BSD-3
- Format: source code
- Description: CMSIS Driver style GPIO interface
- definition created by NXP.
- Location: CMSIS/Driver/Include/Driver_GPIO.h
- Origin: NXP (BSD-3-Clause)
-
SDK_Components Name: SDK components and board peripheral drivers
Version: NA
Outgoing License: BSD-3-Clause
@@ -72,13 +62,12 @@ SDK_Components Name: SDK components and board peripheral drivers
freertos Name: FreeRTOS
Version: 202007.00.0
Outgoing License: MIT
- License File:
- rtos/freertos_kernel/License/license.txt
+ License File: rtos/freertos/LICENSE
Format: source code
Description: IoT operating system for
microcontrollers
Location: rtos/freertos
- Origin: Amazon (MIT)
+ Origin: Real Time Engineers, Ltd. (MIT)
Url: https://aws.amazon.com/freertos/
FreeRTOS_heap_newlib Name: FreeRTOS Newlib helper
@@ -97,51 +86,6 @@ FreeRTOS_heap_newlib Name: FreeRTOS Newlib helper
http://www.nadler.com/embedded/newlibAndFreeRTOS.h
tml
-mmcau Name: mmCAU S/W Library
- Version: 2.0.1
- Outgoing License: BSD-3-Clause
- License File: COPYING-BSD-3
- Format: source code
- Description: S/W library that works with the
- memory-mapped cryptographic acceleration unit
- present on some MCUXpresso SoCs
- Location: middleware/mmcau
- Origin: NXP (BSD-3-Clause)
-
-cmsis_drivers Name: SDK CMSIS Peripheral Drivers
- Version: 2.x.x
- Outgoing License: Apache License 2.0
- License File: CMSIS/LICENSE.txt
- Format: source code
- Description: CMSIS Peripheral drivers are designed
- to provide hardware independent APIs which make
- application reusable across a wide range of
- supported microcontroller devices.
- Location: devices//cmsis_drivers
- Origin: NXP (Apache License 2.0)
-
-multicore Name: Multicore SDK
- Version: 2.9.0
- Outgoing License: BSD-3-Clause
- License File: COPYING-BSD-3
- Format: source code
- Description: NXP Multicore Software Development
- Kit.
- Location: middleware/multicore
- Origin: NXP (BSD-3-Clause)
-
-rpmsg_lite Name: RPMsg-Lite
- Version: 3.1.1
- Outgoing License: BSD-3-Clause
- License File: COPYING-BSD-3
- Format: source code
- Description: Open Asymmetric Multi Processing
- (OpenAMP) framework project
- Location: middleware/multicore/rpmsg_lite
- Origin: Mentor Graphics Corporation & community
- contributors
- Url: https://github.com/NXPmicro/rpmsg-lite
-
sdmmc Name: SD MMC SDIO Card middleware
Version: 2.2.7
Outgoing License: BSC-3-Clause
@@ -152,156 +96,71 @@ sdmmc Name: SD MMC SDIO Card middleware
Location: middleware/sdmmc
Origin: NXP (BSD-3-Clause)
-sdmmc_sdspi Name: SD Card middleware
- Version: 2.1.4
- Outgoing License: BSC-3-Clause
- License File: COPYING-BSD-3
- Format: source code
- Description: A software component support access
- SD card through spi.
- Location: middleware/sdmmc/sdspi
- Origin: NXP (BSD-3-Clause)
-
-segger_systemview Name: Segger SystemView Demo
- Version: 2.40a
+mbedtls Name: Mbed TLS
+ Version: 2.16.6
+ Outgoing License: Apache-2.0
+ License File: middleware/mbedtls/apache-2.0.txt
+ Format: source code
+ Description: Cryptographic and SSL/TLS Library
+ Location: middleware/mbedtls
+ Origin: ARM(Apache-2.0) -
+ https://github.com/ARMmbed/mbedtls/releases/tag/mb
+ edtls-2.16.6
+
+lwip Name: lwIP TCP/IP Stack
+ Version: lwIP git repository (2019-12-12, branch:
+ master, SHA-1:
+ 555812dcec38c9a2ef1ef9b31816291549fbf9f8)
Outgoing License: BSD-3-Clause
- License File:
- boards//rtos_examples/visualization/freerto
- s_segger_sysview/LICENSE
- Format: source code
- Description: Segger systemview demo
- Location:
- boards//rtos_examples/visualization/freerto
- s_segger_sysview
- Origin: Segger (BSD-3-Clause)
-
-erpc Name: eRPC
- Version: 1.8.0
- Outgoing License: BSD-3-Clause
- License File: middleware/multicore/erpc/LICENSE
- Format: source code
- Description: Embedded Remote Procedure Call
- Location: middleware/multicore/erpc
- Origin: NXP & community contributors
- Url: https://github.com/EmbeddedRPC/erpc
-
-the_bus_pirate Name: The Bus Pirate
- Version: NA
- Outgoing License: Open Source - CC0 (Public Domain
- Dedication License)
- License File:
- http://code.google.com/p/the-bus-pirate/
- Format: source code
- Description: OS independent serial interface
- Location:
- middleware/multicore/erpc/erpc_c/port/erpc_serial.
- h,
- middleware/multicore/erpc/erpc_c/port/erpc_serial.
- cpp
- Origin: Community
- Url: http://code.google.com/p/the-bus-pirate/
-
-cpp_template Name: CPP Template
- Version: NA
- Outgoing License: Open Source - MIT
- License File:
- middleware/multicore/erpc/erpcgen/src/cpptemplate/
- LICENSE.txt
- Format: source code
- Description: CPP Template
- Location:
- middleware/multicore/erpc/erpcgen/src/cpptemplate
- Origin: Ryan Ginstrom & Martinho Fernandes
-
-cpp_option_parser Name: C++ option-parser
- Version: NA
- Outgoing License: Brad Appleton's license
- License File:
- http://www.bradapp.com/ftp/src/libs/C++/Options.ta
- r.gz , see README file
- Format: Plain Text
- Description: C++ option-parser
- Location:
- middleware/multicore/erpc/erpcgen/src/options.cpp
- Origin: Brad Appleton bradapp@enteract.com
- Url:
- http://www.bradapp.com/ftp/src/libs/C++/Options.ht
- ml
-
-Pedometer_Library Name: Pedometer Library
- Version: 1.0
- Outgoing License: LA_OPT_NXP_Software_License
- License File:
- Format: binary library
- Description: Pedometer algorithm library for Arm
- Cortex M0+ and M4 processors
- Location:
- middleware/issdk/algorithms/pedometer/lib
- Origin: KEYnetik, Inc
-
-dsp_audio_framework Name: dsp_audio_framework
- Version: 2.0
- Outgoing License: MIT
- License File:
- middleware/dsp/audio_framework/LICENSE.txt
- Format: source code
- Description: DSP Audio Streamer Framework based on
- Xtensa Audio Framework from Cadence Design
- Location: middleware/dsp/audio_framework
- Origin: Cadence Design Systems, Inc. & NXP
-
-dsp_nn Name: dsp_nn
- Version: 2.2.0
- Outgoing License: Cadence Design Systems License
- Agreement
- License File: middleware\dsp\nn\nnlib\LICENSE
- Format: source code, header files, binary files
- Description: DSP Neural Networks Framework based
- on Xtensa Neural Networks Library from Cadence
- Design
- Location: middleware/dsp/nn
- Origin: Cadence Design Systems, Inc. & NXP
-
-naturedsp_hifi4 Name: naturedsp
- Version: 4.0.0
- Outgoing License: LA_OPT_NXP_Software_License.txt
- - No distribution permitted, license in Section
- 2.2 applies.
+ License File: middleware/lwip/COPYING
+ Format: source code
+ Description: A light-weight TCP/IP stack
+ Location: middleware/lwip
+ Origin: Swedish Institute of Computer Science
+ Url: http://savannah.nongnu.org/projects/lwip
+
+wifi_nxp Name: NXP Wi-Fi driver
+ Version: 1.3.r20.p1
+ Outgoing License: LA_OPT_NXP_Software_License -
+ Additional distribution license granted - License
+ in Section 2.3 applies
License File: LA_OPT_NXP_Software_License.txt
- Format: source code
- Description: Digital Signal Processing for Xtensa
- HiFi Audio Engines
- Location: middleware/dsp/naturedsp/hifi4
- Origin: Cadence Design Systems (Proprietary)
-
-CRC32-GS Name: CRC32 code
+ Format: source code, header files, firmware
+ binaries
+ Description: NXP Wi-Fi driver and networking
+ utilities
+ Location: middleware/wifi
+ Origin: NXP
+
+sha224_256 Name: Secure Hash Algorithms SHA-224 and SHA-256
Version: NA
- Outgoing License: Public domain
- License File:
- Format: source code
- Description: CRC32 code written by Gary S. Brown
- Location:
- components/codec/tfa9xxx/vas_tfa_drv/tfa_container
- _crc32.c
- Origin: Gary S. Brown
-
-MCMGR Name: MCMGR
- Version: 4.1.1
Outgoing License: BSD-3-Clause
License File: COPYING-BSD-3
Format: source code
- Description: Multicore manager
- Location: middleware/multicore/mcmgr
- Origin: NXP (BSD-3-Clause)
+ Description: Secure Hash Algorithms SHA-224 and
+ SHA-256 implementations
+ Location: boards\rdmw320_r0\mbedtls_common
+ Origin: IETF Trust and the persons
-bosch_sensor_drivers.lpcxprName: Bosch Sensor drivers
-esso54114 Version: NA
- Outgoing License: BSD-3-Clause
- License File: COPYING-BSD-3
- Format: source code
- Description: Bosch Sensor drivers
- Location:
- boards/lpcxpresso54114/multicore_examples/low_powe
- r/sensors
- Origin: Bosch Sensortec GmbH
- Url: https://github.com/BoschSensortec
+boot2 Name: MW3xx device boot loader
+ Version: 6.0
+ Outgoing License: LA_OPT_NXP_Software_License.txt
+ - Additional distribution license granted -
+ License in Section 2.3 applies
+ License file: LA_OPT_NXP_Software_License.txt
+ Format: binary
+ Description: MW3xx device boot loader from WMSDK
+ V6.0.r7.p1
+ Location: tools/boot2/boot2.bin
+ Origin: NXP
+
+mw_img_conv Name: MW3xx image converter
+ Version: 1.0.0
+ Outgoing License: LA_OPT_NXP_Software_License.txt
+ - Additional distribution license granted -
+ License in Section 2.3 applies
+ License file: LA_OPT_NXP_Software_License.txt
+ Format: Source, binary
+ Description: Tool for MW3xx image converter.
+ Location: tools/mw_img_conv
+ Origin: NXP
diff --git a/all_devices.cmake b/all_devices.cmake
index f31a32803..9a8b4b510 100644
--- a/all_devices.cmake
+++ b/all_devices.cmake
@@ -1,56 +1,56 @@
CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0)
# OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+if(${MCUX_DEVICE} STREQUAL "88MW320")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1052
+ ${CMAKE_CURRENT_LIST_DIR}/devices/88MW320
)
- include(all_lib_device_MIMXRT1052)
+ include(all_lib_device_88MW320)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1064
+ ${CMAKE_CURRENT_LIST_DIR}/devices/K32L2A41A
)
- include(all_lib_device_MIMXRT1064)
+ include(all_lib_device_K32L2A41A)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC845")
+if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC845
+ ${CMAKE_CURRENT_LIST_DIR}/devices/K32L2B31A
)
- include(all_lib_device_LPC845)
+ include(all_lib_device_K32L2B31A)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC812")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC812
+ ${CMAKE_CURRENT_LIST_DIR}/devices/K32L3A60
)
- include(all_lib_device_LPC812)
+ include(all_lib_device_K32L3A60_cm4)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK28FA15")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MK28FA15
+ ${CMAKE_CURRENT_LIST_DIR}/devices/K32L3A60
)
- include(all_lib_device_MK28FA15)
+ include(all_lib_device_K32L3A60_cm0plus)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC802")
+if(${MCUX_DEVICE} STREQUAL "LPC51U68")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC802
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC51U68
)
- include(all_lib_device_LPC802)
+ include(all_lib_device_LPC51U68)
endif()
@@ -72,354 +72,363 @@ if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4")
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
+if(${MCUX_DEVICE} STREQUAL "LPC54628")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8MQ6
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC54628
)
- include(all_lib_device_MIMX8MQ6)
+ include(all_lib_device_LPC54628)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
+if(${MCUX_DEVICE} STREQUAL "LPC54S018")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8MM6
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC54S018
)
- include(all_lib_device_MIMX8MM6)
+ include(all_lib_device_LPC54S018)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
+if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKE15Z7
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC54S018M
)
- include(all_lib_device_MKE15Z7)
+ include(all_lib_device_LPC54S018M)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
+if(${MCUX_DEVICE} STREQUAL "LPC55S16")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/K32L2B31A
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC55S16
)
- include(all_lib_device_K32L2B31A)
+ include(all_lib_device_LPC55S16)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK64F12")
+if(${MCUX_DEVICE} STREQUAL "LPC55S28")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MK64F12
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC55S28
)
- include(all_lib_device_MK64F12)
+ include(all_lib_device_LPC55S28)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MK66F18
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC55S69
)
- include(all_lib_device_MK66F18)
+ include(all_lib_device_LPC55S69_cm33_core1)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKE16Z4
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC55S69
)
- include(all_lib_device_MKE16Z4)
+ include(all_lib_device_LPC55S69_cm33_core0)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
+if(${MCUX_DEVICE} STREQUAL "LPC802")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8QM6
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC802
)
- include(all_lib_device_MIMX8QM6_cm4_core0)
+ include(all_lib_device_LPC802)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
+if(${MCUX_DEVICE} STREQUAL "LPC804")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8QM6
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC804
)
- include(all_lib_device_MIMX8QM6_cm4_core1)
+ include(all_lib_device_LPC804)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
+if(${MCUX_DEVICE} STREQUAL "LPC812")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKV11Z7
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC812
)
- include(all_lib_device_MKV11Z7)
+ include(all_lib_device_LPC812)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
+if(${MCUX_DEVICE} STREQUAL "LPC824")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKV31F51212
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC824
)
- include(all_lib_device_MKV31F51212)
+ include(all_lib_device_LPC824)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54628")
+if(${MCUX_DEVICE} STREQUAL "LPC845")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC54628
+ ${CMAKE_CURRENT_LIST_DIR}/devices/LPC845
)
- include(all_lib_device_LPC54628)
+ include(all_lib_device_LPC845)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MK22F51212
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MCIMX7U5
)
- include(all_lib_device_MK22F51212)
+ include(all_lib_device_MCIMX7U5)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE06Z4")
+if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKE06Z4
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8MM6
)
- include(all_lib_device_MKE06Z4)
+ include(all_lib_device_MIMX8MM6)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
+if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8QX6
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8MN6
)
- include(all_lib_device_MIMX8QX6)
+ include(all_lib_device_MIMX8MN6)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC824")
+if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC824
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8MQ6
)
- include(all_lib_device_LPC824)
+ include(all_lib_device_MIMX8MQ6)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
+if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1021
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8QM6
)
- include(all_lib_device_MIMXRT1021)
+ include(all_lib_device_MIMX8QM6_cm4_core0)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE02Z4")
+if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKE02Z4
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8QM6
)
- include(all_lib_device_MKE02Z4)
+ include(all_lib_device_MIMX8QM6_cm4_core1)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
+if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC55S16
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8QX6
)
- include(all_lib_device_LPC55S16)
+ include(all_lib_device_MIMX8QX6)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1062
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1011
)
- include(all_lib_device_MIMXRT1062)
+ include(all_lib_device_MIMXRT1011)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMX8MN6
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1015
)
- include(all_lib_device_MIMX8MN6)
+ include(all_lib_device_MIMXRT1015)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54S018")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC54S018
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1021
)
- include(all_lib_device_LPC54S018)
+ include(all_lib_device_MIMXRT1021)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE04Z4")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKE04Z4
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1024
)
- include(all_lib_device_MKE04Z4)
+ include(all_lib_device_MIMXRT1024)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC804")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC804
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1052
)
- include(all_lib_device_LPC804)
+ include(all_lib_device_MIMXRT1052)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/K32L3A60
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1062
)
- include(all_lib_device_K32L3A60_cm4)
+ include(all_lib_device_MIMXRT1062)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/K32L3A60
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1064
)
- include(all_lib_device_K32L3A60_cm0plus)
+ include(all_lib_device_MIMXRT1064)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC54S018M
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT685S
)
- include(all_lib_device_LPC54S018M)
+ include(all_lib_device_MIMXRT685S_cm33)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+if(${MCUX_DEVICE} STREQUAL "MK22F51212")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKM35Z7
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MK22F51212
)
- include(all_lib_device_MKM35Z7)
+ include(all_lib_device_MK22F51212)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+if(${MCUX_DEVICE} STREQUAL "MK28FA15")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC51U68
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MK28FA15
)
- include(all_lib_device_LPC51U68)
+ include(all_lib_device_MK28FA15)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
+if(${MCUX_DEVICE} STREQUAL "MK64F12")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MKL27Z644
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MK64F12
)
- include(all_lib_device_MKL27Z644)
+ include(all_lib_device_MK64F12)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1")
+if(${MCUX_DEVICE} STREQUAL "MK66F18")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC55S69
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MK66F18
)
- include(all_lib_device_LPC55S69_cm33_core1)
+ include(all_lib_device_MK66F18)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
+if(${MCUX_DEVICE} STREQUAL "MKE02Z4")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC55S69
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKE02Z4
)
- include(all_lib_device_LPC55S69_cm33_core0)
+ include(all_lib_device_MKE02Z4)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+if(${MCUX_DEVICE} STREQUAL "MKE04Z4")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MCIMX7U5
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKE04Z4
)
- include(all_lib_device_MCIMX7U5)
+ include(all_lib_device_MKE04Z4)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+if(${MCUX_DEVICE} STREQUAL "MKE06Z4")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1024
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKE06Z4
)
- include(all_lib_device_MIMXRT1024)
+ include(all_lib_device_MKE06Z4)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1011
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKE15Z7
)
- include(all_lib_device_MIMXRT1011)
+ include(all_lib_device_MKE15Z7)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S28")
+if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/LPC55S28
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKE16Z4
)
- include(all_lib_device_LPC55S28)
+ include(all_lib_device_MKE16Z4)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
+if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/K32L2A41A
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKL27Z644
)
- include(all_lib_device_K32L2A41A)
+ include(all_lib_device_MKL27Z644)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
+if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT685S
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKM35Z7
)
- include(all_lib_device_MIMXRT685S_cm33)
+ include(all_lib_device_MKM35Z7)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
list(APPEND CMAKE_MODULE_PATH
- ${CMAKE_CURRENT_LIST_DIR}/devices/MIMXRT1015
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKV11Z7
)
- include(all_lib_device_MIMXRT1015)
+ include(all_lib_device_MKV11Z7)
+
+endif()
+
+if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
+ list(APPEND CMAKE_MODULE_PATH
+ ${CMAKE_CURRENT_LIST_DIR}/devices/MKV31F51212
+ )
+
+ include(all_lib_device_MKV31F51212)
endif()
diff --git a/boards/rdmw320_r0/board.c b/boards/rdmw320_r0/board.c
new file mode 100644
index 000000000..9c4f7ed0f
--- /dev/null
+++ b/boards/rdmw320_r0/board.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_clock.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq;
+
+ /* attach FAST clock to UART0 (debug console) */
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+ uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
diff --git a/boards/rdmw320_r0/board.h b/boards/rdmw320_r0/board.h
new file mode 100644
index 000000000..7b7367572
--- /dev/null
+++ b/boards/rdmw320_r0/board.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "RDMW320-R0"
+
+/*! @brief Macro to judge XIP */
+#define BOARD_IS_XIP() \
+ (((uint32_t)BOARD_InitDebugConsole >= 0x1F000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x20000000U))
+
+/*! @brief The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) UART0
+#define BOARD_DEBUG_UART_INSTANCE 0U
+#define BOARD_DEBUG_UART UART0
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetUartClkFreq(0)
+#define BOARD_DEBUG_UART_CLK_ATTACH kSYS_CLK_to_FAST_UART0
+#define BOARD_DEBUG_UART_CLK_DIV kCLOCK_DivUartFast
+#define BOARD_UART_IRQ_HANDLER UART0_IRQHandler
+#define BOARD_UART_IRQ UART0_IRQn
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/* Board led color mapping */
+#define LOGIC_LED_ON 0U
+#define LOGIC_LED_OFF 1U
+
+#ifndef BOARD_LED_AMBER_GPIO
+#define BOARD_LED_AMBER_GPIO GPIO
+#endif
+#ifndef BOARD_LED_AMBER_GPIO_PIN
+#define BOARD_LED_AMBER_GPIO_PIN 40U
+#endif
+
+#ifndef BOARD_LED_YELLOW_GPIO
+#define BOARD_LED_YELLOW_GPIO GPIO
+#endif
+#ifndef BOARD_LED_YELLOW_GPIO_PIN
+#define BOARD_LED_YELLOW_GPIO_PIN 41U
+#endif
+
+#define LED_AMBER_INIT(output) \
+ GPIO_PinInit(BOARD_LED_AMBER_GPIO, BOARD_LED_AMBER_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_AMBER */
+#define LED_AMBER_ON() GPIO_PinClear(BOARD_LED_AMBER_GPIO, BOARD_LED_AMBER_GPIO_PIN) /*!< Turn on target LED_AMBER */
+#define LED_AMBER_OFF() GPIO_PinSet(BOARD_LED_AMBER_GPIO, BOARD_LED_AMBER_GPIO_PIN) /*!< Turn off target LED_AMBER */
+#define LED_AMBER_TOGGLE() \
+ GPIO_PinToggle(BOARD_LED_AMBER_GPIO, BOARD_LED_AMBER_GPIO_PIN) /*!< Toggle on target LED_AMBER */
+
+#define LED_YELLOW_INIT(output) \
+ GPIO_PinInit(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_YELLOW */
+#define LED_YELLOW_ON() \
+ GPIO_PinClear(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_GPIO_PIN) /*!< Turn on target LED_YELLOW */
+#define LED_YELLOW_OFF() \
+ GPIO_PinSet(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_GPIO_PIN) /*!< Turn off target LED_YELLOW */
+#define LED_YELLOW_TOGGLE() \
+ GPIO_PinToggle(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_GPIO_PIN) /*!< Toggle on target LED_YELLOW */
+
+/* Board SW PIN */
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 24U
+#endif
+#define BOARD_SW1_IRQ GPIO_IRQn
+#define BOARD_SW1_IRQ_HANDLER GPIO_IRQHandler
+#define BOARD_SW1_NAME "SW1"
+
+#ifndef BOARD_SW2_GPIO
+#define BOARD_SW2_GPIO GPIO
+#endif
+#ifndef BOARD_SW2_GPIO_PIN
+#define BOARD_SW2_GPIO_PIN 26U
+#endif
+#define BOARD_SW2_IRQ GPIO_IRQn
+#define BOARD_SW2_IRQ_HANDLER GPIO_IRQHandler
+#define BOARD_SW2_NAME "SW2"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+
+/* Only used for mbedtls entropy, implemented in board_hash.c */
+void BOARD_GetHash(uint8_t *buf, uint32_t *len);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/rdmw320_r0/clock_config.c b/boards/rdmw320_r0/clock_config.c
new file mode 100644
index 000000000..a354d11e3
--- /dev/null
+++ b/boards/rdmw320_r0/clock_config.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sfll_config_t g_sfllConfig_BOARD_BootClockRUN = {
+ .sfllSrc = kCLOCK_SFllSrcMainXtal, /* XTAL clock */
+ .refDiv = 0x60U,
+ .fbDiv = 0xFAU,
+ .kvco = 0x1U,
+ .postDiv = 0x0U
+};
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+static void BOARD_DeinitFlashC(void)
+{
+ uint32_t reg = FLASHC->FCCR;
+
+ /* Disable cache */
+ reg &= ~FLASHC_FCCR_CACHE_EN_MASK;
+ FLASHC->FCCR = reg;
+ /* Set CMD_TYPE to exit continuous read mode */
+ reg = (reg & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(0xCU);
+ FLASHC->FCCR = reg ;
+ /* Wait exit done */
+ while ((FLASHC->FCSR & FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK) == 0U)
+ {
+ }
+ /* Clear exit done flag */
+ FLASHC->FCSR = FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK;
+ /* Set pad mux to QSPI */
+ FLASHC->FCCR &= ~FLASHC_FCCR_FLASHC_PAD_EN_MASK;
+}
+
+static void BOARD_InitFlashC(void)
+{
+ uint32_t reg = FLASHC->FCCR;
+
+ /* Set pad mux to FLASHC */
+ reg |= FLASHC_FCCR_FLASHC_PAD_EN_MASK;
+ FLASHC->FCCR = reg;
+
+ /* Set CMD_TYPE to continuous read mode */
+ reg = (reg & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(0x6U);
+ FLASHC->FCCR = reg ;
+ /* Enable cache */
+ reg |= FLASHC_FCCR_CACHE_EN_MASK;
+ FLASHC->FCCR = reg;
+}
+
+void BOARD_BootClockRUN(void)
+{
+ POWER_PowerOnVddioPad(kPOWER_VddIoAon);
+ POWER_PowerOnVddioPad(kPOWER_VddIo0);
+ POWER_PowerOnVddioPad(kPOWER_VddIo1);
+ POWER_PowerOnVddioPad(kPOWER_VddIo2);
+ POWER_PowerOnVddioPad(kPOWER_VddIo3);
+
+ if (BOARD_IS_XIP())
+ {
+ /* Stop flash controller before changing clock */
+ BOARD_DeinitFlashC();
+ }
+ /* Enable RC32M. */
+ CLOCK_EnableClock(kCLOCK_Rc32m);
+ CLOCK_EnableRC32M(false);
+
+ /* Set the PMU clock divider to 1 */
+ CLOCK_SetClkDiv(kCLOCK_DivPmu, 1U);
+
+ /* Set external Xtal frequency to clock driver */
+ CLOCK_SetMainXtalFreq(CLK_MAINXTAL_CLK);
+
+ /* Enable System OSC 38.4M. */
+ CLOCK_EnableRefClk(kCLOCK_RefClk_SYS);
+
+ /* Initialize SFLL to 200M. */
+ CLOCK_InitSFll(&g_sfllConfig_BOARD_BootClockRUN);
+
+ /* Set dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivApb0, 2U);
+ CLOCK_SetClkDiv(kCLOCK_DivApb1, 2U);
+ CLOCK_SetClkDiv(kCLOCK_DivPmu, 4U);
+
+ /* Switch system clock source to SFLL before RC32M calibration */
+ CLOCK_SetSysClkSource(kCLOCK_SysClkSrcSFll);
+
+ CLOCK_SetClkDiv(kCLOCK_DivQspi, 4U);
+
+ /* Calibrate RC32M */
+ CLOCK_CalibrateRC32M(true, 0U);
+ /* RC32M enabled, controller clock can be gated. */
+ CLOCK_DisableClock(kCLOCK_Rc32m);
+
+ /* Reset the PMU clock divider to 1 */
+ CLOCK_SetClkDiv(kCLOCK_DivPmu, 1U);
+
+ if (BOARD_IS_XIP())
+ {
+ /* Restart flash controller for XIP */
+ BOARD_InitFlashC();
+ }
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/boards/rdmw320_r0/clock_config.h b/boards/rdmw320_r0/clock_config.h
new file mode 100644
index 000000000..d2397b9ff
--- /dev/null
+++ b/boards/rdmw320_r0/clock_config.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL_SYS_CLK_HZ 384000000U /*!< Board xtal frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 200000000U /*!< Core clock frequency: 200000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/rdmw320_r0/project_template/board.c b/boards/rdmw320_r0/project_template/board.c
new file mode 100644
index 000000000..9c4f7ed0f
--- /dev/null
+++ b/boards/rdmw320_r0/project_template/board.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_clock.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+void BOARD_InitDebugConsole(void)
+{
+ uint32_t uartClkSrcFreq;
+
+ /* attach FAST clock to UART0 (debug console) */
+ CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+ uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+ DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
diff --git a/boards/rdmw320_r0/project_template/board.h b/boards/rdmw320_r0/project_template/board.h
new file mode 100644
index 000000000..7b7367572
--- /dev/null
+++ b/boards/rdmw320_r0/project_template/board.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "RDMW320-R0"
+
+/*! @brief Macro to judge XIP */
+#define BOARD_IS_XIP() \
+ (((uint32_t)BOARD_InitDebugConsole >= 0x1F000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x20000000U))
+
+/*! @brief The UART to use for debug messages. */
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) UART0
+#define BOARD_DEBUG_UART_INSTANCE 0U
+#define BOARD_DEBUG_UART UART0
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetUartClkFreq(0)
+#define BOARD_DEBUG_UART_CLK_ATTACH kSYS_CLK_to_FAST_UART0
+#define BOARD_DEBUG_UART_CLK_DIV kCLOCK_DivUartFast
+#define BOARD_UART_IRQ_HANDLER UART0_IRQHandler
+#define BOARD_UART_IRQ UART0_IRQn
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+/* Board led color mapping */
+#define LOGIC_LED_ON 0U
+#define LOGIC_LED_OFF 1U
+
+#ifndef BOARD_LED_AMBER_GPIO
+#define BOARD_LED_AMBER_GPIO GPIO
+#endif
+#ifndef BOARD_LED_AMBER_GPIO_PIN
+#define BOARD_LED_AMBER_GPIO_PIN 40U
+#endif
+
+#ifndef BOARD_LED_YELLOW_GPIO
+#define BOARD_LED_YELLOW_GPIO GPIO
+#endif
+#ifndef BOARD_LED_YELLOW_GPIO_PIN
+#define BOARD_LED_YELLOW_GPIO_PIN 41U
+#endif
+
+#define LED_AMBER_INIT(output) \
+ GPIO_PinInit(BOARD_LED_AMBER_GPIO, BOARD_LED_AMBER_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_AMBER */
+#define LED_AMBER_ON() GPIO_PinClear(BOARD_LED_AMBER_GPIO, BOARD_LED_AMBER_GPIO_PIN) /*!< Turn on target LED_AMBER */
+#define LED_AMBER_OFF() GPIO_PinSet(BOARD_LED_AMBER_GPIO, BOARD_LED_AMBER_GPIO_PIN) /*!< Turn off target LED_AMBER */
+#define LED_AMBER_TOGGLE() \
+ GPIO_PinToggle(BOARD_LED_AMBER_GPIO, BOARD_LED_AMBER_GPIO_PIN) /*!< Toggle on target LED_AMBER */
+
+#define LED_YELLOW_INIT(output) \
+ GPIO_PinInit(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_GPIO_PIN, \
+ &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED_YELLOW */
+#define LED_YELLOW_ON() \
+ GPIO_PinClear(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_GPIO_PIN) /*!< Turn on target LED_YELLOW */
+#define LED_YELLOW_OFF() \
+ GPIO_PinSet(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_GPIO_PIN) /*!< Turn off target LED_YELLOW */
+#define LED_YELLOW_TOGGLE() \
+ GPIO_PinToggle(BOARD_LED_YELLOW_GPIO, BOARD_LED_YELLOW_GPIO_PIN) /*!< Toggle on target LED_YELLOW */
+
+/* Board SW PIN */
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 24U
+#endif
+#define BOARD_SW1_IRQ GPIO_IRQn
+#define BOARD_SW1_IRQ_HANDLER GPIO_IRQHandler
+#define BOARD_SW1_NAME "SW1"
+
+#ifndef BOARD_SW2_GPIO
+#define BOARD_SW2_GPIO GPIO
+#endif
+#ifndef BOARD_SW2_GPIO_PIN
+#define BOARD_SW2_GPIO_PIN 26U
+#endif
+#define BOARD_SW2_IRQ GPIO_IRQn
+#define BOARD_SW2_IRQ_HANDLER GPIO_IRQHandler
+#define BOARD_SW2_NAME "SW2"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+void BOARD_InitDebugConsole(void);
+
+/* Only used for mbedtls entropy, implemented in board_hash.c */
+void BOARD_GetHash(uint8_t *buf, uint32_t *len);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/rdmw320_r0/project_template/clock_config.c b/boards/rdmw320_r0/project_template/clock_config.c
new file mode 100644
index 000000000..4599a83b1
--- /dev/null
+++ b/boards/rdmw320_r0/project_template/clock_config.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+#include "board.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const clock_sfll_config_t g_sfllConfig_BOARD_BootClockRUN = {
+ .sfllSrc = kCLOCK_SFllSrcMainXtal, /* XTAL clock */
+ .refDiv = 0x60U,
+ .fbDiv = 0xFAU,
+ .kvco = 0x1U,
+ .postDiv = 0x0U
+};
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+static void BOARD_DeinitFlashC(void)
+{
+ uint32_t reg = FLASHC->FCCR;
+
+ /* Disable cache */
+ reg &= ~FLASHC_FCCR_CACHE_EN_MASK;
+ FLASHC->FCCR = reg;
+ /* Set CMD_TYPE to exit continuous read mode */
+ reg = (reg & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(0xCU);
+ FLASHC->FCCR = reg ;
+ /* Wait exit done */
+ while ((FLASHC->FCSR & FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK) == 0U)
+ {
+ }
+ /* Clear exit done flag */
+ FLASHC->FCSR = FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK;
+ /* Set pad mux to QSPI */
+ FLASHC->FCCR &= ~FLASHC_FCCR_FLASHC_PAD_EN_MASK;
+}
+
+static void BOARD_InitFlashC(void)
+{
+ uint32_t reg = FLASHC->FCCR;
+
+ /* Set pad mux to FLASHC */
+ reg |= FLASHC_FCCR_FLASHC_PAD_EN_MASK;
+ FLASHC->FCCR = reg;
+
+ /* Set CMD_TYPE to continuous read mode */
+ reg = (reg & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(0x6U);
+ FLASHC->FCCR = reg ;
+ /* Enable cache */
+ reg |= FLASHC_FCCR_CACHE_EN_MASK;
+ FLASHC->FCCR = reg;
+}
+
+void BOARD_BootClockRUN(void)
+{
+ POWER_PowerOnVddioPad(kPOWER_VddIoAon);
+ POWER_PowerOnVddioPad(kPOWER_VddIo0);
+ POWER_PowerOnVddioPad(kPOWER_VddIo1);
+ POWER_PowerOnVddioPad(kPOWER_VddIo2);
+ POWER_PowerOnVddioPad(kPOWER_VddIo3);
+
+ if (BOARD_IS_XIP())
+ {
+ /* Stop flash controller before changing clock */
+ BOARD_DeinitFlashC();
+ }
+ /* Enable RC32M. */
+ CLOCK_EnableClock(kCLOCK_Rc32m);
+ CLOCK_EnableRC32M(false);
+
+ /* Set the PMU clock divider to 1 */
+ CLOCK_SetClkDiv(kCLOCK_DivPmu, 1U);
+
+ /* Set external Xtal frequency to clock driver */
+ CLOCK_SetMainXtalFreq(CLK_MAINXTAL_CLK);
+
+ /* Enable System OSC 38.4M. */
+ CLOCK_EnableRefClk(kCLOCK_RefClk_SYS);
+
+ /* Initialize SFLL to 200M. */
+ CLOCK_InitSFll(&g_sfllConfig_BOARD_BootClockRUN);
+
+ /* Set dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivApb0, 2U);
+ CLOCK_SetClkDiv(kCLOCK_DivApb1, 2U);
+ CLOCK_SetClkDiv(kCLOCK_DivPmu, 4U);
+
+ /* Switch system clock source to SFLL before RC32M calibration */
+ CLOCK_SetSysClkSource(kCLOCK_SysClkSrcSFll);
+
+ /* Calibrate RC32M */
+ CLOCK_CalibrateRC32M(true, 0U);
+ /* RC32M enabled, controller clock can be gated. */
+ CLOCK_DisableClock(kCLOCK_Rc32m);
+
+ /* Reset the PMU clock divider to 1 */
+ CLOCK_SetClkDiv(kCLOCK_DivPmu, 1U);
+
+ if (BOARD_IS_XIP())
+ {
+ /* Restart flash controller for XIP */
+ BOARD_InitFlashC();
+ }
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
diff --git a/boards/rdmw320_r0/project_template/clock_config.h b/boards/rdmw320_r0/project_template/clock_config.h
new file mode 100644
index 000000000..d2397b9ff
--- /dev/null
+++ b/boards/rdmw320_r0/project_template/clock_config.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL_SYS_CLK_HZ 384000000U /*!< Board xtal frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 200000000U /*!< Core clock frequency: 200000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/boards/rdmw320_r0/project_template/peripherals.c b/boards/rdmw320_r0/project_template/peripherals.c
new file mode 100644
index 000000000..ade3c7f73
--- /dev/null
+++ b/boards/rdmw320_r0/project_template/peripherals.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2020 NXP.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+ BOARD_InitPeripherals();
+}
diff --git a/boards/rdmw320_r0/project_template/peripherals.h b/boards/rdmw320_r0/project_template/peripherals.h
new file mode 100644
index 000000000..4c8f25acf
--- /dev/null
+++ b/boards/rdmw320_r0/project_template/peripherals.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020 NXP.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/boards/rdmw320_r0/project_template/pin_mux.c b/boards/rdmw320_r0/project_template/pin_mux.c
new file mode 100644
index 000000000..e8518e630
--- /dev/null
+++ b/boards/rdmw320_r0/project_template/pin_mux.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_pinmux.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[cm4] */
+ PINMUX_PinMuxSet(BOARD_UART0_TX_PIN, BOARD_UART0_TX_PIN_FUNCTION_ID | PINMUX_MODE_DEFAULT);
+ PINMUX_PinMuxSet(BOARD_UART0_RX_PIN, BOARD_UART0_RX_PIN_FUNCTION_ID | PINMUX_MODE_DEFAULT);
+}
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/rdmw320_r0/project_template/pin_mux.h b/boards/rdmw320_r0/project_template/pin_mux.h
new file mode 100644
index 000000000..0b66ddcb8
--- /dev/null
+++ b/boards/rdmw320_r0/project_template/pin_mux.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2020 NXP.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+#define BOARD_UART0_TX_PIN 2 /*!< Routed pin */
+#define BOARD_UART0_TX_PIN_FUNCTION_ID PINMUX_GPIO2_UART0_TXD /*!< Pin function id */
+
+#define BOARD_UART0_RX_PIN 3 /*!< Routed pin */
+#define BOARD_UART0_RX_PIN_FUNCTION_ID PINMUX_GPIO3_UART0_RXD /*!< Pin function id */
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void); /*!< Function assigned for the core: Cortex-M4[cm4] */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/components/boot2_utils/boot_flags.c b/components/boot2_utils/boot_flags.c
new file mode 100644
index 000000000..8a7654677
--- /dev/null
+++ b/components/boot2_utils/boot_flags.c
@@ -0,0 +1,82 @@
+/** @file boot_flags.c
+ *
+ * @brief This file provides API for Boot Flags
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#include "boot_flags.h"
+#include "fsl_debug_console.h"
+
+#define boot_l(...) PRINTF("boot", ##__VA_ARGS__)
+
+#define REVID_MASK 0x1FF
+
+/* permanent boot flags storage */
+uint32_t g_boot_flags;
+uint32_t g_prev_version_fw;
+uint32_t g_rst_cause;
+
+void boot_init(void)
+{
+ /* Read boot flags stored by boot2 */
+ g_boot_flags = *BOOT_FLAGS;
+
+ if (g_boot_flags & BOOT_MAIN_FIRMWARE_BAD_CRC)
+ {
+ g_prev_version_fw = 1;
+ }
+
+ g_rst_cause = boot_store_reset_cause();
+}
+
+void boot_report_flags(void)
+{
+ boot_l("Boot Flags: 0x%x", g_boot_flags);
+
+ boot_l(" - Partition Table: %d ", !(!(g_boot_flags & BOOT_PARTITION_TABLE_MASK)));
+
+ boot_l(" - Firmware Partition: %d ", g_boot_flags & BOOT_PARTITION_MASK);
+
+ if (g_boot_flags & BOOT_MAIN_FIRMWARE_BAD_CRC)
+ {
+ boot_l(
+ " - Backup firmware due to CRC error in main"
+ " firmware");
+ }
+ /* Bits of register SYS_CTRL->REV_ID can be described
+ * as follows:
+ * [31:24] Company_ID
+ * [23:20] Foundry
+ * [19:16] Process
+ * [15:14] Project_ID
+ * [8:6] Project_Rev_first_part
+ * [5:3] Project_Rev_second_part
+ * [2:0] Project_Rev_third_part
+ */
+ boot_l("Boot Info:");
+ boot_l(" - Chip revision id: 0x%x", SYS_CTL->REV_ID);
+
+ boot_l("Reset Cause Register: 0x%x", boot_reset_cause());
+ if (boot_reset_cause() & (1 << 5))
+ boot_l(" - Watchdog reset bit is set");
+}
diff --git a/components/boot2_utils/boot_flags.h b/components/boot2_utils/boot_flags.h
new file mode 100644
index 000000000..6900102aa
--- /dev/null
+++ b/components/boot2_utils/boot_flags.h
@@ -0,0 +1,102 @@
+/** @file boot_flags.h
+ *
+ * @brief Boot Flags
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#ifndef __boot_flags_h
+#define __boot_flags_h
+
+#include
+#include "fsl_power.h"
+
+/* BooROM version for A0 chip */
+#define BOOTROM_A0_VERSION 3
+
+/*
+ * Location where the boot flags are stored by the bootloader.
+ * Currently this is stored in NVRAM area after BootROM occupied range.
+ */
+#define BOOT_FLAGS ((volatile uint32_t *)0x480C0024)
+
+/* final location for those boot flags */
+extern uint32_t g_boot_flags;
+extern uint32_t g_prev_version_fw;
+extern uint32_t g_rst_cause;
+
+/* boot flag definitions */
+/* partition number used to boot */
+#define BOOT_PARTITION_MASK 0x03
+/* boot partition table */
+#define BOOT_PARTITION_TABLE_MASK 0x100
+/* partition table1 state */
+#define PARTITION_TABLE1_STATE_MASK 0x200
+/* partition table2 state */
+#define PARTITION_TABLE2_STATE_MASK 0x400
+/* main firmware had errors */
+#define BOOT_MAIN_FIRMWARE_BAD_CRC 0x20
+
+/* secure boot config flags for firmware */
+#define BOOT_SECURE_FW_ENABLE 0x10000
+#define BOOT_SECURE_SIGN_FW 0x20000
+#define BOOT_SECURE_ENCRYPT_FW 0x40000
+
+/*
+ * Bootrom stores some information in initial few bytes of retention ram.
+ * Following is the format used for storing this info.
+ */
+struct bootrom_info
+{
+ uint32_t pm3_entryaddr;
+ uint32_t bootMode;
+ uint32_t powerMode;
+};
+
+extern unsigned long _nvram_start;
+
+static inline int boot_get_partition_no()
+{
+ return g_boot_flags & BOOT_PARTITION_MASK;
+}
+
+static inline int boot_old_fw_version()
+{
+ return g_prev_version_fw;
+}
+
+static inline uint32_t boot_store_reset_cause()
+{
+ uint32_t rst_cause = POWER_GetResetCause();
+ POWER_ClearResetCause(kPOWER_ResetCauseAll);
+ return rst_cause;
+}
+
+static inline uint32_t boot_reset_cause()
+{
+ return g_rst_cause;
+}
+
+void boot_init();
+void boot_report_flags();
+
+#endif
diff --git a/components/boot2_utils/component_boot2_partition.cmake b/components/boot2_utils/component_boot2_partition.cmake
new file mode 100644
index 000000000..81042dafb
--- /dev/null
+++ b/components/boot2_utils/component_boot2_partition.cmake
@@ -0,0 +1,16 @@
+#Description: component_boot2_partition; user_visible: True
+include_guard(GLOBAL)
+message("component_boot2_partition component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/partition.c
+ ${CMAKE_CURRENT_LIST_DIR}/crc32.c
+ ${CMAKE_CURRENT_LIST_DIR}/boot_flags.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/components/boot2_utils/component_boot2_psm.cmake b/components/boot2_utils/component_boot2_psm.cmake
new file mode 100644
index 000000000..1f76c1298
--- /dev/null
+++ b/components/boot2_utils/component_boot2_psm.cmake
@@ -0,0 +1,17 @@
+#Description: component_boot2_psm; user_visible: True
+include_guard(GLOBAL)
+message("component_boot2_psm component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/psm-v2.c
+ ${CMAKE_CURRENT_LIST_DIR}/psm-v2-secure.c
+ ${CMAKE_CURRENT_LIST_DIR}/wmtlv.c
+ ${CMAKE_CURRENT_LIST_DIR}/keystore.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(component_boot2_partition)
diff --git a/components/boot2_utils/crc32.c b/components/boot2_utils/crc32.c
new file mode 100644
index 000000000..8f0d4dbf3
--- /dev/null
+++ b/components/boot2_utils/crc32.c
@@ -0,0 +1,108 @@
+/** @file crc32.c
+ *
+ * @brief This file provides CRC 32 API
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#include
+#include
+
+#define TABLE_SIZE 256
+
+/*
+ * Polynomial used to generate the table:
+ * CRC-32-IEEE 802.3, the polynomial is :
+ * x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1
+ */
+
+const uint32_t crc_table[TABLE_SIZE] = {
+ 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832,
+ 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
+ 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856, 0x646ba8c0, 0xfd62f97a,
+ 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
+ 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3,
+ 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
+ 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab,
+ 0xb6662d3d, 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
+ 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, 0x6b6b51f4,
+ 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
+ 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074,
+ 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
+ 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525,
+ 0x206f85b3, 0xb966d409, 0xce61e49f, 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
+ 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615,
+ 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
+ 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, 0xfed41b76,
+ 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
+ 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c, 0x36034af6,
+ 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
+ 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7,
+ 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
+ 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7,
+ 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
+ 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278,
+ 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
+ 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, 0xbdbdf21c, 0xcabac28a, 0x53b39330,
+ 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
+ 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
+};
+
+/* Software CRC */
+uint32_t soft_crc32(const void *data__, int data_size, uint32_t crc)
+{
+ const uint8_t *data = data__;
+ unsigned int result = crc;
+ unsigned char crc_H8;
+
+ while (data_size--)
+ {
+ crc_H8 = (unsigned char)(result & 0x000000FF);
+ result >>= 8;
+ result ^= crc_table[crc_H8 ^ (*data)];
+ data++;
+ }
+
+ return result;
+}
+
+/* Hardware CRC */
+uint32_t crc32(const void *data__, int data_size, uint32_t crc)
+{
+ const uint8_t *data = data__;
+ uint32_t result;
+
+ result = CRC_Calculate(CRC, data, data_size);
+
+ if (crc && (result == crc))
+ {
+ result = 0;
+ }
+
+ return result;
+}
+
+void crc32_init()
+{
+ CRC_Init(CRC);
+ CRC_SetMode(CRC, kCRC_32BitsIeee);
+}
diff --git a/components/boot2_utils/crc32.h b/components/boot2_utils/crc32.h
new file mode 100644
index 000000000..8f3f6731a
--- /dev/null
+++ b/components/boot2_utils/crc32.h
@@ -0,0 +1,36 @@
+/** @file crc32.h
+ *
+ * @brief CRC Header
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#ifndef __CRC32_H
+#define __CRC32_H
+
+#include
+
+uint32_t soft_crc32(const void *data, int data_size, uint32_t crc);
+uint32_t crc32(const void *data, int data_size, uint32_t crc);
+void crc32_init(void);
+
+#endif
diff --git a/components/boot2_utils/flash_layout.h b/components/boot2_utils/flash_layout.h
new file mode 100644
index 000000000..c6a700f5a
--- /dev/null
+++ b/components/boot2_utils/flash_layout.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+/*! \file flash_layout.h
+ * \brief Flash layout details
+ *
+ * This file presents entire layout of flash including secondary boot-loader,
+ * firmware(including redundant partition), file-system and persistent storage
+ * manager.
+ *
+ * The flash layout defined in this file is used in a consistent fashion
+ * across all of SDK, namely by the flashprog utility, secondary boot loader
+ * (boot2) and Firmware Upgrade code.
+ */
+
+#ifndef _FLASH_LAYOUT_H_
+#define _FLASH_LAYOUT_H_
+
+/** Flash base address */
+#define MW300_FLASH_BASE 0x0
+/** Flash sector size */
+#define MW300_FLASH_SECTOR_SIZE 0x1000 /*!< 4KB */
+
+/** Section: Secondary stage boot-loader with bootrom header
+ * Start: 0x0
+ * Length: 0x4000(16KiB)
+ * Device: Internal Flash
+ */
+#define FL_BOOT2_START (MW300_FLASH_BASE + 0x0)
+#define FL_BOOTROM_H_SIZE (0x400)
+/* Note: Maximum size considering future requirements */
+#define FL_BOOT2_BLOCK_SIZE (MW300_FLASH_SECTOR_SIZE * 4)
+#define FL_BOOT2_BLOCK_END (FL_BOOT2_START + FL_BOOT2_BLOCK_SIZE)
+#define FL_BOOT2_DEV FL_INT
+
+/** Section: Partition table 1
+ * Start: 0x4000
+ * Length: 0x1000(4KiB)
+ * Device: Internal Flash
+ */
+#define FL_PART_SIZE (MW300_FLASH_SECTOR_SIZE)
+#define FL_PART1_START FL_BOOT2_BLOCK_END
+#define FL_PART1_TABLE_END (FL_PART1_START + FL_PART_SIZE)
+#define FL_PART_DEV FL_INT
+
+/** Section: Partition table 2
+ * Start: 0x5000
+ * Length: 0x1000(4KiB)
+ * Device: Internal Flash
+ */
+#define FL_PART2_START FL_PART1_TABLE_END
+#define FL_PART2_END (FL_PART2_START + FL_PART_SIZE)
+
+#endif /* ! _FLASH_LAYOUT_H_ */
diff --git a/components/boot2_utils/keystore.c b/components/boot2_utils/keystore.c
new file mode 100644
index 000000000..1e0927d78
--- /dev/null
+++ b/components/boot2_utils/keystore.c
@@ -0,0 +1,104 @@
+/** @file keystore.c
+ *
+ * @brief This file provides Key Store API
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#include
+#include
+#include
+
+#define KS_PRESENT 1
+#define KS_ABSENT -1
+#define KS_UNINIT 0
+
+static int8_t ks_present;
+static uint8_t *keystore_addr = (uint8_t *)SB_KEYSTORE_ADDR;
+
+void keystore_validate()
+{
+ if (ks_present != KS_UNINIT)
+ return;
+
+ crc32_init();
+
+ if (tlv_store_validate((uint8_t *)SB_KEYSTORE_ADDR, BOOT2_KEYSTORE, crc32) == TLV_SUCCESS)
+ ks_present = KS_PRESENT;
+ else
+ ks_present = KS_ABSENT;
+
+ return;
+}
+
+int keystore_get(uint8_t type, uint16_t len, uint8_t *value)
+{
+ keystore_validate();
+ if (ks_present != KS_PRESENT)
+ return ERR_TLV_NOT_FOUND;
+
+ return tlv_store_get((uint8_t *)SB_KEYSTORE_ADDR, type, len, value);
+}
+
+int keystore_get_ref(uint8_t type, uint16_t *plen, const uint8_t **pvalue)
+{
+ keystore_validate();
+ if (ks_present != KS_PRESENT)
+ return ERR_TLV_NOT_FOUND;
+
+ return tlv_store_get_ref((uint8_t *)SB_KEYSTORE_ADDR, type, plen, pvalue);
+}
+
+void keystore_iterate_start()
+{
+ keystore_addr = (uint8_t *)SB_KEYSTORE_ADDR;
+}
+
+int keystore_iterate(uint8_t *ptype, uint16_t len, uint8_t *value)
+{
+ int ret;
+
+ keystore_validate();
+ if (ks_present != KS_PRESENT)
+ return ERR_TLV_NOT_FOUND;
+
+ ret = tlv_store_iterate(keystore_addr, ptype, len, value);
+ if (ret != ERR_TLV_NOT_FOUND)
+ keystore_addr = NULL;
+
+ return ret;
+}
+
+int keystore_iterate_ref(uint8_t *ptype, uint16_t *plen, const uint8_t **pvalue)
+{
+ int ret;
+
+ keystore_validate();
+ if (ks_present != KS_PRESENT)
+ return ERR_TLV_NOT_FOUND;
+
+ ret = tlv_store_iterate_ref(keystore_addr, ptype, plen, pvalue);
+ if (ret != ERR_TLV_NOT_FOUND)
+ keystore_addr = NULL;
+
+ return ret;
+}
diff --git a/components/boot2_utils/keystore.h b/components/boot2_utils/keystore.h
new file mode 100644
index 000000000..28358fb22
--- /dev/null
+++ b/components/boot2_utils/keystore.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+/*! @file keystore.h
+ * @brief Keystore access module (This module is available only for MW30X
+ * devices)
+ *
+ * Keystore is a component of bootloader that is passed by it to application
+ * firmware while booting. Usually, bootloader will be encrypted and hence
+ * keystore acts as read-only secure storage on flash to store important
+ * information such as encryption/decryption keys for secure PSM or any
+ * application specific secure information. Bootloader passes on this
+ * keystore to application firmware in decrypted form in RAM.
+ *
+ * Keystore is basically a packed array of TLV (Type-Length-Value) triplets.
+ * There is a header at the start of keystore which is used to validate and
+ * traverse keystore. Header is followed by one or more TLV triplet, each of
+ * different type and different lengths. TLVs of keystore are divided into two
+ * categories, TLV Types 0-95 are reserved for secure boot process and TLV Types
+ * 96-254 are reserved for applications for custom use, including that for
+ * secure PSM.
+ *
+ * This module provides a simple interface to access keystore from application
+ * firmware.
+ *
+ * @note Keystore is a read-only storage and cannot be updated in memory or
+ * on flash by application firmware. It can only be done by flashing new
+ * bootloader with updated keystore.
+ *
+ * @section keystore_usage Usage
+ *
+ * -# Use keystore_get to get a copy of TLV value stored in keystore
+ * -# Use keystore_get_ref to get in-place pointer to TLV value in keystore
+ * -# To iterate through all TLV's stored in keystore
+ * @code
+ * uint8_t val[256];
+ * uint8_t type;
+ * uint16_t len;
+ * int ret;
+ *
+ * keystore_iterate_start();
+ * while(1) {
+ * ret = keystore_iterate(&type, sizeof(val), val);
+ * if (ret == ERR_TLV_NOT_FOUND)
+ * break;
+ * if (ret == ERR_TLV_BAD_BUF_LEN) {
+ * log("Use_larger_val_buffer");
+ * break;
+ * }
+ * len = ret;
+ * use_tlv(type, len, val);
+ * }
+ * @endcode
+ */
+
+#ifndef __KEYSTORE_H__
+#define __KEYSTORE_H__
+
+#include
+
+/** Predefined TLV key types for keystore. Note that TLV types must be unique
+ * throughout the system to avoid any confusion.
+ * Applications must use a unique integer in the range KEY_APP_DATA_START
+ * and KEY_APP_DATA_END as TLV type for its use.
+ */
+enum ks_tlv_type
+{
+ /* Start of Reserved TLV types. Applications must not modify them */
+ /* Boot2 key types */
+ KEY_BOOT2_SIGNING_ALGO = 0,
+ KEY_BOOT2_HASH_ALGO,
+ KEY_BOOT2_ENCRYPT_ALGO,
+ KEY_BOOT2_PRIVATE_KEY,
+ KEY_BOOT2_PUBLIC_KEY,
+ KEY_BOOT2_ENCRYPT_KEY,
+ KEY_BOOT2_DECRYPT_KEY,
+ KEY_BOOT2_NONCE,
+ KEY_BOOT2_LOAD_ADDR,
+ KEY_BOOT2_ENTRY_ADDR,
+
+ /* OTP key types */
+ KEY_OTP_JTAG_ENABLE = 24,
+ KEY_OTP_UART_USB_BOOT_ENABLE,
+ KEY_OTP_USER_DATA,
+
+ /* Firmware key types */
+ KEY_FW_SIGNING_ALGO = 32,
+ KEY_FW_HASH_ALGO,
+ KEY_FW_ENCRYPT_ALGO,
+ KEY_FW_PRIVATE_KEY,
+ KEY_FW_PUBLIC_KEY,
+ KEY_FW_ENCRYPT_KEY,
+ KEY_FW_DECRYPT_KEY,
+ KEY_FW_NONCE,
+ KEY_FW_IMAGE_LEN,
+
+ /* Firmware Image Header key types */
+ KEY_FW_MIC = 64,
+ KEY_FW_SIGNATURE,
+
+ /* End of Reserved TLV types */
+
+ /** Application specific TLV type must be greater than or equal to this
+ * value (= 96) */
+ KEY_APP_DATA_START = 96,
+
+ /* PSMv2 */
+ KEY_PSM_ENCRYPT_KEY = 97,
+ KEY_PSM_NONCE = 98,
+ /** Application specific TLV type must be less than or equal to this
+ * value (= 254)*/
+ KEY_APP_DATA_END = 254,
+
+ /* Filler or padding data */
+ KEY_FILLER = 255
+};
+
+/** This function retrives a TLV from keystore.
+ *
+ * @param[in] type TLV type to retrieve. Refer to enum \ref ks_tlv_type
+ * for pre-defined values
+ * @param[in] len Length of the buffer in which to copy TLV value
+ * @param[out] value Buffer in which to copy TLV value. Can be NULL
+ * to retrive the the length of TLV value
+ *
+ * @return Length of TLV value if TLV type found (can be 0)
+ * @return ERR_TLV_BAD_BUF_LEN if buffer length is smaller than TLV value size
+ * @return ERR_TLV_NOT_FOUND if TLV type not found
+ */
+int keystore_get(uint8_t type, uint16_t len, uint8_t *value);
+
+/** This function retrives a TLV from keystore. Unlike keystore_get()
+ * this function returns reference of TLV value, rather than copy into
+ * a separate buffer.
+ *
+ * @note Application must not modify this TLV value.
+ *
+ * @param[in] type TLV type to retrieve. Refer to enum \ref ks_tlv_type
+ * for pre-defined values
+ * @param[out] plen Length of TLV value (can be 0)
+ * @param[out] pvalue Pointer within keystore to TLV value of size *plen.
+ * Can be NULL to retrive the the length of TLV value
+ *
+ * @return Length of TLV value if TLV type found
+ * @return ERR_TLV_NOT_FOUND if TLV type not found
+ */
+int keystore_get_ref(uint8_t type, uint16_t *plen, const uint8_t **pvalue);
+
+/** This function enables to iterate over each TLV stored in keystore from
+ * beginning. This must be called once before keystore_iterate() or
+ * keystore_iterate_ref().
+ *
+ * @note This function also enables to restart iteration from beginning.
+ */
+void keystore_iterate_start();
+
+/** This function retrives each TLV from keystore in the sequence in which
+ * they are stored. TLV is copied into the buffer supplied.
+ *
+ * @pre keystore_iterate_start()
+ *
+ * @param[out] ptype TLV type retrived. Refer to enum \ref ks_tlv_type
+ * for pre-defined values
+ * @param[in] len Length of the buffer in which to copy TLV value
+ * @param[out] value Buffer in which to copy TLV value
+ *
+ * @return Length of TLV value if TLV type found
+ * @return ERR_TLV_BAD_BUF_LEN if buffer length is smaller than TLV value size
+ * @return ERR_TLV_NOT_FOUND if end of keystore reached
+ */
+int keystore_iterate(uint8_t *ptype, uint16_t len, uint8_t *value);
+
+/** This function is keystore_get_ref() equivalent of keystore_iterate().
+ * TLV value is returned as reference into keystore rather than separate buffer
+ * copy.
+ *
+ * @note Application must not modify this TLV value.
+ *
+ * @pre keystore_iterate_start()
+ *
+ * @param[out] ptype TLV type retrieved. Refer to enum \ref ks_tlv_type
+ * for pre-defined values
+ * @param[out] plen Length of TLV value (can be 0)
+ * @param[out] pvalue Pointer within keystore to TLV value of size *plen
+ *
+ * @return Length of TLV value if TLV type found
+ * @return ERR_TLV_NOT_FOUND if end of keystore reached
+ */
+int keystore_iterate_ref(uint8_t *ptype, uint16_t *plen, const uint8_t **pvalue);
+
+#endif /* __KEYSTORE_H__ */
diff --git a/components/boot2_utils/partition.c b/components/boot2_utils/partition.c
new file mode 100644
index 000000000..ece7a1d10
--- /dev/null
+++ b/components/boot2_utils/partition.c
@@ -0,0 +1,297 @@
+/** @file partition.c
+ *
+ * @brief This file provides Flash Partition Manager
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#include "crc32.h"
+#include "boot_flags.h"
+#include "partition.h"
+#include "flash_layout.h"
+#include "mflash_drv.h"
+#include "fsl_debug_console.h"
+
+struct partition_table g_flash_table;
+struct partition_entry g_flash_parts[MAX_FL_COMP];
+static uint32_t g_active_part_addr;
+
+static inline uint32_t part_get_table_addr_from_id(bool part_id)
+{
+ return (part_id == 0) ? FL_PART1_START : FL_PART2_START;
+}
+
+static inline uint32_t part_get_passive_table_addr()
+{
+ return (g_active_part_addr == FL_PART1_START) ? FL_PART2_START : FL_PART1_START;
+}
+
+static int part_read_layout()
+{
+ int read_size, ret;
+ uint32_t crc;
+ uint32_t part_addr;
+
+ part_addr = g_active_part_addr;
+ crc32_init();
+
+ ret = mflash_drv_read(part_addr, (uint32_t *)&g_flash_table, sizeof(struct partition_table));
+ if (kStatus_Success != ret)
+ {
+ assert(false);
+ }
+
+ crc = crc32(&g_flash_table, sizeof(g_flash_table), 0);
+ if (crc != 0)
+ {
+ PRINTF("CRC mismatch");
+ return -WM_E_CRC;
+ }
+
+ if (g_flash_table.magic != PARTITION_TABLE_MAGIC)
+ {
+ PRINTF("magic number mismatch");
+ return -WM_FAIL;
+ }
+ if (g_flash_table.version != PARTITION_TABLE_VERSION)
+ {
+ PRINTF("Partition table version mismatch");
+ return -WM_FAIL;
+ }
+ part_addr += sizeof(struct partition_table);
+
+ if (g_flash_table.partition_entries_no > MAX_FL_COMP)
+ {
+ PRINTF(
+ "Only %d partition entries are supported."
+ " Current = %d. Truncating ...",
+ MAX_FL_COMP, g_flash_table.partition_entries_no);
+ g_flash_table.partition_entries_no = MAX_FL_COMP;
+ }
+
+ read_size = g_flash_table.partition_entries_no * sizeof(struct partition_entry);
+ ret = mflash_drv_read(part_addr, (uint32_t *)g_flash_parts, read_size);
+ if (kStatus_Success != ret)
+ {
+ assert(false);
+ }
+
+ return WM_SUCCESS;
+}
+
+int part_init(void)
+{
+ static bool part_init_done;
+ bool act_part_id;
+
+ if (part_init_done == true)
+ return WM_SUCCESS;
+
+ if (((g_boot_flags & PARTITION_TABLE1_STATE_MASK) != 0U) || ((g_boot_flags & PARTITION_TABLE2_STATE_MASK) != 0U))
+ {
+ /* Not valid boot flags, use part 0. */
+ act_part_id = 0U;
+ }
+ else
+ {
+ /* Get active partition table address as setup by Boot2 */
+ act_part_id = !(!(g_boot_flags & BOOT_PARTITION_TABLE_MASK));
+ }
+
+ g_active_part_addr = part_get_table_addr_from_id(act_part_id);
+ part_init_done = true;
+ return part_read_layout();
+}
+
+int part_write_layout(void)
+{
+ /* Get and update passive partition table */
+ uint32_t part_addr = part_get_passive_table_addr();
+ uint32_t crc;
+ int write_size;
+
+ mflash_drv_erase(part_addr, FL_PART_SIZE);
+
+ /* Increment active partition table generation level this will get
+ * written to passive address */
+ ++g_flash_table.gen_level;
+
+ /* Update checksum with updated generation level */
+ crc = crc32((uint8_t *)&g_flash_table, sizeof(struct partition_table) - 4, 0);
+ g_flash_table.crc = crc;
+
+ mflash_drv_write(part_addr, (uint32_t *)&g_flash_table, sizeof(struct partition_table));
+
+ part_addr += sizeof(struct partition_table);
+
+ if (g_flash_table.partition_entries_no > MAX_FL_COMP)
+ {
+ PRINTF(
+ "Only %d partition entries are supported."
+ "Truncating ...",
+ MAX_FL_COMP);
+ g_flash_table.partition_entries_no = MAX_FL_COMP;
+ }
+
+ write_size = g_flash_table.partition_entries_no * sizeof(struct partition_entry);
+ mflash_drv_write(part_addr, (uint32_t *)g_flash_parts, write_size);
+ part_addr += write_size;
+
+ crc = crc32((uint8_t *)g_flash_parts, write_size, 0);
+ mflash_drv_write(part_addr, (uint32_t *)&crc, sizeof(crc));
+
+ return 0;
+}
+
+void part_to_flash_desc(struct partition_entry *p, flash_desc_t *f)
+{
+ f->fl_dev = p->device;
+ f->fl_start = p->start;
+ f->fl_size = p->size;
+}
+
+struct partition_entry *part_get_layout_by_id(enum flash_comp comp, short *start_index)
+{
+ int i = 0;
+
+ if (start_index)
+ i = *start_index;
+
+ for (; i < g_flash_table.partition_entries_no; i++)
+ {
+ if (g_flash_parts[i].type == comp)
+ {
+ if (start_index)
+ *start_index = i + 1;
+ return &g_flash_parts[i];
+ }
+ }
+
+ return NULL;
+}
+
+struct partition_entry *part_get_layout_by_name(const char *name, short *start_index)
+{
+ int i = 0;
+
+ if (start_index)
+ i = *start_index;
+
+ for (; i < g_flash_table.partition_entries_no; i++)
+ {
+ if (!strcmp(g_flash_parts[i].name, name))
+ {
+ if (start_index)
+ *start_index = i + 1;
+ return &g_flash_parts[i];
+ }
+ }
+
+ return NULL;
+}
+
+struct partition_entry *part_get_active_partition(struct partition_entry *p1, struct partition_entry *p2)
+{
+ /* Somehow there aren't two partition defined for this */
+ if (!p1 || !p2)
+ return NULL;
+
+ return p1->gen_level >= p2->gen_level ? p1 : p2;
+}
+
+struct partition_entry *part_get_active_partition_by_name(const char *name)
+{
+ short index = 0;
+ struct partition_entry *p1 = part_get_layout_by_name(name, &index);
+ struct partition_entry *p2 = part_get_layout_by_name(name, &index);
+
+ return part_get_active_partition(p1, p2);
+}
+
+struct partition_entry *part_get_passive_partition(struct partition_entry *p1, struct partition_entry *p2)
+{
+ /* Somehow there aren't two partition defined for this */
+ if (!p1 || !p2)
+ return NULL;
+
+ return p1->gen_level < p2->gen_level ? p1 : p2;
+}
+
+struct partition_entry *part_get_passive_partition_by_name(const char *name)
+{
+ short index = 0;
+ struct partition_entry *p1 = part_get_layout_by_name(name, &index);
+ struct partition_entry *p2 = part_get_layout_by_name(name, &index);
+
+ return part_get_passive_partition(p1, p2);
+}
+
+static bool part_match(struct partition_entry *p1, struct partition_entry *p2)
+{
+ if (p1->type == p2->type && p1->device == p2->device && p1->start == p2->start && p1->size == p2->size)
+ return true;
+
+ return false;
+}
+
+int part_set_active_partition(struct partition_entry *p)
+{
+ short index = 0;
+ struct partition_entry *p1 = part_get_layout_by_name(p->name, &index);
+ struct partition_entry *p2 = part_get_layout_by_name(p->name, &index);
+
+ /* Somehow there aren't two partition defined for this */
+ if (!p1 || !p2)
+ return -WM_E_INVAL;
+
+ if (part_match(p1, p) == true)
+ p1->gen_level = p2->gen_level + 1;
+ else if (part_match(p2, p) == true)
+ p2->gen_level = p1->gen_level + 1;
+ else
+ return -WM_E_INVAL;
+
+ part_write_layout();
+ return WM_SUCCESS;
+}
+
+bool part_is_flash_desc_within_one_partition(flash_desc_t *f)
+{
+ int i;
+ uint32_t start = f->fl_start;
+ uint32_t end = f->fl_start + f->fl_size;
+
+ if (start >= end)
+ {
+ return false;
+ }
+
+ for (i = 0; i < g_flash_table.partition_entries_no; i++)
+ {
+ if ((start >= g_flash_parts[i].start) && (end <= (g_flash_parts[i].start + g_flash_parts[i].size)))
+ {
+ return true;
+ }
+ }
+
+ return false;
+}
diff --git a/components/boot2_utils/partition.h b/components/boot2_utils/partition.h
new file mode 100644
index 000000000..a07ee4966
--- /dev/null
+++ b/components/boot2_utils/partition.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+/*! \file partition.h
+ * \brief Partition Management
+ *
+ * This defines functions for managing the flash partitions.
+ *
+ * \section part_usage Usage
+ *
+ * Applications can define and use their own flash layout using the flashprog
+ * tool. Each partition in the layout has a name, type, start address and a
+ * size associated with it.
+ * Applications can use the part_get_layout_by_name() or part_get_layout_by_id()
+ * functions to retrieve pointers to the partition entry. This partition entry
+ * can be converted to a flash descriptor using the part_to_flash_desc()
+ * function. All components that use the flash accept the flash descriptor to
+ * recognize what portion of the flash they use.
+ *
+ * Additionally, the partition entries store information about active-passive
+ * upgrades. Applications can define their own components in the flash in an
+ * active-passive manner. Applications can then retrieve the active component
+ * using the part_get_active_partition() API. If after an upgrade happens the
+ * partitions need to be toggled then the part_get_active_partition() API is
+ * used.
+ *
+ *
+ */
+
+#ifndef _PARTITION_H_
+#define _PARTITION_H_
+
+#include
+#include
+
+#define MAX_FL_COMP CONFIG_FLASH_PARTITION_COUNT
+#define MAX_NAME 8
+
+/** Partition Table */
+struct partition_table
+{
+#define PARTITION_TABLE_MAGIC (('W' << 0) | ('M' << 8) | ('P' << 16) | ('T' << 24))
+ /** The magic identifying the start of the partition table */
+ uint32_t magic;
+#define PARTITION_TABLE_VERSION 1
+ /** The version number of this partition table */
+ uint16_t version;
+ /** The number of partition entries that follow this */
+ uint16_t partition_entries_no;
+ /** Generation level */
+ uint32_t gen_level;
+ /** The CRC of all the above components */
+ uint32_t crc;
+};
+
+/** Partition Entry */
+struct partition_entry
+{
+ /** The type of the flash component */
+ uint8_t type;
+ /** The device id, internal flash is always id 0 */
+ uint8_t device;
+ /** A descriptive component name */
+ char name[MAX_NAME];
+ /** Start address on the given device */
+ uint32_t start;
+ /** Size on the given device */
+ uint32_t size;
+ /** Generation level */
+ uint32_t gen_level;
+};
+
+/** The various components in a flash layout */
+enum flash_comp
+{
+ /** The secondary stage boot loader to assist firmware bootup */
+ FC_COMP_BOOT2 = 0,
+ /** The firmware image. There can be a maximum of two firmware
+ * components available in a flash layout. These will be used in an
+ * active-passive mode if rfget module is enabled.
+ */
+ FC_COMP_FW,
+ /** The wlan firmware image. There can be one wlan firmware image in the
+ * system. The contents of this location would be downloaded to the WLAN
+ * chip.
+ */
+ FC_COMP_WLAN_FW,
+ /** The FTFS image. */
+ FC_COMP_FTFS,
+ /** The PSM data */
+ FC_COMP_PSM,
+ /** Application Specific component */
+ FC_COMP_USER_APP,
+ /** The BT firmware image if external BT/BLE chip is used */
+ FC_COMP_BT_FW,
+};
+
+/** The flash descriptor
+ *
+ * All components that work with flash refer to the flash descriptor. The flash
+ * descriptor captures the details of the component resident in flash.
+ */
+typedef struct flash_desc
+{
+ /** The flash device */
+ uint8_t fl_dev;
+ /** The start address on flash */
+ uint32_t fl_start;
+ /** The size on flash */
+ uint32_t fl_size;
+} flash_desc_t;
+
+/** Initialize the partitioning module
+ *
+ * \return WM_SUCCESS on success or error code
+ */
+int part_init(void);
+
+/** Update the partitioning table
+ *
+ * \return WM_SUCCESS on success or error code
+ */
+int part_write_layout(void);
+
+/** Convert from partition to flash_descriptor
+ *
+ * All the components that own a portion of flash in the SDK use the flash
+ * descriptor function to identify this portion. This function converts a
+ * partition_entry into a corresponding flash descriptor that can be passed to
+ * these modules.
+ *
+ * \param[in] p a pointer to a partition entry
+ * \param[out] f a pointer to a flash descriptor
+ */
+void part_to_flash_desc(struct partition_entry *p, flash_desc_t *f);
+
+/** Get partition entry by ID
+ *
+ * Retrieve the pointer to a partition entry using an ID. This function can be
+ * called to repetitively to retrieve more entries of the same type. The value
+ * of start_index is modified by the function so that search starts from this
+ * index in the next call.
+ *
+ * \param [in] comp the flash component to search for
+ * \param [in,out] start_index the start index for the search. The first call to
+ * this function should always have a start index of 0.
+ *
+ * \return a pointer to a partition entry on success, null otherwise.
+ */
+struct partition_entry *part_get_layout_by_id(enum flash_comp comp, short *start_index);
+
+/** Get partition entry by name
+ *
+ * Retrieve the pointer to a partition entry using a name. This function can be
+ * called to repetitively to retrieve more entries of the same type. The value
+ * of start_index is modified by the function so that search starts from this
+ * index in the next call.
+ *
+ * \param [in] name the flash component's name as mentioned in the layout.
+ * \param [in,out] start_index the start index for the search. The first call to
+ * this function should always have a start index of 0.
+ *
+ * \return a pointer to a partition entry on success, null otherwise.
+ */
+struct partition_entry *part_get_layout_by_name(const char *name, short *start_index);
+
+struct partition_entry *part_get_active_partition_by_name(const char *name);
+struct partition_entry *part_get_passive_partition_by_name(const char *name);
+
+/** Find the active partition
+ *
+ * Given two partition entries that are upgrade buddies (that is, have the same
+ * friendly name), this function returns the partition that is currently marked
+ * as active.
+ * \param[in] p1 Pointer to a partition entry
+ * \param[in] p2 Pointer to the upgrade buddy for the first partition entry
+ *
+ * \return a pointer to the active partition entry on success, null otherwise.
+ */
+struct partition_entry *part_get_active_partition(struct partition_entry *p1, struct partition_entry *p2);
+
+/** Set active partition
+ *
+ * Given a pointer to a currently passive partition entry, this function marks
+ * this partition entry as active.
+ *
+ * \param[in] p Pointer to partition entry object
+ *
+ * \return -WM_E_INVAL if invalid parameter.
+ * \return WM_SUCCESS if operation successful.
+ */
+int part_set_active_partition(struct partition_entry *p);
+
+static inline int part_get_desc_from_id(enum flash_comp comp, flash_desc_t *fl)
+{
+ if (!fl)
+ return -WM_E_INVAL;
+
+ int rv = part_init();
+ if (rv != 0)
+ return rv;
+
+ struct partition_entry *p = part_get_layout_by_id(comp, NULL);
+ if (!p)
+ return -WM_FAIL;
+
+ part_to_flash_desc(p, fl);
+
+ return WM_SUCCESS;
+}
+
+/* Check if the flash descriptor is within a partition in partition table.
+ *
+ * When return true, the input flash_desc_t 'f' can be either a subset of
+ * a partition's flash space or exactly the same as this partition flash
+ * space itself.
+ *
+ * \param[in] f Pointer to a flash descriptor for a flash space range.
+ *
+ * \return true if 'f' is part of an existing partition flash space.
+ * \return false if not.
+ */
+bool part_is_flash_desc_within_one_partition(flash_desc_t *f);
+
+#endif /* _PARTITION_H_ */
diff --git a/components/boot2_utils/psm-internal.h b/components/boot2_utils/psm-internal.h
new file mode 100644
index 000000000..6740fee96
--- /dev/null
+++ b/components/boot2_utils/psm-internal.h
@@ -0,0 +1,101 @@
+/** @file psm-internal.h
+ *
+ * @brief PSM Internal Header
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#ifndef __PSM_INTERNAL_H__
+#define __PSM_INTERNAL_H__
+
+/* #define CONFIG_PSM_INIT_SCAN_DEBUG */
+/* #define CONFIG_PSM_EXTRA_DEBUG */
+/* #define CONFIG_PSM_FUNC_DEBUG */
+/* #define CONFIG_PSM_INDEXING_DEBUG */
+/* #define CONFIG_PSM_LOWLEVEL_FLASH_OPR_DEBUG */
+/* #define CONFIG_PSM_LOCKS_DEBUG */
+
+#include
+
+#ifdef CONFIG_PSM_INIT_SCAN_DEBUG
+#define psm_isc(...) wmlog("psm-isc", ##__VA_ARGS__)
+#else
+#define psm_isc(...)
+#endif
+
+#define psm_e(...) wmlog_e("psm", ##__VA_ARGS__)
+#define psm_w(...) wmlog_w("psm", ##__VA_ARGS__)
+#ifdef CONFIG_PSM_DEBUG
+#define psm_d(...) wmlog("psm", ##__VA_ARGS__)
+#else
+#define psm_d(...)
+#endif /* ! CONFIG_PSM_DEBUG */
+#ifdef CONFIG_PSM_EXTRA_DEBUG
+#define psm_ed(...) wmlog("psm-ed", ##__VA_ARGS__)
+#else
+#define psm_ed(...)
+#endif /* ! CONFIG_PSM_EXTRA_DEBUG */
+#ifdef CONFIG_PSM_INDEXING_DEBUG
+#define psm_i(...) wmlog("psm-i", ##__VA_ARGS__)
+#else
+#define psm_i(...)
+#endif /* ! CONFIG_PSM_INDEXING_DEBUG */
+#ifdef CONFIG_PSM_LOWLEVEL_FLASH_OPR_DEBUG
+#define psm_ll(...) wmlog("psm-ll", ##__VA_ARGS__)
+#else
+#define psm_ll(...)
+#endif /* ! CONFIG_PSM_LOWLEVEL_FLASH_OPR_DEBUG */
+
+#ifdef CONFIG_PSM_FUNC_DEBUG
+#define psm_entry(_fmt_, ...) wmprintf("######## > %s (" _fmt_ ") ####\n\r", __func__, ##__VA_ARGS__)
+#define psm_entry_i(...) wmlog_entry(__VA_ARGS__)
+#else
+#define psm_entry(...)
+#define psm_entry_i(...)
+#endif /* ! CONFIG_PSM_DEBUG */
+
+typedef enum
+{
+ PSM_EVENT_READ,
+ PSM_EVENT_WRITE,
+ PSM_EVENT_ERASE,
+ PSM_EVENT_COMPACTION,
+} psm_event_t;
+
+typedef enum
+{
+ PSM_COMPACTION_1,
+ PSM_COMPACTION_2,
+ PSM_COMPACTION_3,
+ PSM_COMPACTION_4,
+ PSM_COMPACTION_5,
+ PSM_COMPACTION_6,
+ PSM_COMPACTION_7,
+ PSM_COMPACTION_8,
+ PSM_COMPACTION_9,
+ PSM_COMPACTION_10,
+ PSM_COMPACTION_MAX,
+} psm_compaction_evt_t;
+
+typedef void (*psm_event_callback)(psm_event_t event, void *data, void *data1);
+
+int psm_register_event_callback(psm_event_callback cb);
+
+#endif /* __PSM_INTERNAL_H__ */
diff --git a/components/boot2_utils/psm-v2-secure.c b/components/boot2_utils/psm-v2-secure.c
new file mode 100644
index 000000000..a7268a8e6
--- /dev/null
+++ b/components/boot2_utils/psm-v2-secure.c
@@ -0,0 +1,218 @@
+/** @file psm-v2-secure.c
+ *
+ * @brief Persistent storage manager version 2
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#ifdef CONFIG_SECURE_PSM
+
+#include
+#include "psm-v2-secure.h"
+#include
+#include "psm-internal.h"
+#include "wm_os.h"
+#include "fsl_aes.h"
+
+/*
+ * To encrypt (and decrypt) for each PSM object the "name + value"
+ * together is considered as a single unit. 'resetkey' function is called at
+ * the start of enc/dec operation for every object.
+ *
+ * Note that IV/nonce will be repeated for each PSM object. As of now each
+ * object encryption starts will same IV and key.
+ */
+
+typedef struct
+{
+ bool is_key_copied;
+ const uint8_t *key;
+ const uint8_t *iv;
+ uint16_t key_sz;
+ uint16_t iv_sz;
+ /* CTR context */
+ uint8_t nonce[AES_BLOCK_SIZE];
+ uint8_t streamBlock[AES_BLOCK_SIZE];
+ size_t offset;
+} sec_data_t;
+
+static int psm_keystore_get_data(sec_data_t *sec_data)
+{
+ /* get encryption key & key_size from keystore */
+ psm_d("Using secure keystore");
+ int rv = keystore_get_ref(KEY_PSM_ENCRYPT_KEY, &sec_data->key_sz, &sec_data->key);
+ if (rv == ERR_TLV_NOT_FOUND)
+ {
+ psm_e(
+ "psm: Could not read key key_size from keystore. "
+ "Please flash correct boot2");
+ return -WM_E_NOENT;
+ }
+
+ /* get nonce from keystore */
+ rv = keystore_get_ref(KEY_PSM_NONCE, &sec_data->iv_sz, &sec_data->iv);
+ if (rv == ERR_TLV_NOT_FOUND)
+ {
+ psm_e("psm: Could not read nonce");
+ return -WM_E_NOENT;
+ }
+
+ return WM_SUCCESS;
+}
+
+int psm_security_init(psm_sec_hnd_t *sec_handle)
+{
+ sec_data_t *sec_data = os_mem_calloc(sizeof(sec_data_t));
+ if (!sec_data)
+ return -WM_E_NOMEM;
+
+ int rv = psm_keystore_get_data(sec_data);
+ if (rv != WM_SUCCESS)
+ {
+ os_mem_free(sec_data);
+ return rv;
+ }
+
+ sec_data->is_key_copied = false;
+
+ *sec_handle = (psm_sec_hnd_t)sec_data;
+ return WM_SUCCESS;
+}
+
+int psm_security_init_with_key(psm_sec_hnd_t *sec_handle, psm_cfg_t *psm_cfg)
+{
+ /* Check if psm_cfg provides a key */
+ if ((psm_cfg->key == NULL) || (psm_cfg->iv == NULL) || (psm_cfg->key_sz == 0) || (psm_cfg->iv_sz == 0))
+ {
+ return -WM_E_INVAL;
+ }
+
+ sec_data_t *sec_data = os_mem_calloc(sizeof(sec_data_t));
+ if (!sec_data)
+ {
+ return -WM_E_NOMEM;
+ }
+
+ uint8_t *key = os_mem_calloc(psm_cfg->key_sz);
+ if (!key)
+ {
+ os_mem_free(sec_data);
+ return -WM_E_NOMEM;
+ }
+ memcpy(key, psm_cfg->key, psm_cfg->key_sz);
+ sec_data->key = key;
+ sec_data->key_sz = psm_cfg->key_sz;
+
+ uint8_t *iv = os_mem_calloc(psm_cfg->iv_sz);
+ if (!iv)
+ {
+ os_mem_free(key);
+ os_mem_free(sec_data);
+ return -WM_E_NOMEM;
+ }
+ memcpy(iv, psm_cfg->iv, psm_cfg->iv_sz);
+ sec_data->iv = iv;
+ sec_data->iv_sz = psm_cfg->iv_sz;
+
+ sec_data->is_key_copied = true;
+
+ *sec_handle = (psm_sec_hnd_t)sec_data;
+ return WM_SUCCESS;
+}
+
+#define KEY_IN_KS_UNINIT -1
+#define KEY_IN_KS_ABSENT 0
+#define KEY_IN_KS_PRESENT 1
+
+bool psm_is_key_present_in_keystore()
+{
+ static int8_t key_present = KEY_IN_KS_UNINIT;
+
+ /* Prevent frequent searches */
+ if (key_present == KEY_IN_KS_UNINIT)
+ key_present = ((keystore_get_ref(KEY_PSM_ENCRYPT_KEY, NULL, NULL) != ERR_TLV_NOT_FOUND) &&
+ (keystore_get_ref(KEY_PSM_NONCE, NULL, NULL) != ERR_TLV_NOT_FOUND));
+
+ return key_present;
+}
+
+int psm_key_reset(psm_sec_hnd_t sec_handle, psm_resetkey_mode_t mode)
+{
+ sec_data_t *sec_data = (sec_data_t *)sec_handle;
+
+ if (!sec_data)
+ return -WM_FAIL;
+
+ AES_SetCTRCountModular(AES, 0);
+ assert(sec_data->iv_sz >= AES_BLOCK_SIZE);
+ memcpy(sec_data->nonce, sec_data->iv, AES_BLOCK_SIZE);
+ sec_data->offset = 0U;
+
+ return WM_SUCCESS;
+}
+
+int psm_encrypt(psm_sec_hnd_t sec_handle, const void *plain, void *cipher, uint32_t len)
+{
+ sec_data_t *sec_data = (sec_data_t *)sec_handle;
+ int status;
+
+ if (!sec_data)
+ return -WM_FAIL;
+
+ status = AES_CryptCtrWithLock(AES, sec_data->key, sec_data->key_sz, plain, cipher, len, sec_data->nonce,
+ sec_data->streamBlock, &sec_data->offset);
+
+ return status;
+}
+
+int psm_decrypt(psm_sec_hnd_t sec_handle, const void *cipher, void *plain, uint32_t len)
+{
+ sec_data_t *sec_data = (sec_data_t *)sec_handle;
+ int status;
+
+ if (!sec_data)
+ return -WM_FAIL;
+
+ status = AES_CryptCtrWithLock(AES, sec_data->key, sec_data->key_sz, cipher, plain, len, sec_data->nonce,
+ sec_data->streamBlock, &sec_data->offset);
+
+ return status;
+}
+
+void psm_security_deinit(psm_sec_hnd_t *sec_handle)
+{
+ sec_data_t *sec_data = (sec_data_t *)*sec_handle;
+
+ if (!sec_data)
+ return;
+
+ uint8_t *key = (uint8_t *)sec_data->key;
+ uint8_t *iv = (uint8_t *)sec_data->iv;
+
+ if (sec_data->is_key_copied)
+ {
+ os_mem_free(iv);
+ os_mem_free(key);
+ }
+ os_mem_free(sec_data);
+}
+#endif /* CONFIG_SECURE_PSM */
diff --git a/components/boot2_utils/psm-v2-secure.h b/components/boot2_utils/psm-v2-secure.h
new file mode 100644
index 000000000..fe10717b9
--- /dev/null
+++ b/components/boot2_utils/psm-v2-secure.h
@@ -0,0 +1,156 @@
+/** @file psm-v2-secure.h
+ *
+ * @brief Persistent storage manager version 2 (secure)
+ *
+ * This file is used in case of Secure PSM. The idea is to have easily
+ * replacable security function. The security functions declared in this
+ * file need to be implemented. There can be mupliple versions. One of them
+ * can be selected at compile time.
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#include
+
+typedef void *psm_sec_hnd_t;
+
+/** Enum values which will be passed back in callback function 'resetkey' */
+typedef enum
+{
+ SET_ENCRYPTION_KEY = 0,
+ SET_DECRYPTION_KEY = 1,
+} psm_resetkey_mode_t;
+
+/**
+ * Security Init.
+ *
+ * This function should perform the initialization required for psm
+ * encryption and decryption operations. This should do everything that is
+ * required to enable encryption and decryption operations later. This
+ * function is invoked when psm_module_init() is invoked.
+ *
+ * @param[out] sec_handle Pointer to handle. Will be populated by
+ * psm_security_init()
+ *
+ * @return User defined value typically WM_SUCCESS or -WM_FAIL. Any
+ * failure here will abort the ongoing PSM operation.
+ */
+int psm_security_init(psm_sec_hnd_t *sec_handle);
+
+/**
+ * Security Init with key from caller.
+ *
+ * This function is similar to psm_security_init() with key from caller.
+ * This function should perform the initialization required for psm
+ * encryption and decryption operations. This should do everything that is
+ * required to enable encryption and decryption operations later. This
+ * function is invoked when psm_module_init() is invoked.
+ *
+ * @param[out] sec_handle Pointer to handle. Will be populated by
+ * psm_security_init_with_key()
+ * @param[in] psm_cfg Pointer to psm_cfg_t where it contains key/iv to be
+ * used by security encryption/decryption operations. PSMv2 won't need user
+ * copy of any field in psm_cfg after call returns.
+ *
+ * @return User defined value typically WM_SUCCESS or -WM_FAIL. Any
+ * failure here will abort the ongoing PSM operation.
+ */
+int psm_security_init_with_key(psm_sec_hnd_t *sec_handle, psm_cfg_t *psm_cfg);
+
+/**
+ * Specify if encryption/decryption key is present in keystore or not.
+ *
+ * This function returns true if the key is present in
+ * keystore, otherwise returns false.
+ *
+ * @return True if encryption/decryption key is present in keystore,
+ * otherwise false.
+ */
+bool psm_is_key_present_in_keystore();
+
+/**
+ * Reset PSM key.
+ *
+ * This function should reset the encryption/decryption key and/or
+ * nonce. This function will be called at the start of operation on every
+ * PSM object.
+ *
+ * Every PSM object is regarded as a independant encryption/decryption unit
+ * by the PSM. Hence, this function will be called at the start of
+ * processing of any new object.
+ *
+ * @param[in] sec_handle The same handle returned by psm_security_init().
+ * @param[in] mode The exact operation that will happen later for this
+ * key.
+ *
+ * @return User defined value typically WM_SUCCESS or -WM_FAIL. Any
+ * failure here will abort the ongoing PSM operation.
+ */
+int psm_key_reset(psm_sec_hnd_t sec_handle, psm_resetkey_mode_t mode);
+
+/**
+ * Encrypt PSM operation.
+ *
+ * This function should perform the encryption of psm data passed as a
+ * parameter.
+ *
+ * @param[in] sec_handle The same handle returned by psm_security_init().
+ * @param[in] plain Pointer to data to be encrypted (plain text)
+ * @param[out] cipher Pointer to encrypted data (cipher text).
+ * @param[in] len Length of data to be encrypted.
+ *
+ * @return User defined value typically WM_SUCCESS or -WM_FAIL. Any
+ * failure here will abort the ongoing PSM operation.
+ */
+int psm_encrypt(psm_sec_hnd_t sec_handle, const void *plain, void *cipher, uint32_t len);
+
+/**
+ * Decrypt PSM operation.
+ *
+ * This function should perform the decryption of psm data passed as a
+ * parameter.
+ *
+ * @param[in] sec_handle The same handle returned by psm_security_init().
+ * @param[in] cipher Pointer to data to be decrypted (cipher text)
+ * @param[out] plain Pointer to buffer where decrypted data (plain
+ * text) should be stored. Note that cipher and plain point to
+ * same buffer i.e. PSM-v2 expects in place decryption.
+ * @param[in] len Length of data to be decrypted.
+ *
+ * @return User defined value typically WM_SUCCESS or -WM_FAIL. Any
+ * failure here will abort the ongoing PSM operation.
+ */
+int psm_decrypt(psm_sec_hnd_t sec_handle, const void *cipher, void *plain, uint32_t len);
+
+/**
+ * Security de-init
+ *
+ * This function should perform the de-initialization required to
+ * free up the resources used for psm encryption and decryption
+ * operations. After this API no other security related function will be
+ * invoked. The implementation can free up any resources it is using. This
+ * function is invoked when psm_module_deinit() is invoked.
+ *
+ * @param[in] sec_handle Pointer to the same handle returned by
+ * psm_security_init().
+ */
+void psm_security_deinit(psm_sec_hnd_t *sec_handle);
diff --git a/components/boot2_utils/psm-v2.c b/components/boot2_utils/psm-v2.c
new file mode 100644
index 000000000..b41d42929
--- /dev/null
+++ b/components/boot2_utils/psm-v2.c
@@ -0,0 +1,3383 @@
+/** @file psm-v2.c
+ *
+ * @brief Persistent storage manager version 2
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include "psm-internal.h"
+#ifdef CONFIG_SECURE_PSM
+#include "psm-v2-secure.h"
+#endif
+#include
+#include
+#include "mflash_drv.h"
+#include "psm_list.h"
+#include "crc32.h"
+
+#define OBJECT_TYPE_INVALID (object_type_t)0x0000
+#define OBJECT_TYPE_SMALL_BINARY (object_type_t)0xAA55
+#define OBJECT_TYPE_SMALL_BINARY_MAX_SIZE (uint16_t)(~0)
+
+/*
+ * Terminology:
+ *
+ * offset: Offset from the assigned flash block
+ * address: Address of the flash device
+ * bit clear: value is '1'
+ * bit set: value is '0'
+ * compaction: remove all inactive variables from flash.
+ * indexing: Save the offset of active objects in RAM for direct access.
+ */
+
+/**
+ * Defines the single read size during verification. Bigger size will speed
+ * up verification but may cause stack overflows depending on application
+ * stack usage pattern.
+ */
+#define READ_BUFFER_SIZE 64
+#define PSM_INVALID_OBJ_ID 0xFFFF
+#define PSM_DATA_SWAP_DEMARCATION 4
+#define CHECKPOINT_MARKER 0x55AA
+#define PSM_MAX_OBJNAME_LEN 256
+
+/*
+ * This is soft limit. Is defined to optimize memory usage considering
+ * real world scenario. Can be increased upto what is supported by flash
+ * object object-id data type.
+ */
+#define PSM_MAX_OBJECTS 512
+#define PSM_DEFAULT_INDEX_ELEMENTS 10
+
+/**
+ * fixme: This value needs to be asked from flash driver. Fix this later
+ * when appropriate API is added in flash driver.
+ */
+#define PSM_FLASH_SECTOR_SIZE 4096
+
+enum
+{
+ PSM_OBJ_INACTIVE = 0x01,
+ PSM_OBJ_CACHE_REQ = 0x02,
+ PSM_OBJ_INDEX_REQ = 0x04,
+ PSM_OBJ_SECURE_MASK = 0x18,
+};
+
+/*
+ * Encoding of secure status bits (PSM_OBJ_SECURE_MASK) is as follows:
+ * (2b' stands for 2-bit binary bit-field)
+ * 2b'00 : Encrypted
+ * 2b'01 : Unencrypted
+ * 2b'10 : Encrypted (legacy value, update to 2b'00)
+ * 2b'11 : Unset, set to either 2b'00 or 2b'01
+ * Values are shifted by secure status bit-position.
+ */
+enum
+{
+ PSM_OBJ_SECURE = 0x00,
+ PSM_OBJ_UNSECURE = 0x08,
+ PSM_OBJ_SECURE_LEGACY = 0x10,
+ PSM_OBJ_SECURE_UNSET = 0x18
+};
+
+enum
+{
+ PSM_WRITE_NO_VERIFY = false,
+ PSM_WRITE_VERIFY = true
+};
+
+typedef uint16_t objectid_t;
+typedef uint16_t object_type_t;
+
+PACK_START typedef struct
+{
+ uint8_t name_len;
+ uint16_t data_len;
+ /* If secure PSM is enabled, the name variable will be encrypted. */
+ /* void *name */
+ /* If secure PSM is enabled, the data buffer will be in decrypted
+ state */
+ /* void *data */
+} PACK_END psm_cache_t;
+
+typedef struct psm_index_s
+{
+ uint32_t name_hash;
+ uint16_t obj_id;
+ uint32_t flash_offset;
+ psm_cache_t *cache;
+} psm_index_t;
+
+/* Every PSM object has this structure on the flash */
+PACK_START typedef struct
+{
+ object_type_t object_type;
+ /** Flags:
+ * [7-5]: Reserved
+ * [3:4] : Secure status bits
+ * [2] : Index request
+ * [1] : Cache request
+ * [0] : Active status
+ */
+ uint8_t flags;
+ /** CRC32 of entire psm object including metadata */
+ uint32_t crc32;
+ /** Length of the data field */
+ uint16_t data_len;
+
+ /** Object ID: A unique id for the object name ASCII string */
+ objectid_t obj_id;
+ /** Length of object name. If this is zero the object has been
+ * seen before and obj_id->name mapping is present. X-Ref: macro
+ * PSM_MAX_OBJNAME_LEN
+ */
+ uint8_t name_len;
+ /** Variable length object name string. */
+ /* uint8_t name[]; */
+ /** Binary data here. Length == psm_object.data_len member above */
+ /* uint8_t bin_data[]; */
+} PACK_END psm_object_t;
+
+PACK_START typedef struct
+{
+ uint32_t swap_start_offset;
+ uint32_t swap_start_offset_inv;
+ uint16_t checkpoint_marker;
+ uint16_t checkpoint_marker_inv;
+} PACK_END psm_swap_desc_t;
+
+typedef struct
+{
+ os_rw_lock_t prwlock;
+
+ uint32_t total_active_object_size;
+ uint32_t object_offset_limit;
+ uint32_t data_free_offset;
+ /*
+ * We do not re-use object ID's of inactivated objects. It is
+ * expected that number of used object ID will never actually reach
+ * the highest number we support. After erase object ID's are
+ * re-programmed.
+ */
+ objectid_t highest_used_obj_id;
+ uint32_t index_max_elements;
+ uint32_t index_elements;
+ psm_index_t *index;
+ psm_cfg_t psm_cfg;
+
+ /* Flash driver handle */
+ uint8_t fdesc_fl_dev;
+ uint32_t block_size;
+ uint32_t block_cnt;
+ uint32_t part_size;
+ uint32_t start_address;
+#ifdef CONFIG_SECURE_PSM
+ psm_sec_hnd_t psm_sec_hnd;
+ uint8_t psm_enc_buf[READ_BUFFER_SIZE];
+ /* This will hold encrypted copy of the name for the whole time
+ the object is open in write mode. For read mode it is valid
+ only for some time during open */
+ uint8_t psm_name_enc_buf[PSM_MAX_OBJNAME_LEN];
+#endif
+
+ psm_list_t node;
+} psm_t;
+
+/* Ephemeral RAM structure corresponding to PSM object in flash */
+typedef struct psm_objinfo_s
+{
+ psm_t *psm;
+ psm_object_t pobj;
+ /* Start of object offset */
+ uint32_t object_flash_offset;
+ /* Will move according to user operations on the object */
+ uint32_t curr_flash_offset;
+ psm_mode_t mode;
+ /* Communicated by caller in psm_object_open(). */
+ uint32_t max_data_len;
+ /** CRC32 calculated on the fly in read mode */
+ uint32_t crc32;
+ bool old_active_object_present;
+ /* Pointer to old object structure, if any */
+ uint32_t old_object_flash_offset;
+ uint32_t old_object_size;
+
+ psm_index_t *index;
+} psm_objinfo_t;
+
+#define block_size(__psm__) (__psm__->block_size)
+#define block_cnt(__psm__) (__psm__->block_cnt)
+#define part_size(__psm__) (__psm__->part_size)
+#define start_address(__psm__) (__psm__->start_address)
+#define fldev(__psm__) (__psm__->fl_dev)
+
+#define offset_to_address(__psm__, __offset__) (__psm__->start_address + __offset__)
+
+#define align_to_block_offset(__psm__, __offset__) (__offset__ & ~(__psm__->block_size - 1))
+
+#define is_offset_block_aligned(__psm__, __offset__) (!(__offset__ & (__psm__->block_size - 1)))
+
+#define object_size(__pobj__) (sizeof(psm_object_t) + (__pobj__)->name_len + (__pobj__)->data_len)
+
+#define psm_is_data_len_sane(__psm__, __len__) \
+ ((__len__ < OBJECT_TYPE_SMALL_BINARY_MAX_SIZE) && (__len__ < (part_size(psm) / 2)))
+
+#define metadata_size(__pobj__) (sizeof(psm_object_t) + (__pobj__)->name_len)
+
+#define is_object_active(__pobj__) ((__pobj__)->flags & PSM_OBJ_INACTIVE)
+#define is_object_indexable(__pobj__) (!((__pobj__)->flags & PSM_OBJ_INDEX_REQ))
+#define is_object_cacheable(__pobj__) (!((__pobj__)->flags & PSM_OBJ_CACHE_REQ))
+
+#ifdef CONFIG_SECURE_PSM
+#define get_object_secure_bits(__pobj__) ((__pobj__)->flags & PSM_OBJ_SECURE_MASK)
+
+#define set_object_secure_bits(__pobj__, bitval) \
+ do \
+ { \
+ (__pobj__)->flags = (((__pobj__)->flags & ~PSM_OBJ_SECURE_MASK) | (bitval)); \
+ } while (0)
+
+static inline bool is_object_secure(psm_object_t *__pobj__)
+{
+ uint8_t sec_status = get_object_secure_bits(__pobj__);
+
+ switch (sec_status)
+ {
+ case PSM_OBJ_SECURE:
+ return true;
+ case PSM_OBJ_SECURE_LEGACY:
+ return true;
+ case PSM_OBJ_UNSECURE:
+ return false;
+ case PSM_OBJ_SECURE_UNSET:
+ if (psm_is_key_present_in_keystore())
+ return true;
+ else
+ return false;
+ }
+
+ /* Default is false */
+ return false;
+}
+
+#define set_object_secure(__pobj__) set_object_secure_bits((__pobj__), PSM_OBJ_SECURE)
+
+#define clear_object_secure(__pobj__) set_object_secure_bits((__pobj__), PSM_OBJ_UNSECURE)
+#endif /* CONFIG_SECURE_PSM */
+
+#define remaining_part_space(__psm__) (part_size(psm) - data_free_offset)
+
+#define part_readonly(__psm__) (__psm__->psm_cfg.read_only)
+#define part_encrypted(__psm__) (__psm__->psm_cfg.secure)
+
+psm_event_callback g_psm_event_cb;
+
+/* This is a list of all initialized PSM partitions */
+static psm_list_t part_list;
+
+/* Only for test code. */
+#ifdef CONFIG_SECURE_PSM
+static bool force_psm_secure;
+#endif
+
+#ifdef CONFIG_PSM_EXTRA_DEBUG
+void psm_print_object(psm_object_t *pobj)
+{
+ wmprintf("*******************\r\n");
+ wmprintf("object_type: %x\r\n", pobj->object_type);
+ wmprintf("flags : %x\r\n", pobj->flags);
+ wmprintf("crc32 : %x\r\n", pobj->crc32);
+ wmprintf("data_len : %d\r\n", pobj->data_len);
+ wmprintf("obj_id : %d\r\n", pobj->obj_id);
+ wmprintf("name_len : %d\r\n", pobj->name_len);
+ wmprintf("*******************\r\n");
+}
+
+void psm_dump_hex(const char *buf, uint32_t size)
+{
+ int index = 0;
+ wmprintf("-----------------\r\n");
+ for (index = 0; index < size; index++)
+ {
+ if (isprint((unsigned char)buf[index]))
+ wmprintf("%2x-(%c) ", (unsigned char)buf[index], buf[index]);
+ else
+ wmprintf("%2x-( ) ", (unsigned char)buf[index]);
+ if (!((index + 1) % 4))
+ wmprintf("\r\n");
+ }
+ wmprintf("\r\n-----------------\r\n");
+}
+#endif /* CONFIG_PSM_EXTRA_DEBUG */
+
+static int psm_init_locks(psm_t *psm)
+{
+ int rv = os_rwlock_create(&psm->prwlock, "prwmutex", "prwlock");
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: rwlock create failed", __func__);
+ return rv;
+ }
+
+ return rv;
+}
+
+static int psm_deinit_locks(psm_t *psm)
+{
+ os_rwlock_delete(&psm->prwlock);
+ return WM_SUCCESS;
+}
+
+int psm_rwlock_part(psm_t *psm, psm_mode_t mode)
+{
+#ifdef CONFIG_PSM_LOCKS_DEBUG
+ psm_entry_i("mode: %d", mode);
+#endif /* CONFIG_PSM_LOCKS_DEBUG */
+
+ if (mode == PSM_MODE_WRITE)
+ os_rwlock_write_lock(&psm->prwlock, OS_WAIT_FOREVER);
+ else
+ os_rwlock_read_lock(&psm->prwlock, OS_WAIT_FOREVER);
+
+ return WM_SUCCESS;
+}
+
+void psm_rwunlock_part(psm_t *psm, psm_mode_t mode)
+{
+#ifdef CONFIG_PSM_LOCKS_DEBUG
+ psm_entry_i("mode: %d", mode);
+#endif /* CONFIG_PSM_LOCKS_DEBUG */
+
+ if (mode == PSM_MODE_WRITE)
+ os_rwlock_write_unlock(&psm->prwlock);
+ else
+ os_rwlock_read_unlock(&psm->prwlock);
+}
+
+static bool psm_is_objid_available(psm_t *psm)
+{
+ psm_entry_i();
+ if (psm->highest_used_obj_id == (PSM_INVALID_OBJ_ID - 1))
+ return false;
+ else
+ return true;
+}
+
+bool psm_is_free_space(const psm_object_t *pobj)
+{
+ if (pobj->object_type == (object_type_t)~0)
+ return true;
+
+ return false;
+}
+
+/*
+ * Block size can be a multiple of sector size. For now keep it same as
+ * sector size.
+ */
+static int psm_get_block_size()
+{
+ return PSM_FLASH_SECTOR_SIZE;
+}
+
+static objectid_t psm_get_unused_obj_id(psm_t *psm)
+{
+ psm_entry_i();
+ if (psm->highest_used_obj_id >= (objectid_t)PSM_MAX_OBJECTS)
+ {
+ /*
+ * It is expected that this case would never occur. Put
+ * other way the number of unique objects in PSM can never
+ * cross PSM_MAX_OBJECTS. During compaction we re-program
+ * the object IDs. So, holes are not an issue anyway.
+ */
+ psm_d("Invalid use case");
+ return PSM_INVALID_OBJ_ID;
+ }
+
+ psm->highest_used_obj_id++;
+ psm_ed("New object id assigned: 0x%x", psm->highest_used_obj_id);
+ return psm->highest_used_obj_id;
+}
+
+static uint32_t psm_calc_metadata_crc32(psm_object_t *pobj, uint32_t partial_crc32)
+{
+ /* Backup */
+ uint32_t temp_crc32 = pobj->crc32;
+ /* Init */
+ pobj->crc32 = ~0;
+ /* Calculate */
+ uint32_t crc32 = soft_crc32(pobj, sizeof(psm_object_t), partial_crc32);
+ /* Restore */
+ pobj->crc32 = temp_crc32;
+ return crc32;
+}
+
+/*
+ * Ensure that offset and size is block aligned.
+ */
+static int psm_erase_flash(psm_t *psm, uint32_t offset, uint32_t size)
+{
+ psm_ll("%s: offset: 0x%x size: 0x%x", __func__, offset, size);
+
+ if ((offset % block_size(psm)) || (size % block_size(psm)))
+ {
+ psm_d("Misaligned offset or size: %x: %d", offset, size);
+ return -WM_E_INVAL;
+ }
+
+ if ((offset + size) > part_size(psm))
+ {
+ psm_d("Invalid params given to erase: %u: %u", offset, size);
+ return -WM_E_INVAL;
+ }
+
+ uint32_t address = offset_to_address(psm, offset);
+ int rv = mflash_drv_erase(address, size);
+ if (rv != kStatus_Success)
+ {
+ psm_d("Unable to erase flash data %x:%d", address, size);
+ return rv;
+ }
+
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_ERASE, (void *)((unsigned long)address), (void *)((unsigned long)size));
+
+ return rv;
+}
+
+int psm_read_flash(psm_t *psm, void *buffer, uint32_t size, uint32_t offset)
+{
+ psm_ll("%s: %x, %d", __func__, offset, size);
+
+ if (size == 0)
+ psm_d("%s: Zero length read from 0x%x", __func__, (uint32_t)__builtin_return_address(0));
+
+ if ((offset + size) > part_size(psm))
+ {
+ psm_d("Invalid params given to read: %u: %u", offset, size);
+ return -WM_E_INVAL;
+ }
+
+ uint32_t address = offset_to_address(psm, offset);
+
+ int rv = mflash_drv_read(address, buffer, size);
+ if (rv != kStatus_Success)
+ {
+ psm_d("Unable to read from flash: %x: %d", address, size);
+ return rv;
+ }
+
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_READ, (void *)((unsigned long)address), (void *)((unsigned long)size));
+
+ return rv;
+}
+
+static int psm_write_verify(psm_t *psm, const uint8_t *reference_buf, uint32_t size, uint32_t offset)
+{
+ psm_entry_i();
+ int rv;
+ uint32_t read_size;
+ char buf[READ_BUFFER_SIZE];
+ uint32_t index;
+ for (index = 0; index < size; index += read_size)
+ {
+ uint32_t remaining = (size - index);
+ read_size = remaining > READ_BUFFER_SIZE ? READ_BUFFER_SIZE : remaining;
+ rv = psm_read_flash(psm, buf, read_size, offset + index);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: psm_read_flash %x: %d failed", __func__, offset + index, read_size);
+ return rv;
+ }
+
+ if (memcmp(&reference_buf[index], buf, read_size))
+ {
+ psm_d("%s: verification failed @ offset: %x: %d", __func__, offset + index, read_size);
+ return -WM_FAIL;
+ }
+ }
+
+ return WM_SUCCESS;
+}
+
+/*
+ * This function is necessary only when source and destination address is
+ * from the same flash.
+ */
+static int psm_write_flash_same_device_rw(psm_t *psm, const void *buffer, uint32_t size, uint32_t address)
+{
+ int rv = -WM_FAIL;
+ const int tmpbuf_size = 16;
+ void *tmpbuf = os_mem_alloc(tmpbuf_size);
+ if (!tmpbuf)
+ return -WM_E_NOMEM;
+
+ uint32_t remaining_size = size;
+ while (remaining_size)
+ {
+ int chunk_size = remaining_size > tmpbuf_size ? tmpbuf_size : remaining_size;
+ memcpy(tmpbuf, buffer, chunk_size);
+ rv = mflash_drv_write(address, tmpbuf, chunk_size);
+ if (rv != kStatus_Success)
+ {
+ psm_d("Unable to write to flash: %x: %d", address, size);
+ break;
+ }
+
+ address += chunk_size;
+ remaining_size -= chunk_size;
+ buffer = (const uint8_t *)buffer + chunk_size;
+ }
+
+ os_mem_free(tmpbuf);
+ return rv;
+}
+
+/**
+ * If verify is 'true' the written data will be re-read and verified with
+ * original given buffer. Note that this uses heap to allocate read
+ * buffer.
+ */
+static int psm_write_flash(psm_t *psm, const void *buffer, uint32_t size, uint32_t offset, bool verify)
+{
+ psm_ll("%s: %x, %d", __func__, offset, size);
+
+ if ((offset + size) > part_size(psm))
+ {
+ psm_d("Invalid params given to write: %u: %u", offset, size);
+ return -WM_E_INVAL;
+ }
+
+ int rv;
+ uint32_t address = offset_to_address(psm, offset);
+
+ rv = mflash_drv_write(address, (void *)buffer, size);
+ if (rv != kStatus_Success)
+ {
+ if (rv == -WM_E_FAULT)
+ rv = psm_write_flash_same_device_rw(psm, buffer, size, address);
+ if (rv != kStatus_Success)
+ psm_d("(rw-flash) Unable to write to flash: %x: %d", address, size);
+ return rv;
+ }
+
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_WRITE, (void *)((unsigned long)address), (void *)((unsigned long)size));
+
+ if (verify)
+ return psm_write_verify(psm, buffer, size, offset);
+
+ return WM_SUCCESS;
+}
+
+static int write_flag_bit(psm_t *psm, uint32_t flag_offset, uint8_t flag)
+{
+ /*
+ * Note: As per flash properties '0' value of a bit cannot be
+ * changed to '1' unless the flash sector is erased. Hence, we do
+ * not need to do a read-modify-write cycle to set a particular bit
+ * to zero as long as other bits in the written byte are '1'
+ */
+ uint8_t inv_flag = ~(flag);
+ return psm_write_flash(psm, &inv_flag, sizeof(uint8_t), flag_offset, PSM_WRITE_NO_VERIFY);
+}
+
+static int read_swap_descriptor(psm_t *psm, psm_swap_desc_t *swap_desc)
+{
+ psm_entry_i();
+ uint32_t offset = part_size(psm) - sizeof(psm_swap_desc_t);
+ int rv = psm_read_flash(psm, swap_desc, sizeof(psm_swap_desc_t), offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Unable to read swap descriptor");
+ return rv;
+ }
+
+ return WM_SUCCESS;
+}
+
+static int write_swap_descriptor(psm_t *psm, const psm_swap_desc_t *swap_desc, bool write_swap_offset)
+{
+ uint32_t offset = part_size(psm) - sizeof(psm_swap_desc_t);
+ if (write_swap_offset)
+ {
+ psm_entry_i("swap_offset: 0x%x", swap_desc->swap_start_offset);
+ int rv = psm_write_flash(psm, &swap_desc->swap_start_offset, sizeof(swap_desc->swap_start_offset) * 2, offset,
+ PSM_WRITE_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Unable to write swap descriptor offset");
+ return rv;
+ }
+ }
+ else
+ {
+ psm_entry_i("marker: 0x%x", swap_desc->checkpoint_marker);
+ offset += offsetof(psm_swap_desc_t, checkpoint_marker);
+ int rv = psm_write_flash(psm, &swap_desc->checkpoint_marker, sizeof(swap_desc->checkpoint_marker) * 2, offset,
+ PSM_WRITE_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Unable to write swap descriptor marker");
+ return rv;
+ }
+ }
+
+ return WM_SUCCESS;
+}
+
+static int invalidate_swap_descriptor(psm_t *psm)
+{
+ psm_entry_i();
+ psm_swap_desc_t swap_desc;
+ memset(&swap_desc, 0x00, sizeof(psm_swap_desc_t));
+
+ uint32_t offset = part_size(psm) - sizeof(psm_swap_desc_t);
+ int rv = psm_write_flash(psm, &swap_desc, sizeof(psm_swap_desc_t), offset, PSM_WRITE_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Unable to invalidate swap descriptor offset");
+ return rv;
+ }
+
+ return WM_SUCCESS;
+}
+
+typedef enum
+{
+ /*
+ * - Data area good.
+ * - No/Invalid swap descriptor present.
+ * - Compaction to be done.
+ */
+ CHECKPOINT_0,
+ /*
+ * - Data area good.
+ * - Compaction has/was started.
+ * - Swap offset is correct.
+ * - Checkpoint marker is not correct.
+ */
+ CHECKPOINT_1,
+ /*
+ * - Swap area is good.
+ * - Data incorrect assumed.
+ * - Valid swap descriptor present with checkpoint marker.
+ */
+ CHECKPOINT_2,
+ /*
+ * - Data area is good.
+ * - Swap area descriptor is invalid.
+ * - Compaction is not needed. Only the swap needs to be brought to
+ * init state.
+ */
+ CHECKPOINT_3,
+ /*
+ * - Data area is good.
+ * - Swap area is clean.
+ * - No-op
+ */
+ CHECKPOINT_4,
+} checkpoint_t;
+
+static uint32_t psm_get_swap_start_offset(psm_t *psm)
+{
+ return align_to_block_offset(psm, (part_size(psm) - sizeof(psm_swap_desc_t) - psm->total_active_object_size));
+}
+
+#ifdef CONFIG_SECURE_PSM
+int resetkey(psm_t *psm, psm_resetkey_mode_t mode)
+{
+ return psm_key_reset(psm->psm_sec_hnd, mode);
+}
+
+int encrypt_buf(psm_t *psm, const void *plain, void *cipher, int len)
+{
+ return psm_encrypt(psm->psm_sec_hnd, plain, cipher, len);
+}
+
+int decrypt_buf(psm_t *psm, const void *cipher, void *plain, int len)
+{
+ return psm_decrypt(psm->psm_sec_hnd, cipher, plain, len);
+}
+#endif /* CONFIG_SECURE_PSM */
+
+static void psm_reset_index(psm_t *psm)
+{
+ psm_entry_i();
+ if (!psm->index)
+ {
+ psm->index_elements = 0;
+ psm->index_max_elements = 0;
+ return;
+ }
+
+ int cnt;
+ for (cnt = 0; cnt < psm->index_elements; cnt++)
+ {
+ if (psm->index[cnt].cache)
+ {
+ os_mem_free(psm->index[cnt].cache);
+ psm->index[cnt].cache = NULL;
+ }
+ }
+
+ os_mem_free(psm->index);
+ psm->index = NULL;
+ psm->index_elements = 0;
+ psm->index_max_elements = 0;
+}
+
+/*
+ * Also copies the name to the name buffer is buffer address is supplied.
+ */
+static int psm_calc_name_hash(
+ psm_t *psm, psm_object_t *pobj, uint32_t flash_offset, uint32_t *name_hash, uint8_t *name_buf)
+{
+ uint8_t buf[READ_BUFFER_SIZE];
+ uint32_t crc32 = 0;
+ uint8_t read_size;
+ uint8_t index;
+ uint32_t name_flash_offset = flash_offset + sizeof(psm_object_t);
+
+ flash_offset += sizeof(psm_object_t);
+ for (index = 0; index < pobj->name_len; index += read_size)
+ {
+ uint8_t remaining = pobj->name_len - index;
+ read_size = remaining > READ_BUFFER_SIZE ? READ_BUFFER_SIZE : remaining;
+ int rv = psm_read_flash(psm, buf, read_size, name_flash_offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: Unable to read name", __func__);
+ return rv;
+ }
+
+ if (name_buf)
+ memcpy(&name_buf[index], buf, read_size);
+
+ name_flash_offset += read_size;
+ crc32 = soft_crc32(buf, read_size, crc32);
+ }
+
+ *name_hash = crc32;
+ return WM_SUCCESS;
+}
+
+static void psm_add_to_index(psm_t *psm, psm_object_t *pobj, uint32_t flash_offset)
+{
+ psm_i("Indexing obj_id: %d", pobj->obj_id);
+ if (!psm->index)
+ {
+ psm_i("Allocating index");
+ uint32_t index_size = sizeof(psm_index_t) * PSM_DEFAULT_INDEX_ELEMENTS;
+ psm->index = os_mem_calloc(index_size);
+ if (!psm->index)
+ {
+ psm_d("Index allocation failed");
+ return;
+ }
+
+ psm->index_elements = 0;
+ psm->index_max_elements = PSM_DEFAULT_INDEX_ELEMENTS;
+ }
+
+ if (psm->index_elements == psm->index_max_elements)
+ {
+ /* Indexing space is over. Try to get more space */
+ psm_i("Increasing index allocation");
+ uint32_t current_index_size = sizeof(psm_index_t) * psm->index_max_elements;
+ uint32_t new_index_size = current_index_size + (sizeof(psm_index_t) * PSM_DEFAULT_INDEX_ELEMENTS);
+ psm_index_t *new_index = os_mem_alloc(new_index_size);
+
+ if (!new_index)
+ {
+ psm_d("New index allocation failed: %d", new_index_size);
+ return;
+ }
+ memcpy(new_index, psm->index, current_index_size);
+ os_mem_free(psm->index);
+
+ /* Zero out new allocated area */
+ memset(&new_index[psm->index_max_elements], 0x00, (sizeof(psm_index_t) * PSM_DEFAULT_INDEX_ELEMENTS));
+ psm->index = new_index;
+ psm->index_max_elements += PSM_DEFAULT_INDEX_ELEMENTS;
+ }
+
+ psm_cache_t *cache = NULL;
+ uint8_t *name_buf = NULL;
+ uint8_t *data_buf = NULL;
+ if (is_object_cacheable(pobj))
+ {
+ uint32_t cache_size = sizeof(psm_cache_t) + pobj->name_len + pobj->data_len;
+ cache = os_mem_calloc(cache_size);
+ if (cache)
+ {
+ cache->name_len = pobj->name_len;
+ cache->data_len = pobj->data_len;
+ /* Point name buf to name field of cache */
+ name_buf = (uint8_t *)(cache + 1);
+ data_buf = name_buf + cache->name_len;
+ }
+ else
+ {
+ psm_d("Cache allocation failed. Ignoring");
+ }
+ }
+
+ psm_index_t *index = &psm->index[psm->index_elements];
+
+ uint32_t name_hash = 0;
+
+ int rv = psm_calc_name_hash(psm, pobj, flash_offset, &name_hash, name_buf);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Name_Hash calculation failed");
+ os_mem_free(cache);
+ return;
+ }
+
+ index->name_hash = name_hash;
+ index->obj_id = pobj->obj_id;
+ index->flash_offset = flash_offset;
+ index->cache = cache;
+
+ if (!cache)
+ {
+ psm->index_elements++;
+ return;
+ }
+
+ psm_i("Object %d is also cacheable. Caching name and value (size: %d)", pobj->obj_id, cache->data_len);
+ /*
+ * Object is also cacheable. Name field is already read and
+ * cached. Other fields of cache object are populated. Now cache
+ * the data field.
+ */
+ if (cache->data_len != 0)
+ {
+ rv = psm_read_flash(psm, data_buf, cache->data_len, flash_offset + metadata_size(pobj));
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to cache name field");
+ os_mem_free(cache);
+ memset(index, 0x00, sizeof(psm_index_t));
+ return;
+ }
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ {
+ rv = resetkey(psm, SET_DECRYPTION_KEY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("reset enc key (data_i) fail");
+ os_mem_free(cache);
+ memset(index, 0x00, sizeof(psm_index_t));
+ return;
+ }
+
+ /* Use 'psm_name_enc_buf' as temp. buffer */
+ rv = decrypt_buf(psm, name_buf, psm->psm_name_enc_buf, cache->name_len);
+ if (rv != WM_SUCCESS)
+ {
+ os_mem_free(cache);
+ memset(index, 0x00, sizeof(psm_index_t));
+ return;
+ }
+
+ rv = decrypt_buf(psm, data_buf, data_buf, cache->data_len);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("dec-i fail");
+ os_mem_free(cache);
+ memset(index, 0x00, sizeof(psm_index_t));
+ return;
+ }
+ }
+#endif /* CONFIG_SECURE_PSM */
+ }
+
+ psm->index_elements++;
+}
+
+/*
+ * Return -WM_FAIL if already set. Set bit and return WM_SUCCESS
+ * otherwise.
+ */
+static int test_and_set_bitmap(uint8_t *bitmap, objectid_t obj_id)
+{
+ uint32_t bit_num = (uint32_t)obj_id;
+ uint32_t array_offset = bit_num / (sizeof(uint8_t) * 8);
+ uint32_t bit_offset = bit_num % (sizeof(uint8_t) * 8);
+
+ if (bitmap[array_offset] & (uint8_t)(1 << bit_offset))
+ return -WM_FAIL; /* Already set */
+
+ bitmap[array_offset] |= (uint8_t)(1 << bit_offset);
+ return WM_SUCCESS;
+}
+
+/*
+ * Kill the object. A recovery would be needed invariably.
+ */
+static void handle_double_active_object(psm_t *psm, uint32_t object_offset)
+{
+ /*
+ * Kill the object and invalidating the object type field. All
+ * objects after this object will become effectively lost after
+ * this. This is not so bad because a double active object case
+ * would is expected to occur when an new object write did not
+ * complete successfully. Thus, there should be no objects after
+ * this.
+ */
+ object_type_t invalid_obj = OBJECT_TYPE_INVALID;
+ (void)psm_write_flash(psm, &invalid_obj, sizeof(invalid_obj), object_offset, false);
+}
+
+static int psm_part_scan(psm_t *psm)
+{
+ psm_entry_i();
+
+ uint32_t offset = 0;
+
+ uint32_t limit = psm->object_offset_limit;
+ psm_object_t pobj;
+ objectid_t highest_found = 0;
+
+ uint32_t bitmap_size = (PSM_MAX_OBJECTS / 8) + 1;
+
+ /* A bitmap to map all active objects */
+ uint8_t *bitmap = os_mem_calloc(bitmap_size);
+ if (!bitmap)
+ {
+ psm_e("unable to alloc psm object bitmap");
+ return -WM_E_NOMEM;
+ }
+
+ int rv = WM_SUCCESS, rv1;
+
+ psm->total_active_object_size = 0;
+ psm_reset_index(psm);
+
+ while (offset < limit)
+ {
+ psm_isc("offset: %p (%p) limit: %p (%p) ", (void *)offset, (void *)offset_to_address(psm, offset),
+ (void *)limit, (void *)offset_to_address(psm, limit));
+ rv1 = psm_read_flash(psm, &pobj, sizeof(psm_object_t), offset);
+ if (rv1 != WM_SUCCESS)
+ {
+ psm_w("scan: could not read object @ off: %x", offset);
+ rv = rv1;
+ break;
+ }
+
+ if (psm_is_free_space(&pobj))
+ {
+ psm_isc("Free space marker found");
+ break;
+ }
+
+ if (pobj.object_type != OBJECT_TYPE_SMALL_BINARY)
+ {
+ psm_w(
+ "scan: Invalid obj (%x) at the end of"
+ " data area off: %p addr: %p",
+ pobj.object_type, (void *)((long)offset), (void *)((long)offset_to_address(psm, offset)));
+ rv = -WM_FAIL;
+ break;
+ }
+
+ if (!psm_is_data_len_sane(psm, pobj.data_len))
+ {
+ /* Invalid length of object. Need recovery */
+ psm_w("PSM invalid object found during scan.");
+ rv = -WM_FAIL;
+ break;
+ }
+
+ if (pobj.obj_id > highest_found)
+ highest_found = pobj.obj_id;
+
+ if (!is_object_active(&pobj))
+ {
+ offset += object_size(&pobj);
+ continue;
+ }
+
+ rv1 = test_and_set_bitmap(bitmap, pobj.obj_id);
+ if (rv1 == -WM_FAIL)
+ {
+ psm_w("Double active object %d detected", pobj.obj_id);
+ handle_double_active_object(psm, offset);
+ /* Report error to start recovery */
+ rv = rv1;
+ break;
+ }
+
+#ifdef CONFIG_SECURE_PSM
+ /*
+ * Check for partition encryption status vs. object encryption
+ * status mismatch
+ */
+ if ((part_encrypted(psm) && !is_object_secure(&pobj)) || (!part_encrypted(psm) && is_object_secure(&pobj)))
+ {
+ /*
+ * Report error to start recovery/upgrade.
+ * Continue scanning however.
+ */
+ psm_d(
+ "PSM secure status mismatch found during"
+ " scan");
+ rv = -WM_FAIL;
+ offset += object_size(&pobj);
+ psm->total_active_object_size += object_size(&pobj);
+ continue;
+ }
+#else
+ /*
+ * Ignore this case, as no recovery/upgrade is possible because
+ * of absence of encryption/decryption functions
+ */
+#endif /* CONFIG_SECURE_PSM */
+
+ if (is_object_indexable(&pobj)) /* Ignore any error */
+ psm_add_to_index(psm, &pobj, offset);
+
+ psm_isc("Obj: Name Len: %d Data Len: %d Active: %d", pobj.name_len, pobj.data_len, is_object_active(&pobj));
+
+ /* Only active objects length is added */
+ psm->total_active_object_size += object_size(&pobj);
+ offset += object_size(&pobj);
+ }
+
+ psm_isc("Scan complete: Data Free Offset: %p Phy. Address: %p", offset, offset_to_address(psm, offset));
+
+ psm->highest_used_obj_id = highest_found;
+ psm->data_free_offset = offset;
+ psm_d("data_free_offset set to 0x%x", psm->data_free_offset);
+
+ os_mem_free(bitmap);
+ return rv;
+}
+
+/*
+ * - Copies an object from source offset (swap) to dest offset (data).
+ * - Verification of CRC is also done on-the-go. If the CRC is wrong, the
+ * destination object is marked inactive.
+ * - Assumes that the source psm_object_t is already read and pobj param is
+ * populated.
+ */
+static int psm_copy_object(
+ psm_t *psm, psm_object_t *pobj, uint32_t source_offset, uint32_t dest_offset, objectid_t new_objid)
+{
+ psm_entry_i("obj-id: 0x%x len: %d source: 0x%x dest: 0x%x", pobj->obj_id, pobj->data_len, source_offset,
+ dest_offset);
+
+ psm_ed("Copying object %d\r\n", pobj->obj_id);
+
+ /*
+ * The destination object ID is different than that of source. CRC
+ * comparison needs to take care of this fact. Basically, CRC needs
+ * to be calculated separately for source object and destination
+ * object.
+ */
+ uint32_t src_ref_crc32 = pobj->crc32;
+ uint32_t cal_crc32 = 0;
+ objectid_t saved_src_obj_id = pobj->obj_id;
+
+ uint32_t dest_object_start_offset = dest_offset;
+
+ /* Update Object iD for destination object */
+ pobj->obj_id = new_objid;
+ /* Keep CRC32 field uninitialized */
+ pobj->crc32 = (uint32_t)~0;
+
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_10, (void *)PSM_COMPACTION_MAX);
+
+ int rv = psm_write_flash(psm, pobj, sizeof(psm_object_t), dest_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: metadata write failed", __func__);
+ return rv;
+ }
+
+ dest_offset += sizeof(psm_object_t);
+ source_offset += sizeof(psm_object_t);
+
+ uint32_t copy_size = pobj->name_len + pobj->data_len;
+
+ uint8_t buf[READ_BUFFER_SIZE];
+ uint32_t index;
+ uint32_t read_size;
+ for (index = 0; index < copy_size; index += read_size)
+ {
+ uint32_t remaining = copy_size - index;
+ read_size = remaining > READ_BUFFER_SIZE ? READ_BUFFER_SIZE : remaining;
+
+ int rv = psm_read_flash(psm, buf, read_size, source_offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: read failed", __func__);
+ return rv;
+ }
+
+ rv = psm_write_flash(psm, buf, read_size, dest_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: write failed", __func__);
+ return rv;
+ }
+
+ cal_crc32 = soft_crc32(buf, read_size, cal_crc32);
+
+ source_offset += read_size;
+ dest_offset += read_size;
+ }
+
+ uint32_t dest_crc32 = psm_calc_metadata_crc32(pobj, cal_crc32);
+
+ /* Restore obj_id to calculate CRC32 */
+ pobj->obj_id = saved_src_obj_id;
+ uint32_t src_crc32 = psm_calc_metadata_crc32(pobj, cal_crc32);
+
+ psm_ed("src_ref_crc32: 0x%x src_crc32: 0x%x dest_crc32: 0x%x", src_ref_crc32, src_crc32, dest_crc32);
+ /*
+ * Check is source object CRC32 was correct. We are doing this
+ * late to avoid two passes over source object data.
+ */
+ if (src_crc32 == src_ref_crc32)
+ {
+ /*
+ * Write new CRC32. We have to update CRC32 because we have
+ * programmed new obj-id.
+ */
+ uint32_t crc32_offset = dest_object_start_offset + offsetof(psm_object_t, crc32);
+ rv = psm_write_flash(psm, &dest_crc32, sizeof(dest_crc32), crc32_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to update CRC32 of copied object");
+ return rv;
+ }
+
+ return WM_SUCCESS;
+ }
+
+ /*
+ * Mark inactive just copied object because CRC calculation
+ * failed. This effectively deletes the object from the PSM.
+ */
+ psm_d("Object: 0x%x has failed CRC during copy. Marking inactive", pobj->obj_id);
+ uint32_t flag_offset = dest_object_start_offset + offsetof(psm_object_t, flags);
+ rv = write_flag_bit(psm, flag_offset, PSM_OBJ_INACTIVE);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to mark copied object inactive");
+ return rv;
+ }
+
+ return WM_SUCCESS;
+}
+
+static int psm_upgrade_object(
+ psm_t *psm, psm_object_t *pobj, uint32_t source_offset, uint32_t dest_offset, objectid_t new_objid)
+{
+ psm_entry_i("obj-id: 0x%x len: %d source: 0x%x dest: 0x%x", pobj->obj_id, pobj->data_len, source_offset,
+ dest_offset);
+
+ psm_ed("Upgrading object %d\r\n", pobj->obj_id);
+
+ /*
+ * The destination object ID is different than that of source. CRC
+ * comparison needs to take care of this fact. Basically, CRC needs
+ * to be calculated separately for source object and destination
+ * object.
+ */
+ uint32_t src_ref_crc32 = pobj->crc32;
+ uint32_t src_cal_crc32 = 0, dest_cal_crc32 = 0;
+ objectid_t saved_src_obj_id = pobj->obj_id;
+
+ uint32_t dest_object_start_offset = dest_offset;
+
+ /* Handle object metadata */
+ /* Update Object iD for destination object */
+ pobj->obj_id = new_objid;
+ /* Keep CRC32 field uninitialized */
+ pobj->crc32 = (uint32_t)~0;
+
+#ifdef CONFIG_SECURE_PSM
+ uint8_t saved_object_secure_bits = get_object_secure_bits(pobj);
+ bool saved_is_object_secure = is_object_secure(pobj);
+ if (part_encrypted(psm))
+ set_object_secure(pobj);
+ else
+ clear_object_secure(pobj);
+#endif /* CONFIG_SECURE_PSM */
+
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_10, (void *)PSM_COMPACTION_MAX);
+
+ int rv = psm_write_flash(psm, pobj, sizeof(psm_object_t), dest_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: metadata write failed", __func__);
+ return rv;
+ }
+
+ dest_offset += sizeof(psm_object_t);
+ source_offset += sizeof(psm_object_t);
+
+ /* Handle object name & data */
+ uint32_t copy_size = pobj->name_len + pobj->data_len;
+
+ uint8_t buf[READ_BUFFER_SIZE];
+ uint32_t index;
+ uint32_t read_size;
+
+#ifdef CONFIG_SECURE_PSM
+ /* Encryption/decryption sequence is:
+ * 1. Reset AES engine (resetkey())
+ * 2. Encrypt/decrypt name field in chunks
+ * 3. Encrypt/decrypt data field in chunks
+ */
+ if (part_encrypted(psm) && !saved_is_object_secure)
+ {
+ /* Reset the AES engine */
+ rv = resetkey(psm, SET_ENCRYPTION_KEY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("upgrade: reset enc key fail");
+ return rv;
+ }
+ }
+ else if (!part_encrypted(psm) && saved_is_object_secure)
+ {
+ /* Reset the AES engine */
+ rv = resetkey(psm, SET_DECRYPTION_KEY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("upgrade: reset dec key fail");
+ return rv;
+ }
+ }
+#endif /* CONFIG_SECURE_PSM */
+
+ for (index = 0; index < copy_size; index += read_size)
+ {
+ uint32_t remaining = copy_size - index;
+ read_size = remaining > READ_BUFFER_SIZE ? READ_BUFFER_SIZE : remaining;
+
+ int rv = psm_read_flash(psm, buf, read_size, source_offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: read failed", __func__);
+ return rv;
+ }
+
+ src_cal_crc32 = soft_crc32(buf, read_size, src_cal_crc32);
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm) && !saved_is_object_secure)
+ {
+ /* Encrypt the object chunk */
+ rv = encrypt_buf(psm, buf, buf, read_size);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("upgrade: enc fail");
+ return rv;
+ }
+ }
+ else if (!part_encrypted(psm) && saved_is_object_secure)
+ {
+ /* Decrypt the object chunk */
+ rv = decrypt_buf(psm, buf, buf, read_size);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("upgrade: dec fail");
+ return rv;
+ }
+ }
+#endif /* CONFIG_SECURE_PSM */
+
+ rv = psm_write_flash(psm, buf, read_size, dest_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: write failed", __func__);
+ return rv;
+ }
+
+ dest_cal_crc32 = soft_crc32(buf, read_size, dest_cal_crc32);
+
+ source_offset += read_size;
+ dest_offset += read_size;
+ }
+
+ uint32_t dest_crc32 = psm_calc_metadata_crc32(pobj, dest_cal_crc32);
+
+ /* Restore obj_id to calculate CRC32 */
+ pobj->obj_id = saved_src_obj_id;
+#ifdef CONFIG_SECURE_PSM
+ /* Restore secure flag to calculate CRC32 */
+ set_object_secure_bits(pobj, saved_object_secure_bits);
+#endif /* CONFIG_SECURE_PSM */
+
+ uint32_t src_crc32 = psm_calc_metadata_crc32(pobj, src_cal_crc32);
+
+ psm_ed("src_ref_crc32: 0x%x src_crc32: 0x%x dest_crc32: 0x%x", src_ref_crc32, src_crc32, dest_crc32);
+ /*
+ * Check is source object CRC32 was correct. We are doing this
+ * late to avoid two passes over source object data.
+ */
+ if (src_crc32 == src_ref_crc32)
+ {
+ /*
+ * Write new CRC32. We have to update CRC32 because we have
+ * programmed new obj-id.
+ */
+ uint32_t crc32_offset = dest_object_start_offset + offsetof(psm_object_t, crc32);
+ rv = psm_write_flash(psm, &dest_crc32, sizeof(dest_crc32), crc32_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to update CRC32 of copied object");
+ return rv;
+ }
+
+ return WM_SUCCESS;
+ }
+
+ /*
+ * Mark inactive just upgraded object because CRC calculation
+ * on source object failed. This effectively deletes the object from the PSM.
+ */
+ psm_d("Object: 0x%x has failed CRC during upgrade. Marking inactive", pobj->obj_id);
+ uint32_t flag_offset = dest_object_start_offset + offsetof(psm_object_t, flags);
+ rv = write_flag_bit(psm, flag_offset, PSM_OBJ_INACTIVE);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to mark copied object inactive");
+ return rv;
+ }
+
+ return WM_SUCCESS;
+}
+
+static int psm_copy_all_objects(psm_t *psm,
+ checkpoint_t checkpoint,
+ uint32_t source_offset,
+ uint32_t source_limit,
+ uint32_t dest_offset,
+ uint32_t dest_limit)
+{
+ psm_entry_i();
+
+ psm_object_t pobj;
+ objectid_t objid_counter = 0;
+
+ while (source_offset < source_limit)
+ {
+ if (objid_counter >= PSM_MAX_OBJECTS)
+ {
+ psm_d("Unexpected error during copy all objs");
+ return -WM_FAIL;
+ }
+
+ int rv = psm_read_flash(psm, &pobj, sizeof(psm_object_t), source_offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: could not read object @ : %x", __func__, source_offset);
+ return -WM_FAIL;
+ }
+
+ if (psm_is_free_space(&pobj))
+ break;
+
+ if (!psm_is_data_len_sane(psm, pobj.data_len))
+ {
+ psm_d("%s: Invalid data length: %d", __func__, pobj.data_len);
+ return -WM_FAIL;
+ }
+
+ if (pobj.object_type != OBJECT_TYPE_SMALL_BINARY)
+ {
+ psm_d(
+ "%s: Invalid obj at the end of data area. "
+ "Ignoring",
+ __func__);
+ break;
+ }
+
+ if (!is_object_active(&pobj))
+ {
+ psm_ed("Inactive object with id: %x size: %d", pobj.obj_id, pobj.data_len);
+ source_offset += object_size(&pobj);
+ continue;
+ }
+
+ if (checkpoint == CHECKPOINT_1)
+ {
+ /*
+ * This is operation from data area to swap area.
+ * We upgrade data here to desired psm format,
+ * instead of simple copy. If no upgrade is required,
+ * following will do a simple copy
+ */
+ rv = psm_upgrade_object(psm, &pobj, source_offset, dest_offset, ++objid_counter);
+ }
+ else if (checkpoint == CHECKPOINT_2)
+ {
+ /*
+ * This is operation from swap area to data area.
+ * We simply copy data here
+ */
+ rv = psm_copy_object(psm, &pobj, source_offset, dest_offset, ++objid_counter);
+ }
+ else
+ {
+ rv = -WM_FAIL;
+ psm_d("Invalid checkpoint during compaction/upgrade");
+ }
+
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("compaction/upgrade failed");
+ return rv;
+ }
+
+ source_offset += object_size(&pobj);
+ dest_offset += object_size(&pobj);
+
+ if (dest_offset >= dest_limit)
+ {
+ /*
+ * This case should never occur because we always
+ * keep tab of total size of active objects.
+ */
+ psm_d("%s: no space left in destination to copy", __func__);
+ return -WM_FAIL;
+ }
+ }
+
+ return WM_SUCCESS;
+}
+
+static uint32_t get_erase_start_offset(psm_t *psm)
+{
+ uint32_t erase_start;
+ /*
+ * We have no idea about start of swap address. So erase all non
+ * data area.
+ */
+ if (!is_offset_block_aligned(psm, psm->data_free_offset))
+ {
+ erase_start = align_to_block_offset(psm, psm->data_free_offset);
+ erase_start += block_size(psm);
+ /* 'erase_start' is now block aligned */
+ }
+ else
+ {
+ erase_start = psm->data_free_offset;
+ }
+
+ return erase_start;
+}
+
+static int handle_recovery(psm_t *psm, checkpoint_t checkpoint, psm_swap_desc_t *swap_desc)
+{
+ psm_entry_i("Checkpoint: %d", checkpoint);
+ int rv;
+ bool swap_erase_done = false;
+ bool data_erase_done = false;
+
+ switch (checkpoint)
+ {
+ case CHECKPOINT_0:
+ {
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_1, (void *)PSM_COMPACTION_MAX);
+ /* Swap needs to be erased */
+ uint32_t swap_start_offset = psm_get_swap_start_offset(psm);
+ uint32_t swap_size = part_size(psm) - swap_start_offset;
+ rv = psm_erase_flash(psm, swap_start_offset, swap_size);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("CHK-0: Cannot erase swap area");
+ return -WM_FAIL;
+ }
+
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_2, (void *)PSM_COMPACTION_MAX);
+ swap_erase_done = true;
+ memset(swap_desc, 0xFF, sizeof(psm_swap_desc_t));
+ swap_desc->swap_start_offset = swap_start_offset;
+ swap_desc->swap_start_offset_inv = ~swap_start_offset;
+ /* Leave checkpoint marker uninit'ed */
+ rv = write_swap_descriptor(psm, swap_desc, true);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("CHK-0: Cannot write swap descriptor");
+ return -WM_FAIL;
+ }
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_3, (void *)PSM_COMPACTION_MAX);
+ checkpoint = CHECKPOINT_1;
+ psm_d("Swap des successfully written. Crossing CHK-1");
+ }
+ /* Fall through */
+ case CHECKPOINT_1:
+ {
+ if (!swap_erase_done)
+ {
+ psm_d("Direct jump to chkpt 1 not supported");
+ return -WM_FAIL;
+ }
+
+ uint32_t data_offset = 0;
+ uint32_t data_limit = psm->data_free_offset;
+
+ uint32_t swap_data_offset = swap_desc->swap_start_offset + PSM_DATA_SWAP_DEMARCATION;
+ uint32_t swap_limit = part_size(psm) - sizeof(psm_swap_desc_t);
+
+ rv = psm_copy_all_objects(psm, checkpoint, data_offset, data_limit, swap_data_offset, swap_limit);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("CHK-1: copy/upgrade to swap failed");
+ return rv;
+ }
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_5, (void *)PSM_COMPACTION_MAX);
+
+ swap_desc->checkpoint_marker = CHECKPOINT_MARKER;
+ swap_desc->checkpoint_marker_inv = ~CHECKPOINT_MARKER;
+ rv = write_swap_descriptor(psm, swap_desc, false);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("CHK-1: Can't write swap desc marker");
+ return -WM_FAIL;
+ }
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_6, (void *)PSM_COMPACTION_MAX);
+ checkpoint = CHECKPOINT_2;
+ psm_d("Swap now has all objects. Crossing CHK-2");
+ }
+ /* Fall through */
+ case CHECKPOINT_2:
+ {
+ /*
+ * Swap descriptor is fully valid and data area
+ * state is unknown. In this state compaction
+ * process will have to continue irrespective of
+ * caller request.
+ */
+ rv = psm_erase_flash(psm, 0, swap_desc->swap_start_offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to erase data section");
+ return rv;
+ }
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_7, (void *)PSM_COMPACTION_MAX);
+ data_erase_done = true;
+
+ uint32_t swap_data_offset = swap_desc->swap_start_offset + PSM_DATA_SWAP_DEMARCATION;
+ uint32_t swap_limit = part_size(psm) - sizeof(psm_swap_desc_t);
+
+ uint32_t data_offset = 0;
+ uint32_t data_limit = swap_desc->swap_start_offset;
+
+ rv = psm_copy_all_objects(psm, checkpoint, swap_data_offset, swap_limit, data_offset, data_limit);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("CHK-2: swap copy to data failed");
+ return rv;
+ }
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_8, (void *)PSM_COMPACTION_MAX);
+ rv = invalidate_swap_descriptor(psm);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("CHK-2: swap invalidation failed");
+ return rv;
+ }
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_9, (void *)PSM_COMPACTION_MAX);
+ checkpoint = CHECKPOINT_3;
+ psm_d("All objs copied to data area. Crossing CHK-3");
+ }
+ /* Fall through */
+ case CHECKPOINT_3:
+ {
+ /*
+ * Swap descriptor is invalid. Cleanup the swap area.
+ */
+ uint32_t erase_start;
+ if (!data_erase_done)
+ {
+ erase_start = get_erase_start_offset(psm);
+ }
+ else
+ {
+ /* Fall through case */
+ erase_start = swap_desc->swap_start_offset;
+ }
+
+ rv = psm_erase_flash(psm, erase_start, part_size(psm) - erase_start);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("CHK-3 erase failed");
+ return -WM_FAIL;
+ }
+ if (g_psm_event_cb)
+ g_psm_event_cb(PSM_EVENT_COMPACTION, (void *)PSM_COMPACTION_10, (void *)PSM_COMPACTION_MAX);
+ checkpoint = CHECKPOINT_4;
+ psm_d("Swap area is now erased. Crossing CHK-4");
+ }
+ break;
+ case CHECKPOINT_4:
+ /* No-op */
+ break;
+ default:
+ psm_d("Unknown checkpoint: %d", checkpoint);
+ return -WM_FAIL;
+ break;
+ }
+
+ return WM_SUCCESS;
+}
+
+/*
+ * 1: Match
+ * 0: No match
+ * < 0: Error
+ *
+ * 'pobj' is passed because this function should only read name length
+ * equal to actually present in flash.
+ */
+static int read_and_match_name(psm_t *psm, const psm_object_t *pobj, const char *name, uint32_t offset)
+{
+ /* We have ensured that user given and flash name is same in length */
+ char buf[READ_BUFFER_SIZE];
+
+ uint32_t read_size, index;
+ for (index = 0; index < pobj->name_len; index += read_size)
+ {
+ uint32_t remaining = pobj->name_len - index;
+ read_size = remaining > READ_BUFFER_SIZE ? READ_BUFFER_SIZE : remaining;
+ int rv = psm_read_flash(psm, buf, read_size, offset + index);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to read name data @ off: %x", offset);
+ return rv;
+ }
+
+ if (memcmp(&name[index], buf, read_size))
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * Returns:
+ * 2 : Object found and matched.
+ * 1 : An object found but no match.
+ * 0 : No PSM object found.
+ * < 0: Error
+ */
+static int read_and_match_object(psm_t *psm,
+ psm_object_t *pobj,
+ objectid_t *obj_id,
+ const char *name,
+ uint32_t name_len,
+ uint32_t offset,
+ uint32_t limit)
+{
+ int rv = psm_read_flash(psm, pobj, sizeof(psm_object_t), offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("could not read object @ off: %x", offset);
+ return rv;
+ }
+
+ if (psm_is_free_space(pobj))
+ return 0;
+
+ if (pobj->object_type != OBJECT_TYPE_SMALL_BINARY)
+ {
+ psm_d("Object type not valid @ off %x", offset);
+ return 0;
+ }
+
+ /* An object is definately present */
+ if (*obj_id == PSM_INVALID_OBJ_ID)
+ {
+ /* No mapping has been done yet */
+ if (pobj->name_len == 0)
+ {
+ psm_d("Object with name length 0 is not supported");
+ return -WM_FAIL;
+ }
+
+ /* Need to use name to match */
+ if (name_len != pobj->name_len)
+ return 1;
+
+ rv = read_and_match_name(psm, pobj, name, offset + sizeof(psm_object_t));
+ if (rv < 0)
+ return rv;
+
+ if (rv == 0)
+ return 1;
+
+ /* Name has matched */
+ *obj_id = pobj->obj_id;
+ }
+ else
+ {
+ /* A name to obj_id was already done before */
+ if (*obj_id != pobj->obj_id)
+ return 1;
+ }
+
+ if (is_object_active(pobj))
+ {
+ psm_d("Object active and matched");
+ return 2;
+ }
+
+ return 1;
+}
+
+/*
+ * 'pobj' will be populated only if found and cache was not present.
+ */
+static psm_index_t *psm_search_index(psm_t *psm, const char *name, uint32_t name_len, psm_object_t *pobj)
+{
+ psm_entry_i("name: %s", name);
+ psm_index_t *index = NULL;
+ uint32_t name_hash = soft_crc32(name, name_len, 0);
+ int cnt;
+ for (cnt = 0; cnt < psm->index_elements; cnt++)
+ {
+ index = &psm->index[cnt];
+ psm_i("Check: obj_id: %x H: %x: %x", index->obj_id, name_hash, index->name_hash);
+ if (name_hash != index->name_hash)
+ continue;
+
+ psm_i("Hash match: obj_id: %x", index->obj_id);
+ /*
+ * Name_Hash has matched but there could be a collision. We
+ * need to probe more. If a cache is present the task is
+ * simpler. If not we will have to read the name field from
+ * the object stored in flash.
+ */
+ if (index->cache)
+ {
+ psm_i("Cache available: obj_id: %x", index->obj_id);
+ /* Cache is present */
+ psm_cache_t *cache = index->cache;
+ if (name_len != cache->name_len)
+ continue;
+
+ psm_i("Cache: check name match: %s", name);
+ uint8_t *name_buf = (uint8_t *)(cache + 1);
+ if (memcmp(name, name_buf, name_len))
+ continue; /* No match */
+
+ psm_i("Cache: name matched");
+ /*
+ * Name has matched. Since cache is there flash
+ * is not supposed to be accessed and thus 'pobj'
+ * will not be populated. Caller to should care.
+ */
+ return index;
+ }
+
+ psm_i("Index: Check name match by accessing flash object");
+ /* No cache is present. Need to access flash object */
+ int rv = psm_read_flash(psm, pobj, sizeof(psm_object_t), index->flash_offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: Unable to read flash", __func__);
+ break;
+ }
+
+ if (name_len != pobj->name_len)
+ {
+ /* Mismatch */
+ psm_i("Name hash matched but name len mismatch");
+ continue;
+ }
+
+ rv = read_and_match_name(psm, pobj, name, index->flash_offset + sizeof(psm_object_t));
+ if (rv < 0)
+ {
+ psm_i("Error during name match: %d", rv);
+ break;
+ }
+
+ if (rv == 1)
+ {
+ psm_i("Object %d found in index", pobj->obj_id);
+ /* A match is found */
+ return index;
+ }
+
+ /* Mismatch */
+ psm_i("Name hash matched but name mismatch");
+ }
+
+ return NULL;
+}
+
+static void psm_remove_index_entry(psm_t *psm, psm_index_t *index)
+{
+ psm_i("Removing object: %d from index", index->obj_id);
+
+ if (index->cache)
+ {
+ psm_i("Freeing object %d cache", index->obj_id);
+ os_mem_free(index->cache);
+ }
+
+ uint32_t cnt = index - psm->index;
+ if (cnt == (psm->index_elements - 1))
+ {
+ /* Last entry is to be deleted */
+ psm->index_elements--;
+ }
+ else
+ {
+ uint32_t later_index_count = psm->index_elements - cnt - 1;
+ memmove(index, index + 1, (sizeof(psm_index_t) * later_index_count));
+ psm->index_elements--;
+ }
+}
+
+static int search_active_object(psm_t *psm,
+ psm_object_t *pobj,
+ const char *name,
+ uint32_t name_len,
+ uint32_t *flash_offset,
+ bool *found,
+ objectid_t *obj_id,
+ psm_index_t **index)
+{
+ psm_entry_i("%s", name);
+
+ *index = NULL;
+ if (psm->index)
+ {
+ *index = psm_search_index(psm, name, name_len, pobj);
+ if (*index != NULL)
+ {
+ /* Object found in index */
+ *flash_offset = (*index)->flash_offset;
+ *found = true;
+
+ /*
+ * Load pobj with some values cached. This is tied
+ * to implementation of function psm_object_open()
+ * and keep this always in sync with that
+ * implementation.
+ */
+ pobj->obj_id = (*index)->obj_id;
+ if ((*index)->cache)
+ {
+ pobj->data_len = (*index)->cache->data_len;
+ pobj->name_len = (*index)->cache->name_len;
+ }
+
+ psm_ed("Index matched for %s", name);
+ return WM_SUCCESS;
+ }
+
+ psm_i("Index miss");
+ }
+
+ uint32_t offset = 0;
+ /*
+ * Don't try reading flash if remaining size is less than
+ * necessary.
+ */
+ uint32_t limit = psm->object_offset_limit;
+
+ /* Set default not found */
+ *found = false;
+
+ while (offset < limit)
+ {
+ int rv = read_and_match_object(psm, pobj, obj_id, name, name_len, offset, limit);
+ if (rv < 0)
+ {
+ psm_d("Failure during object search");
+ return rv;
+ }
+
+ if (rv == 0)
+ {
+ psm_d("No more PSM objects");
+ return WM_SUCCESS;
+ }
+
+ if (rv == 2)
+ {
+ /* Object found */
+ *flash_offset = offset;
+ *found = true;
+ return WM_SUCCESS;
+ }
+
+ offset += object_size(pobj);
+ }
+
+ return WM_SUCCESS;
+}
+
+static void psm_init_new_object(psm_t *psm,
+ psm_objinfo_t *objinfo,
+ objectid_t obj_id,
+ uint32_t name_len,
+ psm_objattrib_t *attribs,
+ psm_mode_t mode,
+ uint32_t max_data_len)
+{
+ psm_entry_i("New obj: id: 0x%x", obj_id);
+ /* Re-use the object structure */
+ memset(objinfo, 0x00, sizeof(psm_objinfo_t));
+ /* Init all 0xFF as per flash properties */
+ memset(&objinfo->pobj, 0xFF, sizeof(psm_object_t));
+
+ objinfo->psm = psm;
+ objinfo->mode = mode;
+ objinfo->max_data_len = max_data_len;
+
+ objinfo->pobj.object_type = OBJECT_TYPE_SMALL_BINARY;
+ if (attribs)
+ {
+ if (attribs->flags & PSM_INDEXING_ENABLED)
+ objinfo->pobj.flags &= ~PSM_OBJ_INDEX_REQ;
+ if (attribs->flags & PSM_CACHING_ENABLED)
+ objinfo->pobj.flags &= ~PSM_OBJ_CACHE_REQ;
+ }
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ set_object_secure(&(objinfo->pobj));
+ else
+ clear_object_secure(&(objinfo->pobj));
+#endif /* CONFIG_SECURE_PSM */
+
+ /* Keep data length uninitialized i.e. all bytes to 0xFF */
+ objinfo->pobj.name_len = name_len;
+ objinfo->pobj.obj_id = obj_id;
+}
+
+static int manage_space_constraints(psm_t *psm, uint32_t new_obj_size, bool *compaction_reqd)
+{
+ psm_entry_i("new_obj_size: %d", new_obj_size);
+
+ if (compaction_reqd)
+ *compaction_reqd = false;
+
+ if (!psm_is_data_len_sane(psm, new_obj_size))
+ {
+ psm_d("data length invalid for new object: %u", new_obj_size);
+ return -WM_E_INVAL;
+ }
+
+ uint32_t proposed_active_objects_size = psm->total_active_object_size + new_obj_size;
+ uint32_t proposed_swap_start_offset = align_to_block_offset(
+ psm, (part_size(psm) - sizeof(psm_swap_desc_t) - PSM_DATA_SWAP_DEMARCATION - proposed_active_objects_size));
+ uint32_t proposed_data_free_offset = psm->data_free_offset + new_obj_size;
+
+ if (proposed_data_free_offset < proposed_swap_start_offset)
+ return WM_SUCCESS;
+
+ /*
+ * If we allow write of this object _no_ space will be left
+ * for swap handling. Check if compaction will help
+ */
+ if (proposed_active_objects_size > proposed_swap_start_offset)
+ {
+ /* Compaction will also _not_ help */
+ psm_d("Compaction will not help");
+ return -WM_E_NOSPC;
+ }
+
+ /* Compaction will help */
+ if (compaction_reqd)
+ {
+ *compaction_reqd = true;
+ return WM_SUCCESS;
+ }
+
+ /* Return error as we could not signal compaction reqd status */
+ return -WM_FAIL;
+}
+
+static int psm_part_compact(psm_t *psm)
+{
+ psm_d("Compaction needs to be done to accomodate");
+ psm_swap_desc_t swap_desc;
+ int rv = handle_recovery(psm, CHECKPOINT_0, &swap_desc);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: compaction failed", __func__);
+ return rv;
+ }
+
+ /* Need to scan again as flash layout has changed */
+ rv = psm_part_scan(psm);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: Could not scan", __func__);
+ return rv;
+ }
+
+ return WM_SUCCESS;
+}
+
+static int _psm_object_open(psm_t *psm,
+ psm_objinfo_t *objinfo,
+ const char *name,
+ psm_mode_t mode,
+ uint32_t max_data_len,
+ psm_objattrib_t *attribs)
+{
+ psm_entry_i("name: %s mode: %d max_data_len = %d", name, mode, max_data_len);
+
+ uint32_t name_len = strnlen(name, PSM_MAX_OBJNAME_LEN + 1);
+ if (!name_len || name_len > PSM_MAX_OBJNAME_LEN)
+ {
+ psm_d("name length invalid: %d", name_len);
+ return -WM_E_INVAL;
+ }
+
+ int rv;
+ if (mode == PSM_MODE_WRITE)
+ {
+ if (part_readonly(psm))
+ return -WM_E_PERM;
+
+ bool compaction_reqd;
+ rv = manage_space_constraints(psm, sizeof(psm_object_t) + name_len + max_data_len, &compaction_reqd);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Unable to alloc space for new obj size: %u", max_data_len);
+ return rv;
+ }
+
+ if (compaction_reqd)
+ {
+ rv = psm_part_compact(psm);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d(
+ "Compaction to alloc space for new "
+ "obj size: %u failed",
+ max_data_len);
+ return rv;
+ }
+ }
+ }
+
+ memset(objinfo, 0x00, sizeof(psm_objinfo_t));
+
+ /* The object may be already be present. */
+ bool found;
+ uint32_t flash_offset;
+ psm_index_t *index = NULL;
+ objectid_t obj_id = PSM_INVALID_OBJ_ID;
+ const void *name_to_search = name;
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ {
+ rv = resetkey(psm, SET_ENCRYPTION_KEY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("reset enc key (name) fail");
+ return rv;
+ }
+
+ rv = encrypt_buf(psm, name, psm->psm_name_enc_buf, name_len);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("enc name fail");
+ return rv;
+ }
+
+ /* Override 'name_to_search' */
+ name_to_search = psm->psm_name_enc_buf;
+ }
+#endif /* CONFIG_SECURE_PSM */
+
+ rv = search_active_object(psm, &objinfo->pobj, name_to_search, name_len, &flash_offset, &found, &obj_id, &index);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: Failed: %d", __func__, rv);
+ return rv;
+ }
+
+ objinfo->object_flash_offset = flash_offset;
+ objinfo->curr_flash_offset = flash_offset;
+ if (mode == PSM_MODE_READ)
+ {
+ if (!found)
+ {
+ psm_d("Object: %s not found for reading", name);
+ memset(objinfo, 0x00, sizeof(psm_objinfo_t));
+ return -WM_FAIL;
+ }
+
+ objinfo->psm = psm;
+ /* Point to start of data */
+ objinfo->curr_flash_offset += metadata_size(&objinfo->pobj);
+
+ /* Since name has already matched calculate CRC32 using
+ user name buffer */
+ objinfo->crc32 = soft_crc32(name_to_search, name_len, 0);
+ objinfo->mode = mode;
+ objinfo->index = index;
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ {
+ /*
+ * A Dummy decryption is needed. Since "name +
+ * data" are encrypted in that sequence the
+ * decryption also need to happen in that
+ * sequence. Since we have already encrypted the
+ * name field we can decrypt it here.
+ */
+ rv = resetkey(psm, SET_DECRYPTION_KEY);
+ if (rv)
+ return rv;
+
+ /* The 'psm_name_enc_buf' will not be used after
+ this. Re-use that buffer.
+ */
+ rv = decrypt_buf(psm, psm->psm_name_enc_buf, psm->psm_name_enc_buf, name_len);
+ if (rv)
+ return rv;
+ }
+#endif /* CONFIG_SECURE_PSM */
+
+ return WM_SUCCESS;
+ }
+
+ objectid_t old_obj_id;
+ uint32_t old_object_flash_offset;
+ if (found)
+ {
+ psm_d("Existing object %s is found.", name);
+ /* Cache the needed values before re-using object */
+ old_obj_id = objinfo->pobj.obj_id;
+ old_object_flash_offset = objinfo->object_flash_offset;
+ uint32_t old_object_size = object_size(&objinfo->pobj);
+ psm_init_new_object(psm, objinfo, old_obj_id, name_len, attribs, mode, max_data_len);
+ objinfo->old_active_object_present = true;
+ objinfo->old_object_flash_offset = old_object_flash_offset;
+ objinfo->old_object_size = old_object_size;
+ }
+ else
+ {
+ if (!psm_is_objid_available(psm))
+ {
+ /* No space */
+ psm_d("No space for new objects. No more object ID's");
+ return -WM_E_NOSPC;
+ }
+
+ /*
+ * It is possible that active object is not found but an
+ * inactive object was present.
+ */
+ objectid_t new_obj_id = (obj_id == PSM_INVALID_OBJ_ID) ? psm_get_unused_obj_id(psm) : obj_id;
+ /* Brand new object */
+ psm_init_new_object(psm, objinfo, new_obj_id, name_len, attribs, mode, max_data_len);
+ }
+
+ objinfo->object_flash_offset = psm->data_free_offset;
+ objinfo->curr_flash_offset = psm->data_free_offset;
+
+ /* Write the metadata structure. Keep data length as undefined
+ for now */
+ psm_d("Writing metadata");
+ rv = psm_write_flash(psm, &objinfo->pobj, sizeof(psm_object_t), objinfo->curr_flash_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: metadata write failed.", __func__);
+ return rv;
+ }
+
+ /* Initialize length to 0 after object has been written */
+ objinfo->pobj.data_len = 0;
+
+ objinfo->curr_flash_offset += sizeof(psm_object_t);
+
+ /* Write name field */
+ psm_d("Writing name field");
+
+ rv = psm_write_flash(psm, name_to_search, name_len, objinfo->curr_flash_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: metadata write failed.", __func__);
+ return rv;
+ }
+
+ /* Start CRC calculation with name field */
+ objinfo->pobj.crc32 = soft_crc32(name_to_search, name_len, 0);
+
+ objinfo->curr_flash_offset += name_len;
+
+ if (index)
+ psm_remove_index_entry(psm, index);
+ return WM_SUCCESS;
+}
+
+static int _psm_object_write(psm_t *psm, psm_objinfo_t *objinfo, const uint8_t *data, uint32_t len)
+{
+ psm_object_t *pobj = &objinfo->pobj;
+ psm_entry_i("id: %x len: %d", pobj->obj_id, len);
+ int rv;
+
+ if (len == 0)
+ {
+ psm_d("Ignoring zero length write");
+ return WM_SUCCESS;
+ }
+
+ uint32_t max_allowed_len = objinfo->max_data_len - pobj->data_len;
+
+ if (max_allowed_len < len)
+ {
+ psm_d("Write failed. Write more than requested: %d: %d", max_allowed_len, len);
+ return -WM_E_NOSPC;
+ }
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ {
+ int data_remaining = len;
+ int offset = 0;
+ while (data_remaining)
+ {
+ int enc_len = data_remaining > READ_BUFFER_SIZE ? READ_BUFFER_SIZE : data_remaining;
+
+ rv = encrypt_buf(psm, data + offset, psm->psm_enc_buf, enc_len);
+ if (rv)
+ {
+ psm_d("%s: encryption failed", __func__);
+ return rv;
+ }
+
+ rv = psm_write_flash(psm, psm->psm_enc_buf, enc_len, objinfo->curr_flash_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: Write failed", __func__);
+ return rv;
+ }
+ pobj->crc32 = soft_crc32(psm->psm_enc_buf, enc_len, pobj->crc32);
+ objinfo->curr_flash_offset += enc_len;
+
+ offset += enc_len;
+ data_remaining -= enc_len;
+ }
+
+ pobj->data_len += len;
+ psm_d("Wrote %d bytes of data", len);
+ return WM_SUCCESS;
+ }
+#endif
+ rv = psm_write_flash(psm, data, len, objinfo->curr_flash_offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: Write failed", __func__);
+ return rv;
+ }
+
+ /* Update CRC32 */
+ pobj->crc32 = soft_crc32(data, len, pobj->crc32);
+
+ objinfo->curr_flash_offset += len;
+ pobj->data_len += len;
+
+ psm_d("Wrote %d bytes of data", len);
+ return WM_SUCCESS;
+}
+
+static int _psm_object_read(psm_t *psm, psm_objinfo_t *objinfo, uint8_t *buf, uint32_t max_len)
+{
+ psm_object_t *pobj = &objinfo->pobj;
+ psm_entry_i("obj-id: %x mode: %d max_len: %d", pobj->obj_id, objinfo->mode, max_len);
+ int rv;
+
+ if (!max_len)
+ {
+ psm_d("Ignoring zero length read");
+ return WM_SUCCESS;
+ }
+
+ const uint32_t data_start_offset = objinfo->object_flash_offset + metadata_size(pobj);
+ uint32_t remaining = pobj->data_len - (objinfo->curr_flash_offset - data_start_offset);
+ if (remaining == 0)
+ {
+ psm_d("no data to read");
+ return 0;
+ }
+
+ uint32_t read_size = remaining > max_len ? max_len : remaining;
+
+ if (objinfo->index && objinfo->index->cache)
+ {
+ psm_cache_t *cache = objinfo->index->cache;
+ uint8_t *name_buf = (uint8_t *)(cache + 1);
+ uint8_t *data_buf = name_buf + cache->name_len;
+
+ uint32_t read_offset = pobj->data_len - remaining;
+ memcpy(buf, &data_buf[read_offset], read_size);
+ goto skip_actual_flash_read;
+ }
+
+ rv = psm_read_flash(psm, buf, read_size, objinfo->curr_flash_offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: read failed size: %d", __func__, read_size);
+ return rv;
+ }
+
+ objinfo->crc32 = soft_crc32(buf, read_size, objinfo->crc32);
+ /* Check if this is the last read */
+ if (remaining == read_size)
+ {
+ /*
+ * Since this is last read, CRC32 on-the-fly calculation is
+ * now done. Verification can be done now
+ */
+ objinfo->crc32 = psm_calc_metadata_crc32(&objinfo->pobj, objinfo->crc32);
+ if (objinfo->crc32 != pobj->crc32)
+ {
+ psm_d(
+ "Invalid CRC32 during read detected "
+ "0x%x != 0x%x",
+ objinfo->crc32, pobj->crc32);
+ return -WM_E_CRC;
+ }
+ }
+
+#ifdef CONFIG_SECURE_PSM
+ /* If read data is encrypted, decrypt it before sending back. */
+ if (part_encrypted(psm))
+ {
+ rv = decrypt_buf(psm, buf, buf, read_size);
+ if (rv)
+ return rv;
+ }
+#endif /* CONFIG_SECURE_PSM */
+
+skip_actual_flash_read:
+ objinfo->curr_flash_offset += read_size;
+ return read_size;
+}
+
+static int _psm_object_close(psm_t *psm, psm_objinfo_t *objinfo)
+{
+ psm_entry_i("obj-id: %d mode: %d", objinfo->pobj.obj_id, objinfo->mode);
+ if (objinfo->mode == PSM_MODE_READ)
+ {
+ psm_d("Object %d (opened in read mode) closed", objinfo->pobj.obj_id);
+ return WM_SUCCESS;
+ }
+
+ psm_object_t *pobj = &objinfo->pobj;
+ /*
+ * CRC32 of name and data is already done. Calculate CRC32 of
+ * metadata.
+ */
+ pobj->crc32 = psm_calc_metadata_crc32(pobj, pobj->crc32);
+
+ psm_d("Closing object: length: %d Crc32: 0x%x", pobj->data_len, pobj->crc32);
+ /* Write the crc32 and data length fields to flash */
+ uint32_t size = sizeof(pobj->crc32) + sizeof(pobj->data_len);
+ uint32_t offset = objinfo->object_flash_offset + offsetof(psm_object_t, crc32);
+ int rv = psm_write_flash(psm, &pobj->crc32, size, offset, PSM_WRITE_NO_VERIFY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d(
+ "Failed to update length and crc32 fields for "
+ "object: %d",
+ pobj->obj_id);
+ return rv;
+ }
+
+ psm->total_active_object_size += object_size(pobj);
+ psm_d("Checking if need to make earlier object inactive");
+ if (objinfo->old_active_object_present)
+ {
+ psm_d("Marking earlier object inactive");
+ /* Need to make earlier object inactive */
+ uint32_t flag_offset = objinfo->old_object_flash_offset + offsetof(psm_object_t, flags);
+ rv = write_flag_bit(psm, flag_offset, PSM_OBJ_INACTIVE);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to make earlier object inactive");
+ }
+
+ /* Earlier object size can be reduced */
+ psm->total_active_object_size -= objinfo->old_object_size;
+ objinfo->old_object_flash_offset = 0;
+ }
+
+ /* For benefit of next object */
+ psm->data_free_offset += object_size(&objinfo->pobj);
+
+ if (is_object_indexable(pobj)) /* Ignore any error */
+ psm_add_to_index(psm, pobj, objinfo->object_flash_offset);
+ return WM_SUCCESS;
+}
+
+int psm_object_read(psm_object_handle_t ohandle, void *buf, uint32_t max_len)
+{
+ psm_entry();
+ if (!ohandle || !buf || !max_len)
+ {
+ psm_d("%s: Invalid arguments", __func__);
+ return -WM_E_INVAL;
+ }
+
+ psm_objinfo_t *objinfo = (psm_objinfo_t *)ohandle;
+ psm_t *psm = objinfo->psm;
+ return _psm_object_read(psm, objinfo, buf, max_len);
+}
+
+int psm_object_write(psm_object_handle_t ohandle, const void *buf, uint32_t len)
+{
+ psm_entry();
+ if (!ohandle || !buf || !len)
+ {
+ psm_d("%s: Invalid arguments", __func__);
+ return -WM_E_INVAL;
+ }
+
+ psm_objinfo_t *objinfo = (psm_objinfo_t *)ohandle;
+ psm_t *psm = objinfo->psm;
+ if (objinfo->mode != PSM_MODE_WRITE)
+ {
+ psm_d("Cannot write in read mode");
+ return -WM_E_PERM;
+ }
+
+ return _psm_object_write(psm, objinfo, buf, len);
+}
+
+int psm_object_open(psm_hnd_t phandle,
+ const char *name,
+ psm_mode_t mode,
+ uint32_t max_data_len,
+ psm_objattrib_t *attribs,
+ psm_object_handle_t *ohandle)
+{
+ psm_entry("name: %s mode: %d", name, mode);
+ if (!phandle || !name || !ohandle)
+ {
+ psm_d("%s: Invalid arguments", __func__);
+ return -WM_E_INVAL;
+ }
+
+ *ohandle = 0;
+ psm_t *psm = (psm_t *)phandle;
+
+ if (mode == PSM_MODE_WRITE)
+ {
+ if (!psm_is_data_len_sane(psm, max_data_len))
+ {
+ psm_d("Unsupported data length for new object: %u", max_data_len);
+ return -WM_E_INVAL;
+ }
+ }
+
+ if (attribs)
+ if (attribs->flags & PSM_CACHING_ENABLED)
+ attribs->flags |= PSM_INDEXING_ENABLED;
+
+ psm_rwlock_part(psm, mode);
+
+ psm_objinfo_t *objinfo = os_mem_calloc(sizeof(psm_objinfo_t));
+ if (!objinfo)
+ {
+ psm_rwunlock_part(psm, mode);
+ psm_d("unable to alloc psm object");
+ return -WM_E_NOMEM;
+ }
+
+ int rv = _psm_object_open(psm, objinfo, name, mode, max_data_len, attribs);
+ if (rv != WM_SUCCESS)
+ {
+ os_mem_free(objinfo);
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ *ohandle = (psm_object_handle_t)objinfo;
+
+ if (mode == PSM_MODE_WRITE)
+ return WM_SUCCESS;
+ else /* READ Mode */
+ return objinfo->pobj.data_len;
+}
+
+static int _psm_object_delete(psm_t *psm, const char *name, uint32_t name_len)
+{
+ psm_entry_i();
+ bool found;
+ psm_object_t pobj;
+ psm_index_t *index = NULL;
+ uint32_t flash_offset;
+ objectid_t obj_id = PSM_INVALID_OBJ_ID;
+ const void *name_to_search = name;
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ {
+ int rv = resetkey(psm, SET_ENCRYPTION_KEY);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("d: reset enc key (name) fail");
+ return rv;
+ }
+
+ rv = encrypt_buf(psm, name, psm->psm_name_enc_buf, name_len);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("d: enc name fail");
+ return rv;
+ }
+
+ /* Override 'name_to_search' */
+ name_to_search = psm->psm_name_enc_buf;
+ }
+#endif /* CONFIG_SECURE_PSM */
+
+ int rv = search_active_object(psm, &pobj, name_to_search, name_len, &flash_offset, &found, &obj_id, &index);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: Failure during search: %d", __func__, rv);
+ return rv;
+ }
+
+ if (!found)
+ {
+ psm_d("Object \"%s\" not found to delete", name);
+ return WM_SUCCESS;
+ }
+
+ psm_d("Deleting object \"%s\" by making it inactive", name);
+ /* Need to make earlier object inactive */
+ uint32_t flag_offset = flash_offset + offsetof(psm_object_t, flags);
+ rv = write_flag_bit(psm, flag_offset, PSM_OBJ_INACTIVE);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("%s: Failed to make object inactive", __func__);
+ return rv;
+ }
+
+ /* Reduce the size counter */
+ psm->total_active_object_size -= object_size(&pobj);
+
+ if (index)
+ psm_remove_index_entry(psm, index);
+ return rv;
+}
+
+int psm_object_delete(psm_hnd_t phandle, const char *name)
+{
+ psm_entry("name: %s", name);
+ if (!phandle || !name)
+ {
+ psm_d("Invalid arguments");
+ return -WM_E_INVAL;
+ }
+
+ uint32_t name_len = strnlen(name, PSM_MAX_OBJNAME_LEN + 1);
+ if (!name_len || name_len > PSM_MAX_OBJNAME_LEN)
+ {
+ psm_d("%s: name length invalid: %d", __func__, name_len);
+ return -WM_E_INVAL;
+ }
+
+ psm_t *psm = (psm_t *)phandle;
+ psm_rwlock_part(psm, PSM_MODE_WRITE);
+ int rv = _psm_object_delete(psm, name, name_len);
+ psm_rwunlock_part(psm, PSM_MODE_WRITE);
+
+ return rv;
+}
+
+int psm_object_close(psm_object_handle_t *ohandle)
+{
+ psm_entry();
+ if (!ohandle)
+ {
+ psm_d("%s: Invalid argument", __func__);
+ return -WM_E_INVAL;
+ }
+
+ psm_objinfo_t *objinfo = (psm_objinfo_t *)*ohandle;
+
+ /* Save necessary variables before objinfo is freed */
+ psm_t *psm = objinfo->psm;
+ psm_mode_t mode = objinfo->mode;
+
+ int rv = _psm_object_close(psm, objinfo);
+
+ psm_rwunlock_part(psm, mode);
+
+ memset(objinfo, 0x00, sizeof(psm_objinfo_t));
+ os_mem_free(objinfo);
+
+ *ohandle = 0;
+ return rv;
+}
+
+static int _psm_init_verify_params(const flash_desc_t *fdesc, uint32_t block_size, psm_cfg_t *psm_cfg)
+{
+ if (!fdesc->fl_size)
+ {
+ psm_d("Zero sized partition given");
+ return -WM_E_INVAL;
+ }
+
+ uint32_t block_cnt = fdesc->fl_size / block_size;
+ /* With read/write capability atleast two blocks are required */
+ uint32_t min_block_cnt_req = 2;
+ if (psm_cfg && psm_cfg->read_only)
+ min_block_cnt_req = 1;
+
+ if (block_cnt < min_block_cnt_req)
+ {
+ psm_d("Atleast %d block(s) are required for PSM operation", min_block_cnt_req);
+ return -WM_E_PERM;
+ }
+
+ /* Basic sanity check */
+ if (block_size < 64)
+ {
+ psm_d("Block size %d is too less\r\n", block_size);
+ return -WM_E_INVAL;
+ }
+
+ return WM_SUCCESS;
+}
+
+static int deduce_checkpoint_at_init(psm_t *psm, psm_swap_desc_t *swap_desc, checkpoint_t *checkpoint)
+{
+ psm_entry_i();
+
+ int rv = read_swap_descriptor(psm, swap_desc);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Parititon check cannot start. Swap read failed");
+ return rv;
+ }
+
+ /* Check if all are 0xFF */
+ int index = 0;
+ uint8_t *ptr = (uint8_t *)swap_desc;
+ for (index = 0; index < sizeof(psm_swap_desc_t); index++)
+ if (ptr[index] != 0xFF)
+ break;
+
+ if (index == sizeof(psm_swap_desc_t))
+ {
+ /*
+ * Swap area is clean. This implies that no compaction was
+ * in progress.
+ */
+ *checkpoint = CHECKPOINT_4;
+ return WM_SUCCESS;
+ }
+
+ /*
+ * Swap has some data. If checkpoint marker is not valid it
+ * implies that compaction process did not complete after the last
+ * time it started. Set checkpoint such that only swap cleanup will
+ * be performed.
+ */
+ if (swap_desc->checkpoint_marker == (uint16_t)~swap_desc->checkpoint_marker_inv)
+ {
+ if (swap_desc->swap_start_offset == ~swap_desc->swap_start_offset_inv)
+ {
+ /*
+ * The descriptor is fully valid. This implies that
+ * compaction was interrupted after all objects
+ * were successfully copied to swap area. Now, we
+ * need to continue and copy them back to data area.
+ */
+ *checkpoint = CHECKPOINT_2;
+ return WM_SUCCESS;
+ }
+
+ /*
+ * This case is not expected because swap_start_offset is
+ * always written before checkpoint_marker. Lets erase the
+ * swap and cross our fingers.
+ */
+ *checkpoint = CHECKPOINT_3;
+ return WM_SUCCESS;
+ }
+
+ /*
+ * Swap descriptor is invalid. This implies that compaction process
+ * was incomplete. Data area is good. So only perform a cleanup of
+ * swap area.
+ */
+ *checkpoint = CHECKPOINT_3;
+ return WM_SUCCESS;
+}
+
+static int psm_module_physical_init(psm_t *psm)
+{
+ checkpoint_t checkpoint;
+ psm_swap_desc_t swap_desc;
+
+ int rv = deduce_checkpoint_at_init(psm, &swap_desc, &checkpoint);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("swap state check failed");
+ return rv;
+ }
+
+ psm_isc("Checkpoint: %d", checkpoint);
+ if (checkpoint != CHECKPOINT_2)
+ {
+ /* Data area valid as per checkpoint. So, do a scan */
+ rv = psm_part_scan(psm);
+ if (rv != WM_SUCCESS)
+ {
+ /*
+ * Since partition scan has failed it implies that
+ * something is amiss in the data area. Running
+ * compaction/upgrade may salvage intact objects.
+ */
+ psm_d(
+ "Partition scan failed. Will try compaction"
+ "/upgrade");
+
+ /* Check if space is available for compaction/upgrade */
+ bool compaction_reqd;
+ rv = manage_space_constraints(psm, 0, &compaction_reqd);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Unable to alloc space for swap");
+ return rv;
+ }
+
+ /* Force checkpoint and compaction */
+ checkpoint = CHECKPOINT_0;
+ }
+ }
+
+ rv = handle_recovery(psm, checkpoint, &swap_desc);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("unexpected error while compaction");
+ return rv;
+ }
+
+ /* Scan is pending */
+ if (checkpoint != CHECKPOINT_4)
+ {
+ rv = psm_part_scan(psm);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("psm scan failed after restoring swap to data");
+ return rv;
+ }
+ }
+
+ return rv;
+}
+
+static psm_t *_get_existing_psm_object(const flash_desc_t *fdesc)
+{
+ psm_list_t *list;
+
+ if (part_list.next == NULL)
+ {
+ /* This is the first partition to be init'ed */
+ PSM_List_Init(&part_list);
+ return NULL;
+ }
+
+ psm_t *psm;
+ for (list = part_list.next; list != &part_list; list = list->next)
+ {
+ psm = PSM_LIST_OBJ(psm_t *, node, list);
+ if (psm->fdesc_fl_dev == fdesc->fl_dev && psm->start_address == fdesc->fl_start)
+ {
+ /*
+ * There is a PSM already registered for this start
+ * address.
+ */
+ psm_w("Using existing psm object");
+ return psm;
+ }
+ }
+
+ return NULL;
+}
+
+int psm_module_init(flash_desc_t *fdesc, psm_hnd_t *phandle, psm_cfg_t *psm_cfg)
+{
+ if (!fdesc)
+ {
+ psm_d("%s: Invalid arguments", __func__);
+ return -WM_E_INVAL;
+ }
+
+ if (phandle)
+ *phandle = 0;
+
+ /*
+ * Check is PSM is already registered for received partition and
+ * return same handle.
+ */
+ int save = os_enter_critical_section(); /* We are working on a list */
+ psm_t *psm = _get_existing_psm_object(fdesc);
+ os_exit_critical_section(save);
+ if (psm)
+ {
+ if (phandle)
+ *phandle = (psm_hnd_t)psm;
+ return WM_SUCCESS;
+ }
+
+ psm_entry("start-address: 0x%x size: %d", fdesc->fl_start, fdesc->fl_size);
+
+ uint32_t block_size = psm_get_block_size();
+ int rv = _psm_init_verify_params(fdesc, block_size, psm_cfg);
+ if (rv != WM_SUCCESS)
+ return rv;
+
+ /* Allocate partition object. */
+ psm = os_mem_calloc(sizeof(psm_t));
+ if (!psm)
+ {
+ psm_d("cannot allocate PSM instance");
+ return -WM_E_NOMEM;
+ }
+
+ rv = psm_init_locks(psm);
+ if (rv != WM_SUCCESS)
+ {
+ os_mem_free(psm);
+ return rv;
+ }
+
+ if (psm_cfg)
+ memcpy(&psm->psm_cfg, psm_cfg, sizeof(psm_cfg_t));
+
+#ifdef CONFIG_SECURE_PSM
+ /* For test code only */
+ if (force_psm_secure)
+ psm->psm_cfg.secure = true;
+
+ if (psm->psm_cfg.keystore_override == false)
+ {
+ /* First check if keystore has a key */
+ rv = psm_security_init(&psm->psm_sec_hnd);
+ if (rv == WM_SUCCESS)
+ psm_d("Using key from keystore");
+ else if (rv == -WM_E_NOENT)
+ {
+ psm_d("No key in keystore. Try using key from app");
+ rv = psm_security_init_with_key(&psm->psm_sec_hnd, &psm->psm_cfg);
+ if (rv == WM_SUCCESS)
+ psm_d("Using key from app");
+ else if (rv == -WM_E_INVAL)
+ psm_e("No app key found");
+ }
+ }
+ else
+ {
+ /* Directly use app key, ignoring keystore key if any. */
+ rv = psm_security_init_with_key(&psm->psm_sec_hnd, &psm->psm_cfg);
+ if (rv == WM_SUCCESS)
+ psm_d("Using key from app");
+ else if (rv == -WM_E_INVAL)
+ psm_e("No app key found");
+ }
+
+ /* Return error only if partition is encrypted. */
+ if (part_encrypted(psm) && (rv != WM_SUCCESS))
+ {
+ psm_d("sec init failed");
+ psm_deinit_locks(psm);
+ memset(psm, 0x00, sizeof(psm_t));
+ os_mem_free(psm);
+ return rv;
+ }
+#endif /* CONFIG_SECURE_PSM */
+
+ psm->fdesc_fl_dev = fdesc->fl_dev;
+ psm->block_size = block_size;
+ psm->block_cnt = fdesc->fl_size / block_size;
+ psm->part_size = psm->block_size * psm->block_cnt;
+
+ psm->start_address = fdesc->fl_start;
+
+ if (!part_readonly(psm))
+ {
+ /* Leave atleast one block for swap */
+ psm->object_offset_limit = part_size(psm) - block_size(psm) - sizeof(psm_object_t);
+ }
+ else
+ {
+ psm->object_offset_limit = part_size(psm) - sizeof(psm_object_t);
+ }
+
+ psm_rwlock_part(psm, PSM_MODE_WRITE);
+ rv = psm_module_physical_init(psm);
+ if (rv != WM_SUCCESS)
+ {
+ psm_rwunlock_part(psm, PSM_MODE_WRITE);
+ psm_deinit_locks(psm);
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ psm_security_deinit(&psm->psm_sec_hnd);
+#endif
+ memset(psm, 0x00, sizeof(psm_t));
+ os_mem_free(psm);
+ return rv;
+ }
+ psm_rwunlock_part(psm, PSM_MODE_WRITE);
+
+ save = os_enter_critical_section();
+ PSM_List_AddTail(&part_list, &psm->node);
+ os_exit_critical_section(save);
+
+ if (phandle)
+ *phandle = (psm_hnd_t)psm;
+
+ return WM_SUCCESS;
+}
+
+int psm_module_deinit(psm_hnd_t *phandle)
+{
+ psm_entry();
+ if (!phandle)
+ {
+ psm_d("NULL psm handle");
+ return -WM_FAIL;
+ }
+
+ psm_t *psm = (psm_t *)*phandle;
+
+ /* Ensure that all others have exited */
+ psm_rwlock_part(psm, PSM_MODE_WRITE);
+ psm_rwunlock_part(psm, PSM_MODE_WRITE);
+
+ psm_reset_index(psm);
+ psm_deinit_locks(psm);
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ psm_security_deinit(&psm->psm_sec_hnd);
+#endif
+
+ /* Remove ourselves from the global list */
+ int save = os_enter_critical_section(); /* We are working on a list */
+ PSM_List_Remove(&psm->node);
+ os_exit_critical_section(save);
+
+ memset(psm, 0x00, sizeof(psm_t));
+ os_mem_free(psm);
+
+ return WM_SUCCESS;
+}
+
+int psm_module_init_ex(const psm_init_part_t *psm_init_part, psm_hnd_t *phandle)
+{
+ flash_desc_t fl;
+ int ret;
+ struct partition_entry *p;
+
+ ret = part_init();
+ if (ret != WM_SUCCESS)
+ {
+ return ret;
+ }
+
+ memset(&fl, 0, sizeof(flash_desc_t));
+ if (psm_init_part->pitype == PART_INFO_NAME)
+ {
+ p = part_get_layout_by_name(psm_init_part->part_info.name, NULL);
+ if (p == NULL)
+ return -WM_E_INVAL;
+ part_to_flash_desc(p, &fl);
+ }
+ else if (psm_init_part->pitype == PART_INFO_FL_DESC)
+ {
+ memcpy(&fl, psm_init_part->part_info.fl, sizeof(flash_desc_t));
+ if (!part_is_flash_desc_within_one_partition(&fl))
+ return -WM_E_INVAL;
+ }
+ else
+ return -WM_E_INVAL;
+
+ return psm_module_init(&fl, phandle, psm_init_part->psm_cfg);
+}
+
+int psm_format(psm_hnd_t phandle)
+{
+ psm_entry();
+ if (!phandle)
+ {
+ psm_d("NULL psm handle");
+ return -WM_E_INVAL;
+ }
+
+ psm_t *psm = (psm_t *)phandle;
+
+ psm_rwlock_part(psm, PSM_MODE_WRITE);
+ psm_reset_index(psm);
+
+ psm_d("Erasing psm partition");
+ int rv = psm_erase_flash(psm, 0, part_size(psm));
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Could not format");
+ psm_rwunlock_part(psm, PSM_MODE_WRITE);
+ return rv;
+ }
+
+ rv = psm_part_scan(psm);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Could not scan after format");
+ psm_rwunlock_part(psm, PSM_MODE_WRITE);
+ return rv;
+ }
+
+ psm_rwunlock_part(psm, PSM_MODE_WRITE);
+
+ return WM_SUCCESS;
+}
+
+int psm_set_variable(psm_hnd_t phandle, const char *variable, const void *value, uint32_t len)
+{
+ psm_entry("name: %s data-len: %d", variable, len);
+ if (!phandle || !variable || !value)
+ {
+ psm_d("%s: Invalid arguments", __func__);
+ return -WM_E_INVAL;
+ }
+
+ psm_t *psm = (psm_t *)phandle;
+ if (!psm_is_data_len_sane(psm, len))
+ {
+ psm_d("Unsupported data length for new object: %u", len);
+ return -WM_E_INVAL;
+ }
+
+ psm_mode_t mode = PSM_MODE_WRITE;
+ psm_rwlock_part(psm, mode);
+
+ psm_objinfo_t objinfo;
+ int rv = _psm_object_open(psm, &objinfo, variable, mode, len, NULL);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to open during set var-value");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ rv = _psm_object_write(psm, &objinfo, value, len);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to write during set var-value");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ rv = _psm_object_close(psm, &objinfo);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to close during set var-value");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ psm_rwunlock_part(psm, mode);
+ return WM_SUCCESS;
+}
+
+int psm_get_variable(psm_hnd_t phandle, const char *variable, void *value, uint32_t max_len)
+{
+ int read_len;
+
+ psm_entry("name: %s", variable);
+ if (!phandle || !variable || !value || !max_len)
+ {
+ psm_d("%s: Invalid arguments", __func__);
+ return -WM_E_INVAL;
+ }
+
+ psm_mode_t mode = PSM_MODE_READ;
+ psm_t *psm = (psm_t *)phandle;
+ psm_rwlock_part(psm, mode);
+
+ psm_objinfo_t objinfo;
+ int rv = _psm_object_open(psm, &objinfo, variable, mode, 0, NULL);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to open during get var-value");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ if (objinfo.pobj.data_len > max_len)
+ {
+ psm_d("%s: Variable value %d will not fit in given buffer %d", __func__, objinfo.pobj.data_len, max_len);
+
+ rv = _psm_object_close(psm, &objinfo);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to close during get var-value (NO_SPC)");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ rv = -WM_E_NOSPC;
+ goto psm_get_skip_read;
+ }
+
+ read_len = _psm_object_read(psm, &objinfo, value, max_len);
+ if (read_len < WM_SUCCESS)
+ {
+ psm_d("Failed to read during get var-value");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ rv = _psm_object_close(psm, &objinfo);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to close during get var-value");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ rv = read_len;
+psm_get_skip_read:
+ psm_rwunlock_part(psm, mode);
+ return rv;
+}
+
+int psm_get_variable_size(psm_hnd_t phandle, const char *variable)
+{
+ psm_entry("name: %s", variable);
+ if (!phandle || !variable)
+ {
+ psm_d("%s: Invalid arguments", __func__);
+ return -WM_E_INVAL;
+ }
+
+ psm_mode_t mode = PSM_MODE_READ;
+ psm_t *psm = (psm_t *)phandle;
+ psm_rwlock_part(psm, mode);
+
+ psm_objinfo_t objinfo;
+ int rv = _psm_object_open(psm, &objinfo, variable, mode, 0, NULL);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to open during get size");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ int obj_size = objinfo.pobj.data_len;
+ rv = _psm_object_close(psm, &objinfo);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to close during get size");
+ psm_rwunlock_part(psm, mode);
+ return rv;
+ }
+
+ psm_rwunlock_part(psm, mode);
+ return obj_size;
+}
+
+/* Only for testing interface */
+int psm_register_event_callback(psm_event_callback cb)
+{
+ g_psm_event_cb = cb;
+ return WM_SUCCESS;
+}
+
+/* Internal function. Only for testing. */
+void psm_secure_state(bool state)
+{
+#ifdef CONFIG_SECURE_PSM
+ force_psm_secure = state;
+#endif
+}
+
+bool is_psm_encrypted(psm_hnd_t phandle)
+{
+ psm_entry();
+ if (!phandle)
+ return -WM_E_INVAL;
+
+#ifdef CONFIG_SECURE_PSM
+ psm_t *psm = (psm_t *)phandle;
+ return part_encrypted(psm);
+#else
+ return false;
+#endif
+}
+
+/* return non-zero value to signify that user does not want more names */
+static int list_object(psm_t *psm, psm_object_t *pobj, uint32_t object_offset, psm_list_cb list_cb)
+{
+ if (pobj->name_len > READ_BUFFER_SIZE)
+ {
+ psm_d("name size more than buffer: %d", pobj->name_len);
+ return -WM_FAIL;
+ }
+
+ uint8_t buf[READ_BUFFER_SIZE + 1];
+ int rv;
+ uint32_t name_offset = object_offset + sizeof(psm_object_t);
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ {
+ rv = resetkey(psm, SET_DECRYPTION_KEY);
+ if (rv)
+ return -WM_FAIL;
+ }
+#endif
+
+ /* Read the name field */
+ rv = psm_read_flash(psm, buf, pobj->name_len, name_offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("Failed to read name field @ 0x%x", name_offset);
+ return -WM_FAIL;
+ }
+
+ /* NULL terminate */
+ buf[pobj->name_len] = 0;
+
+#ifdef CONFIG_SECURE_PSM
+ if (part_encrypted(psm))
+ {
+ rv = decrypt_buf(psm, buf, buf, pobj->name_len);
+ if (rv)
+ return -WM_FAIL;
+ }
+#endif
+
+ /* Pass on to the user through the callback */
+ return list_cb(buf);
+}
+
+static void _psm_objects_list(psm_t *psm, psm_list_cb list_cb)
+{
+ psm_entry_i();
+
+ uint32_t offset = 0;
+
+ /*
+ * Don't try reading flash if remaining size is less than
+ * necessary.
+ */
+ uint32_t limit = psm->object_offset_limit;
+ psm_object_t pobj;
+
+ while (offset < limit)
+ {
+ int rv = psm_read_flash(psm, &pobj, sizeof(psm_object_t), offset);
+ if (rv != WM_SUCCESS)
+ {
+ psm_d("list: could not read object @ off: %x", offset);
+ return;
+ }
+
+ if (psm_is_free_space(&pobj))
+ {
+ psm_d("Object list done");
+ break;
+ }
+
+ if (pobj.object_type != OBJECT_TYPE_SMALL_BINARY)
+ {
+ psm_d("Invalid object at the end of data area");
+ break;
+ }
+
+ if (!is_object_active(&pobj))
+ {
+ offset += object_size(&pobj);
+ continue;
+ }
+
+ if (!pobj.name_len)
+ {
+ psm_d("Zero name length objects not supported");
+ offset += object_size(&pobj);
+ continue;
+ }
+
+ rv = list_object(psm, &pobj, offset, list_cb);
+ if (rv != WM_SUCCESS)
+ break;
+
+ offset += object_size(&pobj);
+ }
+}
+
+void psm_objects_list(psm_hnd_t phandle, psm_list_cb list_cb)
+{
+ psm_entry();
+ if (!phandle)
+ return;
+
+ psm_t *psm = (psm_t *)phandle;
+
+ psm_rwlock_part(psm, PSM_MODE_READ);
+ _psm_objects_list(psm, list_cb);
+ psm_rwunlock_part(psm, PSM_MODE_READ);
+}
diff --git a/components/boot2_utils/psm-v2.h b/components/boot2_utils/psm-v2.h
new file mode 100644
index 000000000..1bd4d61bd
--- /dev/null
+++ b/components/boot2_utils/psm-v2.h
@@ -0,0 +1,829 @@
+/*
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+/** @file psm-v2.h
+ *
+ * @brief Persistent storage module version 2
+ *
+ * PSM (Persistent Storage Module) is a module which provides a PSM object
+ * abstraction layer over low level flash sector read/write operations. This is
+ * similar to how a filesystem provides a file abstraction over a block
+ * device driver.
+ *
+ * The PSM is specifically developed to work on flash memory devices which
+ * can be read/written on byte level but erases are possible only on block
+ * level. PSM helps reduce the flash usage thus helping in wear
+ * leveling. The working is described in brief as follows. A PSM object is
+ * an atomic structure on the flash and contains metadata and
+ * data (value). Metadata contains object name, length, etc. When an object
+ * value is changed a new object with same name is appended to the flash
+ * block instead of:
+ * - Backing up other objects
+ * - Erasing flash
+ * - Restoring objects
+ * - Writing new object.
+ *
+ * The earlier object with obsolete value will be inactivated and it is
+ * practically deleted from the PSM. It will be physically deleted during
+ * the compaction process.
+ *
+ * \section psm-v2_compaction Compaction process
+ *
+ * As new objects are appended to current objects a
+ * time will come when the flash space is close to getting full. At this
+ * point all the objects (excluding the inactivated ones) are copied to a
+ * special variable sized reserved area of the same flash partition. The
+ * data area i.e. the area of the partition which contained the active and
+ * inactive objects uptill now, is erased and the objects are copied back
+ * to data area. In effect, all obsolete objects are now physically deleted.
+ *
+ * During the process of compaction, or during new object write a power
+ * failure could occur. PSM is designed to handle this situation and has
+ * error recovery algorithms. It will ensure that no existing objects are
+ * corrupted and corrupted objects are safely removed during psm module
+ * initialization.
+ *
+ * The PSM module is designed to be able to read/write to arbitrary sized
+ * objects spanning multiple flash blocks. The only limitation is flash
+ * size and space reserved for compaction process.
+ *
+ * \section psm-v2_terminology Terminology
+ * Block
+ * -----
+ * This is the storage unit for the PSM. The size of a block has to
+ * be in multiples of sector size of the NOR flash chip used.
+ *
+ * \section psm-v2_mem_usage Memory usage of PSM module
+ *
+ * Flash space usage
+ * ------------------
+ * PSM has 12 bytes of overhead per PSM object. Thus,
+ * every PSM object size is: Data size (user defined) + name length (user
+ * defined) + 12 bytes (PSM defined).
+ *
+ * Heap usage
+ * ----------
+ * PSM init (psm_module_init()) allocates about 34 bytes for (internal) PSM
+ * singleton object. This object will be present on heap till
+ * psm_module_deinit() is called.
+ * psm_object_open() allocates about 46 bytes internally and remains
+ * allocated till psm_object_close() is called. If instead
+ * psm_set_variable() or psm_get_variable() is used no heap is used.
+ *
+ * \section psm-v2_thread Thread safety
+ * PSM module is designed to be completely thread safe. Even across
+ * multiple instances of PSM module (i.e. multiple psm_module_init()
+ * calls) on separate sections/partitions of flash. Only caveat is that low
+ * level flash driver also needs take care of thread safety if multiple PSM
+ * partitions are on the _same_ flash chip.
+ *
+ * \section psm-v2_readonly Read only usage
+ * In certain use cases it may be desired to use PSM in a read only
+ * mode. One of the benefits of this is that reserved space is not
+ * required and PSM can fit in lesser number of sectors. When the read only
+ * flag is passed to the psm_module_init(), PSM will run in read only mode
+ * for that partition and not allow any writes.
+ *
+ * \section psm-v2_usage Usage
+ *
+ * PSM provides two types of API's for separate use cases. First type
+ * (Simple case) is when the caller has entire value in a buffer for write
+ * or has a buffer size equal to entire data to be read. Second type (
+ * Advanced case) is when caller needs to read/write huge files in
+ * multiple KB's or MB's. In this case the caller needs an API which helps
+ * him read/write across multiple calls. Both the cases: are illustrated
+ * below.
+ *
+ * PSM initialization
+ * ------------------
+ * This needs to be done for both the simple and advanced case. It is
+ * generally done only once after boot.
+ *
+ * Statically/dynamically allocate and populate \ref flash_desc_t
+ * object. Note that this object needs to persist until psm_module_deinit()
+ * returns. PSM does _not_ make an internal copy of this object to avoid
+ * wasting space.
+ *
+ * \code
+ * psm_hnd_t phandle;
+ * int rv = psm_module_init(&ppart, &phandle, NULL);
+ * if (rv != WM_SUCCESS) {
+ * wmprintf("PSM init failed");
+ * return rv;
+ * }
+ * \endcode
+ *
+ * This handle 'phandle' can now be used for other API which require
+ * it. The third parameter is passed as NULL here. If any special flags
+ * need to be passed the \ref psm_cfg_t param can be passed accordingly.
+ *
+ * PSM simple usage case
+ * ---------------------
+ * Write and read back a small variable.
+ *
+ * \code
+ * char var[] = "name";
+ * char value[] = "Tim";
+ * int rv = psm_set_variable(phandle, var, value, strlen(value));
+ * if (rv != WM_SUCCESS) {
+ * wmprintf("Variable write failed");
+ * return rv;
+ * }
+ *
+ * char read_value[10];
+ * rv = psm_get_variable(phandle, var, read_value, strlen(value));
+ * if (rv != WM_SUCCESS) {
+ * wmprintf("Variable read failed");
+ * return rv;
+ * }
+ *
+ * \endcode
+ *
+ * PSM advanced use case
+ * ---------------------
+ * Write a huge valued object
+ *
+ * \code
+ * char var[] = "hello.mp3";
+ * char value[1024]; //Assume data is already in this buffer
+ *
+ * psm_object_handle_t ohandle;
+ * int rv = psm_object_open(phandle, var, PSM_MODE_WRITE, sizeof(value),
+ * NULL, &ohandle);
+ * if (rv != WM_SUCCESS) {
+ * //Failed
+ * return rv;
+ * }
+ * //Write the object in two chunks just to show valid usage pattern
+ * rv = psm_object_write(ohandle, value, 512);
+ * if (rv != WM_SUCCESS) {
+ * //Failed
+ * return rv;
+ * }
+ *
+ * rv = psm_object_write(ohandle, &value[512], 512);
+ * if (rv != WM_SUCCESS) {
+ * //Failed *
+ * return rv;
+ * }
+ *
+ * rv = psm_object_close(&ohandle);
+ * if (rv != WM_SUCCESS) {
+ * //Failed
+ * return rv;
+ * }
+ *
+ * \endcode
+ *
+ * De initialize PSM
+ * -----------------
+ * This would generally be done once only during system shutdown.
+ *
+ * \code
+ * int rv = psm_module_deinit(&phandle);
+ * if (rv != WM_SUCCESS) {
+ * //Failed
+ * return rv;
+ * }
+ *
+ * \endcode
+ *
+ * \section psm-v2_index_caching Indexing and caching
+ *
+ * Indexing and Caching are additional features to be used when fast
+ * access to a PSM object is required. Both are to be enabled
+ * separately per object. When indexing is enabled the address of the PSM
+ * object is saved in RAM. This avoids a search for the object in the
+ * flash. When caching is enabled the object name and value are cached in
+ * RAM. This gives instant access to the values and NO flash is
+ * accessed. When caching is enabled indexing is also automatically enabled
+ * for that object.
+ *
+ * Predictably caching consumes more RAM and amount of RAM consumed
+ * depends on the size of the name and value of object. Indexing uses 14
+ * bytes per object.
+ *
+ * \section psm-v2_secure PSM Encryption (Secure PSM)
+ *
+ * User may choose to store the data in PSM in encrypted format. If
+ * encryption is enabled, data is encrypted before storing it into PSM
+ * and decrypted when data is retrieved. PSMv2 currently uses AES-CTR for
+ * encryption. The keys are retrieved from the secure keystore. If
+ * encryption is enabled and secure keystore does not have the keys psm
+ * initialization will fail. Each PSM object is encrypted separately
+ * before storing to flash. The metadata is not encrypted. The name
+ * field and data field is encrypted.
+ *
+ * Note that, even if Secure PSM is enabled, users can still use PSM in
+ * non-encrypted mode. This is useful when there are more than one
+ * PSM partitions and only some of them are encrypted.
+ *
+ */
+
+#ifndef __PSMV2_H__
+#define __PSMV2_H__
+
+#include
+#include
+#include
+#include
+#include
+#include
+#define PSM_MODULE_VER "2.0"
+
+/** PSM Handle */
+typedef void *psm_hnd_t;
+
+/** PSM Object handle */
+typedef void *psm_object_handle_t;
+
+/** PSM opening mode */
+typedef enum
+{
+ /** Read mode */
+ PSM_MODE_READ = 1,
+ /** Write mode */
+ PSM_MODE_WRITE = 2,
+} psm_mode_t;
+
+/** PSM Flags
+ *
+ * Required in \ref psm_objattrib_t. Please refer \ref psm-v2_index_caching
+ * for details
+ */
+typedef enum
+{
+ /** Indexing enabled */
+ PSM_INDEXING_ENABLED = 0x01,
+ /** Caching enabled */
+ PSM_CACHING_ENABLED = 0x02,
+} psm_flags_t;
+
+/** PSM Object attributes
+ *
+ * This structure is accepted by psm_object_open()
+ */
+typedef struct
+{
+ /** OR of the flags defined in \ref psm_flags_t */
+ uint32_t flags;
+} psm_objattrib_t;
+
+/** PSM Configuration
+ *
+ * This structure is passed to psm_module_init(). PSMv2 won't need the user
+ * copy of this structure after call to psm_module_init() returns.
+ */
+typedef struct
+{
+ /** If read-only is enabled no writes will be possible to the
+ partition */
+ bool read_only;
+ /**
+ * If 'secure' is set, the object will be encrypted before
+ * writing, and object will be decrypted before reading. If secure
+ * PSM is enabled KEY_PSM_ENCRYPT_KEY and KEY_PSM_NONCE needs to
+ * be present in the keystore or must be provided through following
+ * members. Without these parameters the PSM initialization will fail.
+ * This variable should not be set in case of mc200.
+ */
+ bool secure;
+
+#ifdef CONFIG_SECURE_PSM
+ /**
+ * If 'keystore_override' is set, and secure is required, then it must
+ * use below key/iv field so that the keystore will be ignored.
+ * If 'keystore_override' is not set, and secure is required, then keystore
+ * key will be checked first before checking below key/iv field, whichever
+ * has valid key/iv will be used.
+ */
+ bool keystore_override;
+
+ /**
+ * 'key' from app to be used for encryption/decryption when applicable.
+ */
+ const uint8_t *key;
+
+ /**
+ * 'iv' from app to be used for encryption/decryption when applicable.
+ */
+ const uint8_t *iv;
+
+ /**
+ * 'key_sz' from app for the 'key' size in byte. typical 16.
+ */
+ uint16_t key_sz;
+
+ /**
+ * 'iv_sz' from app for the 'iv' size in byte. typical 16.
+ */
+ uint16_t iv_sz;
+#endif /* CONFIG_SECURE_PSM */
+} psm_cfg_t;
+
+/** Part Info types */
+enum part_info_type
+{
+ /** part_info.name is valid */
+ PART_INFO_NAME = 0,
+ /** part_info.fl is valid */
+ PART_INFO_FL_DESC = 1,
+};
+
+/** PSM init partition info
+ *
+ * This structure is passed to psm_module_init_ex() to specify partition
+ * details. It allows app to specify an arbitrary flash space
+ * or an existing partition name in addition to the PSM configuration for
+ * this partition. PSMv2 won't need the user copy of this structure or
+ * any pointer within this structure after call to psm_module_init_ex()
+ * returns.
+ */
+typedef struct
+{
+ /** part info type below */
+ enum part_info_type pitype;
+ union
+ {
+ /** 'name' is valid if 'pitype'= PART_INFO_NAME */
+ const char *name;
+ /** 'fl' is valid if 'pitype'= PART_INFO_FL_DESC */
+ const flash_desc_t *fl;
+ } part_info;
+
+ /** PSM Configuration settings for this init partition */
+ psm_cfg_t *psm_cfg;
+} psm_init_part_t;
+
+/**
+ * Initialize the PSM module
+ *
+ * This API initializes the PSM module. The given flash space will
+ * be accessed and initialized if necessary. Since this function is the
+ * first one called after a power cycle, if a flash operation was in
+ * progress recovery actions will be performed.
+ *
+ * @note If secure PSM is enabled KEY_PSM_ENCRYPT_KEY and KEY_PSM_NONCE
+ * needs to be present in the keystore or can optionally be provided
+ * through \t ref psm_cfg_t structure.
+ *
+ * @param[in] fdesc Populated flash descriptor \ref flash_desc_t having
+ * partition details. Please refer to \ref partition.h for relevant APIs.
+ * @param[out] phandle Pointer to the handle \ref psm_hnd_t. Populated by PSM.
+ * @param[in] psm_cfg \ref psm_cfg_t PSM configuration structure. If NULL
+ * is passed default configuration i.e. read/write mode is used.
+ *
+ * @return WM_SUCCESS Init success.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_E_NOMEM Memory allocation failure.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_module_init(flash_desc_t *fdesc, psm_hnd_t *phandle, psm_cfg_t *psm_cfg);
+
+/**
+ * Initialize the PSM module with specified partition name or flash space.
+ *
+ * This API initializes the PSM module with the enhancement that
+ * partition details can be specified either as a partition name
+ * from partition table or as flash descriptor itself.
+ *
+ * The given flash spaces will be accessed and initialized if necessary.
+ * Since this function is the first one called after a power cycle,
+ * if a flash operation was in progress recovery actions will be performed.
+ *
+ * @note If secure PSM is enabled KEY_PSM_ENCRYPT_KEY and KEY_PSM_NONCE
+ * needs to be present in the keystore or can optionally be provided
+ * through \t ref psm_cfg_t structure that is part of \ref
+ * psm_init_part_t structure.
+ *
+ * @note there is no corresponding psm_module_deinit_ex() API required.
+ * Use existing \ref psm_module_deinit() instead.
+ *
+ * @param[in] psm_init_part Pointer to \ref psm_init_part_t structure having
+ * partition details. PSMv2 won't need the user copy of any field in
+ * psm_init_part after call returns.
+ * @param[out] phandle Pointer to the handle \ref psm_hnd_t. Populated by PSM.
+ *
+ * @return WM_SUCCESS Init success.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_E_NOMEM Memory allocation failure.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_module_init_ex(const psm_init_part_t *psm_init_part, psm_hnd_t *phandle);
+
+/**
+ * Open an existing or a new PSM object
+ *
+ * This API allows the caller to open a new or existing PSM object.
+ * This call is essential before called psm_object_read() or
+ * psm_object_write().
+ *
+ * \note If write mode is specified and if an object with the same
+ * name is already present, the existing object will be deleted
+ * and replaced with the new one.
+ *
+ * @param[in] phandle Handle returned in earlier call to psm_module_init()
+ * @param[in] name NULL terminated ASCII name of PSM object.
+ * @param[in] mode Specify read mode (\ref PSM_MODE_READ) or a write
+ * mode(\ref PSM_MODE_WRITE).
+ * @param[in] max_data_len Valid only for write mode. This specifies the
+ * maximum length of the data the caller expect to write across single or
+ * multiple calls of psm_object_write(). It is okay if the caller later
+ * actually writes less number of bytes to be object than max_data_len
+ * given here. For e.g. Giving 'max_data_len' 20 but writing only 4 bytes
+ * is perfectly alright. The remaining 16 bytes will be released to the
+ * free space pool once this object is closed.
+ * @param[in] attribs Additional attributes as per \ref psm_objattrib_t.
+ * Pass NULL if not required.
+ * @param[out] ohandle Pointer to Object handle. Will be populated by
+ * psm_object_open() if open operation was successful. This needs to be
+ * passed to other psm read/write API's.
+ *
+ * @return For read mode: If open is successful size of the object is returned.
+ * For write mode: If open is successful WM_SUCCESS is returned.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_E_NOMEM Memory allocation failure.
+ * @return -WM_E_NOSPC If enough space is unavailable for the new
+ * object. This error can only be returned in write mode.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_object_open(psm_hnd_t phandle,
+ const char *name,
+ psm_mode_t mode,
+ uint32_t max_data_len,
+ psm_objattrib_t *attribs,
+ psm_object_handle_t *ohandle);
+
+/**
+ * Read data of an existing and opened object
+ *
+ * This API allows the caller to read data from an object. This
+ * call can be invoked as many times as the caller wants till the data read
+ * finishes. Offset from where data is read is automatically incremented
+ * depending on the size read. When data read is over, zero is returned.
+ *
+ * @pre psm_object_open()
+ *
+ * @note To avoid double pass over flash data area, CRC calculations are done
+ * on-the-go as data is being read progressively by the caller. CRC
+ * verification is done only in the last call to psm_object_read(). The
+ * downside to this is that whole object needs to be read by caller before
+ * object integrity can be confirmed.
+ *
+ * @note This API will block if other writers are currently using
+ * the PSM in write mode.
+ *
+ * @param[in] ohandle Handle returned from call to psm_object_open().
+ * @param[out] buf Destination buffer of data read from flash. Ensure that
+ * it is atleast equal to max_len
+ * @param[in] max_len Length of the buffer passed as second parameter. Data
+ * read can be less than this value is end of object is reached.
+ *
+ * @return Non-zero positive value equal to number of bytes written to user
+ * given buffer
+ * @return 0 No more data available.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_E_CRC If CRC check failed.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_object_read(psm_object_handle_t ohandle, void *buf, uint32_t max_len);
+
+/**
+ * Write data to an opened PSM object.
+ *
+ * This API allows the caller to write data to an object. This
+ * call can be invoked as many times as the caller wants as long as total
+ * size written is less that 'max_len' specified during
+ * psm_object_open(). Data passed in every invocation is appended to the
+ * existing data already written.
+ *
+ * @pre psm_object_open()
+ *
+ * @note This API will block if other readers/writers are currently using
+ * the PSM.
+ *
+ * @param[in] ohandle Handle returned from call to psm_object_open().
+ * @param[in] buf Pointer to buffer containing data to be written to flash.
+ * @param[in] len Length of the data in the buffer passed.
+ *
+ * @return WM_SUCCESS Data was written successfully.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_E_PERM If object was opened in read mode.
+ * @return -WM_E_NOSPC If caller tries to write more data than specified in
+ * call to psm_object_open().
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_object_write(psm_object_handle_t ohandle, const void *buf, uint32_t len);
+
+/**
+ * Close the PSM object
+ *
+ * This API will close the earlier opened PSM object. The object
+ * is finalized in the flash only after this call.
+ *
+ * @pre psm_object_open()
+ *
+ * @param[in] ohandle Handle returned from earlier call to
+ * psm_object_open()
+ *
+ * @return WM_SUCCESS Object was closed successfully.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_object_close(psm_object_handle_t *ohandle);
+
+/**
+ * Delete a PSM object
+ *
+ * This API deletes an object from the PSM.
+ *
+ * @param[in] phandle Handle returned from earlier call to
+ * psm_module_init()
+ * @param[in] name NULL terminated ASCII name of the PSM object to be
+ * deleted.
+ *
+ * @note This API will block if other readers/writers are currently using
+ * the PSM.
+ *
+ * @return WM_SUCCESS Object was deleted successfully.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_E_NOSPC If caller tries to write more data than specified in
+ * call to psm_object_open().
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_object_delete(psm_hnd_t phandle, const char *name);
+
+/**
+ * Format the PSM partition
+ *
+ * This API allows the caller to erase and initialize the PSM
+ * partition. All the existing objects will be erased.
+ *
+ * @note This API will block if other readers/writers are currently using
+ * the PSM.
+ *
+ * @param[in] phandle Handle to PSM returned earlier from the call to
+ * psm_module_init()
+ *
+ * @return WM_SUCCESS Format operation was successful.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_format(psm_hnd_t phandle);
+
+/**
+ * This callback will be invoked 'n' times if there are 'n' total variables
+ * in the PSM. The user can call any API to read the PSM variables in the
+ * callback. Any write operation to PSM will cause a deadlock if done in
+ * the callback implementation.
+ *
+ * If the callback implementation returns a non-zero value no futher
+ * callbacks will be given. This can be useful when the callback has found
+ * what it was searching for and does not need remaining variables. The
+ * callback is invoked till all variables are done or callback returns
+ * WM_SUCCESS, whichever comes first.
+ */
+typedef int (*psm_list_cb)(const uint8_t *name);
+
+/**
+ * Print all the objects and their data to console.
+ *
+ * @param[in] phandle Handle to PSM returned earlier from the call to
+ * psm_module_init()
+ * @param[in] list_cb Callback invoked by this API to pass on variable
+ * names one by one to the user.
+ *
+ * @return void
+ */
+void psm_objects_list(psm_hnd_t phandle, psm_list_cb list_cb);
+
+/*
+ * Check if PSM module is encrypted.
+ *
+ * @param[in] phandle Handle to PSM returned earlier from the call to
+ * psm_module_init()
+ *
+ * @return 'true' if PSM is encrypted or 'false' otherwise.
+ */
+bool is_psm_encrypted(psm_hnd_t phandle);
+
+/**
+ * Set a variable value pair
+ *
+ * This API is built on top of existing
+ * psm_object_open(), psm_object_write() and psm_object_close()
+ * APIs. This API is preferable when small sized objects
+ * are being written.
+ *
+ * @note psm_object_open() and psm_object_close() are not required to be
+ * called if this API is used.
+ *
+ * @param[in] phandle Handle to PSM returned earlier from the call to
+ * psm_module_init()
+ * @param[in] variable Name of the object.
+ * @param[in] value Pointer to buffer having the data to be written
+ * @param[in] len Length of the data to be written.
+ *
+ * @return WM_SUCCESS Variable-value pair was set successfully.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_set_variable(psm_hnd_t phandle, const char *variable, const void *value, uint32_t len);
+
+/**
+ * Helper function to simplify set of NULL terminated value.
+ *
+ * psm_set_variable_str() will self calculate the length of the NULL
+ * terminated string sent by caller.
+ *
+ * @param[in] phandle See documentation of psm_set_variable()
+ * @param[in] variable See documentation of psm_set_variable()
+ * @param[in] value See documentation of psm_set_variable()
+ *
+ * @return See documentation of psm_set_variable()
+ */
+static inline int psm_set_variable_str(psm_hnd_t phandle, const char *variable, const void *value)
+{
+ return psm_set_variable(phandle, variable, value, strlen((const char *)value));
+}
+
+/**
+ * Helper function to set integer value to PSM
+ *
+ * This function will convert given int to string representation and store
+ * it to PSM. psm_get_variable_int() can be used to read the value back
+ * again in int format.
+ *
+ * for e.g. 1234 given by the user will be stored as "1234"
+ *
+ * @param[in] phandle See documentation of psm_get_variable()
+ * @param[in] variable See documentation of psm_get_variable()
+ * @param[out] value The value to be stored to PSM
+ *
+ * @return See documentation of psm_set_variable()
+ */
+static inline int psm_set_variable_int(psm_hnd_t phandle, const char *variable, int value)
+{
+ char int_s[14];
+
+ snprintf(int_s, sizeof(int_s), "%d", value);
+ return psm_set_variable_str(phandle, variable, int_s);
+}
+
+/**
+ * Get a variable value pair
+ *
+ * This API is built on top of existing
+ * psm_object_open(), psm_object_read() and psm_object_close()
+ * APIs. This API is preferable when small sized objects
+ * are being read.
+ *
+ * @note psm_object_open() and psm_object_close() are not required to be
+ * called if this API is used.
+ *
+ * @param[in] phandle Handle to PSM returned earlier from the call to
+ * psm_module_init()
+ * @param[in] variable Name of the object.
+ * @param[out] value Pointer to buffer where value will be written by PSM.
+ * @param[in] max_len Length of the buffer passed as third parameter. If
+ * the buffer is not enough to fit the whole object error will be
+ * returned. Partial read will not be done.
+ *
+ * @note Note that this function returns the length of the value. It will
+ * \b not< NULL terminate the returned data.
+ *
+ * @return If operation is a success then length of the value field will be
+ * returned.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_E_NOSPC If variable value exceeds buffer length given.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_get_variable(psm_hnd_t phandle, const char *variable, void *value, uint32_t max_len);
+
+/**
+ * Get size of a PSM variable
+ *
+ * No changes are done to the PSM.
+ *
+ * @param[in] phandle Handle to PSM returned earlier from the call to
+ * psm_module_init()
+ * @param[in] variable Name of the variable.
+ *
+ * @return Zero or positive value of size of variable if variable is present.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_FAIL if object not found or any error occurred.
+ */
+int psm_get_variable_size(psm_hnd_t phandle, const char *variable);
+
+/**
+ * Check if a variable is present
+ *
+ * No changes are done to the PSM.
+ *
+ * @param[in] phandle Handle to PSM returned earlier from the call to
+ * psm_module_init()
+ * @param[in] variable Name of the variable.
+ *
+ * @return 'true' if variable is present.
+ * @return 'false' if variable is absent or some other error.
+ */
+static inline bool psm_is_variable_present(psm_hnd_t phandle, const char *variable)
+{
+ return (psm_get_variable_size(phandle, variable) >= 0);
+}
+
+/**
+ * Helper function to simplify get of NULL terminated value.
+ *
+ * This function will automatically NULL terminate the byte string
+ * retrieved from PSM. One additional byte should be kept reserved by the
+ * caller for this NULL terminator.
+ *
+ * @param[in] phandle See documentation of psm_get_variable()
+ * @param[in] variable See documentation of psm_get_variable()
+ * @param[out] value See documentation of psm_set_gariable()
+ * @param[in] max_len See documentation of psm_get_variable()
+ *
+ * @return See documentation of psm_get_variable()
+ */
+static inline int psm_get_variable_str(psm_hnd_t phandle, const char *variable, void *value, uint32_t max_len)
+{
+ if (!max_len)
+ return -WM_E_INVAL;
+
+ uint8_t *valp = (uint8_t *)value;
+
+ int ret = psm_get_variable(phandle, variable, valp, max_len - 1);
+ if (ret >= 0) /* NULL terminate */
+ valp[ret] = 0;
+
+ return ret;
+}
+
+/**
+ * Helper function to get integer value from PSM
+ *
+ * This function will automatically read string representation of a number
+ * from PSM and convert it to int format before returning.
+ *
+ * for e.g. "1234" stored in PSM will be returned as 1234 in the user given
+ * int variable.
+ *
+ * @param[in] phandle See documentation of psm_get_variable()
+ * @param[in] variable See documentation of psm_get_variable()
+ * @param[out] value The value returned.
+ *
+ * @return WM_SUCCESS if retrieval was successful
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_FAIL If any other error occurs.
+ */
+static inline int psm_get_variable_int(psm_hnd_t phandle, const char *variable, int *value)
+{
+ char int_s[14];
+
+ int ret = psm_get_variable_str(phandle, variable, int_s, sizeof(int_s));
+ if (ret < 0)
+ return ret;
+
+ *value = strtol(int_s, NULL, 0);
+ return WM_SUCCESS;
+}
+
+/**
+ * De-initialize the PSM module
+ *
+ * This API unloads the PSM module from handling the flash partition.
+ *
+ * @note This API will block till other readers/writers are currently using
+ * the PSM.
+ *
+ * @param[in] phandle Handle to the PSM obtained earlier through
+ * psm_module_init()
+ *
+ * @return WM_SUCCESS Module de-init success.
+ * @return -WM_E_INVAL Invalid arguments.
+ * @return -WM_FAIL If any other error occurs.
+ */
+int psm_module_deinit(psm_hnd_t *phandle);
+
+#endif /* __PSMV2_H__ */
diff --git a/components/boot2_utils/psm_list.h b/components/boot2_utils/psm_list.h
new file mode 100644
index 000000000..c54ef1236
--- /dev/null
+++ b/components/boot2_utils/psm_list.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2017-2020, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PSM_LIST_H__
+#define __PSM_LIST_H__
+
+#include
+
+/*!
+ * @addtogroup psm
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/**
+ * @brief Get PSM list object structure pointer.
+ */
+#define PSM_LIST_OBJ(type, field, list) (type)((uint32_t)list - (uint32_t)(&((type)0)->field))
+
+/**
+ * @brief PSM list fields
+ */
+typedef struct _psm_list
+{
+ struct _psm_list *prev; /*!< previous list node */
+ struct _psm_list *next; /*!< next list node */
+} psm_list_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+ * @brief Initialize PSM list head.
+ *
+ * @param list PSM list head pointer.
+ */
+static inline void PSM_List_Init(psm_list_t *list)
+{
+ assert(list);
+
+ list->prev = list;
+ list->next = list;
+}
+
+/*!
+ * @brief Check whether PSM list is empty.
+ *
+ * @param list PSM list head pointer.
+ * @return TRUE when list is empty, FALSE otherwise.
+ */
+static inline bool PSM_List_IsEmpty(psm_list_t *list)
+{
+ assert(list);
+
+ return list->next == list;
+}
+
+/*!
+ * @brief Add list node at list head.
+ *
+ * @param list PSM list head pointer.
+ * @param node PSM list node pointer to add.
+ */
+static inline void PSM_List_AddHead(psm_list_t *list, psm_list_t *node)
+{
+ assert(list);
+ assert(node);
+
+ node->next = list->next;
+ node->prev = list;
+ list->next->prev = node;
+ list->next = node;
+}
+
+/*!
+ * @brief Add list node at list tail.
+ *
+ * @param list PSM list head pointer.
+ * @param node PSM list node pointer to add.
+ */
+static inline void PSM_List_AddTail(psm_list_t *list, psm_list_t *node)
+{
+ assert(list);
+ assert(node);
+
+ node->prev = list->prev;
+ node->next = list;
+ list->prev->next = node;
+ list->prev = node;
+}
+
+/*!
+ * @brief Insert list node before another.
+ *
+ * @param anchor PSM list anchor node pointer.
+ * @param node PSM list node pointer to insert.
+ */
+static inline void PSM_List_InsertBefore(psm_list_t *anchor, psm_list_t *node)
+{
+ PSM_List_AddTail(anchor, node);
+}
+
+/*!
+ * @brief Insert list node after another.
+ *
+ * @param anchor PSM list anchor node pointer.
+ * @param node PSM list node pointer to insert.
+ */
+static inline void PSM_List_InsertAfter(psm_list_t *anchor, psm_list_t *node)
+{
+ PSM_List_AddHead(anchor, node);
+}
+
+/*!
+ * @brief Remove list node from list.
+ *
+ * @param node PSM list node pointer to remove.
+ */
+static inline void PSM_List_Remove(psm_list_t *node)
+{
+ assert(node);
+
+ node->prev->next = node->next;
+ node->next->prev = node->prev;
+ /* clear node */
+ PSM_List_Init(node);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/*! @} */
+
+#endif /* __PSM_LIST_H__ */
diff --git a/components/boot2_utils/secure_boot.h b/components/boot2_utils/secure_boot.h
new file mode 100644
index 000000000..a33e97462
--- /dev/null
+++ b/components/boot2_utils/secure_boot.h
@@ -0,0 +1,66 @@
+/** @file secure_boot.h
+ *
+ * @brief Secure Algo Enums
+ *
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#ifndef __SECURE_BOOT_H__
+#define __SECURE_BOOT_H__
+
+#include
+#include
+
+/* End of SRAM0 address where boot-loader will copy keystore
+ * Note: Boot loader refers to this macro and same address space is reserved
+ * in linker script of application fw as well.
+ * Important point to remember here is, this should note overlap with
+ * boot-loader CODE/DATA/BSS region, otherwise that may result in undefined
+ * behaviour.
+ * Please do not modify.
+ */
+#define SB_KEYSTORE_ADDR ((volatile uint32_t *)(0x15F000))
+#define SB_KEYSTORE_SIZE (4 * 1024)
+#define SB_SEC_IMG_HDR_SIZE (512)
+
+typedef struct tlv_hdr img_sec_hdr, boot2_ks_hdr;
+
+enum signing_algo_t
+{
+ NO_SIGN = 0,
+ RSA_SIGN,
+};
+
+enum hash_algo_t
+{
+ NO_HASH = 0,
+ SHA256_HASH,
+};
+
+enum encrypt_algo_t
+{
+ NO_ENCRYPT = 0,
+ AES_CCM_256_ENCRYPT,
+ AES_CTR_128_ENCRYPT,
+};
+
+#endif /* __SECURE_BOOT_H__ */
diff --git a/components/boot2_utils/wmtlv.c b/components/boot2_utils/wmtlv.c
new file mode 100644
index 000000000..66208992f
--- /dev/null
+++ b/components/boot2_utils/wmtlv.c
@@ -0,0 +1,242 @@
+/** @file wmtlv.c
+ *
+ * @brief This file provides API for Type Length Value
+ *
+ * Copyright 2015-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#include
+#include
+#include
+
+int tlv_store_init(uint8_t *tlv_buf, uint32_t max_size, uint8_t store_type)
+{
+ struct tlv_hdr *thdr = (struct tlv_hdr *)tlv_buf;
+
+ if (store_type == BOOT2_KEYSTORE)
+ thdr->magic = SEC_KEYSTORE_MAGIC_SIG;
+ else if (IMAGE_SECURE_HEADER)
+ thdr->magic = SEC_FW_MAGIC_SIG;
+ else
+ thdr->magic = SEC_DEFAULT_MAGIC_SIG;
+
+ thdr->len = sizeof(struct tlv_hdr);
+
+ /* At the moment store max size in crc for buffer overflow detection */
+ thdr->crc = max_size;
+ return TLV_SUCCESS;
+}
+
+int tlv_store_add(uint8_t *tlv_buf, uint8_t type, uint16_t len, const uint8_t *value)
+{
+ struct tlv_hdr *thdr = (struct tlv_hdr *)tlv_buf;
+ struct tlv_entry *tentry = (struct tlv_entry *)(tlv_buf + thdr->len);
+
+ if ((thdr->len + sizeof(tentry->type) + sizeof(tentry->len) + len) > thdr->crc)
+ return ERR_TLV_INSUFFICIENT_MEMORY;
+
+ tentry->type = type;
+ tentry->len = len;
+ memcpy(tentry->value, value, len);
+
+ thdr->len += sizeof(tentry->type) + sizeof(tentry->len) + len;
+
+ return TLV_SUCCESS;
+}
+
+/* Special routine for XIP image where keystore has to be a
+ * multiple of 4 bytes */
+int tlv_store_xip_padding(uint8_t *tlv_buf, uint8_t *pad_value)
+{
+ struct tlv_hdr *thdr = (struct tlv_hdr *)tlv_buf;
+ struct tlv_entry *tentry = (struct tlv_entry *)(tlv_buf + thdr->len);
+ uint32_t len;
+
+ /* Already aligned so no padding */
+ if (!(thdr->len & (XIP_ALIGN_SIZE - 1)))
+ return TLV_SUCCESS;
+
+ len = XIP_ALIGN_SIZE -
+ ((thdr->len + sizeof(tentry->type) + sizeof(tentry->len) + XIP_ALIGN_SIZE) & (XIP_ALIGN_SIZE - 1));
+
+ if ((thdr->len + len) > thdr->crc)
+ return ERR_TLV_INSUFFICIENT_MEMORY;
+
+ tentry->type = KEY_FILLER;
+ tentry->len = len;
+ memset(tentry->value, *pad_value, tentry->len);
+
+ thdr->len += sizeof(tentry->type) + sizeof(tentry->len) + tentry->len;
+
+ return TLV_SUCCESS;
+}
+
+int tlv_store_get(uint8_t *tlv_buf, uint8_t type, uint16_t len, uint8_t *value)
+{
+ struct tlv_hdr *thdr = (struct tlv_hdr *)tlv_buf;
+ struct tlv_entry *tentry = (struct tlv_entry *)(tlv_buf + sizeof(struct tlv_hdr));
+
+ while ((uint8_t *)tentry < tlv_buf + thdr->len)
+ {
+ if (tentry->type == type)
+ {
+ if (value && tentry->len <= len)
+ {
+ memcpy(value, tentry->value, tentry->len);
+ return tentry->len;
+ }
+ else if (value == NULL)
+ return tentry->len;
+ else
+ return ERR_TLV_BAD_BUF_LEN;
+ }
+ tentry = (struct tlv_entry *)((uint8_t *)tentry + sizeof(tentry->type) + sizeof(tentry->len) + tentry->len);
+ }
+
+ return ERR_TLV_NOT_FOUND;
+}
+
+static struct tlv_hdr *thdr;
+static struct tlv_entry *tentry;
+
+int tlv_store_iterate(uint8_t *tlv_buf, uint8_t *ptype, uint16_t len, uint8_t *value)
+{
+ if (tlv_buf)
+ {
+ thdr = (struct tlv_hdr *)tlv_buf;
+ tentry = (struct tlv_entry *)(tlv_buf + sizeof(struct tlv_hdr));
+ }
+
+ if ((uint8_t *)tentry < (uint8_t *)thdr + thdr->len)
+ {
+ if (ptype)
+ *ptype = tentry->type;
+ if (value == NULL || tentry->len > len)
+ return ERR_TLV_BAD_BUF_LEN;
+
+ memcpy(value, tentry->value, tentry->len);
+ tentry = (struct tlv_entry *)((uint8_t *)tentry + sizeof(tentry->type) + sizeof(tentry->len) + tentry->len);
+ return tentry->len;
+ }
+
+ return ERR_TLV_NOT_FOUND;
+}
+
+int tlv_store_get_ref(uint8_t *tlv_buf, uint8_t type, uint16_t *plen, const uint8_t **pvalue)
+{
+ struct tlv_hdr *thdr = (struct tlv_hdr *)tlv_buf;
+ struct tlv_entry *tentry = (struct tlv_entry *)(tlv_buf + sizeof(struct tlv_hdr));
+
+ while ((uint8_t *)tentry < tlv_buf + thdr->len)
+ {
+ if (tentry->type == type)
+ {
+ if (plen)
+ *plen = tentry->len;
+ if (pvalue)
+ *pvalue = tentry->value;
+ return tentry->len;
+ }
+ tentry = (struct tlv_entry *)((uint8_t *)tentry + sizeof(tentry->type) + sizeof(tentry->len) + tentry->len);
+ }
+
+ if (plen)
+ *plen = 0;
+ if (pvalue)
+ *pvalue = NULL;
+
+ return ERR_TLV_NOT_FOUND;
+}
+
+int tlv_store_iterate_ref(uint8_t *tlv_buf, uint8_t *ptype, uint16_t *plen, const uint8_t **pvalue)
+{
+ if (tlv_buf)
+ {
+ thdr = (struct tlv_hdr *)tlv_buf;
+ tentry = (struct tlv_entry *)(tlv_buf + sizeof(struct tlv_hdr));
+ }
+
+ if ((uint8_t *)tentry < (uint8_t *)thdr + thdr->len)
+ {
+ uint8_t len = tentry->len;
+
+ if (ptype)
+ *ptype = tentry->type;
+ if (plen)
+ *plen = tentry->len;
+ if (pvalue)
+ *pvalue = tentry->value;
+ tentry = (struct tlv_entry *)((uint8_t *)tentry + sizeof(tentry->type) + sizeof(tentry->len) + tentry->len);
+ return len;
+ }
+
+ if (plen)
+ *plen = 0;
+ if (pvalue)
+ *pvalue = NULL;
+
+ return ERR_TLV_NOT_FOUND;
+}
+
+int tlv_store_close(uint8_t *tlv_buf, crc_func_t crc_func)
+{
+ struct tlv_hdr *thdr = (struct tlv_hdr *)tlv_buf;
+
+ thdr->crc = crc_func((tlv_buf + sizeof(struct tlv_hdr)), (thdr->len - sizeof(struct tlv_hdr)), 0);
+ return TLV_SUCCESS;
+}
+
+int tlv_store_validate(uint8_t *tlv_buf, uint8_t store_type, crc_func_t crc_func)
+{
+ struct tlv_hdr *thdr = (struct tlv_hdr *)tlv_buf;
+ uint32_t magic, crc;
+
+ switch (store_type)
+ {
+ case BOOT2_KEYSTORE:
+ magic = SEC_KEYSTORE_MAGIC_SIG;
+ break;
+ case IMAGE_SECURE_HEADER:
+ magic = SEC_FW_MAGIC_SIG;
+ break;
+ default:
+ magic = SEC_DEFAULT_MAGIC_SIG;
+ break;
+ }
+
+ if (thdr->magic != magic)
+ return ERR_TLV_MAGIC_FAILURE;
+
+ crc = crc_func((tlv_buf + sizeof(struct tlv_hdr)), (thdr->len - sizeof(struct tlv_hdr)), 0);
+
+ if (crc != thdr->crc)
+ return ERR_TLV_CRC_FAILURE;
+
+ return TLV_SUCCESS;
+}
+
+int tlv_store_length(uint8_t *tlv_buf)
+{
+ struct tlv_hdr *thdr = (struct tlv_hdr *)tlv_buf;
+
+ return thdr->len;
+}
diff --git a/components/boot2_utils/wmtlv.h b/components/boot2_utils/wmtlv.h
new file mode 100644
index 000000000..9f4194bba
--- /dev/null
+++ b/components/boot2_utils/wmtlv.h
@@ -0,0 +1,97 @@
+/** @file wmtlv.h
+ *
+ * @brief TLV (Type-Length-Value) module
+ *
+ * Copyright 2015-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+/*! \file wmtlv.h
+ * \brief TLV (Type-Length-Value) module
+ *
+ * TLV module is the low-level module on top of which keystore is based.
+ * (For details of keystore, refer to keystore.h). This module manages
+ * the pre-defined TLV types.
+ */
+
+#ifndef __TLV_H__
+#define __TLV_H__
+
+#include
+#include
+
+#define IS_VALID_TLV_TYPE(tlv_type) (((tlv_type) >= 0 && (tlv_type) <= 255) ? 1 : 0)
+#define XIP_ALIGN_SIZE 4
+
+PACK_START
+struct tlv_hdr
+{
+ uint32_t magic;
+ uint32_t len;
+ uint32_t crc;
+} PACK_END;
+
+PACK_START
+struct tlv_entry
+{
+ uint8_t type;
+ uint16_t len;
+ uint8_t value[];
+} PACK_END;
+
+enum tlv_store_type
+{
+ BOOT2_KEYSTORE = 0,
+ IMAGE_SECURE_HEADER,
+ CONFIG_FILE_STORE
+};
+
+#define SEC_KEYSTORE_MAGIC_SIG (('S' << 0) | ('B' << 8) | ('K' << 16) | ('S' << 24))
+#define SEC_FW_MAGIC_SIG (('S' << 0) | ('B' << 8) | ('F' << 16) | ('H' << 24))
+#define SEC_DEFAULT_MAGIC_SIG 0x00
+
+#define TLV_SUCCESS 0
+#define ERR_TLV_MAGIC_FAILURE -1
+#define ERR_TLV_CRC_FAILURE -2
+#define ERR_TLV_BAD_BUF_LEN -3
+#define ERR_TLV_NOT_FOUND -4
+#define ERR_TLV_BAD_LENGTH -5
+#define ERR_TLV_INSUFFICIENT_MEMORY -6
+#define ERR_TLV_INVALID_TYPE -7
+#define ERR_TLV_INVALID_VALUE -7
+
+/* Following apis should not be used directly for accessing keystore.
+ * Use keystore APIs instead. Refer to keystore.h for details.
+ */
+typedef uint32_t (*crc_func_t)(const void *data, int data_size, uint32_t crc);
+
+int tlv_store_init(uint8_t *tlv_buf, uint32_t max_size, uint8_t store_type);
+int tlv_store_add(uint8_t *tlv_buf, uint8_t type, uint16_t len, const uint8_t *value);
+int tlv_store_close(uint8_t *tlv_buf, crc_func_t crc_func);
+int tlv_store_length(uint8_t *tlv_buf);
+int tlv_store_validate(uint8_t *tlv_buf, uint8_t store_type, crc_func_t crc_func);
+int tlv_store_get(uint8_t *tlv_buf, uint8_t type, uint16_t len, uint8_t *value);
+int tlv_store_get_ref(uint8_t *tlv_buf, uint8_t type, uint16_t *plen, const uint8_t **pvalue);
+int tlv_store_iterate(uint8_t *tlv_buf, uint8_t *ptype, uint16_t len, uint8_t *value);
+int tlv_store_iterate_ref(uint8_t *tlv_buf, uint8_t *ptype, uint16_t *plen, const uint8_t **pvalue);
+int tlv_store_xip_padding(uint8_t *tlv_buf, uint8_t *pad_value);
+
+#endif /* __TLV_H__ */
diff --git a/components/codec/cs42888/driver_cs42888.cmake b/components/codec/cs42888/driver_cs42888.cmake
index d84246308..ecb64dadd 100644
--- a/components/codec/cs42888/driver_cs42888.cmake
+++ b/components/codec/cs42888/driver_cs42888.cmake
@@ -11,9 +11,6 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(component_codec_i2c_MIMXRT1052)
-endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
include(component_codec_i2c_MIMX8QM6_cm4_core0)
endif()
@@ -23,6 +20,9 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
include(component_codec_i2c_MIMX8QX6)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(component_codec_i2c_MIMXRT1052)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
include(component_codec_i2c_MIMXRT685S_cm33)
endif()
diff --git a/components/codec/wm8904/driver_wm8904.cmake b/components/codec/wm8904/driver_wm8904.cmake
index 8c2355867..4119da957 100644
--- a/components/codec/wm8904/driver_wm8904.cmake
+++ b/components/codec/wm8904/driver_wm8904.cmake
@@ -11,30 +11,30 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
+if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+ include(component_codec_i2c_LPC51U68)
+endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4")
include(component_codec_i2c_LPC54114_cm4)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54628")
include(component_codec_i2c_LPC54628)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
- include(component_codec_i2c_LPC55S16)
-endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018")
include(component_codec_i2c_LPC54S018)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
include(component_codec_i2c_LPC54S018M)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
- include(component_codec_i2c_LPC51U68)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
- include(component_codec_i2c_LPC55S69_cm33_core0)
+if(${MCUX_DEVICE} STREQUAL "LPC55S16")
+ include(component_codec_i2c_LPC55S16)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC55S28")
include(component_codec_i2c_LPC55S28)
endif()
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
+ include(component_codec_i2c_LPC55S69_cm33_core0)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
include(component_codec_i2c_MIMXRT685S_cm33)
endif()
diff --git a/components/codec/wm8960/driver_wm8960.cmake b/components/codec/wm8960/driver_wm8960.cmake
index 6d30a7b2d..133974bb5 100644
--- a/components/codec/wm8960/driver_wm8960.cmake
+++ b/components/codec/wm8960/driver_wm8960.cmake
@@ -11,11 +11,8 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(component_codec_i2c_MIMXRT1052)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(component_codec_i2c_MIMXRT1064)
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+ include(component_codec_i2c_MCIMX7U5)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
include(component_codec_i2c_MIMX8QM6_cm4_core0)
@@ -26,22 +23,25 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
include(component_codec_i2c_MIMX8QX6)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
- include(component_codec_i2c_MIMXRT1021)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+ include(component_codec_i2c_MIMXRT1011)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
- include(component_codec_i2c_MIMXRT1062)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+ include(component_codec_i2c_MIMXRT1015)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
- include(component_codec_i2c_MCIMX7U5)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
+ include(component_codec_i2c_MIMXRT1021)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
include(component_codec_i2c_MIMXRT1024)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
- include(component_codec_i2c_MIMXRT1011)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(component_codec_i2c_MIMXRT1052)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
- include(component_codec_i2c_MIMXRT1015)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
+ include(component_codec_i2c_MIMXRT1062)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(component_codec_i2c_MIMXRT1064)
endif()
diff --git a/components/flash/mflash/component_mflash_common.cmake b/components/flash/mflash/component_mflash_common.cmake
new file mode 100644
index 000000000..fda58170b
--- /dev/null
+++ b/components/flash/mflash/component_mflash_common.cmake
@@ -0,0 +1,12 @@
+#Description: statically allocated file system for mflash; user_visible: False
+include_guard(GLOBAL)
+message("component_mflash_common component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
diff --git a/components/flash/mflash/component_mflash_file.cmake b/components/flash/mflash/component_mflash_file.cmake
new file mode 100644
index 000000000..e760dd27d
--- /dev/null
+++ b/components/flash/mflash/component_mflash_file.cmake
@@ -0,0 +1,14 @@
+#Description: statically allocated file system for mflash; user_visible: False
+include_guard(GLOBAL)
+message("component_mflash_file component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/mflash_file.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(component_mflash_mw320)
diff --git a/components/flash/mflash/mflash_common.h b/components/flash/mflash/mflash_common.h
index 644b39b86..d39cbf2c4 100644
--- a/components/flash/mflash/mflash_common.h
+++ b/components/flash/mflash/mflash_common.h
@@ -16,8 +16,6 @@
* Common definitions
******************************************************************************/
-#define MFLASH_INVALID_ADDRESS (UINT32_MAX)
-
#define mflash_drv_is_page_aligned(x) (((x) % (MFLASH_PAGE_SIZE)) == 0)
#define mflash_drv_is_sector_aligned(x) (((x) % (MFLASH_SECTOR_SIZE)) == 0)
diff --git a/components/flash/mflash/mflash_file.c b/components/flash/mflash/mflash_file.c
index 47e10258d..41a74defa 100644
--- a/components/flash/mflash/mflash_file.c
+++ b/components/flash/mflash/mflash_file.c
@@ -8,622 +8,171 @@
#include
#include
#include
-
-#ifdef FSL_RTOS_FREE_RTOS
-#include "FreeRTOS.h"
-#endif
-
#include "mflash_file.h"
#include "mflash_drv.h"
#include "fsl_common.h"
-/* Magic numbers to check for presence of the structures below */
-#define MFLASH_DIR_MAGIC_NO (0xF17E07AB)
-#define MFLASH_META_MAGIC_NO (0xABECEDA8)
-#define MFLASH_FS_VERSION (0x00010000)
-#define MFLASH_BLANK_PATTERN (0xFF)
-
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
-/* linker symbols imported as described in https://www.keil.com/support/man/docs/armlink/armlink_pge1362065952432.htm */
-extern char Image$$mflash_fs$$Base[];
-#define MFLASH_FS_START ((void *)Image$$mflash_fs$$Base)
-#else
-extern char __MFLASH_FS_START[];
-#define MFLASH_FS_START ((void *)__MFLASH_FS_START)
-#endif
-
-/*
- * The table header and table record structures have to be aligned
- * with pages/sectors that are expected to be of 2**n size, hence there is some padding
- */
-typedef struct
-{
- uint32_t file_offset;
- uint32_t alloc_size;
- uint8_t path[MFLASH_MAX_PATH_LEN];
-} mflash_dir_record_t;
-
-typedef struct
-{
- uint32_t magic_no;
- uint32_t version;
- uint32_t page_size;
- uint32_t sector_size;
- uint32_t file_count;
- uint32_t total_size;
- uint8_t padding[sizeof(mflash_dir_record_t) - 6 * sizeof(uint32_t)];
-} mflash_fs_header_t;
+static mflash_file_t *g_file_table = NULL;
+static bool g_mflash_initialized = false;
-typedef struct
-{
- mflash_fs_header_t header;
- mflash_dir_record_t records[];
-} mflash_fs_t;
+/* Help to identify mfile without knowing an address */
+#define MFLASH_META_MAGIC_NO (0xABECEDA8)
-/* Metadata prepended to the file itself to identify valid (already written) file and keep actual length of the file */
typedef struct
{
uint32_t file_size;
uint32_t magic_no;
-} mflash_file_meta_t;
+} mfile_meta_t;
-/* Pointer to the filesystem */
-static mflash_fs_t *g_mflash_fs = NULL;
-
-/* API - True if mflash is already initialized */
-bool mflash_is_initialized(void)
+bool mflash_is_initialized()
{
- return (g_mflash_fs != NULL);
+ return g_mflash_initialized;
}
-/* Store path string to directory record structure */
-static bool dir_path_store(mflash_dir_record_t *dr, char *path)
+int mflash_init(mflash_file_t *user_file_table, bool init_drv)
{
- assert(dr);
- assert(path);
-
- for (int i = 0; i < MFLASH_MAX_PATH_LEN; i++)
- {
- dr->path[i] = *path;
-
- /* End of string, exit the loop */
- if (*path == '\0')
- break;
-
- path++;
- }
-
- /* Check whether the whole given path string was processed */
- if (*path != '\0')
+ /* Check params */
+ if (NULL == user_file_table)
return false;
- return true;
-}
-
-/* Match path string against directory record */
-static bool dir_path_match(mflash_dir_record_t *dr, char *path)
-{
- assert(dr);
- assert(path);
-
- for (int i = 0; i < MFLASH_MAX_PATH_LEN; i++)
+ /* Check attributes of each file in table */
+ for (mflash_file_t *tmp_file = user_file_table; (0 != tmp_file->flash_addr) && (0 != tmp_file->max_size);
+ tmp_file += 1)
{
- if (dr->path[i] != *path)
+ /* NOTE: This loop does not check overlapping sectors !!! */
+ /* Assume that zero address and zero size belong to unitialized struct. */
+ if ((0 == tmp_file->flash_addr) || (0 == tmp_file->max_size))
+ return false;
+ /* Starting file address ('flash_addr') must be sector aligned */
+ if (!mflash_drv_is_sector_aligned(tmp_file->flash_addr))
+ return false;
+ /* File max_size must be multiple of sector size */
+ if (!mflash_drv_is_sector_aligned(tmp_file->max_size))
return false;
-
- /* End of string, there is match */
- if (*path == '\0')
- return true;
-
- path++;
}
-
- /* Check whether the whole given path string was processed */
- if (*path != '\0')
- return false;
-
- return true;
-}
-
-/* Buffer allocation wrapper */
-static void *mflash_page_buf_get(void)
-{
- void *page_buf;
-#ifdef FSL_RTOS_FREE_RTOS
- page_buf = pvPortMalloc(MFLASH_PAGE_SIZE);
-#else
- page_buf = malloc(MFLASH_PAGE_SIZE);
-#endif
- return page_buf;
-}
-
-/* Buffer allocation wrapper */
-static void mflash_page_buf_release(void *page_buf)
-{
-#ifdef FSL_RTOS_FREE_RTOS
- vPortFree(page_buf);
-#else
- free(page_buf);
-#endif
-}
-
-/* Low level abstraction - erase sector of the filesystem */
-static status_t mflash_fs_sector_erase(mflash_fs_t *fs, uint32_t sector_offset)
-{
- uint32_t phys_addr;
-
- /* Translate filesystem offset to physical address in FLASH */
- phys_addr = mflash_drv_log2phys((uint8_t *)fs + sector_offset, MFLASH_SECTOR_SIZE);
- if (phys_addr == MFLASH_INVALID_ADDRESS)
- return kStatus_Fail;
-
- return mflash_drv_sector_erase(phys_addr);
-}
-
-/* Low level abstraction - program page of the filesystem */
-static status_t mflash_fs_page_program(mflash_fs_t *fs, uint32_t page_offset, uint32_t *data)
-{
- uint32_t phys_addr;
-
- /* Translate filesystem offset to physical address in FLASH */
- phys_addr = mflash_drv_log2phys((uint8_t *)fs + page_offset, MFLASH_PAGE_SIZE);
- if (phys_addr == MFLASH_INVALID_ADDRESS)
- return kStatus_Fail;
-
- return mflash_drv_page_program(phys_addr, data);
-}
-
-/* Low level abstraction - get pointer to filesystem location specified by offset */
-static inline void *mflash_fs_get_ptr(mflash_fs_t *fs, uint32_t offset)
-{
- return (void *)((uint8_t *)fs + offset);
-}
-
-/*
- * Check whether give area of FLASH is readable by direct pointer access.
- * This is necessary on plaforms featuring page checksums as access to page containing invalid data may result in a
- * hardfault.
- */
-static status_t mflash_readable_check(void *ptr, uint32_t size)
-{
-#if MFLASH_PAGE_INTEGRITY_CHECKS
- status_t status;
-
- uintptr_t start_addr = (uintptr_t)ptr - (uintptr_t)ptr % MFLASH_PAGE_SIZE;
- uintptr_t end_addr = (uintptr_t)ptr + size;
-
- for (uintptr_t check_addr = start_addr; check_addr < end_addr; check_addr += MFLASH_PAGE_SIZE)
+ /* Store reference to user*/
+ g_file_table = user_file_table;
+ /* Init flash driver */
+ if (init_drv)
{
- status = mflash_drv_is_readable(check_addr);
- if (status != kStatus_Success)
- return status;
+ mflash_drv_init();
}
- return kStatus_Success;
-#else
- return kStatus_Success;
-#endif
-}
-
-/* Check for filesystem presence and validity */
-static status_t mflash_fs_check(mflash_fs_t *fs)
-{
- status_t status;
-
- /* Check params */
- if (fs == NULL)
- return kStatus_InvalidArgument;
-
- /* Check readability before accessing filesystem structure by pointer */
- status = mflash_readable_check(fs, sizeof(mflash_fs_header_t));
- if (status != kStatus_Success)
- return status;
-
- /* Check magic */
- if (fs->header.magic_no != MFLASH_DIR_MAGIC_NO)
- return kStatus_Fail;
-
- /* Check major version */
- if ((fs->header.version & 0xFFFF0000) != (MFLASH_FS_VERSION & 0xFFFF0000))
- return kStatus_Fail;
-
- /* Check FLASH memory characteristics */
- if (fs->header.page_size != MFLASH_PAGE_SIZE || fs->header.sector_size != MFLASH_SECTOR_SIZE)
- return kStatus_Fail;
-
- /* Check readability of the whole directory */
- status =
- mflash_readable_check(fs, sizeof(mflash_fs_header_t) + fs->header.file_count * sizeof(mflash_dir_record_t));
-
- return status;
+ g_mflash_initialized = true;
+ return true;
}
-/* Check for presence of a file data */
-static status_t mflash_file_check(mflash_fs_t *fs, mflash_dir_record_t *dr)
+/* Find a file in file_table */
+int32_t mflash_find_file(char *path, mflash_file_t *file)
{
- status_t status;
- mflash_file_meta_t *meta;
-
- /* Check params */
- if (fs == NULL)
- return kStatus_InvalidArgument;
-
- if (dr == NULL)
- return kStatus_InvalidArgument;
-
- /* Get pointer to file meta structure */
- meta = mflash_fs_get_ptr(fs, dr->file_offset);
-
- /* Check readability before accessing file meta structure */
- status = mflash_readable_check(meta, sizeof(mflash_file_meta_t));
- if (status != kStatus_Success)
- return status;
-
- /* Check magic signature */
- if (meta->magic_no != MFLASH_META_MAGIC_NO)
- return kStatus_Fail;
-
- /* Check wheter actual file size in meta fits the pre-allocated area */
- if (meta->file_size + sizeof(mflash_file_meta_t) > dr->alloc_size)
- return kStatus_Fail;
+ int32_t status = -1;
- /* Check readability of the whole file */
- status = mflash_readable_check(meta, sizeof(mflash_file_meta_t) + meta->file_size);
+ /* Check file_table */
+ if (NULL == g_file_table)
+ return -1;
- return kStatus_Success;
-}
-
-/* Searches for directory record with given path and retrieves a copy of it */
-static status_t mflash_dir_lookup(mflash_fs_t *fs, char *path, mflash_dir_record_t *dr_ptr)
-{
- int file_count = fs->header.file_count;
- mflash_dir_record_t *dr = fs->records;
-
- for (int i = 0; i < file_count; i++)
+ for (mflash_file_t *tmp_file = g_file_table; (0 != tmp_file->flash_addr) && (0 != tmp_file->max_size);
+ tmp_file += 1)
{
- if (dir_path_match(dr, path))
+ /* Found a file by path */
+ if (0 == strncmp(path, tmp_file->path, 64))
{
- if (dr_ptr)
- *dr_ptr = *dr;
- return kStatus_Success;
+ status = 0;
+ *file = *tmp_file;
+ break;
}
- dr++;
}
-
- return kStatus_Fail;
+ return status;
}
-/* Create filesystem structure in FLASH according to given directory template */
-static status_t mflash_format_internal(mflash_fs_t *fs,
- void *page_buf,
- uint32_t fs_size_limit,
- const mflash_file_t *dir_template)
+/* NOTE: Don't try to store constant data that are located in XIP !! */
+/* API, write to file of path 'pcFileName' */
+int mflash_save_file(char *pcFileName, uint8_t *pucData, uint32_t ulDataSize)
{
- status_t status;
-
- int file_count;
- int total_sectors;
+ mflash_file_t tmp_file = {0};
+ mfile_meta_t tmp_meta = {0};
- int dir_size;
- int dir_sectors;
+ /* No file was found in file table */
+ if (0 != mflash_find_file(pcFileName, &tmp_file))
+ return false;
+ /* Trying to write data over file boundary */
+ if (ulDataSize > tmp_file.max_size + sizeof(tmp_meta))
+ return false;
- uint32_t file_offset;
- uint32_t dir_offset;
+ /* Erase sector for the new file - files are aligned with sectors */
+ if (0 != mflash_drv_sector_erase(tmp_file.flash_addr))
+ return false;
- mflash_fs_header_t *fsh;
+ /* Set meta data */
+ tmp_meta.magic_no = MFLASH_META_MAGIC_NO;
+ tmp_meta.file_size = ulDataSize;
- /* The directory records shall be aligned to page size */
- assert((MFLASH_PAGE_SIZE % sizeof(mflash_dir_record_t)) == 0);
+ uint32_t page_buff[MFLASH_PAGE_SIZE / sizeof(uint32_t)];
+ /* Prepare first page - start with meta data */
+ memcpy(page_buff, &tmp_meta, sizeof(tmp_meta));
- /* Count the files and calculate number of FLASH sectors to be occupied by the filesystem */
- file_count = 0;
- total_sectors = 0;
- for (const mflash_file_t *dt = dir_template; dt->path && dt->path[0] && dt->max_size; dt++)
+ uint32_t data_len = MFLASH_PAGE_SIZE - sizeof(tmp_meta);
+ if (data_len > ulDataSize)
{
- /* Calculate number of sectors to be occupied by the file */
- int file_sectors = (dt->max_size + MFLASH_SECTOR_SIZE - 1) / MFLASH_SECTOR_SIZE;
- total_sectors += file_sectors;
- file_count++;
+ data_len = ulDataSize;
}
- dir_size = file_count * sizeof(mflash_dir_record_t) + sizeof(mflash_fs_header_t);
- dir_sectors = (dir_size + MFLASH_SECTOR_SIZE - 1) / MFLASH_SECTOR_SIZE;
- total_sectors += dir_sectors;
-
- /* Check whether the filestytem fits into the given FLASH area */
- if (fs_size_limit && (fs_size_limit < total_sectors * MFLASH_SECTOR_SIZE))
- return kStatus_OutOfRange;
+ /* Fill the page buffer with data */
+ memcpy((void *)((uint32_t)page_buff + sizeof(tmp_meta)), pucData, data_len);
- /* Erase the whole FLASH area to be occupied by the filesystem */
- for (int i = 0; i < total_sectors; i++)
- {
- status = mflash_fs_sector_erase(fs, i * MFLASH_SECTOR_SIZE);
- if (status != kStatus_Success)
- return status;
- }
-
- /* Clear the page buffer and set inital values for offsets */
- memset(page_buf, MFLASH_BLANK_PATTERN, MFLASH_PAGE_SIZE);
- dir_offset = file_count * sizeof(mflash_dir_record_t) + sizeof(mflash_fs_header_t);
- file_offset = total_sectors * MFLASH_SECTOR_SIZE;
+ /* Write the page */
+ if (0 != mflash_drv_page_program(tmp_file.flash_addr, page_buff))
+ return false;
- /* Create directory entries in reverse order so that programming of the page containing the dir header is the last
- * step */
- for (int fi = file_count; fi--;)
+ uint32_t written = data_len;
+ uint32_t page_idx = 1;
+ while (written < ulDataSize)
{
- /* Check for enough space for the directory record */
- assert(dir_offset >= sizeof(mflash_dir_record_t));
-
- dir_offset -= sizeof(mflash_dir_record_t);
-
- mflash_dir_record_t *dr = (mflash_dir_record_t *)((uint8_t *)page_buf + (dir_offset % MFLASH_PAGE_SIZE));
- const mflash_file_t *dt = &dir_template[fi];
-
- /* Calculate number of sectors to be occupied by the file */
- int file_sectors = (dt->max_size + MFLASH_SECTOR_SIZE - 1) / MFLASH_SECTOR_SIZE;
-
- /* Fill in directory record */
- dr->alloc_size = file_sectors * MFLASH_SECTOR_SIZE;
- dr->file_offset = (file_offset -= dr->alloc_size);
- dir_path_store(dr, dt->path);
-
- if (dir_offset % MFLASH_PAGE_SIZE == 0)
+ data_len = ulDataSize - written;
+ if (data_len > MFLASH_PAGE_SIZE)
{
- /* We reached the beginning of a page, program it and start over */
- status = mflash_fs_page_program(fs, dir_offset, page_buf);
- if (status != kStatus_Success)
- return status;
-
- /* Clear the page buffer */
- memset(page_buf, MFLASH_BLANK_PATTERN, MFLASH_PAGE_SIZE);
+ data_len = MFLASH_PAGE_SIZE;
}
- }
-
- /* There should be space left exactly for the filesystem header */
- assert(dir_offset == sizeof(mflash_fs_header_t));
-
- /* Create filesystem header at the very beginning of the first page */
- fsh = (mflash_fs_header_t *)page_buf;
- fsh->magic_no = MFLASH_DIR_MAGIC_NO;
- fsh->version = MFLASH_FS_VERSION;
- fsh->page_size = MFLASH_PAGE_SIZE;
- fsh->sector_size = MFLASH_SECTOR_SIZE;
- fsh->total_size = total_sectors * MFLASH_SECTOR_SIZE;
- fsh->file_count = file_count;
- /* Programming of the first page puts header into place marking the filesystem as valid */
- status = mflash_fs_page_program(fs, 0, page_buf);
-
- return status;
-}
-
-/* API - Create filesystem structure in FLASH according to given directory template */
-status_t mflash_format(mflash_fs_t *fs, uint32_t fs_size_limit, const mflash_file_t *dir_template)
-{
- status_t status;
- void *page_buf;
-
- /* Check parameters */
- if (dir_template == NULL)
- return kStatus_InvalidArgument;
-
- /* Get page buffer for FLASH writes */
- page_buf = mflash_page_buf_get();
- if (page_buf == NULL)
- return kStatus_Fail;
-
- /* Actual formatting of the filesystem */
- status = mflash_format_internal(fs, page_buf, fs_size_limit, dir_template);
-
- /* Release page buffer */
- mflash_page_buf_release(page_buf);
-
- return status;
-}
-
-/* Match dir against given template. Checks whether all files defined in the template are pre-allocsated in the fs
- * directory */
-status_t mflash_template_match(mflash_fs_t *fs, const mflash_file_t *dir_template)
-{
- status_t status;
-
- for (const mflash_file_t *dt = dir_template; dt->path && dt->path[0] && dt->max_size; dt++)
- {
- mflash_dir_record_t dr;
-
- /* Lookup directory record */
- status = mflash_dir_lookup(fs, dt->path, &dr);
- if (status != kStatus_Success)
- return status;
-
- /* Check whether pre-allocated size is sufficient */
- if (dr.alloc_size < dt->max_size)
- return kStatus_Fail;
- }
-
- return kStatus_Success;
-}
-
-/* Initialize mflash driver and filesystem */
-static status_t mflash_fs_init(mflash_fs_t *fs, uint32_t fs_size_limit, const mflash_file_t *dir_template)
-{
- status_t status;
-
- /* Check whether there is a filesystem header and directory already in place */
- status = mflash_fs_check(fs);
-
- /* Filesystem is valid, check whether its directory provides records for all required files */
- if (status == kStatus_Success)
- status = mflash_template_match(fs, dir_template);
-
- /* The filesystem not present or does not fit the template, create a new one */
- if (status == kStatus_Fail) /* Error codes other then 'Fail' are not captured here but rather intentinally passed to
- the caller */
- status = mflash_format(fs, fs_size_limit, dir_template); /* Format the filestem */
-
- if (status == kStatus_Success)
- g_mflash_fs = fs; /* If all went ok, keep pointer to the filesytem */
-
- return status;
-}
-
-/* API - Initialize mflash driver and filesystem at default address specified by linker symbol */
-status_t mflash_init(const mflash_file_t *dir_template, bool init_drv)
-{
- status_t status;
- mflash_fs_t *fs;
-
- /* Initialize the driver */
- if (init_drv)
- {
- status = mflash_drv_init();
- if (status == kStatus_Fail)
- return status;
- }
+ /* Fill page buffer with next data */
+ memcpy(page_buff, pucData + written, data_len);
-#ifdef MFLASH_FILE_BASEADDR
- /* Convert physical address in FLASH to memory pointer */
- fs = (mflash_fs_t *)mflash_drv_phys2log(MFLASH_FILE_BASEADDR, 0);
-#else
- /* Otherwise take address from linker file */
- fs = (mflash_fs_t *)MFLASH_FS_START;
-#endif
-
- if (fs == NULL)
- return kStatus_Fail;
-
- return mflash_fs_init(fs, 0, dir_template);
-}
-
-/* Save file */
-static status_t mflash_file_save_internal(
- mflash_fs_t *fs, void *page_buf, mflash_dir_record_t *dr, uint8_t *data, uint32_t size)
-{
- status_t status;
-
- /* Check whether the data + meta fits into the pre-allocated file area */
- if (size + sizeof(mflash_file_meta_t) > dr->alloc_size)
- return kStatus_OutOfRange;
-
- /* Erase the whole file area sector by sector */
- for (int sector_offset = 0; sector_offset < dr->alloc_size; sector_offset += MFLASH_SECTOR_SIZE)
- {
- /* Erase the sector */
- status = mflash_fs_sector_erase(fs, dr->file_offset + sector_offset);
- if (status != kStatus_Success)
- return status;
- }
-
- /* Program the file data page by page, skipping the first page containing meta that is going to be programmed in the
- * last step */
- for (int data_offset = MFLASH_PAGE_SIZE - sizeof(mflash_file_meta_t); data_offset < size;
- data_offset += MFLASH_PAGE_SIZE)
- {
- /* Pointer and size of the data portion to be programmed */
- void *copy_ptr = data + data_offset;
- int copy_size = size - data_offset;
- if (copy_size > MFLASH_PAGE_SIZE)
- copy_size = MFLASH_PAGE_SIZE;
-
- memset(page_buf, MFLASH_BLANK_PATTERN, MFLASH_PAGE_SIZE);
- memcpy(page_buf, copy_ptr, copy_size);
+ /* Write the page */
+ if (0 != mflash_drv_page_program(tmp_file.flash_addr + page_idx * MFLASH_PAGE_SIZE, page_buff))
+ return false;
- /* Data offset is off by sizeof(mflash_file_meta_t) as this structure occupies the very beginning of the first
- * page */
- status = mflash_fs_page_program(fs, dr->file_offset + data_offset + sizeof(mflash_file_meta_t), page_buf);
- if (status != kStatus_Success)
- return status;
+ written += data_len;
+ page_idx++;
}
- /* Prepare the missing portion of data to be programme to the first page */
- int copy_size = size;
- if (copy_size > MFLASH_PAGE_SIZE - sizeof(mflash_file_meta_t))
- copy_size = MFLASH_PAGE_SIZE - sizeof(mflash_file_meta_t);
-
- memset(page_buf, MFLASH_BLANK_PATTERN, MFLASH_PAGE_SIZE);
- memcpy((uint8_t *)page_buf + sizeof(mflash_file_meta_t), data, copy_size);
-
- /* Set file metadata */
- mflash_file_meta_t *meta = (mflash_file_meta_t *)page_buf;
- meta->file_size = size;
- meta->magic_no = MFLASH_META_MAGIC_NO;
-
- /* Program the first page putting the metadata in place which marks the file as valid */
- status = mflash_fs_page_program(fs, dr->file_offset, page_buf);
-
- return status;
-}
-
-/* API, save data to file with given path */
-status_t mflash_file_save(char *path, uint8_t *data, uint32_t size)
-{
- status_t status;
- mflash_dir_record_t dr;
- mflash_fs_t *fs = g_mflash_fs;
- void *page_buf;
-
- if (path == NULL)
- return kStatus_InvalidArgument;
-
- if (data == NULL && size != 0)
- return kStatus_InvalidArgument;
-
- /* Lookup directory record */
- status = mflash_dir_lookup(fs, path, &dr);
- if (status != kStatus_Success)
- return status;
-
- /* Get page buffer for FLASH writes */
- page_buf = mflash_page_buf_get();
- if (page_buf == NULL)
- return kStatus_Fail;
-
- /* Save the file */
- status = mflash_file_save_internal(fs, page_buf, &dr, data, size);
-
- /* Release page buffer */
- mflash_page_buf_release(page_buf);
-
- return status;
-}
-
-/* Get direct pointer to file data */
-static status_t mflash_file_mmap_internal(mflash_fs_t *fs, mflash_dir_record_t *dr, uint8_t **pdata, uint32_t *psize)
-{
- status_t status;
- mflash_file_meta_t *meta;
-
- status = mflash_file_check(fs, dr);
- if (status != kStatus_Success)
- return status;
-
- meta = mflash_fs_get_ptr(fs, dr->file_offset);
-
- *pdata = (uint8_t *)meta + sizeof(*meta);
- *psize = meta->file_size;
-
- return kStatus_Success;
+ return true;
}
-/* API, get direct pointer to data of file with given path */
-status_t mflash_file_mmap(char *path, uint8_t **pdata, uint32_t *psize)
+/* API, read file of path 'pcFileName' */
+int mflash_read_file(char *pcFileName, uint8_t **ppucData, uint32_t *pulDataSize)
{
- status_t status;
- mflash_dir_record_t dr;
- mflash_fs_t *fs = g_mflash_fs;
-
- if (path == NULL)
- return kStatus_InvalidArgument;
-
- if (pdata == NULL || psize == NULL)
- return kStatus_InvalidArgument;
-
- /* Lookup directory record */
- status = mflash_dir_lookup(fs, path, &dr);
- if (status != kStatus_Success)
- return status;
-
- status = mflash_file_mmap_internal(fs, &dr, pdata, psize);
+ mflash_file_t tmp_file = {0};
+ mfile_meta_t *tmp_meta = NULL;
+ /* No file was found in file table */
+ if (0 != mflash_find_file(pcFileName, &tmp_file))
+ return false;
+ /* Check whether address is set */
+ if (0 == tmp_file.flash_addr)
+ return false;
+ /* Obtain pointer to meta data */
+ tmp_meta = (mfile_meta_t *)mflash_drv_phys2log(tmp_file.flash_addr, sizeof(mfile_meta_t));
+ /* To avoid hard-fault better check NULL ptr */
+ if (NULL == tmp_meta)
+ return false;
+ /* Magic number does not match, this location is not a valid file */
+ if (MFLASH_META_MAGIC_NO != tmp_meta->magic_no)
+ return false;
+ /* Set file size */
+ *pulDataSize = tmp_meta->file_size;
+ /* Obtain pointer to real_data */
+ *ppucData = (uint8_t *)mflash_drv_phys2log(tmp_file.flash_addr + sizeof(mfile_meta_t), tmp_meta->file_size);
+ if (NULL == *ppucData)
+ return false;
- return status;
+ return true;
}
diff --git a/components/flash/mflash/mflash_file.h b/components/flash/mflash/mflash_file.h
index 794ad2573..57d2056b3 100644
--- a/components/flash/mflash/mflash_file.h
+++ b/components/flash/mflash/mflash_file.h
@@ -7,32 +7,22 @@
#ifndef __MFLASH_FILE__
#define __MFLASH_FILE__
-#include "fsl_common.h"
-
#include "mflash_drv.h"
+#include "mflash_params.h"
-#define MFLASH_MAX_PATH_LEN 56
-
-/*
- * Template for file record defines file path and size to be pre-allocated for that file.
- * The actual size of the file shall not exceed the size defined in the template.
- */
typedef struct
{
- char *path;
+ uint32_t flash_addr;
uint32_t max_size;
+ char path[64];
} mflash_file_t;
-/*! @brief Initialization status of mflash subsystem */
bool mflash_is_initialized(void);
-/*! @brief Initializes mflash filesystem and driver. Creates new filesystem unless already in place. */
-status_t mflash_init(const mflash_file_t *dir_template, bool init_drv);
+int mflash_init(mflash_file_t *user_file_table, bool init_drv);
-/*! @brief Saves data to file with given path. */
-status_t mflash_file_save(char *path, uint8_t *data, uint32_t size);
+int mflash_read_file(char *pcFileName, uint8_t **ppucData, uint32_t *pulDataSize);
-/*! @brief Returns pointer for direct memory mapped access to file data. */
-status_t mflash_file_mmap(char *path, uint8_t **pdata, uint32_t *psize);
+int mflash_save_file(char *pcFileName, uint8_t *pucData, uint32_t ulDataSize);
#endif
diff --git a/components/flash/mflash/mw320/component_mflash_mw320.cmake b/components/flash/mflash/mw320/component_mflash_mw320.cmake
new file mode 100644
index 000000000..3033bfe6d
--- /dev/null
+++ b/components/flash/mflash/mw320/component_mflash_mw320.cmake
@@ -0,0 +1,15 @@
+#Description: mflash mw320; user_visible: True
+include_guard(GLOBAL)
+message("component_mflash_mw320 component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/mflash_drv.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(component_mflash_common)
+include(driver_mw_qspi)
diff --git a/components/flash/mflash/mw320/mflash_drv.c b/components/flash/mflash/mw320/mflash_drv.c
new file mode 100644
index 000000000..ece7732fd
--- /dev/null
+++ b/components/flash/mflash/mw320/mflash_drv.c
@@ -0,0 +1,1351 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include
+
+#include "mflash_drv.h"
+#include "board.h"
+#include "fsl_qspi.h"
+#include "fsl_flashc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define FLASH_INS_CODE_WE 0x06 /*!< Write enable */
+#define FLASH_INS_CODE_WE_VSR 0x50 /*!< Write enable for volatile status register */
+#define FLASH_INS_CODE_WD 0x04 /*!< Write disable */
+#define FLASH_INS_CODE_RSR1 0x05 /*!< Read status register 1 */
+#define FLASH_INS_CODE_RSR2 0x35 /*!< Read status register 2 */
+#define FLASH_INS_CODE_WSR1 0x01 /*!< Write status register 1 */
+#define FLASH_INS_CODE_WSR2 0x31 /*!< Write status register 2 */
+#define FLASH_INS_CODE_PP 0x02 /*!< Page program */
+#define FLASH_INS_CODE_QPP 0x32 /*!< Quad page program */
+#define FLASH_INS_CODE_QPP_MX 0x38 /*!< Quad page program for Macronix chip*/
+#define FLASH_INS_CODE_SE 0x20 /*!< Sector(4k) erase */
+#define FLASH_INS_CODE_BE_32K 0x52 /*!< Block(32k) erase */
+#define FLASH_INS_CODE_BE_64K 0xD8 /*!< Block(64k) erase */
+#define FLASH_INS_CODE_CE 0xC7 /*!< Chip erase */
+#define FLASH_INS_CODE_PD 0xB9 /*!< Power down */
+
+#define FLASH_INS_CODE_RD 0x03 /*!< Read data */
+#define FLASH_INS_CODE_FR 0x0B /*!< Fast read */
+#define FLASH_INS_CODE_FRDO 0x3B /*!< Fast read dual output */
+#define FLASH_INS_CODE_FRQO 0x6B /*!< Fast read quad output */
+#define FLASH_INS_CODE_FRDIO 0xBB /*!< Fast read dual IO */
+#define FLASH_INS_CODE_FRQIO 0xEB /*!< Fast read quad IO */
+#define FLASH_INS_CODE_WFRQIO 0xE7 /*!< Word Fast read quad IO, A0 must be zero */
+#define FLASH_INS_CODE_OWFRQIO 0xE3 /*!< Octal word Fast read quad IO, A[3:0] must be zero */
+#define FLASH_INS_CODE_FDRST 0xFFFF /*!< Fast dual read mode reset */
+#define FLASH_INS_CODE_FQRST 0xFF /*!< Fast quad read mode reset */
+
+#define FLASH_INS_CODE_RPD_DI 0xAB /*!< Release power down or device ID */
+#define FLASH_INS_CODE_RUID 0x4B /*!< Read unique ID number */
+#define FLASH_INS_CODE_JEDEC_ID 0x9F /*!< Read JEDEC ID number */
+
+/*! @brief Flash read type */
+typedef enum
+{
+ kFLASH_NormalRead, /*!< Normal read mode */
+ kFLASH_FastRead, /*!< Fast read mode */
+ kFLASH_FastReadDualOUT, /*!< Fast read dual output mode */
+ kFLASH_FastReadDaulIO, /*!< Fast read dual IO mode */
+ kFLASH_FastReadQuadOUT, /*!< Fast read quad output mode */
+ kFLASH_FastReadQuadIO, /*!< Fast read quad IO mode */
+ kFLASH_WordFastReadQuadIO, /*!< Word fast read quad IO mode */
+ kFLASH_OctalWordFastReadQuadIO, /*!< Octal word fast read quad IO mode */
+} flash_read_mode_type_t;
+
+/*! @brief Flash program type */
+typedef enum
+{
+ kFLASH_ProgramNormal, /*!< Normal page program mode */
+ kFLASH_ProgramQuad, /*!< Quad page program mode */
+} flash_program_mode_type_t;
+
+#define KILO_BYTE 0x400 /*!< 1KB */
+#define MEGA_BYTE 0x100000 /*!< 1MB */
+
+#define FLASH_32K_BLOCK_SIZE 0x8000 /*!< 32KB */
+#define FLASH_64K_BLOCK_SIZE 0x10000 /*!< 64KB */
+
+/*! Get the page number according to the address with the page space */
+#define FLASH_PAGE_NUM(addr) ((addr) >> 8)
+
+#define FLASH_NAME_SIZE 16
+
+/*! @brief Flash device configuration structure */
+struct FlashDeviceConfig
+{
+ char name[FLASH_NAME_SIZE]; /*!< Flash name. */
+ uint32_t jedecId; /*!< JEDEC ID. */
+ uint32_t chipSize; /*!< Flash memory size. */
+ uint32_t sectorSize; /*!< Flash memory sector size. */
+ uint32_t blockSize; /*!< Flash memory block size. */
+ uint16_t pageSize; /*!< Flash memory page size. */
+};
+
+const struct FlashDeviceConfig flashDevList[] = {
+ {"W25Q80BL", 0xef4014, 1 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"W25Q16CL", 0xef4015, 2 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"W25Q32BV", 0xef4016, 4 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"W25Q32JV", 0xef4016, 4 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"W25Q64CV", 0xef4017, 8 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"W25Q128BV", 0xef4018, 16 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"GD25Q16B", 0xc84015, 2 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"GD25Q16C", 0xc84015, 2 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"GD25Q32C", 0xc84016, 4 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"GD25LQ32C", 0xc86016, 4 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"GD25Q127C", 0xc84018, 16 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25L8035E", 0xc22014, 1 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25L3233F", 0xc22016, 4 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25L6433F", 0xc22017, 8 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25L12835F", 0xc22018, 16 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25R512F", 0xc22810, 64 * KILO_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25R1035F", 0xc22811, 128 * KILO_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25R2035F", 0xc22812, 256 * KILO_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25R4035F", 0xc22813, 512 * KILO_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25R8035F", 0xc22814, 1 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25R1635F", 0xc22815, 2 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25R3235F", 0xc22816, 4 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25R6435F", 0xc22817, 8 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25V512F", 0xc22310, 64 * KILO_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25V1035F", 0xc22311, 128 * KILO_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25V2035F", 0xc22312, 256 * KILO_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25V4035F", 0xc22313, 512 * KILO_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25V8035F", 0xc22314, 1 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+ {"MX25V1635F", 0xc22315, 2 * MEGA_BYTE, 4 * KILO_BYTE, 64 * KILO_BYTE, 256},
+};
+
+#define FLASH_WEL_BIT_SET 0x02U
+#define FLASH_WEL_BIT_CLEAR 0x00U
+
+#ifndef FLASH_DEFAULT_INDEX
+#define FLASH_DEFAULT_INDEX (0x0C)
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static status_t FLASH_CheckWriteEnableLatch(QSPI_Type *base);
+static uint8_t FLASH_GetStatusReg(QSPI_Type *base, uint8_t index);
+static bool FLASH_GetBusyStatus(QSPI_Type *base);
+
+/*******************************************************************************
+ * Variables
+ *****************************************************************************/
+/* Flash address offset from AHB access. */
+static uint32_t mflashOffset;
+static bool mflashInitialized;
+
+static const struct FlashDeviceConfig *g_flashConfig = &flashDevList[FLASH_DEFAULT_INDEX];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static status_t FLASH_CheckWriteEnableLatch(QSPI_Type *base)
+{
+ status_t status = kStatus_Success;
+ uint32_t statusReg1Val = 0x00U;
+
+ /*Check WEL bit is cleared or not. */
+ statusReg1Val = FLASH_GetStatusReg(base, 0x01U);
+ if ((statusReg1Val & FLASH_WEL_BIT_SET) == FLASH_WEL_BIT_SET)
+ {
+ status = kStatus_Fail;
+ }
+
+ return status;
+}
+
+/* Set flash write enable / disable */
+static void FLASH_WriteEnable(QSPI_Type *base, bool enable)
+{
+ qspi_header_count_config_t config;
+
+ config.instructionCnt = kQSPI_InstructionCnt1Byte;
+ config.addressCnt = kQSPI_AddressCnt0Byte;
+ config.readModeCnt = kQSPI_ReadModeCnt0Byte;
+ config.dummyCnt = kQSPI_DummyCnt0Byte;
+
+ /* Clear QSPI1 FIFO */
+ QSPI_FlushFIFO(base);
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter */
+ QSPI_SetHeaderCount(base, &config);
+
+ /* Set data in counter */
+ QSPI_SetDataInCnt(base, 0x00U);
+
+ if (enable == true)
+ {
+ /* Set instruction for write enable. */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_WE);
+ }
+ else
+ {
+ /* Set instruction for write disable. */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_WD);
+ }
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+}
+
+/* Write enable for volatile status register */
+static void FLASH_WriteEnableVolatileStatusReg(QSPI_Type *base)
+{
+ qspi_header_count_config_t config;
+
+ config.instructionCnt = kQSPI_InstructionCnt1Byte;
+ config.addressCnt = kQSPI_AddressCnt0Byte;
+ config.readModeCnt = kQSPI_ReadModeCnt0Byte;
+ config.dummyCnt = kQSPI_DummyCnt0Byte;
+
+ /* Clear QSPI1 FIFO */
+ QSPI_FlushFIFO(base);
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter */
+ QSPI_SetHeaderCount(base, &config);
+
+ /* Set data in counter */
+ QSPI_SetDataInCnt(base, 0x00U);
+
+ /* Set instruction for volatile status register. */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_WE_VSR);
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+}
+
+/* Reset Flash Continuous Quad Read mode */
+static void FLASH_ResetFastReadQuad(QSPI_Type *base)
+{
+ qspi_header_count_config_t config;
+
+ config.instructionCnt = kQSPI_InstructionCnt1Byte;
+ config.addressCnt = kQSPI_AddressCnt0Byte;
+ config.readModeCnt = kQSPI_ReadModeCnt1Byte;
+ config.dummyCnt = kQSPI_DummyCnt0Byte;
+
+ /* Clear QSPI1 FIFO */
+ QSPI_FlushFIFO(base);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinQuad);
+
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinSingle);
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter */
+ QSPI_SetHeaderCount(base, &config);
+
+ /* Set read mode. */
+ QSPI_SetReadMode(base, 0x00U);
+
+ /* Set data in counter */
+ QSPI_SetDataInCnt(base, 0x00U);
+
+ /* Set instruction for fast read quad mode reset. */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_FQRST);
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+}
+
+/* Get the flash status register value */
+static uint8_t FLASH_GetStatusReg(QSPI_Type *base, uint8_t index)
+{
+ uint8_t status;
+ qspi_header_count_config_t config;
+
+ /* Configure header count. */
+ config.instructionCnt = kQSPI_InstructionCnt1Byte;
+ config.addressCnt = kQSPI_AddressCnt0Byte;
+ config.readModeCnt = kQSPI_ReadModeCnt0Byte;
+ config.dummyCnt = kQSPI_DummyCnt0Byte;
+
+ /* Clear QSPI1 FIFO */
+ QSPI_FlushFIFO(base);
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter */
+ QSPI_SetHeaderCount(base, &config);
+
+ /* Set data in counter */
+ QSPI_SetDataInCnt(base, 0x01U);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ if (index == 0x01U)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_RSR1);
+ }
+ else if (index == 0x02U)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_RSR2);
+ }
+
+ /* QSPI one-byte length mode */
+ QSPI_UpdateTansferLength(base, kQSPI_TransferLength1Byte);
+
+ /* Set QSPI read */
+ QSPI_StartTransfer(base, kQSPI_Read);
+
+ /* Get flash busy status */
+ status = QSPI_ReadByte(base);
+
+ /* Disable QSPI */
+ QSPI_SetSSEnable(base, false);
+
+ return status;
+}
+
+/* Write flash status register */
+static status_t FLASH_WriteStatusReg(QSPI_Type *base, uint16_t status)
+{
+ volatile uint32_t localCnt = 0;
+ uint8_t byte;
+
+ /* 0xC2 is for macronix. */
+ if (((g_flashConfig->jedecId >> 16) & 0xFF) == 0xc2)
+ {
+ FLASH_WriteEnable(base, true);
+ }
+ else
+ {
+ /* Enable flash write */
+ FLASH_WriteEnableVolatileStatusReg(base);
+ }
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_WSR1);
+
+ /* QSPI one-byte length mode */
+ QSPI_UpdateTansferLength(base, kQSPI_TransferLength1Byte);
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ /* Write status[7:0] */
+ byte = status & 0xFF;
+ QSPI_WriteByte(base, byte);
+
+ if ((g_flashConfig->jedecId != 0xc84016) && (g_flashConfig->jedecId != 0xc84018) &&
+ (((g_flashConfig->jedecId >> 16) & 0xFF) != 0xc2))
+ {
+ /* Write status[15:8] */
+ byte = (status >> 8) & 0xFF;
+ QSPI_WriteByte(base, byte);
+ }
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+
+ while (localCnt++ < 100000)
+ {
+ /* Check flash busy status */
+ if (FLASH_GetBusyStatus(base) == false)
+ {
+ if ((g_flashConfig->jedecId != 0xc84016) && (g_flashConfig->jedecId != 0xc84018))
+ {
+ return kStatus_Success;
+ }
+ else
+ {
+ break;
+ }
+ }
+ }
+
+ /* Following code is specific to GigaDevice Flash GD25Q32C
+ only and is written as per its datasheet */
+ if ((g_flashConfig->jedecId == 0xc84016) || (g_flashConfig->jedecId == 0xc84018))
+ {
+ /* Write enable for volatile status register */
+ FLASH_WriteEnableVolatileStatusReg(base);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_WSR2);
+
+ /* QSPI one-byte length mode */
+ QSPI_UpdateTansferLength(base, kQSPI_TransferLength1Byte);
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ /* Write status[15:8] */
+ byte = (status >> 8) & 0xFF;
+ QSPI_WriteByte(base, byte);
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+
+ localCnt = 0;
+ while (localCnt++ < 100000)
+ {
+ /* Check flash busy status */
+ if (FLASH_GetBusyStatus(base) == false)
+ {
+ return kStatus_Success;
+ }
+ }
+ }
+
+ return kStatus_Fail;
+}
+
+/* Get the flash busy status */
+static bool FLASH_GetBusyStatus(QSPI_Type *base)
+{
+ bool status;
+ qspi_header_count_config_t config;
+
+ /* Configure header count. */
+ config.instructionCnt = kQSPI_InstructionCnt1Byte;
+ config.addressCnt = kQSPI_AddressCnt0Byte;
+ config.readModeCnt = kQSPI_ReadModeCnt0Byte;
+ config.dummyCnt = kQSPI_DummyCnt0Byte;
+
+ /* Clear QSPI1 FIFO */
+ QSPI_FlushFIFO(base);
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter */
+ QSPI_SetHeaderCount(base, &config);
+
+ /* Set data in counter */
+ QSPI_SetDataInCnt(base, 0x01U);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_RSR1);
+
+ /* QSPI one-byte length mode */
+ QSPI_UpdateTansferLength(base, kQSPI_TransferLength1Byte);
+
+ /* Set QSPI read */
+ QSPI_StartTransfer(base, kQSPI_Read);
+
+ /* Get flash busy status */
+ status = (QSPI_ReadByte(base) & 0x01U) ? true : false;
+
+ /* Disable QSPI */
+ QSPI_SetSSEnable(base, false);
+
+ return status;
+}
+
+/* Flash sector erase */
+static status_t FLASH_SectorErase(QSPI_Type *base, uint32_t sectorNumber)
+{
+ status_t status = kStatus_Fail;
+ uint32_t sectorAddress;
+ uint32_t lastSector = (g_flashConfig->chipSize / g_flashConfig->sectorSize) - 0x01U;
+ volatile uint32_t localCnt = 0U;
+
+ if (!(sectorNumber > lastSector))
+ {
+ /* Enable flash write */
+ FLASH_WriteEnable(base, true);
+
+ /* Get start address for sector to be erased */
+ sectorAddress = sectorNumber * g_flashConfig->sectorSize;
+
+ /* Set address counter */
+ QSPI_SetAddressCnt(base, kQSPI_AddressCnt3Byte);
+
+ /* Set address pin. */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinSingle);
+
+ /* Set data pin. */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ /* Set address */
+ QSPI_SetAddress(base, sectorAddress);
+
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_SE);
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+
+ while (localCnt++ < 1000000)
+ {
+ /* Check flash busy status */
+ if (FLASH_GetBusyStatus(base) == false)
+ {
+ status = kStatus_Success;
+ break;
+ }
+ }
+ }
+
+ /*Check WEL bit is cleared or not. */
+ if (kStatus_Success != FLASH_CheckWriteEnableLatch(base))
+ {
+ status = kStatus_Fail;
+ }
+
+ return status;
+}
+
+/* Flash 32KB block erase */
+static status_t FLASH_Block32KErase(QSPI_Type *base, uint32_t blockNumber)
+{
+ status_t status = kStatus_Fail;
+ uint32_t blockAddress;
+ volatile uint32_t localCnt = 0;
+ uint32_t last32KBlock = (g_flashConfig->chipSize / FLASH_32K_BLOCK_SIZE) - 1;
+
+ if (!(blockNumber > last32KBlock))
+ {
+ /* Enable flash write */
+ FLASH_WriteEnable(base, true);
+
+ /* Get start address of the block to be erased */
+ blockAddress = blockNumber * FLASH_32K_BLOCK_SIZE;
+
+ /* Set address counter */
+ QSPI_SetAddressCnt(base, kQSPI_AddressCnt3Byte);
+
+ /* Set address pin. */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinSingle);
+
+ /* Set data pin. */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ /* Set address */
+ QSPI_SetAddress(base, blockAddress);
+
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_BE_32K);
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+
+ while (localCnt++ < 2000000)
+ {
+ /* Check flash busy status */
+ if (FLASH_GetBusyStatus(base) == false)
+ {
+ status = kStatus_Success;
+ break;
+ }
+ }
+ }
+
+ /*Check WEL bit is cleared or not. */
+ if (kStatus_Success != FLASH_CheckWriteEnableLatch(base))
+ {
+ status = kStatus_Fail;
+ }
+
+ return status;
+}
+
+/* Flash 64KB block erase */
+static status_t FLASH_Block64KErase(QSPI_Type *base, uint32_t blockNumber)
+{
+ status_t status = kStatus_Fail;
+ uint32_t blockAddress;
+ volatile uint32_t localCnt = 0;
+ uint32_t last64KBlock = (g_flashConfig->chipSize / FLASH_64K_BLOCK_SIZE) - 1;
+
+ if (!(blockNumber > last64KBlock))
+ {
+ /* Enable flash write */
+ FLASH_WriteEnable(base, true);
+
+ /* Get start address of the block to be erased */
+ blockAddress = blockNumber * FLASH_64K_BLOCK_SIZE;
+
+ /* Set address counter */
+ QSPI_SetAddressCnt(base, kQSPI_AddressCnt3Byte);
+
+ /* Set address pin. */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinSingle);
+
+ /* Set data pin. */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ /* Set address */
+ QSPI_SetAddress(base, blockAddress);
+
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_BE_64K);
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+
+ while (localCnt++ < 2000000)
+ {
+ /* Check flash busy status */
+ if (FLASH_GetBusyStatus(base) == false)
+ {
+ status = kStatus_Success;
+ break;
+ }
+ }
+ }
+
+ /*Check WEL bit is cleared or not. */
+ if (kStatus_Success != FLASH_CheckWriteEnableLatch(base))
+ {
+ status = kStatus_Fail;
+ }
+
+ return status;
+}
+
+/* Erase specfied address of the flash */
+static status_t FLASH_Erase(QSPI_Type *base, uint32_t startAddr, uint32_t endAddr)
+{
+ status_t ret;
+ uint32_t sectorNumber, blockNumber, length, validStart;
+
+ length = endAddr - startAddr + 1;
+
+ while (length != 0)
+ {
+ if ((startAddr & (FLASH_64K_BLOCK_SIZE - 1)) == 0 &&
+ length > (FLASH_64K_BLOCK_SIZE - g_flashConfig->sectorSize))
+ {
+ /* Address is a multiple of 64K and length is > (64K block -4K sector)
+ * So directly erase 64K from this address */
+ blockNumber = startAddr / FLASH_64K_BLOCK_SIZE;
+ ret = FLASH_Block64KErase(base, blockNumber);
+ endAddr = startAddr + FLASH_64K_BLOCK_SIZE;
+ }
+ else if ((startAddr & (FLASH_32K_BLOCK_SIZE - 1)) == 0 &&
+ length > (FLASH_32K_BLOCK_SIZE - g_flashConfig->sectorSize))
+ {
+ /* Address is a multiple of 32K and length is > (32K block -4K sector)
+ * So directly erase 32K from this address */
+ blockNumber = startAddr / FLASH_32K_BLOCK_SIZE;
+ ret = FLASH_Block32KErase(base, blockNumber);
+ endAddr = startAddr + FLASH_32K_BLOCK_SIZE;
+ }
+ else
+ {
+ /* Find 4K aligned address and erase 4K sector */
+ validStart = startAddr - (startAddr & (g_flashConfig->sectorSize - 1));
+ sectorNumber = validStart / g_flashConfig->sectorSize;
+ ret = FLASH_SectorErase(base, sectorNumber);
+ endAddr = validStart + g_flashConfig->sectorSize;
+ }
+
+ /* If erase operation fails then return error */
+ if (ret != kStatus_Success)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Calculate the remaining length that is to be erased yet */
+ if (length < (endAddr - startAddr))
+ {
+ length = 0;
+ }
+ else
+ {
+ length -= (endAddr - startAddr);
+ }
+
+ startAddr = endAddr;
+ }
+
+ return kStatus_Success;
+}
+
+/* Read flash from specified address to buffer */
+uint32_t FLASH_Read(QSPI_Type *base, flash_read_mode_type_t mode, uint32_t address, uint8_t *buffer, uint32_t size)
+{
+ uint32_t readBytes = 0x00U;
+ uint16_t statusWrite = 0x00U;
+ uint16_t statusReg1 = 0x00U;
+ uint16_t statusReg2 = 0x00U;
+
+ qspi_header_count_config_t config;
+
+ /* Configure header count. */
+ config.instructionCnt = kQSPI_InstructionCnt1Byte;
+ config.addressCnt = kQSPI_AddressCnt3Byte;
+ config.readModeCnt = kQSPI_ReadModeCnt0Byte;
+ config.dummyCnt = kQSPI_DummyCnt0Byte;
+
+ /* Enable quad mode. */
+ if ((mode == kFLASH_FastReadQuadOUT) || (mode == kFLASH_FastReadQuadIO) || (mode == kFLASH_WordFastReadQuadIO) ||
+ (mode == kFLASH_OctalWordFastReadQuadIO))
+ {
+ /* Get status register 1. */
+ statusReg1 = FLASH_GetStatusReg(base, 0x01U);
+
+ if (((g_flashConfig->jedecId >> 16) & 0xFF) != 0xc2U)
+ {
+ /* Get status register 2. */
+ statusReg2 = FLASH_GetStatusReg(base, 0x02U);
+ statusWrite = ((statusReg2 << 8) | statusReg1) | 0x0200U;
+ FLASH_WriteStatusReg(base, statusWrite);
+ }
+ else if ((statusReg1 & 0x40U) != 0x40U)
+ {
+ statusWrite = statusReg1 | 0x40U;
+ FLASH_WriteStatusReg(base, statusWrite);
+ }
+ }
+
+ /* Clear QSPI FIFO */
+ QSPI_FlushFIFO(base);
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter */
+ QSPI_SetHeaderCount(base, &config);
+
+ /* Set read mode */
+ QSPI_SetReadMode(base, 0x00U);
+
+ /* Set data in counter */
+ QSPI_SetDataInCnt(base, size);
+
+ /* Set address */
+ QSPI_SetAddress(base, address);
+
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinSingle);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ if (mode == kFLASH_NormalRead)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_RD);
+ }
+ else if (mode == kFLASH_FastRead)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_FR);
+
+ /* Set dummy counter */
+ QSPI_SetDummyCnt(base, kQSPI_DummyCnt1Byte);
+ }
+ else if (mode == kFLASH_FastReadDualOUT)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_FRDO);
+
+ /* Set dummy counter */
+ QSPI_SetDummyCnt(base, kQSPI_DummyCnt1Byte);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinDual);
+ }
+ else if (mode == kFLASH_FastReadDaulIO)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_FRDIO);
+
+ /* Set read mode counter */
+ QSPI_SetReadModeCnt(base, kQSPI_ReadModeCnt1Byte);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinDual);
+
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinAsData);
+ }
+ else if (mode == kFLASH_FastReadQuadOUT)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_FRQO);
+
+ /* Set dummy counter */
+ QSPI_SetDummyCnt(base, kQSPI_DummyCnt1Byte);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinQuad);
+ }
+ else if (mode == kFLASH_FastReadQuadIO)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_FRQIO);
+
+ /* Set read mode counter */
+ QSPI_SetReadModeCnt(base, kQSPI_ReadModeCnt1Byte);
+
+ /* Set dummy counter */
+ QSPI_SetDummyCnt(base, kQSPI_DummyCnt2Byte);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinQuad);
+
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinAsData);
+ }
+ else if (mode == kFLASH_WordFastReadQuadIO)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_WFRQIO);
+
+ /* Set read mode counter */
+ QSPI_SetReadModeCnt(base, kQSPI_ReadModeCnt1Byte);
+
+ /* Set dummy counter */
+ QSPI_SetDummyCnt(base, kQSPI_DummyCnt1Byte);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinQuad);
+
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinAsData);
+ }
+ else if (mode == kFLASH_OctalWordFastReadQuadIO)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_OWFRQIO);
+
+ /* Set read mode counter */
+ QSPI_SetReadModeCnt(base, kQSPI_ReadModeCnt1Byte);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinQuad);
+
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinAsData);
+ }
+ else
+ {
+ ; /* Intentional empty for MISTA C-2012 rule 15.7. */
+ }
+
+ /* QSPI one-byte length mode */
+ QSPI_UpdateTansferLength(base, kQSPI_TransferLength1Byte);
+
+ /* Set QSPI read */
+ QSPI_StartTransfer(base, kQSPI_Read);
+
+ for (uint32_t i = 0x00U; i < size; i++)
+ {
+ buffer[i] = QSPI_ReadByte(base);
+ readBytes++;
+ }
+
+ /* Disable QSPI */
+ QSPI_SetSSEnable(base, false);
+
+ return readBytes;
+}
+
+/* Program flash within a page */
+static status_t FLASH_PageProgram(
+ QSPI_Type *base, flash_program_mode_type_t mode, uint32_t address, uint8_t *buffer, uint32_t size)
+{
+ status_t status = kStatus_Fail;
+ volatile uint32_t localCnt = 0x00U;
+ uint16_t statusWrite = 0x00U;
+ uint16_t statusReg1Val = 0x00U;
+ uint16_t statusReg2Val = 0x00U;
+
+ qspi_header_count_config_t config;
+
+ /* Configure header count. */
+ config.instructionCnt = kQSPI_InstructionCnt1Byte;
+ config.addressCnt = kQSPI_AddressCnt3Byte;
+ config.readModeCnt = kQSPI_ReadModeCnt0Byte;
+ config.dummyCnt = kQSPI_DummyCnt0Byte;
+
+ if (mode == kFLASH_ProgramQuad)
+ {
+ /* Get status register 1. */
+ statusReg1Val = FLASH_GetStatusReg(base, 0x01U);
+
+ if (((g_flashConfig->jedecId >> 16) & 0xFFU) != 0xC2U)
+ {
+ /* Get status register 2. */
+ statusReg2Val = FLASH_GetStatusReg(base, 0x02U);
+ statusWrite = ((statusReg2Val << 8) | statusReg1Val) | 0x0200U;
+ FLASH_WriteStatusReg(base, statusWrite);
+ }
+ else if ((statusReg1Val & 0x40U) != 0x40U)
+ {
+ statusWrite = statusReg1Val | 0x40U;
+ FLASH_WriteStatusReg(base, statusWrite);
+ }
+ }
+
+ /* Check address validity */
+ if ((FLASH_PAGE_NUM(address + size - 1) > FLASH_PAGE_NUM(address)) || size == 0)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Enable flash write */
+ FLASH_WriteEnable(base, true);
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter */
+ QSPI_SetHeaderCount(base, &config);
+
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinSingle);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ /* Set address */
+ QSPI_SetAddress(base, address);
+
+ if (mode == kFLASH_ProgramNormal)
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_PP);
+ }
+ else if (mode == kFLASH_ProgramQuad)
+ {
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinQuad);
+
+ if (((g_flashConfig->jedecId >> 16) & 0xFFU) == 0xC2U)
+ {
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinAsData);
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_QPP_MX);
+ }
+ else
+ {
+ /* Set instruction */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_QPP);
+ }
+ }
+
+ /* QSPI one-byte length mode */
+ QSPI_UpdateTansferLength(base, kQSPI_TransferLength1Byte);
+
+ /* Set QSPI write */
+ QSPI_StartTransfer(base, kQSPI_Write);
+
+ for (uint32_t i = 0x00U; i < size; i++)
+ {
+ QSPI_WriteByte(base, buffer[i]);
+ }
+
+ /* Stop QSPI transfer */
+ QSPI_StopTransfer(base);
+
+ while (localCnt++ < 1000000)
+ {
+ /* Check flash busy status */
+ if (FLASH_GetBusyStatus(base) == false)
+ {
+ status = kStatus_Success;
+ break;
+ }
+ }
+
+ statusReg1Val = FLASH_GetStatusReg(base, 0x01U);
+
+ /* Check WEL bit is cleared or not. */
+ if ((statusReg1Val & FLASH_WEL_BIT_SET) == FLASH_WEL_BIT_SET)
+ {
+ status = kStatus_Fail;
+ }
+
+ return status;
+}
+
+/* Program flash with any address and size */
+static status_t FLASH_Program(
+ QSPI_Type *base, flash_program_mode_type_t mode, uint32_t address, uint8_t *buffer, uint32_t size)
+{
+ uint8_t *programBuf;
+ uint32_t begPgNum;
+ uint32_t endPgNum;
+ uint32_t step;
+ uint32_t currentAddr;
+ uint32_t endPgAddr;
+ status_t status = kStatus_Fail;
+
+ programBuf = buffer;
+ currentAddr = address;
+
+ /* Get page number of start address */
+ begPgNum = FLASH_PAGE_NUM(address);
+ /* Get page number of end address */
+ endPgNum = FLASH_PAGE_NUM(address + size - 1);
+
+ /* Both start address and end address are within the same page */
+ if (begPgNum == endPgNum)
+ {
+ return (FLASH_PageProgram(base, mode, address, buffer, size));
+ }
+ /* Start address and end address are not in the same page */
+ else
+ {
+ /* For first page */
+ endPgAddr = (g_flashConfig->pageSize * (FLASH_PAGE_NUM(address) + 1U) - 1U);
+ step = endPgAddr - address + 1;
+ status = FLASH_PageProgram(base, mode, address, programBuf, step);
+ if (status == kStatus_Fail)
+ {
+ return kStatus_Fail;
+ }
+
+ programBuf += step;
+ currentAddr += step;
+
+ for (uint32_t i = begPgNum + 1U; i <= endPgNum; i++)
+ {
+ /* For last page */
+ if (i == endPgNum)
+ {
+ step = (address + size) & 0xFF;
+
+ /* If step is 0, the last page has 256 bytes data to be writen ( size of data is 0x100 ) */
+ if (step == 0)
+ {
+ step = 0x100;
+ }
+
+ return (FLASH_PageProgram(base, mode, currentAddr, programBuf, step));
+ }
+ else
+ {
+ status = FLASH_PageProgram(base, mode, currentAddr, programBuf, g_flashConfig->pageSize);
+ if (status == kStatus_Fail)
+ {
+ return kStatus_Fail;
+ }
+
+ programBuf += g_flashConfig->pageSize;
+ currentAddr += g_flashConfig->pageSize;
+ }
+ }
+ }
+
+ return status;
+}
+
+/* Get JEDEC ID */
+static uint32_t FLASH_GetJEDECID(QSPI_Type *base)
+{
+ uint32_t jedecID = 0;
+ qspi_header_count_config_t config;
+
+ /* Configure header count. */
+ config.instructionCnt = kQSPI_InstructionCnt1Byte;
+ config.addressCnt = kQSPI_AddressCnt0Byte;
+ config.readModeCnt = kQSPI_ReadModeCnt0Byte;
+ config.dummyCnt = kQSPI_DummyCnt0Byte;
+
+ /* Clear QSPI FIFO */
+ QSPI_FlushFIFO(base);
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter*/
+ QSPI_SetHeaderCount(base, &config);
+
+ /* Set data in counter */
+ QSPI_SetDataInCnt(base, 0x03U);
+
+ /* Read JEDEC ID */
+ QSPI_SetInstruction(base, FLASH_INS_CODE_JEDEC_ID);
+
+ /* Set QSPI address pin mode */
+ QSPI_SetAddressPin(base, kQSPI_AddrPinSingle);
+
+ /* Set QSPI data pin mode */
+ QSPI_SetDatePin(base, kQSPI_DataPinSingle);
+
+ /* QSPI one-byte length mode */
+ QSPI_UpdateTansferLength(base, kQSPI_TransferLength1Byte);
+
+ /* Set QSPI read */
+ QSPI_StartTransfer(base, kQSPI_Read);
+
+ jedecID = QSPI_ReadByte(base);
+ jedecID <<= 8;
+ jedecID |= QSPI_ReadByte(base);
+ jedecID <<= 8;
+ jedecID |= QSPI_ReadByte(base);
+
+ /* Disable QSPI */
+ QSPI_SetSSEnable(base, false);
+
+ return jedecID;
+}
+
+static const struct FlashDeviceConfig *FLASH_GetConfigFromJedecID(uint32_t jedecID)
+{
+ uint32_t count = sizeof(flashDevList) / sizeof(struct FlashDeviceConfig);
+
+ for (uint32_t i = 0U; i < count; i++)
+ {
+ if (flashDevList[i].jedecId == jedecID)
+ {
+ return &flashDevList[i];
+ }
+ }
+
+ return NULL;
+}
+
+static status_t FLASH_SetConfig(uint32_t jedecID)
+{
+ status_t status = kStatus_Fail;
+ const struct FlashDeviceConfig *cfg;
+
+ cfg = FLASH_GetConfigFromJedecID(jedecID);
+
+ if (NULL != cfg)
+ {
+ g_flashConfig = cfg;
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+const struct FlashDeviceConfig *FLASH_GetConfig(void)
+{
+ return g_flashConfig;
+}
+
+static void FLASH_Init(QSPI_Type *base)
+{
+ qspi_config_t config;
+
+ /*Get QSPI default settings and configure the qspi */
+ QSPI_GetDefaultConfig(&config);
+
+ QSPI_Init(base, &config);
+}
+
+static status_t FLASH_EnableQSPI(void)
+{
+ return FLASHC_EnableQSPIPad(FLASHC);
+}
+
+static void FLASH_EnableFlashC(void)
+{
+ assert(g_flashConfig != NULL);
+
+ FLASHC_EnableFLASHCPad(FLASHC, kFLASHC_HardwareCmdFastReadQuadIO, g_flashConfig->jedecId);
+}
+
+/* API - initialize 'mflash' */
+int32_t mflash_drv_init(void)
+{
+ uint32_t jedecID = 0x00U;
+ status_t status;
+ uint32_t primask;
+
+ if (mflashInitialized)
+ {
+ return kStatus_Success;
+ }
+
+ assert((FLASHC->FCCR & FLASHC_FCCR_FLASHC_PAD_EN_MASK) != 0U);
+
+ if ((FLASHC->FCACR & FLASHC_FCACR_OFFSET_EN_MASK) == 0U)
+ {
+ mflashOffset = 0U;
+ }
+ else
+ {
+ mflashOffset = FLASHC->FAOFFR;
+ }
+
+ /* During QSPI operation, no interrupt allowed in XIP case. */
+ primask = DisableGlobalIRQ();
+
+ FLASH_EnableQSPI();
+
+ FLASH_Init(QSPI);
+
+ FLASH_ResetFastReadQuad(QSPI);
+
+ /*Get JEDEC ID. */
+ jedecID = FLASH_GetJEDECID(QSPI);
+
+ status = FLASH_SetConfig(jedecID);
+ if (status == kStatus_Success)
+ {
+ mflashInitialized = true;
+ }
+
+ FLASH_EnableFlashC();
+
+ EnableGlobalIRQ(primask);
+
+ return status;
+}
+
+/* Calling wrapper for 'mflash_drv_sector_erase_internal'.
+ * Erase one sector starting at 'sector_addr' - must be sector aligned.
+ */
+int32_t mflash_drv_sector_erase(uint32_t sector_addr)
+{
+ status_t status;
+ uint32_t primask;
+
+ if (0 == mflash_drv_is_sector_aligned(sector_addr))
+ return kStatus_InvalidArgument;
+
+ /* During flash operation, no interrupt allowed in XIP case. */
+ primask = DisableGlobalIRQ();
+
+ FLASH_EnableQSPI();
+
+ status = FLASH_Erase(QSPI, sector_addr, sector_addr + MFLASH_SECTOR_SIZE - 1U);
+
+ FLASH_EnableFlashC();
+
+ EnableGlobalIRQ(primask);
+
+ return status;
+}
+
+/* Calling wrapper for 'mflash_drv_page_program_internal'.
+ * Write 'data' to 'page_addr' - must be page aligned.
+ * NOTE: Don't try to store constant data that are located in XIP !!
+ */
+int32_t mflash_drv_page_program(uint32_t page_addr, uint32_t *data)
+{
+ status_t status;
+ uint32_t primask;
+
+ if (0 == mflash_drv_is_page_aligned(page_addr))
+ return kStatus_InvalidArgument;
+
+ /* During flash operation, no interrupt allowed in XIP case. */
+ primask = DisableGlobalIRQ();
+
+ FLASH_EnableQSPI();
+
+ status = FLASH_PageProgram(QSPI, kFLASH_ProgramQuad, page_addr, (uint8_t *)data, MFLASH_PAGE_SIZE);
+
+ FLASH_EnableFlashC();
+
+ EnableGlobalIRQ(primask);
+
+ return status;
+}
+
+/* API - Read data, access by FLASHC. */
+int32_t mflash_drv_read(uint32_t addr, uint32_t *buffer, uint32_t len)
+{
+ status_t status;
+ uint32_t primask;
+
+ /* Ensure current flash access via FLASHC. */
+ assert((FLASHC->FCCR & FLASHC_FCCR_FLASHC_PAD_EN_MASK) != 0U);
+ /* If physical address is larger than mflashOffset, access from FLASHC directly. */
+ if (addr > mflashOffset)
+ {
+ memcpy(buffer, (void *)(addr + MFLASH_BASE_ADDRESS - mflashOffset), len);
+ status = kStatus_Success;
+ }
+ else
+ {
+ /* During flash operation, no interrupt allowed in XIP case. */
+ primask = DisableGlobalIRQ();
+
+ FLASH_EnableQSPI();
+
+ status = (FLASH_Read(QSPI, kFLASH_FastReadQuadIO, addr, (uint8_t *)(void *)buffer, len) == len) ?
+ kStatus_Success :
+ kStatus_Fail;
+
+ FLASH_EnableFlashC();
+
+ EnableGlobalIRQ(primask);
+ }
+
+ return status;
+}
+
+/* API - Write data */
+int32_t mflash_drv_write(uint32_t addr, uint32_t *buffer, uint32_t len)
+{
+ status_t status;
+ uint32_t primask;
+
+ /* Only allow buffer in SRAM, flash address cannot be used in QSPI operation. */
+ assert(((uint32_t)buffer & 0x1F000000U) != 0x1F000000U);
+
+ /* During flash operation, no interrupt allowed in XIP case. */
+ primask = DisableGlobalIRQ();
+
+ FLASH_EnableQSPI();
+
+ status = FLASH_Program(QSPI, kFLASH_ProgramQuad, addr, (uint8_t *)buffer, len);
+
+ FLASH_EnableFlashC();
+
+ EnableGlobalIRQ(primask);
+
+ return status;
+}
+
+/* API - Erase data */
+int32_t mflash_drv_erase(uint32_t addr, uint32_t len)
+{
+ status_t status;
+ uint32_t primask;
+
+ /* During flash operation, no interrupt allowed in XIP case. */
+ primask = DisableGlobalIRQ();
+
+ FLASH_EnableQSPI();
+
+ status = FLASH_Erase(QSPI, addr, addr + len - 1U);
+
+ FLASH_EnableFlashC();
+
+ EnableGlobalIRQ(primask);
+
+ return status;
+}
+
+/* API - Get pointer to FLASH region */
+void *mflash_drv_phys2log(uint32_t addr, uint32_t len)
+{
+ assert(addr > mflashOffset);
+ return (void *)(addr + MFLASH_BASE_ADDRESS - mflashOffset);
+}
+
+/* API - Get pointer to FLASH region */
+uint32_t mflash_drv_log2phys(void *ptr, uint32_t len)
+{
+ if ((uint32_t)ptr < MFLASH_BASE_ADDRESS)
+ return kStatus_InvalidArgument;
+
+ return ((uint32_t)ptr + mflashOffset - MFLASH_BASE_ADDRESS);
+}
diff --git a/components/flash/mflash/mw320/mflash_drv.h b/components/flash/mflash/mw320/mflash_drv.h
new file mode 100644
index 000000000..890e51fe7
--- /dev/null
+++ b/components/flash/mflash/mw320/mflash_drv.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MFLASH_DRV_H__
+#define __MFLASH_DRV_H__
+
+#include "mflash_common.h"
+
+/* Flash constants */
+#ifndef MFLASH_SECTOR_SIZE
+#define MFLASH_SECTOR_SIZE (4096U)
+#endif
+
+#ifndef MFLASH_PAGE_SIZE
+#define MFLASH_PAGE_SIZE (256U)
+#endif
+
+/* Device specific settings */
+#ifndef MFLASH_QSPI
+#define MFLASH_QSPI (QSPI)
+#endif
+
+#ifndef MFLASH_BASE_ADDRESS
+#define MFLASH_BASE_ADDRESS (0x1F000000U)
+#endif
+
+#define FLASH_SIZE 0x00001000U /* 4MB in KB unit */
+
+/*! @brief Write data of arbitrary length */
+int32_t mflash_drv_write(uint32_t addr, uint32_t *buffer, uint32_t len);
+
+/*! @brief Erase data of arbitrary length */
+int32_t mflash_drv_erase(uint32_t addr, uint32_t len);
+#endif
diff --git a/components/flash/mflash/mw320/mflash_params.h b/components/flash/mflash/mw320/mflash_params.h
new file mode 100644
index 000000000..bd961a6d2
--- /dev/null
+++ b/components/flash/mflash/mw320/mflash_params.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MFLASH_PARAMS__
+#define __MFLASH_PARAMS__
+
+#include "mflash_drv.h"
+
+#define MFLASH_FILE_BASEADDR (0x000F0000) /* mem address 0x1F0F0000 */
+#define MFLASH_FILE_SIZE (MFLASH_SECTOR_SIZE)
+
+#endif
diff --git a/components/lists/fsl_component_generic_list.h b/components/lists/fsl_component_generic_list.h
index ccdc2192b..fada08c6f 100644
--- a/components/lists/fsl_component_generic_list.h
+++ b/components/lists/fsl_component_generic_list.h
@@ -15,13 +15,17 @@
* @{
*/
-/**********************************************************************************
+/*!*********************************************************************************
+*************************************************************************************
* Include
-***********************************************************************************/
+*************************************************************************************
+********************************************************************************** */
-/**********************************************************************************
+/*! *********************************************************************************
+*************************************************************************************
* Public macro definitions
-***********************************************************************************/
+*************************************************************************************
+********************************************************************************** */
/*! @brief Definition to determine whether use list light. */
#ifndef GENERIC_LIST_LIGHT
#define GENERIC_LIST_LIGHT (1)
@@ -32,9 +36,11 @@
#define GENERIC_LIST_DUPLICATED_CHECKING (0)
#endif
-/**********************************************************************************
+/*! *********************************************************************************
+*************************************************************************************
* Public type definitions
-***********************************************************************************/
+*************************************************************************************
+********************************************************************************** */
/*! @brief The list status */
typedef enum _list_status
{
@@ -70,12 +76,14 @@ typedef struct list_element_tag
struct list_label *list; /*!< pointer to the list */
} list_element_t, *list_element_handle_t;
#endif
-/**********************************************************************************
+/*! *********************************************************************************
+*************************************************************************************
* Public prototypes
-***********************************************************************************/
-/**********************************************************************************
+*************************************************************************************
+********************************************************************************** */
+/*******************************************************************************
* API
- **********************************************************************************/
+ ******************************************************************************/
#if defined(__cplusplus)
extern "C" {
@@ -166,6 +174,7 @@ list_status_t LIST_RemoveElement(list_element_handle_t element);
/*!
* @brief Links an element in the previous position relative to a given member of a list.
*
+ * @param list - Handle of the list.
* @param element - Handle of the element.
* @param newElement - New element to insert before the given member.
*
diff --git a/components/mem_manager/fsl_component_mem_manager.c b/components/mem_manager/fsl_component_mem_manager.c
index 31fff60c6..596449e37 100644
--- a/components/mem_manager/fsl_component_mem_manager.c
+++ b/components/mem_manager/fsl_component_mem_manager.c
@@ -179,7 +179,7 @@ static void MEM_BufferAllocates_memStatis(void *buffer, uint32_t time, uint32_t
s_memStatis.ram_lost += (uint16_t)(block_size - requestedSize);
UPDATE_PEAK(s_memStatis.ram_lost, s_memStatis.peak_ram_lost);
- /* UPDATE_PEAK(((uint32_t)FreeBlockHdrList.tail + BLOCK_HDR_SIZE), s_memStatis.peak_upper_addr); */
+ // UPDATE_PEAK(((uint32_t)FreeBlockHdrList.tail + BLOCK_HDR_SIZE), s_memStatis.peak_upper_addr);
#ifdef MEM_MANAGER_BENCH
if (time != 0U)
@@ -430,7 +430,7 @@ mem_status_t MEM_RemoveBuffer(uint8_t *buffer)
MEM_EXIT_CRITICAL();
return kStatus_MemUnknownError;
}
-#endif /* MEM_MANAGER_BUFFER_REMOVE */
+#endif // MEM_MANAGER_BUFFER_REMOVE
/*!
* @brief Allocate a block from the memory pools. The function uses the
diff --git a/components/mem_manager/fsl_component_mem_manager_light.c b/components/mem_manager/fsl_component_mem_manager_light.c
index 959d31d9d..80bf53f98 100644
--- a/components/mem_manager/fsl_component_mem_manager_light.c
+++ b/components/mem_manager/fsl_component_mem_manager_light.c
@@ -387,7 +387,7 @@ mem_status_t MEM_Init(void)
blockHeader_t *firstBlockHdr;
firstBlockHdr = ptr.block_hdr_ptr;
- /* MEM_DBG_LOG("%x %d\r\n", memHeap, heapSize_c/sizeof(uint32_t)); */
+ // MEM_DBG_LOG("%x %d\r\n", memHeap, heapSize_c/sizeof(uint32_t));
/* Init firstBlockHdr as a free block */
firstBlockHdr->next = NULL;
@@ -581,7 +581,7 @@ static void *MEM_BufferAllocate(uint32_t numBytes, uint8_t poolId)
/* avoid looping */
assert(FreeBlockHdr != FreeBlockHdr->next_free);
} while (true);
- /* MEM_DBG_LOG("BlockHdrFound: %x", BlockHdrFound); */
+ // MEM_DBG_LOG("BlockHdrFound: %x", BlockHdrFound);
#ifdef MEM_DEBUG_OUT_OF_MEMORY
assert(BlockHdrFound);
@@ -675,7 +675,7 @@ mem_status_t MEM_BufferFree(void *buffer /* IN: Block of memory to free*/)
MEM_BlockHeaderCheck(BlockHdr->next);
#endif
- /* MEM_DBG_LOG("%x %d", BlockHdr, BlockHdr->buff_size); */
+ // MEM_DBG_LOG("%x %d", BlockHdr, BlockHdr->buff_size);
#if defined(MEM_STATISTICS_INTERNAL)
MEM_BufferFrees_memStatis(buffer);
diff --git a/components/osa/component_osa.cmake b/components/osa/component_osa.cmake
index 776e86a78..9b2126a65 100644
--- a/components/osa/component_osa.cmake
+++ b/components/osa/component_osa.cmake
@@ -12,13 +12,13 @@ target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1052)
+if(CONFIG_USE_middleware_freertos-kernel_K32L2A41A)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1064)
+if(CONFIG_USE_middleware_freertos-kernel_K32L2B31A)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
@@ -30,109 +30,109 @@ target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_K32L2B31A)
+if(CONFIG_USE_middleware_freertos-kernel_LPC54628)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MK64F12)
+if(CONFIG_USE_middleware_freertos-kernel_LPC54S018)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MK66F18)
+if(CONFIG_USE_middleware_freertos-kernel_LPC54S018M)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_LPC54628)
+if(CONFIG_USE_middleware_freertos-kernel_LPC55S16)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MK22F51212)
+if(CONFIG_USE_middleware_freertos-kernel_LPC55S28)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1021)
+if(CONFIG_USE_middleware_freertos-kernel_LPC55S69_cm33_core0)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_LPC55S16)
+if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1011)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1062)
+if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1015)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_LPC54S018)
+if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1021)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_LPC54S018M)
+if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1024)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MKL27Z644)
+if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1052)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_LPC55S69_cm33_core0)
+if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1062)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1024)
+if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1064)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1011)
+if(CONFIG_USE_middleware_freertos-kernel_MIMXRT685S_cm33)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_LPC55S28)
+if(CONFIG_USE_middleware_freertos-kernel_MK22F51212)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_K32L2A41A)
+if(CONFIG_USE_middleware_freertos-kernel_MK64F12)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MIMXRT685S_cm33)
+if(CONFIG_USE_middleware_freertos-kernel_MK66F18)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
endif()
-if(CONFIG_USE_middleware_freertos-kernel_MIMXRT1015)
+if(CONFIG_USE_middleware_freertos-kernel_MKL27Z644)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_os_abstraction_free_rtos.c
)
diff --git a/components/osa/component_osa_free_rtos.cmake b/components/osa/component_osa_free_rtos.cmake
index 2daf78c4d..edfc56312 100644
--- a/components/osa/component_osa_free_rtos.cmake
+++ b/components/osa/component_osa_free_rtos.cmake
@@ -11,53 +11,56 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(middleware_freertos-kernel_MIMXRT1052)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(middleware_freertos-kernel_MIMXRT1064)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK28FA15")
- include(middleware_freertos-kernel_MK28FA15)
+if(${MCUX_DEVICE} STREQUAL "88MW320")
+ include(middleware_freertos-kernel_88MW320)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK64F12")
- include(middleware_freertos-kernel_MK64F12)
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
+ include(middleware_freertos-kernel_K32L3A60_cm0plus)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
- include(middleware_freertos-kernel_MK66F18)
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+ include(middleware_freertos-kernel_K32L3A60_cm4)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54628")
include(middleware_freertos-kernel_LPC54628)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
- include(middleware_freertos-kernel_MIMXRT1021)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
- include(middleware_freertos-kernel_MIMXRT1062)
-endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018")
include(middleware_freertos-kernel_LPC54S018)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
- include(middleware_freertos-kernel_K32L3A60_cm0plus)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
- include(middleware_freertos-kernel_K32L3A60_cm4)
-endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
include(middleware_freertos-kernel_LPC54S018M)
endif()
+if(${MCUX_DEVICE} STREQUAL "LPC55S28")
+ include(middleware_freertos-kernel_LPC55S28)
+endif()
if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
include(middleware_freertos-kernel_LPC55S69_cm33_core0)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
+ include(middleware_freertos-kernel_MIMXRT1021)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
include(middleware_freertos-kernel_MIMXRT1024)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S28")
- include(middleware_freertos-kernel_LPC55S28)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(middleware_freertos-kernel_MIMXRT1052)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
+ include(middleware_freertos-kernel_MIMXRT1062)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(middleware_freertos-kernel_MIMXRT1064)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
include(middleware_freertos-kernel_MIMXRT685S_cm33)
endif()
+if(${MCUX_DEVICE} STREQUAL "MK28FA15")
+ include(middleware_freertos-kernel_MK28FA15)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MK64F12")
+ include(middleware_freertos-kernel_MK64F12)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MK66F18")
+ include(middleware_freertos-kernel_MK66F18)
+endif()
include(component_lists)
diff --git a/components/osa/fsl_os_abstraction.h b/components/osa/fsl_os_abstraction.h
index 805a3bbf8..ecc4390f6 100644
--- a/components/osa/fsl_os_abstraction.h
+++ b/components/osa/fsl_os_abstraction.h
@@ -792,17 +792,6 @@ osa_status_t OSA_MsgQPut(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage
*/
osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage, uint32_t millisec);
-/*!
- * @brief Get the available message
- *
- * This function is used to get the available message.
- *
- * @param msgqHandle Message Queue handler.
- *
- * @return Available message count
- */
-int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle);
-
/*!
* @brief Destroys a previously created queue.
*
diff --git a/components/osa/fsl_os_abstraction_bm.c b/components/osa/fsl_os_abstraction_bm.c
index bac5ec50d..58bf72401 100644
--- a/components/osa/fsl_os_abstraction_bm.c
+++ b/components/osa/fsl_os_abstraction_bm.c
@@ -1157,21 +1157,6 @@ osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage
return status;
}
-/*FUNCTION**********************************************************************
- *
- * Function Name : OSA_MsgQAvailableMsgs
- * Description : This function is used to get the available message.
- * Return : Available message count
- *
- *END**************************************************************************/
-int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle)
-{
- assert(msgqHandle);
- msg_queue_t *pQueue = (msg_queue_t *)msgqHandle;
-
- return (int)pQueue->number;
-}
-
/*FUNCTION**********************************************************************
*
* Function Name : OSA_EXT_MsgQDestroy
diff --git a/components/osa/fsl_os_abstraction_config.h b/components/osa/fsl_os_abstraction_config.h
index 85aa37b98..03798df93 100644
--- a/components/osa/fsl_os_abstraction_config.h
+++ b/components/osa/fsl_os_abstraction_config.h
@@ -33,8 +33,4 @@
#define FSL_OSA_TASK_ENABLE 1U
#endif /* OSA_USED */
-#ifndef FSL_OSA_MAIN_FUNC_ENABLE
-#define FSL_OSA_MAIN_FUNC_ENABLE 1U
-#endif
-
#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */
diff --git a/components/osa/fsl_os_abstraction_free_rtos.c b/components/osa/fsl_os_abstraction_free_rtos.c
index fa5ece499..98ab17473 100644
--- a/components/osa/fsl_os_abstraction_free_rtos.c
+++ b/components/osa/fsl_os_abstraction_free_rtos.c
@@ -96,7 +96,7 @@ void startup_task(void *argument);
* Public memory declarations
*************************************************************************************
********************************************************************************** */
-const uint8_t gUseRtos_c = USE_RTOS; /* USE_RTOS = 0 for BareMetal and 1 for OS */
+const uint8_t gUseRtos_c = USE_RTOS; // USE_RTOS = 0 for BareMetal and 1 for OS
static osa_state_t s_osaState = {0};
/*! *********************************************************************************
@@ -266,18 +266,11 @@ osa_status_t OSA_TaskSetPriority(osa_task_handle_t taskHandle, osa_task_priority
#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
osa_status_t OSA_TaskCreate(osa_task_handle_t taskHandle, const osa_task_def_t *thread_def, osa_task_param_t task_param)
{
- static uint8_t s_osaTaskListInitialized = 0;
assert(sizeof(osa_freertos_task_t) == OSA_TASK_HANDLE_SIZE);
assert(taskHandle);
TaskHandle_t pxCreatedTask;
osa_freertos_task_t *ptask = (osa_freertos_task_t *)taskHandle;
- if (0u == s_osaTaskListInitialized)
- {
- s_osaTaskListInitialized = 1u;
- LIST_Init((&s_osaState.taskList), 0);
- }
-
if (xTaskCreate((TaskFunction_t)thread_def->pthread, /* pointer to the task */
(char const *)thread_def->tname, /* task name for kernel awareness debugging */
(configSTACK_DEPTH_TYPE)thread_def->stacksize / sizeof(portSTACK_TYPE), /* task stack size */
@@ -898,21 +891,6 @@ osa_status_t OSA_MsgQGet(osa_msgq_handle_t msgqHandle, osa_msg_handle_t pMessage
return osaStatus;
}
-/*FUNCTION**********************************************************************
- *
- * Function Name : OSA_MsgQAvailableMsgs
- * Description : This function is used to get the available message.
- * Return : Available message count
- *
- *END**************************************************************************/
-int OSA_MsgQAvailableMsgs(osa_msgq_handle_t msgqHandle)
-{
- QueueHandle_t handler;
- assert(NULL != msgqHandle);
- handler = (QueueHandle_t)(void *)(uint32_t *)(*(uint32_t *)msgqHandle);
- return (int)uxQueueMessagesWaiting((QueueHandle_t)handler);
-}
-
/*FUNCTION**********************************************************************
*
* Function Name : OSA_MsgQDestroy
@@ -1037,13 +1015,13 @@ void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void))
*************************************************************************************
********************************************************************************** */
#if (defined(FSL_OSA_TASK_ENABLE) && (FSL_OSA_TASK_ENABLE > 0U))
-#if (defined(FSL_OSA_MAIN_FUNC_ENABLE) && (FSL_OSA_MAIN_FUNC_ENABLE > 0U))
+
static OSA_TASK_DEFINE(startup_task, gMainThreadPriority_c, 1, gMainThreadStackSize_c, 0);
-__WEAK_FUNC int main(void)
+int main(void)
{
extern void BOARD_InitHardware(void);
-
+ LIST_Init((&s_osaState.taskList), 0);
/* Initialize MCU clock */
BOARD_InitHardware();
@@ -1054,7 +1032,4 @@ __WEAK_FUNC int main(void)
vTaskStartScheduler();
return 0;
}
-
-#endif
-
#endif /* FSL_OSA_TASK_ENABLE */
diff --git a/components/osa/fsl_os_abstraction_free_rtos.h b/components/osa/fsl_os_abstraction_free_rtos.h
index 00b4b6011..8cb02b692 100644
--- a/components/osa/fsl_os_abstraction_free_rtos.h
+++ b/components/osa/fsl_os_abstraction_free_rtos.h
@@ -14,7 +14,7 @@
/**
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
*/
-/* http://supp.iar.com/Support/?note=24725 */
+// http://supp.iar.com/Support/?note=24725
#define MISRAC_DISABLE \
_Pragma( \
@@ -129,4 +129,4 @@ extern void DefaultISR(void);
/*! @}*/
/*! @}*/
-#endif /* __FSL_OS_ABSTRACTION_FREERTOS_H__ */
+#endif // __FSL_OS_ABSTRACTION_FREERTOS_H__
diff --git a/components/serial_manager/component_serial_manager_uart.cmake b/components/serial_manager/component_serial_manager_uart.cmake
index 1ae025eb3..c7975034c 100644
--- a/components/serial_manager/component_serial_manager_uart.cmake
+++ b/components/serial_manager/component_serial_manager_uart.cmake
@@ -11,127 +11,130 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+if(${MCUX_DEVICE} STREQUAL "88MW320")
+ include(component_mw_uart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK28FA15")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
include(component_lpuart_adapter)
endif()
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+ include(component_lpuart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+ include(component_usart_adapter)
+endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm0plus")
include(component_usart_adapter)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4")
include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
- include(component_iuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC54628")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
- include(component_iuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC54S018")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC55S16")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK64F12")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC55S28")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1")
+ include(component_usart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
include(component_lpuart_adapter)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
+ include(component_iuart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
+ include(component_iuart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
+ include(component_iuart_adapter)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
include(component_lpuart_adapter)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
- include(component_uart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
- include(component_uart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54628")
- include(component_usart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
+ include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE06Z4")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+ include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
include(component_lpuart_adapter)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE02Z4")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+ include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(component_lpuart_adapter)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
- include(component_iuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54S018")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MK22F51212")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+if(${MCUX_DEVICE} STREQUAL "MK28FA15")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
- include(component_usart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+if(${MCUX_DEVICE} STREQUAL "MK64F12")
include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
- include(component_usart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MK66F18")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKE02Z4")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKE06Z4")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S28")
- include(component_usart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
+ include(component_uart_adapter)
endif()
diff --git a/components/serial_manager/fsl_component_serial_manager.c b/components/serial_manager/fsl_component_serial_manager.c
index 5d5bd4026..c7f327196 100644
--- a/components/serial_manager/fsl_component_serial_manager.c
+++ b/components/serial_manager/fsl_component_serial_manager.c
@@ -616,7 +616,7 @@ static void SerialManager_Task(void *param)
ringBufferLength =
handle->ringBuffer.ringHead + handle->ringBuffer.ringBufferSize - handle->ringBuffer.ringTail;
ringBufferLength = ringBufferLength % handle->ringBuffer.ringBufferSize;
- /* Notify there are data in ringbuffer */
+ // Notify there are data in ringbuffer
if (0U != ringBufferLength)
{
msg.buffer = NULL;
@@ -948,7 +948,7 @@ static serial_manager_status_t SerialManager_Read(serial_read_handle_t readHandl
assert(handle);
#if (defined(SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE) && (SERIAL_MANAGER_NON_BLOCKING_DUAL_MODE > 0U))
if (handle->handleType == kSerialManager_Blocking)
- /* if ((handle->handleType == kSerialManager_Blocking) || (kSerialManager_TransmissionBlocking == mode)) */
+ // if ((handle->handleType == kSerialManager_Blocking) || (kSerialManager_TransmissionBlocking == mode))
{
return SerialManager_StartReading(handle, serialReadHandle, buffer, length);
}
diff --git a/components/serial_manager/fsl_component_serial_manager.h b/components/serial_manager/fsl_component_serial_manager.h
index 914ddd931..448a63f9a 100644
--- a/components/serial_manager/fsl_component_serial_manager.h
+++ b/components/serial_manager/fsl_component_serial_manager.h
@@ -12,7 +12,7 @@
#include "fsl_common.h"
/*!
- * @addtogroup Serial_Manager
+ * @addtogroup serialmanager
* @{
*/
diff --git a/components/serial_manager/fsl_component_serial_port_swo.h b/components/serial_manager/fsl_component_serial_port_swo.h
index f819643b4..b46104021 100644
--- a/components/serial_manager/fsl_component_serial_port_swo.h
+++ b/components/serial_manager/fsl_component_serial_port_swo.h
@@ -9,7 +9,8 @@
#define __SERIAL_PORT_SWO_H__
/*!
- * @addtogroup serial_port_swo
+ * @addtogroup serial_port_swo Serial Port SWO
+ * @ingroup serialmanager
* @{
*/
diff --git a/components/serial_manager/fsl_component_serial_port_uart.h b/components/serial_manager/fsl_component_serial_port_uart.h
index 0b8e35e84..bf1e627cf 100644
--- a/components/serial_manager/fsl_component_serial_port_uart.h
+++ b/components/serial_manager/fsl_component_serial_port_uart.h
@@ -12,7 +12,8 @@
#include "fsl_adapter_uart.h"
/*!
- * @addtogroup serial_port_uart
+ * @addtogroup serial_port_uart Serial Port Uart
+ * @ingroup serialmanager
* @{
*/
@@ -71,10 +72,6 @@ typedef struct _serial_port_uart_config
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
serial_port_uart_block_mode_t mode; /*!< serial port uart block mode */
#endif /* SERIAL_MANAGER_NON_BLOCKING_MODE */
-#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
- uint8_t txFifoWatermark;
- uint8_t rxFifoWatermark;
-#endif
} serial_port_uart_config_t;
/*! @} */
#endif /* __SERIAL_PORT_UART_H__ */
diff --git a/components/srtm/driver_srtm.cmake b/components/srtm/driver_srtm.cmake
index 7159c6afe..a8d25254b 100644
--- a/components/srtm/driver_srtm.cmake
+++ b/components/srtm/driver_srtm.cmake
@@ -14,7 +14,6 @@ target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
${CMAKE_CURRENT_LIST_DIR}/include
${CMAKE_CURRENT_LIST_DIR}/srtm
- ${CMAKE_CURRENT_LIST_DIR}/port
)
diff --git a/components/uart/component_mw_uart_adapter.cmake b/components/uart/component_mw_uart_adapter.cmake
new file mode 100644
index 000000000..a51b53361
--- /dev/null
+++ b/components/uart/component_mw_uart_adapter.cmake
@@ -0,0 +1,14 @@
+#Description: uart_adapter; user_visible: True
+include_guard(GLOBAL)
+message("component_mw_uart_adapter component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_adapter_mwuart.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_mw_uart)
diff --git a/components/uart/fsl_adapter_mwuart.c b/components/uart/fsl_adapter_mwuart.c
new file mode 100644
index 000000000..838ec1f89
--- /dev/null
+++ b/components/uart/fsl_adapter_mwuart.c
@@ -0,0 +1,672 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_uart.h"
+
+#include "fsl_adapter_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_receive_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_send_state
+{
+ volatile uint8_t *buffer;
+ volatile uint32_t bufferLength;
+ volatile uint32_t bufferSofar;
+} hal_uart_send_state_t;
+#endif
+/*! @brief uart state structure. */
+typedef struct _hal_uart_state
+{
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ hal_uart_transfer_callback_t callback;
+ void *callbackParam;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ uart_handle_t hardwareHandle;
+#endif
+ hal_uart_receive_state_t rx;
+ hal_uart_send_state_t tx;
+#endif
+ uint8_t instance;
+} hal_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static UART_Type *const s_UartAdapterBase[] = UART_BASE_PTRS;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+/* Array of UART IRQ number. */
+static const IRQn_Type s_UartIRQ[] = UART_IRQS;
+
+static hal_uart_state_t *s_UartState[sizeof(s_UartAdapterBase) / sizeof(UART_Type *)];
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ hal_uart_status_t uartStatus = kStatus_HAL_UartError;
+ switch (status)
+ {
+ case kStatus_Success:
+ uartStatus = kStatus_HAL_UartSuccess;
+ break;
+ case kStatus_UART_TxBusy:
+ uartStatus = kStatus_HAL_UartTxBusy;
+ break;
+ case kStatus_UART_RxBusy:
+ uartStatus = kStatus_HAL_UartRxBusy;
+ break;
+ case kStatus_UART_TxIdle:
+ uartStatus = kStatus_HAL_UartTxIdle;
+ break;
+ case kStatus_UART_RxIdle:
+ uartStatus = kStatus_HAL_UartRxIdle;
+ break;
+ case kStatus_UART_BaudrateNotSupport:
+ uartStatus = kStatus_HAL_UartBaudrateNotSupport;
+ break;
+ case kStatus_UART_RxFifoError:
+ case kStatus_UART_FramingError:
+ case kStatus_UART_ParityError:
+ uartStatus = kStatus_HAL_UartProtocolError;
+ break;
+ default:
+ /* This comments for MISRA C-2012 Rule 16.4 */
+ break;
+ }
+ return uartStatus;
+}
+#else
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+ if (kStatus_Success == status)
+ {
+ return kStatus_HAL_UartSuccess;
+ }
+ else
+ {
+ return kStatus_HAL_UartError;
+ }
+}
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static void HAL_UartCallback(UART_Type *base, uart_handle_t *handle, status_t status, void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+ hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+ assert(callbackParam);
+
+ uartHandle = (hal_uart_state_t *)callbackParam;
+
+ if (kStatus_HAL_UartProtocolError == uartStatus)
+ {
+ if (0U != uartHandle->hardwareHandle.rxDataSize)
+ {
+ uartStatus = kStatus_HAL_UartError;
+ }
+ }
+
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
+ }
+}
+
+#else
+
+static void HAL_UartInterruptHandle(uint8_t instance)
+{
+ hal_uart_state_t *uartHandle = s_UartState[instance];
+ uint16_t status;
+
+ if (NULL == uartHandle)
+ {
+ return;
+ }
+
+ status = UART_GetStatusFlags(s_UartAdapterBase[instance]);
+
+ /* Receive data register full */
+ if ((0U != ((uint16_t)kUART_RxDataReadyInterruptFlag & status)) &&
+ (0U != (UART_GetEnabledInterrupts(s_UartAdapterBase[instance]) & (uint8_t)kUART_RxDataReadyInterruptEnable)))
+ {
+ if (NULL != uartHandle->rx.buffer)
+ {
+ uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = UART_ReadByte(s_UartAdapterBase[instance]);
+ if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
+ {
+ UART_DisableInterrupts(s_UartAdapterBase[instance], (uint8_t)kUART_RxDataReadyInterruptEnable |
+ (uint8_t)kUART_RxStatusInterruptEnable);
+ uartHandle->rx.buffer = NULL;
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+
+ /* Send data register empty and the interrupt is enabled. */
+ if ((0U != ((uint16_t)kUART_TxDataRequestInterruptFlag & status)) &&
+ (0U != (UART_GetEnabledInterrupts(s_UartAdapterBase[instance]) & (uint8_t)kUART_TxDataRequestInterruptEnable)))
+ {
+ if (NULL != uartHandle->tx.buffer)
+ {
+ UART_WriteByte(s_UartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
+ if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
+ {
+ UART_DisableInterrupts(s_UartAdapterBase[uartHandle->instance],
+ (uint8_t)kUART_TxDataRequestInterruptEnable);
+ uartHandle->tx.buffer = NULL;
+ if (NULL != uartHandle->callback)
+ {
+ uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
+ }
+ }
+ }
+ }
+}
+#endif
+
+#endif
+
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, const hal_uart_config_t *config)
+{
+ hal_uart_state_t *uartHandle;
+ uart_config_t uartConfig;
+ status_t status;
+ assert(handle);
+ assert(config);
+ assert(config->instance < (sizeof(s_UartAdapterBase) / sizeof(UART_Type *)));
+ assert(s_UartAdapterBase[config->instance]);
+
+ assert(HAL_UART_HANDLE_SIZE >= sizeof(hal_uart_state_t));
+
+ UART_GetDefaultConfig(&uartConfig);
+ uartConfig.baudRate_Bps = config->baudRate_Bps;
+
+ if (kHAL_UartParityEven == config->parityMode)
+ {
+ uartConfig.parityMode = kUART_ParityEven;
+ }
+ else if (kHAL_UartParityOdd == config->parityMode)
+ {
+ uartConfig.parityMode = kUART_ParityOdd;
+ }
+ else
+ {
+ uartConfig.parityMode = kUART_ParityDisabled;
+ }
+#if defined(FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT
+ if (kHAL_UartTwoStopBit == config->stopBitCount)
+ {
+ uartConfig.stopBitCount = kUART_Stopbits2;
+ }
+ else
+ {
+ uartConfig.stopBitCount = kUART_Stopbits1;
+ }
+#endif
+
+ uartConfig.enable = (bool)(config->enableRx || config->enableTx);
+ uartConfig.enableRxRTS = (bool)config->enableRxRTS;
+ uartConfig.enableTxCTS = (bool)config->enableTxCTS;
+ uartConfig.fifoConfig.txFifoWatermark = kUART_TxfifoHalfEmpty;
+ uartConfig.fifoConfig.rxFifoWatermark = kUART_RxfifoByte1;
+
+ status = UART_Init(s_UartAdapterBase[config->instance], &uartConfig, config->srcClock_Hz);
+
+ if (kStatus_Success != status)
+ {
+ return HAL_UartGetStatus(status);
+ }
+
+ uartHandle = (hal_uart_state_t *)handle;
+ uartHandle->instance = config->instance;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ UART_TransferCreateHandle(s_UartAdapterBase[config->instance], &uartHandle->hardwareHandle,
+ (uart_transfer_callback_t)HAL_UartCallback, handle);
+#else
+ s_UartState[uartHandle->instance] = uartHandle;
+ /* Enable interrupt in NVIC. */
+ NVIC_SetPriority((IRQn_Type)s_UartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
+ (void)EnableIRQ(s_UartIRQ[config->instance]);
+#endif
+
+#endif
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ UART_Deinit(s_UartAdapterBase[uartHandle->instance]);
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+ s_UartState[uartHandle->instance] = NULL;
+#endif
+
+#endif
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (NULL != uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+#endif
+
+ status = UART_ReadBlocking(s_UartAdapterBase[uartHandle->instance], data, length);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+ if (NULL != uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+#endif
+
+ (void)UART_WriteBlocking(s_UartAdapterBase[uartHandle->instance], data, length);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)
+{
+ assert(handle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)
+{
+ assert(handle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = UART_TransferReceiveNonBlocking(s_UartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (uart_transfer_t *)(void *)transfer, NULL);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(transfer);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = UART_TransferSendNonBlocking(s_UartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+ (uart_transfer_t *)(void *)transfer);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = UART_TransferGetReceiveCount(s_UartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
+{
+ hal_uart_state_t *uartHandle;
+ status_t status;
+ assert(handle);
+ assert(count);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ status = UART_TransferGetSendCount(s_UartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+ return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ UART_TransferAbortReceive(s_UartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ UART_TransferAbortSend(s_UartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#else
+
+/* None transactional API with non-blocking mode. */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+ hal_uart_transfer_callback_t callback,
+ void *callbackParam)
+{
+ hal_uart_state_t *uartHandle;
+
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ uartHandle->callbackParam = callbackParam;
+ uartHandle->callback = callback;
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ return kStatus_HAL_UartRxBusy;
+ }
+
+ uartHandle->rx.bufferLength = length;
+ uartHandle->rx.bufferSofar = 0;
+ uartHandle->rx.buffer = data;
+ UART_EnableInterrupts(s_UartAdapterBase[uartHandle->instance],
+ (uint8_t)kUART_RxDataReadyInterruptEnable | (uint8_t)kUART_RxStatusInterruptEnable);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(data);
+ assert(length);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ return kStatus_HAL_UartTxBusy;
+ }
+ uartHandle->tx.bufferLength = length;
+ uartHandle->tx.bufferSofar = 0;
+ uartHandle->tx.buffer = (volatile uint8_t *)data;
+ UART_EnableInterrupts(s_UartAdapterBase[uartHandle->instance], (uint8_t)kUART_TxDataRequestInterruptEnable);
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(reCount);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ *reCount = uartHandle->rx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(seCount);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ *seCount = uartHandle->tx.bufferSofar;
+ return kStatus_HAL_UartSuccess;
+ }
+ return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->rx.buffer)
+ {
+ UART_DisableInterrupts(s_UartAdapterBase[uartHandle->instance],
+ (uint8_t)kUART_RxDataReadyInterruptEnable | (uint8_t)kUART_RxStatusInterruptEnable);
+ uartHandle->rx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+ if (NULL != uartHandle->tx.buffer)
+ {
+ UART_DisableInterrupts(s_UartAdapterBase[uartHandle->instance], (uint8_t)kUART_TxDataRequestInterruptEnable);
+ uartHandle->tx.buffer = NULL;
+ }
+
+ return kStatus_HAL_UartSuccess;
+}
+
+#endif
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UartIRQ[uartHandle->instance]);
+#endif
+ UART_TransferHandleIRQ(s_UartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UartIRQ[uartHandle->instance]);
+#endif
+}
+
+#else
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+ hal_uart_state_t *uartHandle;
+ assert(handle);
+ assert(!HAL_UART_TRANSFER_MODE);
+
+ uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+ DisableIRQ(s_UartIRQ[uartHandle->instance]);
+#endif
+ HAL_UartInterruptHandle(uartHandle->instance);
+#if 0
+ NVIC_SetPriority((IRQn_Type)s_UartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+ EnableIRQ(s_UartIRQ[uartHandle->instance]);
+#endif
+}
+
+#if defined(UART0)
+void UART0_IRQHandler(void);
+void UART0_IRQHandler(void)
+{
+ HAL_UartInterruptHandle(0);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(UART1)
+void UART1_IRQHandler(void);
+void UART1_IRQHandler(void)
+{
+ HAL_UartInterruptHandle(1);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(UART2)
+void UART2_IRQHandler(void);
+void UART2_IRQHandler(void)
+{
+ HAL_UartInterruptHandle(2);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+#endif
+#endif
diff --git a/components/uart/fsl_adapter_uart.h b/components/uart/fsl_adapter_uart.h
index f97c00e9b..a9b2e155f 100644
--- a/components/uart/fsl_adapter_uart.h
+++ b/components/uart/fsl_adapter_uart.h
@@ -58,10 +58,6 @@
#define HAL_UART_ADAPTER_LOWPOWER (0U)
#endif /* HAL_UART_ADAPTER_LOWPOWER */
-#ifndef HAL_UART_ADAPTER_FIFO
-#define HAL_UART_ADAPTER_FIFO (0U)
-#endif /* HAL_UART_ADAPTER_FIFO */
-
/*! @brief Definition of uart adapter handle size. */
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
#define HAL_UART_HANDLE_SIZE (92U + HAL_UART_ADAPTER_LOWPOWER * 16U)
@@ -153,10 +149,6 @@ typedef struct _hal_uart_config
#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
hal_uart_block_mode_t mode; /*!< Uart block mode */
#endif /* UART_ADAPTER_NON_BLOCKING_MODE */
-#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
- uint8_t txFifoWatermark;
- uint8_t rxFifoWatermark;
-#endif
} hal_uart_config_t;
/*! @brief UART transfer callback function. */
diff --git a/devices/88MW320/88MW320.h b/devices/88MW320/88MW320.h
new file mode 100644
index 000000000..0447b9777
--- /dev/null
+++ b/devices/88MW320/88MW320.h
@@ -0,0 +1,19873 @@
+/*
+** ###################################################################
+** Processor: 88MW320_A0_NAPC
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: 88MW320-88MW322, Rev.3, July 2020
+** Version: rev. 1.0, 2020-09-07
+** Build: b201223
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for 88MW320
+**
+** Copyright 1997-2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2020-09-07)
+** Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file 88MW320.h
+ * @version 1.0
+ * @date 2020-09-07
+ * @brief CMSIS Peripheral Access Layer for 88MW320
+ *
+ * CMSIS Peripheral Access Layer for 88MW320
+ */
+
+#ifndef _88MW320_H_
+#define _88MW320_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 79 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ EXTPIN0_IRQn = 0, /**< Ext. Pin 0 */
+ EXTPIN1_IRQn = 1, /**< Ext. Pin 1 */
+ RTC_IRQn = 2, /**< RTC INT */
+ CRC_IRQn = 3, /**< CRC INT */
+ AES_IRQn = 4, /**< AES INT */
+ I2C0_IRQn = 5, /**< I2C0 INT */
+ I2C1_IRQn = 6, /**< I2C1 INT */
+ Reserved23_IRQn = 7, /**< Reserved interrupt */
+ DMAC_IRQn = 8, /**< DMAC INT */
+ GPIO_IRQn = 9, /**< GPIO INT */
+ SSP0_IRQn = 10, /**< SSP0 INT */
+ SSP1_IRQn = 11, /**< SSP1 INT */
+ SSP2_IRQn = 12, /**< SSP2 INT */
+ QSPI_IRQn = 13, /**< QSPI INT */
+ GPT0_IRQn = 14, /**< GPT0 INT */
+ GPT1_IRQn = 15, /**< GPT1 INT */
+ GPT2_IRQn = 16, /**< GPT2 INT */
+ GPT3_IRQn = 17, /**< GPT3 INT */
+ UART0_IRQn = 18, /**< UART0 INT */
+ UART1_IRQn = 19, /**< UART1 INT */
+ UART2_IRQn = 20, /**< UART2 INT */
+ Reserved37_IRQn = 21, /**< Reserved interrupt */
+ WDT_IRQn = 22, /**< WDT INT */
+ Reserved39_IRQn = 23, /**< Reserved interrupt */
+ ADC0_IRQn = 24, /**< ADC0 INT */
+ DAC_IRQn = 25, /**< DAC INT */
+ ACOMP_WAKEUP_IRQn = 26, /**< ACOMP Wake-up INT */
+ ACOMP_IRQn = 27, /**< ACOMP INT */
+ SDIO_IRQn = 28, /**< SDIO INT */
+ USB_IRQn = 29, /**< USB INT */
+ Reserved46_IRQn = 30, /**< Reserved interrupt */
+ PLL_IRQn = 31, /**< PLL INT */
+ Reserved48_IRQn = 32, /**< Reserved interrupt */
+ RC32M_IRQn = 33, /**< RC32M INT FUNC */
+ GPIO_0_1_IRQn = 34, /**< External Pin 0 selected by PMU.EXT_SEL_REG */
+ GPIO_2_3_IRQn = 35, /**< External Pin 1 selected by PMU.EXT_SEL_REG */
+ GPIO_4_5_IRQn = 36, /**< External Pin 2 selected by PMU.EXT_SEL_REG */
+ GPIO_6_7_IRQn = 37, /**< External Pin 3 selected by PMU.EXT_SEL_REG */
+ GPIO_8_9_IRQn = 38, /**< External Pin 4 selected by PMU.EXT_SEL_REG */
+ GPIO_10_11_IRQn = 39, /**< External Pin 5 selected by PMU.EXT_SEL_REG */
+ GPIO_12_13_IRQn = 40, /**< External Pin 6 selected by PMU.EXT_SEL_REG */
+ GPIO_14_15_IRQn = 41, /**< External Pin 7 selected by PMU.EXT_SEL_REG */
+ GPIO_16_17_IRQn = 42, /**< External Pin 8 selected by PMU.EXT_SEL_REG */
+ GPIO_18_19_IRQn = 43, /**< External Pin 9 selected by PMU.EXT_SEL_REG */
+ GPIO_20_21_IRQn = 44, /**< External Pin 10 selected by PMU.EXT_SEL_REG */
+ GPIO_22_23_IRQn = 45, /**< External Pin 11 selected by PMU.EXT_SEL_REG */
+ GPIO_24_25_IRQn = 46, /**< External Pin 12 selected by PMU.EXT_SEL_REG */
+ GPIO_26_27_IRQn = 47, /**< External Pin 13 selected by PMU.EXT_SEL_REG */
+ GPIO_28_29_IRQn = 48, /**< External Pin 14 selected by PMU.EXT_SEL_REG */
+ GPIO_30_31_IRQn = 49, /**< External Pin 15 selected by PMU.EXT_SEL_REG */
+ GPIO_32_33_IRQn = 50, /**< External Pin 16 selected by PMU.EXT_SEL_REG */
+ GPIO_34_35_IRQn = 51, /**< External Pin 17 selected by PMU.EXT_SEL_REG */
+ GPIO_36_37_IRQn = 52, /**< External Pin 18 selected by PMU.EXT_SEL_REG */
+ GPIO_38_39_IRQn = 53, /**< External Pin 19 selected by PMU.EXT_SEL_REG */
+ GPIO_40_41_IRQn = 54, /**< External Pin 20 selected by PMU.EXT_SEL_REG */
+ GPIO_42_43_IRQn = 55, /**< External Pin 21 selected by PMU.EXT_SEL_REG */
+ GPIO_44_45_IRQn = 56, /**< External Pin 22 selected by PMU.EXT_SEL_REG */
+ GPIO_46_47_IRQn = 57, /**< External Pin 23 selected by PMU.EXT_SEL_REG */
+ GPIO_48_49_IRQn = 58, /**< External Pin 24 selected by PMU.EXT_SEL_REG */
+ Reserved75_IRQn = 59, /**< Reserved interrupt */
+ PMU_IRQn = 60, /**< ULP COMP */
+ BRNOUT_IRQn = 61, /**< Brnout INT */
+ WIFIWKUP_IRQn = 62 /**< WiFi Wakeup INT */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_88MW320.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup dmac_peripheral_number
+ * @{ */
+
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+
+/*!
+ * @brief Enumeration for the DMAC peripheral request number
+ *
+ * Defines the enumeration for the DMAC peripheral request number collections.
+ */
+typedef enum _dmac_peripheral_number
+{
+ kDMAC_PeriphNum_None = 0xFFU, /**< Invalid peripheral number */
+ kDMAC_PeriphNum_GPT0_0 = 0x00U, /**< PER0 GPT0 CH0 mapping */
+ kDMAC_PeriphNum_GPT0_1 = 0x01U, /**< PER1 GPT0 CH1 mapping */
+ kDMAC_PeriphNum_GPT1_0 = 0x02U, /**< PER2 GPT1 CH0 mapping */
+ kDMAC_PeriphNum_GPT1_1 = 0x03U, /**< PER3 GPT1 CH1 mapping */
+ kDMAC_PeriphNum_I2C0_Rx = 0x04U, /**< PER4 I2C0 RX mapping */
+ kDMAC_PeriphNum_I2C0_Tx = 0x05U, /**< PER5 I2C0 TX mapping */
+ kDMAC_PeriphNum_QSPI0_Rx = 0x06U, /**< PER6 QSPI0 RX mapping */
+ kDMAC_PeriphNum_QSPI0_Tx = 0x07U, /**< PER7 QSPI0 TX mapping */
+ kDMAC_PeriphNum_SSP0_Rx = 0x0AU, /**< PER10 SSP0 RX mapping */
+ kDMAC_PeriphNum_SSP0_Tx = 0x0BU, /**< PER11 SSP0 TX mapping */
+ kDMAC_PeriphNum_SSP1_Rx = 0x0CU, /**< PER12 SSP1 RX mapping */
+ kDMAC_PeriphNum_SSP1_Tx = 0x0DU, /**< PER13 SSP1 TX mapping */
+ kDMAC_PeriphNum_UART0_Rx = 0x0EU, /**< PER14 UART0 RX mapping */
+ kDMAC_PeriphNum_UART0_Tx = 0x0FU, /**< PER15 UART0 TX mapping */
+ kDMAC_PeriphNum_UART1_Rx = 0x10U, /**< PER16 UART1 RX mapping */
+ kDMAC_PeriphNum_UART1_Tx = 0x11U, /**< PER17 UART1 TX mapping */
+ kDMAC_PeriphNum_ADC0 = 0x18U, /**< PER24 ADC0 mapping */
+ kDMAC_PeriphNum_DAC0 = 0x1AU, /**< PER26 DAC0 mapping */
+ kDMAC_PeriphNum_DAC1 = 0x1BU, /**< PER27 DAC1 mapping */
+ kDMAC_PeriphNum_GPT2_0 = 0x20U, /**< PER32 GPT2 CH0 mapping */
+ kDMAC_PeriphNum_GPT2_1 = 0x21U, /**< PER33 GPT2 CH1 mapping */
+ kDMAC_PeriphNum_GPT3_0 = 0x22U, /**< PER34 GPT3 CH0 mapping */
+ kDMAC_PeriphNum_GPT3_1 = 0x23U, /**< PER35 GPT3 CH1 mapping */
+ kDMAC_PeriphNum_I2C1_Rx = 0x24U, /**< PER36 I2C1 RX mapping */
+ kDMAC_PeriphNum_I2C1_Tx = 0x25U, /**< PER37 I2C1 TX mapping */
+ kDMAC_PeriphNum_I2C2_Rx = 0x26U, /**< PER38 I2C2 RX mapping */
+ kDMAC_PeriphNum_I2C2_Tx = 0x27U, /**< PER39 I2C2 TX mapping */
+ kDMAC_PeriphNum_SSP2_Rx = 0x28U, /**< PER40 SSP2 RX mapping */
+ kDMAC_PeriphNum_SSP2_Tx = 0x29U, /**< PER41 SSP2 TX mapping */
+ kDMAC_PeriphNum_UART2_Rx = 0x2AU, /**< PER42 UART2 RX mapping */
+ kDMAC_PeriphNum_UART2_Tx = 0x2BU, /**< PER43 UART2 TX mapping */
+ kDMAC_PeriphNum_AES_CrcIn = 0x38U, /**< PER56 AES CRC IN mapping */
+ kDMAC_PeriphNum_AES_CrcOut = 0x39U, /**< PER57 AES CRC OUT mapping */
+} dmac_peripheral_number_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #else
+ #pragma push
+ #pragma anon_unions
+ #endif
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ACOMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer
+ * @{
+ */
+
+/** ACOMP - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL0; /**< ACOMP0 Control Register, offset: 0x0 */
+ __IO uint32_t CTRL1; /**< ACOMP1 Control Register, offset: 0x4 */
+ __I uint32_t STATUS0; /**< ACOMP0 Status Register, offset: 0x8 */
+ __I uint32_t STATUS1; /**< ACOMP1 Status Register, offset: 0xC */
+ __IO uint32_t ROUTE0; /**< ACOMP0 Route Register, offset: 0x10 */
+ __IO uint32_t ROUTE1; /**< ACOMP1 Route Register, offset: 0x14 */
+ __I uint32_t ISR0; /**< ACOMP0 Interrupt Status Register, offset: 0x18 */
+ __I uint32_t ISR1; /**< ACOMP1 Interrupt Status Register, offset: 0x1C */
+ __IO uint32_t IMR0; /**< ACOMP0 Interrupt Mask Register, offset: 0x20 */
+ __IO uint32_t IMR1; /**< ACOMP1 Interrupt Mask Register, offset: 0x24 */
+ __I uint32_t IRSR0; /**< ACOMP0 Interrupt Raw Status Register, offset: 0x28 */
+ __I uint32_t IRSR1; /**< ACOMP1 Interrupt Raw Status Register, offset: 0x2C */
+ __IO uint32_t ICR0; /**< ACOMP0 Interrupt Clear Register, offset: 0x30 */
+ __IO uint32_t ICR1; /**< ACOMP1 Interrupt Clear Register, offset: 0x34 */
+ __IO uint32_t RST0; /**< ACOMP0 Soft Reset Register, offset: 0x38 */
+ __IO uint32_t RST1; /**< ACOMP1 Soft Reset Register, offset: 0x3C */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t CLK; /**< Clock Register, offset: 0x48 */
+} ACOMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ACOMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACOMP_Register_Masks ACOMP Register Masks
+ * @{
+ */
+
+/*! @name CTRL0 - ACOMP0 Control Register */
+/*! @{ */
+#define ACOMP_CTRL0_EN_MASK (0x1U)
+#define ACOMP_CTRL0_EN_SHIFT (0U)
+/*! en - ACOMP0 enable
+ * 0b0..
+ * 0b1..
+ */
+#define ACOMP_CTRL0_EN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_EN_SHIFT)) & ACOMP_CTRL0_EN_MASK)
+#define ACOMP_CTRL0_GPIOINV_MASK (0x2U)
+#define ACOMP_CTRL0_GPIOINV_SHIFT (1U)
+/*! gpioinv - Enable/Disable inversion of ACOMP0 output to GPIO.
+ * 0b0..do not invert ACOMP0 output
+ * 0b1..invert ACOMP0 output
+ */
+#define ACOMP_CTRL0_GPIOINV(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_GPIOINV_SHIFT)) & ACOMP_CTRL0_GPIOINV_MASK)
+#define ACOMP_CTRL0_WARMTIME_MASK (0xCU)
+#define ACOMP_CTRL0_WARMTIME_SHIFT (2U)
+/*! warmtime - Set ACOMP0 Warm-Up time
+ * 0b00..1 us
+ * 0b01..2 us
+ * 0b10..4 us
+ * 0b11..8 us
+ */
+#define ACOMP_CTRL0_WARMTIME(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_WARMTIME_SHIFT)) & ACOMP_CTRL0_WARMTIME_MASK)
+#define ACOMP_CTRL0_HYST_SELN_MASK (0x70U)
+#define ACOMP_CTRL0_HYST_SELN_SHIFT (4U)
+/*! hyst_seln - Select ACOMP0 negative hysteresis voltage level.
+ * 0b000..no hysteresis
+ * 0b001..-10 mV hysteresis
+ * 0b010..-20 mV hysteresis
+ * 0b011..-30 mV hysteresis
+ * 0b100..-40 mV hysteresis
+ * 0b101..-50 mV hysteresis
+ * 0b110..-60 mV hysteresis
+ * 0b111..-70 mV hysteresis
+ */
+#define ACOMP_CTRL0_HYST_SELN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_HYST_SELN_SHIFT)) & ACOMP_CTRL0_HYST_SELN_MASK)
+#define ACOMP_CTRL0_HYST_SELP_MASK (0x380U)
+#define ACOMP_CTRL0_HYST_SELP_SHIFT (7U)
+/*! hyst_selp - Select ACOMP0 positive hysteresis voltage level.
+ * 0b000..No hysteresis
+ * 0b001..+10 mV hysteresis
+ * 0b010..+20 mV hysteresis
+ * 0b011..+30 mV hysteresis
+ * 0b100..+40 mV hysteresis
+ * 0b101..+50 mV hysteresis
+ * 0b110..+60 mV hysteresis
+ * 0b111..+70 mV hysteresis
+ */
+#define ACOMP_CTRL0_HYST_SELP(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_HYST_SELP_SHIFT)) & ACOMP_CTRL0_HYST_SELP_MASK)
+#define ACOMP_CTRL0_BIAS_PROG_MASK (0xC00U)
+#define ACOMP_CTRL0_BIAS_PROG_SHIFT (10U)
+/*! bias_prog - ACOMP0 bias current control bits or response time control bits.
+ * 0b00..power mode1 (slow response mode)
+ * 0b01..power mode2 (medium response mode)
+ * 0b10..power mode3 (fast response mode)
+ * 0b11..Reserved
+ */
+#define ACOMP_CTRL0_BIAS_PROG(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_BIAS_PROG_SHIFT)) & ACOMP_CTRL0_BIAS_PROG_MASK)
+#define ACOMP_CTRL0_LEVEL_SEL_MASK (0x3F000U)
+#define ACOMP_CTRL0_LEVEL_SEL_SHIFT (12U)
+/*! level_sel - Scaling factor select bits for VIO reference level.
+ * 0b000000..Scaling factor=0.25
+ * 0b010000..Scaling factor= 0.5
+ * 0b100000..Scaling factor= 0.75
+ * 0b110000..Scaling factor= 1
+ */
+#define ACOMP_CTRL0_LEVEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_LEVEL_SEL_SHIFT)) & ACOMP_CTRL0_LEVEL_SEL_MASK)
+#define ACOMP_CTRL0_NEG_SEL_MASK (0x3C0000U)
+#define ACOMP_CTRL0_NEG_SEL_SHIFT (18U)
+/*! neg_sel - ACOMP0 negative input select bits.
+ * 0b0000..acomp_ch<0>
+ * 0b0001..acomp_ch<1>
+ * 0b0010..acomp_ch<2>
+ * 0b0011..acomp_ch<3>
+ * 0b0100..acomp_ch<4>
+ * 0b0101..acomp_ch<5>
+ * 0b0110..acomp_ch<6>
+ * 0b0111..acomp_ch<7>
+ * 0b1000..
+ * 0b1001..
+ * 0b1010..
+ * 0b1011..
+ * 0b1100..vio*scaling factor
+ * 0b1101..vio*scaling factor
+ * 0b1110..vio*scaling factor
+ * 0b1111..vio*scaling factor
+ */
+#define ACOMP_CTRL0_NEG_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_NEG_SEL_SHIFT)) & ACOMP_CTRL0_NEG_SEL_MASK)
+#define ACOMP_CTRL0_POS_SEL_MASK (0x3C00000U)
+#define ACOMP_CTRL0_POS_SEL_SHIFT (22U)
+/*! pos_sel - ACOMP0 positive input select bits.
+ * 0b0000..acomp_ch<0>
+ * 0b0001..acomp_ch<1>
+ * 0b0010..acomp_ch<2>
+ * 0b0011..acomp_ch<3>
+ * 0b0100..acomp_ch<4>
+ * 0b0101..acomp_ch<5>
+ * 0b0110..acomp_ch<6>
+ * 0b0111..acomp_ch<7>
+ * 0b1000..
+ * 0b1001..
+ */
+#define ACOMP_CTRL0_POS_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_POS_SEL_SHIFT)) & ACOMP_CTRL0_POS_SEL_MASK)
+#define ACOMP_CTRL0_MUXEN_MASK (0x4000000U)
+#define ACOMP_CTRL0_MUXEN_SHIFT (26U)
+/*! muxen - ACOMP0 input MUX enable bit.
+ * 0b0..disable input mux
+ * 0b1..enable input mux
+ */
+#define ACOMP_CTRL0_MUXEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_MUXEN_SHIFT)) & ACOMP_CTRL0_MUXEN_MASK)
+#define ACOMP_CTRL0_INACT_VAL_MASK (0x8000000U)
+#define ACOMP_CTRL0_INACT_VAL_SHIFT (27U)
+/*! inact_val - Set output value when ACOMP0 is inactive.
+ * 0b0..output 0 when ACOMP0 is inactive
+ * 0b1..output 1 when ACOMP0 is inactive
+ */
+#define ACOMP_CTRL0_INACT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_INACT_VAL_SHIFT)) & ACOMP_CTRL0_INACT_VAL_MASK)
+#define ACOMP_CTRL0_RIE_MASK (0x10000000U)
+#define ACOMP_CTRL0_RIE_SHIFT (28U)
+/*! rie - ACOMP0 enable/disable rising edge triggered edge pulse.
+ * 0b0..
+ * 0b1..
+ */
+#define ACOMP_CTRL0_RIE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_RIE_SHIFT)) & ACOMP_CTRL0_RIE_MASK)
+#define ACOMP_CTRL0_FIE_MASK (0x20000000U)
+#define ACOMP_CTRL0_FIE_SHIFT (29U)
+/*! fie - ACOMP0 enable/disable falling edge triggered edge pulse.
+ * 0b0..
+ * 0b1..
+ */
+#define ACOMP_CTRL0_FIE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_FIE_SHIFT)) & ACOMP_CTRL0_FIE_MASK)
+#define ACOMP_CTRL0_INT_ACT_HI_MASK (0x40000000U)
+#define ACOMP_CTRL0_INT_ACT_HI_SHIFT (30U)
+/*! int_act_hi - ACOMP0 interrupt active mode select.
+ * 0b0..Low level or falling edge triggered interrupt
+ * 0b1..High level or rising edge triggered interrupt
+ */
+#define ACOMP_CTRL0_INT_ACT_HI(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_INT_ACT_HI_SHIFT)) & ACOMP_CTRL0_INT_ACT_HI_MASK)
+#define ACOMP_CTRL0_EDGE_LEVL_SEL_MASK (0x80000000U)
+#define ACOMP_CTRL0_EDGE_LEVL_SEL_SHIFT (31U)
+/*! edge_levl_sel - ACOMP0 interrupt type select.
+ * 0b0..level triggered interrupt
+ * 0b1..edge triggered interrupt
+ */
+#define ACOMP_CTRL0_EDGE_LEVL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL0_EDGE_LEVL_SEL_SHIFT)) & ACOMP_CTRL0_EDGE_LEVL_SEL_MASK)
+/*! @} */
+
+/*! @name CTRL1 - ACOMP1 Control Register */
+/*! @{ */
+#define ACOMP_CTRL1_EN_MASK (0x1U)
+#define ACOMP_CTRL1_EN_SHIFT (0U)
+/*! en - ACOMP1 enable bit.
+ * 0b0..
+ * 0b1..
+ */
+#define ACOMP_CTRL1_EN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_EN_SHIFT)) & ACOMP_CTRL1_EN_MASK)
+#define ACOMP_CTRL1_GPIOINV_MASK (0x2U)
+#define ACOMP_CTRL1_GPIOINV_SHIFT (1U)
+/*! gpioinv - Enable/disable inversion of ACOMP1 output to GPIO.
+ * 0b0..do not invert ACOMP1 output
+ * 0b1..invert ACOMP1 output
+ */
+#define ACOMP_CTRL1_GPIOINV(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_GPIOINV_SHIFT)) & ACOMP_CTRL1_GPIOINV_MASK)
+#define ACOMP_CTRL1_WARMTIME_MASK (0xCU)
+#define ACOMP_CTRL1_WARMTIME_SHIFT (2U)
+/*! warmtime - Set ACOMP1 warm-up time.
+ * 0b00..1 us
+ * 0b01..2 us
+ * 0b10..4 us
+ * 0b11..8 us
+ */
+#define ACOMP_CTRL1_WARMTIME(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_WARMTIME_SHIFT)) & ACOMP_CTRL1_WARMTIME_MASK)
+#define ACOMP_CTRL1_HYST_SELN_MASK (0x70U)
+#define ACOMP_CTRL1_HYST_SELN_SHIFT (4U)
+/*! hyst_seln - Select ACOMP1 negative hysteresis voltage level.
+ * 0b000..No hysteresis
+ * 0b001..-10 mV hysteresis
+ * 0b010..-20 mV hysteresis
+ * 0b011..-30 mV hysteresis
+ * 0b100..-40 mV hysteresis
+ * 0b101..-50 mV hysteresis
+ * 0b110..-60 mV hysteresis
+ * 0b111..-70 mV hysteresis
+ */
+#define ACOMP_CTRL1_HYST_SELN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_HYST_SELN_SHIFT)) & ACOMP_CTRL1_HYST_SELN_MASK)
+#define ACOMP_CTRL1_HYST_SELP_MASK (0x380U)
+#define ACOMP_CTRL1_HYST_SELP_SHIFT (7U)
+/*! hyst_selp - Select ACOMP1 positive hysteresis voltage level.
+ * 0b000..No hysteresis
+ * 0b001..+10 mV hysteresis
+ * 0b010..+20 mV hysteresis
+ * 0b011..+30 mV hysteresis
+ * 0b100..+40 mV hysteresis
+ * 0b101..+50 mV hysteresis
+ * 0b110..+60 mV hysteresis
+ * 0b111..+70 mV hysteresis
+ */
+#define ACOMP_CTRL1_HYST_SELP(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_HYST_SELP_SHIFT)) & ACOMP_CTRL1_HYST_SELP_MASK)
+#define ACOMP_CTRL1_BIAS_PROG_MASK (0xC00U)
+#define ACOMP_CTRL1_BIAS_PROG_SHIFT (10U)
+/*! bias_prog - ACOMP1 bias current control bits Or response time control bits.
+ * 0b00..power mode1 (Slow response mode)
+ * 0b01..power mode2 (Medium response mode)
+ * 0b10..power mode3 (Fast response mode)
+ * 0b11..Reserved
+ */
+#define ACOMP_CTRL1_BIAS_PROG(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_BIAS_PROG_SHIFT)) & ACOMP_CTRL1_BIAS_PROG_MASK)
+#define ACOMP_CTRL1_LEVEL_SEL_MASK (0x3F000U)
+#define ACOMP_CTRL1_LEVEL_SEL_SHIFT (12U)
+/*! level_sel - Scaling factor select bits for vio reference level.
+ * 0b000000..Scaling factor=0.25
+ * 0b010000..Scaling factor= 0.5
+ * 0b100000..Scaling factor= 0.75
+ * 0b110000..Scaling factor= 1
+ */
+#define ACOMP_CTRL1_LEVEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_LEVEL_SEL_SHIFT)) & ACOMP_CTRL1_LEVEL_SEL_MASK)
+#define ACOMP_CTRL1_NEG_SEL_MASK (0x3C0000U)
+#define ACOMP_CTRL1_NEG_SEL_SHIFT (18U)
+/*! neg_sel - ACOMP1 negative input select
+ * 0b0000..acomp_ch<0>
+ * 0b0001..acomp_ch<1>
+ * 0b0010..acomp_ch<2>
+ * 0b0011..acomp_ch<3>
+ * 0b0100..acomp_ch<4>
+ * 0b0101..acomp_ch<5>
+ * 0b0110..acomp_ch<6>
+ * 0b0111..acomp_ch<7>
+ * 0b1000..
+ * 0b1001..
+ * 0b1010..
+ * 0b1011..
+ * 0b1100..vio*scaling factor
+ * 0b1101..vio*scaling factor
+ * 0b1110..vio*scaling factor
+ * 0b1111..vio*scaling factor
+ */
+#define ACOMP_CTRL1_NEG_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_NEG_SEL_SHIFT)) & ACOMP_CTRL1_NEG_SEL_MASK)
+#define ACOMP_CTRL1_POS_SEL_MASK (0x3C00000U)
+#define ACOMP_CTRL1_POS_SEL_SHIFT (22U)
+/*! pos_sel - ACOMP1 positive input select
+ * 0b0000..acomp_ch<0>
+ * 0b0001..acomp_ch<1>
+ * 0b0010..acomp_ch<2>
+ * 0b0011..acomp_ch<3>
+ * 0b0100..acomp_ch<4>
+ * 0b0101..acomp_ch<5>
+ * 0b0110..acomp_ch<6>
+ * 0b0111..acomp_ch<7>
+ * 0b1000..
+ * 0b1001..
+ */
+#define ACOMP_CTRL1_POS_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_POS_SEL_SHIFT)) & ACOMP_CTRL1_POS_SEL_MASK)
+#define ACOMP_CTRL1_MUXEN_MASK (0x4000000U)
+#define ACOMP_CTRL1_MUXEN_SHIFT (26U)
+/*! muxen - ACOMP1 input MUX enable
+ * 0b0..disable input mux
+ * 0b1..enable input mux
+ */
+#define ACOMP_CTRL1_MUXEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_MUXEN_SHIFT)) & ACOMP_CTRL1_MUXEN_MASK)
+#define ACOMP_CTRL1_INACT_VAL_MASK (0x8000000U)
+#define ACOMP_CTRL1_INACT_VAL_SHIFT (27U)
+/*! inact_val - Set output value when ACOMP1 is inactive.
+ * 0b0..output 0 when ACOMP1 is inactive
+ * 0b1..output 1 when ACOMP1 is inactive
+ */
+#define ACOMP_CTRL1_INACT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_INACT_VAL_SHIFT)) & ACOMP_CTRL1_INACT_VAL_MASK)
+#define ACOMP_CTRL1_RIE_MASK (0x10000000U)
+#define ACOMP_CTRL1_RIE_SHIFT (28U)
+/*! rie - ACOMP1 enable/disable rising edge triggered edge pulse.
+ * 0b0..
+ * 0b1..
+ */
+#define ACOMP_CTRL1_RIE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_RIE_SHIFT)) & ACOMP_CTRL1_RIE_MASK)
+#define ACOMP_CTRL1_FIE_MASK (0x20000000U)
+#define ACOMP_CTRL1_FIE_SHIFT (29U)
+/*! fie - ACOMP1 enable/disable falling edge triggered edge pulse.
+ * 0b0..
+ * 0b1..
+ */
+#define ACOMP_CTRL1_FIE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_FIE_SHIFT)) & ACOMP_CTRL1_FIE_MASK)
+#define ACOMP_CTRL1_INT_ACT_HI_MASK (0x40000000U)
+#define ACOMP_CTRL1_INT_ACT_HI_SHIFT (30U)
+/*! int_act_hi - ACOMP1 interrupt active mode select.
+ * 0b0..Low level or falling edge triggered interrupt
+ * 0b1..High level or rising edge triggered interrupt
+ */
+#define ACOMP_CTRL1_INT_ACT_HI(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_INT_ACT_HI_SHIFT)) & ACOMP_CTRL1_INT_ACT_HI_MASK)
+#define ACOMP_CTRL1_EDGE_LEVL_SEL_MASK (0x80000000U)
+#define ACOMP_CTRL1_EDGE_LEVL_SEL_SHIFT (31U)
+/*! edge_levl_sel - ACOMP1 interrupt type select.
+ * 0b0..level triggered interrupt
+ * 0b1..edge triggered interrupt
+ */
+#define ACOMP_CTRL1_EDGE_LEVL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL1_EDGE_LEVL_SEL_SHIFT)) & ACOMP_CTRL1_EDGE_LEVL_SEL_MASK)
+/*! @} */
+
+/*! @name STATUS0 - ACOMP0 Status Register */
+/*! @{ */
+#define ACOMP_STATUS0_ACT_MASK (0x1U)
+#define ACOMP_STATUS0_ACT_SHIFT (0U)
+/*! act - ACOMP0 active status.
+ * 0b0..ACOMP0 is inactive
+ * 0b1..ACOMP0 is active
+ */
+#define ACOMP_STATUS0_ACT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_STATUS0_ACT_SHIFT)) & ACOMP_STATUS0_ACT_MASK)
+#define ACOMP_STATUS0_OUT_MASK (0x2U)
+#define ACOMP_STATUS0_OUT_SHIFT (1U)
+/*! out - ACOMP0 comparison output value.
+ */
+#define ACOMP_STATUS0_OUT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_STATUS0_OUT_SHIFT)) & ACOMP_STATUS0_OUT_MASK)
+/*! @} */
+
+/*! @name STATUS1 - ACOMP1 Status Register */
+/*! @{ */
+#define ACOMP_STATUS1_ACT_MASK (0x1U)
+#define ACOMP_STATUS1_ACT_SHIFT (0U)
+/*! act - ACOMP1 active status.
+ * 0b0..ACOMP1 is inactive
+ * 0b1..ACOMP1 is active
+ */
+#define ACOMP_STATUS1_ACT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_STATUS1_ACT_SHIFT)) & ACOMP_STATUS1_ACT_MASK)
+#define ACOMP_STATUS1_OUT_MASK (0x2U)
+#define ACOMP_STATUS1_OUT_SHIFT (1U)
+/*! out - ACOMP1 comparison output value.
+ */
+#define ACOMP_STATUS1_OUT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_STATUS1_OUT_SHIFT)) & ACOMP_STATUS1_OUT_MASK)
+/*! @} */
+
+/*! @name ROUTE0 - ACOMP0 Route Register */
+/*! @{ */
+#define ACOMP_ROUTE0_OUTSEL_MASK (0x1U)
+#define ACOMP_ROUTE0_OUTSEL_SHIFT (0U)
+/*! outsel - Select ACOMP0 synchronous or asynchronous output to pin.
+ * 0b0..Synchronous output
+ * 0b1..Asynchronous output
+ */
+#define ACOMP_ROUTE0_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ROUTE0_OUTSEL_SHIFT)) & ACOMP_ROUTE0_OUTSEL_MASK)
+#define ACOMP_ROUTE0_PE_MASK (0x2U)
+#define ACOMP_ROUTE0_PE_SHIFT (1U)
+/*! pe - Enable/disable ACOMP0 output to pin.
+ * 0b0..
+ * 0b1..
+ */
+#define ACOMP_ROUTE0_PE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ROUTE0_PE_SHIFT)) & ACOMP_ROUTE0_PE_MASK)
+/*! @} */
+
+/*! @name ROUTE1 - ACOMP1 Route Register */
+/*! @{ */
+#define ACOMP_ROUTE1_OUTSEL_MASK (0x1U)
+#define ACOMP_ROUTE1_OUTSEL_SHIFT (0U)
+/*! outsel - Select ACOMP1 synchronous or asynchronous output to pin
+ * 0b0..Synchronous output
+ * 0b1..Asynchronous output
+ */
+#define ACOMP_ROUTE1_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ROUTE1_OUTSEL_SHIFT)) & ACOMP_ROUTE1_OUTSEL_MASK)
+#define ACOMP_ROUTE1_PE_MASK (0x2U)
+#define ACOMP_ROUTE1_PE_SHIFT (1U)
+/*! pe - Enable/disable ACOMP1 output to pin
+ * 0b0..
+ * 0b1..
+ */
+#define ACOMP_ROUTE1_PE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ROUTE1_PE_SHIFT)) & ACOMP_ROUTE1_PE_MASK)
+/*! @} */
+
+/*! @name ISR0 - ACOMP0 Interrupt Status Register */
+/*! @{ */
+#define ACOMP_ISR0_OUT_INT_MASK (0x1U)
+#define ACOMP_ISR0_OUT_INT_SHIFT (0U)
+/*! out_int - ACOMP0 Synchronized Output Interrupt
+ */
+#define ACOMP_ISR0_OUT_INT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ISR0_OUT_INT_SHIFT)) & ACOMP_ISR0_OUT_INT_MASK)
+#define ACOMP_ISR0_OUTA_INT_MASK (0x2U)
+#define ACOMP_ISR0_OUTA_INT_SHIFT (1U)
+/*! outa_int - ACOMP0 Asynchronized Output Interrupt
+ */
+#define ACOMP_ISR0_OUTA_INT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ISR0_OUTA_INT_SHIFT)) & ACOMP_ISR0_OUTA_INT_MASK)
+/*! @} */
+
+/*! @name ISR1 - ACOMP1 Interrupt Status Register */
+/*! @{ */
+#define ACOMP_ISR1_OUT_INT_MASK (0x1U)
+#define ACOMP_ISR1_OUT_INT_SHIFT (0U)
+/*! out_int - ACOMP1 Synchronized Output Interrupt
+ */
+#define ACOMP_ISR1_OUT_INT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ISR1_OUT_INT_SHIFT)) & ACOMP_ISR1_OUT_INT_MASK)
+#define ACOMP_ISR1_OUTA_INT_MASK (0x2U)
+#define ACOMP_ISR1_OUTA_INT_SHIFT (1U)
+/*! outa_int - ACOMP1 Asynchronized Output Interrupt
+ */
+#define ACOMP_ISR1_OUTA_INT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ISR1_OUTA_INT_SHIFT)) & ACOMP_ISR1_OUTA_INT_MASK)
+/*! @} */
+
+/*! @name IMR0 - ACOMP0 Interrupt Mask Register */
+/*! @{ */
+#define ACOMP_IMR0_OUT_INT_MASK_MASK (0x1U)
+#define ACOMP_IMR0_OUT_INT_MASK_SHIFT (0U)
+/*! out_int_mask - Mask Synchronized Interrupt
+ */
+#define ACOMP_IMR0_OUT_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_IMR0_OUT_INT_MASK_SHIFT)) & ACOMP_IMR0_OUT_INT_MASK_MASK)
+#define ACOMP_IMR0_OUTA_INT_MASK_MASK (0x2U)
+#define ACOMP_IMR0_OUTA_INT_MASK_SHIFT (1U)
+/*! outa_int_mask - Mask Asynchronized Interrupt
+ */
+#define ACOMP_IMR0_OUTA_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_IMR0_OUTA_INT_MASK_SHIFT)) & ACOMP_IMR0_OUTA_INT_MASK_MASK)
+/*! @} */
+
+/*! @name IMR1 - ACOMP1 Interrupt Mask Register */
+/*! @{ */
+#define ACOMP_IMR1_OUT_INT_MASK_MASK (0x1U)
+#define ACOMP_IMR1_OUT_INT_MASK_SHIFT (0U)
+/*! out_int_mask - Mask Synchronized Interrupt
+ */
+#define ACOMP_IMR1_OUT_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_IMR1_OUT_INT_MASK_SHIFT)) & ACOMP_IMR1_OUT_INT_MASK_MASK)
+#define ACOMP_IMR1_OUTA_INT_MASK_MASK (0x2U)
+#define ACOMP_IMR1_OUTA_INT_MASK_SHIFT (1U)
+/*! outa_int_mask - Mask Asynchronized Interrupt
+ */
+#define ACOMP_IMR1_OUTA_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_IMR1_OUTA_INT_MASK_SHIFT)) & ACOMP_IMR1_OUTA_INT_MASK_MASK)
+/*! @} */
+
+/*! @name IRSR0 - ACOMP0 Interrupt Raw Status Register */
+/*! @{ */
+#define ACOMP_IRSR0_OUT_INT_RAW_MASK (0x1U)
+#define ACOMP_IRSR0_OUT_INT_RAW_SHIFT (0U)
+/*! out_int_raw - Raw Mask Synchronized Interrupt
+ */
+#define ACOMP_IRSR0_OUT_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_IRSR0_OUT_INT_RAW_SHIFT)) & ACOMP_IRSR0_OUT_INT_RAW_MASK)
+#define ACOMP_IRSR0_OUTA_INT_RAW_MASK (0x2U)
+#define ACOMP_IRSR0_OUTA_INT_RAW_SHIFT (1U)
+/*! outa_int_raw - Raw Mask Asynchronized Interrupt
+ */
+#define ACOMP_IRSR0_OUTA_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_IRSR0_OUTA_INT_RAW_SHIFT)) & ACOMP_IRSR0_OUTA_INT_RAW_MASK)
+/*! @} */
+
+/*! @name IRSR1 - ACOMP1 Interrupt Raw Status Register */
+/*! @{ */
+#define ACOMP_IRSR1_OUT_INT_RAW_MASK (0x1U)
+#define ACOMP_IRSR1_OUT_INT_RAW_SHIFT (0U)
+/*! out_int_raw - Raw Mask Synchronized Interrupt
+ */
+#define ACOMP_IRSR1_OUT_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_IRSR1_OUT_INT_RAW_SHIFT)) & ACOMP_IRSR1_OUT_INT_RAW_MASK)
+#define ACOMP_IRSR1_OUTA_INT_RAW_MASK (0x2U)
+#define ACOMP_IRSR1_OUTA_INT_RAW_SHIFT (1U)
+/*! outa_int_raw - Raw Mask Asynchronized Interrupt
+ */
+#define ACOMP_IRSR1_OUTA_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_IRSR1_OUTA_INT_RAW_SHIFT)) & ACOMP_IRSR1_OUTA_INT_RAW_MASK)
+/*! @} */
+
+/*! @name ICR0 - ACOMP0 Interrupt Clear Register */
+/*! @{ */
+#define ACOMP_ICR0_OUT_INT_CLR_MASK (0x1U)
+#define ACOMP_ICR0_OUT_INT_CLR_SHIFT (0U)
+/*! out_int_clr - ACOMP0 syncrhonized output interrupt flag clear signal.
+ */
+#define ACOMP_ICR0_OUT_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ICR0_OUT_INT_CLR_SHIFT)) & ACOMP_ICR0_OUT_INT_CLR_MASK)
+#define ACOMP_ICR0_OUTA_INT_CLR_MASK (0x2U)
+#define ACOMP_ICR0_OUTA_INT_CLR_SHIFT (1U)
+/*! outa_int_clr - ACOMP0 asyncrhonized output interrupt flag clear signal.
+ */
+#define ACOMP_ICR0_OUTA_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ICR0_OUTA_INT_CLR_SHIFT)) & ACOMP_ICR0_OUTA_INT_CLR_MASK)
+/*! @} */
+
+/*! @name ICR1 - ACOMP1 Interrupt Clear Register */
+/*! @{ */
+#define ACOMP_ICR1_OUT_INT_CLR_MASK (0x1U)
+#define ACOMP_ICR1_OUT_INT_CLR_SHIFT (0U)
+/*! out_int_clr - ACOMP1 syncrhonized output interrupt flag clear signal.
+ */
+#define ACOMP_ICR1_OUT_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ICR1_OUT_INT_CLR_SHIFT)) & ACOMP_ICR1_OUT_INT_CLR_MASK)
+#define ACOMP_ICR1_OUTA_INT_CLR_MASK (0x2U)
+#define ACOMP_ICR1_OUTA_INT_CLR_SHIFT (1U)
+/*! outa_int_clr - ACOMP1 asyncrhonized output interrupt flag clear signal.
+ */
+#define ACOMP_ICR1_OUTA_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_ICR1_OUTA_INT_CLR_SHIFT)) & ACOMP_ICR1_OUTA_INT_CLR_MASK)
+/*! @} */
+
+/*! @name RST0 - ACOMP0 Soft Reset Register */
+/*! @{ */
+#define ACOMP_RST0_SOFT_RST_MASK (0x1U)
+#define ACOMP_RST0_SOFT_RST_SHIFT (0U)
+/*! soft_rst - Soft Reset for ACOMP0 (active high)
+ * 0b0..no action
+ * 0b1..
+ */
+#define ACOMP_RST0_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_RST0_SOFT_RST_SHIFT)) & ACOMP_RST0_SOFT_RST_MASK)
+/*! @} */
+
+/*! @name RST1 - ACOMP1 Soft Reset Register */
+/*! @{ */
+#define ACOMP_RST1_SOFT_RST_MASK (0x1U)
+#define ACOMP_RST1_SOFT_RST_SHIFT (0U)
+/*! soft_rst - Soft Reset for ACOMP1 (active high)
+ * 0b0..no action
+ * 0b1..
+ */
+#define ACOMP_RST1_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_RST1_SOFT_RST_SHIFT)) & ACOMP_RST1_SOFT_RST_MASK)
+/*! @} */
+
+/*! @name CLK - Clock Register */
+/*! @{ */
+#define ACOMP_CLK_SOFT_CLK_RST_MASK (0x2U)
+#define ACOMP_CLK_SOFT_CLK_RST_SHIFT (1U)
+/*! soft_clk_rst - soft reset for clock divider
+ * 0b0..no action
+ * 0b1..
+ */
+#define ACOMP_CLK_SOFT_CLK_RST(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CLK_SOFT_CLK_RST_SHIFT)) & ACOMP_CLK_SOFT_CLK_RST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ACOMP_Register_Masks */
+
+
+/* ACOMP - Peripheral instance base addresses */
+/** Peripheral ACOMP base address */
+#define ACOMP_BASE (0x460B0400u)
+/** Peripheral ACOMP base pointer */
+#define ACOMP ((ACOMP_Type *)ACOMP_BASE)
+/** Array initializer of ACOMP peripheral base addresses */
+#define ACOMP_BASE_ADDRS { ACOMP_BASE }
+/** Array initializer of ACOMP peripheral base pointers */
+#define ACOMP_BASE_PTRS { ACOMP }
+/** Interrupt vectors for the ACOMP peripheral type */
+#define ACOMP_FUNC_IRQS { ACOMP_IRQn }
+#define ACOMP_WAKE_IRQS { ACOMP_WAKEUP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ACOMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t ADC_REG_CMD; /**< , offset: 0x0 */
+ __IO uint32_t ADC_REG_GENERAL; /**< , offset: 0x4 */
+ __IO uint32_t ADC_REG_CONFIG; /**< , offset: 0x8 */
+ __IO uint32_t ADC_REG_INTERVAL; /**< , offset: 0xC */
+ __IO uint32_t ADC_REG_ANA; /**< , offset: 0x10 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ADC_REG_SCN1; /**< adc converation sequence 1, offset: 0x18 */
+ __IO uint32_t ADC_REG_SCN2; /**< adc converation sequence 2, offset: 0x1C */
+ __IO uint32_t ADC_REG_RESULT_BUF; /**< , offset: 0x20 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t ADC_REG_DMAR; /**< , offset: 0x28 */
+ __I uint32_t ADC_REG_STATUS; /**< , offset: 0x2C */
+ __I uint32_t ADC_REG_ISR; /**< , offset: 0x30 */
+ __IO uint32_t ADC_REG_IMR; /**< , offset: 0x34 */
+ __I uint32_t ADC_REG_IRSR; /**< , offset: 0x38 */
+ __IO uint32_t ADC_REG_ICR; /**< , offset: 0x3C */
+ uint8_t RESERVED_2[4];
+ __I uint32_t ADC_REG_RESULT; /**< , offset: 0x44 */
+ __I uint32_t ADC_REG_RAW_RESULT; /**< , offset: 0x48 */
+ __IO uint32_t ADC_REG_OFFSET_CAL; /**< , offset: 0x4C */
+ __IO uint32_t ADC_REG_GAIN_CAL; /**< , offset: 0x50 */
+ __IO uint32_t ADC_REG_TEST; /**< , offset: 0x54 */
+ __IO uint32_t ADC_REG_AUDIO; /**< , offset: 0x58 */
+ __IO uint32_t ADC_REG_VOICE_DET; /**< , offset: 0x5C */
+ __IO uint32_t ADC_REG_RSVD; /**< , offset: 0x60 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name ADC_REG_CMD - */
+/*! @{ */
+#define ADC_ADC_REG_CMD_CONV_START_MASK (0x1U)
+#define ADC_ADC_REG_CMD_CONV_START_SHIFT (0U)
+/*! conv_start - converaion control bit.
+ * 0b0..stop converation
+ * 0b1..start converation. This will clear the FIFO.
+ */
+#define ADC_ADC_REG_CMD_CONV_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CMD_CONV_START_SHIFT)) & ADC_ADC_REG_CMD_CONV_START_MASK)
+#define ADC_ADC_REG_CMD_SOFT_RST_MASK (0x2U)
+#define ADC_ADC_REG_CMD_SOFT_RST_SHIFT (1U)
+/*! soft_rst - user reset the whole block
+ */
+#define ADC_ADC_REG_CMD_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CMD_SOFT_RST_SHIFT)) & ADC_ADC_REG_CMD_SOFT_RST_MASK)
+#define ADC_ADC_REG_CMD_SOFT_CLK_RST_MASK (0x4U)
+#define ADC_ADC_REG_CMD_SOFT_CLK_RST_SHIFT (2U)
+/*! soft_clk_rst - user reset clock
+ */
+#define ADC_ADC_REG_CMD_SOFT_CLK_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CMD_SOFT_CLK_RST_SHIFT)) & ADC_ADC_REG_CMD_SOFT_CLK_RST_MASK)
+/*! @} */
+
+/*! @name ADC_REG_GENERAL - */
+/*! @{ */
+#define ADC_ADC_REG_GENERAL_GPADC_MASTER_MASK (0x1U)
+#define ADC_ADC_REG_GENERAL_GPADC_MASTER_SHIFT (0U)
+/*! gpadc_master - play as master or slave in dual mode, master is the only controller of when slave start
+ * 0b0..ADC is slave
+ * 0b1..ADC is master
+ */
+#define ADC_ADC_REG_GENERAL_GPADC_MASTER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_GPADC_MASTER_SHIFT)) & ADC_ADC_REG_GENERAL_GPADC_MASTER_MASK)
+#define ADC_ADC_REG_GENERAL_GLOBAL_EN_MASK (0x2U)
+#define ADC_ADC_REG_GENERAL_GLOBAL_EN_SHIFT (1U)
+/*! global_en - ADC enable/disable
+ */
+#define ADC_ADC_REG_GENERAL_GLOBAL_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_GLOBAL_EN_SHIFT)) & ADC_ADC_REG_GENERAL_GLOBAL_EN_MASK)
+#define ADC_ADC_REG_GENERAL_FORCE_CLK_ON_MASK (0x4U)
+#define ADC_ADC_REG_GENERAL_FORCE_CLK_ON_SHIFT (2U)
+/*! force_clk_on - override the gpadc_mclk_en from outside
+ * 0b0..clock disable
+ * 0b1..clock enable
+ */
+#define ADC_ADC_REG_GENERAL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_FORCE_CLK_ON_SHIFT)) & ADC_ADC_REG_GENERAL_FORCE_CLK_ON_MASK)
+#define ADC_ADC_REG_GENERAL_CLK_ANA64M_INV_MASK (0x8U)
+#define ADC_ADC_REG_GENERAL_CLK_ANA64M_INV_SHIFT (3U)
+/*! clk_ana64M_inv - analog clock 64M inverted
+ */
+#define ADC_ADC_REG_GENERAL_CLK_ANA64M_INV(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_CLK_ANA64M_INV_SHIFT)) & ADC_ADC_REG_GENERAL_CLK_ANA64M_INV_MASK)
+#define ADC_ADC_REG_GENERAL_CLK_ANA2M_INV_MASK (0x10U)
+#define ADC_ADC_REG_GENERAL_CLK_ANA2M_INV_SHIFT (4U)
+/*! clk_ana2M_inv - analog clock 2M inverted
+ */
+#define ADC_ADC_REG_GENERAL_CLK_ANA2M_INV(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_CLK_ANA2M_INV_SHIFT)) & ADC_ADC_REG_GENERAL_CLK_ANA2M_INV_MASK)
+#define ADC_ADC_REG_GENERAL_ADC_CAL_EN_MASK (0x20U)
+#define ADC_ADC_REG_GENERAL_ADC_CAL_EN_SHIFT (5U)
+/*! adc_cal_en - calibration enable, auto cleared after calibration done
+ */
+#define ADC_ADC_REG_GENERAL_ADC_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_ADC_CAL_EN_SHIFT)) & ADC_ADC_REG_GENERAL_ADC_CAL_EN_MASK)
+#define ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_MASK (0x3F00U)
+#define ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_SHIFT (8U)
+/*! clk_div_ratio - analog 64M clock division ratio
+ */
+#define ADC_ADC_REG_GENERAL_CLK_DIV_RATIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_SHIFT)) & ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_MASK)
+/*! @} */
+
+/*! @name ADC_REG_CONFIG - */
+/*! @{ */
+#define ADC_ADC_REG_CONFIG_TRIGGER_SEL_MASK (0xFU)
+#define ADC_ADC_REG_CONFIG_TRIGGER_SEL_SHIFT (0U)
+/*! trigger_sel - External trigger source select bits
+ */
+#define ADC_ADC_REG_CONFIG_TRIGGER_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_TRIGGER_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_TRIGGER_SEL_MASK)
+#define ADC_ADC_REG_CONFIG_TRIGGER_EN_MASK (0x10U)
+#define ADC_ADC_REG_CONFIG_TRIGGER_EN_SHIFT (4U)
+/*! trigger_en - External elevel trigger enable bit, support gpadc_trigger/gpadc_data_valid handshake
+ * 0b0..
+ * 0b1..conversion start further controlled by external level signal
+ */
+#define ADC_ADC_REG_CONFIG_TRIGGER_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_TRIGGER_EN_SHIFT)) & ADC_ADC_REG_CONFIG_TRIGGER_EN_MASK)
+#define ADC_ADC_REG_CONFIG_DUAL_MODE_MASK (0x20U)
+#define ADC_ADC_REG_CONFIG_DUAL_MODE_SHIFT (5U)
+/*! dual_mode - dual mode select
+ * 0b0..simultaneous mode
+ * 0b1..interleave mode
+ */
+#define ADC_ADC_REG_CONFIG_DUAL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_DUAL_MODE_SHIFT)) & ADC_ADC_REG_CONFIG_DUAL_MODE_MASK)
+#define ADC_ADC_REG_CONFIG_SINGLE_DUAL_MASK (0x40U)
+#define ADC_ADC_REG_CONFIG_SINGLE_DUAL_SHIFT (6U)
+/*! single_dual - work mode select
+ * 0b0..independent mode
+ * 0b1..dual mode
+ */
+#define ADC_ADC_REG_CONFIG_SINGLE_DUAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_SINGLE_DUAL_SHIFT)) & ADC_ADC_REG_CONFIG_SINGLE_DUAL_MASK)
+#define ADC_ADC_REG_CONFIG_CONT_CONV_EN_MASK (0x100U)
+#define ADC_ADC_REG_CONFIG_CONT_CONV_EN_SHIFT (8U)
+/*! cont_conv_en - To enable continuous conversion
+ * 0b0..one shot conversion
+ * 0b1..continuous conversion
+ */
+#define ADC_ADC_REG_CONFIG_CONT_CONV_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_CONT_CONV_EN_SHIFT)) & ADC_ADC_REG_CONFIG_CONT_CONV_EN_MASK)
+#define ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL_MASK (0x200U)
+#define ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL_SHIFT (9U)
+/*! data_format_sel - set data format for the final data
+ * 0b0..signed differential code in two's complement
+ * 0b1..unsigned single-end code
+ */
+#define ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_DATA_FORMAT_SEL_MASK)
+#define ADC_ADC_REG_CONFIG_CAL_VREF_SEL_MASK (0x400U)
+#define ADC_ADC_REG_CONFIG_CAL_VREF_SEL_SHIFT (10U)
+/*! cal_vref_sel - select input reference channel for gain calibration
+ * 0b0..select internal vref as input for calibration
+ * 0b1..select external vref as input for calibration
+ */
+#define ADC_ADC_REG_CONFIG_CAL_VREF_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_CAL_VREF_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_CAL_VREF_SEL_MASK)
+#define ADC_ADC_REG_CONFIG_CAL_DATA_RST_MASK (0x800U)
+#define ADC_ADC_REG_CONFIG_CAL_DATA_RST_SHIFT (11U)
+/*! cal_data_rst - reset the self calibration data.
+ * 0b0..no reset
+ * 0b1..
+ */
+#define ADC_ADC_REG_CONFIG_CAL_DATA_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_CAL_DATA_RST_SHIFT)) & ADC_ADC_REG_CONFIG_CAL_DATA_RST_MASK)
+#define ADC_ADC_REG_CONFIG_CAL_DATA_SEL_MASK (0x1000U)
+#define ADC_ADC_REG_CONFIG_CAL_DATA_SEL_SHIFT (12U)
+/*! cal_data_sel - select calibration data source.
+ * 0b0..use self calibration data
+ * 0b1..user user defined calibration data
+ */
+#define ADC_ADC_REG_CONFIG_CAL_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_CAL_DATA_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_CAL_DATA_SEL_MASK)
+#define ADC_ADC_REG_CONFIG_AVG_SEL_MASK (0xE000U)
+#define ADC_ADC_REG_CONFIG_AVG_SEL_SHIFT (13U)
+/*! avg_sel - moving average length
+ */
+#define ADC_ADC_REG_CONFIG_AVG_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_AVG_SEL_SHIFT)) & ADC_ADC_REG_CONFIG_AVG_SEL_MASK)
+#define ADC_ADC_REG_CONFIG_SCAN_LENGTH_MASK (0xF0000U)
+#define ADC_ADC_REG_CONFIG_SCAN_LENGTH_SHIFT (16U)
+/*! scan_length - scan converation length, actual length is scan_length+1.
+ */
+#define ADC_ADC_REG_CONFIG_SCAN_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_SCAN_LENGTH_SHIFT)) & ADC_ADC_REG_CONFIG_SCAN_LENGTH_MASK)
+#define ADC_ADC_REG_CONFIG_PWR_MODE_MASK (0x100000U)
+#define ADC_ADC_REG_CONFIG_PWR_MODE_SHIFT (20U)
+/*! pwr_mode - ADC power mode select.
+ * 0b0..Power mode 0. Analog biasing and reference block are powered up when both global_en and gpadc_conv_start is 1
+ * 0b1..Power mode 1. Analog biasing and reference block are powered up once gpadc_global_en is 1
+ */
+#define ADC_ADC_REG_CONFIG_PWR_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_CONFIG_PWR_MODE_SHIFT)) & ADC_ADC_REG_CONFIG_PWR_MODE_MASK)
+/*! @} */
+
+/*! @name ADC_REG_INTERVAL - */
+/*! @{ */
+#define ADC_ADC_REG_INTERVAL_WARMUP_TIME_MASK (0x1FU)
+#define ADC_ADC_REG_INTERVAL_WARMUP_TIME_SHIFT (0U)
+/*! Warmup_time - warmup time, should be set equal to or higher than 1uS.
+ * 0b00000..ADC warm-up is 1us
+ * 0b11111..ADC warm-up is 32us
+ */
+#define ADC_ADC_REG_INTERVAL_WARMUP_TIME(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_INTERVAL_WARMUP_TIME_SHIFT)) & ADC_ADC_REG_INTERVAL_WARMUP_TIME_MASK)
+#define ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_MASK (0x20U)
+#define ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_SHIFT (5U)
+/*! bypass_warmup - Bypass warmup state inside adc.
+ * 0b0..adc warmup state enabled (warmup period is controlled by warmup time)
+ * 0b1..adc warmup state bypassed
+ */
+#define ADC_ADC_REG_INTERVAL_BYPASS_WARMUP(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_SHIFT)) & ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_MASK)
+/*! @} */
+
+/*! @name ADC_REG_ANA - */
+/*! @{ */
+#define ADC_ADC_REG_ANA_TSEXT_SEL_MASK (0x1U)
+#define ADC_ADC_REG_ANA_TSEXT_SEL_SHIFT (0U)
+/*! tsext_sel - temperature sensor diode select
+ * 0b0..internal diode mode
+ * 0b1..external diode mode
+ */
+#define ADC_ADC_REG_ANA_TSEXT_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_TSEXT_SEL_SHIFT)) & ADC_ADC_REG_ANA_TSEXT_SEL_MASK)
+#define ADC_ADC_REG_ANA_TS_EN_MASK (0x2U)
+#define ADC_ADC_REG_ANA_TS_EN_SHIFT (1U)
+/*! ts_en - temperature sensor enable, only enable when channel source is temperature sensor
+ * 0b0..
+ * 0b1..
+ */
+#define ADC_ADC_REG_ANA_TS_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_TS_EN_SHIFT)) & ADC_ADC_REG_ANA_TS_EN_MASK)
+#define ADC_ADC_REG_ANA_VREF_SCF_BYPASS_MASK (0x4U)
+#define ADC_ADC_REG_ANA_VREF_SCF_BYPASS_SHIFT (2U)
+/*! vref_scf_bypass - adc voltage reference buffer sc-filter bypass
+ * 0b0..not bypass sc-filter
+ * 0b1..bypass sc-filter
+ */
+#define ADC_ADC_REG_ANA_VREF_SCF_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_VREF_SCF_BYPASS_SHIFT)) & ADC_ADC_REG_ANA_VREF_SCF_BYPASS_MASK)
+#define ADC_ADC_REG_ANA_VREF_CHOP_EN_MASK (0x8U)
+#define ADC_ADC_REG_ANA_VREF_CHOP_EN_SHIFT (3U)
+/*! vref_chop_en - adc voltage reference buffer chopper enable
+ * 0b0..disable chopper
+ * 0b1..enable chopper
+ */
+#define ADC_ADC_REG_ANA_VREF_CHOP_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_VREF_CHOP_EN_SHIFT)) & ADC_ADC_REG_ANA_VREF_CHOP_EN_MASK)
+#define ADC_ADC_REG_ANA_VREF_SEL_MASK (0x30U)
+#define ADC_ADC_REG_ANA_VREF_SEL_SHIFT (4U)
+/*! vref_sel - adc reference voltage select.
+ * 0b00..Internal 1.8V vaa
+ * 0b01..Internal 1.2V bandgap
+ * 0b10..External single-ended reference (gpadc_ch[3])
+ * 0b11..Internal 1.2V bandgap with external bypass pin (gpadc_ch[3])
+ */
+#define ADC_ADC_REG_ANA_VREF_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_VREF_SEL_SHIFT)) & ADC_ADC_REG_ANA_VREF_SEL_MASK)
+#define ADC_ADC_REG_ANA_SINGLEDIFF_MASK (0x400U)
+#define ADC_ADC_REG_ANA_SINGLEDIFF_SHIFT (10U)
+/*! Singlediff - Select single ended or differential input.
+ * 0b0..Single-ended input
+ * 0b1..Differential input
+ */
+#define ADC_ADC_REG_ANA_SINGLEDIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_SINGLEDIFF_SHIFT)) & ADC_ADC_REG_ANA_SINGLEDIFF_MASK)
+#define ADC_ADC_REG_ANA_INBUF_GAIN_MASK (0x1800U)
+#define ADC_ADC_REG_ANA_INBUF_GAIN_SHIFT (11U)
+/*! inbuf_gain - adc gain control. Also select input voltage range.
+ * 0b00..PGA gain is 0.5. Input voltage range is 2*vref
+ * 0b01..PGA gain is 1. Input voltage range is vref
+ * 0b10..PGA gain is 2. Input voltage range is 0.5*vref
+ * 0b11..reserved
+ */
+#define ADC_ADC_REG_ANA_INBUF_GAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_INBUF_GAIN_SHIFT)) & ADC_ADC_REG_ANA_INBUF_GAIN_MASK)
+#define ADC_ADC_REG_ANA_INBUF_CHOP_EN_MASK (0x2000U)
+#define ADC_ADC_REG_ANA_INBUF_CHOP_EN_SHIFT (13U)
+/*! inbuf_chop_en - Input buffer chopper enable
+ * 0b0..disable chopper
+ * 0b1..enable chopper
+ */
+#define ADC_ADC_REG_ANA_INBUF_CHOP_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_INBUF_CHOP_EN_SHIFT)) & ADC_ADC_REG_ANA_INBUF_CHOP_EN_MASK)
+#define ADC_ADC_REG_ANA_INBUF_EN_MASK (0x4000U)
+#define ADC_ADC_REG_ANA_INBUF_EN_SHIFT (14U)
+/*! inbuf_en - gpadc input gain buffer enable bit.
+ * 0b0..input gain buffer disabled
+ * 0b1..input gain buffer enabled
+ */
+#define ADC_ADC_REG_ANA_INBUF_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_INBUF_EN_SHIFT)) & ADC_ADC_REG_ANA_INBUF_EN_MASK)
+#define ADC_ADC_REG_ANA_CHOP_EN_MASK (0x8000U)
+#define ADC_ADC_REG_ANA_CHOP_EN_SHIFT (15U)
+/*! chop_en - adc chopper/auto-zero(only in 12bit mode) enable
+ * 0b0..disable chopper
+ * 0b1..enable chopper
+ */
+#define ADC_ADC_REG_ANA_CHOP_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_CHOP_EN_SHIFT)) & ADC_ADC_REG_ANA_CHOP_EN_MASK)
+#define ADC_ADC_REG_ANA_BIAS_SEL_MASK (0x10000U)
+#define ADC_ADC_REG_ANA_BIAS_SEL_SHIFT (16U)
+/*! bias_sel - adc analog portion low power mode select. Half the biasing current for modulator when enabled.
+ * 0b0..Full biasing current
+ * 0b1..Half biasing current
+ */
+#define ADC_ADC_REG_ANA_BIAS_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_BIAS_SEL_SHIFT)) & ADC_ADC_REG_ANA_BIAS_SEL_MASK)
+#define ADC_ADC_REG_ANA_RES_SEL_MASK (0x60000U)
+#define ADC_ADC_REG_ANA_RES_SEL_SHIFT (17U)
+/*! res_sel - adc resolution/data rate select
+ */
+#define ADC_ADC_REG_ANA_RES_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ANA_RES_SEL_SHIFT)) & ADC_ADC_REG_ANA_RES_SEL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_SCN1 - adc converation sequence 1 */
+/*! @{ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_0_MASK (0xFU)
+#define ADC_ADC_REG_SCN1_SCAN_CH_0_SHIFT (0U)
+/*! scan_ch_0 - amux source 0
+ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_0_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_0_MASK)
+#define ADC_ADC_REG_SCN1_SCAN_CH_1_MASK (0xF0U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_1_SHIFT (4U)
+/*! scan_ch_1 - amux source 1
+ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_1_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_1_MASK)
+#define ADC_ADC_REG_SCN1_SCAN_CH_2_MASK (0xF00U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_2_SHIFT (8U)
+/*! scan_ch_2 - amux source 2
+ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_2_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_2_MASK)
+#define ADC_ADC_REG_SCN1_SCAN_CH_3_MASK (0xF000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_3_SHIFT (12U)
+/*! scan_ch_3 - amux source 3
+ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_3_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_3_MASK)
+#define ADC_ADC_REG_SCN1_SCAN_CH_4_MASK (0xF0000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_4_SHIFT (16U)
+/*! scan_ch_4 - amux source 4
+ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_4_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_4_MASK)
+#define ADC_ADC_REG_SCN1_SCAN_CH_5_MASK (0xF00000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_5_SHIFT (20U)
+/*! scan_ch_5 - amux source 5
+ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_5_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_5_MASK)
+#define ADC_ADC_REG_SCN1_SCAN_CH_6_MASK (0xF000000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_6_SHIFT (24U)
+/*! scan_ch_6 - amux source 6
+ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_6_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_6_MASK)
+#define ADC_ADC_REG_SCN1_SCAN_CH_7_MASK (0xF0000000U)
+#define ADC_ADC_REG_SCN1_SCAN_CH_7_SHIFT (28U)
+/*! scan_ch_7 - amux source 7
+ */
+#define ADC_ADC_REG_SCN1_SCAN_CH_7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN1_SCAN_CH_7_SHIFT)) & ADC_ADC_REG_SCN1_SCAN_CH_7_MASK)
+/*! @} */
+
+/*! @name ADC_REG_SCN2 - adc converation sequence 2 */
+/*! @{ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_8_MASK (0xFU)
+#define ADC_ADC_REG_SCN2_SCAN_CH_8_SHIFT (0U)
+/*! scan_ch_8 - amux source 8
+ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_8(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_8_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_8_MASK)
+#define ADC_ADC_REG_SCN2_SCAN_CH_9_MASK (0xF0U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_9_SHIFT (4U)
+/*! scan_ch_9 - amux source 9
+ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_9(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_9_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_9_MASK)
+#define ADC_ADC_REG_SCN2_SCAN_CH_10_MASK (0xF00U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_10_SHIFT (8U)
+/*! scan_ch_10 - amux source 10
+ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_10(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_10_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_10_MASK)
+#define ADC_ADC_REG_SCN2_SCAN_CH_11_MASK (0xF000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_11_SHIFT (12U)
+/*! scan_ch_11 - amux source 11
+ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_11(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_11_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_11_MASK)
+#define ADC_ADC_REG_SCN2_SCAN_CH_12_MASK (0xF0000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_12_SHIFT (16U)
+/*! scan_ch_12 - amux source 12
+ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_12(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_12_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_12_MASK)
+#define ADC_ADC_REG_SCN2_SCAN_CH_13_MASK (0xF00000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_13_SHIFT (20U)
+/*! scan_ch_13 - amux source 13
+ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_13(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_13_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_13_MASK)
+#define ADC_ADC_REG_SCN2_SCAN_CH_14_MASK (0xF000000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_14_SHIFT (24U)
+/*! scan_ch_14 - amux source 14
+ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_14(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_14_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_14_MASK)
+#define ADC_ADC_REG_SCN2_SCAN_CH_15_MASK (0xF0000000U)
+#define ADC_ADC_REG_SCN2_SCAN_CH_15_SHIFT (28U)
+/*! scan_ch_15 - amux source 15
+ */
+#define ADC_ADC_REG_SCN2_SCAN_CH_15(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_SCN2_SCAN_CH_15_SHIFT)) & ADC_ADC_REG_SCN2_SCAN_CH_15_MASK)
+/*! @} */
+
+/*! @name ADC_REG_RESULT_BUF - */
+/*! @{ */
+#define ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_MASK (0x1U)
+#define ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_SHIFT (0U)
+/*! width_sel - adc finial result fifo data packed format select, must set scan_length as even when choose 32-bits
+ * 0b0..16-bits and adc_reg_result fifo is lower 16-bits effective
+ * 0b1..32-bits and adc_reg_result fifo is 32-bits effective
+ */
+#define ADC_ADC_REG_RESULT_BUF_WIDTH_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_SHIFT)) & ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_DMAR - */
+/*! @{ */
+#define ADC_ADC_REG_DMAR_DMA_EN_MASK (0x1U)
+#define ADC_ADC_REG_DMAR_DMA_EN_SHIFT (0U)
+/*! dma_en - dma enbale
+ * 0b0..disable dma handshake. This will also clear remaining dma request to system dmac
+ * 0b1..enable dma handshake. Must enable after conv_start is asserted to ensure FIFO is cleared.
+ */
+#define ADC_ADC_REG_DMAR_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_DMAR_DMA_EN_SHIFT)) & ADC_ADC_REG_DMAR_DMA_EN_MASK)
+#define ADC_ADC_REG_DMAR_FIFO_THL_MASK (0x6U)
+#define ADC_ADC_REG_DMAR_FIFO_THL_SHIFT (1U)
+/*! fifo_thl - fifo threshold
+ * 0b00..1 data
+ * 0b01..4 data
+ * 0b10..8 data
+ * 0b11..16 data
+ */
+#define ADC_ADC_REG_DMAR_FIFO_THL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_DMAR_FIFO_THL_SHIFT)) & ADC_ADC_REG_DMAR_FIFO_THL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_STATUS - */
+/*! @{ */
+#define ADC_ADC_REG_STATUS_ACT_MASK (0x1U)
+#define ADC_ADC_REG_STATUS_ACT_SHIFT (0U)
+/*! act - adc status
+ * 0b0..ADC converstion inactive status
+ * 0b1..ADC conversion active status
+ */
+#define ADC_ADC_REG_STATUS_ACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_STATUS_ACT_SHIFT)) & ADC_ADC_REG_STATUS_ACT_MASK)
+#define ADC_ADC_REG_STATUS_FIFO_NE_MASK (0x2U)
+#define ADC_ADC_REG_STATUS_FIFO_NE_SHIFT (1U)
+/*! fifo_ne - fifo not empty status
+ */
+#define ADC_ADC_REG_STATUS_FIFO_NE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_STATUS_FIFO_NE_SHIFT)) & ADC_ADC_REG_STATUS_FIFO_NE_MASK)
+#define ADC_ADC_REG_STATUS_FIFO_FULL_MASK (0x4U)
+#define ADC_ADC_REG_STATUS_FIFO_FULL_SHIFT (2U)
+/*! fifo_full - fifo full status
+ */
+#define ADC_ADC_REG_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_STATUS_FIFO_FULL_SHIFT)) & ADC_ADC_REG_STATUS_FIFO_FULL_MASK)
+#define ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_MASK (0x1F8U)
+#define ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_SHIFT (3U)
+/*! fifo_data_count - fifo data number
+ */
+#define ADC_ADC_REG_STATUS_FIFO_DATA_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_SHIFT)) & ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_MASK)
+/*! @} */
+
+/*! @name ADC_REG_ISR - */
+/*! @{ */
+#define ADC_ADC_REG_ISR_RDY_MASK (0x1U)
+#define ADC_ADC_REG_ISR_RDY_SHIFT (0U)
+/*! rdy - Conversion data ready interrupt flag
+ */
+#define ADC_ADC_REG_ISR_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_RDY_SHIFT)) & ADC_ADC_REG_ISR_RDY_MASK)
+#define ADC_ADC_REG_ISR_GAINSAT_MASK (0x2U)
+#define ADC_ADC_REG_ISR_GAINSAT_SHIFT (1U)
+/*! gainsat - Gain correction saturation interrupt flag
+ */
+#define ADC_ADC_REG_ISR_GAINSAT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_GAINSAT_SHIFT)) & ADC_ADC_REG_ISR_GAINSAT_MASK)
+#define ADC_ADC_REG_ISR_OFFSAT_MASK (0x4U)
+#define ADC_ADC_REG_ISR_OFFSAT_SHIFT (2U)
+/*! offsat - Offset correction saturation interrupt flag
+ */
+#define ADC_ADC_REG_ISR_OFFSAT(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_OFFSAT_SHIFT)) & ADC_ADC_REG_ISR_OFFSAT_MASK)
+#define ADC_ADC_REG_ISR_DATASAT_NEG_MASK (0x8U)
+#define ADC_ADC_REG_ISR_DATASAT_NEG_SHIFT (3U)
+/*! datasat_neg - ADC data negative side saturation interrupt flag
+ */
+#define ADC_ADC_REG_ISR_DATASAT_NEG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_DATASAT_NEG_SHIFT)) & ADC_ADC_REG_ISR_DATASAT_NEG_MASK)
+#define ADC_ADC_REG_ISR_DATASAT_POS_MASK (0x10U)
+#define ADC_ADC_REG_ISR_DATASAT_POS_SHIFT (4U)
+/*! datasat_pos - ADC data positive side saturation interrupt flag
+ */
+#define ADC_ADC_REG_ISR_DATASAT_POS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_DATASAT_POS_SHIFT)) & ADC_ADC_REG_ISR_DATASAT_POS_MASK)
+#define ADC_ADC_REG_ISR_FIFO_OVERRUN_MASK (0x20U)
+#define ADC_ADC_REG_ISR_FIFO_OVERRUN_SHIFT (5U)
+/*! fifo_overrun - FIFO overrun interrupt flag
+ */
+#define ADC_ADC_REG_ISR_FIFO_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_FIFO_OVERRUN_SHIFT)) & ADC_ADC_REG_ISR_FIFO_OVERRUN_MASK)
+#define ADC_ADC_REG_ISR_FIFO_UNDERRUN_MASK (0x40U)
+#define ADC_ADC_REG_ISR_FIFO_UNDERRUN_SHIFT (6U)
+/*! fifo_underrun - FIFO underrun interrupt flag
+ */
+#define ADC_ADC_REG_ISR_FIFO_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ISR_FIFO_UNDERRUN_SHIFT)) & ADC_ADC_REG_ISR_FIFO_UNDERRUN_MASK)
+/*! @} */
+
+/*! @name ADC_REG_IMR - */
+/*! @{ */
+#define ADC_ADC_REG_IMR_RDY_MASK_MASK (0x1U)
+#define ADC_ADC_REG_IMR_RDY_MASK_SHIFT (0U)
+/*! rdy_mask - write 1 mask
+ */
+#define ADC_ADC_REG_IMR_RDY_MASK(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_RDY_MASK_SHIFT)) & ADC_ADC_REG_IMR_RDY_MASK_MASK)
+#define ADC_ADC_REG_IMR_GAINSAT_MASK_MASK (0x2U)
+#define ADC_ADC_REG_IMR_GAINSAT_MASK_SHIFT (1U)
+/*! gainsat_mask - write 1 mask
+ */
+#define ADC_ADC_REG_IMR_GAINSAT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_GAINSAT_MASK_SHIFT)) & ADC_ADC_REG_IMR_GAINSAT_MASK_MASK)
+#define ADC_ADC_REG_IMR_OFFSAT_MASK_MASK (0x4U)
+#define ADC_ADC_REG_IMR_OFFSAT_MASK_SHIFT (2U)
+/*! offsat_mask - write 1 mask
+ */
+#define ADC_ADC_REG_IMR_OFFSAT_MASK(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_OFFSAT_MASK_SHIFT)) & ADC_ADC_REG_IMR_OFFSAT_MASK_MASK)
+#define ADC_ADC_REG_IMR_DATASAT_NEG_MASK_MASK (0x8U)
+#define ADC_ADC_REG_IMR_DATASAT_NEG_MASK_SHIFT (3U)
+/*! datasat_neg_mask - write 1 mask
+ */
+#define ADC_ADC_REG_IMR_DATASAT_NEG_MASK(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_DATASAT_NEG_MASK_SHIFT)) & ADC_ADC_REG_IMR_DATASAT_NEG_MASK_MASK)
+#define ADC_ADC_REG_IMR_DATASAT_POS_MASK_MASK (0x10U)
+#define ADC_ADC_REG_IMR_DATASAT_POS_MASK_SHIFT (4U)
+/*! datasat_pos_mask - write 1 mask
+ */
+#define ADC_ADC_REG_IMR_DATASAT_POS_MASK(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_DATASAT_POS_MASK_SHIFT)) & ADC_ADC_REG_IMR_DATASAT_POS_MASK_MASK)
+#define ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_MASK (0x20U)
+#define ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_SHIFT (5U)
+/*! fifo_overrun_mask - write 1 mask
+ */
+#define ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_SHIFT)) & ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_MASK)
+#define ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_MASK (0x40U)
+#define ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_SHIFT (6U)
+/*! fifo_underrun_mask - write 1 mask
+ */
+#define ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_SHIFT)) & ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_MASK)
+/*! @} */
+
+/*! @name ADC_REG_IRSR - */
+/*! @{ */
+#define ADC_ADC_REG_IRSR_RDY_RAW_MASK (0x1U)
+#define ADC_ADC_REG_IRSR_RDY_RAW_SHIFT (0U)
+/*! rdy_raw - The corresponding flag will be captured into this register regardless the interrupt
+ * mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_RDY_RAW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_RDY_RAW_SHIFT)) & ADC_ADC_REG_IRSR_RDY_RAW_MASK)
+#define ADC_ADC_REG_IRSR_GAINSAT_RAW_MASK (0x2U)
+#define ADC_ADC_REG_IRSR_GAINSAT_RAW_SHIFT (1U)
+/*! gainsat_raw - The corresponding flag will be captured into this register regardless the
+ * interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_GAINSAT_RAW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_GAINSAT_RAW_SHIFT)) & ADC_ADC_REG_IRSR_GAINSAT_RAW_MASK)
+#define ADC_ADC_REG_IRSR_OFFSAT_RAW_MASK (0x4U)
+#define ADC_ADC_REG_IRSR_OFFSAT_RAW_SHIFT (2U)
+/*! offsat_raw - The corresponding flag will be captured into this register regardless the interrupt
+ * mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_OFFSAT_RAW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_OFFSAT_RAW_SHIFT)) & ADC_ADC_REG_IRSR_OFFSAT_RAW_MASK)
+#define ADC_ADC_REG_IRSR_DATASAT_NEG_RAW_MASK (0x8U)
+#define ADC_ADC_REG_IRSR_DATASAT_NEG_RAW_SHIFT (3U)
+/*! datasat_neg_raw - The corresponding flag will be captured into this register regardless the
+ * interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_DATASAT_NEG_RAW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_DATASAT_NEG_RAW_SHIFT)) & ADC_ADC_REG_IRSR_DATASAT_NEG_RAW_MASK)
+#define ADC_ADC_REG_IRSR_DATASAT_POS_RAW_MASK (0x10U)
+#define ADC_ADC_REG_IRSR_DATASAT_POS_RAW_SHIFT (4U)
+/*! datasat_pos_raw - The corresponding flag will be captured into this register regardless the
+ * interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_DATASAT_POS_RAW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_DATASAT_POS_RAW_SHIFT)) & ADC_ADC_REG_IRSR_DATASAT_POS_RAW_MASK)
+#define ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW_MASK (0x20U)
+#define ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW_SHIFT (5U)
+/*! fifo_overrun_raw - The corresponding flag will be captured into this register regardless the
+ * interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW_SHIFT)) & ADC_ADC_REG_IRSR_FIFO_OVERRUN_RAW_MASK)
+#define ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW_MASK (0x40U)
+#define ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW_SHIFT (6U)
+/*! fifo_underrun_raw - The corresponding flag will be captured into this register regardless the
+ * interrupt mask. Will be cleared only when int_clr is asserted.
+ */
+#define ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW_SHIFT)) & ADC_ADC_REG_IRSR_FIFO_UNDERRUN_RAW_MASK)
+/*! @} */
+
+/*! @name ADC_REG_ICR - */
+/*! @{ */
+#define ADC_ADC_REG_ICR_RDY_CLR_MASK (0x1U)
+#define ADC_ADC_REG_ICR_RDY_CLR_SHIFT (0U)
+/*! rdy_clr - Write 1 to clear both adc_reg_irsr and adc_reg_isr
+ */
+#define ADC_ADC_REG_ICR_RDY_CLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_RDY_CLR_SHIFT)) & ADC_ADC_REG_ICR_RDY_CLR_MASK)
+#define ADC_ADC_REG_ICR_GAINSAT_CLR_MASK (0x2U)
+#define ADC_ADC_REG_ICR_GAINSAT_CLR_SHIFT (1U)
+/*! gainsat_clr - Write 1 to clear both adc_reg_irsr and adc_reg_isr
+ */
+#define ADC_ADC_REG_ICR_GAINSAT_CLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_GAINSAT_CLR_SHIFT)) & ADC_ADC_REG_ICR_GAINSAT_CLR_MASK)
+#define ADC_ADC_REG_ICR_OFFSAT_CLR_MASK (0x4U)
+#define ADC_ADC_REG_ICR_OFFSAT_CLR_SHIFT (2U)
+/*! offsat_clr - Write 1 to clear both adc_reg_irsr and adc_reg_isr
+ */
+#define ADC_ADC_REG_ICR_OFFSAT_CLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_OFFSAT_CLR_SHIFT)) & ADC_ADC_REG_ICR_OFFSAT_CLR_MASK)
+#define ADC_ADC_REG_ICR_DATASAT_NEG_CLR_MASK (0x8U)
+#define ADC_ADC_REG_ICR_DATASAT_NEG_CLR_SHIFT (3U)
+/*! datasat_neg_clr - Write 1 to clear both adc_reg_irsr and adc_reg_isr
+ */
+#define ADC_ADC_REG_ICR_DATASAT_NEG_CLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_DATASAT_NEG_CLR_SHIFT)) & ADC_ADC_REG_ICR_DATASAT_NEG_CLR_MASK)
+#define ADC_ADC_REG_ICR_DATASAT_POS_CLR_MASK (0x10U)
+#define ADC_ADC_REG_ICR_DATASAT_POS_CLR_SHIFT (4U)
+/*! datasat_pos_clr - Write 1 to clear both adc_reg_irsr and adc_reg_isr
+ */
+#define ADC_ADC_REG_ICR_DATASAT_POS_CLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_DATASAT_POS_CLR_SHIFT)) & ADC_ADC_REG_ICR_DATASAT_POS_CLR_MASK)
+#define ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR_MASK (0x20U)
+#define ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR_SHIFT (5U)
+/*! fifo_overrun_clr - Write 1 to clear both adc_reg_irsr and adc_reg_isr
+ */
+#define ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR_SHIFT)) & ADC_ADC_REG_ICR_FIFO_OVERRUN_CLR_MASK)
+#define ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR_MASK (0x40U)
+#define ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR_SHIFT (6U)
+/*! fifo_underrun_clr - Write 1 to clear both adc_reg_irsr and adc_reg_isr
+ */
+#define ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR_SHIFT)) & ADC_ADC_REG_ICR_FIFO_UNDERRUN_CLR_MASK)
+/*! @} */
+
+/*! @name ADC_REG_RESULT - */
+/*! @{ */
+#define ADC_ADC_REG_RESULT_DATA_MASK (0xFFFFFFFFU)
+#define ADC_ADC_REG_RESULT_DATA_SHIFT (0U)
+/*! data - ADC finial conversion result data, after calibratiob and signed/unsigned process
+ */
+#define ADC_ADC_REG_RESULT_DATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_RESULT_DATA_SHIFT)) & ADC_ADC_REG_RESULT_DATA_MASK)
+/*! @} */
+
+/*! @name ADC_REG_RAW_RESULT - */
+/*! @{ */
+#define ADC_ADC_REG_RAW_RESULT_RAW_DATA_MASK (0x3FFFFFU)
+#define ADC_ADC_REG_RAW_RESULT_RAW_DATA_SHIFT (0U)
+/*! raw_data - ADC Raw data in signed 22bit format
+ */
+#define ADC_ADC_REG_RAW_RESULT_RAW_DATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_RAW_RESULT_RAW_DATA_SHIFT)) & ADC_ADC_REG_RAW_RESULT_RAW_DATA_MASK)
+/*! @} */
+
+/*! @name ADC_REG_OFFSET_CAL - */
+/*! @{ */
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_MASK (0xFFFFU)
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_SHIFT (0U)
+/*! offset_cal - ADC self offset calibration value. 16-bit signed .
+ */
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_SHIFT)) & ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_MASK)
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_MASK (0xFFFF0000U)
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_SHIFT (16U)
+/*! offset_cal_usr - User offset calibration data. 16-bit signed.
+ */
+#define ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_SHIFT)) & ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_MASK)
+/*! @} */
+
+/*! @name ADC_REG_GAIN_CAL - */
+/*! @{ */
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_MASK (0xFFFFU)
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_SHIFT (0U)
+/*! gain_cal - ADC self gain calibration value. 16-bit signed.
+ */
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GAIN_CAL_GAIN_CAL_SHIFT)) & ADC_ADC_REG_GAIN_CAL_GAIN_CAL_MASK)
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_MASK (0xFFFF0000U)
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_SHIFT (16U)
+/*! gain_cal_usr - ADC user gain calibration value. 16-bit signed.
+ */
+#define ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_SHIFT)) & ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_MASK)
+/*! @} */
+
+/*! @name ADC_REG_TEST - */
+/*! @{ */
+#define ADC_ADC_REG_TEST_TEST_EN_MASK (0x1U)
+#define ADC_ADC_REG_TEST_TEST_EN_SHIFT (0U)
+/*! test_en - Analog test enable.
+ * 0b0..disable analog test. adc_atest=Hi-Z
+ * 0b1..enable analog test
+ */
+#define ADC_ADC_REG_TEST_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_TEST_TEST_EN_SHIFT)) & ADC_ADC_REG_TEST_TEST_EN_MASK)
+#define ADC_ADC_REG_TEST_TEST_SEL_MASK (0xEU)
+#define ADC_ADC_REG_TEST_TEST_SEL_SHIFT (1U)
+#define ADC_ADC_REG_TEST_TEST_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_TEST_TEST_SEL_SHIFT)) & ADC_ADC_REG_TEST_TEST_SEL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_AUDIO - */
+/*! @{ */
+#define ADC_ADC_REG_AUDIO_EN_MASK (0x1U)
+#define ADC_ADC_REG_AUDIO_EN_SHIFT (0U)
+/*! en - Audio enable.
+ * 0b0..disable audio pga and decimation rate select
+ * 0b1..enable audio pga and decimation rate select
+ */
+#define ADC_ADC_REG_AUDIO_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_AUDIO_EN_SHIFT)) & ADC_ADC_REG_AUDIO_EN_MASK)
+#define ADC_ADC_REG_AUDIO_PGA_GAIN_MASK (0x38U)
+#define ADC_ADC_REG_AUDIO_PGA_GAIN_SHIFT (3U)
+/*! pga_gain - Audio PGA voltage gain select
+ */
+#define ADC_ADC_REG_AUDIO_PGA_GAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_AUDIO_PGA_GAIN_SHIFT)) & ADC_ADC_REG_AUDIO_PGA_GAIN_MASK)
+#define ADC_ADC_REG_AUDIO_PGA_CM_MASK (0x1C0U)
+#define ADC_ADC_REG_AUDIO_PGA_CM_SHIFT (6U)
+/*! pga_cm - Audio PGA output common mode control
+ * 0b000..common mode is 0.82V
+ * 0b001..common mode is 0.84V
+ * 0b010..common mode is 0.86V
+ * 0b011..common mode is 0.88V
+ * 0b100..common mode is 0.90V
+ * 0b101..common mode is 0.92V
+ * 0b110..common mode is 0.94V
+ * 0b111..common mode is 0.96V
+ */
+#define ADC_ADC_REG_AUDIO_PGA_CM(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_AUDIO_PGA_CM_SHIFT)) & ADC_ADC_REG_AUDIO_PGA_CM_MASK)
+#define ADC_ADC_REG_AUDIO_PGA_CHOP_EN_MASK (0x200U)
+#define ADC_ADC_REG_AUDIO_PGA_CHOP_EN_SHIFT (9U)
+/*! pga_chop_en - Audio PGA chopper enable.
+ * 0b0..disable audio pga chopper
+ * 0b1..enable audio pga chopper
+ */
+#define ADC_ADC_REG_AUDIO_PGA_CHOP_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_AUDIO_PGA_CHOP_EN_SHIFT)) & ADC_ADC_REG_AUDIO_PGA_CHOP_EN_MASK)
+/*! @} */
+
+/*! @name ADC_REG_VOICE_DET - */
+/*! @{ */
+#define ADC_ADC_REG_VOICE_DET_DET_EN_MASK (0x1U)
+#define ADC_ADC_REG_VOICE_DET_DET_EN_SHIFT (0U)
+/*! det_en - Voice level detection enable select
+ * 0b0..Disable level detection
+ * 0b1..Ensable level detection
+ */
+#define ADC_ADC_REG_VOICE_DET_DET_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_VOICE_DET_DET_EN_SHIFT)) & ADC_ADC_REG_VOICE_DET_DET_EN_MASK)
+#define ADC_ADC_REG_VOICE_DET_LEVEL_SEL_MASK (0xEU)
+#define ADC_ADC_REG_VOICE_DET_LEVEL_SEL_SHIFT (1U)
+/*! level_sel - Voice level selection.
+ */
+#define ADC_ADC_REG_VOICE_DET_LEVEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_VOICE_DET_LEVEL_SEL_SHIFT)) & ADC_ADC_REG_VOICE_DET_LEVEL_SEL_MASK)
+/*! @} */
+
+/*! @name ADC_REG_RSVD - */
+/*! @{ */
+#define ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS_MASK (0xFFFFU)
+#define ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS_SHIFT (0U)
+#define ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS_SHIFT)) & ADC_ADC_REG_RSVD_UNUSED_RESERVED_ADC_CONTROL_BITS_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC base address */
+#define ADC_BASE (0x460B0000u)
+/** Peripheral ADC base pointer */
+#define ADC ((ADC_Type *)ADC_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AES Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AES_Peripheral_Access_Layer AES Peripheral Access Layer
+ * @{
+ */
+
+/** AES - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL1; /**< AES Control Register 1, offset: 0x0 */
+ __IO uint32_t CTRL2; /**< AES Control Register 2, offset: 0x4 */
+ __I uint32_t STATUS; /**< AES Status Register, offset: 0x8 */
+ __IO uint32_t ASTR_LEN; /**< AES Astr Length Register, offset: 0xC */
+ __IO uint32_t MSTR_LEN; /**< AES Mstr Length Register, offset: 0x10 */
+ __O uint32_t STR_IN; /**< AES Stream Input Register, offset: 0x14 */
+ __IO uint32_t IV0; /**< AES Input Vector Register 0, offset: 0x18 */
+ __IO uint32_t IV1; /**< AES Input Vector Register 1, offset: 0x1C */
+ __IO uint32_t IV2; /**< AES Input Vector Register 2, offset: 0x20 */
+ __IO uint32_t IV3; /**< AES Input Vector Register 3, offset: 0x24 */
+ __IO uint32_t KEY0; /**< AES Key 0 Register, offset: 0x28 */
+ __IO uint32_t KEY1; /**< AES Key 1 Register, offset: 0x2C */
+ __IO uint32_t KEY2; /**< AES Key 2 Register, offset: 0x30 */
+ __IO uint32_t KEY3; /**< AES Key 3 Register, offset: 0x34 */
+ __IO uint32_t KEY4; /**< AES Key 4 Register, offset: 0x38 */
+ __IO uint32_t KEY5; /**< AES Key 5 Register, offset: 0x3C */
+ __IO uint32_t KEY6; /**< AES Key 6 Register, offset: 0x40 */
+ __IO uint32_t KEY7; /**< AES Key 7 Register, offset: 0x44 */
+ __I uint32_t STR_OUT; /**< AES Stream Output Port Register, offset: 0x48 */
+ __I uint32_t OV0; /**< AES Output Vector 0 Register, offset: 0x4C */
+ __I uint32_t OV1; /**< AES Output Vector 1 Register, offset: 0x50 */
+ __I uint32_t OV2; /**< AES Output Vector 2 Register, offset: 0x54 */
+ __I uint32_t OV3; /**< AES Output Vector 3 Register, offset: 0x58 */
+ __I uint32_t ISR; /**< AES Interrupt Status Register, offset: 0x5C */
+ __IO uint32_t IMR; /**< AES Interrupt Mask Register, offset: 0x60 */
+ __I uint32_t IRSR; /**< AES Interrupt Raw Status Register, offset: 0x64 */
+ __IO uint32_t ICR; /**< AES Interrupt Clear Register, offset: 0x68 */
+ uint8_t RESERVED_0[32];
+ __I uint32_t REV_ID; /**< AES Revision Register, offset: 0x8C */
+} AES_Type;
+
+/* ----------------------------------------------------------------------------
+ -- AES Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AES_Register_Masks AES Register Masks
+ * @{
+ */
+
+/*! @name CTRL1 - AES Control Register 1 */
+/*! @{ */
+#define AES_CTRL1_START_MASK (0x1U)
+#define AES_CTRL1_START_SHIFT (0U)
+/*! start - Start AES
+ */
+#define AES_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_START_SHIFT)) & AES_CTRL1_START_MASK)
+#define AES_CTRL1_LOCK0_MASK (0x2U)
+#define AES_CTRL1_LOCK0_SHIFT (1U)
+/*! lock0 - Lock AES on MCU side
+ * 0b0..Write 0 to release AES
+ * 0b1..Write 1 to lock AES on behalf of MCU
+ */
+#define AES_CTRL1_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_LOCK0_SHIFT)) & AES_CTRL1_LOCK0_MASK)
+#define AES_CTRL1_IF_CLR_MASK (0x4U)
+#define AES_CTRL1_IF_CLR_SHIFT (2U)
+/*! if_clr - Clear input FIFO
+ */
+#define AES_CTRL1_IF_CLR(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_IF_CLR_SHIFT)) & AES_CTRL1_IF_CLR_MASK)
+#define AES_CTRL1_OF_CLR_MASK (0x8U)
+#define AES_CTRL1_OF_CLR_SHIFT (3U)
+/*! of_clr - Clear output FIFO
+ */
+#define AES_CTRL1_OF_CLR(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_OF_CLR_SHIFT)) & AES_CTRL1_OF_CLR_MASK)
+#define AES_CTRL1_OUT_MSG_MASK (0x10U)
+#define AES_CTRL1_OUT_MSG_SHIFT (4U)
+/*! out_msg - Output stream to output FIFO
+ * 0b0..block output stream from output FIFO
+ * 0b1..forward output stream to output FIFO
+ */
+#define AES_CTRL1_OUT_MSG(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_OUT_MSG_SHIFT)) & AES_CTRL1_OUT_MSG_MASK)
+#define AES_CTRL1_OUT_HDR_MASK (0x20U)
+#define AES_CTRL1_OUT_HDR_SHIFT (5U)
+/*! out_hdr - Output B0 and l(a) in CCM* mode
+ * 0b0..do not output B0 and l(a) at the beginning of output stream
+ * 0b1..output B0 and l(a) at the beginning of output stream
+ */
+#define AES_CTRL1_OUT_HDR(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_OUT_HDR_SHIFT)) & AES_CTRL1_OUT_HDR_MASK)
+#define AES_CTRL1_PRI0_MASK (0x40U)
+#define AES_CTRL1_PRI0_SHIFT (6U)
+/*! pri0 - AES priority on MCU (software) side
+ * 0b0..Low priority
+ * 0b1..High priority
+ */
+#define AES_CTRL1_PRI0(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_PRI0_SHIFT)) & AES_CTRL1_PRI0_MASK)
+#define AES_CTRL1_PRI1_MASK (0x80U)
+#define AES_CTRL1_PRI1_SHIFT (7U)
+/*! pri1 - AES priority on hardware (BH-MAC) side
+ * 0b0..Low priority
+ * 0b1..High priority
+ */
+#define AES_CTRL1_PRI1(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_PRI1_SHIFT)) & AES_CTRL1_PRI1_MASK)
+#define AES_CTRL1_IO_SRC_MASK (0x100U)
+#define AES_CTRL1_IO_SRC_SHIFT (8U)
+/*! io_src - AES data input source
+ * 0b0..I/O through register
+ * 0b1..I/O through DMA
+ */
+#define AES_CTRL1_IO_SRC(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_IO_SRC_SHIFT)) & AES_CTRL1_IO_SRC_MASK)
+#define AES_CTRL1_DMA_EN_MASK (0x200U)
+#define AES_CTRL1_DMA_EN_SHIFT (9U)
+/*! dma_en - Enable DMA
+ * 0b0..Disable DMA
+ * 0b1..Enable DMA
+ */
+#define AES_CTRL1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_DMA_EN_SHIFT)) & AES_CTRL1_DMA_EN_MASK)
+#define AES_CTRL1_KEY_SIZE_MASK (0xC00U)
+#define AES_CTRL1_KEY_SIZE_SHIFT (10U)
+/*! key_size - Key size parameter
+ * 0b00..16 bytes
+ * 0b01..32 bytes
+ * 0b10..24 bytes
+ * 0b11..reserved
+ */
+#define AES_CTRL1_KEY_SIZE(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_KEY_SIZE_SHIFT)) & AES_CTRL1_KEY_SIZE_MASK)
+#define AES_CTRL1_MIC_LEN_MASK (0x3000U)
+#define AES_CTRL1_MIC_LEN_SHIFT (12U)
+/*! mic_len - Length of MIC field
+ * 0b00..0 bytes
+ * 0b01..4 bytes
+ * 0b10..8 bytes
+ * 0b11..16 bytes
+ */
+#define AES_CTRL1_MIC_LEN(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_MIC_LEN_SHIFT)) & AES_CTRL1_MIC_LEN_MASK)
+#define AES_CTRL1_OUT_MIC_MASK (0x4000U)
+#define AES_CTRL1_OUT_MIC_SHIFT (14U)
+/*! out_mic - Append MIC/HASH at the end of output stream in CCM* mode
+ * 0b0..Not append MIC/HASH at the end of output stream in CCM* mode decryption or MMO mode
+ * 0b1..Append MIC/HASH at the end of output stream in CCM* mode decryption or MMO mode
+ */
+#define AES_CTRL1_OUT_MIC(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_OUT_MIC_SHIFT)) & AES_CTRL1_OUT_MIC_MASK)
+#define AES_CTRL1_DECRYPT_MASK (0x8000U)
+#define AES_CTRL1_DECRYPT_SHIFT (15U)
+/*! decrypt - Decrypt operation (ignored in MMO and BYPASS mode)
+ * 0b0..
+ * 0b1..
+ */
+#define AES_CTRL1_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_DECRYPT_SHIFT)) & AES_CTRL1_DECRYPT_MASK)
+#define AES_CTRL1_MODE_MASK (0x70000U)
+#define AES_CTRL1_MODE_SHIFT (16U)
+/*! mode - AES running mode
+ * 0b000..
+ * 0b001..
+ * 0b010..
+ * 0b011..RESERVED
+ * 0b100..RESERVED
+ * 0b101..CCM*
+ * 0b110..
+ * 0b111..
+ */
+#define AES_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_MODE_SHIFT)) & AES_CTRL1_MODE_MASK)
+#define AES_CTRL1_CTR_MOD_MASK (0x3F80000U)
+#define AES_CTRL1_CTR_MOD_SHIFT (19U)
+/*! ctr_mod - CTR mode's counter modular
+ */
+#define AES_CTRL1_CTR_MOD(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_CTR_MOD_SHIFT)) & AES_CTRL1_CTR_MOD_MASK)
+#define AES_CTRL1_CTS_MODE_MASK (0x4000000U)
+#define AES_CTRL1_CTS_MODE_SHIFT (26U)
+/*! cts_mode - Cipher stealing mode of CBC
+ * 0b0..Marvell mode
+ * 0b1..NIST-CS2 mode
+ */
+#define AES_CTRL1_CTS_MODE(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL1_CTS_MODE_SHIFT)) & AES_CTRL1_CTS_MODE_MASK)
+/*! @} */
+
+/*! @name CTRL2 - AES Control Register 2 */
+/*! @{ */
+#define AES_CTRL2_AES_RESET_MASK (0x1U)
+#define AES_CTRL2_AES_RESET_SHIFT (0U)
+/*! aes_reset - Reset AES
+ * 0b0..un-reset AES
+ * 0b1..Reset AES
+ */
+#define AES_CTRL2_AES_RESET(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL2_AES_RESET_SHIFT)) & AES_CTRL2_AES_RESET_MASK)
+#define AES_CTRL2_AUTO_RESET_EN_MASK (0x2U)
+#define AES_CTRL2_AUTO_RESET_EN_SHIFT (1U)
+/*! auto_reset_en - Enable atutomatic reset after lock successfully
+ * 0b0..No automatic reset
+ * 0b1..Automatic reset after lock successfully
+ */
+#define AES_CTRL2_AUTO_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << AES_CTRL2_AUTO_RESET_EN_SHIFT)) & AES_CTRL2_AUTO_RESET_EN_MASK)
+/*! @} */
+
+/*! @name STATUS - AES Status Register */
+/*! @{ */
+#define AES_STATUS_DONE_MASK (0x1U)
+#define AES_STATUS_DONE_SHIFT (0U)
+/*! done - AES operation done
+ * 0b0..AES operation has not done yet
+ * 0b1..AES operation done
+ */
+#define AES_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_DONE_SHIFT)) & AES_STATUS_DONE_MASK)
+#define AES_STATUS_RSVD0_MASK (0x2U)
+#define AES_STATUS_RSVD0_SHIFT (1U)
+/*! rsvd0 - AES is locked by MCU
+ * 0b0..AES is not locked by MCU
+ * 0b1..AES is locked by MCU
+ */
+#define AES_STATUS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_RSVD0_SHIFT)) & AES_STATUS_RSVD0_MASK)
+#define AES_STATUS_RSVD1_MASK (0x4U)
+#define AES_STATUS_RSVD1_SHIFT (2U)
+/*! rsvd1 - AES is locked by hardware (BH-MAC)
+ * 0b0..AES is not locked by hardware
+ * 0b1..AES is locked by hardware
+ */
+#define AES_STATUS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_RSVD1_SHIFT)) & AES_STATUS_RSVD1_MASK)
+#define AES_STATUS_LOCK1_MASK (0x8U)
+#define AES_STATUS_LOCK1_SHIFT (3U)
+/*! lock1 - Lock AES on hardware (BH-MAC) side
+ * 0b0..hardware unlocks AES
+ * 0b1..hardware requests to lock AES
+ */
+#define AES_STATUS_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_LOCK1_SHIFT)) & AES_STATUS_LOCK1_MASK)
+#define AES_STATUS_IF_FULL_MASK (0x10U)
+#define AES_STATUS_IF_FULL_SHIFT (4U)
+/*! if_full - Input FIFO full
+ * 0b0..Input FIFO is not full
+ * 0b1..Input FIFO is full
+ */
+#define AES_STATUS_IF_FULL(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_IF_FULL_SHIFT)) & AES_STATUS_IF_FULL_MASK)
+#define AES_STATUS_OF_RDY_MASK (0x40U)
+#define AES_STATUS_OF_RDY_SHIFT (6U)
+/*! of_rdy - Output FIFO is ready to read
+ * 0b0..Output FIFO is not ready to read
+ * 0b1..Output FIFO is ready to read
+ */
+#define AES_STATUS_OF_RDY(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_OF_RDY_SHIFT)) & AES_STATUS_OF_RDY_MASK)
+#define AES_STATUS_OF_EMPTY_MASK (0x80U)
+#define AES_STATUS_OF_EMPTY_SHIFT (7U)
+/*! of_empty - Output FIFO empty
+ * 0b0..Output FIFO is not empty
+ * 0b1..Output FIFO is empty
+ */
+#define AES_STATUS_OF_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_OF_EMPTY_SHIFT)) & AES_STATUS_OF_EMPTY_MASK)
+#define AES_STATUS_STATUS_MASK (0x3800U)
+#define AES_STATUS_STATUS_SHIFT (11U)
+/*! status - AES operation error status
+ * 0b000..No operation error
+ * 0b001..Input stream size less than 16 byte in ECB,CBC and CTR mode
+ * 0b010..Data is not multiple of 16 bytes in ECB mode or Data is more than 2^13-1 bytes in MMO mode
+ * 0b011..Data is not multiple of 16 bytes and less than 16 byte in ECB mode
+ * 0b100..MIC Mismatch during CCM* Decryption
+ */
+#define AES_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_STATUS_SHIFT)) & AES_STATUS_STATUS_MASK)
+#define AES_STATUS_IF_DEPTH_MASK (0x1C000U)
+#define AES_STATUS_IF_DEPTH_SHIFT (14U)
+/*! if_depth - input FIFO depth
+ */
+#define AES_STATUS_IF_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_IF_DEPTH_SHIFT)) & AES_STATUS_IF_DEPTH_MASK)
+#define AES_STATUS_OF_DEPTH_MASK (0xE0000U)
+#define AES_STATUS_OF_DEPTH_SHIFT (17U)
+/*! of_depth - output FIFO depth
+ */
+#define AES_STATUS_OF_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_OF_DEPTH_SHIFT)) & AES_STATUS_OF_DEPTH_MASK)
+#define AES_STATUS_RSVD_VLD_MASK (0x100000U)
+#define AES_STATUS_RSVD_VLD_SHIFT (20U)
+/*! rsvd_vld - RSVD Valid
+ * 0b0..rsvd0 and rsvd1 not valid
+ * 0b1..rsvd0 and rsvd1 are valid
+ */
+#define AES_STATUS_RSVD_VLD(x) (((uint32_t)(((uint32_t)(x)) << AES_STATUS_RSVD_VLD_SHIFT)) & AES_STATUS_RSVD_VLD_MASK)
+/*! @} */
+
+/*! @name ASTR_LEN - AES Astr Length Register */
+/*! @{ */
+#define AES_ASTR_LEN_ASTR_LEN_MASK (0xFFFFFFFFU)
+#define AES_ASTR_LEN_ASTR_LEN_SHIFT (0U)
+/*! astr_len - Size of associate string
+ */
+#define AES_ASTR_LEN_ASTR_LEN(x) (((uint32_t)(((uint32_t)(x)) << AES_ASTR_LEN_ASTR_LEN_SHIFT)) & AES_ASTR_LEN_ASTR_LEN_MASK)
+/*! @} */
+
+/*! @name MSTR_LEN - AES Mstr Length Register */
+/*! @{ */
+#define AES_MSTR_LEN_MSTR_LEN_MASK (0xFFFFFFFFU)
+#define AES_MSTR_LEN_MSTR_LEN_SHIFT (0U)
+/*! mstr_len - Size of message string
+ */
+#define AES_MSTR_LEN_MSTR_LEN(x) (((uint32_t)(((uint32_t)(x)) << AES_MSTR_LEN_MSTR_LEN_SHIFT)) & AES_MSTR_LEN_MSTR_LEN_MASK)
+/*! @} */
+
+/*! @name STR_IN - AES Stream Input Register */
+/*! @{ */
+#define AES_STR_IN_STR_IN_MASK (0xFFFFFFFFU)
+#define AES_STR_IN_STR_IN_SHIFT (0U)
+/*! str_in - Input message word
+ */
+#define AES_STR_IN_STR_IN(x) (((uint32_t)(((uint32_t)(x)) << AES_STR_IN_STR_IN_SHIFT)) & AES_STR_IN_STR_IN_MASK)
+/*! @} */
+
+/*! @name IV0 - AES Input Vector Register 0 */
+/*! @{ */
+#define AES_IV0_IV0_MASK (0xFFFFFFFFU)
+#define AES_IV0_IV0_SHIFT (0U)
+/*! iv0 - Byte 0-3 of initial vector
+ */
+#define AES_IV0_IV0(x) (((uint32_t)(((uint32_t)(x)) << AES_IV0_IV0_SHIFT)) & AES_IV0_IV0_MASK)
+/*! @} */
+
+/*! @name IV1 - AES Input Vector Register 1 */
+/*! @{ */
+#define AES_IV1_IV1_MASK (0xFFFFFFFFU)
+#define AES_IV1_IV1_SHIFT (0U)
+/*! iv1 - Byte 4-7 of initial vector
+ */
+#define AES_IV1_IV1(x) (((uint32_t)(((uint32_t)(x)) << AES_IV1_IV1_SHIFT)) & AES_IV1_IV1_MASK)
+/*! @} */
+
+/*! @name IV2 - AES Input Vector Register 2 */
+/*! @{ */
+#define AES_IV2_IV2_MASK (0xFFFFFFFFU)
+#define AES_IV2_IV2_SHIFT (0U)
+/*! iv2 - Byte 8-11 of initial vector
+ */
+#define AES_IV2_IV2(x) (((uint32_t)(((uint32_t)(x)) << AES_IV2_IV2_SHIFT)) & AES_IV2_IV2_MASK)
+/*! @} */
+
+/*! @name IV3 - AES Input Vector Register 3 */
+/*! @{ */
+#define AES_IV3_IV3_MASK (0xFFFFFFFFU)
+#define AES_IV3_IV3_SHIFT (0U)
+/*! iv3 - Byte 12-15 of initial vector
+ */
+#define AES_IV3_IV3(x) (((uint32_t)(((uint32_t)(x)) << AES_IV3_IV3_SHIFT)) & AES_IV3_IV3_MASK)
+/*! @} */
+
+/*! @name KEY0 - AES Key 0 Register */
+/*! @{ */
+#define AES_KEY0_KEY0_MASK (0xFFFFFFFFU)
+#define AES_KEY0_KEY0_SHIFT (0U)
+/*! key0 - Byte 0-3 of key
+ */
+#define AES_KEY0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY0_KEY0_SHIFT)) & AES_KEY0_KEY0_MASK)
+/*! @} */
+
+/*! @name KEY1 - AES Key 1 Register */
+/*! @{ */
+#define AES_KEY1_KEY1_MASK (0xFFFFFFFFU)
+#define AES_KEY1_KEY1_SHIFT (0U)
+/*! key1 - Byte 4-7 of key
+ */
+#define AES_KEY1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY1_KEY1_SHIFT)) & AES_KEY1_KEY1_MASK)
+/*! @} */
+
+/*! @name KEY2 - AES Key 2 Register */
+/*! @{ */
+#define AES_KEY2_KEY2_MASK (0xFFFFFFFFU)
+#define AES_KEY2_KEY2_SHIFT (0U)
+/*! key2 - Byte 8-11 of key
+ */
+#define AES_KEY2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY2_KEY2_SHIFT)) & AES_KEY2_KEY2_MASK)
+/*! @} */
+
+/*! @name KEY3 - AES Key 3 Register */
+/*! @{ */
+#define AES_KEY3_KEY3_MASK (0xFFFFFFFFU)
+#define AES_KEY3_KEY3_SHIFT (0U)
+/*! key3 - Byte 12-15 of key
+ */
+#define AES_KEY3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY3_KEY3_SHIFT)) & AES_KEY3_KEY3_MASK)
+/*! @} */
+
+/*! @name KEY4 - AES Key 4 Register */
+/*! @{ */
+#define AES_KEY4_KEY4_MASK (0xFFFFFFFFU)
+#define AES_KEY4_KEY4_SHIFT (0U)
+/*! key4 - Byte 16-19 of key
+ */
+#define AES_KEY4_KEY4(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY4_KEY4_SHIFT)) & AES_KEY4_KEY4_MASK)
+/*! @} */
+
+/*! @name KEY5 - AES Key 5 Register */
+/*! @{ */
+#define AES_KEY5_KEY5_MASK (0xFFFFFFFFU)
+#define AES_KEY5_KEY5_SHIFT (0U)
+/*! key5 - Byte 20-23 of key
+ */
+#define AES_KEY5_KEY5(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY5_KEY5_SHIFT)) & AES_KEY5_KEY5_MASK)
+/*! @} */
+
+/*! @name KEY6 - AES Key 6 Register */
+/*! @{ */
+#define AES_KEY6_KEY6_MASK (0xFFFFFFFFU)
+#define AES_KEY6_KEY6_SHIFT (0U)
+/*! key6 - Byte 24-27 of key
+ */
+#define AES_KEY6_KEY6(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY6_KEY6_SHIFT)) & AES_KEY6_KEY6_MASK)
+/*! @} */
+
+/*! @name KEY7 - AES Key 7 Register */
+/*! @{ */
+#define AES_KEY7_KEY7_MASK (0xFFFFFFFFU)
+#define AES_KEY7_KEY7_SHIFT (0U)
+/*! key7 - Byte 28-31 of key
+ */
+#define AES_KEY7_KEY7(x) (((uint32_t)(((uint32_t)(x)) << AES_KEY7_KEY7_SHIFT)) & AES_KEY7_KEY7_MASK)
+/*! @} */
+
+/*! @name STR_OUT - AES Stream Output Port Register */
+/*! @{ */
+#define AES_STR_OUT_STR_OUT_MASK (0xFFFFFFFFU)
+#define AES_STR_OUT_STR_OUT_SHIFT (0U)
+/*! str_out - Output message word
+ */
+#define AES_STR_OUT_STR_OUT(x) (((uint32_t)(((uint32_t)(x)) << AES_STR_OUT_STR_OUT_SHIFT)) & AES_STR_OUT_STR_OUT_MASK)
+/*! @} */
+
+/*! @name OV0 - AES Output Vector 0 Register */
+/*! @{ */
+#define AES_OV0_OV0_MASK (0xFFFFFFFFU)
+#define AES_OV0_OV0_SHIFT (0U)
+/*! ov0 - Byte 0-3 of output vector
+ */
+#define AES_OV0_OV0(x) (((uint32_t)(((uint32_t)(x)) << AES_OV0_OV0_SHIFT)) & AES_OV0_OV0_MASK)
+/*! @} */
+
+/*! @name OV1 - AES Output Vector 1 Register */
+/*! @{ */
+#define AES_OV1_OV1_MASK (0xFFFFFFFFU)
+#define AES_OV1_OV1_SHIFT (0U)
+/*! ov1 - Byte 4-7 of output vector
+ */
+#define AES_OV1_OV1(x) (((uint32_t)(((uint32_t)(x)) << AES_OV1_OV1_SHIFT)) & AES_OV1_OV1_MASK)
+/*! @} */
+
+/*! @name OV2 - AES Output Vector 2 Register */
+/*! @{ */
+#define AES_OV2_OV2_MASK (0xFFFFFFFFU)
+#define AES_OV2_OV2_SHIFT (0U)
+/*! ov2 - Byte 8-11 of output vector
+ */
+#define AES_OV2_OV2(x) (((uint32_t)(((uint32_t)(x)) << AES_OV2_OV2_SHIFT)) & AES_OV2_OV2_MASK)
+/*! @} */
+
+/*! @name OV3 - AES Output Vector 3 Register */
+/*! @{ */
+#define AES_OV3_OV3_MASK (0xFFFFFFFFU)
+#define AES_OV3_OV3_SHIFT (0U)
+/*! ov3 - Byte 12-15 of output vector
+ */
+#define AES_OV3_OV3(x) (((uint32_t)(((uint32_t)(x)) << AES_OV3_OV3_SHIFT)) & AES_OV3_OV3_MASK)
+/*! @} */
+
+/*! @name ISR - AES Interrupt Status Register */
+/*! @{ */
+#define AES_ISR_STATUS_0_MASK (0x1U)
+#define AES_ISR_STATUS_0_SHIFT (0U)
+/*! status_0 - Status of AES output FIFO empty interrupt
+ * 0b0..AES operation done interrupt not occurred
+ * 0b1..AES operation done interrupt occurred
+ */
+#define AES_ISR_STATUS_0(x) (((uint32_t)(((uint32_t)(x)) << AES_ISR_STATUS_0_SHIFT)) & AES_ISR_STATUS_0_MASK)
+#define AES_ISR_STATUS_1_MASK (0x2U)
+#define AES_ISR_STATUS_1_SHIFT (1U)
+/*! status_1 - Status of AES input FIFO full interrupt
+ * 0b0..AES input FIFO full interrupt not occurred
+ * 0b1..AES input FIFO full interrupt occurred
+ */
+#define AES_ISR_STATUS_1(x) (((uint32_t)(((uint32_t)(x)) << AES_ISR_STATUS_1_SHIFT)) & AES_ISR_STATUS_1_MASK)
+#define AES_ISR_STATUS_2_MASK (0x4U)
+#define AES_ISR_STATUS_2_SHIFT (2U)
+/*! status_2 - Status of AES output FIFO empty interrupt
+ * 0b0..AES output FIFO empty interrupt not occurred
+ * 0b1..AES output FIFO empty interrupt occurred
+ */
+#define AES_ISR_STATUS_2(x) (((uint32_t)(((uint32_t)(x)) << AES_ISR_STATUS_2_SHIFT)) & AES_ISR_STATUS_2_MASK)
+/*! @} */
+
+/*! @name IMR - AES Interrupt Mask Register */
+/*! @{ */
+#define AES_IMR_MASK_0_MASK (0x1U)
+#define AES_IMR_MASK_0_SHIFT (0U)
+/*! mask_0 - mask[0]: Mask of AES operation done interrupt
+ * 0b0..Enable AES operation done interrupt
+ * 0b1..Disable AES operation done interrupt
+ */
+#define AES_IMR_MASK_0(x) (((uint32_t)(((uint32_t)(x)) << AES_IMR_MASK_0_SHIFT)) & AES_IMR_MASK_0_MASK)
+#define AES_IMR_MASK_1_MASK (0x2U)
+#define AES_IMR_MASK_1_SHIFT (1U)
+/*! mask_1 - Mask of AES input FIFO full interrupt
+ * 0b0..Enable AES input FIFO full interrupt
+ * 0b1..Disable AES input FIFO full interrupt
+ */
+#define AES_IMR_MASK_1(x) (((uint32_t)(((uint32_t)(x)) << AES_IMR_MASK_1_SHIFT)) & AES_IMR_MASK_1_MASK)
+#define AES_IMR_MASK_2_MASK (0x4U)
+#define AES_IMR_MASK_2_SHIFT (2U)
+/*! mask_2 - Mask of AES output FIFO empty interrupt
+ * 0b0..Enable AES output FIFO empty interrupt
+ * 0b1..Disable AES output FIFO empty interrupt
+ */
+#define AES_IMR_MASK_2(x) (((uint32_t)(((uint32_t)(x)) << AES_IMR_MASK_2_SHIFT)) & AES_IMR_MASK_2_MASK)
+/*! @} */
+
+/*! @name IRSR - AES Interrupt Raw Status Register */
+/*! @{ */
+#define AES_IRSR_STATUS_RAW_0_MASK (0x1U)
+#define AES_IRSR_STATUS_RAW_0_SHIFT (0U)
+/*! status_raw_0 - AES operation done interrupt raw status regardless of mask
+ * 0b0..AES operation done interrupt not occurred
+ * 0b1..AES operation done interrupt occurred
+ */
+#define AES_IRSR_STATUS_RAW_0(x) (((uint32_t)(((uint32_t)(x)) << AES_IRSR_STATUS_RAW_0_SHIFT)) & AES_IRSR_STATUS_RAW_0_MASK)
+#define AES_IRSR_STATUS_RAW_1_MASK (0x2U)
+#define AES_IRSR_STATUS_RAW_1_SHIFT (1U)
+/*! status_raw_1 - AES input FIFO full interrupt raw status regardless of mask
+ * 0b0..AES no input FIFO full interrupt not occurred
+ * 0b1..AES no input FIFO full interrupt occurred
+ */
+#define AES_IRSR_STATUS_RAW_1(x) (((uint32_t)(((uint32_t)(x)) << AES_IRSR_STATUS_RAW_1_SHIFT)) & AES_IRSR_STATUS_RAW_1_MASK)
+#define AES_IRSR_STATUS_RAW_2_MASK (0x4U)
+#define AES_IRSR_STATUS_RAW_2_SHIFT (2U)
+/*! status_raw_2 - AES output FIFO empty interrupt raw status regardless of mask
+ * 0b0..AES output FIFO empty interrupt not occurred
+ * 0b1..AES output FIFO empty interrupt
+ */
+#define AES_IRSR_STATUS_RAW_2(x) (((uint32_t)(((uint32_t)(x)) << AES_IRSR_STATUS_RAW_2_SHIFT)) & AES_IRSR_STATUS_RAW_2_MASK)
+/*! @} */
+
+/*! @name ICR - AES Interrupt Clear Register */
+/*! @{ */
+#define AES_ICR_CLEAR_0_MASK (0x1U)
+#define AES_ICR_CLEAR_0_SHIFT (0U)
+/*! clear_0 - Clearance of AES operation done interrupt status and raw status
+ */
+#define AES_ICR_CLEAR_0(x) (((uint32_t)(((uint32_t)(x)) << AES_ICR_CLEAR_0_SHIFT)) & AES_ICR_CLEAR_0_MASK)
+#define AES_ICR_CLEAR_1_MASK (0x2U)
+#define AES_ICR_CLEAR_1_SHIFT (1U)
+/*! clear_1 - Clearance of AES input FIFO full interrupt status and raw status
+ */
+#define AES_ICR_CLEAR_1(x) (((uint32_t)(((uint32_t)(x)) << AES_ICR_CLEAR_1_SHIFT)) & AES_ICR_CLEAR_1_MASK)
+#define AES_ICR_CLEAR_2_MASK (0x4U)
+#define AES_ICR_CLEAR_2_SHIFT (2U)
+/*! clear_2 - Clearance of AES output FIFO empty interrupt status and raw status
+ */
+#define AES_ICR_CLEAR_2(x) (((uint32_t)(((uint32_t)(x)) << AES_ICR_CLEAR_2_SHIFT)) & AES_ICR_CLEAR_2_MASK)
+/*! @} */
+
+/*! @name REV_ID - AES Revision Register */
+/*! @{ */
+#define AES_REV_ID_MINOR_REV_ID_MASK (0xFU)
+#define AES_REV_ID_MINOR_REV_ID_SHIFT (0U)
+/*! minor_rev_id - Minor revision ID
+ */
+#define AES_REV_ID_MINOR_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << AES_REV_ID_MINOR_REV_ID_SHIFT)) & AES_REV_ID_MINOR_REV_ID_MASK)
+#define AES_REV_ID_MAJOR_REV_ID_MASK (0xF0U)
+#define AES_REV_ID_MAJOR_REV_ID_SHIFT (4U)
+/*! major_rev_id - Major revision ID
+ */
+#define AES_REV_ID_MAJOR_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << AES_REV_ID_MAJOR_REV_ID_SHIFT)) & AES_REV_ID_MAJOR_REV_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AES_Register_Masks */
+
+
+/* AES - Peripheral instance base addresses */
+/** Peripheral AES base address */
+#define AES_BASE (0x44004000u)
+/** Peripheral AES base pointer */
+#define AES ((AES_Type *)AES_BASE)
+/** Array initializer of AES peripheral base addresses */
+#define AES_BASE_ADDRS { AES_BASE }
+/** Array initializer of AES peripheral base pointers */
+#define AES_BASE_PTRS { AES }
+/** Interrupt vectors for the AES peripheral type */
+#define AES_IRQS { AES_IRQn }
+
+/*!
+ * @}
+ */ /* end of group AES_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- BG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BG_Peripheral_Access_Layer BG Peripheral Access Layer
+ * @{
+ */
+
+/** BG - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */
+ __I uint32_t STATUS; /**< Status Register, offset: 0x4 */
+} BG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- BG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BG_Register_Masks BG Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define BG_CTRL_PD_MASK (0x1U)
+#define BG_CTRL_PD_SHIFT (0U)
+/*! pd - Bandgap power down.
+ * 0b0..Power up
+ * 0b1..Power down
+ */
+#define BG_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << BG_CTRL_PD_SHIFT)) & BG_CTRL_PD_MASK)
+#define BG_CTRL_RES_TRIM_MASK (0xF0U)
+#define BG_CTRL_RES_TRIM_SHIFT (4U)
+/*! res_trim - 1.2V voltage reference resistor trim.
+ * 0b0000..1.159V
+ * 0b0001..1.163V
+ * 0b0010..1.168V
+ * 0b0011..1.172V
+ * 0b0100..1.177V
+ * 0b0101..1.181V
+ * 0b0110..1.186V
+ * 0b0111..1.190V
+ * 0b1000..1.194V
+ * 0b1001..1.199V
+ * 0b1010..1.204V
+ * 0b1011..1.208V
+ * 0b1100..1.213V
+ * 0b1101..1.217V
+ * 0b1110..1.222V
+ * 0b1111..1.226V
+ */
+#define BG_CTRL_RES_TRIM(x) (((uint32_t)(((uint32_t)(x)) << BG_CTRL_RES_TRIM_SHIFT)) & BG_CTRL_RES_TRIM_MASK)
+/*! @} */
+
+/*! @name STATUS - Status Register */
+/*! @{ */
+#define BG_STATUS_RDY_MASK (0x1U)
+#define BG_STATUS_RDY_SHIFT (0U)
+/*! rdy - 1'b1 indicates BG ready flag.
+ */
+#define BG_STATUS_RDY(x) (((uint32_t)(((uint32_t)(x)) << BG_STATUS_RDY_SHIFT)) & BG_STATUS_RDY_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BG_Register_Masks */
+
+
+/* BG - Peripheral instance base addresses */
+/** Peripheral BG base address */
+#define BG_BASE (0x460B0700u)
+/** Peripheral BG base pointer */
+#define BG ((BG_Type *)BG_BASE)
+/** Array initializer of BG peripheral base addresses */
+#define BG_BASE_ADDRS { BG_BASE }
+/** Array initializer of BG peripheral base pointers */
+#define BG_BASE_PTRS { BG }
+
+/*!
+ * @}
+ */ /* end of group BG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ISR; /**< Interrupt Status Register, offset: 0x0 */
+ __I uint32_t IRSR; /**< Interrupt Raw Status Register, offset: 0x4 */
+ __O uint32_t ICR; /**< Interrupt Clear Register, offset: 0x8 */
+ __IO uint32_t IMR; /**< Interrupt Mask Register, offset: 0xC */
+ __IO uint32_t CTRL; /**< CRC Module Control Register, offset: 0x10 */
+ __IO uint32_t STREAM_LEN_M1; /**< Stream Length Minus 1 Register, offset: 0x14 */
+ __IO uint32_t STREAM_IN; /**< Stream Input Register, offset: 0x18 */
+ __I uint32_t RESULT; /**< CRC Calculation Result Register, offset: 0x1C */
+ uint8_t RESERVED_0[28];
+ __I uint32_t REV_ID; /**< CRC Revision ID register, offset: 0x3C */
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name ISR - Interrupt Status Register */
+/*! @{ */
+#define CRC_ISR_STATUS_MASK (0x1U)
+#define CRC_ISR_STATUS_SHIFT (0U)
+/*! status - CRC calculation interrupt status after mask
+ * 0b0..interrupt is not occurred
+ * 0b1..interrupt is occurred
+ */
+#define CRC_ISR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CRC_ISR_STATUS_SHIFT)) & CRC_ISR_STATUS_MASK)
+/*! @} */
+
+/*! @name IRSR - Interrupt Raw Status Register */
+/*! @{ */
+#define CRC_IRSR_STATUS_RAW_0_MASK (0x1U)
+#define CRC_IRSR_STATUS_RAW_0_SHIFT (0U)
+/*! status_raw_0 - Raw status of IRQ regardless of mask
+ */
+#define CRC_IRSR_STATUS_RAW_0(x) (((uint32_t)(((uint32_t)(x)) << CRC_IRSR_STATUS_RAW_0_SHIFT)) & CRC_IRSR_STATUS_RAW_0_MASK)
+/*! @} */
+
+/*! @name ICR - Interrupt Clear Register */
+/*! @{ */
+#define CRC_ICR_CLEAR_MASK (0x1U)
+#define CRC_ICR_CLEAR_SHIFT (0U)
+/*! clear - Clearance of status[0] and status_raw[0]
+ */
+#define CRC_ICR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << CRC_ICR_CLEAR_SHIFT)) & CRC_ICR_CLEAR_MASK)
+/*! @} */
+
+/*! @name IMR - Interrupt Mask Register */
+/*! @{ */
+#define CRC_IMR_MASK_MASK (0x1U)
+#define CRC_IMR_MASK_SHIFT (0U)
+/*! mask - Mask of interrupt
+ * 0b0..enable generation of IRQ and corresponding status[0]
+ * 0b1..disable generation of IRQ and corresponding status[0]
+ */
+#define CRC_IMR_MASK(x) (((uint32_t)(((uint32_t)(x)) << CRC_IMR_MASK_SHIFT)) & CRC_IMR_MASK_MASK)
+/*! @} */
+
+/*! @name CTRL - CRC Module Control Register */
+/*! @{ */
+#define CRC_CTRL_ENABLE_MASK (0x1U)
+#define CRC_CTRL_ENABLE_SHIFT (0U)
+/*! enable - CRC calcuate enable
+ * 0b0..diable CRC calculation
+ * 0b1..enable CRC calculation (automatically cleared when CRC calculation is finished)
+ */
+#define CRC_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_ENABLE_SHIFT)) & CRC_CTRL_ENABLE_MASK)
+#define CRC_CTRL_MODE_MASK (0xEU)
+#define CRC_CTRL_MODE_SHIFT (1U)
+/*! mode - CRC mode select
+ * 0b000..x**16+x**12+x**5+1 (CRC-16-CCITT, CRC-CCITT)
+ * 0b001..x**16+x**15+x**2+1 (CRC-16, CRC-16-IBM, CRC-16-ANSI)
+ * 0b010..x**16+x**15+x**11+x**9+x**8+x**7+x**5+x**4+x**2+x+1 (CRC-16-T10-DIF)
+ * 0b011..x**32+x**26+x**23+x**22+x**16+x**12+x**11+x**10+x**8+x**7+x**5+x**4+x**2+x+1 (CRC-32-IEEE802.3)
+ * 0b100..x**16+x**13+x**12+x**11+x**10+x**8+x**6+x**5+x**2+1(CRC-16-DNP)
+ */
+#define CRC_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_MODE_SHIFT)) & CRC_CTRL_MODE_MASK)
+/*! @} */
+
+/*! @name STREAM_LEN_M1 - Stream Length Minus 1 Register */
+/*! @{ */
+#define CRC_STREAM_LEN_M1_LENGTH_M1_MASK (0xFFFFFFFFU)
+#define CRC_STREAM_LEN_M1_LENGTH_M1_SHIFT (0U)
+/*! length_m1 - Input stream length minus 1 (units of bytes)
+ * 0b00000000000000000000000000000000..input stream length of 1 byte
+ * 0b00000000000000000000000011111111..input stream length of 256 bytes
+ */
+#define CRC_STREAM_LEN_M1_LENGTH_M1(x) (((uint32_t)(((uint32_t)(x)) << CRC_STREAM_LEN_M1_LENGTH_M1_SHIFT)) & CRC_STREAM_LEN_M1_LENGTH_M1_MASK)
+/*! @} */
+
+/*! @name STREAM_IN - Stream Input Register */
+/*! @{ */
+#define CRC_STREAM_IN_DATA_MASK (0xFFFFFFFFU)
+#define CRC_STREAM_IN_DATA_SHIFT (0U)
+/*! data - Stream input data
+ */
+#define CRC_STREAM_IN_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_STREAM_IN_DATA_SHIFT)) & CRC_STREAM_IN_DATA_MASK)
+/*! @} */
+
+/*! @name RESULT - CRC Calculation Result Register */
+/*! @{ */
+#define CRC_RESULT_DATA_MASK (0xFFFFFFFFU)
+#define CRC_RESULT_DATA_SHIFT (0U)
+/*! data - CRC calculation result
+ */
+#define CRC_RESULT_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_RESULT_DATA_SHIFT)) & CRC_RESULT_DATA_MASK)
+/*! @} */
+
+/*! @name REV_ID - CRC Revision ID register */
+/*! @{ */
+#define CRC_REV_ID_MINOR_REV_ID_MASK (0xFU)
+#define CRC_REV_ID_MINOR_REV_ID_SHIFT (0U)
+/*! minor_rev_id - Minor revision ID
+ */
+#define CRC_REV_ID_MINOR_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << CRC_REV_ID_MINOR_REV_ID_SHIFT)) & CRC_REV_ID_MINOR_REV_ID_MASK)
+#define CRC_REV_ID_MAJOR_REV_ID_MASK (0xF0U)
+#define CRC_REV_ID_MAJOR_REV_ID_SHIFT (4U)
+/*! major_rev_id - Major revision ID
+ */
+#define CRC_REV_ID_MAJOR_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << CRC_REV_ID_MAJOR_REV_ID_SHIFT)) & CRC_REV_ID_MAJOR_REV_ID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x44005000u)
+/** Peripheral CRC base pointer */
+#define CRC ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC }
+/** Interrupt vectors for the CRC peripheral type */
+#define CRC_IRQS { CRC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< DAC Control Register, offset: 0x0 */
+ __I uint32_t STATUS; /**< DAC Status Register, offset: 0x4 */
+ __IO uint32_t ACTRL; /**< Channel A Control Register, offset: 0x8 */
+ __IO uint32_t BCTRL; /**< Channel B Control Register, offset: 0xC */
+ __IO uint32_t ADATA; /**< Channel A Data Register, offset: 0x10 */
+ __IO uint32_t BDATA; /**< Channel B Data Register, offset: 0x14 */
+ __I uint32_t ISR; /**< Interrupt Status Register, offset: 0x18 */
+ __IO uint32_t IMR; /**< Interrupt Mask Register, offset: 0x1C */
+ __I uint32_t IRSR; /**< Interrupt Raw Status Register, offset: 0x20 */
+ __IO uint32_t ICR; /**< Interrupt Clear Register, offset: 0x24 */
+ __IO uint32_t CLK; /**< Clock Register, offset: 0x28 */
+ __IO uint32_t RST; /**< Soft Reset Register, offset: 0x2C */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DAC Control Register */
+/*! @{ */
+#define DAC_CTRL_REF_SEL_MASK (0x1U)
+#define DAC_CTRL_REF_SEL_SHIFT (0U)
+/*! ref_sel - Reference selector
+ * 0b0..internal reference
+ * 0b1..external reference
+ */
+#define DAC_CTRL_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_REF_SEL_SHIFT)) & DAC_CTRL_REF_SEL_MASK)
+/*! @} */
+
+/*! @name STATUS - DAC Status Register */
+/*! @{ */
+#define DAC_STATUS_A_DV_MASK (0x1U)
+#define DAC_STATUS_A_DV_SHIFT (0U)
+/*! a_dv - DACA conversion status.
+ * 0b0..channel A conversion is not done
+ * 0b1..channel A conversion complete
+ */
+#define DAC_STATUS_A_DV(x) (((uint32_t)(((uint32_t)(x)) << DAC_STATUS_A_DV_SHIFT)) & DAC_STATUS_A_DV_MASK)
+#define DAC_STATUS_B_DV_MASK (0x2U)
+#define DAC_STATUS_B_DV_SHIFT (1U)
+/*! b_dv - DACB conversion status
+ * 0b0..channel B conversion is not done
+ * 0b1..channel B conversion complete
+ */
+#define DAC_STATUS_B_DV(x) (((uint32_t)(((uint32_t)(x)) << DAC_STATUS_B_DV_SHIFT)) & DAC_STATUS_B_DV_MASK)
+/*! @} */
+
+/*! @name ACTRL - Channel A Control Register */
+/*! @{ */
+#define DAC_ACTRL_A_EN_MASK (0x1U)
+#define DAC_ACTRL_A_EN_SHIFT (0U)
+/*! a_en - Channel A Enable/Disable signal
+ * 0b0..disable channel A conversion
+ * 0b1..enable channel A conversion
+ */
+#define DAC_ACTRL_A_EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_EN_SHIFT)) & DAC_ACTRL_A_EN_MASK)
+#define DAC_ACTRL_A_IO_EN_MASK (0x2U)
+#define DAC_ACTRL_A_IO_EN_SHIFT (1U)
+/*! a_io_en - Channel A conversion output to pad enable
+ * 0b0..disable channel A conversion result to GPIO
+ * 0b1..enable channel A conversion result to GPIO
+ */
+#define DAC_ACTRL_A_IO_EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_IO_EN_SHIFT)) & DAC_ACTRL_A_IO_EN_MASK)
+#define DAC_ACTRL_A_TRIG_EN_MASK (0x4U)
+#define DAC_ACTRL_A_TRIG_EN_SHIFT (2U)
+/*! a_trig_en - Channel A trigger enable
+ * 0b0..Channel A conversion triggered by external event disabled
+ * 0b1..Channel A conversion triggered by external event enabled
+ */
+#define DAC_ACTRL_A_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIG_EN_SHIFT)) & DAC_ACTRL_A_TRIG_EN_MASK)
+#define DAC_ACTRL_A_TRIG_SEL_MASK (0x18U)
+#define DAC_ACTRL_A_TRIG_SEL_SHIFT (3U)
+/*! a_trig_sel - Channel A trigger selector
+ */
+#define DAC_ACTRL_A_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIG_SEL_SHIFT)) & DAC_ACTRL_A_TRIG_SEL_MASK)
+#define DAC_ACTRL_A_TRIG_TYP_MASK (0x60U)
+#define DAC_ACTRL_A_TRIG_TYP_SHIFT (5U)
+/*! a_trig_typ - Channel A trigger type
+ * 0b00..reserved
+ * 0b01..rising edge trigger
+ * 0b10..falling edge trigger
+ * 0b11..both rising and falling edge trigger
+ */
+#define DAC_ACTRL_A_TRIG_TYP(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIG_TYP_SHIFT)) & DAC_ACTRL_A_TRIG_TYP_MASK)
+#define DAC_ACTRL_A_DEN_MASK (0x80U)
+#define DAC_ACTRL_A_DEN_SHIFT (7U)
+/*! a_den - Channel A DMA enable
+ * 0b0..DMA data transfer disabled
+ * 0b1..DMA data transfer enabled
+ */
+#define DAC_ACTRL_A_DEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_DEN_SHIFT)) & DAC_ACTRL_A_DEN_MASK)
+#define DAC_ACTRL_A_TIME_MODE_MASK (0x100U)
+#define DAC_ACTRL_A_TIME_MODE_SHIFT (8U)
+/*! a_time_mode - Channel A Mode
+ * 0b0..non-timing related
+ * 0b1..timing related
+ */
+#define DAC_ACTRL_A_TIME_MODE(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TIME_MODE_SHIFT)) & DAC_ACTRL_A_TIME_MODE_MASK)
+#define DAC_ACTRL_A_TRIA_HALF_MASK (0x200U)
+#define DAC_ACTRL_A_TRIA_HALF_SHIFT (9U)
+/*! a_tria_half - Channel A triangle wave type selector.
+ * 0b0..full triangle
+ * 0b1..half triangle
+ */
+#define DAC_ACTRL_A_TRIA_HALF(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIA_HALF_SHIFT)) & DAC_ACTRL_A_TRIA_HALF_MASK)
+#define DAC_ACTRL_A_TRIA_MAMP_SEL_MASK (0x3C00U)
+#define DAC_ACTRL_A_TRIA_MAMP_SEL_SHIFT (10U)
+/*! a_tria_mamp_sel - Channel A triangle wave max amplitude selector.
+ * 0b0000..63
+ * 0b0001..127
+ * 0b0010..191
+ * 0b0011..255
+ * 0b0100..319
+ * 0b0101..383
+ * 0b0110..447
+ * 0b0111..511
+ * 0b1000..575
+ * 0b1001..639
+ * 0b1010..703
+ * 0b1011..767
+ * 0b1100..831
+ * 0b1101..895
+ * 0b1110..959
+ * 0b1111..1023
+ */
+#define DAC_ACTRL_A_TRIA_MAMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIA_MAMP_SEL_SHIFT)) & DAC_ACTRL_A_TRIA_MAMP_SEL_MASK)
+#define DAC_ACTRL_A_TRIA_STEP_SEL_MASK (0xC000U)
+#define DAC_ACTRL_A_TRIA_STEP_SEL_SHIFT (14U)
+/*! a_tria_step_sel - Channel A triangle wave step selector.
+ * 0b00..1
+ * 0b01..3
+ * 0b10..15
+ * 0b11..511
+ */
+#define DAC_ACTRL_A_TRIA_STEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_TRIA_STEP_SEL_SHIFT)) & DAC_ACTRL_A_TRIA_STEP_SEL_MASK)
+#define DAC_ACTRL_A_WAVE_MASK (0x30000U)
+#define DAC_ACTRL_A_WAVE_SHIFT (16U)
+/*! a_wave - Channel A wave type select.
+ * 0b00..
+ * 0b01..triangle wave
+ * 0b10..sine wave
+ * 0b11..
+ */
+#define DAC_ACTRL_A_WAVE(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_WAVE_SHIFT)) & DAC_ACTRL_A_WAVE_MASK)
+#define DAC_ACTRL_A_RANGE_MASK (0xC0000U)
+#define DAC_ACTRL_A_RANGE_SHIFT (18U)
+/*! a_range - Output voltage range control, with Internal/External reference
+ * 0b00..0.16+(0.64*input code/1023) with ref_sel=0(internal)/0.08* Vref_ext+(0.32* Vref_ext*input_code/1023) with ref_sel=1(external)
+ * 0b01..0.19+(1.01*input code /1023) with ref_sel=0(internal)/0.095* Vref_ext+(0.505* Vref_ext*input_code/1023) with ref_sel=1(external)
+ * 0b10..0.19+(1.01*input code /1023) with ref_sel=0(internal)/0.095* Vref_ext+(0.505* Vref_ext*input_code/1023) with ref_sel=1(external)
+ * 0b11..0.18+(1.42*input code /1023) with ref_sel=0(internal)/0.09*Vref_ext+(0.71* Vref_ext*input_code/1023) with ref_sel=1(external)
+ */
+#define DAC_ACTRL_A_RANGE(x) (((uint32_t)(((uint32_t)(x)) << DAC_ACTRL_A_RANGE_SHIFT)) & DAC_ACTRL_A_RANGE_MASK)
+/*! @} */
+
+/*! @name BCTRL - Channel B Control Register */
+/*! @{ */
+#define DAC_BCTRL_B_EN_MASK (0x1U)
+#define DAC_BCTRL_B_EN_SHIFT (0U)
+/*! b_en - Channel B Enable/Disable signal
+ * 0b0..disable channel B conversion
+ * 0b1..enable channel B conversion
+ */
+#define DAC_BCTRL_B_EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_EN_SHIFT)) & DAC_BCTRL_B_EN_MASK)
+#define DAC_BCTRL_B_IO_EN_MASK (0x2U)
+#define DAC_BCTRL_B_IO_EN_SHIFT (1U)
+/*! b_io_en - Channel B conversion output to pad enable
+ * 0b0..disable channel B conversion result to GPIO
+ * 0b1..enable channel B conversion result to GPIO
+ */
+#define DAC_BCTRL_B_IO_EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_IO_EN_SHIFT)) & DAC_BCTRL_B_IO_EN_MASK)
+#define DAC_BCTRL_B_TRIG_EN_MASK (0x4U)
+#define DAC_BCTRL_B_TRIG_EN_SHIFT (2U)
+/*! b_trig_en - Channel B trigger enable
+ * 0b0..Channel B conversion triggered by external event disabled
+ * 0b1..Channel B conversion triggered by external event enabled
+ */
+#define DAC_BCTRL_B_TRIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_TRIG_EN_SHIFT)) & DAC_BCTRL_B_TRIG_EN_MASK)
+#define DAC_BCTRL_B_TRIG_SEL_MASK (0x18U)
+#define DAC_BCTRL_B_TRIG_SEL_SHIFT (3U)
+/*! b_trig_sel - Channel B trigger selector
+ */
+#define DAC_BCTRL_B_TRIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_TRIG_SEL_SHIFT)) & DAC_BCTRL_B_TRIG_SEL_MASK)
+#define DAC_BCTRL_B_TRIG_TYP_MASK (0x60U)
+#define DAC_BCTRL_B_TRIG_TYP_SHIFT (5U)
+/*! b_trig_typ - Channel B trigger type
+ * 0b00..reserved
+ * 0b01..rising edge trigger
+ * 0b10..falling edge trigger
+ * 0b11..both rising and falling edge trigger
+ */
+#define DAC_BCTRL_B_TRIG_TYP(x) (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_TRIG_TYP_SHIFT)) & DAC_BCTRL_B_TRIG_TYP_MASK)
+#define DAC_BCTRL_B_DEN_MASK (0x80U)
+#define DAC_BCTRL_B_DEN_SHIFT (7U)
+/*! b_den - Channel B DMA enable
+ * 0b0..DMA data transfer disabled
+ * 0b1..DMA data transfer enabled
+ */
+#define DAC_BCTRL_B_DEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_DEN_SHIFT)) & DAC_BCTRL_B_DEN_MASK)
+#define DAC_BCTRL_B_TIME_MODE_MASK (0x100U)
+#define DAC_BCTRL_B_TIME_MODE_SHIFT (8U)
+/*! b_time_mode - Channel B Mode
+ * 0b0..non-timing related
+ * 0b1..timing related
+ */
+#define DAC_BCTRL_B_TIME_MODE(x) (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_TIME_MODE_SHIFT)) & DAC_BCTRL_B_TIME_MODE_MASK)
+#define DAC_BCTRL_B_WAVE_MASK (0x600U)
+#define DAC_BCTRL_B_WAVE_SHIFT (9U)
+/*! b_wave - Channel B wave type select.
+ * 0b00..
+ * 0b01..reserved
+ * 0b10..reserved
+ * 0b11..differential mode with channel A
+ */
+#define DAC_BCTRL_B_WAVE(x) (((uint32_t)(((uint32_t)(x)) << DAC_BCTRL_B_WAVE_SHIFT)) & DAC_BCTRL_B_WAVE_MASK)
+/*! @} */
+
+/*! @name ADATA - Channel A Data Register */
+/*! @{ */
+#define DAC_ADATA_A_DATA_MASK (0x3FFU)
+#define DAC_ADATA_A_DATA_SHIFT (0U)
+/*! a_data - Channel A Data input
+ */
+#define DAC_ADATA_A_DATA(x) (((uint32_t)(((uint32_t)(x)) << DAC_ADATA_A_DATA_SHIFT)) & DAC_ADATA_A_DATA_MASK)
+/*! @} */
+
+/*! @name BDATA - Channel B Data Register */
+/*! @{ */
+#define DAC_BDATA_B_DATA_MASK (0x3FFU)
+#define DAC_BDATA_B_DATA_SHIFT (0U)
+/*! b_data - Channel B Data input
+ */
+#define DAC_BDATA_B_DATA(x) (((uint32_t)(((uint32_t)(x)) << DAC_BDATA_B_DATA_SHIFT)) & DAC_BDATA_B_DATA_MASK)
+/*! @} */
+
+/*! @name ISR - Interrupt Status Register */
+/*! @{ */
+#define DAC_ISR_A_RDY_INT_MASK (0x1U)
+#define DAC_ISR_A_RDY_INT_SHIFT (0U)
+/*! a_rdy_int - Channel A Data Ready
+ */
+#define DAC_ISR_A_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_ISR_A_RDY_INT_SHIFT)) & DAC_ISR_A_RDY_INT_MASK)
+#define DAC_ISR_B_RDY_INT_MASK (0x2U)
+#define DAC_ISR_B_RDY_INT_SHIFT (1U)
+/*! b_rdy_int - Channel B Data Ready
+ */
+#define DAC_ISR_B_RDY_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_ISR_B_RDY_INT_SHIFT)) & DAC_ISR_B_RDY_INT_MASK)
+#define DAC_ISR_A_TO_INT_MASK (0x4U)
+#define DAC_ISR_A_TO_INT_SHIFT (2U)
+/*! a_to_int - Channel A Timeout
+ */
+#define DAC_ISR_A_TO_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_ISR_A_TO_INT_SHIFT)) & DAC_ISR_A_TO_INT_MASK)
+#define DAC_ISR_B_TO_INT_MASK (0x8U)
+#define DAC_ISR_B_TO_INT_SHIFT (3U)
+/*! b_to_int - Channel B Timeout
+ */
+#define DAC_ISR_B_TO_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_ISR_B_TO_INT_SHIFT)) & DAC_ISR_B_TO_INT_MASK)
+#define DAC_ISR_TRIA_OVFL_INT_MASK (0x10U)
+#define DAC_ISR_TRIA_OVFL_INT_SHIFT (4U)
+/*! tria_ovfl_int - Triangle Overflow
+ */
+#define DAC_ISR_TRIA_OVFL_INT(x) (((uint32_t)(((uint32_t)(x)) << DAC_ISR_TRIA_OVFL_INT_SHIFT)) & DAC_ISR_TRIA_OVFL_INT_MASK)
+/*! @} */
+
+/*! @name IMR - Interrupt Mask Register */
+/*! @{ */
+#define DAC_IMR_A_RDY_INT_MSK_MASK (0x1U)
+#define DAC_IMR_A_RDY_INT_MSK_SHIFT (0U)
+/*! a_rdy_int_msk - Channel A Data Ready Mask
+ */
+#define DAC_IMR_A_RDY_INT_MSK(x) (((uint32_t)(((uint32_t)(x)) << DAC_IMR_A_RDY_INT_MSK_SHIFT)) & DAC_IMR_A_RDY_INT_MSK_MASK)
+#define DAC_IMR_B_RDY_INT_MSK_MASK (0x2U)
+#define DAC_IMR_B_RDY_INT_MSK_SHIFT (1U)
+/*! b_rdy_int_msk - Channel B Data Ready Mask
+ */
+#define DAC_IMR_B_RDY_INT_MSK(x) (((uint32_t)(((uint32_t)(x)) << DAC_IMR_B_RDY_INT_MSK_SHIFT)) & DAC_IMR_B_RDY_INT_MSK_MASK)
+#define DAC_IMR_A_TO_INT_MSK_MASK (0x4U)
+#define DAC_IMR_A_TO_INT_MSK_SHIFT (2U)
+/*! a_to_int_msk - Channel A Timeout Mask
+ */
+#define DAC_IMR_A_TO_INT_MSK(x) (((uint32_t)(((uint32_t)(x)) << DAC_IMR_A_TO_INT_MSK_SHIFT)) & DAC_IMR_A_TO_INT_MSK_MASK)
+#define DAC_IMR_B_TO_INT_MSK_MASK (0x8U)
+#define DAC_IMR_B_TO_INT_MSK_SHIFT (3U)
+/*! b_to_int_msk - Channel B Timeout Mask
+ */
+#define DAC_IMR_B_TO_INT_MSK(x) (((uint32_t)(((uint32_t)(x)) << DAC_IMR_B_TO_INT_MSK_SHIFT)) & DAC_IMR_B_TO_INT_MSK_MASK)
+#define DAC_IMR_TRIA_OVFL_INT_MSK_MASK (0x10U)
+#define DAC_IMR_TRIA_OVFL_INT_MSK_SHIFT (4U)
+/*! tria_ovfl_int_msk - Triangle Overflow Mask
+ */
+#define DAC_IMR_TRIA_OVFL_INT_MSK(x) (((uint32_t)(((uint32_t)(x)) << DAC_IMR_TRIA_OVFL_INT_MSK_SHIFT)) & DAC_IMR_TRIA_OVFL_INT_MSK_MASK)
+/*! @} */
+
+/*! @name IRSR - Interrupt Raw Status Register */
+/*! @{ */
+#define DAC_IRSR_A_RDY_INT_RAW_MASK (0x1U)
+#define DAC_IRSR_A_RDY_INT_RAW_SHIFT (0U)
+/*! a_rdy_int_raw - Channel A Data Ready Raw
+ */
+#define DAC_IRSR_A_RDY_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_A_RDY_INT_RAW_SHIFT)) & DAC_IRSR_A_RDY_INT_RAW_MASK)
+#define DAC_IRSR_B_RDY_INT_RAW_MASK (0x2U)
+#define DAC_IRSR_B_RDY_INT_RAW_SHIFT (1U)
+/*! b_rdy_int_raw - Channel B Data Ready Raw
+ */
+#define DAC_IRSR_B_RDY_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_B_RDY_INT_RAW_SHIFT)) & DAC_IRSR_B_RDY_INT_RAW_MASK)
+#define DAC_IRSR_A_TO_INT_RAW_MASK (0x4U)
+#define DAC_IRSR_A_TO_INT_RAW_SHIFT (2U)
+/*! a_to_int_raw - Channel A Timeout Raw
+ */
+#define DAC_IRSR_A_TO_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_A_TO_INT_RAW_SHIFT)) & DAC_IRSR_A_TO_INT_RAW_MASK)
+#define DAC_IRSR_B_TO_INT_RAW_MASK (0x8U)
+#define DAC_IRSR_B_TO_INT_RAW_SHIFT (3U)
+/*! b_to_int_raw - Channel B Timeout Raw
+ */
+#define DAC_IRSR_B_TO_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_B_TO_INT_RAW_SHIFT)) & DAC_IRSR_B_TO_INT_RAW_MASK)
+#define DAC_IRSR_TRIA_OVFL_INT_RAW_MASK (0x10U)
+#define DAC_IRSR_TRIA_OVFL_INT_RAW_SHIFT (4U)
+/*! tria_ovfl_int_raw - Triangle Overflow Raw
+ */
+#define DAC_IRSR_TRIA_OVFL_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << DAC_IRSR_TRIA_OVFL_INT_RAW_SHIFT)) & DAC_IRSR_TRIA_OVFL_INT_RAW_MASK)
+/*! @} */
+
+/*! @name ICR - Interrupt Clear Register */
+/*! @{ */
+#define DAC_ICR_A_RDY_INT_CLR_MASK (0x1U)
+#define DAC_ICR_A_RDY_INT_CLR_SHIFT (0U)
+/*! a_rdy_int_clr - Channel A Data Ready Clear
+ */
+#define DAC_ICR_A_RDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DAC_ICR_A_RDY_INT_CLR_SHIFT)) & DAC_ICR_A_RDY_INT_CLR_MASK)
+#define DAC_ICR_B_RDY_INT_CLR_MASK (0x2U)
+#define DAC_ICR_B_RDY_INT_CLR_SHIFT (1U)
+/*! b_rdy_int_clr - Channel B Data Ready Clear
+ */
+#define DAC_ICR_B_RDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DAC_ICR_B_RDY_INT_CLR_SHIFT)) & DAC_ICR_B_RDY_INT_CLR_MASK)
+#define DAC_ICR_A_TO_INT_CLR_MASK (0x4U)
+#define DAC_ICR_A_TO_INT_CLR_SHIFT (2U)
+/*! a_to_int_clr - Channel A Timeout Clear
+ */
+#define DAC_ICR_A_TO_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DAC_ICR_A_TO_INT_CLR_SHIFT)) & DAC_ICR_A_TO_INT_CLR_MASK)
+#define DAC_ICR_B_TO_INT_CLR_MASK (0x8U)
+#define DAC_ICR_B_TO_INT_CLR_SHIFT (3U)
+/*! b_to_int_clr - Channel B Timeout Clear
+ */
+#define DAC_ICR_B_TO_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DAC_ICR_B_TO_INT_CLR_SHIFT)) & DAC_ICR_B_TO_INT_CLR_MASK)
+#define DAC_ICR_TRIA_OVFL_INT_CLR_MASK (0x10U)
+#define DAC_ICR_TRIA_OVFL_INT_CLR_SHIFT (4U)
+/*! tria_ovfl_int_clr - Triangle Overflow Clear
+ */
+#define DAC_ICR_TRIA_OVFL_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << DAC_ICR_TRIA_OVFL_INT_CLR_SHIFT)) & DAC_ICR_TRIA_OVFL_INT_CLR_MASK)
+/*! @} */
+
+/*! @name CLK - Clock Register */
+/*! @{ */
+#define DAC_CLK_CLK_CTRL_MASK (0x6U)
+#define DAC_CLK_CLK_CTRL_SHIFT (1U)
+/*! clk_ctrl - DAC conversion rate selector.
+ * 0b00..62.5K
+ * 0b01..125K
+ * 0b10..250K
+ * 0b11..500K
+ */
+#define DAC_CLK_CLK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CLK_CLK_CTRL_SHIFT)) & DAC_CLK_CLK_CTRL_MASK)
+#define DAC_CLK_SOFT_CLK_RST_MASK (0x10U)
+#define DAC_CLK_SOFT_CLK_RST_SHIFT (4U)
+/*! soft_clk_rst - Soft reset for clock divider
+ * 0b0..
+ * 0b1..
+ */
+#define DAC_CLK_SOFT_CLK_RST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CLK_SOFT_CLK_RST_SHIFT)) & DAC_CLK_SOFT_CLK_RST_MASK)
+/*! @} */
+
+/*! @name RST - Soft Reset Register */
+/*! @{ */
+#define DAC_RST_A_SOFT_RST_MASK (0x1U)
+#define DAC_RST_A_SOFT_RST_SHIFT (0U)
+/*! a_soft_rst - Soft reset for DAC channel A, active high
+ * 0b0..no action
+ * 0b1..
+ */
+#define DAC_RST_A_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << DAC_RST_A_SOFT_RST_SHIFT)) & DAC_RST_A_SOFT_RST_MASK)
+#define DAC_RST_B_SOFT_RST_MASK (0x2U)
+#define DAC_RST_B_SOFT_RST_SHIFT (1U)
+/*! b_soft_rst - Soft reset for DAC channel B, active high
+ * 0b0..no action
+ * 0b1..
+ */
+#define DAC_RST_B_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << DAC_RST_B_SOFT_RST_SHIFT)) & DAC_RST_B_SOFT_RST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC base address */
+#define DAC_BASE (0x460B0200u)
+/** Peripheral DAC base pointer */
+#define DAC ((DAC_Type *)DAC_BASE)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAC_Peripheral_Access_Layer DMAC Peripheral Access Layer
+ * @{
+ */
+
+/** DMAC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MASK_BLOCKINT; /**< DMA channel BLOCK TRANSFER INTERRUPT MASK registers, offset: 0x0 */
+ __IO uint32_t STATUS_BLOCKINT; /**< DMA channel BLOCK TRANSFER INTERRUPT Registers, offset: 0x4 */
+ __IO uint32_t MASK_TFRINT; /**< DMA Channel transfer completion interrupt mask Registers, offset: 0x8 */
+ __IO uint32_t STATUS_TFRINT; /**< DMA Channel transfer completion interrupt Registers, offset: 0xC */
+ __IO uint32_t MASK_BUSERRINT; /**< DMA Channel bus error interrupt mask Registers, offset: 0x10 */
+ __IO uint32_t STATUS_BUSERRINT; /**< DMA Channel bus error interrupt mask Registers, offset: 0x14 */
+ __IO uint32_t MASK_ADDRERRINT; /**< DMA Channel source/target address alignment error interrupt mask Registers, offset: 0x18 */
+ __IO uint32_t STATUS_ADDRERRINT; /**< DMA Channel source/target address alignment error interrupt Registers, offset: 0x1C */
+ __I uint32_t STATUS_CHLINT; /**< DMA CHANNEL INTERRUPT REGISTER, offset: 0x20 */
+ uint8_t RESERVED_0[92];
+ __IO uint32_t HPROT; /**< THE PROTECTION CONTROL SIGNALS REGISTERS, offset: 0x80 */
+ uint8_t RESERVED_1[124];
+ struct { /* offset: 0x100, array step: 0x30 */
+ __IO uint32_t SADR; /**< DMA SOURCE ADDRESS REGISTERS, array offset: 0x100, array step: 0x30 */
+ __IO uint32_t TADR; /**< DMA TARGET ADDRESS REGISTERS, array offset: 0x104, array step: 0x30 */
+ __IO uint32_t CTRLA; /**< DMA CONTROL REGISTERS A, array offset: 0x108, array step: 0x30 */
+ __IO uint32_t CTRLB; /**< DMA CONTROL REGISTERS B, array offset: 0x10C, array step: 0x30 */
+ __IO uint32_t CHL_EN; /**< DMA CHANNEL ENABLE REGISTERS, array offset: 0x110, array step: 0x30 */
+ __IO uint32_t CHL_STOP; /**< DMA CHANNEL STOP REGISTERS, array offset: 0x114, array step: 0x30 */
+ uint8_t RESERVED_0[24];
+ } CHANNEL[32];
+ uint8_t RESERVED_2[256];
+ __IO uint32_t ACK_DELAY; /**< DMA ACK DELAY CYCLE for single transfer in M2P transfer type Registers, offset: 0x800 */
+ uint8_t RESERVED_3[252];
+ __I uint32_t ERR_INFO0; /**< DMA ERROR INFORMATION REGISTER 0, offset: 0x900 */
+ __I uint32_t ERR_INFO1; /**< DMA ERROR INFORMATION REGISTER 1, offset: 0x904 */
+ __I uint32_t DIAGNOSE_INFO0; /**< DMA DIAGNOSE INFORMATION REGISTER 0, offset: 0x908 */
+ __I uint32_t DIAGNOSE_INFO1; /**< DMA DIAGNOSE INFORMATION REGISTER 1, offset: 0x90C */
+ __I uint32_t DIAGNOSE_INFO2; /**< DMA DIAGNOSE INFORMATION REGISTER 2, offset: 0x910 */
+ __I uint32_t DIAGNOSE_INFO3; /**< DMA DIAGNOSE INFORMATION REGISTER 3, offset: 0x914 */
+ __I uint32_t DIAGNOSE_INFO4; /**< DMA DIAGNOSE INFORMATION REGISTER 4, offset: 0x918 */
+ __I uint32_t DIAGNOSE_INFO5; /**< DMA DIAGNOSE INFORMATION REGISTER 5, offset: 0x91C */
+ __I uint32_t DIAGNOSE_INFO6; /**< DMA DIAGNOSE INFORMATION REGISTER 6, offset: 0x920 */
+ __I uint32_t DIAGNOSE_INFO7; /**< DMA DIAGNOSE INFORMATION REGISTER 7, offset: 0x924 */
+} DMAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAC_Register_Masks DMAC Register Masks
+ * @{
+ */
+
+/*! @name MASK_BLOCKINT - DMA channel BLOCK TRANSFER INTERRUPT MASK registers */
+/*! @{ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT0_MASK (0x1U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT0_SHIFT (0U)
+/*! MASK_BLOCKINT0 - DMA channel 0 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT0_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT0_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT1_MASK (0x2U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT1_SHIFT (1U)
+/*! MASK_BLOCKINT1 - DMA channel 1 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT1_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT1_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT2_MASK (0x4U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT2_SHIFT (2U)
+/*! MASK_BLOCKINT2 - DMA channel 2 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT2_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT2_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT3_MASK (0x8U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT3_SHIFT (3U)
+/*! MASK_BLOCKINT3 - DMA channel 3 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT3_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT3_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT4_MASK (0x10U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT4_SHIFT (4U)
+/*! MASK_BLOCKINT4 - DMA channel 4 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT4_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT4_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT5_MASK (0x20U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT5_SHIFT (5U)
+/*! MASK_BLOCKINT5 - DMA channel 5 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT5_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT5_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT6_MASK (0x40U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT6_SHIFT (6U)
+/*! MASK_BLOCKINT6 - DMA channel 6 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT6_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT6_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT7_MASK (0x80U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT7_SHIFT (7U)
+/*! MASK_BLOCKINT7 - DMA channel 7 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT7_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT7_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT8_MASK (0x100U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT8_SHIFT (8U)
+/*! MASK_BLOCKINT8 - DMA channel 8 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT8_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT8_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT9_MASK (0x200U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT9_SHIFT (9U)
+/*! MASK_BLOCKINT9 - DMA channel 9 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT9_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT9_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT10_MASK (0x400U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT10_SHIFT (10U)
+/*! MASK_BLOCKINT10 - DMA channel 10 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT10_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT10_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT11_MASK (0x800U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT11_SHIFT (11U)
+/*! MASK_BLOCKINT11 - DMA channel 11 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT11_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT11_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT12_MASK (0x1000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT12_SHIFT (12U)
+/*! MASK_BLOCKINT12 - DMA channel 12 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT12_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT12_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT13_MASK (0x2000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT13_SHIFT (13U)
+/*! MASK_BLOCKINT13 - DMA channel 13 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT13_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT13_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT14_MASK (0x4000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT14_SHIFT (14U)
+/*! MASK_BLOCKINT14 - DMA channel 14 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT14_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT14_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT15_MASK (0x8000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT15_SHIFT (15U)
+/*! MASK_BLOCKINT15 - DMA channel 15 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT15_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT15_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT16_MASK (0x10000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT16_SHIFT (16U)
+/*! MASK_BLOCKINT16 - DMA channel 16 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT16_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT16_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT17_MASK (0x20000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT17_SHIFT (17U)
+/*! MASK_BLOCKINT17 - DMA channel 17 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT17_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT17_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT18_MASK (0x40000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT18_SHIFT (18U)
+/*! MASK_BLOCKINT18 - DMA channel 18 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT18_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT18_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT19_MASK (0x80000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT19_SHIFT (19U)
+/*! MASK_BLOCKINT19 - DMA channel 19 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT19_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT19_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT20_MASK (0x100000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT20_SHIFT (20U)
+/*! MASK_BLOCKINT20 - DMA channel 20 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT20_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT20_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT21_MASK (0x200000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT21_SHIFT (21U)
+/*! MASK_BLOCKINT21 - DMA channel 21 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT21_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT21_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT22_MASK (0x400000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT22_SHIFT (22U)
+/*! MASK_BLOCKINT22 - DMA channel 22 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT22_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT22_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT23_MASK (0x800000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT23_SHIFT (23U)
+/*! MASK_BLOCKINT23 - DMA channel 23 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT23_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT23_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT24_MASK (0x1000000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT24_SHIFT (24U)
+/*! MASK_BLOCKINT24 - DMA channel 24 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT24_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT24_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT25_MASK (0x2000000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT25_SHIFT (25U)
+/*! MASK_BLOCKINT25 - DMA channel 25 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT25_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT25_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT26_MASK (0x4000000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT26_SHIFT (26U)
+/*! MASK_BLOCKINT26 - DMA channel 26 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT26_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT26_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT27_MASK (0x8000000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT27_SHIFT (27U)
+/*! MASK_BLOCKINT27 - DMA channel 27 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT27_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT27_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT28_MASK (0x10000000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT28_SHIFT (28U)
+/*! MASK_BLOCKINT28 - DMA channel 28 block transfer interrupt mask bit
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT28_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT28_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT29_MASK (0x20000000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT29_SHIFT (29U)
+/*! MASK_BLOCKINT29 - DMA channel 29 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT29_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT29_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT30_MASK (0x40000000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT30_SHIFT (30U)
+/*! MASK_BLOCKINT30 - DMA channel 30 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT30_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT30_MASK)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT31_MASK (0x80000000U)
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT31_SHIFT (31U)
+/*! MASK_BLOCKINT31 - DMA channel 31 block transfer interrupt mask bit
+ * 0b0..mask the corresponding block interrupt
+ * 0b1..unmask the corresponding block interrupt
+ */
+#define DMAC_MASK_BLOCKINT_MASK_BLOCKINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BLOCKINT_MASK_BLOCKINT31_SHIFT)) & DMAC_MASK_BLOCKINT_MASK_BLOCKINT31_MASK)
+/*! @} */
+
+/*! @name STATUS_BLOCKINT - DMA channel BLOCK TRANSFER INTERRUPT Registers */
+/*! @{ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT0_MASK (0x1U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT0_SHIFT (0U)
+/*! STATUS_BLOCKINT0 - DMA channel 0 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT0_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT0_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT1_MASK (0x2U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT1_SHIFT (1U)
+/*! STATUS_BLOCKINT1 - DMA channel 1 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT1_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT1_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT2_MASK (0x4U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT2_SHIFT (2U)
+/*! STATUS_BLOCKINT2 - DMA channel 2 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT2_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT2_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT3_MASK (0x8U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT3_SHIFT (3U)
+/*! STATUS_BLOCKINT3 - DMA channel 3 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT3_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT3_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT4_MASK (0x10U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT4_SHIFT (4U)
+/*! STATUS_BLOCKINT4 - DMA channel 4 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT4_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT4_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT5_MASK (0x20U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT5_SHIFT (5U)
+/*! STATUS_BLOCKINT5 - DMA channel 5 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT5_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT5_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT6_MASK (0x40U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT6_SHIFT (6U)
+/*! STATUS_BLOCKINT6 - DMA channel 6 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT6_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT6_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT7_MASK (0x80U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT7_SHIFT (7U)
+/*! STATUS_BLOCKINT7 - DMA channel 7 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT7_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT7_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT8_MASK (0x100U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT8_SHIFT (8U)
+/*! STATUS_BLOCKINT8 - DMA channel 8 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT8_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT8_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT9_MASK (0x200U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT9_SHIFT (9U)
+/*! STATUS_BLOCKINT9 - DMA channel 9 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT9_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT9_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT10_MASK (0x400U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT10_SHIFT (10U)
+/*! STATUS_BLOCKINT10 - DMA channel 10 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT10_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT10_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT11_MASK (0x800U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT11_SHIFT (11U)
+/*! STATUS_BLOCKINT11 - DMA channel 11 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT11_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT11_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT12_MASK (0x1000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT12_SHIFT (12U)
+/*! STATUS_BLOCKINT12 - DMA channel 12 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT12_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT12_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT13_MASK (0x2000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT13_SHIFT (13U)
+/*! STATUS_BLOCKINT13 - DMA channel 13 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT13_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT13_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT14_MASK (0x4000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT14_SHIFT (14U)
+/*! STATUS_BLOCKINT14 - DMA channel 14 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT14_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT14_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT15_MASK (0x8000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT15_SHIFT (15U)
+/*! STATUS_BLOCKINT15 - DMA channel 15 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT15_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT15_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT16_MASK (0x10000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT16_SHIFT (16U)
+/*! STATUS_BLOCKINT16 - DMA channel 16 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT16_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT16_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT17_MASK (0x20000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT17_SHIFT (17U)
+/*! STATUS_BLOCKINT17 - DMA channel 17 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT17_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT17_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT18_MASK (0x40000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT18_SHIFT (18U)
+/*! STATUS_BLOCKINT18 - DMA channel 18 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT18_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT18_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT19_MASK (0x80000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT19_SHIFT (19U)
+/*! STATUS_BLOCKINT19 - DMA channel 19 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT19_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT19_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT20_MASK (0x100000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT20_SHIFT (20U)
+/*! STATUS_BLOCKINT20 - DMA channel 20 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT20_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT20_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT21_MASK (0x200000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT21_SHIFT (21U)
+/*! STATUS_BLOCKINT21 - DMA channel 21 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT21_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT21_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT22_MASK (0x400000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT22_SHIFT (22U)
+/*! STATUS_BLOCKINT22 - DMA channel 22 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT22_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT22_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT23_MASK (0x800000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT23_SHIFT (23U)
+/*! STATUS_BLOCKINT23 - DMA channel 23 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT23_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT23_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT24_MASK (0x1000000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT24_SHIFT (24U)
+/*! STATUS_BLOCKINT24 - DMA channel 24 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT24_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT24_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT25_MASK (0x2000000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT25_SHIFT (25U)
+/*! STATUS_BLOCKINT25 - DMA channel 25 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT25_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT25_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT26_MASK (0x4000000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT26_SHIFT (26U)
+/*! STATUS_BLOCKINT26 - DMA channel 26 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT26_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT26_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT27_MASK (0x8000000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT27_SHIFT (27U)
+/*! STATUS_BLOCKINT27 - DMA channel 27 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT27_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT27_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT28_MASK (0x10000000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT28_SHIFT (28U)
+/*! STATUS_BLOCKINT28 - DMA channel 28 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT28_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT28_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT29_MASK (0x20000000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT29_SHIFT (29U)
+/*! STATUS_BLOCKINT29 - DMA channel 29 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT29_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT29_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT30_MASK (0x40000000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT30_SHIFT (30U)
+/*! STATUS_BLOCKINT30 - DMA channel 30 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT30_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT30_MASK)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT31_MASK (0x80000000U)
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT31_SHIFT (31U)
+/*! STATUS_BLOCKINT31 - DMA channel 31 block transfer interrupt bit
+ * 0b0..DMA block burst/single transfer is not completed
+ * 0b1..DMA block burst/single transfer is completed
+ */
+#define DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT31_SHIFT)) & DMAC_STATUS_BLOCKINT_STATUS_BLOCKINT31_MASK)
+/*! @} */
+
+/*! @name MASK_TFRINT - DMA Channel transfer completion interrupt mask Registers */
+/*! @{ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT0_MASK (0x1U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT0_SHIFT (0U)
+/*! MASK_TFRINT0 - DMA channel 0 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT0_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT0_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT1_MASK (0x2U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT1_SHIFT (1U)
+/*! MASK_TFRINT1 - DMA channel 1 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT1_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT1_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT2_MASK (0x4U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT2_SHIFT (2U)
+/*! MASK_TFRINT2 - DMA channel 2 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT2_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT2_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT3_MASK (0x8U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT3_SHIFT (3U)
+/*! MASK_TFRINT3 - DMA channel 3 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT3_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT3_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT4_MASK (0x10U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT4_SHIFT (4U)
+/*! MASK_TFRINT4 - DMA channel 4 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT4_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT4_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT5_MASK (0x20U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT5_SHIFT (5U)
+/*! MASK_TFRINT5 - DMA channel 5 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT5_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT5_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT6_MASK (0x40U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT6_SHIFT (6U)
+/*! MASK_TFRINT6 - DMA channel 6 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT6_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT6_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT7_MASK (0x80U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT7_SHIFT (7U)
+/*! MASK_TFRINT7 - DMA channel 7 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT7_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT7_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT8_MASK (0x100U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT8_SHIFT (8U)
+/*! MASK_TFRINT8 - DMA channel 8 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT8_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT8_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT9_MASK (0x200U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT9_SHIFT (9U)
+/*! MASK_TFRINT9 - DMA channel 9 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT9_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT9_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT10_MASK (0x400U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT10_SHIFT (10U)
+/*! MASK_TFRINT10 - DMA channel 10 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT10_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT10_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT11_MASK (0x800U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT11_SHIFT (11U)
+/*! MASK_TFRINT11 - DMA channel 11 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT11_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT11_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT12_MASK (0x1000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT12_SHIFT (12U)
+/*! MASK_TFRINT12 - DMA channel 12 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT12_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT12_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT13_MASK (0x2000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT13_SHIFT (13U)
+/*! MASK_TFRINT13 - DMA channel 13 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT13_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT13_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT14_MASK (0x4000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT14_SHIFT (14U)
+/*! MASK_TFRINT14 - DMA channel 14 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT14_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT14_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT15_MASK (0x8000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT15_SHIFT (15U)
+/*! MASK_TFRINT15 - DMA channel 15 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT15_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT15_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT16_MASK (0x10000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT16_SHIFT (16U)
+/*! MASK_TFRINT16 - DMA channel 16 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT16_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT16_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT17_MASK (0x20000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT17_SHIFT (17U)
+/*! MASK_TFRINT17 - DMA channel 17 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT17_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT17_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT18_MASK (0x40000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT18_SHIFT (18U)
+/*! MASK_TFRINT18 - DMA channel 18 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT18_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT18_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT19_MASK (0x80000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT19_SHIFT (19U)
+/*! MASK_TFRINT19 - DMA channel 19 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT19_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT19_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT20_MASK (0x100000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT20_SHIFT (20U)
+/*! MASK_TFRINT20 - DMA channel 20 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT20_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT20_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT21_MASK (0x200000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT21_SHIFT (21U)
+/*! MASK_TFRINT21 - DMA channel 21 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT21_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT21_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT22_MASK (0x400000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT22_SHIFT (22U)
+/*! MASK_TFRINT22 - DMA channel 22 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT22_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT22_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT23_MASK (0x800000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT23_SHIFT (23U)
+/*! MASK_TFRINT23 - DMA channel 23 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT23_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT23_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT24_MASK (0x1000000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT24_SHIFT (24U)
+/*! MASK_TFRINT24 - DMA channel 24 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT24_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT24_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT25_MASK (0x2000000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT25_SHIFT (25U)
+/*! MASK_TFRINT25 - DMA channel 25 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT25_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT25_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT26_MASK (0x4000000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT26_SHIFT (26U)
+/*! MASK_TFRINT26 - DMA channel 26 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT26_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT26_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT27_MASK (0x8000000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT27_SHIFT (27U)
+/*! MASK_TFRINT27 - DMA channel 27 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT27_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT27_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT28_MASK (0x10000000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT28_SHIFT (28U)
+/*! MASK_TFRINT28 - DMA channel 28 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT28_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT28_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT29_MASK (0x20000000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT29_SHIFT (29U)
+/*! MASK_TFRINT29 - DMA channel 29 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT29_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT29_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT30_MASK (0x40000000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT30_SHIFT (30U)
+/*! MASK_TFRINT30 - DMA channel 30 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT30_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT30_MASK)
+#define DMAC_MASK_TFRINT_MASK_TFRINT31_MASK (0x80000000U)
+#define DMAC_MASK_TFRINT_MASK_TFRINT31_SHIFT (31U)
+/*! MASK_TFRINT31 - DMA channel 31 transfer completion interrupt mask bit
+ * 0b0..mask the corresponding transfer completion interrupt
+ * 0b1..unmask the corresponding transfer completion interrupt
+ */
+#define DMAC_MASK_TFRINT_MASK_TFRINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_TFRINT_MASK_TFRINT31_SHIFT)) & DMAC_MASK_TFRINT_MASK_TFRINT31_MASK)
+/*! @} */
+
+/*! @name STATUS_TFRINT - DMA Channel transfer completion interrupt Registers */
+/*! @{ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT0_MASK (0x1U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT0_SHIFT (0U)
+/*! STATUS_TFRINT0 - DMA channel 0 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT0_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT0_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT1_MASK (0x2U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT1_SHIFT (1U)
+/*! STATUS_TFRINT1 - DMA channel 1 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT1_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT1_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT2_MASK (0x4U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT2_SHIFT (2U)
+/*! STATUS_TFRINT2 - DMA channel 2 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT2_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT2_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT3_MASK (0x8U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT3_SHIFT (3U)
+/*! STATUS_TFRINT3 - DMA channel 3 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT3_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT3_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT4_MASK (0x10U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT4_SHIFT (4U)
+/*! STATUS_TFRINT4 - DMA channel 4 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT4_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT4_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT5_MASK (0x20U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT5_SHIFT (5U)
+/*! STATUS_TFRINT5 - DMA channel 5 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT5_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT5_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT6_MASK (0x40U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT6_SHIFT (6U)
+/*! STATUS_TFRINT6 - DMA channel 6 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT6_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT6_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT7_MASK (0x80U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT7_SHIFT (7U)
+/*! STATUS_TFRINT7 - DMA channel 7 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT7_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT7_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT8_MASK (0x100U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT8_SHIFT (8U)
+/*! STATUS_TFRINT8 - DMA channel 8 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT8_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT8_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT9_MASK (0x200U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT9_SHIFT (9U)
+/*! STATUS_TFRINT9 - DMA channel 9 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT9_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT9_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT10_MASK (0x400U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT10_SHIFT (10U)
+/*! STATUS_TFRINT10 - DMA channel 10 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT10_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT10_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT11_MASK (0x800U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT11_SHIFT (11U)
+/*! STATUS_TFRINT11 - DMA channel 11 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT11_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT11_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT12_MASK (0x1000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT12_SHIFT (12U)
+/*! STATUS_TFRINT12 - DMA channel 12 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT12_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT12_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT13_MASK (0x2000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT13_SHIFT (13U)
+/*! STATUS_TFRINT13 - DMA channel 13 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT13_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT13_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT14_MASK (0x4000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT14_SHIFT (14U)
+/*! STATUS_TFRINT14 - DMA channel 14 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT14_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT14_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT15_MASK (0x8000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT15_SHIFT (15U)
+/*! STATUS_TFRINT15 - DMA channel 15 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT15_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT15_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT16_MASK (0x10000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT16_SHIFT (16U)
+/*! STATUS_TFRINT16 - DMA channel 16 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT16_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT16_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT17_MASK (0x20000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT17_SHIFT (17U)
+/*! STATUS_TFRINT17 - DMA channel 17 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT17_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT17_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT18_MASK (0x40000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT18_SHIFT (18U)
+/*! STATUS_TFRINT18 - DMA channel 18 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT18_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT18_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT19_MASK (0x80000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT19_SHIFT (19U)
+/*! STATUS_TFRINT19 - DMA channel 19 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT19_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT19_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT20_MASK (0x100000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT20_SHIFT (20U)
+/*! STATUS_TFRINT20 - DMA channel 20 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT20_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT20_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT21_MASK (0x200000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT21_SHIFT (21U)
+/*! STATUS_TFRINT21 - DMA channel 21 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT21_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT21_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT22_MASK (0x400000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT22_SHIFT (22U)
+/*! STATUS_TFRINT22 - DMA channel 22 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT22_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT22_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT23_MASK (0x800000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT23_SHIFT (23U)
+/*! STATUS_TFRINT23 - DMA channel 23 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT23_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT23_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT24_MASK (0x1000000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT24_SHIFT (24U)
+/*! STATUS_TFRINT24 - DMA channel 24 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT24_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT24_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT25_MASK (0x2000000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT25_SHIFT (25U)
+/*! STATUS_TFRINT25 - DMA channel 25 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT25_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT25_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT26_MASK (0x4000000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT26_SHIFT (26U)
+/*! STATUS_TFRINT26 - DMA channel 26 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT26_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT26_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT27_MASK (0x8000000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT27_SHIFT (27U)
+/*! STATUS_TFRINT27 - DMA channel 27 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT27_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT27_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT28_MASK (0x10000000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT28_SHIFT (28U)
+/*! STATUS_TFRINT28 - DMA channel 28 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT28_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT28_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT29_MASK (0x20000000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT29_SHIFT (29U)
+/*! STATUS_TFRINT29 - DMA channel 29 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT29_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT29_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT30_MASK (0x40000000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT30_SHIFT (30U)
+/*! STATUS_TFRINT30 - DMA channel 30 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT30_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT30_MASK)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT31_MASK (0x80000000U)
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT31_SHIFT (31U)
+/*! STATUS_TFRINT31 - DMA channel 31 transfer completion interrupt
+ * 0b0..transfer is not completed
+ * 0b1..transfer is completed
+ */
+#define DMAC_STATUS_TFRINT_STATUS_TFRINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_TFRINT_STATUS_TFRINT31_SHIFT)) & DMAC_STATUS_TFRINT_STATUS_TFRINT31_MASK)
+/*! @} */
+
+/*! @name MASK_BUSERRINT - DMA Channel bus error interrupt mask Registers */
+/*! @{ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT0_MASK (0x1U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT0_SHIFT (0U)
+/*! MASK_BUSERRINT0 - DMA Channel 0 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT0_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT0_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT1_MASK (0x2U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT1_SHIFT (1U)
+/*! MASK_BUSERRINT1 - DMA Channel 1 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT1_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT1_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT2_MASK (0x4U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT2_SHIFT (2U)
+/*! MASK_BUSERRINT2 - DMA Channel 2 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT2_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT2_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT3_MASK (0x8U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT3_SHIFT (3U)
+/*! MASK_BUSERRINT3 - DMA Channel 3 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT3_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT3_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT4_MASK (0x10U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT4_SHIFT (4U)
+/*! MASK_BUSERRINT4 - DMA Channel 4 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT4_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT4_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT5_MASK (0x20U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT5_SHIFT (5U)
+/*! MASK_BUSERRINT5 - DMA Channel 5 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT5_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT5_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT6_MASK (0x40U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT6_SHIFT (6U)
+/*! MASK_BUSERRINT6 - DMA Channel 6 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT6_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT6_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT7_MASK (0x80U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT7_SHIFT (7U)
+/*! MASK_BUSERRINT7 - DMA Channel 7 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT7_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT7_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT8_MASK (0x100U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT8_SHIFT (8U)
+/*! MASK_BUSERRINT8 - DMA Channel 8 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT8_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT8_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT9_MASK (0x200U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT9_SHIFT (9U)
+/*! MASK_BUSERRINT9 - DMA Channel 9 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT9_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT9_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT10_MASK (0x400U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT10_SHIFT (10U)
+/*! MASK_BUSERRINT10 - DMA Channel 10 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT10_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT10_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT11_MASK (0x800U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT11_SHIFT (11U)
+/*! MASK_BUSERRINT11 - DMA Channel 11 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT11_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT11_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT12_MASK (0x1000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT12_SHIFT (12U)
+/*! MASK_BUSERRINT12 - DMA Channel 12 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT12_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT12_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT13_MASK (0x2000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT13_SHIFT (13U)
+/*! MASK_BUSERRINT13 - DMA Channel 13 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT13_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT13_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT14_MASK (0x4000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT14_SHIFT (14U)
+/*! MASK_BUSERRINT14 - DMA Channel 14 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT14_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT14_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT15_MASK (0x8000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT15_SHIFT (15U)
+/*! MASK_BUSERRINT15 - DMA Channel 15 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT15_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT15_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT16_MASK (0x10000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT16_SHIFT (16U)
+/*! MASK_BUSERRINT16 - DMA Channel 16 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT16_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT16_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT17_MASK (0x20000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT17_SHIFT (17U)
+/*! MASK_BUSERRINT17 - DMA Channel 17 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT17_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT17_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT18_MASK (0x40000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT18_SHIFT (18U)
+/*! MASK_BUSERRINT18 - DMA Channel 18 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT18_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT18_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT19_MASK (0x80000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT19_SHIFT (19U)
+/*! MASK_BUSERRINT19 - DMA Channel 19 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT19_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT19_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT20_MASK (0x100000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT20_SHIFT (20U)
+/*! MASK_BUSERRINT20 - DMA Channel 20 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT20_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT20_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT21_MASK (0x200000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT21_SHIFT (21U)
+/*! MASK_BUSERRINT21 - DMA Channel 21 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT21_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT21_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT22_MASK (0x400000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT22_SHIFT (22U)
+/*! MASK_BUSERRINT22 - DMA Channel 22 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT22_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT22_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT23_MASK (0x800000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT23_SHIFT (23U)
+/*! MASK_BUSERRINT23 - DMA Channel 23 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT23_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT23_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT24_MASK (0x1000000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT24_SHIFT (24U)
+/*! MASK_BUSERRINT24 - DMA Channel 24 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT24_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT24_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT25_MASK (0x2000000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT25_SHIFT (25U)
+/*! MASK_BUSERRINT25 - DMA Channel 25 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT25_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT25_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT26_MASK (0x4000000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT26_SHIFT (26U)
+/*! MASK_BUSERRINT26 - DMA Channel 26 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT26_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT26_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT27_MASK (0x8000000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT27_SHIFT (27U)
+/*! MASK_BUSERRINT27 - DMA Channel 27 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT27_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT27_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT28_MASK (0x10000000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT28_SHIFT (28U)
+/*! MASK_BUSERRINT28 - DMA Channel 28 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT28_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT28_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT29_MASK (0x20000000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT29_SHIFT (29U)
+/*! MASK_BUSERRINT29 - DMA Channel 29 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT29_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT29_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT30_MASK (0x40000000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT30_SHIFT (30U)
+/*! MASK_BUSERRINT30 - DMA Channel 30 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT30_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT30_MASK)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT31_MASK (0x80000000U)
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT31_SHIFT (31U)
+/*! MASK_BUSERRINT31 - DMA Channel 31 bus error interrupt mask bit
+ * 0b0..mask the corresponding bus error interrupt
+ * 0b1..unmask the corresponding bus error interrupt
+ */
+#define DMAC_MASK_BUSERRINT_MASK_BUSERRINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_BUSERRINT_MASK_BUSERRINT31_SHIFT)) & DMAC_MASK_BUSERRINT_MASK_BUSERRINT31_MASK)
+/*! @} */
+
+/*! @name STATUS_BUSERRINT - DMA Channel bus error interrupt mask Registers */
+/*! @{ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT0_MASK (0x1U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT0_SHIFT (0U)
+/*! STATUS_BUSERRINT0 - DMA channel 0 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT0_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT0_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT1_MASK (0x2U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT1_SHIFT (1U)
+/*! STATUS_BUSERRINT1 - DMA channel 1 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT1_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT1_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT2_MASK (0x4U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT2_SHIFT (2U)
+/*! STATUS_BUSERRINT2 - DMA channel 2 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT2_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT2_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT3_MASK (0x8U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT3_SHIFT (3U)
+/*! STATUS_BUSERRINT3 - DMA channel 3 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT3_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT3_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT4_MASK (0x10U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT4_SHIFT (4U)
+/*! STATUS_BUSERRINT4 - DMA channel 4 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT4_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT4_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT5_MASK (0x20U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT5_SHIFT (5U)
+/*! STATUS_BUSERRINT5 - DMA channel 5 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT5_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT5_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT6_MASK (0x40U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT6_SHIFT (6U)
+/*! STATUS_BUSERRINT6 - DMA channel 6 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT6_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT6_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT7_MASK (0x80U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT7_SHIFT (7U)
+/*! STATUS_BUSERRINT7 - DMA channel 7 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT7_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT7_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT8_MASK (0x100U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT8_SHIFT (8U)
+/*! STATUS_BUSERRINT8 - DMA channel 8 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT8_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT8_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT9_MASK (0x200U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT9_SHIFT (9U)
+/*! STATUS_BUSERRINT9 - DMA channel 9 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT9_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT9_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT10_MASK (0x400U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT10_SHIFT (10U)
+/*! STATUS_BUSERRINT10 - DMA channel 10 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT10_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT10_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT11_MASK (0x800U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT11_SHIFT (11U)
+/*! STATUS_BUSERRINT11 - DMA channel 11 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT11_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT11_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT12_MASK (0x1000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT12_SHIFT (12U)
+/*! STATUS_BUSERRINT12 - DMA channel 12 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT12_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT12_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT13_MASK (0x2000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT13_SHIFT (13U)
+/*! STATUS_BUSERRINT13 - DMA channel 13 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT13_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT13_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT14_MASK (0x4000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT14_SHIFT (14U)
+/*! STATUS_BUSERRINT14 - DMA channel 14 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT14_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT14_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT15_MASK (0x8000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT15_SHIFT (15U)
+/*! STATUS_BUSERRINT15 - DMA channel 15 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT15_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT15_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT16_MASK (0x10000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT16_SHIFT (16U)
+/*! STATUS_BUSERRINT16 - DMA channel 16 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT16_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT16_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT17_MASK (0x20000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT17_SHIFT (17U)
+/*! STATUS_BUSERRINT17 - DMA channel 17 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT17_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT17_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT18_MASK (0x40000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT18_SHIFT (18U)
+/*! STATUS_BUSERRINT18 - DMA channel 18 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT18_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT18_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT19_MASK (0x80000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT19_SHIFT (19U)
+/*! STATUS_BUSERRINT19 - DMA channel 19 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT19_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT19_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT20_MASK (0x100000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT20_SHIFT (20U)
+/*! STATUS_BUSERRINT20 - DMA channel 20 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT20_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT20_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT21_MASK (0x200000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT21_SHIFT (21U)
+/*! STATUS_BUSERRINT21 - DMA channel 21 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT21_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT21_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT22_MASK (0x400000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT22_SHIFT (22U)
+/*! STATUS_BUSERRINT22 - DMA channel 22 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT22_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT22_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT23_MASK (0x800000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT23_SHIFT (23U)
+/*! STATUS_BUSERRINT23 - DMA channel 23 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT23_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT23_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT24_MASK (0x1000000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT24_SHIFT (24U)
+/*! STATUS_BUSERRINT24 - DMA channel 24 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT24_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT24_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT25_MASK (0x2000000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT25_SHIFT (25U)
+/*! STATUS_BUSERRINT25 - DMA channel 25 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT25_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT25_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT26_MASK (0x4000000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT26_SHIFT (26U)
+/*! STATUS_BUSERRINT26 - DMA channel 26 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT26_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT26_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT27_MASK (0x8000000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT27_SHIFT (27U)
+/*! STATUS_BUSERRINT27 - DMA channel 27 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT27_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT27_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT28_MASK (0x10000000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT28_SHIFT (28U)
+/*! STATUS_BUSERRINT28 - DMA channel 28 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT28_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT28_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT29_MASK (0x20000000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT29_SHIFT (29U)
+/*! STATUS_BUSERRINT29 - DMA channel 29 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT29_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT29_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT30_MASK (0x40000000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT30_SHIFT (30U)
+/*! STATUS_BUSERRINT30 - DMA channel 30 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT30_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT30_MASK)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT31_MASK (0x80000000U)
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT31_SHIFT (31U)
+/*! STATUS_BUSERRINT31 - DMA channel 31 bus error interrupt bit
+ * 0b0..no bus error interrupt is generated
+ * 0b1..bus error interrupt is generated
+ */
+#define DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT31_SHIFT)) & DMAC_STATUS_BUSERRINT_STATUS_BUSERRINT31_MASK)
+/*! @} */
+
+/*! @name MASK_ADDRERRINT - DMA Channel source/target address alignment error interrupt mask Registers */
+/*! @{ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT0_MASK (0x1U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT0_SHIFT (0U)
+/*! MASK_ADDRERRINT0 - DMA Channel 0 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT0_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT0_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT1_MASK (0x2U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT1_SHIFT (1U)
+/*! MASK_ADDRERRINT1 - DMA Channel 1 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT1_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT1_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT2_MASK (0x4U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT2_SHIFT (2U)
+/*! MASK_ADDRERRINT2 - DMA Channel 2 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT2_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT2_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT3_MASK (0x8U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT3_SHIFT (3U)
+/*! MASK_ADDRERRINT3 - DMA Channel 3 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT3_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT3_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT4_MASK (0x10U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT4_SHIFT (4U)
+/*! MASK_ADDRERRINT4 - DMA Channel 4 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT4_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT4_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT5_MASK (0x20U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT5_SHIFT (5U)
+/*! MASK_ADDRERRINT5 - DMA Channel 5 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT5_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT5_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT6_MASK (0x40U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT6_SHIFT (6U)
+/*! MASK_ADDRERRINT6 - DMA Channel 6 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT6_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT6_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT7_MASK (0x80U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT7_SHIFT (7U)
+/*! MASK_ADDRERRINT7 - DMA Channel 7 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT7_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT7_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT8_MASK (0x100U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT8_SHIFT (8U)
+/*! MASK_ADDRERRINT8 - DMA Channel 8 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT8_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT8_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT9_MASK (0x200U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT9_SHIFT (9U)
+/*! MASK_ADDRERRINT9 - DMA Channel 9 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT9_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT9_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT10_MASK (0x400U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT10_SHIFT (10U)
+/*! MASK_ADDRERRINT10 - DMA Channel 10 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT10_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT10_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT11_MASK (0x800U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT11_SHIFT (11U)
+/*! MASK_ADDRERRINT11 - DMA Channel 11 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT11_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT11_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT12_MASK (0x1000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT12_SHIFT (12U)
+/*! MASK_ADDRERRINT12 - DMA Channel 12 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT12_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT12_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT13_MASK (0x2000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT13_SHIFT (13U)
+/*! MASK_ADDRERRINT13 - DMA Channel 13 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT13_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT13_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT14_MASK (0x4000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT14_SHIFT (14U)
+/*! MASK_ADDRERRINT14 - DMA Channel 14 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT14_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT14_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT15_MASK (0x8000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT15_SHIFT (15U)
+/*! MASK_ADDRERRINT15 - DMA Channel 15 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT15_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT15_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT16_MASK (0x10000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT16_SHIFT (16U)
+/*! MASK_ADDRERRINT16 - DMA Channel 16 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT16_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT16_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT17_MASK (0x20000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT17_SHIFT (17U)
+/*! MASK_ADDRERRINT17 - DMA Channel 17 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT17_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT17_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT18_MASK (0x40000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT18_SHIFT (18U)
+/*! MASK_ADDRERRINT18 - DMA Channel 18 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT18_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT18_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT19_MASK (0x80000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT19_SHIFT (19U)
+/*! MASK_ADDRERRINT19 - DMA Channel 19 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT19_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT19_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT20_MASK (0x100000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT20_SHIFT (20U)
+/*! MASK_ADDRERRINT20 - DMA Channel 20 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT20_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT20_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT21_MASK (0x200000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT21_SHIFT (21U)
+/*! MASK_ADDRERRINT21 - DMA Channel 21 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT21_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT21_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT22_MASK (0x400000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT22_SHIFT (22U)
+/*! MASK_ADDRERRINT22 - DMA Channel 22 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT22_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT22_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT23_MASK (0x800000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT23_SHIFT (23U)
+/*! MASK_ADDRERRINT23 - DMA Channel 23 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT23_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT23_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT24_MASK (0x1000000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT24_SHIFT (24U)
+/*! MASK_ADDRERRINT24 - DMA Channel 24 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT24_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT24_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT25_MASK (0x2000000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT25_SHIFT (25U)
+/*! MASK_ADDRERRINT25 - DMA Channel 25 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT25_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT25_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT26_MASK (0x4000000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT26_SHIFT (26U)
+/*! MASK_ADDRERRINT26 - DMA Channel 26 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT26_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT26_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT27_MASK (0x8000000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT27_SHIFT (27U)
+/*! MASK_ADDRERRINT27 - DMA Channel 27 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT27_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT27_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT28_MASK (0x10000000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT28_SHIFT (28U)
+/*! MASK_ADDRERRINT28 - DMA Channel 28 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT28_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT28_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT29_MASK (0x20000000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT29_SHIFT (29U)
+/*! MASK_ADDRERRINT29 - DMA Channel 29 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT29_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT29_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT30_MASK (0x40000000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT30_SHIFT (30U)
+/*! MASK_ADDRERRINT30 - DMA Channel 30 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT30_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT30_MASK)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT31_MASK (0x80000000U)
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT31_SHIFT (31U)
+/*! MASK_ADDRERRINT31 - DMA Channel 31 source/target address alignment error interrupt mask bit
+ * 0b0..mask the corresponding address error interrupt
+ * 0b1..unmask the corresponding address error interrupt
+ */
+#define DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT31_SHIFT)) & DMAC_MASK_ADDRERRINT_MASK_ADDRERRINT31_MASK)
+/*! @} */
+
+/*! @name STATUS_ADDRERRINT - DMA Channel source/target address alignment error interrupt Registers */
+/*! @{ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT0_MASK (0x1U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT0_SHIFT (0U)
+/*! STATUS_ADDRERRINT0 - DMA Channel 0 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT0_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT0_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT1_MASK (0x2U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT1_SHIFT (1U)
+/*! STATUS_ADDRERRINT1 - DMA Channel 1 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT1_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT1_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT2_MASK (0x4U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT2_SHIFT (2U)
+/*! STATUS_ADDRERRINT2 - DMA Channel 2 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT2_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT2_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT3_MASK (0x8U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT3_SHIFT (3U)
+/*! STATUS_ADDRERRINT3 - DMA Channel 3 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT3_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT3_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT4_MASK (0x10U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT4_SHIFT (4U)
+/*! STATUS_ADDRERRINT4 - DMA Channel 4 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT4_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT4_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT5_MASK (0x20U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT5_SHIFT (5U)
+/*! STATUS_ADDRERRINT5 - DMA Channel 5 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT5_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT5_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT6_MASK (0x40U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT6_SHIFT (6U)
+/*! STATUS_ADDRERRINT6 - DMA Channel 6 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT6_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT6_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT7_MASK (0x80U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT7_SHIFT (7U)
+/*! STATUS_ADDRERRINT7 - DMA Channel 7 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT7_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT7_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT8_MASK (0x100U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT8_SHIFT (8U)
+/*! STATUS_ADDRERRINT8 - DMA Channel 8 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT8_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT8_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT9_MASK (0x200U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT9_SHIFT (9U)
+/*! STATUS_ADDRERRINT9 - DMA Channel 9 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT9_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT9_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT10_MASK (0x400U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT10_SHIFT (10U)
+/*! STATUS_ADDRERRINT10 - DMA Channel 10 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT10_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT10_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT11_MASK (0x800U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT11_SHIFT (11U)
+/*! STATUS_ADDRERRINT11 - DMA Channel 11 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT11_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT11_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT12_MASK (0x1000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT12_SHIFT (12U)
+/*! STATUS_ADDRERRINT12 - DMA Channel 12 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT12_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT12_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT13_MASK (0x2000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT13_SHIFT (13U)
+/*! STATUS_ADDRERRINT13 - DMA Channel 13 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT13_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT13_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT14_MASK (0x4000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT14_SHIFT (14U)
+/*! STATUS_ADDRERRINT14 - DMA Channel 14 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT14_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT14_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT15_MASK (0x8000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT15_SHIFT (15U)
+/*! STATUS_ADDRERRINT15 - DMA Channel 15 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT15_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT15_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT16_MASK (0x10000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT16_SHIFT (16U)
+/*! STATUS_ADDRERRINT16 - DMA Channel 16 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT16_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT16_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT17_MASK (0x20000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT17_SHIFT (17U)
+/*! STATUS_ADDRERRINT17 - DMA Channel 17 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT17_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT17_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT18_MASK (0x40000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT18_SHIFT (18U)
+/*! STATUS_ADDRERRINT18 - DMA Channel 18 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT18_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT18_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT19_MASK (0x80000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT19_SHIFT (19U)
+/*! STATUS_ADDRERRINT19 - DMA Channel 19 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT19_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT19_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT20_MASK (0x100000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT20_SHIFT (20U)
+/*! STATUS_ADDRERRINT20 - DMA Channel 20 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT20_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT20_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT21_MASK (0x200000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT21_SHIFT (21U)
+/*! STATUS_ADDRERRINT21 - DMA Channel 21 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT21_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT21_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT22_MASK (0x400000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT22_SHIFT (22U)
+/*! STATUS_ADDRERRINT22 - DMA Channel 22 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT22_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT22_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT23_MASK (0x800000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT23_SHIFT (23U)
+/*! STATUS_ADDRERRINT23 - DMA Channel 23 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT23_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT23_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT24_MASK (0x1000000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT24_SHIFT (24U)
+/*! STATUS_ADDRERRINT24 - DMA Channel 24 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT24_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT24_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT25_MASK (0x2000000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT25_SHIFT (25U)
+/*! STATUS_ADDRERRINT25 - DMA Channel 25 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT25_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT25_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT26_MASK (0x4000000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT26_SHIFT (26U)
+/*! STATUS_ADDRERRINT26 - DMA Channel 26 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT26_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT26_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT27_MASK (0x8000000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT27_SHIFT (27U)
+/*! STATUS_ADDRERRINT27 - DMA Channel 27 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT27_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT27_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT28_MASK (0x10000000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT28_SHIFT (28U)
+/*! STATUS_ADDRERRINT28 - DMA Channel 28 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT28_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT28_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT29_MASK (0x20000000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT29_SHIFT (29U)
+/*! STATUS_ADDRERRINT29 - DMA Channel 29 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT29_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT29_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT30_MASK (0x40000000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT30_SHIFT (30U)
+/*! STATUS_ADDRERRINT30 - DMA Channel 30 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT30_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT30_MASK)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT31_MASK (0x80000000U)
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT31_SHIFT (31U)
+/*! STATUS_ADDRERRINT31 - DMA Channel 31 source/target address alignment error interrupt bit
+ * 0b0..no address error interrupt is generated
+ * 0b1..address error interrupt is generated
+ */
+#define DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT31_SHIFT)) & DMAC_STATUS_ADDRERRINT_STATUS_ADDRERRINT31_MASK)
+/*! @} */
+
+/*! @name STATUS_CHLINT - DMA CHANNEL INTERRUPT REGISTER */
+/*! @{ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT0_MASK (0x1U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT0_SHIFT (0U)
+/*! STATUS_CHLINT0 - DMA channel 0 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT0_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT0_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT1_MASK (0x2U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT1_SHIFT (1U)
+/*! STATUS_CHLINT1 - DMA channel 1 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT1(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT1_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT1_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT2_MASK (0x4U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT2_SHIFT (2U)
+/*! STATUS_CHLINT2 - DMA channel 2 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT2(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT2_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT2_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT3_MASK (0x8U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT3_SHIFT (3U)
+/*! STATUS_CHLINT3 - DMA channel 3 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT3(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT3_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT3_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT4_MASK (0x10U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT4_SHIFT (4U)
+/*! STATUS_CHLINT4 - DMA channel 4 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT4(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT4_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT4_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT5_MASK (0x20U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT5_SHIFT (5U)
+/*! STATUS_CHLINT5 - DMA channel 5 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT5(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT5_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT5_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT6_MASK (0x40U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT6_SHIFT (6U)
+/*! STATUS_CHLINT6 - DMA channel 6 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT6(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT6_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT6_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT7_MASK (0x80U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT7_SHIFT (7U)
+/*! STATUS_CHLINT7 - DMA channel 7 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT7(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT7_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT7_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT8_MASK (0x100U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT8_SHIFT (8U)
+/*! STATUS_CHLINT8 - DMA channel 8 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT8(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT8_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT8_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT9_MASK (0x200U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT9_SHIFT (9U)
+/*! STATUS_CHLINT9 - DMA channel 9 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT9(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT9_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT9_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT10_MASK (0x400U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT10_SHIFT (10U)
+/*! STATUS_CHLINT10 - DMA channel 10 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT10(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT10_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT10_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT11_MASK (0x800U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT11_SHIFT (11U)
+/*! STATUS_CHLINT11 - DMA channel 11 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT11(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT11_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT11_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT12_MASK (0x1000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT12_SHIFT (12U)
+/*! STATUS_CHLINT12 - DMA channel 12 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT12(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT12_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT12_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT13_MASK (0x2000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT13_SHIFT (13U)
+/*! STATUS_CHLINT13 - DMA channel 13 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT13(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT13_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT13_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT14_MASK (0x4000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT14_SHIFT (14U)
+/*! STATUS_CHLINT14 - DMA channel 14 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT14(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT14_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT14_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT15_MASK (0x8000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT15_SHIFT (15U)
+/*! STATUS_CHLINT15 - DMA channel 15 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT15(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT15_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT15_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT16_MASK (0x10000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT16_SHIFT (16U)
+/*! STATUS_CHLINT16 - DMA channel 16 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT16(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT16_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT16_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT17_MASK (0x20000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT17_SHIFT (17U)
+/*! STATUS_CHLINT17 - DMA channel 17 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT17(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT17_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT17_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT18_MASK (0x40000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT18_SHIFT (18U)
+/*! STATUS_CHLINT18 - DMA channel 18 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT18(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT18_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT18_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT19_MASK (0x80000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT19_SHIFT (19U)
+/*! STATUS_CHLINT19 - DMA channel 19 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT19(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT19_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT19_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT20_MASK (0x100000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT20_SHIFT (20U)
+/*! STATUS_CHLINT20 - DMA channel 20 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT20(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT20_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT20_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT21_MASK (0x200000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT21_SHIFT (21U)
+/*! STATUS_CHLINT21 - DMA channel 21 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT21(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT21_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT21_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT22_MASK (0x400000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT22_SHIFT (22U)
+/*! STATUS_CHLINT22 - DMA channel 22 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT22(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT22_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT22_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT23_MASK (0x800000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT23_SHIFT (23U)
+/*! STATUS_CHLINT23 - DMA channel 23 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT23(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT23_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT23_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT24_MASK (0x1000000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT24_SHIFT (24U)
+/*! STATUS_CHLINT24 - DMA channel 24 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT24(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT24_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT24_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT25_MASK (0x2000000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT25_SHIFT (25U)
+/*! STATUS_CHLINT25 - DMA channel 25 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT25(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT25_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT25_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT26_MASK (0x4000000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT26_SHIFT (26U)
+/*! STATUS_CHLINT26 - DMA channel 26 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT26(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT26_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT26_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT27_MASK (0x8000000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT27_SHIFT (27U)
+/*! STATUS_CHLINT27 - DMA channel 27 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT27(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT27_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT27_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT28_MASK (0x10000000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT28_SHIFT (28U)
+/*! STATUS_CHLINT28 - DMA channel 28 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT28(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT28_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT28_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT29_MASK (0x20000000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT29_SHIFT (29U)
+/*! STATUS_CHLINT29 - DMA channel 29 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT29(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT29_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT29_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT30_MASK (0x40000000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT30_SHIFT (30U)
+/*! STATUS_CHLINT30 - DMA channel 30 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT30(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT30_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT30_MASK)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT31_MASK (0x80000000U)
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT31_SHIFT (31U)
+/*! STATUS_CHLINT31 - DMA channel 31 interrupt
+ */
+#define DMAC_STATUS_CHLINT_STATUS_CHLINT31(x) (((uint32_t)(((uint32_t)(x)) << DMAC_STATUS_CHLINT_STATUS_CHLINT31_SHIFT)) & DMAC_STATUS_CHLINT_STATUS_CHLINT31_MASK)
+/*! @} */
+
+/*! @name HPROT - THE PROTECTION CONTROL SIGNALS REGISTERS */
+/*! @{ */
+#define DMAC_HPROT_HPROT_MASK (0xFU)
+#define DMAC_HPROT_HPROT_SHIFT (0U)
+/*! HPROT - protection control signals
+ */
+#define DMAC_HPROT_HPROT(x) (((uint32_t)(((uint32_t)(x)) << DMAC_HPROT_HPROT_SHIFT)) & DMAC_HPROT_HPROT_MASK)
+/*! @} */
+
+/*! @name SADR - DMA SOURCE ADDRESS REGISTERS */
+/*! @{ */
+#define DMAC_SADR_SRCADDR0_MASK (0x3U)
+#define DMAC_SADR_SRCADDR0_SHIFT (0U)
+/*! SRCADDR0 - SRCADDR0
+ */
+#define DMAC_SADR_SRCADDR0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_SADR_SRCADDR0_SHIFT)) & DMAC_SADR_SRCADDR0_MASK)
+#define DMAC_SADR_SRCADDR_MASK (0xFFFFFFFCU)
+#define DMAC_SADR_SRCADDR_SHIFT (2U)
+/*! SRCADDR - SOURCE ADDRESS
+ */
+#define DMAC_SADR_SRCADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_SADR_SRCADDR_SHIFT)) & DMAC_SADR_SRCADDR_MASK)
+/*! @} */
+
+/* The count of DMAC_SADR */
+#define DMAC_SADR_COUNT (32U)
+
+/*! @name TADR - DMA TARGET ADDRESS REGISTERS */
+/*! @{ */
+#define DMAC_TADR_TRGADDR0_MASK (0x3U)
+#define DMAC_TADR_TRGADDR0_SHIFT (0U)
+/*! TRGADDR0 - TRGADDR0
+ */
+#define DMAC_TADR_TRGADDR0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_TADR_TRGADDR0_SHIFT)) & DMAC_TADR_TRGADDR0_MASK)
+#define DMAC_TADR_TRGADDR_MASK (0xFFFFFFFCU)
+#define DMAC_TADR_TRGADDR_SHIFT (2U)
+/*! TRGADDR - TARGET ADDRESS
+ */
+#define DMAC_TADR_TRGADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_TADR_TRGADDR_SHIFT)) & DMAC_TADR_TRGADDR_MASK)
+/*! @} */
+
+/* The count of DMAC_TADR */
+#define DMAC_TADR_COUNT (32U)
+
+/*! @name CTRLA - DMA CONTROL REGISTERS A */
+/*! @{ */
+#define DMAC_CTRLA_LEN_MASK (0x1FFFU)
+#define DMAC_CTRLA_LEN_SHIFT (0U)
+/*! LEN - Length of the transfer in bytes
+ */
+#define DMAC_CTRLA_LEN(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CTRLA_LEN_SHIFT)) & DMAC_CTRLA_LEN_MASK)
+#define DMAC_CTRLA_WIDTH_MASK (0x6000U)
+#define DMAC_CTRLA_WIDTH_SHIFT (13U)
+/*! WIDTH - Width
+ * 0b00..reserved for on-chip peripheral-related transactions (1 byte)
+ * 0b01..1 byte
+ * 0b10..half-word (2 bytes)
+ * 0b11..word (4 bytes)
+ */
+#define DMAC_CTRLA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CTRLA_WIDTH_SHIFT)) & DMAC_CTRLA_WIDTH_MASK)
+#define DMAC_CTRLA_TRAN_SIZE_MASK (0x18000U)
+#define DMAC_CTRLA_TRAN_SIZE_SHIFT (15U)
+/*! TRAN_SIZE - Size
+ * 0b00..1
+ * 0b01..4
+ * 0b10..8
+ * 0b11..16
+ */
+#define DMAC_CTRLA_TRAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CTRLA_TRAN_SIZE_SHIFT)) & DMAC_CTRLA_TRAN_SIZE_MASK)
+#define DMAC_CTRLA_TRAN_TYPE_MASK (0x60000U)
+#define DMAC_CTRLA_TRAN_TYPE_SHIFT (17U)
+/*! TRAN_TYPE - Source to target transfer type
+ * 0b00..M2M
+ * 0b01..M2P
+ * 0b10..P2M
+ * 0b11..reserved
+ */
+#define DMAC_CTRLA_TRAN_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CTRLA_TRAN_TYPE_SHIFT)) & DMAC_CTRLA_TRAN_TYPE_MASK)
+#define DMAC_CTRLA_INCTRGADDR_MASK (0x20000000U)
+#define DMAC_CTRLA_INCTRGADDR_SHIFT (29U)
+/*! INCTRGADDR - Target address increment
+ * 0b0..do not increment target address
+ * 0b1..increment target address
+ */
+#define DMAC_CTRLA_INCTRGADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CTRLA_INCTRGADDR_SHIFT)) & DMAC_CTRLA_INCTRGADDR_MASK)
+#define DMAC_CTRLA_INCSRCADDR_MASK (0x40000000U)
+#define DMAC_CTRLA_INCSRCADDR_SHIFT (30U)
+/*! INCSRCADDR - Source address increment
+ * 0b0..do not increment source address
+ * 0b1..stop the running channel
+ */
+#define DMAC_CTRLA_INCSRCADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CTRLA_INCSRCADDR_SHIFT)) & DMAC_CTRLA_INCSRCADDR_MASK)
+/*! @} */
+
+/* The count of DMAC_CTRLA */
+#define DMAC_CTRLA_COUNT (32U)
+
+/*! @name CTRLB - DMA CONTROL REGISTERS B */
+/*! @{ */
+#define DMAC_CTRLB_PERNUM_MASK (0x3FU)
+#define DMAC_CTRLB_PERNUM_SHIFT (0U)
+/*! PERNUM - peripheral number
+ */
+#define DMAC_CTRLB_PERNUM(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CTRLB_PERNUM_SHIFT)) & DMAC_CTRLB_PERNUM_MASK)
+/*! @} */
+
+/* The count of DMAC_CTRLB */
+#define DMAC_CTRLB_COUNT (32U)
+
+/*! @name CHL_EN - DMA CHANNEL ENABLE REGISTERS */
+/*! @{ */
+#define DMAC_CHL_EN_CHL_EN_MASK (0x80000000U)
+#define DMAC_CHL_EN_CHL_EN_SHIFT (31U)
+/*! CHL_EN - Enable/Disable the channel
+ * 0b0..disable the channel
+ * 0b1..enable the channel
+ */
+#define DMAC_CHL_EN_CHL_EN(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CHL_EN_CHL_EN_SHIFT)) & DMAC_CHL_EN_CHL_EN_MASK)
+/*! @} */
+
+/* The count of DMAC_CHL_EN */
+#define DMAC_CHL_EN_COUNT (32U)
+
+/*! @name CHL_STOP - DMA CHANNEL STOP REGISTERS */
+/*! @{ */
+#define DMAC_CHL_STOP_CHL_STOP_MASK (0x80000000U)
+#define DMAC_CHL_STOP_CHL_STOP_SHIFT (31U)
+/*! CHL_STOP - Stop the running channel
+ * 0b0..no impact on the channel
+ * 0b1..stop the running channel
+ */
+#define DMAC_CHL_STOP_CHL_STOP(x) (((uint32_t)(((uint32_t)(x)) << DMAC_CHL_STOP_CHL_STOP_SHIFT)) & DMAC_CHL_STOP_CHL_STOP_MASK)
+/*! @} */
+
+/* The count of DMAC_CHL_STOP */
+#define DMAC_CHL_STOP_COUNT (32U)
+
+/*! @name ACK_DELAY - DMA ACK DELAY CYCLE for single transfer in M2P transfer type Registers */
+/*! @{ */
+#define DMAC_ACK_DELAY_ACK_DELAY_NUM_MASK (0x3FFU)
+#define DMAC_ACK_DELAY_ACK_DELAY_NUM_SHIFT (0U)
+/*! ACK_DELAY_NUM - DMA ACK DELAY CYCLE for single write transaction to peripheral
+ */
+#define DMAC_ACK_DELAY_ACK_DELAY_NUM(x) (((uint32_t)(((uint32_t)(x)) << DMAC_ACK_DELAY_ACK_DELAY_NUM_SHIFT)) & DMAC_ACK_DELAY_ACK_DELAY_NUM_MASK)
+/*! @} */
+
+/*! @name ERR_INFO0 - DMA ERROR INFORMATION REGISTER 0 */
+/*! @{ */
+#define DMAC_ERR_INFO0_ERR_ADDR_MASK (0xFFFFFFFFU)
+#define DMAC_ERR_INFO0_ERR_ADDR_SHIFT (0U)
+/*! ERR_ADDR - ADDRESS INFORMATION RELATED ERROR
+ */
+#define DMAC_ERR_INFO0_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_ERR_INFO0_ERR_ADDR_SHIFT)) & DMAC_ERR_INFO0_ERR_ADDR_MASK)
+/*! @} */
+
+/*! @name ERR_INFO1 - DMA ERROR INFORMATION REGISTER 1 */
+/*! @{ */
+#define DMAC_ERR_INFO1_ERR_CHLNUM_MASK (0xF8000000U)
+#define DMAC_ERR_INFO1_ERR_CHLNUM_SHIFT (27U)
+/*! ERR_CHLNUM - CHANNEL ID INFORMATION RELATED ERROR
+ */
+#define DMAC_ERR_INFO1_ERR_CHLNUM(x) (((uint32_t)(((uint32_t)(x)) << DMAC_ERR_INFO1_ERR_CHLNUM_SHIFT)) & DMAC_ERR_INFO1_ERR_CHLNUM_MASK)
+/*! @} */
+
+/*! @name DIAGNOSE_INFO0 - DMA DIAGNOSE INFORMATION REGISTER 0 */
+/*! @{ */
+#define DMAC_DIAGNOSE_INFO0_DIAGNOSE_ADDR_MASK (0xFFFFFFFFU)
+#define DMAC_DIAGNOSE_INFO0_DIAGNOSE_ADDR_SHIFT (0U)
+/*! DIAGNOSE_ADDR - ADDRESS INFORMATION RELATED DIAGNOSE
+ */
+#define DMAC_DIAGNOSE_INFO0_DIAGNOSE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO0_DIAGNOSE_ADDR_SHIFT)) & DMAC_DIAGNOSE_INFO0_DIAGNOSE_ADDR_MASK)
+/*! @} */
+
+/*! @name DIAGNOSE_INFO1 - DMA DIAGNOSE INFORMATION REGISTER 1 */
+/*! @{ */
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_CHLNUM_MASK (0x1FU)
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_CHLNUM_SHIFT (0U)
+/*! DIAGNOSE_REQ_CHL_DATA_CHLNUM - INDICATE WHICH CHANNEL IS IN SERVICE
+ */
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_CHLNUM(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_CHLNUM_SHIFT)) & DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_CHLNUM_MASK)
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REST_LEN_MASK (0x7FFC0000U)
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REST_LEN_SHIFT (18U)
+/*! DIAGNOSE_REST_LEN - INDICATE THE REMAINING DATA LENGTH OF THE SELESTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REST_LEN(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO1_DIAGNOSE_REST_LEN_SHIFT)) & DMAC_DIAGNOSE_INFO1_DIAGNOSE_REST_LEN_MASK)
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_MASK (0x80000000U)
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_SHIFT (31U)
+/*! DIAGNOSE_REQ_CHL_DATA - INDICATE WHETHER THERE IS A VALID REQUEST
+ */
+#define DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_SHIFT)) & DMAC_DIAGNOSE_INFO1_DIAGNOSE_REQ_CHL_DATA_MASK)
+/*! @} */
+
+/*! @name DIAGNOSE_INFO2 - DMA DIAGNOSE INFORMATION REGISTER 2 */
+/*! @{ */
+#define DMAC_DIAGNOSE_INFO2_DIAGNOSE_CHL_STATE_MASK (0xF0000000U)
+#define DMAC_DIAGNOSE_INFO2_DIAGNOSE_CHL_STATE_SHIFT (28U)
+/*! DIAGNOSE_CHL_STATE - INDICATE THE CHANNEL STATE
+ */
+#define DMAC_DIAGNOSE_INFO2_DIAGNOSE_CHL_STATE(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO2_DIAGNOSE_CHL_STATE_SHIFT)) & DMAC_DIAGNOSE_INFO2_DIAGNOSE_CHL_STATE_MASK)
+/*! @} */
+
+/*! @name DIAGNOSE_INFO3 - DMA DIAGNOSE INFORMATION REGISTER 3 */
+/*! @{ */
+#define DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR0_MASK (0x3U)
+#define DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR0_SHIFT (0U)
+/*! DIAGNOSE_SRC_ADDR0 - INDICATE THE SOURCE ADDRESS 0 OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR0_SHIFT)) & DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR0_MASK)
+#define DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR_MASK (0xFFFFFFFCU)
+#define DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR_SHIFT (2U)
+/*! DIAGNOSE_SRC_ADDR - INDICATE THE SOURCE ADDRESS OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR_SHIFT)) & DMAC_DIAGNOSE_INFO3_DIAGNOSE_SRC_ADDR_MASK)
+/*! @} */
+
+/*! @name DIAGNOSE_INFO4 - DMA DIAGNOSE INFORMATION REGISTER 4 */
+/*! @{ */
+#define DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR0_MASK (0x3U)
+#define DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR0_SHIFT (0U)
+/*! DIAGNOSE_TRG_ADDR0 - INDICATE THE TARGET ADDRESS 0 OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR0_SHIFT)) & DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR0_MASK)
+#define DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR_MASK (0xFFFFFFFCU)
+#define DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR_SHIFT (2U)
+/*! DIAGNOSE_TRG_ADDR - INDICATE THE TARGET ADDRESS OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR_SHIFT)) & DMAC_DIAGNOSE_INFO4_DIAGNOSE_TRG_ADDR_MASK)
+/*! @} */
+
+/*! @name DIAGNOSE_INFO5 - DMA DIAGNOSE INFORMATION REGISTER 5 */
+/*! @{ */
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_WIDTH_MASK (0xC00U)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_WIDTH_SHIFT (10U)
+/*! DIAGNOSE_CTRL_WIDTH - INDICATE THE WIDTH INFORMATION OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_WIDTH_SHIFT)) & DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_WIDTH_MASK)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANTYPE_MASK (0x3000U)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANTYPE_SHIFT (12U)
+/*! DIAGNOSE_CTRL_TRANTYPE - INDICATE THE TRANSFER TYPE INFORMATION OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANTYPE_SHIFT)) & DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANTYPE_MASK)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANSIZE_MASK (0xC000U)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANSIZE_SHIFT (14U)
+/*! DIAGNOSE_CTRL_TRANSIZE - INDICATE THE TRANSFER SIZE INFORMATION OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANSIZE_SHIFT)) & DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_TRANSIZE_MASK)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_LEN_MASK (0x1FFF0000U)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_LEN_SHIFT (16U)
+/*! DIAGNOSE_CTRL_LEN - INDICATE THE LENGTH INFORMATION OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_LEN(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_LEN_SHIFT)) & DMAC_DIAGNOSE_INFO5_DIAGNOSE_CTRL_LEN_MASK)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRTRGADDR_MASK (0x20000000U)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRTRGADDR_SHIFT (29U)
+/*! DIAGNOSE_INCRTRGADDR - INDICATE WHETHER TO INCREASE THE TRG ADDRESS OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRTRGADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRTRGADDR_SHIFT)) & DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRTRGADDR_MASK)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRSRCADDR_MASK (0x40000000U)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRSRCADDR_SHIFT (30U)
+/*! DIAGNOSE_INCRSRCADDR - INDICATE WHETHER TO INCREASE THE SRC ADDRESS OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRSRCADDR(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRSRCADDR_SHIFT)) & DMAC_DIAGNOSE_INFO5_DIAGNOSE_INCRSRCADDR_MASK)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CHL_EN_MASK (0x80000000U)
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CHL_EN_SHIFT (31U)
+/*! DIAGNOSE_CHL_EN - INDICATE THE CHANNEL ENABLE STATE OF THE SELECTED CHANNEL
+ */
+#define DMAC_DIAGNOSE_INFO5_DIAGNOSE_CHL_EN(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO5_DIAGNOSE_CHL_EN_SHIFT)) & DMAC_DIAGNOSE_INFO5_DIAGNOSE_CHL_EN_MASK)
+/*! @} */
+
+/*! @name DIAGNOSE_INFO6 - DMA DIAGNOSE INFORMATION REGISTER 6 */
+/*! @{ */
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_HALFWORD_MASK (0x20000U)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_HALFWORD_SHIFT (17U)
+/*! DIAGNOSE_SPLIT_HALFWORD - INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH
+ */
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_HALFWORD(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_HALFWORD_SHIFT)) & DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_HALFWORD_MASK)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_WORD_MASK (0x40000U)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_WORD_SHIFT (18U)
+/*! DIAGNOSE_SPLIT_WORD - INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH
+ */
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_WORD(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_WORD_SHIFT)) & DMAC_DIAGNOSE_INFO6_DIAGNOSE_SPLIT_WORD_MASK)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SLICECNT_MASK (0x3F80000U)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SLICECNT_SHIFT (19U)
+/*! DIAGNOSE_SLICECNT - INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH
+ */
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_SLICECNT(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO6_DIAGNOSE_SLICECNT_SHIFT)) & DMAC_DIAGNOSE_INFO6_DIAGNOSE_SLICECNT_MASK)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_BURST_MASK (0xC000000U)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_BURST_SHIFT (26U)
+/*! DIAGNOSE_AHB_BURST - INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH
+ */
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_BURST(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_BURST_SHIFT)) & DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_BURST_MASK)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_SIZE_MASK (0x30000000U)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_SIZE_SHIFT (28U)
+/*! DIAGNOSE_AHB_SIZE - INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH
+ */
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_SIZE_SHIFT)) & DMAC_DIAGNOSE_INFO6_DIAGNOSE_AHB_SIZE_MASK)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_WRITE_MASK (0x40000000U)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_WRITE_SHIFT (30U)
+/*! DIAGNOSE_MAS_WRITE - INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH
+ */
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_WRITE(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_WRITE_SHIFT)) & DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_WRITE_MASK)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_READ_MASK (0x80000000U)
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_READ_SHIFT (31U)
+/*! DIAGNOSE_MAS_READ - INDICATE SOME OUTPUT INFO FROM MAIN DATAPATH
+ */
+#define DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_READ(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_READ_SHIFT)) & DMAC_DIAGNOSE_INFO6_DIAGNOSE_MAS_READ_MASK)
+/*! @} */
+
+/*! @name DIAGNOSE_INFO7 - DMA DIAGNOSE INFORMATION REGISTER 7 */
+/*! @{ */
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HRESP_MASK (0x400000U)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HRESP_SHIFT (22U)
+/*! DIAGNOSE_AHB_HRESP - INDICATE SOME AHB MASTER INFO
+ */
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HRESP(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HRESP_SHIFT)) & DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HRESP_MASK)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HREADY_MASK (0x800000U)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HREADY_SHIFT (23U)
+/*! DIAGNOSE_AHB_HREADY - INDICATE SOME AHB MASTER INFO
+ */
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HREADY(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HREADY_SHIFT)) & DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_HREADY_MASK)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_SIZE_MASK (0x7000000U)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_SIZE_SHIFT (24U)
+/*! DIAGNOSE_AHB_SIZE - INDICATE SOME AHB MASTER INFO
+ */
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_SIZE_SHIFT)) & DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_SIZE_MASK)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_TRANS_MASK (0x18000000U)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_TRANS_SHIFT (27U)
+/*! DIAGNOSE_AHB_TRANS - INDICATE SOME AHB MASTER INFO
+ */
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_TRANS(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_TRANS_SHIFT)) & DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_TRANS_MASK)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_BURST_MASK (0xE0000000U)
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_BURST_SHIFT (29U)
+/*! DIAGNOSE_AHB_BURST - INDICATE SOME AHB MASTER INFO
+ */
+#define DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_BURST(x) (((uint32_t)(((uint32_t)(x)) << DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_BURST_SHIFT)) & DMAC_DIAGNOSE_INFO7_DIAGNOSE_AHB_BURST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DMAC_Register_Masks */
+
+
+/* DMAC - Peripheral instance base addresses */
+/** Peripheral DMAC base address */
+#define DMAC_BASE (0x44000000u)
+/** Peripheral DMAC base pointer */
+#define DMAC ((DMAC_Type *)DMAC_BASE)
+/** Array initializer of DMAC peripheral base addresses */
+#define DMAC_BASE_ADDRS { DMAC_BASE }
+/** Array initializer of DMAC peripheral base pointers */
+#define DMAC_BASE_PTRS { DMAC }
+/** Interrupt vectors for the DMAC peripheral type */
+#define DMAC_IRQS { DMAC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLASHC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLASHC_Peripheral_Access_Layer FLASHC Peripheral Access Layer
+ * @{
+ */
+
+/** FLASHC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t FCCR; /**< Flash Controller Configuration Register, offset: 0x0 */
+ __IO uint32_t FCTR; /**< Flash Controller Timing Register, offset: 0x4 */
+ __IO uint32_t FCSR; /**< Flash Controller Status Register, offset: 0x8 */
+ __IO uint32_t FCACR; /**< Flash Controller Auxiliary Configuration Register, offset: 0xC */
+ __IO uint32_t FCHCR; /**< Flash Controller Hit Count Register, offset: 0x10 */
+ __IO uint32_t FCMCR; /**< Flash Controller Miss Count Register, offset: 0x14 */
+ __IO uint32_t FAOFFR; /**< Flash Address Offset Register, offset: 0x18 */
+ __IO uint32_t FADDMAT; /**< Flash Address Match register, offset: 0x1C */
+ __IO uint32_t FWAITR; /**< Flash Wait Register, offset: 0x20 */
+ __IO uint32_t FCCR2; /**< Flash Controller Configurationb Register2, offset: 0x24 */
+ __IO uint32_t FINSTR; /**< Flash Instruction Register, offset: 0x28 */
+ __IO uint32_t FRMR; /**< Flash Read Mode Register, offset: 0x2C */
+} FLASHC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FLASHC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLASHC_Register_Masks FLASHC Register Masks
+ * @{
+ */
+
+/*! @name FCCR - Flash Controller Configuration Register */
+/*! @{ */
+#define FLASHC_FCCR_CMD_TYPE_MASK (0xFU)
+#define FLASHC_FCCR_CMD_TYPE_SHIFT (0U)
+/*! CMD_TYPE - Serial Flash Command typeclocks (based on this Command Type field for Winbond devices)
+ */
+#define FLASHC_FCCR_CMD_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR_CMD_TYPE_SHIFT)) & FLASHC_FCCR_CMD_TYPE_MASK)
+#define FLASHC_FCCR_CLK_PRESCALE_MASK (0x1F00U)
+#define FLASHC_FCCR_CLK_PRESCALE_SHIFT (8U)
+/*! CLK_PRESCALE - Serial interface clock prescaler (from base SPI clock)
+ */
+#define FLASHC_FCCR_CLK_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR_CLK_PRESCALE_SHIFT)) & FLASHC_FCCR_CLK_PRESCALE_MASK)
+#define FLASHC_FCCR_CLK_POL_MASK (0x4000U)
+#define FLASHC_FCCR_CLK_POL_SHIFT (14U)
+/*! CLK_POL - Serial Interface Clock Polarity
+ * 0b0..Serial Interface clock is LOW when inactive.
+ * 0b1..Serial Interface clock is HIGH when inactive.
+ */
+#define FLASHC_FCCR_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR_CLK_POL_SHIFT)) & FLASHC_FCCR_CLK_POL_MASK)
+#define FLASHC_FCCR_CLK_PHA_MASK (0x8000U)
+#define FLASHC_FCCR_CLK_PHA_SHIFT (15U)
+/*! CLK_PHA - Serial Interface Clock Phase
+ * 0b0..Data is captured on the rising edge of the serial clock when CLK_POL=0 and on the falling edge when CLK_POL=1.
+ * 0b1..Data is captured on the falling edge of the serial clock when CLK_POL=0 and on the rising edge when CLK_POL=1.
+ */
+#define FLASHC_FCCR_CLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR_CLK_PHA_SHIFT)) & FLASHC_FCCR_CLK_PHA_MASK)
+#define FLASHC_FCCR_SRAM_MODE_EN_MASK (0x10000000U)
+#define FLASHC_FCCR_SRAM_MODE_EN_SHIFT (28U)
+/*! SRAM_MODE_EN - SRAM Mode Enable
+ */
+#define FLASHC_FCCR_SRAM_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR_SRAM_MODE_EN_SHIFT)) & FLASHC_FCCR_SRAM_MODE_EN_MASK)
+#define FLASHC_FCCR_CACHE_LINE_FLUSH_MASK (0x20000000U)
+#define FLASHC_FCCR_CACHE_LINE_FLUSH_SHIFT (29U)
+/*! CACHE_LINE_FLUSH - Cache Line Flush
+ */
+#define FLASHC_FCCR_CACHE_LINE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR_CACHE_LINE_FLUSH_SHIFT)) & FLASHC_FCCR_CACHE_LINE_FLUSH_MASK)
+#define FLASHC_FCCR_CACHE_EN_MASK (0x40000000U)
+#define FLASHC_FCCR_CACHE_EN_SHIFT (30U)
+/*! CACHE_EN - Flash cache enable
+ */
+#define FLASHC_FCCR_CACHE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR_CACHE_EN_SHIFT)) & FLASHC_FCCR_CACHE_EN_MASK)
+#define FLASHC_FCCR_FLASHC_PAD_EN_MASK (0x80000000U)
+#define FLASHC_FCCR_FLASHC_PAD_EN_SHIFT (31U)
+/*! FLASHC_PAD_EN - Flashc pad enable
+ * 0b0..APB QSPI connects to the Flash device.
+ * 0b1..Flashc connects to the Flash device.
+ */
+#define FLASHC_FCCR_FLASHC_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR_FLASHC_PAD_EN_SHIFT)) & FLASHC_FCCR_FLASHC_PAD_EN_MASK)
+/*! @} */
+
+/*! @name FCTR - Flash Controller Timing Register */
+/*! @{ */
+#define FLASHC_FCTR_DIN_DLY_MASK (0x3U)
+#define FLASHC_FCTR_DIN_DLY_SHIFT (0U)
+/*! DIN_DLY - Data Input Delay
+ */
+#define FLASHC_FCTR_DIN_DLY(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCTR_DIN_DLY_SHIFT)) & FLASHC_FCTR_DIN_DLY_MASK)
+#define FLASHC_FCTR_CLK_IN_DLY_MASK (0xCU)
+#define FLASHC_FCTR_CLK_IN_DLY_SHIFT (2U)
+/*! CLK_IN_DLY - Clock Input Delay
+ */
+#define FLASHC_FCTR_CLK_IN_DLY(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCTR_CLK_IN_DLY_SHIFT)) & FLASHC_FCTR_CLK_IN_DLY_MASK)
+#define FLASHC_FCTR_CLK_CAPT_EDGE_MASK (0x10U)
+#define FLASHC_FCTR_CLK_CAPT_EDGE_SHIFT (4U)
+/*! CLK_CAPT_EDGE - Serial Interface data capture clock edge
+ */
+#define FLASHC_FCTR_CLK_CAPT_EDGE(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCTR_CLK_CAPT_EDGE_SHIFT)) & FLASHC_FCTR_CLK_CAPT_EDGE_MASK)
+#define FLASHC_FCTR_CLK_OUT_DLY_MASK (0x60U)
+#define FLASHC_FCTR_CLK_OUT_DLY_SHIFT (5U)
+/*! CLK_OUT_DLY - Add delay on the outgoing Clock to the flash.
+ */
+#define FLASHC_FCTR_CLK_OUT_DLY(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCTR_CLK_OUT_DLY_SHIFT)) & FLASHC_FCTR_CLK_OUT_DLY_MASK)
+/*! @} */
+
+/*! @name FCSR - Flash Controller Status Register */
+/*! @{ */
+#define FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK (0x1U)
+#define FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_SHIFT (0U)
+/*! CONT_RD_MD_EXIT_DONE - Continuous Read Mode Exit status
+ * 0b0..continuous read mode exit not complete.
+ * 0b1..continuous read mode exit complete.
+ */
+#define FLASHC_FCSR_CONT_RD_MD_EXIT_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_SHIFT)) & FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK)
+/*! @} */
+
+/*! @name FCACR - Flash Controller Auxiliary Configuration Register */
+/*! @{ */
+#define FLASHC_FCACR_HIT_CNT_EN_MASK (0x1U)
+#define FLASHC_FCACR_HIT_CNT_EN_SHIFT (0U)
+/*! HIT_CNT_EN - Miss Count Enable
+ * 0b0..Disable the counting of hits.
+ * 0b1..Enable the counting of number of hits to the cache.
+ */
+#define FLASHC_FCACR_HIT_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCACR_HIT_CNT_EN_SHIFT)) & FLASHC_FCACR_HIT_CNT_EN_MASK)
+#define FLASHC_FCACR_MISS_CNT_EN_MASK (0x2U)
+#define FLASHC_FCACR_MISS_CNT_EN_SHIFT (1U)
+/*! MISS_CNT_EN - Miss Count Enable
+ * 0b0..Disable the counting of misses.
+ * 0b1..Enable the counting of number of misses to the cache.
+ */
+#define FLASHC_FCACR_MISS_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCACR_MISS_CNT_EN_SHIFT)) & FLASHC_FCACR_MISS_CNT_EN_MASK)
+#define FLASHC_FCACR_ADDR_MATCH_EN_MASK (0x4U)
+#define FLASHC_FCACR_ADDR_MATCH_EN_SHIFT (2U)
+/*! ADDR_MATCH_EN - Address Match Enable
+ * 0b0..disable Counting of Misses to a specific address
+ * 0b1..enable Counting of Misses to a specific address defined in FADDMAT
+ */
+#define FLASHC_FCACR_ADDR_MATCH_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCACR_ADDR_MATCH_EN_SHIFT)) & FLASHC_FCACR_ADDR_MATCH_EN_MASK)
+#define FLASHC_FCACR_OFFSET_EN_MASK (0x8U)
+#define FLASHC_FCACR_OFFSET_EN_SHIFT (3U)
+/*! OFFSET_EN - Address Offset Enable
+ * 0b0..All Flash Memory accesses Do not use Address Offset register.
+ * 0b1..Using Address Offset defined in FAOFFR is Enabled for all Flash Memory accesses.
+ */
+#define FLASHC_FCACR_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCACR_OFFSET_EN_SHIFT)) & FLASHC_FCACR_OFFSET_EN_MASK)
+/*! @} */
+
+/*! @name FCHCR - Flash Controller Hit Count Register */
+/*! @{ */
+#define FLASHC_FCHCR_HIT_COUNT_MASK (0xFFFFFFFFU)
+#define FLASHC_FCHCR_HIT_COUNT_SHIFT (0U)
+/*! HIT_COUNT - Hit Counter
+ */
+#define FLASHC_FCHCR_HIT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCHCR_HIT_COUNT_SHIFT)) & FLASHC_FCHCR_HIT_COUNT_MASK)
+/*! @} */
+
+/*! @name FCMCR - Flash Controller Miss Count Register */
+/*! @{ */
+#define FLASHC_FCMCR_MISS_COUNT_MASK (0xFFFFFFFFU)
+#define FLASHC_FCMCR_MISS_COUNT_SHIFT (0U)
+/*! MISS_COUNT - Hit Counter
+ */
+#define FLASHC_FCMCR_MISS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCMCR_MISS_COUNT_SHIFT)) & FLASHC_FCMCR_MISS_COUNT_MASK)
+/*! @} */
+
+/*! @name FAOFFR - Flash Address Offset Register */
+/*! @{ */
+#define FLASHC_FAOFFR_OFFSET_VAL_MASK (0xFFFFFFFFU)
+#define FLASHC_FAOFFR_OFFSET_VAL_SHIFT (0U)
+/*! OFFSET_VAL - Flash Address Offset value
+ */
+#define FLASHC_FAOFFR_OFFSET_VAL(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FAOFFR_OFFSET_VAL_SHIFT)) & FLASHC_FAOFFR_OFFSET_VAL_MASK)
+/*! @} */
+
+/*! @name FADDMAT - Flash Address Match register */
+/*! @{ */
+#define FLASHC_FADDMAT_ADDR_MASK (0xFFFFFFFFU)
+#define FLASHC_FADDMAT_ADDR_SHIFT (0U)
+/*! ADDR - Flash Memory address to compare and match
+ */
+#define FLASHC_FADDMAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FADDMAT_ADDR_SHIFT)) & FLASHC_FADDMAT_ADDR_MASK)
+/*! @} */
+
+/*! @name FWAITR - Flash Wait Register */
+/*! @{ */
+#define FLASHC_FWAITR_ZWAIT_MASK (0x1U)
+#define FLASHC_FWAITR_ZWAIT_SHIFT (0U)
+/*! ZWAIT - Zero Wait.
+ */
+#define FLASHC_FWAITR_ZWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FWAITR_ZWAIT_SHIFT)) & FLASHC_FWAITR_ZWAIT_MASK)
+/*! @} */
+
+/*! @name FCCR2 - Flash Controller Configurationb Register2 */
+/*! @{ */
+#define FLASHC_FCCR2_INSTR_CNT_MASK (0x3U)
+#define FLASHC_FCCR2_INSTR_CNT_SHIFT (0U)
+/*! INSTR_CNT - Instruction Count
+ * 0b00..0 bytes.
+ * 0b01..1 byte
+ * 0b10..2 bytes.
+ * 0b11..Reserved.
+ */
+#define FLASHC_FCCR2_INSTR_CNT(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR2_INSTR_CNT_SHIFT)) & FLASHC_FCCR2_INSTR_CNT_MASK)
+#define FLASHC_FCCR2_ADDR_CNT_MASK (0x70U)
+#define FLASHC_FCCR2_ADDR_CNT_SHIFT (4U)
+/*! ADDR_CNT - Address Count
+ * 0b000..0 bytes.
+ * 0b001..1 byte.
+ * 0b010..2 bytes.
+ * 0b011..3 bytes.
+ * 0b100..4 bytes.
+ * 0b101..reserved
+ * 0b110..reserved
+ * 0b111..reserved
+ */
+#define FLASHC_FCCR2_ADDR_CNT(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR2_ADDR_CNT_SHIFT)) & FLASHC_FCCR2_ADDR_CNT_MASK)
+#define FLASHC_FCCR2_RM_CNT_MASK (0x300U)
+#define FLASHC_FCCR2_RM_CNT_SHIFT (8U)
+/*! RM_CNT - Read Mode Count
+ * 0b00..0 bytes.
+ * 0b01..1 byte.
+ * 0b10..2 bytes.
+ * 0b11..Reserved.
+ */
+#define FLASHC_FCCR2_RM_CNT(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR2_RM_CNT_SHIFT)) & FLASHC_FCCR2_RM_CNT_MASK)
+#define FLASHC_FCCR2_DUMMY_CNT_MASK (0x3000U)
+#define FLASHC_FCCR2_DUMMY_CNT_SHIFT (12U)
+/*! DUMMY_CNT - Dummy count
+ * 0b00..0 bytes.
+ * 0b01..1 byte.
+ * 0b10..2 bytes.
+ * 0b11..Reserved.
+ */
+#define FLASHC_FCCR2_DUMMY_CNT(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR2_DUMMY_CNT_SHIFT)) & FLASHC_FCCR2_DUMMY_CNT_MASK)
+#define FLASHC_FCCR2_BYTE_LEN_MASK (0x8000000U)
+#define FLASHC_FCCR2_BYTE_LEN_SHIFT (27U)
+/*! BYTE_LEN - Byte length
+ * 0b0..1 byte.
+ * 0b1..4 bytes.
+ */
+#define FLASHC_FCCR2_BYTE_LEN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR2_BYTE_LEN_SHIFT)) & FLASHC_FCCR2_BYTE_LEN_MASK)
+#define FLASHC_FCCR2_ADDR_PIN_MASK (0x10000000U)
+#define FLASHC_FCCR2_ADDR_PIN_SHIFT (28U)
+/*! ADDR_PIN - Address transfer pins
+ * 0b0..Use one pin.
+ * 0b1..Use number of pins as indicated by DATA_PIN field in this register.
+ */
+#define FLASHC_FCCR2_ADDR_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR2_ADDR_PIN_SHIFT)) & FLASHC_FCCR2_ADDR_PIN_MASK)
+#define FLASHC_FCCR2_DATA_PIN_MASK (0x60000000U)
+#define FLASHC_FCCR2_DATA_PIN_SHIFT (29U)
+/*! DATA_PIN - Data transfer pins
+ * 0b00..Use 1 pin for data.
+ * 0b01..Use 2 pins for data.
+ * 0b10..Use 4 pins for data.
+ * 0b11..Reserved.
+ */
+#define FLASHC_FCCR2_DATA_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR2_DATA_PIN_SHIFT)) & FLASHC_FCCR2_DATA_PIN_MASK)
+#define FLASHC_FCCR2_USE_CFG_OVRD_MASK (0x80000000U)
+#define FLASHC_FCCR2_USE_CFG_OVRD_SHIFT (31U)
+/*! USE_CFG_OVRD - Use Configuration Override
+ * 0b0..Use FCCR.CMD_TYPE to determine/build Flash command/transfer
+ * 0b1..Use Configuration FCCR2 to determine/build Flash Command/transfer
+ */
+#define FLASHC_FCCR2_USE_CFG_OVRD(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FCCR2_USE_CFG_OVRD_SHIFT)) & FLASHC_FCCR2_USE_CFG_OVRD_MASK)
+/*! @} */
+
+/*! @name FINSTR - Flash Instruction Register */
+/*! @{ */
+#define FLASHC_FINSTR_INSTR_MASK (0xFFFFU)
+#define FLASHC_FINSTR_INSTR_SHIFT (0U)
+/*! INSTR - Flash Instruction
+ */
+#define FLASHC_FINSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FINSTR_INSTR_SHIFT)) & FLASHC_FINSTR_INSTR_MASK)
+/*! @} */
+
+/*! @name FRMR - Flash Read Mode Register */
+/*! @{ */
+#define FLASHC_FRMR_RDMODE_MASK (0xFFFFU)
+#define FLASHC_FRMR_RDMODE_SHIFT (0U)
+/*! RDMODE - Flash Read Mode
+ */
+#define FLASHC_FRMR_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << FLASHC_FRMR_RDMODE_SHIFT)) & FLASHC_FRMR_RDMODE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group FLASHC_Register_Masks */
+
+
+/* FLASHC - Peripheral instance base addresses */
+/** Peripheral FLASHC base address */
+#define FLASHC_BASE (0x44003000u)
+/** Peripheral FLASHC base pointer */
+#define FLASHC ((FLASHC_Type *)FLASHC_BASE)
+/** Array initializer of FLASHC peripheral base addresses */
+#define FLASHC_BASE_ADDRS { FLASHC_BASE }
+/** Array initializer of FLASHC peripheral base pointers */
+#define FLASHC_BASE_PTRS { FLASHC }
+
+/*!
+ * @}
+ */ /* end of group FLASHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __I uint32_t GPLR_REG[3]; /**< GPIO Pin Level Register0..GPIO Pin Level Register2, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t GPDR_REG[3]; /**< GPIO Pin Direction Register0..GPIO Pin Direction Register2, array offset: 0xC, array step: 0x4 */
+ __O uint32_t GPSR_REG[3]; /**< GPIO Pin Output Set Register 0..GPIO Pin Output Set Register 2, array offset: 0x18, array step: 0x4 */
+ __O uint32_t GPCR_REG[3]; /**< GPIO Pin Output Clear Register 0..GPIO Pin Output Clear Register 2, array offset: 0x24, array step: 0x4 */
+ __IO uint32_t GRER_REG[3]; /**< GPIO Rising Edge detect Enable Register 0..GPIO Rising Edge detect Enable Register 2, array offset: 0x30, array step: 0x4 */
+ __IO uint32_t GFER_REG[3]; /**< GPIO Falling Edge detect Enable Register 0..GPIO Falling Edge detect Enable Register 2, array offset: 0x3C, array step: 0x4 */
+ __IO uint32_t GEDR_REG[3]; /**< GPIO Edge detect Status Register 0..GPIO Edge detect Status Register 2, array offset: 0x48, array step: 0x4 */
+ __O uint32_t GSDR_REG[3]; /**< GPIO Pin Bitwise Set Direction Register 0..GPIO Pin Bitwise Set Direction Register 2, array offset: 0x54, array step: 0x4 */
+ __O uint32_t GCDR_REG[3]; /**< GPIO Pin Bitwise Clear Direction Register 0..GPIO Pin Bitwise Clear Direction Register 2, array offset: 0x60, array step: 0x4 */
+ __O uint32_t GSRER_REG[3]; /**< GPIO Bitwise Set Rising Edge detect Enable Register 0..GPIO Bitwise set Rising Edge detect Enable Register 2, array offset: 0x6C, array step: 0x4 */
+ __O uint32_t GCRER_REG[3]; /**< GPIO Bitwise Clear Rising Edge detect Enable Register 0..GPIO Bitwise Clear Rising Edge detect Enable Register 2, array offset: 0x78, array step: 0x4 */
+ __O uint32_t GSFER_REG[3]; /**< GPIO Bitwise Set Falling Edge detect Enable Register 0..GPIO Bitwise set Falling Edge detect Enable Register 2, array offset: 0x84, array step: 0x4 */
+ __O uint32_t GCFER_REG[3]; /**< GPIO Bitwise Clear Falling Edge detect Enable Register 0..GPIO Bitwise Clear Falling Edge detect Enable Register 2, array offset: 0x90, array step: 0x4 */
+ __IO uint32_t APMASK_REG[3]; /**< GPIO Bitwise mask of Edge detect Status Register 0..GPIO Bitwise mask of Edge detect Status Register 2, array offset: 0x9C, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name GPLR_REG - GPIO Pin Level Register0..GPIO Pin Level Register2 */
+/*! @{ */
+#define GPIO_GPLR_REG_GPLR_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GPLR_REG_GPLR_REG0_SHIFT (0U)
+/*! GPLR_REG0 - GPLR Reg0
+ * 0b00000000000000000000000000000000..Port State Low
+ * 0b00000000000000000000000000000001..Port State High
+ */
+#define GPIO_GPLR_REG_GPLR_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPLR_REG_GPLR_REG0_SHIFT)) & GPIO_GPLR_REG_GPLR_REG0_MASK)
+#define GPIO_GPLR_REG_GPLR_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GPLR_REG_GPLR_REG1_SHIFT (0U)
+/*! GPLR_REG1 - GPLR Reg1
+ * 0b00000000000000000000000000000000..Port State Low
+ * 0b00000000000000000000000000000001..Port State High
+ */
+#define GPIO_GPLR_REG_GPLR_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPLR_REG_GPLR_REG1_SHIFT)) & GPIO_GPLR_REG_GPLR_REG1_MASK)
+#define GPIO_GPLR_REG_GPLR_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GPLR_REG_GPLR_REG2_SHIFT (0U)
+/*! GPLR_REG2 - GPLR Reg2
+ * 0b00000000000000000000000000000000..Port State Low
+ * 0b00000000000000000000000000000001..Port State High
+ */
+#define GPIO_GPLR_REG_GPLR_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPLR_REG_GPLR_REG2_SHIFT)) & GPIO_GPLR_REG_GPLR_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GPLR_REG */
+#define GPIO_GPLR_REG_COUNT (3U)
+
+/*! @name GPDR_REG - GPIO Pin Direction Register0..GPIO Pin Direction Register2 */
+/*! @{ */
+#define GPIO_GPDR_REG_GPDR_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GPDR_REG_GPDR_REG0_SHIFT (0U)
+/*! GPDR_REG0 - GPDR Reg0
+ * 0b00000000000000000000000000000000..Input port
+ * 0b00000000000000000000000000000001..Output Port
+ */
+#define GPIO_GPDR_REG_GPDR_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPDR_REG_GPDR_REG0_SHIFT)) & GPIO_GPDR_REG_GPDR_REG0_MASK)
+#define GPIO_GPDR_REG_GPDR_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GPDR_REG_GPDR_REG1_SHIFT (0U)
+/*! GPDR_REG1 - GPDR Reg1
+ * 0b00000000000000000000000000000000..Input port
+ * 0b00000000000000000000000000000001..Output Port
+ */
+#define GPIO_GPDR_REG_GPDR_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPDR_REG_GPDR_REG1_SHIFT)) & GPIO_GPDR_REG_GPDR_REG1_MASK)
+#define GPIO_GPDR_REG_GPDR_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GPDR_REG_GPDR_REG2_SHIFT (0U)
+/*! GPDR_REG2 - GPDR Reg2
+ * 0b00000000000000000000000000000000..Input port
+ * 0b00000000000000000000000000000001..Output Port
+ */
+#define GPIO_GPDR_REG_GPDR_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPDR_REG_GPDR_REG2_SHIFT)) & GPIO_GPDR_REG_GPDR_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GPDR_REG */
+#define GPIO_GPDR_REG_COUNT (3U)
+
+/*! @name GPSR_REG - GPIO Pin Output Set Register 0..GPIO Pin Output Set Register 2 */
+/*! @{ */
+#define GPIO_GPSR_REG_GPSR_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GPSR_REG_GPSR_REG0_SHIFT (0U)
+/*! GPSR_REG0 - GPSR Reg0
+ * 0b00000000000000000000000000000000..
+ * 0b00000000000000000000000000000001..Port set if GPIO is configured as output
+ */
+#define GPIO_GPSR_REG_GPSR_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPSR_REG_GPSR_REG0_SHIFT)) & GPIO_GPSR_REG_GPSR_REG0_MASK)
+#define GPIO_GPSR_REG_GPSR_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GPSR_REG_GPSR_REG1_SHIFT (0U)
+/*! GPSR_REG1 - GPSR Reg1
+ * 0b00000000000000000000000000000000..
+ * 0b00000000000000000000000000000001..Port set if GPIO is configured as output
+ */
+#define GPIO_GPSR_REG_GPSR_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPSR_REG_GPSR_REG1_SHIFT)) & GPIO_GPSR_REG_GPSR_REG1_MASK)
+#define GPIO_GPSR_REG_GPSR_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GPSR_REG_GPSR_REG2_SHIFT (0U)
+/*! GPSR_REG2 - GPSR Reg2
+ * 0b00000000000000000000000000000000..
+ * 0b00000000000000000000000000000001..Port set if GPIO is configured as output
+ */
+#define GPIO_GPSR_REG_GPSR_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPSR_REG_GPSR_REG2_SHIFT)) & GPIO_GPSR_REG_GPSR_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GPSR_REG */
+#define GPIO_GPSR_REG_COUNT (3U)
+
+/*! @name GPCR_REG - GPIO Pin Output Clear Register 0..GPIO Pin Output Clear Register 2 */
+/*! @{ */
+#define GPIO_GPCR_REG_GPCR_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GPCR_REG_GPCR_REG0_SHIFT (0U)
+/*! GPCR_REG0 - GPCR Reg0
+ * 0b00000000000000000000000000000000..
+ * 0b00000000000000000000000000000001..Port Clear if GPIO is configured as output
+ */
+#define GPIO_GPCR_REG_GPCR_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPCR_REG_GPCR_REG0_SHIFT)) & GPIO_GPCR_REG_GPCR_REG0_MASK)
+#define GPIO_GPCR_REG_GPCR_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GPCR_REG_GPCR_REG1_SHIFT (0U)
+/*! GPCR_REG1 - GPCR Reg1
+ * 0b00000000000000000000000000000000..
+ * 0b00000000000000000000000000000001..Port Clear if GPIO is configured as output
+ */
+#define GPIO_GPCR_REG_GPCR_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPCR_REG_GPCR_REG1_SHIFT)) & GPIO_GPCR_REG_GPCR_REG1_MASK)
+#define GPIO_GPCR_REG_GPCR_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GPCR_REG_GPCR_REG2_SHIFT (0U)
+/*! GPCR_REG2 - GPCR Reg2
+ * 0b00000000000000000000000000000000..
+ * 0b00000000000000000000000000000001..Port Clear if GPIO is configured as output
+ */
+#define GPIO_GPCR_REG_GPCR_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GPCR_REG_GPCR_REG2_SHIFT)) & GPIO_GPCR_REG_GPCR_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GPCR_REG */
+#define GPIO_GPCR_REG_COUNT (3U)
+
+/*! @name GRER_REG - GPIO Rising Edge detect Enable Register 0..GPIO Rising Edge detect Enable Register 2 */
+/*! @{ */
+#define GPIO_GRER_REG_GRER_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GRER_REG_GRER_REG0_SHIFT (0U)
+/*! GRER_REG0 - GRER Reg0
+ * 0b00000000000000000000000000000000..Disable Rising Edge detection
+ * 0b00000000000000000000000000000001..Set corresponding GEDR Status bit when Rising edge is detected on GPIO input
+ */
+#define GPIO_GRER_REG_GRER_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GRER_REG_GRER_REG0_SHIFT)) & GPIO_GRER_REG_GRER_REG0_MASK)
+#define GPIO_GRER_REG_GRER_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GRER_REG_GRER_REG1_SHIFT (0U)
+/*! GRER_REG1 - GRER Reg1
+ * 0b00000000000000000000000000000000..Disable Rising Edge detection
+ * 0b00000000000000000000000000000001..Set corresponding GEDR Status bit when Rising edge is detected on GPIO input
+ */
+#define GPIO_GRER_REG_GRER_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GRER_REG_GRER_REG1_SHIFT)) & GPIO_GRER_REG_GRER_REG1_MASK)
+#define GPIO_GRER_REG_GRER_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GRER_REG_GRER_REG2_SHIFT (0U)
+/*! GRER_REG2 - GRER Reg2
+ * 0b00000000000000000000000000000000..Disable Rising Edge detection
+ * 0b00000000000000000000000000000001..Set corresponding GEDR Status bit when Rising edge is detected on GPIO input
+ */
+#define GPIO_GRER_REG_GRER_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GRER_REG_GRER_REG2_SHIFT)) & GPIO_GRER_REG_GRER_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GRER_REG */
+#define GPIO_GRER_REG_COUNT (3U)
+
+/*! @name GFER_REG - GPIO Falling Edge detect Enable Register 0..GPIO Falling Edge detect Enable Register 2 */
+/*! @{ */
+#define GPIO_GFER_REG_GFER_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GFER_REG_GFER_REG0_SHIFT (0U)
+/*! GFER_REG0 - GFER Reg0
+ * 0b00000000000000000000000000000000..Disable Falling Edge detection
+ * 0b00000000000000000000000000000001..Set corresponding GEDR Status bit when Falling edge is detected on GPIO input
+ */
+#define GPIO_GFER_REG_GFER_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GFER_REG_GFER_REG0_SHIFT)) & GPIO_GFER_REG_GFER_REG0_MASK)
+#define GPIO_GFER_REG_GFER_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GFER_REG_GFER_REG1_SHIFT (0U)
+/*! GFER_REG1 - GFER Reg1
+ * 0b00000000000000000000000000000000..Disable Falling Edge detection
+ * 0b00000000000000000000000000000001..Set corresponding GEDR Status bit when Falling edge is detected on GPIO input
+ */
+#define GPIO_GFER_REG_GFER_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GFER_REG_GFER_REG1_SHIFT)) & GPIO_GFER_REG_GFER_REG1_MASK)
+#define GPIO_GFER_REG_GFER_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GFER_REG_GFER_REG2_SHIFT (0U)
+/*! GFER_REG2 - GFER Reg2
+ * 0b00000000000000000000000000000000..Disable Falling Edge detection
+ * 0b00000000000000000000000000000001..Set corresponding GEDR Status bit when Falling edge is detected on GPIO input
+ */
+#define GPIO_GFER_REG_GFER_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GFER_REG_GFER_REG2_SHIFT)) & GPIO_GFER_REG_GFER_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GFER_REG */
+#define GPIO_GFER_REG_COUNT (3U)
+
+/*! @name GEDR_REG - GPIO Edge detect Status Register 0..GPIO Edge detect Status Register 2 */
+/*! @{ */
+#define GPIO_GEDR_REG_GEDR_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GEDR_REG_GEDR_REG0_SHIFT (0U)
+/*! GEDR_REG0 - GEDR Reg0
+ * 0b00000000000000000000000000000000..No edge detected on a port as specified by GRERx or GFERx
+ * 0b00000000000000000000000000000001..Edge detected on a port as specified by GRERx or GFERx
+ */
+#define GPIO_GEDR_REG_GEDR_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GEDR_REG_GEDR_REG0_SHIFT)) & GPIO_GEDR_REG_GEDR_REG0_MASK)
+#define GPIO_GEDR_REG_GEDR_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GEDR_REG_GEDR_REG1_SHIFT (0U)
+/*! GEDR_REG1 - GEDR Reg1
+ * 0b00000000000000000000000000000000..No edge detected on a port as specified by GRERx or GFERx
+ * 0b00000000000000000000000000000001..Edge detected on a port as specified by GRERx or GFERx
+ */
+#define GPIO_GEDR_REG_GEDR_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GEDR_REG_GEDR_REG1_SHIFT)) & GPIO_GEDR_REG_GEDR_REG1_MASK)
+#define GPIO_GEDR_REG_GEDR_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GEDR_REG_GEDR_REG2_SHIFT (0U)
+/*! GEDR_REG2 - GEDR Reg2
+ * 0b00000000000000000000000000000000..No edge detected on a port as specified by GRERx or GFERx
+ * 0b00000000000000000000000000000001..Edge detected on a port as specified by GRERx or GFERx
+ */
+#define GPIO_GEDR_REG_GEDR_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GEDR_REG_GEDR_REG2_SHIFT)) & GPIO_GEDR_REG_GEDR_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GEDR_REG */
+#define GPIO_GEDR_REG_COUNT (3U)
+
+/*! @name GSDR_REG - GPIO Pin Bitwise Set Direction Register 0..GPIO Pin Bitwise Set Direction Register 2 */
+/*! @{ */
+#define GPIO_GSDR_REG_GSDR_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GSDR_REG_GSDR_REG0_SHIFT (0U)
+/*! GSDR_REG0 - GSDR Reg0
+ * 0b00000000000000000000000000000000..GPDR bit unaffected
+ * 0b00000000000000000000000000000001..GPDR Bit set and GPIO Pin is set as output
+ */
+#define GPIO_GSDR_REG_GSDR_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSDR_REG_GSDR_REG0_SHIFT)) & GPIO_GSDR_REG_GSDR_REG0_MASK)
+#define GPIO_GSDR_REG_GSDR_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GSDR_REG_GSDR_REG1_SHIFT (0U)
+/*! GSDR_REG1 - GSDR Reg1
+ * 0b00000000000000000000000000000000..GPDR bit unaffected
+ * 0b00000000000000000000000000000001..GPDR Bit set and GPIO Pin is set as output
+ */
+#define GPIO_GSDR_REG_GSDR_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSDR_REG_GSDR_REG1_SHIFT)) & GPIO_GSDR_REG_GSDR_REG1_MASK)
+#define GPIO_GSDR_REG_GSDR_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GSDR_REG_GSDR_REG2_SHIFT (0U)
+/*! GSDR_REG2 - GSDR Reg2
+ * 0b00000000000000000000000000000000..GPDR bit unaffected
+ * 0b00000000000000000000000000000001..GPDR Bit set and GPIO Pin is set as output
+ */
+#define GPIO_GSDR_REG_GSDR_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSDR_REG_GSDR_REG2_SHIFT)) & GPIO_GSDR_REG_GSDR_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GSDR_REG */
+#define GPIO_GSDR_REG_COUNT (3U)
+
+/*! @name GCDR_REG - GPIO Pin Bitwise Clear Direction Register 0..GPIO Pin Bitwise Clear Direction Register 2 */
+/*! @{ */
+#define GPIO_GCDR_REG_GCDR_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GCDR_REG_GCDR_REG0_SHIFT (0U)
+/*! GCDR_REG0 - GCDR Reg0
+ * 0b00000000000000000000000000000000..GPDR bit unaffected
+ * 0b00000000000000000000000000000001..GPDR Bit clear and GPIO Pin is set as input
+ */
+#define GPIO_GCDR_REG_GCDR_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCDR_REG_GCDR_REG0_SHIFT)) & GPIO_GCDR_REG_GCDR_REG0_MASK)
+#define GPIO_GCDR_REG_GCDR_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GCDR_REG_GCDR_REG1_SHIFT (0U)
+/*! GCDR_REG1 - GCDR Reg1
+ * 0b00000000000000000000000000000000..GPDR bit unaffected
+ * 0b00000000000000000000000000000001..GPDR Bit clear and GPIO Pin is set as input
+ */
+#define GPIO_GCDR_REG_GCDR_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCDR_REG_GCDR_REG1_SHIFT)) & GPIO_GCDR_REG_GCDR_REG1_MASK)
+#define GPIO_GCDR_REG_GCDR_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GCDR_REG_GCDR_REG2_SHIFT (0U)
+/*! GCDR_REG2 - GCDR Reg2
+ * 0b00000000000000000000000000000000..GPDR bit unaffected
+ * 0b00000000000000000000000000000001..GPDR Bit clear and GPIO Pin is set as input
+ */
+#define GPIO_GCDR_REG_GCDR_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCDR_REG_GCDR_REG2_SHIFT)) & GPIO_GCDR_REG_GCDR_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GCDR_REG */
+#define GPIO_GCDR_REG_COUNT (3U)
+
+/*! @name GSRER_REG - GPIO Bitwise Set Rising Edge detect Enable Register 0..GPIO Bitwise set Rising Edge detect Enable Register 2 */
+/*! @{ */
+#define GPIO_GSRER_REG_GSRER_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GSRER_REG_GSRER_REG0_SHIFT (0U)
+/*! GSRER_REG0 - GSRER Reg0
+ * 0b00000000000000000000000000000000..GRER bit Unaffected
+ * 0b00000000000000000000000000000001..GRER Bit set
+ */
+#define GPIO_GSRER_REG_GSRER_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSRER_REG_GSRER_REG0_SHIFT)) & GPIO_GSRER_REG_GSRER_REG0_MASK)
+#define GPIO_GSRER_REG_GSRER_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GSRER_REG_GSRER_REG1_SHIFT (0U)
+/*! GSRER_REG1 - GSRER Reg1
+ * 0b00000000000000000000000000000000..GRER bit Unaffected
+ * 0b00000000000000000000000000000001..GRER Bit set
+ */
+#define GPIO_GSRER_REG_GSRER_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSRER_REG_GSRER_REG1_SHIFT)) & GPIO_GSRER_REG_GSRER_REG1_MASK)
+#define GPIO_GSRER_REG_GSRER_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GSRER_REG_GSRER_REG2_SHIFT (0U)
+/*! GSRER_REG2 - GSRER Reg2
+ * 0b00000000000000000000000000000000..GRER bit Unaffected
+ * 0b00000000000000000000000000000001..GRER Bit set
+ */
+#define GPIO_GSRER_REG_GSRER_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSRER_REG_GSRER_REG2_SHIFT)) & GPIO_GSRER_REG_GSRER_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GSRER_REG */
+#define GPIO_GSRER_REG_COUNT (3U)
+
+/*! @name GCRER_REG - GPIO Bitwise Clear Rising Edge detect Enable Register 0..GPIO Bitwise Clear Rising Edge detect Enable Register 2 */
+/*! @{ */
+#define GPIO_GCRER_REG_GCRER_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GCRER_REG_GCRER_REG0_SHIFT (0U)
+/*! GCRER_REG0 - GCRER Reg0
+ * 0b00000000000000000000000000000000..GRER bit Unaffected
+ * 0b00000000000000000000000000000001..GRER Bit Clear
+ */
+#define GPIO_GCRER_REG_GCRER_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCRER_REG_GCRER_REG0_SHIFT)) & GPIO_GCRER_REG_GCRER_REG0_MASK)
+#define GPIO_GCRER_REG_GCRER_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GCRER_REG_GCRER_REG1_SHIFT (0U)
+/*! GCRER_REG1 - GCRER Reg1
+ * 0b00000000000000000000000000000000..GRER bit Unaffected
+ * 0b00000000000000000000000000000001..GRER Bit Clear
+ */
+#define GPIO_GCRER_REG_GCRER_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCRER_REG_GCRER_REG1_SHIFT)) & GPIO_GCRER_REG_GCRER_REG1_MASK)
+#define GPIO_GCRER_REG_GCRER_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GCRER_REG_GCRER_REG2_SHIFT (0U)
+/*! GCRER_REG2 - GCRER Reg2
+ * 0b00000000000000000000000000000000..GRER bit Unaffected
+ * 0b00000000000000000000000000000001..GRER Bit Clear
+ */
+#define GPIO_GCRER_REG_GCRER_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCRER_REG_GCRER_REG2_SHIFT)) & GPIO_GCRER_REG_GCRER_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GCRER_REG */
+#define GPIO_GCRER_REG_COUNT (3U)
+
+/*! @name GSFER_REG - GPIO Bitwise Set Falling Edge detect Enable Register 0..GPIO Bitwise set Falling Edge detect Enable Register 2 */
+/*! @{ */
+#define GPIO_GSFER_REG_GSFER_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GSFER_REG_GSFER_REG0_SHIFT (0U)
+/*! GSFER_REG0 - GSFER Reg0
+ * 0b00000000000000000000000000000000..GFER bit Unaffected
+ * 0b00000000000000000000000000000001..GFER Bit set
+ */
+#define GPIO_GSFER_REG_GSFER_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSFER_REG_GSFER_REG0_SHIFT)) & GPIO_GSFER_REG_GSFER_REG0_MASK)
+#define GPIO_GSFER_REG_GSFER_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GSFER_REG_GSFER_REG1_SHIFT (0U)
+/*! GSFER_REG1 - GSFER Reg1
+ * 0b00000000000000000000000000000000..GFER bit Unaffected
+ * 0b00000000000000000000000000000001..GFER Bit set
+ */
+#define GPIO_GSFER_REG_GSFER_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSFER_REG_GSFER_REG1_SHIFT)) & GPIO_GSFER_REG_GSFER_REG1_MASK)
+#define GPIO_GSFER_REG_GSFER_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GSFER_REG_GSFER_REG2_SHIFT (0U)
+/*! GSFER_REG2 - GSFER Reg2
+ * 0b00000000000000000000000000000000..GFER bit Unaffected
+ * 0b00000000000000000000000000000001..GFER Bit set
+ */
+#define GPIO_GSFER_REG_GSFER_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GSFER_REG_GSFER_REG2_SHIFT)) & GPIO_GSFER_REG_GSFER_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GSFER_REG */
+#define GPIO_GSFER_REG_COUNT (3U)
+
+/*! @name GCFER_REG - GPIO Bitwise Clear Falling Edge detect Enable Register 0..GPIO Bitwise Clear Falling Edge detect Enable Register 2 */
+/*! @{ */
+#define GPIO_GCFER_REG_GCFER_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_GCFER_REG_GCFER_REG0_SHIFT (0U)
+/*! GCFER_REG0 - GCFER Reg0
+ * 0b00000000000000000000000000000000..GFER bit Unaffected
+ * 0b00000000000000000000000000000001..GFER Bit Clear
+ */
+#define GPIO_GCFER_REG_GCFER_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCFER_REG_GCFER_REG0_SHIFT)) & GPIO_GCFER_REG_GCFER_REG0_MASK)
+#define GPIO_GCFER_REG_GCFER_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_GCFER_REG_GCFER_REG1_SHIFT (0U)
+/*! GCFER_REG1 - GCFER Reg1
+ * 0b00000000000000000000000000000000..GFER bit Unaffected
+ * 0b00000000000000000000000000000001..GFER Bit Clear
+ */
+#define GPIO_GCFER_REG_GCFER_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCFER_REG_GCFER_REG1_SHIFT)) & GPIO_GCFER_REG_GCFER_REG1_MASK)
+#define GPIO_GCFER_REG_GCFER_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_GCFER_REG_GCFER_REG2_SHIFT (0U)
+/*! GCFER_REG2 - GCFER Reg2
+ * 0b00000000000000000000000000000000..GFER bit Unaffected
+ * 0b00000000000000000000000000000001..GFER Bit Clear
+ */
+#define GPIO_GCFER_REG_GCFER_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GCFER_REG_GCFER_REG2_SHIFT)) & GPIO_GCFER_REG_GCFER_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_GCFER_REG */
+#define GPIO_GCFER_REG_COUNT (3U)
+
+/*! @name APMASK_REG - GPIO Bitwise mask of Edge detect Status Register 0..GPIO Bitwise mask of Edge detect Status Register 2 */
+/*! @{ */
+#define GPIO_APMASK_REG_APMASK_REG0_MASK (0xFFFFFFFFU)
+#define GPIO_APMASK_REG_APMASK_REG0_SHIFT (0U)
+/*! APMASK_REG0 - APMASK Reg0
+ * 0b00000000000000000000000000000000..GPIO Edge detects are masked
+ * 0b00000000000000000000000000000001..GPIO Edge detects are not masked
+ */
+#define GPIO_APMASK_REG_APMASK_REG0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_APMASK_REG_APMASK_REG0_SHIFT)) & GPIO_APMASK_REG_APMASK_REG0_MASK)
+#define GPIO_APMASK_REG_APMASK_REG1_MASK (0xFFFFFFFFU)
+#define GPIO_APMASK_REG_APMASK_REG1_SHIFT (0U)
+/*! APMASK_REG1 - APMASK Reg1
+ * 0b00000000000000000000000000000000..GPIO Edge detects are masked
+ * 0b00000000000000000000000000000001..GPIO Edge detects are not masked
+ */
+#define GPIO_APMASK_REG_APMASK_REG1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_APMASK_REG_APMASK_REG1_SHIFT)) & GPIO_APMASK_REG_APMASK_REG1_MASK)
+#define GPIO_APMASK_REG_APMASK_REG2_MASK (0xFFFFFFFFU)
+#define GPIO_APMASK_REG_APMASK_REG2_SHIFT (0U)
+/*! APMASK_REG2 - APMASK Reg2
+ * 0b00000000000000000000000000000000..GPIO Edge detects are masked
+ * 0b00000000000000000000000000000001..GPIO Edge detects are not masked
+ */
+#define GPIO_APMASK_REG_APMASK_REG2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_APMASK_REG_APMASK_REG2_SHIFT)) & GPIO_APMASK_REG_APMASK_REG2_MASK)
+/*! @} */
+
+/* The count of GPIO_APMASK_REG */
+#define GPIO_APMASK_REG_COUNT (3U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO base address */
+#define GPIO_BASE (0x46060000u)
+/** Peripheral GPIO base pointer */
+#define GPIO ((GPIO_Type *)GPIO_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { GPIO_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { GPIO }
+/** Interrupt vectors for the GPIO peripheral type */
+#define GPIO_IRQS { GPIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
+ * @{
+ */
+
+/** GPT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CNT_EN_REG; /**< Counter Enable Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t STS_REG; /**< Status Register, offset: 0x20 */
+ __I uint32_t INT_REG; /**< Interrupt Register, offset: 0x24 */
+ __IO uint32_t INT_MSK_REG; /**< Interrupt Mask Register, offset: 0x28 */
+ uint8_t RESERVED_1[20];
+ __IO uint32_t CNT_CNTL_REG; /**< Counter Control Register, offset: 0x40 */
+ uint8_t RESERVED_2[12];
+ __I uint32_t CNT_VAL_REG; /**< Counter Value Register, offset: 0x50 */
+ uint8_t RESERVED_3[12];
+ __IO uint32_t CNT_UPP_VAL_REG; /**< Counter Upper Value Register, offset: 0x60 */
+ uint8_t RESERVED_4[28];
+ __IO uint32_t CLK_CNTL_REG; /**< Clock Control Register, offset: 0x80 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t IC_CNTL_REG; /**< Input Capture Control Register, offset: 0x88 */
+ uint8_t RESERVED_6[20];
+ __IO uint32_t DMA_CNTL_EN_REG; /**< DMA Control Enable Register, offset: 0xA0 */
+ __IO uint32_t DMA_CNTL_CH_REG; /**< DMA Control Channel Register, offset: 0xA4 */
+ uint8_t RESERVED_7[40];
+ __IO uint32_t ADCT_REG; /**< ADC Trigger Control Register, offset: 0xD0 */
+ uint8_t RESERVED_8[4];
+ __IO uint32_t ADCT_DLY_REG; /**< ADC Trigger Delay Register, offset: 0xD8 */
+ uint8_t RESERVED_9[20];
+ __O uint32_t USER_REQ_REG; /**< User Request Register, offset: 0xF0 */
+ uint8_t RESERVED_10[268];
+ struct { /* offset: 0x200, array step: 0x40 */
+ __IO uint32_t CH_CNTL_REG; /**< Channel 0 Control Register..Channel 5 Control Register, array offset: 0x200, array step: 0x40 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t CH_CMR0_REG; /**< Channel 0 Counter Match Register 0..Channel 5 Counter Match Register 0, array offset: 0x210, array step: 0x40 */
+ __I uint32_t CH_STS_REG; /**< Channel 0 Status Register 0..Channel 5 Status Register 0, array offset: 0x214, array step: 0x40 */
+ uint8_t RESERVED_1[8];
+ __IO uint32_t CH_CMR1_REG; /**< Channel 0 Counter Match Register 1..Channel 5 Counter Match Register 1, array offset: 0x220, array step: 0x40 */
+ uint8_t RESERVED_2[28];
+ } CH[6];
+} GPT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPT_Register_Masks GPT Register Masks
+ * @{
+ */
+
+/*! @name CNT_EN_REG - Counter Enable Register */
+/*! @{ */
+#define GPT_CNT_EN_REG_CNT_START_MASK (0x1U)
+#define GPT_CNT_EN_REG_CNT_START_SHIFT (0U)
+/*! CNT_START - Counter Start
+ * 0b0..No action
+ * 0b1..Enable the counter (poll CNT_RUN for 1 to confirm that the counter is enabled internally)
+ */
+#define GPT_CNT_EN_REG_CNT_START(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_EN_REG_CNT_START_SHIFT)) & GPT_CNT_EN_REG_CNT_START_MASK)
+#define GPT_CNT_EN_REG_CNT_STOP_MASK (0x2U)
+#define GPT_CNT_EN_REG_CNT_STOP_SHIFT (1U)
+/*! CNT_STOP - Counter Stop
+ * 0b0..No action
+ * 0b1..Disable the counter (poll CNT_RUN for 0 to confirm that the counter is disabled internally)
+ */
+#define GPT_CNT_EN_REG_CNT_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_EN_REG_CNT_STOP_SHIFT)) & GPT_CNT_EN_REG_CNT_STOP_MASK)
+#define GPT_CNT_EN_REG_CNT_RESET_MASK (0x4U)
+#define GPT_CNT_EN_REG_CNT_RESET_SHIFT (2U)
+/*! CNT_RESET - Counter Reset
+ * 0b0..No action
+ * 0b1..Reset the counter (counter is reset to 0; channel output states are reset to 0; poll CNT_RST_DONE for 1
+ * before writing to any other registers)
+ */
+#define GPT_CNT_EN_REG_CNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_EN_REG_CNT_RESET_SHIFT)) & GPT_CNT_EN_REG_CNT_RESET_MASK)
+#define GPT_CNT_EN_REG_CNT_RUN_MASK (0x10000U)
+#define GPT_CNT_EN_REG_CNT_RUN_SHIFT (16U)
+/*! CNT_RUN - Counter Enabled Status
+ * 0b0..Counter is disabled
+ * 0b1..Counter is enabled
+ */
+#define GPT_CNT_EN_REG_CNT_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_EN_REG_CNT_RUN_SHIFT)) & GPT_CNT_EN_REG_CNT_RUN_MASK)
+#define GPT_CNT_EN_REG_CNT_RST_DONE_MASK (0x20000U)
+#define GPT_CNT_EN_REG_CNT_RST_DONE_SHIFT (17U)
+/*! CNT_RST_DONE - Counter Reset Done Status
+ * 0b0..Indicates that the counter is still resetting
+ * 0b1..Indicates that the counter has been reset
+ */
+#define GPT_CNT_EN_REG_CNT_RST_DONE(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_EN_REG_CNT_RST_DONE_SHIFT)) & GPT_CNT_EN_REG_CNT_RST_DONE_MASK)
+#define GPT_CNT_EN_REG_STS_RESETN_MASK (0x40000U)
+#define GPT_CNT_EN_REG_STS_RESETN_SHIFT (18U)
+/*! STS_RESETN - System Reset Status
+ * 0b0..Indicates that the system reset is still asserted
+ * 0b1..Indicates that the system reset is deasserted
+ */
+#define GPT_CNT_EN_REG_STS_RESETN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_EN_REG_STS_RESETN_SHIFT)) & GPT_CNT_EN_REG_STS_RESETN_MASK)
+/*! @} */
+
+/*! @name STS_REG - Status Register */
+/*! @{ */
+#define GPT_STS_REG_CH0_STS_MASK (0x1U)
+#define GPT_STS_REG_CH0_STS_SHIFT (0U)
+/*! CH0_STS - Channel Status
+ * 0b0..Status cleared
+ * 0b1..Status bit for this channel has been set
+ */
+#define GPT_STS_REG_CH0_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH0_STS_SHIFT)) & GPT_STS_REG_CH0_STS_MASK)
+#define GPT_STS_REG_CH1_STS_MASK (0x2U)
+#define GPT_STS_REG_CH1_STS_SHIFT (1U)
+/*! CH1_STS - See CH0_STS.
+ */
+#define GPT_STS_REG_CH1_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH1_STS_SHIFT)) & GPT_STS_REG_CH1_STS_MASK)
+#define GPT_STS_REG_CH2_STS_MASK (0x4U)
+#define GPT_STS_REG_CH2_STS_SHIFT (2U)
+/*! CH2_STS - See CH0_STS.
+ */
+#define GPT_STS_REG_CH2_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH2_STS_SHIFT)) & GPT_STS_REG_CH2_STS_MASK)
+#define GPT_STS_REG_CH3_STS_MASK (0x8U)
+#define GPT_STS_REG_CH3_STS_SHIFT (3U)
+/*! CH3_STS - See CH0_STS.
+ */
+#define GPT_STS_REG_CH3_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH3_STS_SHIFT)) & GPT_STS_REG_CH3_STS_MASK)
+#define GPT_STS_REG_CH4_STS_MASK (0x10U)
+#define GPT_STS_REG_CH4_STS_SHIFT (4U)
+/*! CH4_STS - See CH0_STS.
+ */
+#define GPT_STS_REG_CH4_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH4_STS_SHIFT)) & GPT_STS_REG_CH4_STS_MASK)
+#define GPT_STS_REG_CH5_STS_MASK (0x20U)
+#define GPT_STS_REG_CH5_STS_SHIFT (5U)
+/*! CH5_STS - See CH0_STS.
+ */
+#define GPT_STS_REG_CH5_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH5_STS_SHIFT)) & GPT_STS_REG_CH5_STS_MASK)
+#define GPT_STS_REG_CH0_ERR_STS_MASK (0x100U)
+#define GPT_STS_REG_CH0_ERR_STS_SHIFT (8U)
+/*! CH0_ERR_STS - Channel Error Status
+ * 0b0..Status cleared
+ * 0b1..An error has occurred in this channel
+ */
+#define GPT_STS_REG_CH0_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH0_ERR_STS_SHIFT)) & GPT_STS_REG_CH0_ERR_STS_MASK)
+#define GPT_STS_REG_CH1_ERR_STS_MASK (0x200U)
+#define GPT_STS_REG_CH1_ERR_STS_SHIFT (9U)
+/*! CH1_ERR_STS - See CH0_ERR_STS.
+ */
+#define GPT_STS_REG_CH1_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH1_ERR_STS_SHIFT)) & GPT_STS_REG_CH1_ERR_STS_MASK)
+#define GPT_STS_REG_CH2_ERR_STS_MASK (0x400U)
+#define GPT_STS_REG_CH2_ERR_STS_SHIFT (10U)
+/*! CH2_ERR_STS - See CH0_ERR_STS.
+ */
+#define GPT_STS_REG_CH2_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH2_ERR_STS_SHIFT)) & GPT_STS_REG_CH2_ERR_STS_MASK)
+#define GPT_STS_REG_CH3_ERR_STS_MASK (0x800U)
+#define GPT_STS_REG_CH3_ERR_STS_SHIFT (11U)
+/*! CH3_ERR_STS - See CH0_ERR_STS.
+ */
+#define GPT_STS_REG_CH3_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH3_ERR_STS_SHIFT)) & GPT_STS_REG_CH3_ERR_STS_MASK)
+#define GPT_STS_REG_CH4_ERR_STS_MASK (0x1000U)
+#define GPT_STS_REG_CH4_ERR_STS_SHIFT (12U)
+/*! CH4_ERR_STS - See CH0_ERR_STS.
+ */
+#define GPT_STS_REG_CH4_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH4_ERR_STS_SHIFT)) & GPT_STS_REG_CH4_ERR_STS_MASK)
+#define GPT_STS_REG_CH5_ERR_STS_MASK (0x2000U)
+#define GPT_STS_REG_CH5_ERR_STS_SHIFT (13U)
+/*! CH5_ERR_STS - See CH0_ERR_STS.
+ */
+#define GPT_STS_REG_CH5_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CH5_ERR_STS_SHIFT)) & GPT_STS_REG_CH5_ERR_STS_MASK)
+#define GPT_STS_REG_CNT_UPP_STS_MASK (0x10000U)
+#define GPT_STS_REG_CNT_UPP_STS_SHIFT (16U)
+/*! CNT_UPP_STS - Counter-Reach-Upper Status
+ */
+#define GPT_STS_REG_CNT_UPP_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_CNT_UPP_STS_SHIFT)) & GPT_STS_REG_CNT_UPP_STS_MASK)
+#define GPT_STS_REG_DMA0_OF_STS_MASK (0x1000000U)
+#define GPT_STS_REG_DMA0_OF_STS_SHIFT (24U)
+/*! DMA0_OF_STS - DMA Overflow Status
+ * 0b0..Status cleared
+ * 0b1..Indicates that there has been a new input capture before this DMA channel could transfer the captured data away
+ */
+#define GPT_STS_REG_DMA0_OF_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_DMA0_OF_STS_SHIFT)) & GPT_STS_REG_DMA0_OF_STS_MASK)
+#define GPT_STS_REG_DMA1_OF_STS_MASK (0x2000000U)
+#define GPT_STS_REG_DMA1_OF_STS_SHIFT (25U)
+/*! DMA1_OF_STS - See DMA0_OF_STS.
+ */
+#define GPT_STS_REG_DMA1_OF_STS(x) (((uint32_t)(((uint32_t)(x)) << GPT_STS_REG_DMA1_OF_STS_SHIFT)) & GPT_STS_REG_DMA1_OF_STS_MASK)
+/*! @} */
+
+/*! @name INT_REG - Interrupt Register */
+/*! @{ */
+#define GPT_INT_REG_CH0_INTR_MASK (0x1U)
+#define GPT_INT_REG_CH0_INTR_SHIFT (0U)
+/*! CH0_INTR - Masked signal of CH0_STS
+ */
+#define GPT_INT_REG_CH0_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH0_INTR_SHIFT)) & GPT_INT_REG_CH0_INTR_MASK)
+#define GPT_INT_REG_CH1_INTR_MASK (0x2U)
+#define GPT_INT_REG_CH1_INTR_SHIFT (1U)
+/*! CH1_INTR - Masked signal of CH1_STS
+ */
+#define GPT_INT_REG_CH1_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH1_INTR_SHIFT)) & GPT_INT_REG_CH1_INTR_MASK)
+#define GPT_INT_REG_CH2_INTR_MASK (0x4U)
+#define GPT_INT_REG_CH2_INTR_SHIFT (2U)
+/*! CH2_INTR - Masked signal of CH2_STS
+ */
+#define GPT_INT_REG_CH2_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH2_INTR_SHIFT)) & GPT_INT_REG_CH2_INTR_MASK)
+#define GPT_INT_REG_CH3_INTR_MASK (0x8U)
+#define GPT_INT_REG_CH3_INTR_SHIFT (3U)
+/*! CH3_INTR - Masked signal of CH3_STS
+ */
+#define GPT_INT_REG_CH3_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH3_INTR_SHIFT)) & GPT_INT_REG_CH3_INTR_MASK)
+#define GPT_INT_REG_CH4_INTR_MASK (0x10U)
+#define GPT_INT_REG_CH4_INTR_SHIFT (4U)
+/*! CH4_INTR - Masked signal of CH4_STS
+ */
+#define GPT_INT_REG_CH4_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH4_INTR_SHIFT)) & GPT_INT_REG_CH4_INTR_MASK)
+#define GPT_INT_REG_CH5_INTR_MASK (0x20U)
+#define GPT_INT_REG_CH5_INTR_SHIFT (5U)
+/*! CH5_INTR - Masked signal of CH5_STS
+ */
+#define GPT_INT_REG_CH5_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH5_INTR_SHIFT)) & GPT_INT_REG_CH5_INTR_MASK)
+#define GPT_INT_REG_CH0_ERR_INTR_MASK (0x100U)
+#define GPT_INT_REG_CH0_ERR_INTR_SHIFT (8U)
+/*! CH0_ERR_INTR - Masked signal of CH0_ERR_STS
+ */
+#define GPT_INT_REG_CH0_ERR_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH0_ERR_INTR_SHIFT)) & GPT_INT_REG_CH0_ERR_INTR_MASK)
+#define GPT_INT_REG_CH1_ERR_INTR_MASK (0x200U)
+#define GPT_INT_REG_CH1_ERR_INTR_SHIFT (9U)
+/*! CH1_ERR_INTR - Masked signal of CH1_ERR_STS
+ */
+#define GPT_INT_REG_CH1_ERR_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH1_ERR_INTR_SHIFT)) & GPT_INT_REG_CH1_ERR_INTR_MASK)
+#define GPT_INT_REG_CH2_ERR_INTR_MASK (0x400U)
+#define GPT_INT_REG_CH2_ERR_INTR_SHIFT (10U)
+/*! CH2_ERR_INTR - Masked signal of CH2_ERR_STS
+ */
+#define GPT_INT_REG_CH2_ERR_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH2_ERR_INTR_SHIFT)) & GPT_INT_REG_CH2_ERR_INTR_MASK)
+#define GPT_INT_REG_CH3_ERR_INTR_MASK (0x800U)
+#define GPT_INT_REG_CH3_ERR_INTR_SHIFT (11U)
+/*! CH3_ERR_INTR - Masked signal of CH3_ERR_STS
+ */
+#define GPT_INT_REG_CH3_ERR_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH3_ERR_INTR_SHIFT)) & GPT_INT_REG_CH3_ERR_INTR_MASK)
+#define GPT_INT_REG_CH4_ERR_INTR_MASK (0x1000U)
+#define GPT_INT_REG_CH4_ERR_INTR_SHIFT (12U)
+/*! CH4_ERR_INTR - Masked signal of CH4_ERR_STS
+ */
+#define GPT_INT_REG_CH4_ERR_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH4_ERR_INTR_SHIFT)) & GPT_INT_REG_CH4_ERR_INTR_MASK)
+#define GPT_INT_REG_CH5_ERR_INTR_MASK (0x2000U)
+#define GPT_INT_REG_CH5_ERR_INTR_SHIFT (13U)
+/*! CH5_ERR_INTR - Masked signal of CH5_ERR_STS
+ */
+#define GPT_INT_REG_CH5_ERR_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CH5_ERR_INTR_SHIFT)) & GPT_INT_REG_CH5_ERR_INTR_MASK)
+#define GPT_INT_REG_CNT_UPP_INTR_MASK (0x10000U)
+#define GPT_INT_REG_CNT_UPP_INTR_SHIFT (16U)
+/*! CNT_UPP_INTR - Masked signal of CNT_UPP_STS
+ */
+#define GPT_INT_REG_CNT_UPP_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_CNT_UPP_INTR_SHIFT)) & GPT_INT_REG_CNT_UPP_INTR_MASK)
+#define GPT_INT_REG_DMA0_OF_INTR_MASK (0x1000000U)
+#define GPT_INT_REG_DMA0_OF_INTR_SHIFT (24U)
+/*! DMA0_OF_INTR - Masked signal of DMA0_OF_STS
+ */
+#define GPT_INT_REG_DMA0_OF_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_DMA0_OF_INTR_SHIFT)) & GPT_INT_REG_DMA0_OF_INTR_MASK)
+#define GPT_INT_REG_DMA1_OF_INTR_MASK (0x2000000U)
+#define GPT_INT_REG_DMA1_OF_INTR_SHIFT (25U)
+/*! DMA1_OF_INTR - Masked signal of DMA1_OF_STS
+ */
+#define GPT_INT_REG_DMA1_OF_INTR(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_REG_DMA1_OF_INTR_SHIFT)) & GPT_INT_REG_DMA1_OF_INTR_MASK)
+/*! @} */
+
+/*! @name INT_MSK_REG - Interrupt Mask Register */
+/*! @{ */
+#define GPT_INT_MSK_REG_CH0_MSK_MASK (0x1U)
+#define GPT_INT_MSK_REG_CH0_MSK_SHIFT (0U)
+/*! CH0_MSK - Channel Interrupt Mask
+ * 0b0..Do not mask CH0_STS
+ * 0b1..Mask CH0_STS
+ */
+#define GPT_INT_MSK_REG_CH0_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH0_MSK_SHIFT)) & GPT_INT_MSK_REG_CH0_MSK_MASK)
+#define GPT_INT_MSK_REG_CH1_MSK_MASK (0x2U)
+#define GPT_INT_MSK_REG_CH1_MSK_SHIFT (1U)
+/*! CH1_MSK - See CH0_STS.
+ */
+#define GPT_INT_MSK_REG_CH1_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH1_MSK_SHIFT)) & GPT_INT_MSK_REG_CH1_MSK_MASK)
+#define GPT_INT_MSK_REG_CH2_MSK_MASK (0x4U)
+#define GPT_INT_MSK_REG_CH2_MSK_SHIFT (2U)
+/*! CH2_MSK - See CH0_STS.
+ */
+#define GPT_INT_MSK_REG_CH2_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH2_MSK_SHIFT)) & GPT_INT_MSK_REG_CH2_MSK_MASK)
+#define GPT_INT_MSK_REG_CH3_MSK_MASK (0x8U)
+#define GPT_INT_MSK_REG_CH3_MSK_SHIFT (3U)
+/*! CH3_MSK - See CH0_STS.
+ */
+#define GPT_INT_MSK_REG_CH3_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH3_MSK_SHIFT)) & GPT_INT_MSK_REG_CH3_MSK_MASK)
+#define GPT_INT_MSK_REG_CH4_MSK_MASK (0x10U)
+#define GPT_INT_MSK_REG_CH4_MSK_SHIFT (4U)
+/*! CH4_MSK - See CH0_STS.
+ */
+#define GPT_INT_MSK_REG_CH4_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH4_MSK_SHIFT)) & GPT_INT_MSK_REG_CH4_MSK_MASK)
+#define GPT_INT_MSK_REG_CH5_MSK_MASK (0x20U)
+#define GPT_INT_MSK_REG_CH5_MSK_SHIFT (5U)
+/*! CH5_MSK - See CH0_STS.
+ */
+#define GPT_INT_MSK_REG_CH5_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH5_MSK_SHIFT)) & GPT_INT_MSK_REG_CH5_MSK_MASK)
+#define GPT_INT_MSK_REG_CH0_ERR_MSK_MASK (0x100U)
+#define GPT_INT_MSK_REG_CH0_ERR_MSK_SHIFT (8U)
+/*! CH0_ERR_MSK - Channel Error Interrupt Mask
+ * 0b0..Do not mask CH0_ERR_STS
+ * 0b1..Mask CH0_ERR_STS
+ */
+#define GPT_INT_MSK_REG_CH0_ERR_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH0_ERR_MSK_SHIFT)) & GPT_INT_MSK_REG_CH0_ERR_MSK_MASK)
+#define GPT_INT_MSK_REG_CH1_ERR_MSK_MASK (0x200U)
+#define GPT_INT_MSK_REG_CH1_ERR_MSK_SHIFT (9U)
+/*! CH1_ERR_MSK - See CH0_ERR_STS.
+ */
+#define GPT_INT_MSK_REG_CH1_ERR_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH1_ERR_MSK_SHIFT)) & GPT_INT_MSK_REG_CH1_ERR_MSK_MASK)
+#define GPT_INT_MSK_REG_CH2_ERR_MSK_MASK (0x400U)
+#define GPT_INT_MSK_REG_CH2_ERR_MSK_SHIFT (10U)
+/*! CH2_ERR_MSK - See CH0_ERR_STS.
+ */
+#define GPT_INT_MSK_REG_CH2_ERR_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH2_ERR_MSK_SHIFT)) & GPT_INT_MSK_REG_CH2_ERR_MSK_MASK)
+#define GPT_INT_MSK_REG_CH3_ERR_MSK_MASK (0x800U)
+#define GPT_INT_MSK_REG_CH3_ERR_MSK_SHIFT (11U)
+/*! CH3_ERR_MSK - See CH0_ERR_STS.
+ */
+#define GPT_INT_MSK_REG_CH3_ERR_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH3_ERR_MSK_SHIFT)) & GPT_INT_MSK_REG_CH3_ERR_MSK_MASK)
+#define GPT_INT_MSK_REG_CH4_ERR_MSK_MASK (0x1000U)
+#define GPT_INT_MSK_REG_CH4_ERR_MSK_SHIFT (12U)
+/*! CH4_ERR_MSK - See CH0_ERR_STS.
+ */
+#define GPT_INT_MSK_REG_CH4_ERR_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH4_ERR_MSK_SHIFT)) & GPT_INT_MSK_REG_CH4_ERR_MSK_MASK)
+#define GPT_INT_MSK_REG_CH5_ERR_MSK_MASK (0x2000U)
+#define GPT_INT_MSK_REG_CH5_ERR_MSK_SHIFT (13U)
+/*! CH5_ERR_MSK - See CH0_ERR_STS.
+ */
+#define GPT_INT_MSK_REG_CH5_ERR_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CH5_ERR_MSK_SHIFT)) & GPT_INT_MSK_REG_CH5_ERR_MSK_MASK)
+#define GPT_INT_MSK_REG_CNT_UPP_MSK_MASK (0x10000U)
+#define GPT_INT_MSK_REG_CNT_UPP_MSK_SHIFT (16U)
+/*! CNT_UPP_MSK - Upper Value Interrupt Mask
+ * 0b0..Do not mask CNT_UPP_STS
+ * 0b1..Mask CNT_UPP_STS
+ */
+#define GPT_INT_MSK_REG_CNT_UPP_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_CNT_UPP_MSK_SHIFT)) & GPT_INT_MSK_REG_CNT_UPP_MSK_MASK)
+#define GPT_INT_MSK_REG_DMA0_OF_MSK_MASK (0x1000000U)
+#define GPT_INT_MSK_REG_DMA0_OF_MSK_SHIFT (24U)
+/*! DMA0_OF_MSK - DMA Channel Overflow Mask
+ * 0b0..Do not mask DMA0_OF_STS
+ * 0b1..Mask DMA0_OF_STS
+ */
+#define GPT_INT_MSK_REG_DMA0_OF_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_DMA0_OF_MSK_SHIFT)) & GPT_INT_MSK_REG_DMA0_OF_MSK_MASK)
+#define GPT_INT_MSK_REG_DMA1_OF_MSK_MASK (0x2000000U)
+#define GPT_INT_MSK_REG_DMA1_OF_MSK_SHIFT (25U)
+/*! DMA1_OF_MSK - See DMA0_OF_MSK
+ */
+#define GPT_INT_MSK_REG_DMA1_OF_MSK(x) (((uint32_t)(((uint32_t)(x)) << GPT_INT_MSK_REG_DMA1_OF_MSK_SHIFT)) & GPT_INT_MSK_REG_DMA1_OF_MSK_MASK)
+/*! @} */
+
+/*! @name CNT_CNTL_REG - Counter Control Register */
+/*! @{ */
+#define GPT_CNT_CNTL_REG_CNT_DBG_ACT_MASK (0x10U)
+#define GPT_CNT_CNTL_REG_CNT_DBG_ACT_SHIFT (4U)
+/*! CNT_DBG_ACT - Counter Debug Mode Action Mask
+ * 0b0..In debug mode, stop the counter
+ * 0b1..In debug mode, the counter is not affected
+ */
+#define GPT_CNT_CNTL_REG_CNT_DBG_ACT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_CNTL_REG_CNT_DBG_ACT_SHIFT)) & GPT_CNT_CNTL_REG_CNT_DBG_ACT_MASK)
+#define GPT_CNT_CNTL_REG_CNT_UPDT_MOD_MASK (0x300U)
+#define GPT_CNT_CNTL_REG_CNT_UPDT_MOD_SHIFT (8U)
+/*! CNT_UPDT_MOD - Counter Value Update Mode
+ * 0b00..Auto-update normal (can be used for any clock relationship between the counter clock and the APB clock;
+ * only every 3-4 counter ticks are updated to CNT_VAL)
+ * 0b01..Auto-update fast (use when counter clock is at least 5 times slower than the APB clock; every counter tick is updated to CNT_VAL)
+ * 0b10..Reserved
+ * 0b11..Update off (of CNT_VAL does not need to be read, CNT_UPDT_MOD can be set to off to save power)
+ */
+#define GPT_CNT_CNTL_REG_CNT_UPDT_MOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_CNTL_REG_CNT_UPDT_MOD_SHIFT)) & GPT_CNT_CNTL_REG_CNT_UPDT_MOD_MASK)
+/*! @} */
+
+/*! @name CNT_VAL_REG - Counter Value Register */
+/*! @{ */
+#define GPT_CNT_VAL_REG_CNT_VAL_MASK (0xFFFFFFFFU)
+#define GPT_CNT_VAL_REG_CNT_VAL_SHIFT (0U)
+/*! CNT_VAL - Counter Value
+ */
+#define GPT_CNT_VAL_REG_CNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_VAL_REG_CNT_VAL_SHIFT)) & GPT_CNT_VAL_REG_CNT_VAL_MASK)
+/*! @} */
+
+/*! @name CNT_UPP_VAL_REG - Counter Upper Value Register */
+/*! @{ */
+#define GPT_CNT_UPP_VAL_REG_UPP_VAL_MASK (0xFFFFFFFFU)
+#define GPT_CNT_UPP_VAL_REG_UPP_VAL_SHIFT (0U)
+/*! UPP_VAL - Counter Upper Value
+ */
+#define GPT_CNT_UPP_VAL_REG_UPP_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_UPP_VAL_REG_UPP_VAL_SHIFT)) & GPT_CNT_UPP_VAL_REG_UPP_VAL_MASK)
+/*! @} */
+
+/*! @name CLK_CNTL_REG - Clock Control Register */
+/*! @{ */
+#define GPT_CLK_CNTL_REG_CLK_SRC_MASK (0x1U)
+#define GPT_CLK_CNTL_REG_CLK_SRC_SHIFT (0U)
+/*! CLK_SRC - Counter Clock Select
+ * 0b0..Select clock 0
+ * 0b1..Select clock 1
+ */
+#define GPT_CLK_CNTL_REG_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CLK_CNTL_REG_CLK_SRC_SHIFT)) & GPT_CLK_CNTL_REG_CLK_SRC_MASK)
+#define GPT_CLK_CNTL_REG_CLK_DIV_MASK (0xF00U)
+#define GPT_CLK_CNTL_REG_CLK_DIV_SHIFT (8U)
+/*! CLK_DIV - Clock Divider
+ */
+#define GPT_CLK_CNTL_REG_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << GPT_CLK_CNTL_REG_CLK_DIV_SHIFT)) & GPT_CLK_CNTL_REG_CLK_DIV_MASK)
+#define GPT_CLK_CNTL_REG_CLK_PRE_MASK (0xFF0000U)
+#define GPT_CLK_CNTL_REG_CLK_PRE_SHIFT (16U)
+/*! CLK_PRE - Clock Pre-Scalar
+ */
+#define GPT_CLK_CNTL_REG_CLK_PRE(x) (((uint32_t)(((uint32_t)(x)) << GPT_CLK_CNTL_REG_CLK_PRE_SHIFT)) & GPT_CLK_CNTL_REG_CLK_PRE_MASK)
+/*! @} */
+
+/*! @name IC_CNTL_REG - Input Capture Control Register */
+/*! @{ */
+#define GPT_IC_CNTL_REG_CHX_IC_WIDTH_MASK (0x7U)
+#define GPT_IC_CNTL_REG_CHX_IC_WIDTH_SHIFT (0U)
+/*! CHx_IC_WIDTH - Input Capture Filter Width
+ * 0b000..No filtering (1 cycle)
+ * 0b001..2 cycles
+ * 0b010..3 cycles
+ * 0b011..4 cycles
+ * 0b100..5 cycles
+ * 0b101..6 cycles
+ * 0b110..7 cycles
+ * 0b111..Reserved
+ */
+#define GPT_IC_CNTL_REG_CHX_IC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << GPT_IC_CNTL_REG_CHX_IC_WIDTH_SHIFT)) & GPT_IC_CNTL_REG_CHX_IC_WIDTH_MASK)
+#define GPT_IC_CNTL_REG_CHX_IC_DIV_MASK (0x70U)
+#define GPT_IC_CNTL_REG_CHX_IC_DIV_SHIFT (4U)
+/*! CHx_IC_DIV - Input Capture Sampling Clock Divider
+ */
+#define GPT_IC_CNTL_REG_CHX_IC_DIV(x) (((uint32_t)(((uint32_t)(x)) << GPT_IC_CNTL_REG_CHX_IC_DIV_SHIFT)) & GPT_IC_CNTL_REG_CHX_IC_DIV_MASK)
+/*! @} */
+
+/*! @name DMA_CNTL_EN_REG - DMA Control Enable Register */
+/*! @{ */
+#define GPT_DMA_CNTL_EN_REG_DMA0_EN_MASK (0x1U)
+#define GPT_DMA_CNTL_EN_REG_DMA0_EN_SHIFT (0U)
+/*! DMA0_EN - DMA Channel Enable
+ * 0b0..Disable this DMA channel
+ * 0b1..Enable this DMA channel. In input capture mode, DMA controller will be notified when a value is captured.
+ */
+#define GPT_DMA_CNTL_EN_REG_DMA0_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_DMA_CNTL_EN_REG_DMA0_EN_SHIFT)) & GPT_DMA_CNTL_EN_REG_DMA0_EN_MASK)
+#define GPT_DMA_CNTL_EN_REG_DMA1_EN_MASK (0x2U)
+#define GPT_DMA_CNTL_EN_REG_DMA1_EN_SHIFT (1U)
+/*! DMA1_EN - See DMA0_EN.
+ */
+#define GPT_DMA_CNTL_EN_REG_DMA1_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_DMA_CNTL_EN_REG_DMA1_EN_SHIFT)) & GPT_DMA_CNTL_EN_REG_DMA1_EN_MASK)
+/*! @} */
+
+/*! @name DMA_CNTL_CH_REG - DMA Control Channel Register */
+/*! @{ */
+#define GPT_DMA_CNTL_CH_REG_DMA0_CH_MASK (0x7U)
+#define GPT_DMA_CNTL_CH_REG_DMA0_CH_SHIFT (0U)
+/*! DMA0_CH - DMA Channel Select
+ * 0b000..Connect to channel 0
+ * 0b001..Connect to channel 1
+ * 0b010..Connect to channel 2
+ * 0b011..Connect to channel 3
+ * 0b100..Connect to channel 4
+ * 0b101..Connect to channel 5
+ */
+#define GPT_DMA_CNTL_CH_REG_DMA0_CH(x) (((uint32_t)(((uint32_t)(x)) << GPT_DMA_CNTL_CH_REG_DMA0_CH_SHIFT)) & GPT_DMA_CNTL_CH_REG_DMA0_CH_MASK)
+#define GPT_DMA_CNTL_CH_REG_DMA1_CH_MASK (0x70U)
+#define GPT_DMA_CNTL_CH_REG_DMA1_CH_SHIFT (4U)
+/*! DMA1_CH - See DMA0_CH.
+ */
+#define GPT_DMA_CNTL_CH_REG_DMA1_CH(x) (((uint32_t)(((uint32_t)(x)) << GPT_DMA_CNTL_CH_REG_DMA1_CH_SHIFT)) & GPT_DMA_CNTL_CH_REG_DMA1_CH_MASK)
+/*! @} */
+
+/*! @name ADCT_REG - ADC Trigger Control Register */
+/*! @{ */
+#define GPT_ADCT_REG_ADCT_CHSEL_MASK (0x7U)
+#define GPT_ADCT_REG_ADCT_CHSEL_SHIFT (0U)
+/*! ADCT_CHSEL - ADC Trigger Channel Select
+ * 0b000..Connect to channel 0
+ * 0b001..Connect to channel 1
+ * 0b010..Connect to channel 2
+ * 0b011..Connect to channel 3
+ * 0b100..Connect to channel 4
+ * 0b101..Connect to channel 5
+ */
+#define GPT_ADCT_REG_ADCT_CHSEL(x) (((uint32_t)(((uint32_t)(x)) << GPT_ADCT_REG_ADCT_CHSEL_SHIFT)) & GPT_ADCT_REG_ADCT_CHSEL_MASK)
+#define GPT_ADCT_REG_ADCT_EN_MASK (0x100U)
+#define GPT_ADCT_REG_ADCT_EN_SHIFT (8U)
+/*! ADCT_EN - ADC Trigger Enable
+ * 0b0..Disable the ADC trigger
+ * 0b1..Enable the ADC trigger
+ */
+#define GPT_ADCT_REG_ADCT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_ADCT_REG_ADCT_EN_SHIFT)) & GPT_ADCT_REG_ADCT_EN_MASK)
+/*! @} */
+
+/*! @name ADCT_DLY_REG - ADC Trigger Delay Register */
+/*! @{ */
+#define GPT_ADCT_DLY_REG_ADCT_DLY_MASK (0xFFFFFFFFU)
+#define GPT_ADCT_DLY_REG_ADCT_DLY_SHIFT (0U)
+/*! ADCT_DLY - ADC Trigger Delay
+ */
+#define GPT_ADCT_DLY_REG_ADCT_DLY(x) (((uint32_t)(((uint32_t)(x)) << GPT_ADCT_DLY_REG_ADCT_DLY_SHIFT)) & GPT_ADCT_DLY_REG_ADCT_DLY_MASK)
+/*! @} */
+
+/*! @name USER_REQ_REG - User Request Register */
+/*! @{ */
+#define GPT_USER_REQ_REG_CH0_USER_ITRIG_MASK (0x1U)
+#define GPT_USER_REQ_REG_CH0_USER_ITRIG_SHIFT (0U)
+/*! CH0_USER_ITRIG - User Input Trigger
+ * 0b0..No action
+ * 0b1..If this channel (channel 0) is configured to input-capture mode, generate a manual input trigger to
+ * capture the current counter value (this trigger bypasses the input capture control settings)
+ */
+#define GPT_USER_REQ_REG_CH0_USER_ITRIG(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH0_USER_ITRIG_SHIFT)) & GPT_USER_REQ_REG_CH0_USER_ITRIG_MASK)
+#define GPT_USER_REQ_REG_CH1_USER_ITRIG_MASK (0x2U)
+#define GPT_USER_REQ_REG_CH1_USER_ITRIG_SHIFT (1U)
+/*! CH1_USER_ITRIG - See CH0_USER_ITRIG.
+ */
+#define GPT_USER_REQ_REG_CH1_USER_ITRIG(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH1_USER_ITRIG_SHIFT)) & GPT_USER_REQ_REG_CH1_USER_ITRIG_MASK)
+#define GPT_USER_REQ_REG_CH2_USER_ITRIG_MASK (0x4U)
+#define GPT_USER_REQ_REG_CH2_USER_ITRIG_SHIFT (2U)
+/*! CH2_USER_ITRIG - See CH0_USER_ITRIG.
+ */
+#define GPT_USER_REQ_REG_CH2_USER_ITRIG(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH2_USER_ITRIG_SHIFT)) & GPT_USER_REQ_REG_CH2_USER_ITRIG_MASK)
+#define GPT_USER_REQ_REG_CH3_USER_ITRIG_MASK (0x8U)
+#define GPT_USER_REQ_REG_CH3_USER_ITRIG_SHIFT (3U)
+/*! CH3_USER_ITRIG - See CH0_USER_ITRIG.
+ */
+#define GPT_USER_REQ_REG_CH3_USER_ITRIG(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH3_USER_ITRIG_SHIFT)) & GPT_USER_REQ_REG_CH3_USER_ITRIG_MASK)
+#define GPT_USER_REQ_REG_CH4_USER_ITRIG_MASK (0x10U)
+#define GPT_USER_REQ_REG_CH4_USER_ITRIG_SHIFT (4U)
+/*! CH4_USER_ITRIG - See CH0_USER_ITRIG.
+ */
+#define GPT_USER_REQ_REG_CH4_USER_ITRIG(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH4_USER_ITRIG_SHIFT)) & GPT_USER_REQ_REG_CH4_USER_ITRIG_MASK)
+#define GPT_USER_REQ_REG_CH5_USER_ITRIG_MASK (0x20U)
+#define GPT_USER_REQ_REG_CH5_USER_ITRIG_SHIFT (5U)
+/*! CH5_USER_ITRIG - See CH0_USER_ITRIG.
+ */
+#define GPT_USER_REQ_REG_CH5_USER_ITRIG(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH5_USER_ITRIG_SHIFT)) & GPT_USER_REQ_REG_CH5_USER_ITRIG_MASK)
+#define GPT_USER_REQ_REG_CH0_RST_MASK (0x100U)
+#define GPT_USER_REQ_REG_CH0_RST_SHIFT (8U)
+/*! CH0_RST - Channel Reset
+ * 0b0..No action
+ * 0b1..Reset this channel
+ */
+#define GPT_USER_REQ_REG_CH0_RST(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH0_RST_SHIFT)) & GPT_USER_REQ_REG_CH0_RST_MASK)
+#define GPT_USER_REQ_REG_CH1_RST_MASK (0x200U)
+#define GPT_USER_REQ_REG_CH1_RST_SHIFT (9U)
+/*! CH1_RST - See CH0_RST.
+ */
+#define GPT_USER_REQ_REG_CH1_RST(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH1_RST_SHIFT)) & GPT_USER_REQ_REG_CH1_RST_MASK)
+#define GPT_USER_REQ_REG_CH2_RST_MASK (0x400U)
+#define GPT_USER_REQ_REG_CH2_RST_SHIFT (10U)
+/*! CH2_RST - See CH0_RST.
+ */
+#define GPT_USER_REQ_REG_CH2_RST(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH2_RST_SHIFT)) & GPT_USER_REQ_REG_CH2_RST_MASK)
+#define GPT_USER_REQ_REG_CH3_RST_MASK (0x800U)
+#define GPT_USER_REQ_REG_CH3_RST_SHIFT (11U)
+/*! CH3_RST - See CH0_RST.
+ */
+#define GPT_USER_REQ_REG_CH3_RST(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH3_RST_SHIFT)) & GPT_USER_REQ_REG_CH3_RST_MASK)
+#define GPT_USER_REQ_REG_CH4_RST_MASK (0x1000U)
+#define GPT_USER_REQ_REG_CH4_RST_SHIFT (12U)
+/*! CH4_RST - See CH0_RST.
+ */
+#define GPT_USER_REQ_REG_CH4_RST(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH4_RST_SHIFT)) & GPT_USER_REQ_REG_CH4_RST_MASK)
+#define GPT_USER_REQ_REG_CH5_RST_MASK (0x2000U)
+#define GPT_USER_REQ_REG_CH5_RST_SHIFT (13U)
+/*! CH5_RST - See CH0_RST.
+ */
+#define GPT_USER_REQ_REG_CH5_RST(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH5_RST_SHIFT)) & GPT_USER_REQ_REG_CH5_RST_MASK)
+#define GPT_USER_REQ_REG_CH0_CMR_UPDT_MASK (0x10000U)
+#define GPT_USER_REQ_REG_CH0_CMR_UPDT_SHIFT (16U)
+/*! CH0_CMR_UPDT - Channel CMR Update
+ * 0b0..No action
+ * 0b1..Update CMR0 and CMR1 to the internal shadow registers
+ */
+#define GPT_USER_REQ_REG_CH0_CMR_UPDT(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH0_CMR_UPDT_SHIFT)) & GPT_USER_REQ_REG_CH0_CMR_UPDT_MASK)
+#define GPT_USER_REQ_REG_CH1_CMR_UPDT_MASK (0x20000U)
+#define GPT_USER_REQ_REG_CH1_CMR_UPDT_SHIFT (17U)
+/*! CH1_CMR_UPDT - See CH0_CMR_UPDT.
+ */
+#define GPT_USER_REQ_REG_CH1_CMR_UPDT(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH1_CMR_UPDT_SHIFT)) & GPT_USER_REQ_REG_CH1_CMR_UPDT_MASK)
+#define GPT_USER_REQ_REG_CH2_CMR_UPDT_MASK (0x40000U)
+#define GPT_USER_REQ_REG_CH2_CMR_UPDT_SHIFT (18U)
+/*! CH2_CMR_UPDT - See CH0_CMR_UPDT.
+ */
+#define GPT_USER_REQ_REG_CH2_CMR_UPDT(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH2_CMR_UPDT_SHIFT)) & GPT_USER_REQ_REG_CH2_CMR_UPDT_MASK)
+#define GPT_USER_REQ_REG_CH3_CMR_UPDT_MASK (0x80000U)
+#define GPT_USER_REQ_REG_CH3_CMR_UPDT_SHIFT (19U)
+/*! CH3_CMR_UPDT - See CH0_CMR_UPDT.
+ */
+#define GPT_USER_REQ_REG_CH3_CMR_UPDT(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH3_CMR_UPDT_SHIFT)) & GPT_USER_REQ_REG_CH3_CMR_UPDT_MASK)
+#define GPT_USER_REQ_REG_CH4_CMR_UPDT_MASK (0x100000U)
+#define GPT_USER_REQ_REG_CH4_CMR_UPDT_SHIFT (20U)
+/*! CH4_CMR_UPDT - See CH0_CMR_UPDT.
+ */
+#define GPT_USER_REQ_REG_CH4_CMR_UPDT(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH4_CMR_UPDT_SHIFT)) & GPT_USER_REQ_REG_CH4_CMR_UPDT_MASK)
+#define GPT_USER_REQ_REG_CH5_CMR_UPDT_MASK (0x200000U)
+#define GPT_USER_REQ_REG_CH5_CMR_UPDT_SHIFT (21U)
+/*! CH5_CMR_UPDT - See CH0_CMR_UPDT.
+ */
+#define GPT_USER_REQ_REG_CH5_CMR_UPDT(x) (((uint32_t)(((uint32_t)(x)) << GPT_USER_REQ_REG_CH5_CMR_UPDT_SHIFT)) & GPT_USER_REQ_REG_CH5_CMR_UPDT_MASK)
+/*! @} */
+
+/*! @name CH_CNTL_REG - Channel 0 Control Register..Channel 5 Control Register */
+/*! @{ */
+#define GPT_CH_CNTL_REG_CHX_IO_MASK (0x7U)
+#define GPT_CH_CNTL_REG_CHX_IO_SHIFT (0U)
+/*! CHx_IO - Channel Mode
+ * 0b000..No function
+ * 0b001..Input capture mode
+ * 0b100..One-shot mode (pulse)
+ * 0b101..One-shot mode (edge)
+ * 0b110..PWM mode (edge-aligned)
+ * 0b111..PWM mode (center-aligned)
+ */
+#define GPT_CH_CNTL_REG_CHX_IO(x) (((uint32_t)(((uint32_t)(x)) << GPT_CH_CNTL_REG_CHX_IO_SHIFT)) & GPT_CH_CNTL_REG_CHX_IO_MASK)
+#define GPT_CH_CNTL_REG_IC_EDGE_MASK (0x7000U)
+#define GPT_CH_CNTL_REG_IC_EDGE_SHIFT (12U)
+/*! IC_EDGE - Channel Input Capture Edge
+ * 0b000..Capture rising edge in CMR0
+ * 0b001..Capture falling edge in CMR0
+ */
+#define GPT_CH_CNTL_REG_IC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << GPT_CH_CNTL_REG_IC_EDGE_SHIFT)) & GPT_CH_CNTL_REG_IC_EDGE_MASK)
+#define GPT_CH_CNTL_REG_POL_MASK (0x10000U)
+#define GPT_CH_CNTL_REG_POL_SHIFT (16U)
+/*! POL - Channel Polarity
+ * 0b0..Reset to 0
+ * 0b1..Reset to 1
+ */
+#define GPT_CH_CNTL_REG_POL(x) (((uint32_t)(((uint32_t)(x)) << GPT_CH_CNTL_REG_POL_SHIFT)) & GPT_CH_CNTL_REG_POL_MASK)
+/*! @} */
+
+/* The count of GPT_CH_CNTL_REG */
+#define GPT_CH_CNTL_REG_COUNT (6U)
+
+/*! @name CH_CMR0_REG - Channel 0 Counter Match Register 0..Channel 5 Counter Match Register 0 */
+/*! @{ */
+#define GPT_CH_CMR0_REG_CMR0_MASK (0xFFFFFFFFU)
+#define GPT_CH_CMR0_REG_CMR0_SHIFT (0U)
+/*! CMR0 - Channel Counter Match Register 0
+ */
+#define GPT_CH_CMR0_REG_CMR0(x) (((uint32_t)(((uint32_t)(x)) << GPT_CH_CMR0_REG_CMR0_SHIFT)) & GPT_CH_CMR0_REG_CMR0_MASK)
+/*! @} */
+
+/* The count of GPT_CH_CMR0_REG */
+#define GPT_CH_CMR0_REG_COUNT (6U)
+
+/*! @name CH_STS_REG - Channel 0 Status Register 0..Channel 5 Status Register 0 */
+/*! @{ */
+#define GPT_CH_STS_REG_OUT_ST_MASK (0x1U)
+#define GPT_CH_STS_REG_OUT_ST_SHIFT (0U)
+/*! OUT_ST - Channel Output State
+ */
+#define GPT_CH_STS_REG_OUT_ST(x) (((uint32_t)(((uint32_t)(x)) << GPT_CH_STS_REG_OUT_ST_SHIFT)) & GPT_CH_STS_REG_OUT_ST_MASK)
+/*! @} */
+
+/* The count of GPT_CH_STS_REG */
+#define GPT_CH_STS_REG_COUNT (6U)
+
+/*! @name CH_CMR1_REG - Channel 0 Counter Match Register 1..Channel 5 Counter Match Register 1 */
+/*! @{ */
+#define GPT_CH_CMR1_REG_CMR1_MASK (0xFFFFFFFFU)
+#define GPT_CH_CMR1_REG_CMR1_SHIFT (0U)
+/*! CMR1 - Channel Counter Match Register 1
+ */
+#define GPT_CH_CMR1_REG_CMR1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CH_CMR1_REG_CMR1_SHIFT)) & GPT_CH_CMR1_REG_CMR1_MASK)
+/*! @} */
+
+/* The count of GPT_CH_CMR1_REG */
+#define GPT_CH_CMR1_REG_COUNT (6U)
+
+
+/*!
+ * @}
+ */ /* end of group GPT_Register_Masks */
+
+
+/* GPT - Peripheral instance base addresses */
+/** Peripheral GPT0 base address */
+#define GPT0_BASE (0x46070000u)
+/** Peripheral GPT0 base pointer */
+#define GPT0 ((GPT_Type *)GPT0_BASE)
+/** Peripheral GPT1 base address */
+#define GPT1_BASE (0x46080000u)
+/** Peripheral GPT1 base pointer */
+#define GPT1 ((GPT_Type *)GPT1_BASE)
+/** Peripheral GPT2 base address */
+#define GPT2_BASE (0x48070000u)
+/** Peripheral GPT2 base pointer */
+#define GPT2 ((GPT_Type *)GPT2_BASE)
+/** Peripheral GPT3 base address */
+#define GPT3_BASE (0x48080000u)
+/** Peripheral GPT3 base pointer */
+#define GPT3 ((GPT_Type *)GPT3_BASE)
+/** Array initializer of GPT peripheral base addresses */
+#define GPT_BASE_ADDRS { GPT0_BASE, GPT1_BASE, GPT2_BASE, GPT3_BASE }
+/** Array initializer of GPT peripheral base pointers */
+#define GPT_BASE_PTRS { GPT0, GPT1, GPT2, GPT3 }
+/** Interrupt vectors for the GPT peripheral type */
+#define GPT_IRQS { GPT0_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GPT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t IC_CON; /**< , offset: 0x0 */
+ __IO uint32_t IC_TAR; /**< , offset: 0x4 */
+ __IO uint32_t IC_SAR; /**< , offset: 0x8 */
+ __IO uint32_t IC_HS_MADDR; /**< , offset: 0xC */
+ __IO uint32_t IC_DATA_CMD; /**< , offset: 0x10 */
+ __IO uint32_t IC_SS_SCL_HCNT; /**< , offset: 0x14 */
+ __IO uint32_t IC_SS_SCL_LCNT; /**< , offset: 0x18 */
+ __IO uint32_t IC_FS_SCL_HCNT; /**< , offset: 0x1C */
+ __IO uint32_t IC_FS_SCL_LCNT; /**< , offset: 0x20 */
+ __IO uint32_t IC_HS_SCL_HCNT; /**< , offset: 0x24 */
+ __IO uint32_t IC_HS_SCL_LCNT; /**< , offset: 0x28 */
+ __I uint32_t IC_INTR_STAT; /**< , offset: 0x2C */
+ __IO uint32_t IC_INTR_MASK; /**< , offset: 0x30 */
+ __I uint32_t IC_RAW_INTR_STAT; /**< , offset: 0x34 */
+ __IO uint32_t IC_RX_TL; /**< , offset: 0x38 */
+ __IO uint32_t IC_TX_TL; /**< , offset: 0x3C */
+ __I uint32_t IC_CLR_INTR; /**< , offset: 0x40 */
+ __I uint32_t IC_CLR_RX_UNDER; /**< , offset: 0x44 */
+ __I uint32_t IC_CLR_RX_OVER; /**< , offset: 0x48 */
+ __I uint32_t IC_CLR_TX_OVER; /**< , offset: 0x4C */
+ __I uint32_t IC_CLR_RD_REQ; /**< , offset: 0x50 */
+ __I uint32_t IC_CLR_TX_ABRT; /**< , offset: 0x54 */
+ __I uint32_t IC_CLR_RX_DONE; /**< , offset: 0x58 */
+ __I uint32_t IC_CLR_ACTIVITY; /**< , offset: 0x5C */
+ __I uint32_t IC_CLR_STOP_DET; /**< , offset: 0x60 */
+ __I uint32_t IC_CLR_START_DET; /**< , offset: 0x64 */
+ __I uint32_t IC_CLR_GEN_CALL; /**< , offset: 0x68 */
+ __IO uint32_t IC_ENABLE; /**< , offset: 0x6C */
+ __I uint32_t IC_STATUS; /**< , offset: 0x70 */
+ __I uint32_t IC_TXFLR; /**< , offset: 0x74 */
+ __I uint32_t IC_RXFLR; /**< , offset: 0x78 */
+ __IO uint32_t IC_SDA_HOLD; /**< , offset: 0x7C */
+ __I uint32_t IC_TX_ABRT_SOURCE; /**< , offset: 0x80 */
+ __IO uint32_t IC_SLV_DATA_NACK_ONLY; /**< , offset: 0x84 */
+ __IO uint32_t IC_DMA_CR; /**< , offset: 0x88 */
+ __IO uint32_t IC_DMA_TDLR; /**< , offset: 0x8C */
+ __IO uint32_t IC_DMA_RDLR; /**< , offset: 0x90 */
+ __IO uint32_t IC_SDA_SETUP; /**< , offset: 0x94 */
+ __IO uint32_t IC_ACK_GENERAL_CALL; /**< , offset: 0x98 */
+ __I uint32_t IC_ENABLE_STATUS; /**< , offset: 0x9C */
+ __IO uint32_t IC_FS_SPKLEN; /**< , offset: 0xA0 */
+ __IO uint32_t IC_HS_SPKLEN; /**< , offset: 0xA4 */
+ uint8_t RESERVED_0[76];
+ __I uint32_t IC_COMP_PARAM_1; /**< , offset: 0xF4 */
+ __I uint32_t IC_COMP_VERSION; /**< , offset: 0xF8 */
+ __I uint32_t IC_COMP_TYPE; /**< , offset: 0xFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name IC_CON - */
+/*! @{ */
+#define I2C_IC_CON_MASTER_MODE_MASK (0x1U)
+#define I2C_IC_CON_MASTER_MODE_SHIFT (0U)
+/*! MASTER_MODE
+ * 0b0..master disabled
+ * 0b1..master enabled
+ */
+#define I2C_IC_CON_MASTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CON_MASTER_MODE_SHIFT)) & I2C_IC_CON_MASTER_MODE_MASK)
+#define I2C_IC_CON_SPEED_MASK (0x6U)
+#define I2C_IC_CON_SPEED_SHIFT (1U)
+/*! SPEED
+ * 0b01..standard mode (100 kbit/s)
+ * 0b10..fast mode (400 kbit/s)
+ * 0b11..high speed mode (3.4 Mbit/s)
+ */
+#define I2C_IC_CON_SPEED(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CON_SPEED_SHIFT)) & I2C_IC_CON_SPEED_MASK)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_MASK (0x8U)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_SHIFT (3U)
+/*! IC_10BITADDR_SLAVE
+ * 0b0..7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit
+ * addressing, only the lower 7 bits of the IC_SAR register are compared.
+ * 0b1..10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
+ */
+#define I2C_IC_CON_IC_10BITADDR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CON_IC_10BITADDR_SLAVE_SHIFT)) & I2C_IC_CON_IC_10BITADDR_SLAVE_MASK)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_MASK (0x10U)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_SHIFT (4U)
+/*! IC_10BITADDR_MASTER_rd_only
+ * 0b0..7-bit addressing
+ * 0b1..10-bit addressing
+ */
+#define I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_SHIFT)) & I2C_IC_CON_IC_10BITADDR_MASTER_RD_ONLY_MASK)
+#define I2C_IC_CON_IC_RESTART_EN_MASK (0x20U)
+#define I2C_IC_CON_IC_RESTART_EN_SHIFT (5U)
+/*! IC_RESTART_EN
+ * 0b0..disable
+ * 0b1..enable
+ */
+#define I2C_IC_CON_IC_RESTART_EN(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CON_IC_RESTART_EN_SHIFT)) & I2C_IC_CON_IC_RESTART_EN_MASK)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_MASK (0x40U)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_SHIFT (6U)
+/*! IC_SLAVE_DISABLE
+ * 0b0..slave is enabled
+ * 0b1..slave is disabled
+ */
+#define I2C_IC_CON_IC_SLAVE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CON_IC_SLAVE_DISABLE_SHIFT)) & I2C_IC_CON_IC_SLAVE_DISABLE_MASK)
+/*! @} */
+
+/*! @name IC_TAR - */
+/*! @{ */
+#define I2C_IC_TAR_IC_TAR_MASK (0x3FFU)
+#define I2C_IC_TAR_IC_TAR_SHIFT (0U)
+#define I2C_IC_TAR_IC_TAR(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TAR_IC_TAR_SHIFT)) & I2C_IC_TAR_IC_TAR_MASK)
+#define I2C_IC_TAR_GC_OR_START_MASK (0x400U)
+#define I2C_IC_TAR_GC_OR_START_SHIFT (10U)
+/*! GC_OR_START
+ * 0b0..General Call Address after issuing a General Call, only writes may be performed. Attempting to issue a
+ * read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in
+ * General Call mode until the SPECIAL bit value (bit 11) is cleared.
+ * 0b1..START BYTE
+ */
+#define I2C_IC_TAR_GC_OR_START(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TAR_GC_OR_START_SHIFT)) & I2C_IC_TAR_GC_OR_START_MASK)
+#define I2C_IC_TAR_SPECIAL_MASK (0x800U)
+#define I2C_IC_TAR_SPECIAL_SHIFT (11U)
+/*! SPECIAL
+ * 0b0..ignore bit 10 GC_OR_START and use IC_TAR normally
+ * 0b1..perform special I2C command as specified in GC_OR_START bit
+ */
+#define I2C_IC_TAR_SPECIAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TAR_SPECIAL_SHIFT)) & I2C_IC_TAR_SPECIAL_MASK)
+#define I2C_IC_TAR_IC_10BITADDR_MASTER_MASK (0x1000U)
+#define I2C_IC_TAR_IC_10BITADDR_MASTER_SHIFT (12U)
+/*! IC_10BITADDR_MASTER
+ * 0b0..7-bit addressing
+ * 0b1..10-bit addressing
+ */
+#define I2C_IC_TAR_IC_10BITADDR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TAR_IC_10BITADDR_MASTER_SHIFT)) & I2C_IC_TAR_IC_10BITADDR_MASTER_MASK)
+/*! @} */
+
+/*! @name IC_SAR - */
+/*! @{ */
+#define I2C_IC_SAR_IC_SAR_MASK (0x3FFU)
+#define I2C_IC_SAR_IC_SAR_SHIFT (0U)
+#define I2C_IC_SAR_IC_SAR(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_SAR_IC_SAR_SHIFT)) & I2C_IC_SAR_IC_SAR_MASK)
+/*! @} */
+
+/*! @name IC_HS_MADDR - */
+/*! @{ */
+#define I2C_IC_HS_MADDR_IC_HS_MAR_MASK (0x7U)
+#define I2C_IC_HS_MADDR_IC_HS_MAR_SHIFT (0U)
+#define I2C_IC_HS_MADDR_IC_HS_MAR(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_HS_MADDR_IC_HS_MAR_SHIFT)) & I2C_IC_HS_MADDR_IC_HS_MAR_MASK)
+/*! @} */
+
+/*! @name IC_DATA_CMD - */
+/*! @{ */
+#define I2C_IC_DATA_CMD_DAT_MASK (0xFFU)
+#define I2C_IC_DATA_CMD_DAT_SHIFT (0U)
+#define I2C_IC_DATA_CMD_DAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_DATA_CMD_DAT_SHIFT)) & I2C_IC_DATA_CMD_DAT_MASK)
+#define I2C_IC_DATA_CMD_CMD_MASK (0x100U)
+#define I2C_IC_DATA_CMD_CMD_SHIFT (8U)
+/*! CMD
+ * 0b0..Write
+ * 0b1..Read
+ */
+#define I2C_IC_DATA_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_DATA_CMD_CMD_SHIFT)) & I2C_IC_DATA_CMD_CMD_MASK)
+/*! @} */
+
+/*! @name IC_SS_SCL_HCNT - */
+/*! @{ */
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MASK (0xFFFFU)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_SHIFT (0U)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_SHIFT)) & I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MASK)
+/*! @} */
+
+/*! @name IC_SS_SCL_LCNT - */
+/*! @{ */
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MASK (0xFFFFU)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_SHIFT (0U)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_SHIFT)) & I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MASK)
+/*! @} */
+
+/*! @name IC_FS_SCL_HCNT - */
+/*! @{ */
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MASK (0xFFFFU)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_SHIFT (0U)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_SHIFT)) & I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MASK)
+/*! @} */
+
+/*! @name IC_FS_SCL_LCNT - */
+/*! @{ */
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MASK (0xFFFFU)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_SHIFT (0U)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_SHIFT)) & I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MASK)
+/*! @} */
+
+/*! @name IC_HS_SCL_HCNT - */
+/*! @{ */
+#define I2C_IC_HS_SCL_HCNT_IC_HS_SCL_HCNT_MASK (0xFFFFU)
+#define I2C_IC_HS_SCL_HCNT_IC_HS_SCL_HCNT_SHIFT (0U)
+#define I2C_IC_HS_SCL_HCNT_IC_HS_SCL_HCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_HS_SCL_HCNT_IC_HS_SCL_HCNT_SHIFT)) & I2C_IC_HS_SCL_HCNT_IC_HS_SCL_HCNT_MASK)
+/*! @} */
+
+/*! @name IC_HS_SCL_LCNT - */
+/*! @{ */
+#define I2C_IC_HS_SCL_LCNT_IC_HS_SCL_LCNT_MASK (0xFFFFU)
+#define I2C_IC_HS_SCL_LCNT_IC_HS_SCL_LCNT_SHIFT (0U)
+#define I2C_IC_HS_SCL_LCNT_IC_HS_SCL_LCNT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_HS_SCL_LCNT_IC_HS_SCL_LCNT_SHIFT)) & I2C_IC_HS_SCL_LCNT_IC_HS_SCL_LCNT_MASK)
+/*! @} */
+
+/*! @name IC_INTR_STAT - */
+/*! @{ */
+#define I2C_IC_INTR_STAT_R_RX_UNDER_MASK (0x1U)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_SHIFT (0U)
+#define I2C_IC_INTR_STAT_R_RX_UNDER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_RX_UNDER_SHIFT)) & I2C_IC_INTR_STAT_R_RX_UNDER_MASK)
+#define I2C_IC_INTR_STAT_R_RX_OVER_MASK (0x2U)
+#define I2C_IC_INTR_STAT_R_RX_OVER_SHIFT (1U)
+#define I2C_IC_INTR_STAT_R_RX_OVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_RX_OVER_SHIFT)) & I2C_IC_INTR_STAT_R_RX_OVER_MASK)
+#define I2C_IC_INTR_STAT_R_RX_FULL_MASK (0x4U)
+#define I2C_IC_INTR_STAT_R_RX_FULL_SHIFT (2U)
+#define I2C_IC_INTR_STAT_R_RX_FULL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_RX_FULL_SHIFT)) & I2C_IC_INTR_STAT_R_RX_FULL_MASK)
+#define I2C_IC_INTR_STAT_R_TX_OVER_MASK (0x8U)
+#define I2C_IC_INTR_STAT_R_TX_OVER_SHIFT (3U)
+#define I2C_IC_INTR_STAT_R_TX_OVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_TX_OVER_SHIFT)) & I2C_IC_INTR_STAT_R_TX_OVER_MASK)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_MASK (0x10U)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_SHIFT (4U)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_TX_EMPTY_SHIFT)) & I2C_IC_INTR_STAT_R_TX_EMPTY_MASK)
+#define I2C_IC_INTR_STAT_R_RD_REQ_MASK (0x20U)
+#define I2C_IC_INTR_STAT_R_RD_REQ_SHIFT (5U)
+#define I2C_IC_INTR_STAT_R_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_RD_REQ_SHIFT)) & I2C_IC_INTR_STAT_R_RD_REQ_MASK)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_MASK (0x40U)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_SHIFT (6U)
+#define I2C_IC_INTR_STAT_R_TX_ABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_TX_ABRT_SHIFT)) & I2C_IC_INTR_STAT_R_TX_ABRT_MASK)
+#define I2C_IC_INTR_STAT_R_RX_DONE_MASK (0x80U)
+#define I2C_IC_INTR_STAT_R_RX_DONE_SHIFT (7U)
+#define I2C_IC_INTR_STAT_R_RX_DONE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_RX_DONE_SHIFT)) & I2C_IC_INTR_STAT_R_RX_DONE_MASK)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_MASK (0x100U)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_SHIFT (8U)
+#define I2C_IC_INTR_STAT_R_ACTIVITY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_ACTIVITY_SHIFT)) & I2C_IC_INTR_STAT_R_ACTIVITY_MASK)
+#define I2C_IC_INTR_STAT_R_STOP_DET_MASK (0x200U)
+#define I2C_IC_INTR_STAT_R_STOP_DET_SHIFT (9U)
+#define I2C_IC_INTR_STAT_R_STOP_DET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_STOP_DET_SHIFT)) & I2C_IC_INTR_STAT_R_STOP_DET_MASK)
+#define I2C_IC_INTR_STAT_R_START_DET_MASK (0x400U)
+#define I2C_IC_INTR_STAT_R_START_DET_SHIFT (10U)
+#define I2C_IC_INTR_STAT_R_START_DET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_START_DET_SHIFT)) & I2C_IC_INTR_STAT_R_START_DET_MASK)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_MASK (0x800U)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_SHIFT (11U)
+#define I2C_IC_INTR_STAT_R_GEN_CALL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_STAT_R_GEN_CALL_SHIFT)) & I2C_IC_INTR_STAT_R_GEN_CALL_MASK)
+/*! @} */
+
+/*! @name IC_INTR_MASK - */
+/*! @{ */
+#define I2C_IC_INTR_MASK_M_RX_UNDER_MASK (0x1U)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_SHIFT (0U)
+#define I2C_IC_INTR_MASK_M_RX_UNDER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_RX_UNDER_SHIFT)) & I2C_IC_INTR_MASK_M_RX_UNDER_MASK)
+#define I2C_IC_INTR_MASK_M_RX_OVER_MASK (0x2U)
+#define I2C_IC_INTR_MASK_M_RX_OVER_SHIFT (1U)
+#define I2C_IC_INTR_MASK_M_RX_OVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_RX_OVER_SHIFT)) & I2C_IC_INTR_MASK_M_RX_OVER_MASK)
+#define I2C_IC_INTR_MASK_M_RX_FULL_MASK (0x4U)
+#define I2C_IC_INTR_MASK_M_RX_FULL_SHIFT (2U)
+#define I2C_IC_INTR_MASK_M_RX_FULL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_RX_FULL_SHIFT)) & I2C_IC_INTR_MASK_M_RX_FULL_MASK)
+#define I2C_IC_INTR_MASK_M_TX_OVER_MASK (0x8U)
+#define I2C_IC_INTR_MASK_M_TX_OVER_SHIFT (3U)
+#define I2C_IC_INTR_MASK_M_TX_OVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_TX_OVER_SHIFT)) & I2C_IC_INTR_MASK_M_TX_OVER_MASK)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_MASK (0x10U)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_SHIFT (4U)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_TX_EMPTY_SHIFT)) & I2C_IC_INTR_MASK_M_TX_EMPTY_MASK)
+#define I2C_IC_INTR_MASK_M_RD_REQ_MASK (0x20U)
+#define I2C_IC_INTR_MASK_M_RD_REQ_SHIFT (5U)
+#define I2C_IC_INTR_MASK_M_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_RD_REQ_SHIFT)) & I2C_IC_INTR_MASK_M_RD_REQ_MASK)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_MASK (0x40U)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_SHIFT (6U)
+#define I2C_IC_INTR_MASK_M_TX_ABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_TX_ABRT_SHIFT)) & I2C_IC_INTR_MASK_M_TX_ABRT_MASK)
+#define I2C_IC_INTR_MASK_M_RX_DONE_MASK (0x80U)
+#define I2C_IC_INTR_MASK_M_RX_DONE_SHIFT (7U)
+#define I2C_IC_INTR_MASK_M_RX_DONE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_RX_DONE_SHIFT)) & I2C_IC_INTR_MASK_M_RX_DONE_MASK)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_MASK (0x100U)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_SHIFT (8U)
+#define I2C_IC_INTR_MASK_M_ACTIVITY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_ACTIVITY_SHIFT)) & I2C_IC_INTR_MASK_M_ACTIVITY_MASK)
+#define I2C_IC_INTR_MASK_M_STOP_DET_MASK (0x200U)
+#define I2C_IC_INTR_MASK_M_STOP_DET_SHIFT (9U)
+#define I2C_IC_INTR_MASK_M_STOP_DET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_STOP_DET_SHIFT)) & I2C_IC_INTR_MASK_M_STOP_DET_MASK)
+#define I2C_IC_INTR_MASK_M_START_DET_MASK (0x400U)
+#define I2C_IC_INTR_MASK_M_START_DET_SHIFT (10U)
+#define I2C_IC_INTR_MASK_M_START_DET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_START_DET_SHIFT)) & I2C_IC_INTR_MASK_M_START_DET_MASK)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_MASK (0x800U)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_SHIFT (11U)
+#define I2C_IC_INTR_MASK_M_GEN_CALL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_INTR_MASK_M_GEN_CALL_SHIFT)) & I2C_IC_INTR_MASK_M_GEN_CALL_MASK)
+/*! @} */
+
+/*! @name IC_RAW_INTR_STAT - */
+/*! @{ */
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MASK (0x1U)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_SHIFT (0U)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_RX_UNDER_SHIFT)) & I2C_IC_RAW_INTR_STAT_RX_UNDER_MASK)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_MASK (0x2U)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_SHIFT (1U)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_RX_OVER_SHIFT)) & I2C_IC_RAW_INTR_STAT_RX_OVER_MASK)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_MASK (0x4U)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_SHIFT (2U)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_RX_FULL_SHIFT)) & I2C_IC_RAW_INTR_STAT_RX_FULL_MASK)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_MASK (0x8U)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_SHIFT (3U)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_TX_OVER_SHIFT)) & I2C_IC_RAW_INTR_STAT_TX_OVER_MASK)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MASK (0x10U)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_SHIFT (4U)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_TX_EMPTY_SHIFT)) & I2C_IC_RAW_INTR_STAT_TX_EMPTY_MASK)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_MASK (0x20U)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_SHIFT (5U)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_RD_REQ_SHIFT)) & I2C_IC_RAW_INTR_STAT_RD_REQ_MASK)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MASK (0x40U)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_SHIFT (6U)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_TX_ABRT_SHIFT)) & I2C_IC_RAW_INTR_STAT_TX_ABRT_MASK)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_MASK (0x80U)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_SHIFT (7U)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_RX_DONE_SHIFT)) & I2C_IC_RAW_INTR_STAT_RX_DONE_MASK)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MASK (0x100U)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_SHIFT (8U)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_ACTIVITY_SHIFT)) & I2C_IC_RAW_INTR_STAT_ACTIVITY_MASK)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_MASK (0x200U)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_SHIFT (9U)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_STOP_DET_SHIFT)) & I2C_IC_RAW_INTR_STAT_STOP_DET_MASK)
+#define I2C_IC_RAW_INTR_STAT_START_DET_MASK (0x400U)
+#define I2C_IC_RAW_INTR_STAT_START_DET_SHIFT (10U)
+#define I2C_IC_RAW_INTR_STAT_START_DET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_START_DET_SHIFT)) & I2C_IC_RAW_INTR_STAT_START_DET_MASK)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MASK (0x800U)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_SHIFT (11U)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RAW_INTR_STAT_GEN_CALL_SHIFT)) & I2C_IC_RAW_INTR_STAT_GEN_CALL_MASK)
+/*! @} */
+
+/*! @name IC_RX_TL - */
+/*! @{ */
+#define I2C_IC_RX_TL_RX_TL_MASK (0xFFU)
+#define I2C_IC_RX_TL_RX_TL_SHIFT (0U)
+#define I2C_IC_RX_TL_RX_TL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RX_TL_RX_TL_SHIFT)) & I2C_IC_RX_TL_RX_TL_MASK)
+/*! @} */
+
+/*! @name IC_TX_TL - */
+/*! @{ */
+#define I2C_IC_TX_TL_TX_TL_MASK (0xFFU)
+#define I2C_IC_TX_TL_TX_TL_SHIFT (0U)
+#define I2C_IC_TX_TL_TX_TL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_TL_TX_TL_SHIFT)) & I2C_IC_TX_TL_TX_TL_MASK)
+/*! @} */
+
+/*! @name IC_CLR_INTR - */
+/*! @{ */
+#define I2C_IC_CLR_INTR_CLR_INTR_MASK (0x1U)
+#define I2C_IC_CLR_INTR_CLR_INTR_SHIFT (0U)
+#define I2C_IC_CLR_INTR_CLR_INTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_INTR_CLR_INTR_SHIFT)) & I2C_IC_CLR_INTR_CLR_INTR_MASK)
+/*! @} */
+
+/*! @name IC_CLR_RX_UNDER - */
+/*! @{ */
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MASK (0x1U)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_SHIFT (0U)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_SHIFT)) & I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MASK)
+/*! @} */
+
+/*! @name IC_CLR_RX_OVER - */
+/*! @{ */
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MASK (0x1U)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_SHIFT (0U)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_RX_OVER_CLR_RX_OVER_SHIFT)) & I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MASK)
+/*! @} */
+
+/*! @name IC_CLR_TX_OVER - */
+/*! @{ */
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MASK (0x1U)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_SHIFT (0U)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_TX_OVER_CLR_TX_OVER_SHIFT)) & I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MASK)
+/*! @} */
+
+/*! @name IC_CLR_RD_REQ - */
+/*! @{ */
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MASK (0x1U)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_SHIFT (0U)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_RD_REQ_CLR_RD_REQ_SHIFT)) & I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MASK)
+/*! @} */
+
+/*! @name IC_CLR_TX_ABRT - */
+/*! @{ */
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MASK (0x1U)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_SHIFT (0U)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_SHIFT)) & I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MASK)
+/*! @} */
+
+/*! @name IC_CLR_RX_DONE - */
+/*! @{ */
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MASK (0x1U)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_SHIFT (0U)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_RX_DONE_CLR_RX_DONE_SHIFT)) & I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MASK)
+/*! @} */
+
+/*! @name IC_CLR_ACTIVITY - */
+/*! @{ */
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MASK (0x1U)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_SHIFT (0U)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_SHIFT)) & I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MASK)
+/*! @} */
+
+/*! @name IC_CLR_STOP_DET - */
+/*! @{ */
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MASK (0x1U)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_SHIFT (0U)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_STOP_DET_CLR_STOP_DET_SHIFT)) & I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MASK)
+/*! @} */
+
+/*! @name IC_CLR_START_DET - */
+/*! @{ */
+#define I2C_IC_CLR_START_DET_CLR_START_DET_MASK (0x1U)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_SHIFT (0U)
+#define I2C_IC_CLR_START_DET_CLR_START_DET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_START_DET_CLR_START_DET_SHIFT)) & I2C_IC_CLR_START_DET_CLR_START_DET_MASK)
+/*! @} */
+
+/*! @name IC_CLR_GEN_CALL - */
+/*! @{ */
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MASK (0x1U)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_SHIFT (0U)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_SHIFT)) & I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MASK)
+/*! @} */
+
+/*! @name IC_ENABLE - */
+/*! @{ */
+#define I2C_IC_ENABLE_ENABLE_MASK (0x1U)
+#define I2C_IC_ENABLE_ENABLE_SHIFT (0U)
+/*! ENABLE
+ * 0b0..Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state)
+ * 0b1..Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care
+ * be taken to ensure that DW_apb_i2c is disabled properly. When DW_apb_i2c is disabled, the following
+ * occurs:
+ */
+#define I2C_IC_ENABLE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_ENABLE_ENABLE_SHIFT)) & I2C_IC_ENABLE_ENABLE_MASK)
+/*! @} */
+
+/*! @name IC_STATUS - */
+/*! @{ */
+#define I2C_IC_STATUS_ACTIVITY_MASK (0x1U)
+#define I2C_IC_STATUS_ACTIVITY_SHIFT (0U)
+#define I2C_IC_STATUS_ACTIVITY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_STATUS_ACTIVITY_SHIFT)) & I2C_IC_STATUS_ACTIVITY_MASK)
+#define I2C_IC_STATUS_TFNF_MASK (0x2U)
+#define I2C_IC_STATUS_TFNF_SHIFT (1U)
+/*! TFNF
+ * 0b0..Transmit FIFO is full
+ * 0b1..Transmit FIFO is not full
+ */
+#define I2C_IC_STATUS_TFNF(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_STATUS_TFNF_SHIFT)) & I2C_IC_STATUS_TFNF_MASK)
+#define I2C_IC_STATUS_TFE_MASK (0x4U)
+#define I2C_IC_STATUS_TFE_SHIFT (2U)
+/*! TFE
+ * 0b0..Transmit FIFO is not empty
+ * 0b1..Transmit FIFO is empty
+ */
+#define I2C_IC_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_STATUS_TFE_SHIFT)) & I2C_IC_STATUS_TFE_MASK)
+#define I2C_IC_STATUS_RFNE_MASK (0x8U)
+#define I2C_IC_STATUS_RFNE_SHIFT (3U)
+/*! RFNE
+ * 0b0..Receive FIFO is empty
+ * 0b1..Receive FIFO is not empty
+ */
+#define I2C_IC_STATUS_RFNE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_STATUS_RFNE_SHIFT)) & I2C_IC_STATUS_RFNE_MASK)
+#define I2C_IC_STATUS_RFF_MASK (0x10U)
+#define I2C_IC_STATUS_RFF_SHIFT (4U)
+/*! RFF
+ * 0b0..Receive FIFO is not full
+ * 0b1..Receive FIFO is full
+ */
+#define I2C_IC_STATUS_RFF(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_STATUS_RFF_SHIFT)) & I2C_IC_STATUS_RFF_MASK)
+#define I2C_IC_STATUS_MST_ACTIVITY_MASK (0x20U)
+#define I2C_IC_STATUS_MST_ACTIVITY_SHIFT (5U)
+/*! MST_ACTIVITY
+ * 0b0..Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active
+ * 0b1..Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note IC_STATUS[0]-that is,
+ * ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
+ */
+#define I2C_IC_STATUS_MST_ACTIVITY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_STATUS_MST_ACTIVITY_SHIFT)) & I2C_IC_STATUS_MST_ACTIVITY_MASK)
+#define I2C_IC_STATUS_SLV_ACTIVITY_MASK (0x40U)
+#define I2C_IC_STATUS_SLV_ACTIVITY_SHIFT (6U)
+/*! SLV_ACTIVITY
+ * 0b0..Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active
+ * 0b1..Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active
+ */
+#define I2C_IC_STATUS_SLV_ACTIVITY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_STATUS_SLV_ACTIVITY_SHIFT)) & I2C_IC_STATUS_SLV_ACTIVITY_MASK)
+/*! @} */
+
+/*! @name IC_TXFLR - */
+/*! @{ */
+#define I2C_IC_TXFLR_TXFLR_MASK (0x1FU)
+#define I2C_IC_TXFLR_TXFLR_SHIFT (0U)
+#define I2C_IC_TXFLR_TXFLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TXFLR_TXFLR_SHIFT)) & I2C_IC_TXFLR_TXFLR_MASK)
+/*! @} */
+
+/*! @name IC_RXFLR - */
+/*! @{ */
+#define I2C_IC_RXFLR_RXFLR_MASK (0x1FU)
+#define I2C_IC_RXFLR_RXFLR_SHIFT (0U)
+#define I2C_IC_RXFLR_RXFLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_RXFLR_RXFLR_SHIFT)) & I2C_IC_RXFLR_RXFLR_MASK)
+/*! @} */
+
+/*! @name IC_SDA_HOLD - */
+/*! @{ */
+#define I2C_IC_SDA_HOLD_IC_SDA_HOLD_MASK (0xFFFFU)
+#define I2C_IC_SDA_HOLD_IC_SDA_HOLD_SHIFT (0U)
+#define I2C_IC_SDA_HOLD_IC_SDA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_SDA_HOLD_IC_SDA_HOLD_SHIFT)) & I2C_IC_SDA_HOLD_IC_SDA_HOLD_MASK)
+/*! @} */
+
+/*! @name IC_TX_ABRT_SOURCE - */
+/*! @{ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MASK (0x1U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_SHIFT (0U)
+/*! ABRT_7B_ADDR_NOACK
+ * 0b1..Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MASK (0x2U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_SHIFT (1U)
+/*! ABRT_10ADDR1_NOACK
+ * 0b1..Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MASK (0x4U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_SHIFT (2U)
+/*! ABRT_10ADDR2_NOACK
+ * 0b1..Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MASK (0x8U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_SHIFT (3U)
+/*! ABRT_TXDATA_NOACK
+ * 0b1..This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent
+ * data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MASK (0x10U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_SHIFT (4U)
+/*! ABRT_GCALL_NOACK
+ * 0b1..DW_apb_i2c in master mode sent a General Call and no slave on the bus acknowledged the General Call.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MASK (0x20U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_SHIFT (5U)
+/*! ABRT_GCALL_READ
+ * 0b1..DW_apb_i2c in master mode sent a General Call but the user programmed the byte following the General Call
+ * to be a read from the bus (IC_DATA_CMD[9] is set to 1).
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MASK (0x40U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_SHIFT (6U)
+/*! ABRT_HS_ACKDET
+ * 0b1..Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MASK (0x80U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_SHIFT (7U)
+/*! ABRT_SBYTE_ACKDET
+ * 0b1..Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MASK (0x100U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_SHIFT (8U)
+/*! ABRT_HS_NORSTRT
+ * 0b1..The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MASK (0x200U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_SHIFT (9U)
+/*! ABRT_SBYTE_NORSTRT
+ * 0b1..The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MASK (0x400U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_SHIFT (10U)
+/*! ABRT_10B_RD_NORSTRT
+ * 0b1..The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MASK (0x800U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_SHIFT (11U)
+/*! ABRT_MASTER_DIS
+ * 0b1..User tries to initiate a Master operation with the Master mode disabled.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MASK (0x1000U)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_SHIFT (12U)
+/*! ARB_LOST
+ * 0b1..Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ARB_LOST_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MASK (0x2000U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_SHIFT (13U)
+/*! ABRT_SLVFLUSH_TXFIFO
+ * 0b1..Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MASK (0x4000U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_SHIFT (14U)
+/*! ABRT_SLV_ARBLOST
+ * 0b1..Slave lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MASK)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MASK (0x8000U)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_SHIFT (15U)
+/*! ABRT_SLVRD_INTX
+ * 0b1..When the processor side responds to a slave mode request for data to be transmitted to a remote master
+ * and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
+ */
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_SHIFT)) & I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MASK)
+/*! @} */
+
+/*! @name IC_SLV_DATA_NACK_ONLY - */
+/*! @{ */
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MASK (0x1U)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_SHIFT (0U)
+/*! NACK
+ * 0b0..generate NACK/ACK normally
+ * 0b1..generate NACK after data byte received
+ */
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_SLV_DATA_NACK_ONLY_NACK_SHIFT)) & I2C_IC_SLV_DATA_NACK_ONLY_NACK_MASK)
+/*! @} */
+
+/*! @name IC_DMA_CR - */
+/*! @{ */
+#define I2C_IC_DMA_CR_RDMAE_MASK (0x1U)
+#define I2C_IC_DMA_CR_RDMAE_SHIFT (0U)
+/*! RDMAE
+ * 0b0..Receive DMA disabled
+ * 0b1..Receive DMA enabled
+ */
+#define I2C_IC_DMA_CR_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_DMA_CR_RDMAE_SHIFT)) & I2C_IC_DMA_CR_RDMAE_MASK)
+#define I2C_IC_DMA_CR_TDMAE_MASK (0x2U)
+#define I2C_IC_DMA_CR_TDMAE_SHIFT (1U)
+/*! TDMAE
+ * 0b0..Transmit DMA disabled
+ * 0b1..Transmit DMA enabled
+ */
+#define I2C_IC_DMA_CR_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_DMA_CR_TDMAE_SHIFT)) & I2C_IC_DMA_CR_TDMAE_MASK)
+/*! @} */
+
+/*! @name IC_DMA_TDLR - */
+/*! @{ */
+#define I2C_IC_DMA_TDLR_DMATDL_MASK (0xFU)
+#define I2C_IC_DMA_TDLR_DMATDL_SHIFT (0U)
+#define I2C_IC_DMA_TDLR_DMATDL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_DMA_TDLR_DMATDL_SHIFT)) & I2C_IC_DMA_TDLR_DMATDL_MASK)
+/*! @} */
+
+/*! @name IC_DMA_RDLR - */
+/*! @{ */
+#define I2C_IC_DMA_RDLR_DMARDL_MASK (0xFU)
+#define I2C_IC_DMA_RDLR_DMARDL_SHIFT (0U)
+#define I2C_IC_DMA_RDLR_DMARDL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_DMA_RDLR_DMARDL_SHIFT)) & I2C_IC_DMA_RDLR_DMARDL_MASK)
+/*! @} */
+
+/*! @name IC_SDA_SETUP - */
+/*! @{ */
+#define I2C_IC_SDA_SETUP_SDA_SETUP_MASK (0xFFU)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_SHIFT (0U)
+#define I2C_IC_SDA_SETUP_SDA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_SDA_SETUP_SDA_SETUP_SHIFT)) & I2C_IC_SDA_SETUP_SDA_SETUP_MASK)
+/*! @} */
+
+/*! @name IC_ACK_GENERAL_CALL - */
+/*! @{ */
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MASK (0x1U)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_SHIFT (0U)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_SHIFT)) & I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MASK)
+/*! @} */
+
+/*! @name IC_ENABLE_STATUS - */
+/*! @{ */
+#define I2C_IC_ENABLE_STATUS_IC_EN_MASK (0x1U)
+#define I2C_IC_ENABLE_STATUS_IC_EN_SHIFT (0U)
+#define I2C_IC_ENABLE_STATUS_IC_EN(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_ENABLE_STATUS_IC_EN_SHIFT)) & I2C_IC_ENABLE_STATUS_IC_EN_MASK)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MASK (0x2U)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_SHIFT (1U)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_SHIFT)) & I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MASK)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MASK (0x4U)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_SHIFT (2U)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_SHIFT)) & I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MASK)
+/*! @} */
+
+/*! @name IC_FS_SPKLEN - */
+/*! @{ */
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MASK (0xFFU)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_SHIFT (0U)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_SHIFT)) & I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MASK)
+/*! @} */
+
+/*! @name IC_HS_SPKLEN - */
+/*! @{ */
+#define I2C_IC_HS_SPKLEN_IC_HS_SPKLEN_MASK (0xFFU)
+#define I2C_IC_HS_SPKLEN_IC_HS_SPKLEN_SHIFT (0U)
+#define I2C_IC_HS_SPKLEN_IC_HS_SPKLEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_HS_SPKLEN_IC_HS_SPKLEN_SHIFT)) & I2C_IC_HS_SPKLEN_IC_HS_SPKLEN_MASK)
+/*! @} */
+
+/*! @name IC_COMP_PARAM_1 - */
+/*! @{ */
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MASK (0x3U)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_SHIFT (0U)
+/*! APB_DATA_WIDTH
+ * 0b00..8 bits
+ * 0b01..16 bits
+ * 0b10..32 bits
+ * 0b11..Reserved
+ */
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_SHIFT)) & I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MASK)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MASK (0xCU)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SHIFT (2U)
+/*! MAX_SPEED_MODE
+ * 0b00..Reserved
+ * 0b01..Standard
+ * 0b10..Fast
+ * 0b11..High
+ */
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_SHIFT)) & I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MASK)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MASK (0x10U)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_SHIFT (4U)
+/*! HC_COUNT_VALUES
+ * 0b0..False
+ * 0b1..True
+ */
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_SHIFT)) & I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MASK)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_MASK (0x20U)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_SHIFT (5U)
+/*! INTR_IO
+ * 0b0..Individual
+ * 0b1..Combined
+ */
+#define I2C_IC_COMP_PARAM_1_INTR_IO(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_PARAM_1_INTR_IO_SHIFT)) & I2C_IC_COMP_PARAM_1_INTR_IO_MASK)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_MASK (0x40U)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_SHIFT (6U)
+/*! HAS_DMA
+ * 0b0..False
+ * 0b1..True
+ */
+#define I2C_IC_COMP_PARAM_1_HAS_DMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_PARAM_1_HAS_DMA_SHIFT)) & I2C_IC_COMP_PARAM_1_HAS_DMA_MASK)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MASK (0x80U)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_SHIFT (7U)
+/*! ADD_ENCODED_PARAMS
+ * 0b0..False
+ * 0b1..True
+ */
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_SHIFT)) & I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MASK)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MASK (0xFF00U)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SHIFT (8U)
+/*! RX_BUFFER_DEPTH
+ * 0b00000000..Reserved
+ * 0b00000001..2
+ * 0b00000010..3 to
+ * 0b11111111..256
+ */
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SHIFT)) & I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MASK)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MASK (0xFF0000U)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SHIFT (16U)
+/*! TX_BUFFER_DEPTH
+ * 0b00000000..Reserved
+ * 0b00000001..2
+ * 0b00000010..3 to
+ * 0b11111111..256
+ */
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SHIFT)) & I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MASK)
+/*! @} */
+
+/*! @name IC_COMP_VERSION - */
+/*! @{ */
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MASK (0xFFFFFFFFU)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_SHIFT (0U)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_VERSION_IC_COMP_VERSION_SHIFT)) & I2C_IC_COMP_VERSION_IC_COMP_VERSION_MASK)
+/*! @} */
+
+/*! @name IC_COMP_TYPE - */
+/*! @{ */
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MASK (0xFFFFFFFFU)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_SHIFT (0U)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << I2C_IC_COMP_TYPE_IC_COMP_TYPE_SHIFT)) & I2C_IC_COMP_TYPE_IC_COMP_TYPE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x46000000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x48050000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PINMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINMUX_Peripheral_Access_Layer PINMUX Peripheral Access Layer
+ * @{
+ */
+
+/** PINMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t _GPIO0; /**< padring pin Register, offset: 0x0 */
+ __IO uint32_t _GPIO1; /**< padring pin Register, offset: 0x4 */
+ __IO uint32_t _GPIO2; /**< padring pin Register, offset: 0x8 */
+ __IO uint32_t _GPIO3; /**< padring pin Register, offset: 0xC */
+ __IO uint32_t _GPIO4; /**< padring pin Register, offset: 0x10 */
+ __IO uint32_t _GPIO5; /**< padring pin Register, offset: 0x14 */
+ __IO uint32_t _GPIO6; /**< padring pin Register, offset: 0x18 */
+ __IO uint32_t _GPIO7; /**< padring pin Register, offset: 0x1C */
+ __IO uint32_t _GPIO8; /**< padring pin Register, offset: 0x20 */
+ __IO uint32_t _GPIO9; /**< padring pin Register, offset: 0x24 */
+ __IO uint32_t _GPIO10; /**< padring pin Register, offset: 0x28 */
+ __IO uint32_t _GPIO11; /**< padring pin Register, offset: 0x2C */
+ __IO uint32_t _GPIO12; /**< padring pin Register, offset: 0x30 */
+ __IO uint32_t _GPIO13; /**< padring pin Register, offset: 0x34 */
+ __IO uint32_t _GPIO14; /**< padring pin Register, offset: 0x38 */
+ __IO uint32_t _GPIO15; /**< padring pin Register, offset: 0x3C */
+ __IO uint32_t _GPIO16; /**< padring pin Register, offset: 0x40 */
+ __IO uint32_t _GPIO17; /**< padring pin Register, offset: 0x44 */
+ __IO uint32_t _GPIO18; /**< padring pin Register, offset: 0x48 */
+ __IO uint32_t _GPIO19; /**< padring pin Register, offset: 0x4C */
+ __IO uint32_t _GPIO20; /**< padring pin Register, offset: 0x50 */
+ __IO uint32_t _GPIO21; /**< padring pin Register, offset: 0x54 */
+ __IO uint32_t _GPIO22; /**< padring pin Register, offset: 0x58 */
+ __IO uint32_t _GPIO23; /**< padring pin Register, offset: 0x5C */
+ __IO uint32_t _GPIO24; /**< padring pin Register, offset: 0x60 */
+ __IO uint32_t _GPIO25; /**< padring pin Register, offset: 0x64 */
+ __IO uint32_t _GPIO26; /**< padring pin Register, offset: 0x68 */
+ __IO uint32_t _GPIO27; /**< padring pin Register, offset: 0x6C */
+ __IO uint32_t _GPIO28; /**< padring pin Register, offset: 0x70 */
+ __IO uint32_t _GPIO29; /**< padring pin Register, offset: 0x74 */
+ __IO uint32_t _GPIO30; /**< padring pin Register, offset: 0x78 */
+ __IO uint32_t _GPIO31; /**< padring pin Register, offset: 0x7C */
+ __IO uint32_t _GPIO32; /**< padring pin Register, offset: 0x80 */
+ __IO uint32_t _GPIO33; /**< padring pin Register, offset: 0x84 */
+ __IO uint32_t _GPIO34; /**< padring pin Register, offset: 0x88 */
+ __IO uint32_t _GPIO35; /**< padring pin Register, offset: 0x8C */
+ __IO uint32_t _GPIO36; /**< padring pin Register, offset: 0x90 */
+ __IO uint32_t _GPIO37; /**< padring pin Register, offset: 0x94 */
+ __IO uint32_t _GPIO38; /**< padring pin Register, offset: 0x98 */
+ __IO uint32_t _GPIO39; /**< padring pin Register, offset: 0x9C */
+ __IO uint32_t _GPIO40; /**< padring pin Register, offset: 0xA0 */
+ __IO uint32_t _GPIO41; /**< padring pin Register, offset: 0xA4 */
+ __IO uint32_t _GPIO42; /**< padring pin Register, offset: 0xA8 */
+ __IO uint32_t _GPIO43; /**< padring pin Register, offset: 0xAC */
+ __IO uint32_t _GPIO44; /**< padring pin Register, offset: 0xB0 */
+ __IO uint32_t _GPIO45; /**< padring pin Register, offset: 0xB4 */
+ __IO uint32_t _GPIO46; /**< padring pin Register, offset: 0xB8 */
+ __IO uint32_t _GPIO47; /**< padring pin Register, offset: 0xBC */
+ __IO uint32_t _GPIO48; /**< padring pin Register, offset: 0xC0 */
+ __IO uint32_t _GPIO49; /**< padring pin Register, offset: 0xC4 */
+ __IO uint32_t _GPIO50; /**< padring pin Register, offset: 0xC8 */
+ __IO uint32_t _GPIO51; /**< padring pin Register, offset: 0xCC */
+ __IO uint32_t _GPIO52; /**< padring pin Register, offset: 0xD0 */
+ __IO uint32_t _GPIO53; /**< padring pin Register, offset: 0xD4 */
+ __IO uint32_t _GPIO54; /**< padring pin Register, offset: 0xD8 */
+ __IO uint32_t _GPIO55; /**< padring pin Register, offset: 0xDC */
+} PINMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PINMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINMUX_Register_Masks PINMUX Register Masks
+ * @{
+ */
+
+/*! @name _GPIO0 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO0_FSEL_MASK (0x7U)
+#define PINMUX__GPIO0_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO0_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO0_FSEL_SHIFT)) & PINMUX__GPIO0_FSEL_MASK)
+#define PINMUX__GPIO0_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO0_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO0_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO0_DI_EN_SHIFT)) & PINMUX__GPIO0_DI_EN_MASK)
+#define PINMUX__GPIO0_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO0_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO0_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO0_SLP_VAL_SHIFT)) & PINMUX__GPIO0_SLP_VAL_MASK)
+#define PINMUX__GPIO0_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO0_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO0_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO0_SLP_OE_SHIFT)) & PINMUX__GPIO0_SLP_OE_MASK)
+#define PINMUX__GPIO0_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO0_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO0_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO0_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO0_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO0_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO0_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO0_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO0_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO0_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO0_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO0_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO0_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO0_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO0_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO1 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO1_FSEL_MASK (0x7U)
+#define PINMUX__GPIO1_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO1_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO1_FSEL_SHIFT)) & PINMUX__GPIO1_FSEL_MASK)
+#define PINMUX__GPIO1_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO1_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO1_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO1_DI_EN_SHIFT)) & PINMUX__GPIO1_DI_EN_MASK)
+#define PINMUX__GPIO1_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO1_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO1_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO1_SLP_VAL_SHIFT)) & PINMUX__GPIO1_SLP_VAL_MASK)
+#define PINMUX__GPIO1_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO1_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO1_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO1_SLP_OE_SHIFT)) & PINMUX__GPIO1_SLP_OE_MASK)
+#define PINMUX__GPIO1_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO1_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO1_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO1_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO1_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO1_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO1_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO1_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO1_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO1_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO1_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO1_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO1_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO1_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO1_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO2 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO2_FSEL_MASK (0x7U)
+#define PINMUX__GPIO2_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO2_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO2_FSEL_SHIFT)) & PINMUX__GPIO2_FSEL_MASK)
+#define PINMUX__GPIO2_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO2_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO2_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO2_DI_EN_SHIFT)) & PINMUX__GPIO2_DI_EN_MASK)
+#define PINMUX__GPIO2_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO2_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO2_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO2_SLP_VAL_SHIFT)) & PINMUX__GPIO2_SLP_VAL_MASK)
+#define PINMUX__GPIO2_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO2_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO2_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO2_SLP_OE_SHIFT)) & PINMUX__GPIO2_SLP_OE_MASK)
+#define PINMUX__GPIO2_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO2_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO2_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO2_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO2_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO2_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO2_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO2_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO2_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO2_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO2_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO2_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO2_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO2_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO2_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO3 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO3_FSEL_MASK (0x7U)
+#define PINMUX__GPIO3_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO3_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO3_FSEL_SHIFT)) & PINMUX__GPIO3_FSEL_MASK)
+#define PINMUX__GPIO3_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO3_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO3_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO3_DI_EN_SHIFT)) & PINMUX__GPIO3_DI_EN_MASK)
+#define PINMUX__GPIO3_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO3_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO3_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO3_SLP_VAL_SHIFT)) & PINMUX__GPIO3_SLP_VAL_MASK)
+#define PINMUX__GPIO3_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO3_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO3_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO3_SLP_OE_SHIFT)) & PINMUX__GPIO3_SLP_OE_MASK)
+#define PINMUX__GPIO3_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO3_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO3_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO3_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO3_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO3_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO3_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO3_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO3_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO3_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO3_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO3_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO3_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO3_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO3_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO4 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO4_FSEL_MASK (0x7U)
+#define PINMUX__GPIO4_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO4_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO4_FSEL_SHIFT)) & PINMUX__GPIO4_FSEL_MASK)
+#define PINMUX__GPIO4_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO4_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO4_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO4_DI_EN_SHIFT)) & PINMUX__GPIO4_DI_EN_MASK)
+#define PINMUX__GPIO4_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO4_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO4_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO4_SLP_VAL_SHIFT)) & PINMUX__GPIO4_SLP_VAL_MASK)
+#define PINMUX__GPIO4_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO4_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO4_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO4_SLP_OE_SHIFT)) & PINMUX__GPIO4_SLP_OE_MASK)
+#define PINMUX__GPIO4_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO4_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO4_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO4_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO4_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO4_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO4_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO4_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO4_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO4_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO4_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO4_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO4_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO4_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO4_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO5 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO5_FSEL_MASK (0x7U)
+#define PINMUX__GPIO5_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO5_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO5_FSEL_SHIFT)) & PINMUX__GPIO5_FSEL_MASK)
+#define PINMUX__GPIO5_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO5_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO5_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO5_DI_EN_SHIFT)) & PINMUX__GPIO5_DI_EN_MASK)
+#define PINMUX__GPIO5_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO5_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO5_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO5_SLP_VAL_SHIFT)) & PINMUX__GPIO5_SLP_VAL_MASK)
+#define PINMUX__GPIO5_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO5_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO5_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO5_SLP_OE_SHIFT)) & PINMUX__GPIO5_SLP_OE_MASK)
+#define PINMUX__GPIO5_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO5_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO5_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO5_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO5_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO5_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO5_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO5_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO5_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO5_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO5_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO5_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO5_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO5_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO5_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO6 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO6_FSEL_MASK (0x7U)
+#define PINMUX__GPIO6_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO6_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO6_FSEL_SHIFT)) & PINMUX__GPIO6_FSEL_MASK)
+#define PINMUX__GPIO6_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO6_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO6_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO6_DI_EN_SHIFT)) & PINMUX__GPIO6_DI_EN_MASK)
+#define PINMUX__GPIO6_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO6_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO6_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO6_SLP_VAL_SHIFT)) & PINMUX__GPIO6_SLP_VAL_MASK)
+#define PINMUX__GPIO6_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO6_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO6_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO6_SLP_OE_SHIFT)) & PINMUX__GPIO6_SLP_OE_MASK)
+#define PINMUX__GPIO6_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO6_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO6_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO6_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO6_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO6_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO6_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO6_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO6_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO6_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO6_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO6_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO6_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO6_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO6_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO7 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO7_FSEL_MASK (0x7U)
+#define PINMUX__GPIO7_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO7_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO7_FSEL_SHIFT)) & PINMUX__GPIO7_FSEL_MASK)
+#define PINMUX__GPIO7_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO7_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO7_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO7_DI_EN_SHIFT)) & PINMUX__GPIO7_DI_EN_MASK)
+#define PINMUX__GPIO7_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO7_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO7_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO7_SLP_VAL_SHIFT)) & PINMUX__GPIO7_SLP_VAL_MASK)
+#define PINMUX__GPIO7_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO7_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO7_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO7_SLP_OE_SHIFT)) & PINMUX__GPIO7_SLP_OE_MASK)
+#define PINMUX__GPIO7_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO7_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO7_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO7_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO7_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO7_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO7_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO7_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO7_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO7_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO7_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO7_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO7_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO7_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO7_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO8 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO8_FSEL_MASK (0x7U)
+#define PINMUX__GPIO8_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO8_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO8_FSEL_SHIFT)) & PINMUX__GPIO8_FSEL_MASK)
+#define PINMUX__GPIO8_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO8_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO8_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO8_DI_EN_SHIFT)) & PINMUX__GPIO8_DI_EN_MASK)
+#define PINMUX__GPIO8_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO8_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO8_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO8_SLP_VAL_SHIFT)) & PINMUX__GPIO8_SLP_VAL_MASK)
+#define PINMUX__GPIO8_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO8_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO8_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO8_SLP_OE_SHIFT)) & PINMUX__GPIO8_SLP_OE_MASK)
+#define PINMUX__GPIO8_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO8_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO8_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO8_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO8_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO8_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO8_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO8_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO8_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO8_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO8_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO8_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO8_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO8_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO8_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO9 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO9_FSEL_MASK (0x7U)
+#define PINMUX__GPIO9_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO9_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO9_FSEL_SHIFT)) & PINMUX__GPIO9_FSEL_MASK)
+#define PINMUX__GPIO9_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO9_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO9_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO9_DI_EN_SHIFT)) & PINMUX__GPIO9_DI_EN_MASK)
+#define PINMUX__GPIO9_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO9_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO9_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO9_SLP_VAL_SHIFT)) & PINMUX__GPIO9_SLP_VAL_MASK)
+#define PINMUX__GPIO9_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO9_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO9_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO9_SLP_OE_SHIFT)) & PINMUX__GPIO9_SLP_OE_MASK)
+#define PINMUX__GPIO9_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO9_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO9_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO9_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO9_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO9_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO9_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO9_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO9_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO9_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO9_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO9_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO9_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO9_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO9_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO10 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO10_FSEL_MASK (0x7U)
+#define PINMUX__GPIO10_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO10_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO10_FSEL_SHIFT)) & PINMUX__GPIO10_FSEL_MASK)
+#define PINMUX__GPIO10_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO10_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO10_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO10_DI_EN_SHIFT)) & PINMUX__GPIO10_DI_EN_MASK)
+#define PINMUX__GPIO10_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO10_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO10_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO10_SLP_VAL_SHIFT)) & PINMUX__GPIO10_SLP_VAL_MASK)
+#define PINMUX__GPIO10_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO10_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO10_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO10_SLP_OE_SHIFT)) & PINMUX__GPIO10_SLP_OE_MASK)
+#define PINMUX__GPIO10_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO10_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO10_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO10_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO10_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO10_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO10_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO10_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO10_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO10_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO10_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO10_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO10_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO10_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO10_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO11 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO11_FSEL_MASK (0x7U)
+#define PINMUX__GPIO11_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO11_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO11_FSEL_SHIFT)) & PINMUX__GPIO11_FSEL_MASK)
+#define PINMUX__GPIO11_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO11_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO11_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO11_DI_EN_SHIFT)) & PINMUX__GPIO11_DI_EN_MASK)
+#define PINMUX__GPIO11_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO11_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO11_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO11_SLP_VAL_SHIFT)) & PINMUX__GPIO11_SLP_VAL_MASK)
+#define PINMUX__GPIO11_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO11_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO11_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO11_SLP_OE_SHIFT)) & PINMUX__GPIO11_SLP_OE_MASK)
+#define PINMUX__GPIO11_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO11_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO11_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO11_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO11_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO11_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO11_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO11_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO11_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO11_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO11_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO11_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO11_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO11_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO11_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO12 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO12_FSEL_MASK (0x7U)
+#define PINMUX__GPIO12_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO12_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO12_FSEL_SHIFT)) & PINMUX__GPIO12_FSEL_MASK)
+#define PINMUX__GPIO12_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO12_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO12_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO12_DI_EN_SHIFT)) & PINMUX__GPIO12_DI_EN_MASK)
+#define PINMUX__GPIO12_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO12_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO12_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO12_SLP_VAL_SHIFT)) & PINMUX__GPIO12_SLP_VAL_MASK)
+#define PINMUX__GPIO12_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO12_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO12_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO12_SLP_OE_SHIFT)) & PINMUX__GPIO12_SLP_OE_MASK)
+#define PINMUX__GPIO12_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO12_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO12_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO12_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO12_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO12_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO12_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO12_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO12_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO12_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO12_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO12_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO12_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO12_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO12_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO13 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO13_FSEL_MASK (0x7U)
+#define PINMUX__GPIO13_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO13_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO13_FSEL_SHIFT)) & PINMUX__GPIO13_FSEL_MASK)
+#define PINMUX__GPIO13_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO13_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO13_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO13_DI_EN_SHIFT)) & PINMUX__GPIO13_DI_EN_MASK)
+#define PINMUX__GPIO13_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO13_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO13_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO13_SLP_VAL_SHIFT)) & PINMUX__GPIO13_SLP_VAL_MASK)
+#define PINMUX__GPIO13_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO13_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO13_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO13_SLP_OE_SHIFT)) & PINMUX__GPIO13_SLP_OE_MASK)
+#define PINMUX__GPIO13_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO13_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO13_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO13_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO13_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO13_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO13_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO13_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO13_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO13_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO13_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO13_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO13_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO13_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO13_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO14 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO14_FSEL_MASK (0x7U)
+#define PINMUX__GPIO14_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO14_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO14_FSEL_SHIFT)) & PINMUX__GPIO14_FSEL_MASK)
+#define PINMUX__GPIO14_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO14_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO14_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO14_DI_EN_SHIFT)) & PINMUX__GPIO14_DI_EN_MASK)
+#define PINMUX__GPIO14_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO14_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO14_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO14_SLP_VAL_SHIFT)) & PINMUX__GPIO14_SLP_VAL_MASK)
+#define PINMUX__GPIO14_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO14_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO14_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO14_SLP_OE_SHIFT)) & PINMUX__GPIO14_SLP_OE_MASK)
+#define PINMUX__GPIO14_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO14_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO14_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO14_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO14_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO14_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO14_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO14_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO14_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO14_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO14_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO14_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO14_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO14_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO14_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO15 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO15_FSEL_MASK (0x7U)
+#define PINMUX__GPIO15_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO15_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO15_FSEL_SHIFT)) & PINMUX__GPIO15_FSEL_MASK)
+#define PINMUX__GPIO15_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO15_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO15_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO15_DI_EN_SHIFT)) & PINMUX__GPIO15_DI_EN_MASK)
+#define PINMUX__GPIO15_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO15_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO15_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO15_SLP_VAL_SHIFT)) & PINMUX__GPIO15_SLP_VAL_MASK)
+#define PINMUX__GPIO15_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO15_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO15_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO15_SLP_OE_SHIFT)) & PINMUX__GPIO15_SLP_OE_MASK)
+#define PINMUX__GPIO15_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO15_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO15_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO15_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO15_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO15_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO15_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO15_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO15_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO15_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO15_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO15_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO15_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO15_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO15_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO16 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO16_FSEL_MASK (0x7U)
+#define PINMUX__GPIO16_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO16_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO16_FSEL_SHIFT)) & PINMUX__GPIO16_FSEL_MASK)
+#define PINMUX__GPIO16_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO16_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO16_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO16_DI_EN_SHIFT)) & PINMUX__GPIO16_DI_EN_MASK)
+#define PINMUX__GPIO16_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO16_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO16_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO16_SLP_VAL_SHIFT)) & PINMUX__GPIO16_SLP_VAL_MASK)
+#define PINMUX__GPIO16_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO16_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO16_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO16_SLP_OE_SHIFT)) & PINMUX__GPIO16_SLP_OE_MASK)
+#define PINMUX__GPIO16_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO16_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO16_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO16_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO16_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO16_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO16_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO16_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO16_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO16_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO16_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO16_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO16_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO16_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO16_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO17 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO17_FSEL_MASK (0x7U)
+#define PINMUX__GPIO17_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO17_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO17_FSEL_SHIFT)) & PINMUX__GPIO17_FSEL_MASK)
+#define PINMUX__GPIO17_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO17_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO17_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO17_DI_EN_SHIFT)) & PINMUX__GPIO17_DI_EN_MASK)
+#define PINMUX__GPIO17_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO17_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO17_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO17_SLP_VAL_SHIFT)) & PINMUX__GPIO17_SLP_VAL_MASK)
+#define PINMUX__GPIO17_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO17_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO17_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO17_SLP_OE_SHIFT)) & PINMUX__GPIO17_SLP_OE_MASK)
+#define PINMUX__GPIO17_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO17_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO17_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO17_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO17_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO17_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO17_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO17_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO17_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO17_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO17_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO17_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO17_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO17_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO17_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO18 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO18_FSEL_MASK (0x7U)
+#define PINMUX__GPIO18_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO18_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO18_FSEL_SHIFT)) & PINMUX__GPIO18_FSEL_MASK)
+#define PINMUX__GPIO18_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO18_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO18_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO18_DI_EN_SHIFT)) & PINMUX__GPIO18_DI_EN_MASK)
+#define PINMUX__GPIO18_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO18_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO18_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO18_SLP_VAL_SHIFT)) & PINMUX__GPIO18_SLP_VAL_MASK)
+#define PINMUX__GPIO18_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO18_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO18_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO18_SLP_OE_SHIFT)) & PINMUX__GPIO18_SLP_OE_MASK)
+#define PINMUX__GPIO18_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO18_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO18_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO18_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO18_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO18_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO18_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO18_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO18_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO18_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO18_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO18_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO18_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO18_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO18_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO19 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO19_FSEL_MASK (0x7U)
+#define PINMUX__GPIO19_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO19_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO19_FSEL_SHIFT)) & PINMUX__GPIO19_FSEL_MASK)
+#define PINMUX__GPIO19_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO19_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO19_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO19_DI_EN_SHIFT)) & PINMUX__GPIO19_DI_EN_MASK)
+#define PINMUX__GPIO19_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO19_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO19_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO19_SLP_VAL_SHIFT)) & PINMUX__GPIO19_SLP_VAL_MASK)
+#define PINMUX__GPIO19_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO19_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO19_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO19_SLP_OE_SHIFT)) & PINMUX__GPIO19_SLP_OE_MASK)
+#define PINMUX__GPIO19_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO19_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO19_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO19_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO19_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO19_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO19_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO19_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO19_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO19_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO19_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO19_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO19_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO19_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO19_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO20 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO20_FSEL_MASK (0x7U)
+#define PINMUX__GPIO20_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO20_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO20_FSEL_SHIFT)) & PINMUX__GPIO20_FSEL_MASK)
+#define PINMUX__GPIO20_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO20_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO20_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO20_DI_EN_SHIFT)) & PINMUX__GPIO20_DI_EN_MASK)
+#define PINMUX__GPIO20_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO20_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO20_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO20_SLP_VAL_SHIFT)) & PINMUX__GPIO20_SLP_VAL_MASK)
+#define PINMUX__GPIO20_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO20_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO20_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO20_SLP_OE_SHIFT)) & PINMUX__GPIO20_SLP_OE_MASK)
+#define PINMUX__GPIO20_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO20_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO20_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO20_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO20_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO20_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO20_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO20_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO20_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO20_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO20_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO20_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO20_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO20_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO20_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO21 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO21_FSEL_MASK (0x7U)
+#define PINMUX__GPIO21_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO21_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO21_FSEL_SHIFT)) & PINMUX__GPIO21_FSEL_MASK)
+#define PINMUX__GPIO21_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO21_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO21_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO21_DI_EN_SHIFT)) & PINMUX__GPIO21_DI_EN_MASK)
+#define PINMUX__GPIO21_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO21_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO21_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO21_SLP_VAL_SHIFT)) & PINMUX__GPIO21_SLP_VAL_MASK)
+#define PINMUX__GPIO21_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO21_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO21_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO21_SLP_OE_SHIFT)) & PINMUX__GPIO21_SLP_OE_MASK)
+#define PINMUX__GPIO21_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO21_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO21_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO21_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO21_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO21_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO21_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO21_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO21_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO21_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO21_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO21_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO21_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO21_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO21_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO22 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO22_FSEL_MASK (0x7U)
+#define PINMUX__GPIO22_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO22_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO22_FSEL_SHIFT)) & PINMUX__GPIO22_FSEL_MASK)
+#define PINMUX__GPIO22_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO22_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO22_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO22_DI_EN_SHIFT)) & PINMUX__GPIO22_DI_EN_MASK)
+#define PINMUX__GPIO22_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO22_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO22_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO22_SLP_VAL_SHIFT)) & PINMUX__GPIO22_SLP_VAL_MASK)
+#define PINMUX__GPIO22_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO22_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO22_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO22_SLP_OE_SHIFT)) & PINMUX__GPIO22_SLP_OE_MASK)
+#define PINMUX__GPIO22_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO22_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO22_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO22_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO22_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO22_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO22_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO22_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO22_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO22_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO22_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO22_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO22_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO22_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO22_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO23 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO23_FSEL_MASK (0x7U)
+#define PINMUX__GPIO23_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO23_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO23_FSEL_SHIFT)) & PINMUX__GPIO23_FSEL_MASK)
+#define PINMUX__GPIO23_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO23_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO23_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO23_DI_EN_SHIFT)) & PINMUX__GPIO23_DI_EN_MASK)
+#define PINMUX__GPIO23_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO23_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO23_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO23_SLP_VAL_SHIFT)) & PINMUX__GPIO23_SLP_VAL_MASK)
+#define PINMUX__GPIO23_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO23_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO23_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO23_SLP_OE_SHIFT)) & PINMUX__GPIO23_SLP_OE_MASK)
+#define PINMUX__GPIO23_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO23_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO23_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO23_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO23_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO23_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO23_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO23_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO23_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO23_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO23_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO23_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO23_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO23_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO23_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO24 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO24_FSEL_MASK (0x7U)
+#define PINMUX__GPIO24_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO24_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO24_FSEL_SHIFT)) & PINMUX__GPIO24_FSEL_MASK)
+#define PINMUX__GPIO24_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO24_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO24_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO24_DI_EN_SHIFT)) & PINMUX__GPIO24_DI_EN_MASK)
+#define PINMUX__GPIO24_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO24_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO24_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO24_SLP_VAL_SHIFT)) & PINMUX__GPIO24_SLP_VAL_MASK)
+#define PINMUX__GPIO24_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO24_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO24_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO24_SLP_OE_SHIFT)) & PINMUX__GPIO24_SLP_OE_MASK)
+#define PINMUX__GPIO24_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO24_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO24_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO24_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO24_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO24_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO24_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO24_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO24_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO24_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO24_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO24_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO24_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO24_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO24_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO25 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO25_FSEL_MASK (0x7U)
+#define PINMUX__GPIO25_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO25_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO25_FSEL_SHIFT)) & PINMUX__GPIO25_FSEL_MASK)
+#define PINMUX__GPIO25_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO25_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO25_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO25_DI_EN_SHIFT)) & PINMUX__GPIO25_DI_EN_MASK)
+#define PINMUX__GPIO25_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO25_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO25_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO25_SLP_VAL_SHIFT)) & PINMUX__GPIO25_SLP_VAL_MASK)
+#define PINMUX__GPIO25_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO25_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO25_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO25_SLP_OE_SHIFT)) & PINMUX__GPIO25_SLP_OE_MASK)
+#define PINMUX__GPIO25_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO25_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO25_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO25_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO25_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO25_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO25_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO25_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO25_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO25_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO25_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO25_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO25_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO25_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO25_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO26 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO26_FSEL_MASK (0x7U)
+#define PINMUX__GPIO26_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO26_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO26_FSEL_SHIFT)) & PINMUX__GPIO26_FSEL_MASK)
+#define PINMUX__GPIO26_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO26_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO26_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO26_DI_EN_SHIFT)) & PINMUX__GPIO26_DI_EN_MASK)
+#define PINMUX__GPIO26_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO26_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO26_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO26_SLP_VAL_SHIFT)) & PINMUX__GPIO26_SLP_VAL_MASK)
+#define PINMUX__GPIO26_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO26_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO26_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO26_SLP_OE_SHIFT)) & PINMUX__GPIO26_SLP_OE_MASK)
+#define PINMUX__GPIO26_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO26_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO26_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO26_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO26_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO26_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO26_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO26_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO26_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO26_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO26_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO26_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO26_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO26_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO26_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO27 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO27_FSEL_MASK (0x7U)
+#define PINMUX__GPIO27_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO27_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO27_FSEL_SHIFT)) & PINMUX__GPIO27_FSEL_MASK)
+#define PINMUX__GPIO27_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO27_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO27_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO27_DI_EN_SHIFT)) & PINMUX__GPIO27_DI_EN_MASK)
+#define PINMUX__GPIO27_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO27_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO27_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO27_SLP_VAL_SHIFT)) & PINMUX__GPIO27_SLP_VAL_MASK)
+#define PINMUX__GPIO27_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO27_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO27_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO27_SLP_OE_SHIFT)) & PINMUX__GPIO27_SLP_OE_MASK)
+#define PINMUX__GPIO27_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO27_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO27_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO27_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO27_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO27_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO27_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO27_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO27_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO27_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO27_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO27_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO27_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO27_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO27_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO28 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO28_FSEL_MASK (0x7U)
+#define PINMUX__GPIO28_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO28_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO28_FSEL_SHIFT)) & PINMUX__GPIO28_FSEL_MASK)
+#define PINMUX__GPIO28_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO28_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO28_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO28_DI_EN_SHIFT)) & PINMUX__GPIO28_DI_EN_MASK)
+#define PINMUX__GPIO28_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO28_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO28_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO28_SLP_VAL_SHIFT)) & PINMUX__GPIO28_SLP_VAL_MASK)
+#define PINMUX__GPIO28_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO28_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO28_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO28_SLP_OE_SHIFT)) & PINMUX__GPIO28_SLP_OE_MASK)
+#define PINMUX__GPIO28_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO28_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO28_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO28_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO28_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO28_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO28_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO28_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO28_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO28_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO28_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO28_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO28_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO28_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO28_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO29 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO29_FSEL_MASK (0x7U)
+#define PINMUX__GPIO29_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO29_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO29_FSEL_SHIFT)) & PINMUX__GPIO29_FSEL_MASK)
+#define PINMUX__GPIO29_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO29_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO29_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO29_DI_EN_SHIFT)) & PINMUX__GPIO29_DI_EN_MASK)
+#define PINMUX__GPIO29_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO29_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO29_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO29_SLP_VAL_SHIFT)) & PINMUX__GPIO29_SLP_VAL_MASK)
+#define PINMUX__GPIO29_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO29_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO29_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO29_SLP_OE_SHIFT)) & PINMUX__GPIO29_SLP_OE_MASK)
+#define PINMUX__GPIO29_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO29_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO29_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO29_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO29_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO29_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO29_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO29_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO29_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO29_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO29_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO29_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO29_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO29_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO29_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO30 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO30_FSEL_MASK (0x7U)
+#define PINMUX__GPIO30_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO30_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO30_FSEL_SHIFT)) & PINMUX__GPIO30_FSEL_MASK)
+#define PINMUX__GPIO30_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO30_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO30_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO30_DI_EN_SHIFT)) & PINMUX__GPIO30_DI_EN_MASK)
+#define PINMUX__GPIO30_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO30_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO30_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO30_SLP_VAL_SHIFT)) & PINMUX__GPIO30_SLP_VAL_MASK)
+#define PINMUX__GPIO30_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO30_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO30_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO30_SLP_OE_SHIFT)) & PINMUX__GPIO30_SLP_OE_MASK)
+#define PINMUX__GPIO30_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO30_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO30_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO30_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO30_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO30_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO30_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO30_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO30_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO30_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO30_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO30_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO30_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO30_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO30_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO31 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO31_FSEL_MASK (0x7U)
+#define PINMUX__GPIO31_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO31_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO31_FSEL_SHIFT)) & PINMUX__GPIO31_FSEL_MASK)
+#define PINMUX__GPIO31_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO31_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO31_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO31_DI_EN_SHIFT)) & PINMUX__GPIO31_DI_EN_MASK)
+#define PINMUX__GPIO31_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO31_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO31_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO31_SLP_VAL_SHIFT)) & PINMUX__GPIO31_SLP_VAL_MASK)
+#define PINMUX__GPIO31_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO31_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO31_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO31_SLP_OE_SHIFT)) & PINMUX__GPIO31_SLP_OE_MASK)
+#define PINMUX__GPIO31_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO31_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO31_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO31_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO31_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO31_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO31_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO31_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO31_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO31_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO31_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO31_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO31_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO31_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO31_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO32 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO32_FSEL_MASK (0x7U)
+#define PINMUX__GPIO32_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO32_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO32_FSEL_SHIFT)) & PINMUX__GPIO32_FSEL_MASK)
+#define PINMUX__GPIO32_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO32_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO32_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO32_DI_EN_SHIFT)) & PINMUX__GPIO32_DI_EN_MASK)
+#define PINMUX__GPIO32_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO32_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO32_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO32_SLP_VAL_SHIFT)) & PINMUX__GPIO32_SLP_VAL_MASK)
+#define PINMUX__GPIO32_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO32_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO32_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO32_SLP_OE_SHIFT)) & PINMUX__GPIO32_SLP_OE_MASK)
+#define PINMUX__GPIO32_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO32_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO32_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO32_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO32_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO32_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO32_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO32_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO32_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO32_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO32_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO32_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO32_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO32_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO32_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO33 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO33_FSEL_MASK (0x7U)
+#define PINMUX__GPIO33_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO33_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO33_FSEL_SHIFT)) & PINMUX__GPIO33_FSEL_MASK)
+#define PINMUX__GPIO33_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO33_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO33_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO33_DI_EN_SHIFT)) & PINMUX__GPIO33_DI_EN_MASK)
+#define PINMUX__GPIO33_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO33_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO33_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO33_SLP_VAL_SHIFT)) & PINMUX__GPIO33_SLP_VAL_MASK)
+#define PINMUX__GPIO33_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO33_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO33_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO33_SLP_OE_SHIFT)) & PINMUX__GPIO33_SLP_OE_MASK)
+#define PINMUX__GPIO33_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO33_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO33_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO33_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO33_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO33_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO33_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO33_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO33_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO33_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO33_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO33_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO33_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO33_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO33_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO34 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO34_FSEL_MASK (0x7U)
+#define PINMUX__GPIO34_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO34_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO34_FSEL_SHIFT)) & PINMUX__GPIO34_FSEL_MASK)
+#define PINMUX__GPIO34_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO34_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO34_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO34_DI_EN_SHIFT)) & PINMUX__GPIO34_DI_EN_MASK)
+#define PINMUX__GPIO34_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO34_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO34_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO34_SLP_VAL_SHIFT)) & PINMUX__GPIO34_SLP_VAL_MASK)
+#define PINMUX__GPIO34_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO34_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO34_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO34_SLP_OE_SHIFT)) & PINMUX__GPIO34_SLP_OE_MASK)
+#define PINMUX__GPIO34_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO34_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO34_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO34_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO34_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO34_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO34_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO34_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO34_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO34_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO34_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO34_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO34_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO34_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO34_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO35 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO35_FSEL_MASK (0x7U)
+#define PINMUX__GPIO35_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO35_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO35_FSEL_SHIFT)) & PINMUX__GPIO35_FSEL_MASK)
+#define PINMUX__GPIO35_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO35_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO35_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO35_DI_EN_SHIFT)) & PINMUX__GPIO35_DI_EN_MASK)
+#define PINMUX__GPIO35_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO35_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO35_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO35_SLP_VAL_SHIFT)) & PINMUX__GPIO35_SLP_VAL_MASK)
+#define PINMUX__GPIO35_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO35_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO35_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO35_SLP_OE_SHIFT)) & PINMUX__GPIO35_SLP_OE_MASK)
+#define PINMUX__GPIO35_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO35_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO35_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO35_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO35_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO35_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO35_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO35_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO35_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO35_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO35_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO35_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO35_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO35_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO35_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO36 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO36_FSEL_MASK (0x7U)
+#define PINMUX__GPIO36_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO36_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO36_FSEL_SHIFT)) & PINMUX__GPIO36_FSEL_MASK)
+#define PINMUX__GPIO36_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO36_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO36_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO36_DI_EN_SHIFT)) & PINMUX__GPIO36_DI_EN_MASK)
+#define PINMUX__GPIO36_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO36_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO36_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO36_SLP_VAL_SHIFT)) & PINMUX__GPIO36_SLP_VAL_MASK)
+#define PINMUX__GPIO36_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO36_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO36_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO36_SLP_OE_SHIFT)) & PINMUX__GPIO36_SLP_OE_MASK)
+#define PINMUX__GPIO36_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO36_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO36_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO36_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO36_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO36_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO36_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO36_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO36_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO36_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO36_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO36_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO36_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO36_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO36_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO37 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO37_FSEL_MASK (0x7U)
+#define PINMUX__GPIO37_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO37_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO37_FSEL_SHIFT)) & PINMUX__GPIO37_FSEL_MASK)
+#define PINMUX__GPIO37_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO37_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO37_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO37_DI_EN_SHIFT)) & PINMUX__GPIO37_DI_EN_MASK)
+#define PINMUX__GPIO37_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO37_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO37_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO37_SLP_VAL_SHIFT)) & PINMUX__GPIO37_SLP_VAL_MASK)
+#define PINMUX__GPIO37_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO37_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO37_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO37_SLP_OE_SHIFT)) & PINMUX__GPIO37_SLP_OE_MASK)
+#define PINMUX__GPIO37_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO37_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO37_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO37_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO37_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO37_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO37_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO37_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO37_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO37_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO37_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO37_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO37_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO37_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO37_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO38 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO38_FSEL_MASK (0x7U)
+#define PINMUX__GPIO38_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO38_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO38_FSEL_SHIFT)) & PINMUX__GPIO38_FSEL_MASK)
+#define PINMUX__GPIO38_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO38_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO38_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO38_DI_EN_SHIFT)) & PINMUX__GPIO38_DI_EN_MASK)
+#define PINMUX__GPIO38_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO38_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO38_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO38_SLP_VAL_SHIFT)) & PINMUX__GPIO38_SLP_VAL_MASK)
+#define PINMUX__GPIO38_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO38_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO38_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO38_SLP_OE_SHIFT)) & PINMUX__GPIO38_SLP_OE_MASK)
+#define PINMUX__GPIO38_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO38_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO38_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO38_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO38_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO38_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO38_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO38_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO38_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO38_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO38_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO38_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO38_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO38_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO38_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO39 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO39_FSEL_MASK (0x7U)
+#define PINMUX__GPIO39_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO39_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO39_FSEL_SHIFT)) & PINMUX__GPIO39_FSEL_MASK)
+#define PINMUX__GPIO39_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO39_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO39_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO39_DI_EN_SHIFT)) & PINMUX__GPIO39_DI_EN_MASK)
+#define PINMUX__GPIO39_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO39_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO39_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO39_SLP_VAL_SHIFT)) & PINMUX__GPIO39_SLP_VAL_MASK)
+#define PINMUX__GPIO39_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO39_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO39_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO39_SLP_OE_SHIFT)) & PINMUX__GPIO39_SLP_OE_MASK)
+#define PINMUX__GPIO39_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO39_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO39_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO39_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO39_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO39_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO39_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO39_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO39_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO39_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO39_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO39_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO39_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO39_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO39_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO40 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO40_FSEL_MASK (0x7U)
+#define PINMUX__GPIO40_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO40_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO40_FSEL_SHIFT)) & PINMUX__GPIO40_FSEL_MASK)
+#define PINMUX__GPIO40_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO40_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO40_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO40_DI_EN_SHIFT)) & PINMUX__GPIO40_DI_EN_MASK)
+#define PINMUX__GPIO40_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO40_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO40_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO40_SLP_VAL_SHIFT)) & PINMUX__GPIO40_SLP_VAL_MASK)
+#define PINMUX__GPIO40_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO40_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO40_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO40_SLP_OE_SHIFT)) & PINMUX__GPIO40_SLP_OE_MASK)
+#define PINMUX__GPIO40_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO40_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO40_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO40_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO40_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO40_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO40_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO40_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO40_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO40_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO40_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO40_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO40_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO40_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO40_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO41 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO41_FSEL_MASK (0x7U)
+#define PINMUX__GPIO41_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO41_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO41_FSEL_SHIFT)) & PINMUX__GPIO41_FSEL_MASK)
+#define PINMUX__GPIO41_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO41_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO41_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO41_DI_EN_SHIFT)) & PINMUX__GPIO41_DI_EN_MASK)
+#define PINMUX__GPIO41_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO41_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO41_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO41_SLP_VAL_SHIFT)) & PINMUX__GPIO41_SLP_VAL_MASK)
+#define PINMUX__GPIO41_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO41_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO41_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO41_SLP_OE_SHIFT)) & PINMUX__GPIO41_SLP_OE_MASK)
+#define PINMUX__GPIO41_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO41_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO41_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO41_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO41_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO41_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO41_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO41_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO41_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO41_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO41_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO41_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO41_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO41_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO41_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO42 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO42_FSEL_MASK (0x7U)
+#define PINMUX__GPIO42_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO42_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO42_FSEL_SHIFT)) & PINMUX__GPIO42_FSEL_MASK)
+#define PINMUX__GPIO42_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO42_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO42_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO42_DI_EN_SHIFT)) & PINMUX__GPIO42_DI_EN_MASK)
+#define PINMUX__GPIO42_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO42_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO42_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO42_SLP_VAL_SHIFT)) & PINMUX__GPIO42_SLP_VAL_MASK)
+#define PINMUX__GPIO42_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO42_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO42_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO42_SLP_OE_SHIFT)) & PINMUX__GPIO42_SLP_OE_MASK)
+#define PINMUX__GPIO42_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO42_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO42_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO42_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO42_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO42_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO42_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO42_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO42_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO42_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO42_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO42_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO42_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO42_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO42_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO43 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO43_FSEL_MASK (0x7U)
+#define PINMUX__GPIO43_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO43_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO43_FSEL_SHIFT)) & PINMUX__GPIO43_FSEL_MASK)
+#define PINMUX__GPIO43_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO43_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO43_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO43_DI_EN_SHIFT)) & PINMUX__GPIO43_DI_EN_MASK)
+#define PINMUX__GPIO43_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO43_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO43_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO43_SLP_VAL_SHIFT)) & PINMUX__GPIO43_SLP_VAL_MASK)
+#define PINMUX__GPIO43_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO43_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO43_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO43_SLP_OE_SHIFT)) & PINMUX__GPIO43_SLP_OE_MASK)
+#define PINMUX__GPIO43_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO43_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO43_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO43_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO43_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO43_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO43_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO43_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO43_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO43_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO43_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO43_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO43_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO43_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO43_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO44 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO44_FSEL_MASK (0x7U)
+#define PINMUX__GPIO44_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO44_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO44_FSEL_SHIFT)) & PINMUX__GPIO44_FSEL_MASK)
+#define PINMUX__GPIO44_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO44_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO44_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO44_DI_EN_SHIFT)) & PINMUX__GPIO44_DI_EN_MASK)
+#define PINMUX__GPIO44_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO44_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO44_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO44_SLP_VAL_SHIFT)) & PINMUX__GPIO44_SLP_VAL_MASK)
+#define PINMUX__GPIO44_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO44_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO44_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO44_SLP_OE_SHIFT)) & PINMUX__GPIO44_SLP_OE_MASK)
+#define PINMUX__GPIO44_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO44_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO44_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO44_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO44_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO44_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO44_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO44_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO44_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO44_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO44_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO44_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO44_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO44_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO44_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO45 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO45_FSEL_MASK (0x7U)
+#define PINMUX__GPIO45_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO45_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO45_FSEL_SHIFT)) & PINMUX__GPIO45_FSEL_MASK)
+#define PINMUX__GPIO45_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO45_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO45_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO45_DI_EN_SHIFT)) & PINMUX__GPIO45_DI_EN_MASK)
+#define PINMUX__GPIO45_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO45_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO45_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO45_SLP_VAL_SHIFT)) & PINMUX__GPIO45_SLP_VAL_MASK)
+#define PINMUX__GPIO45_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO45_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO45_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO45_SLP_OE_SHIFT)) & PINMUX__GPIO45_SLP_OE_MASK)
+#define PINMUX__GPIO45_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO45_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO45_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO45_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO45_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO45_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO45_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO45_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO45_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO45_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO45_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO45_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO45_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO45_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO45_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO46 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO46_FSEL_MASK (0x7U)
+#define PINMUX__GPIO46_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO46_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO46_FSEL_SHIFT)) & PINMUX__GPIO46_FSEL_MASK)
+#define PINMUX__GPIO46_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO46_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO46_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO46_DI_EN_SHIFT)) & PINMUX__GPIO46_DI_EN_MASK)
+#define PINMUX__GPIO46_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO46_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO46_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO46_SLP_VAL_SHIFT)) & PINMUX__GPIO46_SLP_VAL_MASK)
+#define PINMUX__GPIO46_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO46_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO46_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO46_SLP_OE_SHIFT)) & PINMUX__GPIO46_SLP_OE_MASK)
+#define PINMUX__GPIO46_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO46_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO46_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO46_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO46_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO46_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO46_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO46_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO46_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO46_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO46_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO46_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO46_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO46_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO46_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO47 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO47_FSEL_MASK (0x7U)
+#define PINMUX__GPIO47_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO47_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO47_FSEL_SHIFT)) & PINMUX__GPIO47_FSEL_MASK)
+#define PINMUX__GPIO47_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO47_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO47_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO47_DI_EN_SHIFT)) & PINMUX__GPIO47_DI_EN_MASK)
+#define PINMUX__GPIO47_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO47_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO47_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO47_SLP_VAL_SHIFT)) & PINMUX__GPIO47_SLP_VAL_MASK)
+#define PINMUX__GPIO47_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO47_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO47_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO47_SLP_OE_SHIFT)) & PINMUX__GPIO47_SLP_OE_MASK)
+#define PINMUX__GPIO47_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO47_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO47_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO47_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO47_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO47_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO47_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO47_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO47_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO47_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO47_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO47_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO47_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO47_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO47_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO48 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO48_FSEL_MASK (0x7U)
+#define PINMUX__GPIO48_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO48_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO48_FSEL_SHIFT)) & PINMUX__GPIO48_FSEL_MASK)
+#define PINMUX__GPIO48_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO48_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO48_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO48_DI_EN_SHIFT)) & PINMUX__GPIO48_DI_EN_MASK)
+#define PINMUX__GPIO48_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO48_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO48_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO48_SLP_VAL_SHIFT)) & PINMUX__GPIO48_SLP_VAL_MASK)
+#define PINMUX__GPIO48_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO48_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO48_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO48_SLP_OE_SHIFT)) & PINMUX__GPIO48_SLP_OE_MASK)
+#define PINMUX__GPIO48_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO48_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO48_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO48_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO48_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO48_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO48_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO48_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO48_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO48_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO48_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO48_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO48_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO48_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO48_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO49 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO49_FSEL_MASK (0x7U)
+#define PINMUX__GPIO49_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO49_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO49_FSEL_SHIFT)) & PINMUX__GPIO49_FSEL_MASK)
+#define PINMUX__GPIO49_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO49_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO49_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO49_DI_EN_SHIFT)) & PINMUX__GPIO49_DI_EN_MASK)
+#define PINMUX__GPIO49_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO49_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO49_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO49_SLP_VAL_SHIFT)) & PINMUX__GPIO49_SLP_VAL_MASK)
+#define PINMUX__GPIO49_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO49_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO49_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO49_SLP_OE_SHIFT)) & PINMUX__GPIO49_SLP_OE_MASK)
+#define PINMUX__GPIO49_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO49_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO49_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO49_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO49_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO49_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO49_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO49_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO49_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO49_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO49_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO49_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO49_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO49_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO49_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO50 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO50_FSEL_MASK (0x7U)
+#define PINMUX__GPIO50_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO50_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO50_FSEL_SHIFT)) & PINMUX__GPIO50_FSEL_MASK)
+#define PINMUX__GPIO50_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO50_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO50_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO50_DI_EN_SHIFT)) & PINMUX__GPIO50_DI_EN_MASK)
+#define PINMUX__GPIO50_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO50_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO50_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO50_SLP_VAL_SHIFT)) & PINMUX__GPIO50_SLP_VAL_MASK)
+#define PINMUX__GPIO50_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO50_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO50_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO50_SLP_OE_SHIFT)) & PINMUX__GPIO50_SLP_OE_MASK)
+#define PINMUX__GPIO50_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO50_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO50_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO50_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO50_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO50_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO50_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO50_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO50_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO50_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO50_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO50_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO50_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO50_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO50_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO51 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO51_FSEL_MASK (0x7U)
+#define PINMUX__GPIO51_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO51_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO51_FSEL_SHIFT)) & PINMUX__GPIO51_FSEL_MASK)
+#define PINMUX__GPIO51_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO51_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO51_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO51_DI_EN_SHIFT)) & PINMUX__GPIO51_DI_EN_MASK)
+#define PINMUX__GPIO51_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO51_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO51_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO51_SLP_VAL_SHIFT)) & PINMUX__GPIO51_SLP_VAL_MASK)
+#define PINMUX__GPIO51_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO51_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO51_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO51_SLP_OE_SHIFT)) & PINMUX__GPIO51_SLP_OE_MASK)
+#define PINMUX__GPIO51_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO51_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO51_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO51_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO51_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO51_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO51_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO51_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO51_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO51_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO51_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO51_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO51_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO51_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO51_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO52 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO52_FSEL_MASK (0x7U)
+#define PINMUX__GPIO52_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO52_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO52_FSEL_SHIFT)) & PINMUX__GPIO52_FSEL_MASK)
+#define PINMUX__GPIO52_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO52_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO52_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO52_DI_EN_SHIFT)) & PINMUX__GPIO52_DI_EN_MASK)
+#define PINMUX__GPIO52_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO52_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO52_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO52_SLP_VAL_SHIFT)) & PINMUX__GPIO52_SLP_VAL_MASK)
+#define PINMUX__GPIO52_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO52_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO52_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO52_SLP_OE_SHIFT)) & PINMUX__GPIO52_SLP_OE_MASK)
+#define PINMUX__GPIO52_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO52_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO52_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO52_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO52_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO52_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO52_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO52_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO52_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO52_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO52_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO52_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO52_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO52_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO52_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO53 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO53_FSEL_MASK (0x7U)
+#define PINMUX__GPIO53_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO53_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO53_FSEL_SHIFT)) & PINMUX__GPIO53_FSEL_MASK)
+#define PINMUX__GPIO53_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO53_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO53_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO53_DI_EN_SHIFT)) & PINMUX__GPIO53_DI_EN_MASK)
+#define PINMUX__GPIO53_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO53_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO53_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO53_SLP_VAL_SHIFT)) & PINMUX__GPIO53_SLP_VAL_MASK)
+#define PINMUX__GPIO53_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO53_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO53_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO53_SLP_OE_SHIFT)) & PINMUX__GPIO53_SLP_OE_MASK)
+#define PINMUX__GPIO53_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO53_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO53_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO53_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO53_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO53_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO53_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO53_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO53_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO53_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO53_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO53_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO53_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO53_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO53_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO54 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO54_FSEL_MASK (0x7U)
+#define PINMUX__GPIO54_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO54_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO54_FSEL_SHIFT)) & PINMUX__GPIO54_FSEL_MASK)
+#define PINMUX__GPIO54_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO54_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO54_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO54_DI_EN_SHIFT)) & PINMUX__GPIO54_DI_EN_MASK)
+#define PINMUX__GPIO54_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO54_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO54_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO54_SLP_VAL_SHIFT)) & PINMUX__GPIO54_SLP_VAL_MASK)
+#define PINMUX__GPIO54_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO54_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO54_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO54_SLP_OE_SHIFT)) & PINMUX__GPIO54_SLP_OE_MASK)
+#define PINMUX__GPIO54_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO54_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO54_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO54_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO54_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO54_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO54_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO54_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO54_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO54_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO54_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO54_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO54_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO54_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO54_PIO_PULL_SEL_MASK)
+/*! @} */
+
+/*! @name _GPIO55 - padring pin Register */
+/*! @{ */
+#define PINMUX__GPIO55_FSEL_MASK (0x7U)
+#define PINMUX__GPIO55_FSEL_SHIFT (0U)
+/*! FSEL - padring function select
+ */
+#define PINMUX__GPIO55_FSEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO55_FSEL_SHIFT)) & PINMUX__GPIO55_FSEL_MASK)
+#define PINMUX__GPIO55_DI_EN_MASK (0x8U)
+#define PINMUX__GPIO55_DI_EN_SHIFT (3U)
+/*! DI_EN - input enable control
+ * 0b0..receiver will be tri-stated
+ * 0b1..receive data from PAD
+ */
+#define PINMUX__GPIO55_DI_EN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO55_DI_EN_SHIFT)) & PINMUX__GPIO55_DI_EN_MASK)
+#define PINMUX__GPIO55_SLP_VAL_MASK (0x10U)
+#define PINMUX__GPIO55_SLP_VAL_SHIFT (4U)
+/*! SLP_VAL - reserved for test purpose
+ */
+#define PINMUX__GPIO55_SLP_VAL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO55_SLP_VAL_SHIFT)) & PINMUX__GPIO55_SLP_VAL_MASK)
+#define PINMUX__GPIO55_SLP_OE_MASK (0x20U)
+#define PINMUX__GPIO55_SLP_OE_SHIFT (5U)
+/*! SLP_OE - reserved for test purpose
+ */
+#define PINMUX__GPIO55_SLP_OE(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO55_SLP_OE_SHIFT)) & PINMUX__GPIO55_SLP_OE_MASK)
+#define PINMUX__GPIO55_PIO_PULL_DN_MASK (0x2000U)
+#define PINMUX__GPIO55_PIO_PULL_DN_SHIFT (13U)
+/*! PIO_PULL_DN - pull-down enable
+ * 0b0..pull-down disabled
+ * 0b1..pull-down enabled
+ */
+#define PINMUX__GPIO55_PIO_PULL_DN(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO55_PIO_PULL_DN_SHIFT)) & PINMUX__GPIO55_PIO_PULL_DN_MASK)
+#define PINMUX__GPIO55_PIO_PULL_UP_MASK (0x4000U)
+#define PINMUX__GPIO55_PIO_PULL_UP_SHIFT (14U)
+/*! PIO_PULL_UP - pull-up enable
+ * 0b0..pull-up disabled
+ * 0b1..pull-up enabled
+ */
+#define PINMUX__GPIO55_PIO_PULL_UP(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO55_PIO_PULL_UP_SHIFT)) & PINMUX__GPIO55_PIO_PULL_UP_MASK)
+#define PINMUX__GPIO55_PIO_PULL_SEL_MASK (0x8000U)
+#define PINMUX__GPIO55_PIO_PULL_SEL_SHIFT (15U)
+/*! PIO_PULL_SEL - custom pull-up and -down configuration control
+ * 0b0..pull-up and pull-down from io_mux
+ * 0b1..pull-up and pull-down from bits [14:13]
+ */
+#define PINMUX__GPIO55_PIO_PULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PINMUX__GPIO55_PIO_PULL_SEL_SHIFT)) & PINMUX__GPIO55_PIO_PULL_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PINMUX_Register_Masks */
+
+
+/* PINMUX - Peripheral instance base addresses */
+/** Peripheral PIN_MUX base address */
+#define PIN_MUX_BASE (0x48010000u)
+/** Peripheral PIN_MUX base pointer */
+#define PIN_MUX ((PINMUX_Type *)PIN_MUX_BASE)
+/** Array initializer of PINMUX peripheral base addresses */
+#define PINMUX_BASE_ADDRS { PIN_MUX_BASE }
+/** Array initializer of PINMUX peripheral base pointers */
+#define PINMUX_BASE_PTRS { PIN_MUX }
+
+/*!
+ * @}
+ */ /* end of group PINMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer
+ * @{
+ */
+
+/** PMU - Register Layout Typedef */
+typedef struct {
+ __O uint32_t PWR_MODE; /**< Power mode control register, offset: 0x0 */
+ __IO uint32_t BOOT_JTAG; /**< BOOT_JTAG register, offset: 0x4 */
+ __I uint32_t LAST_RST_CAUSE; /**< Last Reset Cause Register, offset: 0x8 */
+ __IO uint32_t LAST_RST_CLR; /**< Last Reset Cause Clear Register, offset: 0xC */
+ __IO uint32_t WAKE_SRC_CLR; /**< Wake up source clear register, offset: 0x10 */
+ __I uint32_t PWR_MODE_STATUS; /**< Power mode status register, offset: 0x14 */
+ __IO uint32_t CLK_SRC; /**< Clock source selection register, offset: 0x18 */
+ __I uint32_t WAKEUP_STATUS; /**< Wakeup status register, offset: 0x1C */
+ __IO uint32_t PMIP_BRN_INT_SEL; /**< PMIP Brown Interrupt Select, offset: 0x20 */
+ uint8_t RESERVED_0[4];
+ __I uint32_t CLK_RDY; /**< Clock ready register, offset: 0x28 */
+ __IO uint32_t RC32M_CTRL; /**< RC 32M control Register, offset: 0x2C */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SFLL_CTRL1; /**< SFLL control register 1, offset: 0x34 */
+ __IO uint32_t ANA_GRP_CTRL0; /**< Analog group control register, offset: 0x38 */
+ __IO uint32_t SFLL_CTRL0; /**< SFLL control register 2, offset: 0x3C */
+ __IO uint32_t PWR_CFG; /**< Power configuration register, offset: 0x40 */
+ __I uint32_t PWR_STAT; /**< Power status register, offset: 0x44 */
+ __IO uint32_t WF_OPT0; /**< WF OPT Power-Saving register 0, offset: 0x48 */
+ __IO uint32_t WF_OPT1; /**< WF OPT Power-Saving register 1, offset: 0x4C */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t PMIP_BRN_CFG; /**< Brownout configuration register, offset: 0x54 */
+ __IO uint32_t AUPLL_LOCK; /**< AUPLL lock status register, offset: 0x58 */
+ __IO uint32_t ANA_GRP_CTRL1; /**< BG control register, offset: 0x5C */
+ __IO uint32_t PMIP_PWR_CONFIG; /**< Power Configuration register, offset: 0x60 */
+ uint8_t RESERVED_3[8];
+ __IO uint32_t PMIP_TEST; /**< PMIP test register, offset: 0x6C */
+ uint8_t RESERVED_4[8];
+ __IO uint32_t AUPLL_CTRL0; /**< Audio PLL control register, offset: 0x78 */
+ __IO uint32_t PERI_CLK_EN; /**< Peripheral clock enable register, offset: 0x7C */
+ __IO uint32_t UART_FAST_CLK_DIV; /**< UART fast clock div register, offset: 0x80 */
+ __IO uint32_t UART_SLOW_CLK_DIV; /**< UART slow clock div register, offset: 0x84 */
+ __IO uint32_t UART_CLK_SEL; /**< UART clock select register, offset: 0x88 */
+ __IO uint32_t MCU_CORE_CLK_DIV; /**< MCU CORE clock divider ratio register, offset: 0x8C */
+ __IO uint32_t PERI0_CLK_DIV; /**< Peripheral0 clock divider ratio register, offset: 0x90 */
+ __IO uint32_t PERI1_CLK_DIV; /**< Peripheral1 clock divider ratio register, offset: 0x94 */
+ __IO uint32_t PERI2_CLK_DIV; /**< Peripheral2 Clock Divider Ratio Register, offset: 0x98 */
+ __IO uint32_t CAU_CLK_SEL; /**< select signal for CAU MCLK register, offset: 0x9C */
+ __IO uint32_t LOW_PWR_CTRL; /**< low power control in PM3/PM4 mode register, offset: 0xA0 */
+ __IO uint32_t IO_PAD_PWR_CFG; /**< I/O Pad Power configuration register, offset: 0xA4 */
+ __IO uint32_t EXT_SEL_REG0; /**< extra interrupt select register 0, offset: 0xA8 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t AUPLL_CTRL1; /**< USB and audio PLL control register, offset: 0xB0 */
+ __IO uint32_t CAU_CTRL; /**< CAU Control Register, offset: 0xB4 */
+ __IO uint32_t RC32K_CTRL0; /**< RC32k Control 0 Register, offset: 0xB8 */
+ __IO uint32_t RC32K_CTRL1; /**< RC32k Control 1 Register, offset: 0xBC */
+ __IO uint32_t XTAL32K_CTRL; /**< XTAL32k Control Register, offset: 0xC0 */
+ __IO uint32_t PMIP_CMP_CTRL; /**< PMIP Comparator Control Register, offset: 0xC4 */
+ __IO uint32_t PMIP_BRNDET_AV18; /**< PMIP Brownout AV18 Register, offset: 0xC8 */
+ uint8_t RESERVED_6[4];
+ __IO uint32_t PMIP_BRNDET_VBAT; /**< PMIP Brownout VBAT Register, offset: 0xD0 */
+ __IO uint32_t PMIP_BRNDET_V12; /**< PMIP Brownout V12 Register, offset: 0xD4 */
+ __IO uint32_t PMIP_LDO_CTRL; /**< PMIP LDO Control Register, offset: 0xD8 */
+ __IO uint32_t PERI_CLK_SRC; /**< PERI Clock Source Register, offset: 0xDC */
+ __IO uint32_t PMIP_RSVD; /**< Unused Register, offset: 0xE0 */
+ __IO uint32_t GPT0_CTRL; /**< GPT0 Control Register, offset: 0xE4 */
+ __IO uint32_t GPT1_CTRL; /**< GPT1 Control Register, offset: 0xE8 */
+ __IO uint32_t GPT2_CTRL; /**< GPT2 Control Register, offset: 0xEC */
+ __IO uint32_t GPT3_CTRL; /**< GPT3 Control Register, offset: 0xF0 */
+ __IO uint32_t WAKEUP_EDGE_DETECT; /**< Wakeup Edge Detect Register, offset: 0xF4 */
+ __IO uint32_t AON_CLK_CTRL; /**< AON Clock Control Register, offset: 0xF8 */
+ __IO uint32_t PERI3_CTRL; /**< PERI3 Control Register, offset: 0xFC */
+ __IO uint32_t IO_LPM_G03_; /**< I/O LPM G03 Register, offset: 0x100 */
+ __IO uint32_t IO_LPM_G47_; /**< I/O LPM G47 Register, offset: 0x104 */
+ __IO uint32_t IO_LPM_G811_; /**< I/O LPM G811 Register, offset: 0x108 */
+ __IO uint32_t IO_LPM_G1215_; /**< I/O LPM G1215 Register, offset: 0x10C */
+ __IO uint32_t IO_LPM_G1617_; /**< I/O LPM G1617 Register, offset: 0x110 */
+ __IO uint32_t WAKEUP_MASK; /**< Wakeup Mask Interrupt Register, offset: 0x114 */
+ __IO uint32_t WLAN_CTRL; /**< WLAN Control Register, offset: 0x118 */
+ __IO uint32_t WLAN_CTRL1; /**< WLAN Control 1 Register, offset: 0x11C */
+} PMU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMU_Register_Masks PMU Register Masks
+ * @{
+ */
+
+/*! @name PWR_MODE - Power mode control register */
+/*! @{ */
+#define PMU_PWR_MODE_PWR_MODE_MASK (0x3U)
+#define PMU_PWR_MODE_PWR_MODE_SHIFT (0U)
+/*! pwr_mode - Power mode switch
+ * 0b00..PM0 or PM1
+ * 0b01..
+ * 0b10..
+ * 0b11..
+ */
+#define PMU_PWR_MODE_PWR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PMU_PWR_MODE_PWR_MODE_SHIFT)) & PMU_PWR_MODE_PWR_MODE_MASK)
+/*! @} */
+
+/*! @name BOOT_JTAG - BOOT_JTAG register */
+/*! @{ */
+#define PMU_BOOT_JTAG_JTAG_EN_MASK (0x1U)
+#define PMU_BOOT_JTAG_JTAG_EN_SHIFT (0U)
+/*! jtag_en - JTAG Enable
+ * 0b0..disable JTAG
+ * 0b1..enable JTAG
+ */
+#define PMU_BOOT_JTAG_JTAG_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_BOOT_JTAG_JTAG_EN_SHIFT)) & PMU_BOOT_JTAG_JTAG_EN_MASK)
+#define PMU_BOOT_JTAG_BOOT_MODE_REG_MASK (0x6U)
+#define PMU_BOOT_JTAG_BOOT_MODE_REG_SHIFT (1U)
+/*! boot_mode_reg - Boot Mode
+ * 0b00..do not boot from Flash
+ * 0b01..boot from Flash
+ */
+#define PMU_BOOT_JTAG_BOOT_MODE_REG(x) (((uint32_t)(((uint32_t)(x)) << PMU_BOOT_JTAG_BOOT_MODE_REG_SHIFT)) & PMU_BOOT_JTAG_BOOT_MODE_REG_MASK)
+#define PMU_BOOT_JTAG_FLASH_OPT_MASK (0x8U)
+#define PMU_BOOT_JTAG_FLASH_OPT_SHIFT (3U)
+/*! flash_opt - Flash opt
+ * 0b0..chip with Flash
+ * 0b1..chip without Flash
+ */
+#define PMU_BOOT_JTAG_FLASH_OPT(x) (((uint32_t)(((uint32_t)(x)) << PMU_BOOT_JTAG_FLASH_OPT_SHIFT)) & PMU_BOOT_JTAG_FLASH_OPT_MASK)
+/*! @} */
+
+/*! @name LAST_RST_CAUSE - Last Reset Cause Register */
+/*! @{ */
+#define PMU_LAST_RST_CAUSE_BROWNOUT_VBAT_MASK (0x1U)
+#define PMU_LAST_RST_CAUSE_BROWNOUT_VBAT_SHIFT (0U)
+/*! brownout_vbat - VBAT power brownout
+ * 0b0..VBAT power brownout not detected
+ * 0b1..VBAT power brownout detected
+ */
+#define PMU_LAST_RST_CAUSE_BROWNOUT_VBAT(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CAUSE_BROWNOUT_VBAT_SHIFT)) & PMU_LAST_RST_CAUSE_BROWNOUT_VBAT_MASK)
+#define PMU_LAST_RST_CAUSE_BROWNOUT_V12_MASK (0x2U)
+#define PMU_LAST_RST_CAUSE_BROWNOUT_V12_SHIFT (1U)
+/*! brownout_v12 - AV12 power brownout
+ * 0b0..AV12 power brownout not detected
+ * 0b1..AV12 power brownout detected
+ */
+#define PMU_LAST_RST_CAUSE_BROWNOUT_V12(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CAUSE_BROWNOUT_V12_SHIFT)) & PMU_LAST_RST_CAUSE_BROWNOUT_V12_MASK)
+#define PMU_LAST_RST_CAUSE_BROWNOUT_AV18_MASK (0x4U)
+#define PMU_LAST_RST_CAUSE_BROWNOUT_AV18_SHIFT (2U)
+/*! brownout_av18 - AV18 power brownout
+ * 0b0..AV18 power brownout not detected
+ * 0b1..AV18 power brownout detected
+ */
+#define PMU_LAST_RST_CAUSE_BROWNOUT_AV18(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CAUSE_BROWNOUT_AV18_SHIFT)) & PMU_LAST_RST_CAUSE_BROWNOUT_AV18_MASK)
+#define PMU_LAST_RST_CAUSE_CM3_SYSRESETREQ_MASK (0x8U)
+#define PMU_LAST_RST_CAUSE_CM3_SYSRESETREQ_SHIFT (3U)
+/*! cm3_sysresetreq - CM3 System software reset request
+ * 0b0..reset cause is not system software reset request
+ * 0b1..reset cause is system software reset request
+ */
+#define PMU_LAST_RST_CAUSE_CM3_SYSRESETREQ(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CAUSE_CM3_SYSRESETREQ_SHIFT)) & PMU_LAST_RST_CAUSE_CM3_SYSRESETREQ_MASK)
+#define PMU_LAST_RST_CAUSE_CM3_LOCKUP_MASK (0x10U)
+#define PMU_LAST_RST_CAUSE_CM3_LOCKUP_SHIFT (4U)
+/*! cm3_lockup - CM3 Lockup
+ * 0b0..reset cause is not lockup
+ * 0b1..reset cause is lockup
+ */
+#define PMU_LAST_RST_CAUSE_CM3_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CAUSE_CM3_LOCKUP_SHIFT)) & PMU_LAST_RST_CAUSE_CM3_LOCKUP_MASK)
+#define PMU_LAST_RST_CAUSE_WDT_RST_MASK (0x20U)
+#define PMU_LAST_RST_CAUSE_WDT_RST_SHIFT (5U)
+/*! wdt_rst - WDT Reset
+ * 0b0..reset cause is not watchdog timer
+ * 0b1..reset cause is watchdog timer
+ */
+#define PMU_LAST_RST_CAUSE_WDT_RST(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CAUSE_WDT_RST_SHIFT)) & PMU_LAST_RST_CAUSE_WDT_RST_MASK)
+/*! @} */
+
+/*! @name LAST_RST_CLR - Last Reset Cause Clear Register */
+/*! @{ */
+#define PMU_LAST_RST_CLR_BROWNOUT_VBAT_CLR_MASK (0x1U)
+#define PMU_LAST_RST_CLR_BROWNOUT_VBAT_CLR_SHIFT (0U)
+/*! brownout_vbat_clr - Brownout VBAT Clear
+ */
+#define PMU_LAST_RST_CLR_BROWNOUT_VBAT_CLR(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CLR_BROWNOUT_VBAT_CLR_SHIFT)) & PMU_LAST_RST_CLR_BROWNOUT_VBAT_CLR_MASK)
+#define PMU_LAST_RST_CLR_BROWNOUT_V12_CLR_MASK (0x2U)
+#define PMU_LAST_RST_CLR_BROWNOUT_V12_CLR_SHIFT (1U)
+/*! brownout_v12_clr - Brownout V12 Clear
+ */
+#define PMU_LAST_RST_CLR_BROWNOUT_V12_CLR(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CLR_BROWNOUT_V12_CLR_SHIFT)) & PMU_LAST_RST_CLR_BROWNOUT_V12_CLR_MASK)
+#define PMU_LAST_RST_CLR_BROWNOUT_AV18_CLR_MASK (0x4U)
+#define PMU_LAST_RST_CLR_BROWNOUT_AV18_CLR_SHIFT (2U)
+/*! brownout_av18_clr - Brownout V18 Clear
+ */
+#define PMU_LAST_RST_CLR_BROWNOUT_AV18_CLR(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CLR_BROWNOUT_AV18_CLR_SHIFT)) & PMU_LAST_RST_CLR_BROWNOUT_AV18_CLR_MASK)
+#define PMU_LAST_RST_CLR_CM3_SYSRESETREQ_CLR_MASK (0x8U)
+#define PMU_LAST_RST_CLR_CM3_SYSRESETREQ_CLR_SHIFT (3U)
+/*! cm3_sysresetreq_clr - Clear system reset request
+ */
+#define PMU_LAST_RST_CLR_CM3_SYSRESETREQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CLR_CM3_SYSRESETREQ_CLR_SHIFT)) & PMU_LAST_RST_CLR_CM3_SYSRESETREQ_CLR_MASK)
+#define PMU_LAST_RST_CLR_CM3_LOCKUP_CLR_MASK (0x10U)
+#define PMU_LAST_RST_CLR_CM3_LOCKUP_CLR_SHIFT (4U)
+/*! cm3_lockup_clr - Clear lockup request
+ */
+#define PMU_LAST_RST_CLR_CM3_LOCKUP_CLR(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CLR_CM3_LOCKUP_CLR_SHIFT)) & PMU_LAST_RST_CLR_CM3_LOCKUP_CLR_MASK)
+#define PMU_LAST_RST_CLR_WDT_RST_CLR_MASK (0x20U)
+#define PMU_LAST_RST_CLR_WDT_RST_CLR_SHIFT (5U)
+/*! wdt_rst_clr - Clear watchdog timer reset request
+ */
+#define PMU_LAST_RST_CLR_WDT_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << PMU_LAST_RST_CLR_WDT_RST_CLR_SHIFT)) & PMU_LAST_RST_CLR_WDT_RST_CLR_MASK)
+/*! @} */
+
+/*! @name WAKE_SRC_CLR - Wake up source clear register */
+/*! @{ */
+#define PMU_WAKE_SRC_CLR_CLR_PIN0_INT_MASK (0x1U)
+#define PMU_WAKE_SRC_CLR_CLR_PIN0_INT_SHIFT (0U)
+/*! clr_pin0_int - Clear Pin0 interrupt request
+ */
+#define PMU_WAKE_SRC_CLR_CLR_PIN0_INT(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_CLR_PIN0_INT_SHIFT)) & PMU_WAKE_SRC_CLR_CLR_PIN0_INT_MASK)
+#define PMU_WAKE_SRC_CLR_CLR_PIN1_INT_MASK (0x2U)
+#define PMU_WAKE_SRC_CLR_CLR_PIN1_INT_SHIFT (1U)
+/*! clr_pin1_int - Clear Pin1 interrupt request
+ */
+#define PMU_WAKE_SRC_CLR_CLR_PIN1_INT(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_CLR_PIN1_INT_SHIFT)) & PMU_WAKE_SRC_CLR_CLR_PIN1_INT_MASK)
+#define PMU_WAKE_SRC_CLR_CLR_WL_INT_MASK (0x4U)
+#define PMU_WAKE_SRC_CLR_CLR_WL_INT_SHIFT (2U)
+/*! clr_wl_int - Clear WL interrupt request
+ */
+#define PMU_WAKE_SRC_CLR_CLR_WL_INT(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_CLR_WL_INT_SHIFT)) & PMU_WAKE_SRC_CLR_CLR_WL_INT_MASK)
+#define PMU_WAKE_SRC_CLR_CLR_RTC_INT_MASK (0x8U)
+#define PMU_WAKE_SRC_CLR_CLR_RTC_INT_SHIFT (3U)
+/*! clr_rtc_int - Clear RTC interrupt request
+ */
+#define PMU_WAKE_SRC_CLR_CLR_RTC_INT(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_CLR_RTC_INT_SHIFT)) & PMU_WAKE_SRC_CLR_CLR_RTC_INT_MASK)
+#define PMU_WAKE_SRC_CLR_CLR_COMP_INT_MASK (0x10U)
+#define PMU_WAKE_SRC_CLR_CLR_COMP_INT_SHIFT (4U)
+/*! clr_comp_int - Clear PMIP comp interrupt request
+ */
+#define PMU_WAKE_SRC_CLR_CLR_COMP_INT(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKE_SRC_CLR_CLR_COMP_INT_SHIFT)) & PMU_WAKE_SRC_CLR_CLR_COMP_INT_MASK)
+/*! @} */
+
+/*! @name PWR_MODE_STATUS - Power mode status register */
+/*! @{ */
+#define PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_MASK (0x3U)
+#define PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_SHIFT (0U)
+/*! pwr_mode_status - Power mode status
+ * 0b00..reset the power system
+ * 0b01..do not reset the power system
+ */
+#define PMU_PWR_MODE_STATUS_PWR_MODE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_SHIFT)) & PMU_PWR_MODE_STATUS_PWR_MODE_STATUS_MASK)
+/*! @} */
+
+/*! @name CLK_SRC - Clock source selection register */
+/*! @{ */
+#define PMU_CLK_SRC_SYS_CLK_SEL_MASK (0x3U)
+#define PMU_CLK_SRC_SYS_CLK_SEL_SHIFT (0U)
+/*! sys_clk_sel - System Clock Select
+ * 0b00..PLL 128 MHz clock
+ * 0b01..RC 32 MHz clock
+ * 0b10..XTAL 32 MHz clock
+ * 0b11..RC 32 MHz clock
+ */
+#define PMU_CLK_SRC_SYS_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_CLK_SRC_SYS_CLK_SEL_SHIFT)) & PMU_CLK_SRC_SYS_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name WAKEUP_STATUS - Wakeup status register */
+/*! @{ */
+#define PMU_WAKEUP_STATUS_PIN0_WAKEUP_STATUS_MASK (0x1U)
+#define PMU_WAKEUP_STATUS_PIN0_WAKEUP_STATUS_SHIFT (0U)
+/*! pin0_wakeup_status - External Pin0 wakeup status
+ */
+#define PMU_WAKEUP_STATUS_PIN0_WAKEUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_PIN0_WAKEUP_STATUS_SHIFT)) & PMU_WAKEUP_STATUS_PIN0_WAKEUP_STATUS_MASK)
+#define PMU_WAKEUP_STATUS_PIN1_WAKEUP_STATUS_MASK (0x2U)
+#define PMU_WAKEUP_STATUS_PIN1_WAKEUP_STATUS_SHIFT (1U)
+/*! pin1_wakeup_status - External Pin1 wakeup status
+ */
+#define PMU_WAKEUP_STATUS_PIN1_WAKEUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_PIN1_WAKEUP_STATUS_SHIFT)) & PMU_WAKEUP_STATUS_PIN1_WAKEUP_STATUS_MASK)
+#define PMU_WAKEUP_STATUS_WLINT_WAKEUP_STATUS_MASK (0x4U)
+#define PMU_WAKEUP_STATUS_WLINT_WAKEUP_STATUS_SHIFT (2U)
+/*! wlint_wakeup_status - WLAN interrupt wakeup status
+ */
+#define PMU_WAKEUP_STATUS_WLINT_WAKEUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_WLINT_WAKEUP_STATUS_SHIFT)) & PMU_WAKEUP_STATUS_WLINT_WAKEUP_STATUS_MASK)
+#define PMU_WAKEUP_STATUS_RTC_WAKEUP_STATUS_MASK (0x8U)
+#define PMU_WAKEUP_STATUS_RTC_WAKEUP_STATUS_SHIFT (3U)
+/*! rtc_wakeup_status - RTC wakeup status
+ */
+#define PMU_WAKEUP_STATUS_RTC_WAKEUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_RTC_WAKEUP_STATUS_SHIFT)) & PMU_WAKEUP_STATUS_RTC_WAKEUP_STATUS_MASK)
+#define PMU_WAKEUP_STATUS_PMIP_COMP_WAKEUP_STATUS_MASK (0x10U)
+#define PMU_WAKEUP_STATUS_PMIP_COMP_WAKEUP_STATUS_SHIFT (4U)
+/*! pmip_comp_wakeup_status - pmip_comp wakeup status
+ */
+#define PMU_WAKEUP_STATUS_PMIP_COMP_WAKEUP_STATUS(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_STATUS_PMIP_COMP_WAKEUP_STATUS_SHIFT)) & PMU_WAKEUP_STATUS_PMIP_COMP_WAKEUP_STATUS_MASK)
+/*! @} */
+
+/*! @name PMIP_BRN_INT_SEL - PMIP Brown Interrupt Select */
+/*! @{ */
+#define PMU_PMIP_BRN_INT_SEL_PMIP_BRN_INT_SEL_MASK (0x1U)
+#define PMU_PMIP_BRN_INT_SEL_PMIP_BRN_INT_SEL_SHIFT (0U)
+/*! pmip_brn_int_sel - PMIP Brownout Interrupt Select
+ * 0b0..generate an interrupt when VBAT brownout
+ * 0b1..reset chip when VBAT brownout
+ */
+#define PMU_PMIP_BRN_INT_SEL_PMIP_BRN_INT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRN_INT_SEL_PMIP_BRN_INT_SEL_SHIFT)) & PMU_PMIP_BRN_INT_SEL_PMIP_BRN_INT_SEL_MASK)
+/*! @} */
+
+/*! @name CLK_RDY - Clock ready register */
+/*! @{ */
+#define PMU_CLK_RDY_PLL_CLK_RDY_MASK (0x1U)
+#define PMU_CLK_RDY_PLL_CLK_RDY_SHIFT (0U)
+/*! pll_clk_rdy - PLL clock ready
+ * 0b0..PLL clock not ready for use
+ * 0b1..PLL clock ready for use
+ */
+#define PMU_CLK_RDY_PLL_CLK_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_CLK_RDY_PLL_CLK_RDY_SHIFT)) & PMU_CLK_RDY_PLL_CLK_RDY_MASK)
+#define PMU_CLK_RDY_RC32M_RDY_MASK (0x4U)
+#define PMU_CLK_RDY_RC32M_RDY_SHIFT (2U)
+/*! rc32m_rdy - RC 32M Ready
+ * 0b0..RC 32M clock not ready for use
+ * 0b1..RC 32M clock ready for use
+ */
+#define PMU_CLK_RDY_RC32M_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_CLK_RDY_RC32M_RDY_SHIFT)) & PMU_CLK_RDY_RC32M_RDY_MASK)
+#define PMU_CLK_RDY_X32K_RDY_MASK (0x8U)
+#define PMU_CLK_RDY_X32K_RDY_SHIFT (3U)
+/*! x32k_rdy - XTAL 32k Ready
+ * 0b0..XTAL 32k clock not ready for use
+ * 0b1..XTAL 32k clock ready for use
+ */
+#define PMU_CLK_RDY_X32K_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_CLK_RDY_X32K_RDY_SHIFT)) & PMU_CLK_RDY_X32K_RDY_MASK)
+#define PMU_CLK_RDY_PLL_AUDIO_RDY_MASK (0x10U)
+#define PMU_CLK_RDY_PLL_AUDIO_RDY_SHIFT (4U)
+/*! pll_audio_rdy - PLL audio ready
+ * 0b0..PLL audio clock not ready for use
+ * 0b1..PLL audio clock ready for use
+ */
+#define PMU_CLK_RDY_PLL_AUDIO_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_CLK_RDY_PLL_AUDIO_RDY_SHIFT)) & PMU_CLK_RDY_PLL_AUDIO_RDY_MASK)
+#define PMU_CLK_RDY_XTAL32M_CLK_RDY_MASK (0x40U)
+#define PMU_CLK_RDY_XTAL32M_CLK_RDY_SHIFT (6U)
+/*! xtal32m_clk_rdy - XTAL32M Clock Ready
+ */
+#define PMU_CLK_RDY_XTAL32M_CLK_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_CLK_RDY_XTAL32M_CLK_RDY_SHIFT)) & PMU_CLK_RDY_XTAL32M_CLK_RDY_MASK)
+/*! @} */
+
+/*! @name RC32M_CTRL - RC 32M control Register */
+/*! @{ */
+#define PMU_RC32M_CTRL_CAL_IN_PROGRESS_MASK (0x1U)
+#define PMU_RC32M_CTRL_CAL_IN_PROGRESS_SHIFT (0U)
+/*! cal_in_progress - Asserts high when calibration in progress
+ */
+#define PMU_RC32M_CTRL_CAL_IN_PROGRESS(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32M_CTRL_CAL_IN_PROGRESS_SHIFT)) & PMU_RC32M_CTRL_CAL_IN_PROGRESS_MASK)
+#define PMU_RC32M_CTRL_CAL_ALLOW_MASK (0x2U)
+#define PMU_RC32M_CTRL_CAL_ALLOW_SHIFT (1U)
+/*! cal_allow - Allow calibration command from PMU
+ */
+#define PMU_RC32M_CTRL_CAL_ALLOW(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32M_CTRL_CAL_ALLOW_SHIFT)) & PMU_RC32M_CTRL_CAL_ALLOW_MASK)
+/*! @} */
+
+/*! @name SFLL_CTRL1 - SFLL control register 1 */
+/*! @{ */
+#define PMU_SFLL_CTRL1_SFLL_REFDIV_MASK (0x1FFU)
+#define PMU_SFLL_CTRL1_SFLL_REFDIV_SHIFT (0U)
+/*! sfll_refdiv - Reference clock divider select
+ */
+#define PMU_SFLL_CTRL1_SFLL_REFDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL1_SFLL_REFDIV_SHIFT)) & PMU_SFLL_CTRL1_SFLL_REFDIV_MASK)
+#define PMU_SFLL_CTRL1_SFLL_TEST_ANA_MASK (0xE00U)
+#define PMU_SFLL_CTRL1_SFLL_TEST_ANA_SHIFT (9U)
+/*! sfll_test_ana - DC points Testing control
+ */
+#define PMU_SFLL_CTRL1_SFLL_TEST_ANA(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL1_SFLL_TEST_ANA_SHIFT)) & PMU_SFLL_CTRL1_SFLL_TEST_ANA_MASK)
+#define PMU_SFLL_CTRL1_SFLL_DIV_SEL_MASK (0x180000U)
+#define PMU_SFLL_CTRL1_SFLL_DIV_SEL_SHIFT (19U)
+/*! sfll_div_sel - Post divider
+ * 0b00..divide by 1 (bypass)
+ * 0b01..divide by 2
+ * 0b10..divide by 4
+ * 0b11..divide by 8
+ */
+#define PMU_SFLL_CTRL1_SFLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL1_SFLL_DIV_SEL_SHIFT)) & PMU_SFLL_CTRL1_SFLL_DIV_SEL_MASK)
+#define PMU_SFLL_CTRL1_SFLL_RESERVE_IN_MASK (0x7F800000U)
+#define PMU_SFLL_CTRL1_SFLL_RESERVE_IN_SHIFT (23U)
+/*! sfll_reserve_in - SFLL Reserved Input
+ */
+#define PMU_SFLL_CTRL1_SFLL_RESERVE_IN(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL1_SFLL_RESERVE_IN_SHIFT)) & PMU_SFLL_CTRL1_SFLL_RESERVE_IN_MASK)
+#define PMU_SFLL_CTRL1_REG_PLL_PU_INT_MASK (0x80000000U)
+#define PMU_SFLL_CTRL1_REG_PLL_PU_INT_SHIFT (31U)
+/*! reg_pll_pu_int - PLL PU Int
+ */
+#define PMU_SFLL_CTRL1_REG_PLL_PU_INT(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL1_REG_PLL_PU_INT_SHIFT)) & PMU_SFLL_CTRL1_REG_PLL_PU_INT_MASK)
+/*! @} */
+
+/*! @name ANA_GRP_CTRL0 - Analog group control register */
+/*! @{ */
+#define PMU_ANA_GRP_CTRL0_PU_OSC_MASK (0x1U)
+#define PMU_ANA_GRP_CTRL0_PU_OSC_SHIFT (0U)
+/*! PU_OSC - Power-up signal for OSC circuit
+ */
+#define PMU_ANA_GRP_CTRL0_PU_OSC(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL0_PU_OSC_SHIFT)) & PMU_ANA_GRP_CTRL0_PU_OSC_MASK)
+#define PMU_ANA_GRP_CTRL0_PU_XTAL_MASK (0x2U)
+#define PMU_ANA_GRP_CTRL0_PU_XTAL_SHIFT (1U)
+/*! PU_XTAL - Power-up signal for XTAL circuit
+ */
+#define PMU_ANA_GRP_CTRL0_PU_XTAL(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL0_PU_XTAL_SHIFT)) & PMU_ANA_GRP_CTRL0_PU_XTAL_MASK)
+#define PMU_ANA_GRP_CTRL0_PU_MASK (0x4U)
+#define PMU_ANA_GRP_CTRL0_PU_SHIFT (2U)
+/*! PU - Power-up signal for whole block
+ */
+#define PMU_ANA_GRP_CTRL0_PU(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL0_PU_SHIFT)) & PMU_ANA_GRP_CTRL0_PU_MASK)
+/*! @} */
+
+/*! @name SFLL_CTRL0 - SFLL control register 2 */
+/*! @{ */
+#define PMU_SFLL_CTRL0_SFLL_PU_MASK (0x1U)
+#define PMU_SFLL_CTRL0_SFLL_PU_SHIFT (0U)
+/*! sfll_pu - Power-up signal for the Flock
+ * 0b0..power down
+ * 0b1..power up
+ */
+#define PMU_SFLL_CTRL0_SFLL_PU(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL0_SFLL_PU_SHIFT)) & PMU_SFLL_CTRL0_SFLL_PU_MASK)
+#define PMU_SFLL_CTRL0_SFLL_FBDIV_MASK (0xFF80U)
+#define PMU_SFLL_CTRL0_SFLL_FBDIV_SHIFT (7U)
+/*! sfll_fbdiv - Feedback clock divider select
+ */
+#define PMU_SFLL_CTRL0_SFLL_FBDIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL0_SFLL_FBDIV_SHIFT)) & PMU_SFLL_CTRL0_SFLL_FBDIV_MASK)
+#define PMU_SFLL_CTRL0_SFLL_KVCO_MASK (0x300000U)
+#define PMU_SFLL_CTRL0_SFLL_KVCO_SHIFT (20U)
+/*! sfll_kvco - Select VCO Running Range Default value for output clock=200M
+ */
+#define PMU_SFLL_CTRL0_SFLL_KVCO(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL0_SFLL_KVCO_SHIFT)) & PMU_SFLL_CTRL0_SFLL_KVCO_MASK)
+#define PMU_SFLL_CTRL0_SFLL_REFCLK_SEL_MASK (0x2000000U)
+#define PMU_SFLL_CTRL0_SFLL_REFCLK_SEL_SHIFT (25U)
+/*! sfll_refclk_sel - Reference clock source select
+ * 0b0..RC 32M
+ * 0b1..XTAL 32M from WLAN
+ */
+#define PMU_SFLL_CTRL0_SFLL_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL0_SFLL_REFCLK_SEL_SHIFT)) & PMU_SFLL_CTRL0_SFLL_REFCLK_SEL_MASK)
+#define PMU_SFLL_CTRL0_SFLL_LOCK_MASK (0x4000000U)
+#define PMU_SFLL_CTRL0_SFLL_LOCK_SHIFT (26U)
+/*! sfll_lock - SFLL Lock
+ * 0b0..PLL module unlocked
+ * 0b1..PLL module locked
+ */
+#define PMU_SFLL_CTRL0_SFLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << PMU_SFLL_CTRL0_SFLL_LOCK_SHIFT)) & PMU_SFLL_CTRL0_SFLL_LOCK_MASK)
+/*! @} */
+
+/*! @name PWR_CFG - Power configuration register */
+/*! @{ */
+#define PMU_PWR_CFG_PM3_RET_MEM_CFG_MASK (0x7F0U)
+#define PMU_PWR_CFG_PM3_RET_MEM_CFG_SHIFT (4U)
+/*! PM3_RET_MEM_CFG - Retention memory enable register in PM3 mode
+ */
+#define PMU_PWR_CFG_PM3_RET_MEM_CFG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PWR_CFG_PM3_RET_MEM_CFG_SHIFT)) & PMU_PWR_CFG_PM3_RET_MEM_CFG_MASK)
+/*! @} */
+
+/*! @name PWR_STAT - Power status register */
+/*! @{ */
+#define PMU_PWR_STAT_V12_LDO_RDY_MASK (0x2U)
+#define PMU_PWR_STAT_V12_LDO_RDY_SHIFT (1U)
+/*! v12_ldo_rdy - v12_ldo_rdy
+ */
+#define PMU_PWR_STAT_V12_LDO_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_PWR_STAT_V12_LDO_RDY_SHIFT)) & PMU_PWR_STAT_V12_LDO_RDY_MASK)
+#define PMU_PWR_STAT_AV18_RDY_MASK (0x80U)
+#define PMU_PWR_STAT_AV18_RDY_SHIFT (7U)
+/*! av18_rdy - av18_rdy
+ */
+#define PMU_PWR_STAT_AV18_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_PWR_STAT_AV18_RDY_SHIFT)) & PMU_PWR_STAT_AV18_RDY_MASK)
+/*! @} */
+
+/*! @name WF_OPT0 - WF OPT Power-Saving register 0 */
+/*! @{ */
+#define PMU_WF_OPT0_MAX_FREQ_CTRL_MASK (0x2U)
+#define PMU_WF_OPT0_MAX_FREQ_CTRL_SHIFT (1U)
+/*! max_freq_ctrl - maximum frequency control
+ * 0b0..normal mode
+ * 0b1..maximum frequency is 125 MHz
+ */
+#define PMU_WF_OPT0_MAX_FREQ_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_WF_OPT0_MAX_FREQ_CTRL_SHIFT)) & PMU_WF_OPT0_MAX_FREQ_CTRL_MASK)
+#define PMU_WF_OPT0_MEM_CTRL_MASK (0x4U)
+#define PMU_WF_OPT0_MEM_CTRL_SHIFT (2U)
+/*! mem_ctrl - sram_memory control
+ * 0b0..normal mode
+ * 0b1..limit SRAM to 192K
+ */
+#define PMU_WF_OPT0_MEM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_WF_OPT0_MEM_CTRL_SHIFT)) & PMU_WF_OPT0_MEM_CTRL_MASK)
+/*! @} */
+
+/*! @name WF_OPT1 - WF OPT Power-Saving register 1 */
+/*! @{ */
+#define PMU_WF_OPT1_SPARE_MASK (0xCU)
+#define PMU_WF_OPT1_SPARE_SHIFT (2U)
+/*! spare - Spare
+ */
+#define PMU_WF_OPT1_SPARE(x) (((uint32_t)(((uint32_t)(x)) << PMU_WF_OPT1_SPARE_SHIFT)) & PMU_WF_OPT1_SPARE_MASK)
+/*! @} */
+
+/*! @name PMIP_BRN_CFG - Brownout configuration register */
+/*! @{ */
+#define PMU_PMIP_BRN_CFG_BRNDET_V12_RST_EN_MASK (0x1U)
+#define PMU_PMIP_BRN_CFG_BRNDET_V12_RST_EN_SHIFT (0U)
+/*! brndet_v12_rst_en - Brownout AV12 Reset Enable
+ */
+#define PMU_PMIP_BRN_CFG_BRNDET_V12_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRN_CFG_BRNDET_V12_RST_EN_SHIFT)) & PMU_PMIP_BRN_CFG_BRNDET_V12_RST_EN_MASK)
+#define PMU_PMIP_BRN_CFG_BRNDET_VBAT_RST_EN_MASK (0x2U)
+#define PMU_PMIP_BRN_CFG_BRNDET_VBAT_RST_EN_SHIFT (1U)
+/*! brndet_vbat_rst_en - Brownout VBAT Reset Enable
+ */
+#define PMU_PMIP_BRN_CFG_BRNDET_VBAT_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRN_CFG_BRNDET_VBAT_RST_EN_SHIFT)) & PMU_PMIP_BRN_CFG_BRNDET_VBAT_RST_EN_MASK)
+#define PMU_PMIP_BRN_CFG_BRNDET_AV18_RST_EN_MASK (0x8U)
+#define PMU_PMIP_BRN_CFG_BRNDET_AV18_RST_EN_SHIFT (3U)
+/*! brndet_av18_rst_en - Brownout AV18 Reset Enable
+ */
+#define PMU_PMIP_BRN_CFG_BRNDET_AV18_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRN_CFG_BRNDET_AV18_RST_EN_SHIFT)) & PMU_PMIP_BRN_CFG_BRNDET_AV18_RST_EN_MASK)
+/*! @} */
+
+/*! @name AUPLL_LOCK - AUPLL lock status register */
+/*! @{ */
+#define PMU_AUPLL_LOCK_RESERVED_OUT_0_MASK (0x3U)
+#define PMU_AUPLL_LOCK_RESERVED_OUT_0_SHIFT (0U)
+/*! Reserved_out_0 - Reserved Out 0
+ */
+#define PMU_AUPLL_LOCK_RESERVED_OUT_0(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_LOCK_RESERVED_OUT_0_SHIFT)) & PMU_AUPLL_LOCK_RESERVED_OUT_0_MASK)
+#define PMU_AUPLL_LOCK_AUPLL_LOCK_MASK (0x4U)
+#define PMU_AUPLL_LOCK_AUPLL_LOCK_SHIFT (2U)
+/*! aupll_lock - AUPLL Lock
+ */
+#define PMU_AUPLL_LOCK_AUPLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_LOCK_AUPLL_LOCK_SHIFT)) & PMU_AUPLL_LOCK_AUPLL_LOCK_MASK)
+#define PMU_AUPLL_LOCK_RESERVED_OUT_1_MASK (0xFFFFFFF8U)
+#define PMU_AUPLL_LOCK_RESERVED_OUT_1_SHIFT (3U)
+/*! Reserved_out_1 - Reserved Out 1
+ */
+#define PMU_AUPLL_LOCK_RESERVED_OUT_1(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_LOCK_RESERVED_OUT_1_SHIFT)) & PMU_AUPLL_LOCK_RESERVED_OUT_1_MASK)
+/*! @} */
+
+/*! @name ANA_GRP_CTRL1 - BG control register */
+/*! @{ */
+#define PMU_ANA_GRP_CTRL1_BG_CTRL_MASK (0x7U)
+#define PMU_ANA_GRP_CTRL1_BG_CTRL_SHIFT (0U)
+/*! bg_ctrl - bandgap control
+ */
+#define PMU_ANA_GRP_CTRL1_BG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL1_BG_CTRL_SHIFT)) & PMU_ANA_GRP_CTRL1_BG_CTRL_MASK)
+#define PMU_ANA_GRP_CTRL1_GAINX2_MASK (0x8U)
+#define PMU_ANA_GRP_CTRL1_GAINX2_SHIFT (3U)
+/*! GAINX2 - OSC gain control
+ */
+#define PMU_ANA_GRP_CTRL1_GAINX2(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL1_GAINX2_SHIFT)) & PMU_ANA_GRP_CTRL1_GAINX2_MASK)
+#define PMU_ANA_GRP_CTRL1_R_ORIEN_SEL_MASK (0x10U)
+#define PMU_ANA_GRP_CTRL1_R_ORIEN_SEL_SHIFT (4U)
+/*! R_ORIEN_SEL - RPP resister orientation selection
+ */
+#define PMU_ANA_GRP_CTRL1_R_ORIEN_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL1_R_ORIEN_SEL_SHIFT)) & PMU_ANA_GRP_CTRL1_R_ORIEN_SEL_MASK)
+#define PMU_ANA_GRP_CTRL1_BG_SEL_MASK (0x60U)
+#define PMU_ANA_GRP_CTRL1_BG_SEL_SHIFT (5U)
+/*! BG_SEL - Selects the Bandgap Voltage
+ */
+#define PMU_ANA_GRP_CTRL1_BG_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL1_BG_SEL_SHIFT)) & PMU_ANA_GRP_CTRL1_BG_SEL_MASK)
+#define PMU_ANA_GRP_CTRL1_TEST_MASK (0x380U)
+#define PMU_ANA_GRP_CTRL1_TEST_SHIFT (7U)
+/*! TEST - Analog test control bits
+ */
+#define PMU_ANA_GRP_CTRL1_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL1_TEST_SHIFT)) & PMU_ANA_GRP_CTRL1_TEST_MASK)
+#define PMU_ANA_GRP_CTRL1_BYPASS_MASK (0x400U)
+#define PMU_ANA_GRP_CTRL1_BYPASS_SHIFT (10U)
+/*! BYPASS - XTAL OSC bypass control signal
+ */
+#define PMU_ANA_GRP_CTRL1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMU_ANA_GRP_CTRL1_BYPASS_SHIFT)) & PMU_ANA_GRP_CTRL1_BYPASS_MASK)
+/*! @} */
+
+/*! @name PMIP_PWR_CONFIG - Power Configuration register */
+/*! @{ */
+#define PMU_PMIP_PWR_CONFIG_STATUS_DEL_SEL_MASK (0x3U)
+#define PMU_PMIP_PWR_CONFIG_STATUS_DEL_SEL_SHIFT (0U)
+/*! status_del_sel - Control counter in delay for rdy/rdy<0> handshaking
+ */
+#define PMU_PMIP_PWR_CONFIG_STATUS_DEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_PWR_CONFIG_STATUS_DEL_SEL_SHIFT)) & PMU_PMIP_PWR_CONFIG_STATUS_DEL_SEL_MASK)
+#define PMU_PMIP_PWR_CONFIG_AV18_EXT_MASK (0x4U)
+#define PMU_PMIP_PWR_CONFIG_AV18_EXT_SHIFT (2U)
+/*! av18_ext - AV18 External
+ */
+#define PMU_PMIP_PWR_CONFIG_AV18_EXT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_PWR_CONFIG_AV18_EXT_SHIFT)) & PMU_PMIP_PWR_CONFIG_AV18_EXT_MASK)
+/*! @} */
+
+/*! @name PMIP_TEST - PMIP test register */
+/*! @{ */
+#define PMU_PMIP_TEST_PMIP_TEST_MASK (0xFU)
+#define PMU_PMIP_TEST_PMIP_TEST_SHIFT (0U)
+/*! pmip_test - Test mux output
+ */
+#define PMU_PMIP_TEST_PMIP_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_TEST_PMIP_TEST_SHIFT)) & PMU_PMIP_TEST_PMIP_TEST_MASK)
+#define PMU_PMIP_TEST_PMIP_TEST_EN_MASK (0x10U)
+#define PMU_PMIP_TEST_PMIP_TEST_EN_SHIFT (4U)
+/*! pmip_test_en - PMIP Test Enable
+ * 0b0..disable PMIP analog test mux
+ * 0b1..enable PMIP analog test mux
+ */
+#define PMU_PMIP_TEST_PMIP_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_TEST_PMIP_TEST_EN_SHIFT)) & PMU_PMIP_TEST_PMIP_TEST_EN_MASK)
+#define PMU_PMIP_TEST_PMU_PMIP_TEST_MASK (0x1E0U)
+#define PMU_PMIP_TEST_PMU_PMIP_TEST_SHIFT (5U)
+/*! pmu_pmip_test - Test mux input
+ */
+#define PMU_PMIP_TEST_PMU_PMIP_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_TEST_PMU_PMIP_TEST_SHIFT)) & PMU_PMIP_TEST_PMU_PMIP_TEST_MASK)
+#define PMU_PMIP_TEST_PMU_PMIP_TEST_EN_MASK (0x200U)
+#define PMU_PMIP_TEST_PMU_PMIP_TEST_EN_SHIFT (9U)
+/*! pmu_pmip_test_en - Enable test mux
+ */
+#define PMU_PMIP_TEST_PMU_PMIP_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_TEST_PMU_PMIP_TEST_EN_SHIFT)) & PMU_PMIP_TEST_PMU_PMIP_TEST_EN_MASK)
+/*! @} */
+
+/*! @name AUPLL_CTRL0 - Audio PLL control register */
+/*! @{ */
+#define PMU_AUPLL_CTRL0_FRACT_MASK (0xFFFFFU)
+#define PMU_AUPLL_CTRL0_FRACT_SHIFT (0U)
+/*! FRACT - Fractional Part of PLL feedback divider
+ */
+#define PMU_AUPLL_CTRL0_FRACT(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL0_FRACT_SHIFT)) & PMU_AUPLL_CTRL0_FRACT_MASK)
+#define PMU_AUPLL_CTRL0_PU_MASK (0x100000U)
+#define PMU_AUPLL_CTRL0_PU_SHIFT (20U)
+/*! PU - Power-up signal for the PLL
+ */
+#define PMU_AUPLL_CTRL0_PU(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL0_PU_SHIFT)) & PMU_AUPLL_CTRL0_PU_MASK)
+/*! @} */
+
+/*! @name PERI_CLK_EN - Peripheral clock enable register */
+/*! @{ */
+#define PMU_PERI_CLK_EN_USIM_CLK_EN_MASK (0x1U)
+#define PMU_PERI_CLK_EN_USIM_CLK_EN_SHIFT (0U)
+/*! usim_clk_en - USIM clock enable
+ */
+#define PMU_PERI_CLK_EN_USIM_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_USIM_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_USIM_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_QSPI0_CLK_EN_MASK (0x2U)
+#define PMU_PERI_CLK_EN_QSPI0_CLK_EN_SHIFT (1U)
+/*! qspi0_clk_en - QSPI0 clock enable
+ */
+#define PMU_PERI_CLK_EN_QSPI0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_QSPI0_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_QSPI0_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_IR_CLK_EN_MASK (0x4U)
+#define PMU_PERI_CLK_EN_IR_CLK_EN_SHIFT (2U)
+/*! ir_clk_en - IR clock enable
+ */
+#define PMU_PERI_CLK_EN_IR_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_IR_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_IR_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_PDM_CLK_EN_MASK (0x8U)
+#define PMU_PERI_CLK_EN_PDM_CLK_EN_SHIFT (3U)
+/*! pdm_clk_en - PDM clock enable
+ */
+#define PMU_PERI_CLK_EN_PDM_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_PDM_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_PDM_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_GPIO_CLK_EN_MASK (0x10U)
+#define PMU_PERI_CLK_EN_GPIO_CLK_EN_SHIFT (4U)
+/*! gpio_clk_en - GPIO clock enable
+ */
+#define PMU_PERI_CLK_EN_GPIO_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_GPIO_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_GPIO_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_UART0_CLK_EN_MASK (0x20U)
+#define PMU_PERI_CLK_EN_UART0_CLK_EN_SHIFT (5U)
+/*! uart0_clk_en - UART0 clock enable
+ */
+#define PMU_PERI_CLK_EN_UART0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_UART0_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_UART0_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_UART1_CLK_EN_MASK (0x40U)
+#define PMU_PERI_CLK_EN_UART1_CLK_EN_SHIFT (6U)
+/*! uart1_clk_en - UART1 clock enable
+ */
+#define PMU_PERI_CLK_EN_UART1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_UART1_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_UART1_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_I2C0_CLK_EN_MASK (0x80U)
+#define PMU_PERI_CLK_EN_I2C0_CLK_EN_SHIFT (7U)
+/*! i2c0_clk_en - I2C0 clock enable
+ */
+#define PMU_PERI_CLK_EN_I2C0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_I2C0_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_I2C0_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_SSP0_CLK_EN_MASK (0x100U)
+#define PMU_PERI_CLK_EN_SSP0_CLK_EN_SHIFT (8U)
+/*! ssp0_clk_en - SSP0 clock enable
+ */
+#define PMU_PERI_CLK_EN_SSP0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_SSP0_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_SSP0_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_SSP1_CLK_EN_MASK (0x200U)
+#define PMU_PERI_CLK_EN_SSP1_CLK_EN_SHIFT (9U)
+/*! ssp1_clk_en - SSP1 clock enable
+ */
+#define PMU_PERI_CLK_EN_SSP1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_SSP1_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_SSP1_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_GPT0_CLK_EN_MASK (0x400U)
+#define PMU_PERI_CLK_EN_GPT0_CLK_EN_SHIFT (10U)
+/*! gpt0_clk_en - GPT0 clock enable
+ */
+#define PMU_PERI_CLK_EN_GPT0_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_GPT0_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_GPT0_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_GPT1_CLK_EN_MASK (0x800U)
+#define PMU_PERI_CLK_EN_GPT1_CLK_EN_SHIFT (11U)
+/*! gpt1_clk_en - GPT1 clock enable
+ */
+#define PMU_PERI_CLK_EN_GPT1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_GPT1_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_GPT1_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_UART2_CLK_EN_MASK (0x8000U)
+#define PMU_PERI_CLK_EN_UART2_CLK_EN_SHIFT (15U)
+/*! uart2_clk_en - UART2 clock enable
+ */
+#define PMU_PERI_CLK_EN_UART2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_UART2_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_UART2_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_UART3_CLK_EN_MASK (0x10000U)
+#define PMU_PERI_CLK_EN_UART3_CLK_EN_SHIFT (16U)
+/*! uart3_clk_en - UART3 clock enable
+ */
+#define PMU_PERI_CLK_EN_UART3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_UART3_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_UART3_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_SSP2_CLK_EN_MASK (0x20000U)
+#define PMU_PERI_CLK_EN_SSP2_CLK_EN_SHIFT (17U)
+/*! ssp2_clk_en - SSP2 clock enable
+ */
+#define PMU_PERI_CLK_EN_SSP2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_SSP2_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_SSP2_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_I2C1_CLK_EN_MASK (0x80000U)
+#define PMU_PERI_CLK_EN_I2C1_CLK_EN_SHIFT (19U)
+/*! i2c1_clk_en - I2C1 clock enable
+ */
+#define PMU_PERI_CLK_EN_I2C1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_I2C1_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_I2C1_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_I2C2_CLK_EN_MASK (0x100000U)
+#define PMU_PERI_CLK_EN_I2C2_CLK_EN_SHIFT (20U)
+/*! i2c2_clk_en - I2C2 clock enable
+ */
+#define PMU_PERI_CLK_EN_I2C2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_I2C2_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_I2C2_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_GPT2_CLK_EN_MASK (0x200000U)
+#define PMU_PERI_CLK_EN_GPT2_CLK_EN_SHIFT (21U)
+/*! gpt2_clk_en - GPT2 clock enable
+ */
+#define PMU_PERI_CLK_EN_GPT2_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_GPT2_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_GPT2_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_GPT3_CLK_EN_MASK (0x400000U)
+#define PMU_PERI_CLK_EN_GPT3_CLK_EN_SHIFT (22U)
+/*! gpt3_clk_en - GPT3 clock enable
+ */
+#define PMU_PERI_CLK_EN_GPT3_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_GPT3_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_GPT3_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_WDT_CLK_EN_MASK (0x800000U)
+#define PMU_PERI_CLK_EN_WDT_CLK_EN_SHIFT (23U)
+/*! wdt_clk_en - WDT clock enable
+ */
+#define PMU_PERI_CLK_EN_WDT_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_WDT_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_WDT_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_QSPI1_CLK_EN_MASK (0x1000000U)
+#define PMU_PERI_CLK_EN_QSPI1_CLK_EN_SHIFT (24U)
+/*! qspi1_clk_en - QSPI1 clock enable
+ */
+#define PMU_PERI_CLK_EN_QSPI1_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_QSPI1_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_QSPI1_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_SDIO_CLK_EN_MASK (0x2000000U)
+#define PMU_PERI_CLK_EN_SDIO_CLK_EN_SHIFT (25U)
+/*! sdio_clk_en - SDIO clock enable
+ */
+#define PMU_PERI_CLK_EN_SDIO_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_SDIO_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_SDIO_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_ADC_CLK_EN_MASK (0x4000000U)
+#define PMU_PERI_CLK_EN_ADC_CLK_EN_SHIFT (26U)
+/*! adc_clk_en - ADC clock enable
+ */
+#define PMU_PERI_CLK_EN_ADC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_ADC_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_ADC_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_USBC_CLK_EN_MASK (0x8000000U)
+#define PMU_PERI_CLK_EN_USBC_CLK_EN_SHIFT (27U)
+/*! usbc_clk_en - USBC clock enable
+ */
+#define PMU_PERI_CLK_EN_USBC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_USBC_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_USBC_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_USBC_AHB_CLK_EN_MASK (0x40000000U)
+#define PMU_PERI_CLK_EN_USBC_AHB_CLK_EN_SHIFT (30U)
+/*! usbc_ahb_clk_en - AHB USBC clock enable
+ */
+#define PMU_PERI_CLK_EN_USBC_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_USBC_AHB_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_USBC_AHB_CLK_EN_MASK)
+#define PMU_PERI_CLK_EN_SDIO_AHB_CLK_EN_MASK (0x80000000U)
+#define PMU_PERI_CLK_EN_SDIO_AHB_CLK_EN_SHIFT (31U)
+/*! sdio_ahb_clk_en - AHB SDIO clock enable
+ */
+#define PMU_PERI_CLK_EN_SDIO_AHB_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_EN_SDIO_AHB_CLK_EN_SHIFT)) & PMU_PERI_CLK_EN_SDIO_AHB_CLK_EN_MASK)
+/*! @} */
+
+/*! @name UART_FAST_CLK_DIV - UART fast clock div register */
+/*! @{ */
+#define PMU_UART_FAST_CLK_DIV_DENOMINATOR_MASK (0x7FFU)
+#define PMU_UART_FAST_CLK_DIV_DENOMINATOR_SHIFT (0U)
+/*! denominator - 11-Bit denominator for fractional divider
+ */
+#define PMU_UART_FAST_CLK_DIV_DENOMINATOR(x) (((uint32_t)(((uint32_t)(x)) << PMU_UART_FAST_CLK_DIV_DENOMINATOR_SHIFT)) & PMU_UART_FAST_CLK_DIV_DENOMINATOR_MASK)
+#define PMU_UART_FAST_CLK_DIV_NOMINATOR_MASK (0xFFF800U)
+#define PMU_UART_FAST_CLK_DIV_NOMINATOR_SHIFT (11U)
+/*! nominator - 13-Bit nominator for fraction divider
+ */
+#define PMU_UART_FAST_CLK_DIV_NOMINATOR(x) (((uint32_t)(((uint32_t)(x)) << PMU_UART_FAST_CLK_DIV_NOMINATOR_SHIFT)) & PMU_UART_FAST_CLK_DIV_NOMINATOR_MASK)
+/*! @} */
+
+/*! @name UART_SLOW_CLK_DIV - UART slow clock div register */
+/*! @{ */
+#define PMU_UART_SLOW_CLK_DIV_DENOMINATOR_MASK (0x7FFU)
+#define PMU_UART_SLOW_CLK_DIV_DENOMINATOR_SHIFT (0U)
+/*! denominator - 11-Bit denominator for fractional divider
+ */
+#define PMU_UART_SLOW_CLK_DIV_DENOMINATOR(x) (((uint32_t)(((uint32_t)(x)) << PMU_UART_SLOW_CLK_DIV_DENOMINATOR_SHIFT)) & PMU_UART_SLOW_CLK_DIV_DENOMINATOR_MASK)
+#define PMU_UART_SLOW_CLK_DIV_NOMINATOR_MASK (0xFFF800U)
+#define PMU_UART_SLOW_CLK_DIV_NOMINATOR_SHIFT (11U)
+/*! nominator - 13-Bit nominator for fraction divider
+ */
+#define PMU_UART_SLOW_CLK_DIV_NOMINATOR(x) (((uint32_t)(((uint32_t)(x)) << PMU_UART_SLOW_CLK_DIV_NOMINATOR_SHIFT)) & PMU_UART_SLOW_CLK_DIV_NOMINATOR_MASK)
+/*! @} */
+
+/*! @name UART_CLK_SEL - UART clock select register */
+/*! @{ */
+#define PMU_UART_CLK_SEL_UART0_CLK_SEL_MASK (0x1U)
+#define PMU_UART_CLK_SEL_UART0_CLK_SEL_SHIFT (0U)
+/*! uart0_clk_sel - UART0 APB0 UART clock select
+ * 0b0..
+ * 0b1..
+ */
+#define PMU_UART_CLK_SEL_UART0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_UART_CLK_SEL_UART0_CLK_SEL_SHIFT)) & PMU_UART_CLK_SEL_UART0_CLK_SEL_MASK)
+#define PMU_UART_CLK_SEL_UART1_CLK_SEL_MASK (0x2U)
+#define PMU_UART_CLK_SEL_UART1_CLK_SEL_SHIFT (1U)
+/*! uart1_clk_sel - UART1 APB0 UART clock select
+ * 0b0..
+ * 0b1..
+ */
+#define PMU_UART_CLK_SEL_UART1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_UART_CLK_SEL_UART1_CLK_SEL_SHIFT)) & PMU_UART_CLK_SEL_UART1_CLK_SEL_MASK)
+#define PMU_UART_CLK_SEL_UART2_CLK_SEL_MASK (0x4U)
+#define PMU_UART_CLK_SEL_UART2_CLK_SEL_SHIFT (2U)
+/*! uart2_clk_sel - UART2 APB1 UART clock select
+ * 0b0..
+ * 0b1..
+ */
+#define PMU_UART_CLK_SEL_UART2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_UART_CLK_SEL_UART2_CLK_SEL_SHIFT)) & PMU_UART_CLK_SEL_UART2_CLK_SEL_MASK)
+#define PMU_UART_CLK_SEL_UART3_CLK_SEL_MASK (0x8U)
+#define PMU_UART_CLK_SEL_UART3_CLK_SEL_SHIFT (3U)
+/*! uart3_clk_sel - UART3 APB1 UART clock select
+ * 0b0..
+ * 0b1..
+ */
+#define PMU_UART_CLK_SEL_UART3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_UART_CLK_SEL_UART3_CLK_SEL_SHIFT)) & PMU_UART_CLK_SEL_UART3_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name MCU_CORE_CLK_DIV - MCU CORE clock divider ratio register */
+/*! @{ */
+#define PMU_MCU_CORE_CLK_DIV_FCLK_DIV_MASK (0x3FU)
+#define PMU_MCU_CORE_CLK_DIV_FCLK_DIV_SHIFT (0U)
+/*! fclk_div - FCLK divisor
+ */
+#define PMU_MCU_CORE_CLK_DIV_FCLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_MCU_CORE_CLK_DIV_FCLK_DIV_SHIFT)) & PMU_MCU_CORE_CLK_DIV_FCLK_DIV_MASK)
+/*! @} */
+
+/*! @name PERI0_CLK_DIV - Peripheral0 clock divider ratio register */
+/*! @{ */
+#define PMU_PERI0_CLK_DIV_SSP0_CLK_DIV_MASK (0x1FU)
+#define PMU_PERI0_CLK_DIV_SSP0_CLK_DIV_SHIFT (0U)
+/*! ssp0_clk_div - SSP0 APB0 clock divisor
+ */
+#define PMU_PERI0_CLK_DIV_SSP0_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI0_CLK_DIV_SSP0_CLK_DIV_SHIFT)) & PMU_PERI0_CLK_DIV_SSP0_CLK_DIV_MASK)
+#define PMU_PERI0_CLK_DIV_SSP1_CLK_DIV_MASK (0x3E0U)
+#define PMU_PERI0_CLK_DIV_SSP1_CLK_DIV_SHIFT (5U)
+/*! ssp1_clk_div - SSP1 APB0 clock divisor
+ */
+#define PMU_PERI0_CLK_DIV_SSP1_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI0_CLK_DIV_SSP1_CLK_DIV_SHIFT)) & PMU_PERI0_CLK_DIV_SSP1_CLK_DIV_MASK)
+#define PMU_PERI0_CLK_DIV_SSP2_CLK_DIV_MASK (0x7C00U)
+#define PMU_PERI0_CLK_DIV_SSP2_CLK_DIV_SHIFT (10U)
+/*! ssp2_clk_div - SSP2 APB1 clock divisor
+ */
+#define PMU_PERI0_CLK_DIV_SSP2_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI0_CLK_DIV_SSP2_CLK_DIV_SHIFT)) & PMU_PERI0_CLK_DIV_SSP2_CLK_DIV_MASK)
+#define PMU_PERI0_CLK_DIV_SDIO_CLK_DIV_MASK (0xF0000U)
+#define PMU_PERI0_CLK_DIV_SDIO_CLK_DIV_SHIFT (16U)
+/*! sdio_clk_div - SDIO clock divisor
+ */
+#define PMU_PERI0_CLK_DIV_SDIO_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI0_CLK_DIV_SDIO_CLK_DIV_SHIFT)) & PMU_PERI0_CLK_DIV_SDIO_CLK_DIV_MASK)
+#define PMU_PERI0_CLK_DIV_IR_CLK_DIV_MASK (0x3F00000U)
+#define PMU_PERI0_CLK_DIV_IR_CLK_DIV_SHIFT (20U)
+/*! ir_clk_div - IR clock divisor
+ */
+#define PMU_PERI0_CLK_DIV_IR_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI0_CLK_DIV_IR_CLK_DIV_SHIFT)) & PMU_PERI0_CLK_DIV_IR_CLK_DIV_MASK)
+#define PMU_PERI0_CLK_DIV_PDM_CLK_DIV_MASK (0x7C000000U)
+#define PMU_PERI0_CLK_DIV_PDM_CLK_DIV_SHIFT (26U)
+/*! pdm_clk_div - PDM clock divisor
+ */
+#define PMU_PERI0_CLK_DIV_PDM_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI0_CLK_DIV_PDM_CLK_DIV_SHIFT)) & PMU_PERI0_CLK_DIV_PDM_CLK_DIV_MASK)
+/*! @} */
+
+/*! @name PERI1_CLK_DIV - Peripheral1 clock divider ratio register */
+/*! @{ */
+#define PMU_PERI1_CLK_DIV_FLASH_CLK_DIV_MASK (0x70U)
+#define PMU_PERI1_CLK_DIV_FLASH_CLK_DIV_SHIFT (4U)
+/*! flash_clk_div - Flash QSPI clock divisor
+ */
+#define PMU_PERI1_CLK_DIV_FLASH_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI1_CLK_DIV_FLASH_CLK_DIV_SHIFT)) & PMU_PERI1_CLK_DIV_FLASH_CLK_DIV_MASK)
+#define PMU_PERI1_CLK_DIV_QSPI0_CLK_DIV_MASK (0x700U)
+#define PMU_PERI1_CLK_DIV_QSPI0_CLK_DIV_SHIFT (8U)
+/*! qspi0_clk_div - QSPI0 APB0 clock divisor
+ */
+#define PMU_PERI1_CLK_DIV_QSPI0_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI1_CLK_DIV_QSPI0_CLK_DIV_SHIFT)) & PMU_PERI1_CLK_DIV_QSPI0_CLK_DIV_MASK)
+#define PMU_PERI1_CLK_DIV_QSPI1_CLK_DIV_MASK (0x7000U)
+#define PMU_PERI1_CLK_DIV_QSPI1_CLK_DIV_SHIFT (12U)
+/*! qspi1_clk_div - QSPI1 APB0 clock divisor
+ */
+#define PMU_PERI1_CLK_DIV_QSPI1_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI1_CLK_DIV_QSPI1_CLK_DIV_SHIFT)) & PMU_PERI1_CLK_DIV_QSPI1_CLK_DIV_MASK)
+#define PMU_PERI1_CLK_DIV_USIM_CLK_DIV_MASK (0x1F00000U)
+#define PMU_PERI1_CLK_DIV_USIM_CLK_DIV_SHIFT (20U)
+/*! usim_clk_div - USIM clock divisor
+ */
+#define PMU_PERI1_CLK_DIV_USIM_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI1_CLK_DIV_USIM_CLK_DIV_SHIFT)) & PMU_PERI1_CLK_DIV_USIM_CLK_DIV_MASK)
+/*! @} */
+
+/*! @name PERI2_CLK_DIV - Peripheral2 Clock Divider Ratio Register */
+/*! @{ */
+#define PMU_PERI2_CLK_DIV_GPT_SAMPLE_CLK_DIV_MASK (0x7U)
+#define PMU_PERI2_CLK_DIV_GPT_SAMPLE_CLK_DIV_SHIFT (0U)
+/*! gpt_sample_clk_div - GPT sample clock divisor
+ */
+#define PMU_PERI2_CLK_DIV_GPT_SAMPLE_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI2_CLK_DIV_GPT_SAMPLE_CLK_DIV_SHIFT)) & PMU_PERI2_CLK_DIV_GPT_SAMPLE_CLK_DIV_MASK)
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3_MASK (0x70U)
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3_SHIFT (4U)
+/*! wdt_clk_div_5_3 - See bit[25:24]
+ */
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3_SHIFT)) & PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3_MASK)
+#define PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0_MASK (0x700U)
+#define PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0_SHIFT (8U)
+/*! gpt3_clk_div_2_0 - GPT3 clock divisor[2:0]
+ * 0b000..(divisor = 1)
+ */
+#define PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0_SHIFT)) & PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0_MASK)
+#define PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3_MASK (0x7000U)
+#define PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3_SHIFT (12U)
+/*! gpt3_clk_div_5_3 - See bit[10:8]
+ */
+#define PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3_SHIFT)) & PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3_MASK)
+#define PMU_PERI2_CLK_DIV_I2C_CLK_DIV_MASK (0x300000U)
+#define PMU_PERI2_CLK_DIV_I2C_CLK_DIV_SHIFT (20U)
+/*! i2c_clk_div - i2c function clock divisor, divisor = i2c_clk_div
+ * 0b00..(divisor = 1)
+ */
+#define PMU_PERI2_CLK_DIV_I2C_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI2_CLK_DIV_I2C_CLK_DIV_SHIFT)) & PMU_PERI2_CLK_DIV_I2C_CLK_DIV_MASK)
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0_MASK (0x3000000U)
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0_SHIFT (24U)
+/*! wdt_clk_div_1_0 - WDT clock divisor
+ * 0b00..(divisor = 1)
+ */
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0_SHIFT)) & PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0_MASK)
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2_MASK (0x10000000U)
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2_SHIFT (28U)
+/*! wdt_clk_div_2_2 - See bit[25:24]
+ */
+#define PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2_SHIFT)) & PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2_MASK)
+/*! @} */
+
+/*! @name CAU_CLK_SEL - select signal for CAU MCLK register */
+/*! @{ */
+#define PMU_CAU_CLK_SEL_CAU_CLK_SEL_MASK (0x3U)
+#define PMU_CAU_CLK_SEL_CAU_CLK_SEL_SHIFT (0U)
+/*! cau_clk_sel - select signal for cau mclk
+ * 0b00..192M PLL clock
+ * 0b01..RC32 MHz clock
+ * 0b10..XTAL32 MHz clock
+ * 0b11..AUDIO PLL clock
+ */
+#define PMU_CAU_CLK_SEL_CAU_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAU_CLK_SEL_CAU_CLK_SEL_SHIFT)) & PMU_CAU_CLK_SEL_CAU_CLK_SEL_MASK)
+#define PMU_CAU_CLK_SEL_CAU_SW_GATE_MASK (0x4U)
+#define PMU_CAU_CLK_SEL_CAU_SW_GATE_SHIFT (2U)
+/*! cau_sw_gate - gate signal for cau mclk
+ */
+#define PMU_CAU_CLK_SEL_CAU_SW_GATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAU_CLK_SEL_CAU_SW_GATE_SHIFT)) & PMU_CAU_CLK_SEL_CAU_SW_GATE_MASK)
+/*! @} */
+
+/*! @name LOW_PWR_CTRL - low power control in PM3/PM4 mode register */
+/*! @{ */
+#define PMU_LOW_PWR_CTRL_CACHE_LINE_FLUSH_MASK (0x2U)
+#define PMU_LOW_PWR_CTRL_CACHE_LINE_FLUSH_SHIFT (1U)
+/*! cache_line_flush - flushes the cache
+ */
+#define PMU_LOW_PWR_CTRL_CACHE_LINE_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOW_PWR_CTRL_CACHE_LINE_FLUSH_SHIFT)) & PMU_LOW_PWR_CTRL_CACHE_LINE_FLUSH_MASK)
+#define PMU_LOW_PWR_CTRL_SLP_CTRL_MASK (0x8U)
+#define PMU_LOW_PWR_CTRL_SLP_CTRL_SHIFT (3U)
+/*! SLP_CTRL - 32k output clock enable signal
+ * 0b0..PU enabled while PD disabled
+ * 0b1..PU disabled while PD enabled
+ */
+#define PMU_LOW_PWR_CTRL_SLP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOW_PWR_CTRL_SLP_CTRL_SHIFT)) & PMU_LOW_PWR_CTRL_SLP_CTRL_MASK)
+#define PMU_LOW_PWR_CTRL_RC_OSC_SEL_MASK (0x10U)
+#define PMU_LOW_PWR_CTRL_RC_OSC_SEL_SHIFT (4U)
+/*! RC_OSC_SEL - RC32k and XTAL32k output clock selection
+ */
+#define PMU_LOW_PWR_CTRL_RC_OSC_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_LOW_PWR_CTRL_RC_OSC_SEL_SHIFT)) & PMU_LOW_PWR_CTRL_RC_OSC_SEL_MASK)
+/*! @} */
+
+/*! @name IO_PAD_PWR_CFG - I/O Pad Power configuration register */
+/*! @{ */
+#define PMU_IO_PAD_PWR_CFG_GPIO0_PDB_MASK (0x1U)
+#define PMU_IO_PAD_PWR_CFG_GPIO0_PDB_SHIFT (0U)
+/*! GPIO0_PDB - GPIO0 PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO0_PDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO0_PDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO0_PDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO1_PDB_MASK (0x2U)
+#define PMU_IO_PAD_PWR_CFG_GPIO1_PDB_SHIFT (1U)
+/*! GPIO1_PDB - GPIO1 PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO1_PDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO1_PDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO1_PDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO2_PDB_MASK (0x4U)
+#define PMU_IO_PAD_PWR_CFG_GPIO2_PDB_SHIFT (2U)
+/*! GPIO2_PDB - GPIO2 PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO2_PDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO2_PDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO2_PDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO3_PDB_MASK (0x8U)
+#define PMU_IO_PAD_PWR_CFG_GPIO3_PDB_SHIFT (3U)
+/*! GPIO3_PDB - GPIO3 PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO3_PDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO3_PDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO3_PDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO0_V25_MASK (0x10U)
+#define PMU_IO_PAD_PWR_CFG_GPIO0_V25_SHIFT (4U)
+/*! GPIO0_V25 - GPIO0 PAD group voltage select signal
+ * 0b0..3.3V
+ * 0b1..2.5V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO0_V25(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO0_V25_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO0_V25_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO1_V25_MASK (0x20U)
+#define PMU_IO_PAD_PWR_CFG_GPIO1_V25_SHIFT (5U)
+/*! GPIO1_V25 - GPIO1 PAD group voltage select signal
+ * 0b0..3.3V
+ * 0b1..2.5V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO1_V25(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO1_V25_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO1_V25_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO2_V25_MASK (0x40U)
+#define PMU_IO_PAD_PWR_CFG_GPIO2_V25_SHIFT (6U)
+/*! GPIO2_V25 - GPIO2 PAD group voltage select signal
+ * 0b0..3.3V
+ * 0b1..2.5V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO2_V25(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO2_V25_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO2_V25_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO3_V25_MASK (0x80U)
+#define PMU_IO_PAD_PWR_CFG_GPIO3_V25_SHIFT (7U)
+/*! GPIO3_V25 - GPIO3 PAD group voltage select signal
+ * 0b0..3.3V
+ * 0b1..2.5V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO3_V25(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO3_V25_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO3_V25_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO0_V18_MASK (0x100U)
+#define PMU_IO_PAD_PWR_CFG_GPIO0_V18_SHIFT (8U)
+/*! GPIO0_V18 - GPIO0 PAD group voltage select signal
+ * 0b0..2.5V or 3.3V
+ * 0b1..1.8V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO0_V18(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO0_V18_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO0_V18_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO1_V18_MASK (0x200U)
+#define PMU_IO_PAD_PWR_CFG_GPIO1_V18_SHIFT (9U)
+/*! GPIO1_V18 - GPIO1 PAD group voltage select signal
+ * 0b0..2.5V or 3.3V
+ * 0b1..1.8V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO1_V18(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO1_V18_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO1_V18_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO2_V18_MASK (0x400U)
+#define PMU_IO_PAD_PWR_CFG_GPIO2_V18_SHIFT (10U)
+/*! GPIO2_V18 - GPIO2 PAD group voltage select signal
+ * 0b0..2.5V or 3.3V
+ * 0b1..1.8V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO2_V18(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO2_V18_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO2_V18_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO3_V18_MASK (0x800U)
+#define PMU_IO_PAD_PWR_CFG_GPIO3_V18_SHIFT (11U)
+/*! GPIO3_V18 - GPIO3 PAD group voltage select signal
+ * 0b0..2.5V or 3.3V
+ * 0b1..1.8V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO3_V18(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO3_V18_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO3_V18_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_MASK (0x1000U)
+#define PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_SHIFT (12U)
+/*! GPIO0_LOW_VDDB - GPIO0 PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO1_LOW_VDDB_MASK (0x2000U)
+#define PMU_IO_PAD_PWR_CFG_GPIO1_LOW_VDDB_SHIFT (13U)
+/*! GPIO1_LOW_VDDB - GPIO1 PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO1_LOW_VDDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO1_LOW_VDDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO1_LOW_VDDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO2_LOW_VDDB_MASK (0x4000U)
+#define PMU_IO_PAD_PWR_CFG_GPIO2_LOW_VDDB_SHIFT (14U)
+/*! GPIO2_LOW_VDDB - GPIO2 PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO2_LOW_VDDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO2_LOW_VDDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO2_LOW_VDDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO3_LOW_VDDB_MASK (0x8000U)
+#define PMU_IO_PAD_PWR_CFG_GPIO3_LOW_VDDB_SHIFT (15U)
+/*! GPIO3_LOW_VDDB - GPIO3 PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO3_LOW_VDDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO3_LOW_VDDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO3_LOW_VDDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_LOW_VDDB_MASK (0x10000U)
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_LOW_VDDB_SHIFT (16U)
+/*! GPIO_AON_LOW_VDDB - Always on PAD group power switch signal
+ * 0b0..Power off
+ * 0b1..Power on
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_LOW_VDDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO_AON_LOW_VDDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO_AON_LOW_VDDB_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_V25_MASK (0x20000U)
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_V25_SHIFT (17U)
+/*! GPIO_AON_V25 - Always on PAD group voltage select signal
+ * 0b0..3.3V
+ * 0b1..2.5V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_V25(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO_AON_V25_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO_AON_V25_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_V18_MASK (0x40000U)
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_V18_SHIFT (18U)
+/*! GPIO_AON_V18 - Always on PAD group voltage select signal
+ * 0b0..2.5V or 3.3V
+ * 0b1..1.8V
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_V18(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO_AON_V18_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO_AON_V18_MASK)
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_PDB_MASK (0x80000U)
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_PDB_SHIFT (19U)
+/*! GPIO_AON_PDB - Always on PAD group power down mode control
+ * 0b0..power down mode
+ * 0b1..normal mode
+ */
+#define PMU_IO_PAD_PWR_CFG_GPIO_AON_PDB(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_PAD_PWR_CFG_GPIO_AON_PDB_SHIFT)) & PMU_IO_PAD_PWR_CFG_GPIO_AON_PDB_MASK)
+/*! @} */
+
+/*! @name EXT_SEL_REG0 - extra interrupt select register 0 */
+/*! @{ */
+#define PMU_EXT_SEL_REG0_SEL_34_MASK (0x1U)
+#define PMU_EXT_SEL_REG0_SEL_34_SHIFT (0U)
+/*! SEL_34 - select signal for extra interrupt 34
+ * 0b0..from GPIO_0
+ * 0b1..from GPIO_1
+ */
+#define PMU_EXT_SEL_REG0_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_34_SHIFT)) & PMU_EXT_SEL_REG0_SEL_34_MASK)
+#define PMU_EXT_SEL_REG0_SEL_35_MASK (0x2U)
+#define PMU_EXT_SEL_REG0_SEL_35_SHIFT (1U)
+/*! SEL_35 - select signal for extra interrupt 35
+ * 0b0..from GPIO_2
+ * 0b1..from GPIO_3
+ */
+#define PMU_EXT_SEL_REG0_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_35_SHIFT)) & PMU_EXT_SEL_REG0_SEL_35_MASK)
+#define PMU_EXT_SEL_REG0_SEL_36_MASK (0x4U)
+#define PMU_EXT_SEL_REG0_SEL_36_SHIFT (2U)
+/*! SEL_36 - select signal for extra interrupt 36
+ * 0b0..from GPIO_4
+ * 0b1..from GPIO_5
+ */
+#define PMU_EXT_SEL_REG0_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_36_SHIFT)) & PMU_EXT_SEL_REG0_SEL_36_MASK)
+#define PMU_EXT_SEL_REG0_SEL_37_MASK (0x8U)
+#define PMU_EXT_SEL_REG0_SEL_37_SHIFT (3U)
+/*! SEL_37 - select signal for extra interrupt 37
+ * 0b0..from GPIO_6
+ * 0b1..from GPIO_7
+ */
+#define PMU_EXT_SEL_REG0_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_37_SHIFT)) & PMU_EXT_SEL_REG0_SEL_37_MASK)
+#define PMU_EXT_SEL_REG0_SEL_38_MASK (0x10U)
+#define PMU_EXT_SEL_REG0_SEL_38_SHIFT (4U)
+/*! SEL_38 - select signal for extra interrupt 38
+ * 0b0..from GPIO_8
+ * 0b1..from GPIO_9
+ */
+#define PMU_EXT_SEL_REG0_SEL_38(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_38_SHIFT)) & PMU_EXT_SEL_REG0_SEL_38_MASK)
+#define PMU_EXT_SEL_REG0_SEL_39_MASK (0x20U)
+#define PMU_EXT_SEL_REG0_SEL_39_SHIFT (5U)
+/*! SEL_39 - select signal for extra interrupt 39
+ * 0b0..from GPIO_10
+ * 0b1..from GPIO_11
+ */
+#define PMU_EXT_SEL_REG0_SEL_39(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_39_SHIFT)) & PMU_EXT_SEL_REG0_SEL_39_MASK)
+#define PMU_EXT_SEL_REG0_SEL_40_MASK (0x40U)
+#define PMU_EXT_SEL_REG0_SEL_40_SHIFT (6U)
+/*! SEL_40 - select signal for extra interrupt 40
+ * 0b0..from GPIO_12
+ * 0b1..from GPIO_13
+ */
+#define PMU_EXT_SEL_REG0_SEL_40(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_40_SHIFT)) & PMU_EXT_SEL_REG0_SEL_40_MASK)
+#define PMU_EXT_SEL_REG0_SEL_41_MASK (0x80U)
+#define PMU_EXT_SEL_REG0_SEL_41_SHIFT (7U)
+/*! SEL_41 - select signal for extra interrupt 41
+ * 0b0..from GPIO_14
+ * 0b1..from GPIO_15
+ */
+#define PMU_EXT_SEL_REG0_SEL_41(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_41_SHIFT)) & PMU_EXT_SEL_REG0_SEL_41_MASK)
+#define PMU_EXT_SEL_REG0_SEL_42_MASK (0x100U)
+#define PMU_EXT_SEL_REG0_SEL_42_SHIFT (8U)
+/*! SEL_42 - select signal for extra interrupt 42
+ * 0b0..from GPIO_16
+ * 0b1..from GPIO_17
+ */
+#define PMU_EXT_SEL_REG0_SEL_42(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_42_SHIFT)) & PMU_EXT_SEL_REG0_SEL_42_MASK)
+#define PMU_EXT_SEL_REG0_SEL_43_MASK (0x200U)
+#define PMU_EXT_SEL_REG0_SEL_43_SHIFT (9U)
+/*! SEL_43 - select signal for extra interrupt 43
+ * 0b0..from GPIO_18
+ * 0b1..from GPIO_19
+ */
+#define PMU_EXT_SEL_REG0_SEL_43(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_43_SHIFT)) & PMU_EXT_SEL_REG0_SEL_43_MASK)
+#define PMU_EXT_SEL_REG0_SEL_44_MASK (0x400U)
+#define PMU_EXT_SEL_REG0_SEL_44_SHIFT (10U)
+/*! SEL_44 - select signal for extra interrupt 44
+ * 0b0..from GPIO_20
+ * 0b1..from GPIO_21
+ */
+#define PMU_EXT_SEL_REG0_SEL_44(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_44_SHIFT)) & PMU_EXT_SEL_REG0_SEL_44_MASK)
+#define PMU_EXT_SEL_REG0_SEL_45_MASK (0x800U)
+#define PMU_EXT_SEL_REG0_SEL_45_SHIFT (11U)
+/*! SEL_45 - select signal for extra interrupt 45
+ * 0b0..from GPIO_22
+ * 0b1..from GPIO_23
+ */
+#define PMU_EXT_SEL_REG0_SEL_45(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_45_SHIFT)) & PMU_EXT_SEL_REG0_SEL_45_MASK)
+#define PMU_EXT_SEL_REG0_SEL_46_MASK (0x1000U)
+#define PMU_EXT_SEL_REG0_SEL_46_SHIFT (12U)
+/*! SEL_46 - select signal for extra interrupt 46
+ * 0b0..from GPIO_24
+ * 0b1..from GPIO_25
+ */
+#define PMU_EXT_SEL_REG0_SEL_46(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_46_SHIFT)) & PMU_EXT_SEL_REG0_SEL_46_MASK)
+#define PMU_EXT_SEL_REG0_SEL_47_MASK (0x2000U)
+#define PMU_EXT_SEL_REG0_SEL_47_SHIFT (13U)
+/*! SEL_47 - select signal for extra interrupt 47
+ * 0b0..from GPIO_26
+ * 0b1..from GPIO_27
+ */
+#define PMU_EXT_SEL_REG0_SEL_47(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_47_SHIFT)) & PMU_EXT_SEL_REG0_SEL_47_MASK)
+#define PMU_EXT_SEL_REG0_SEL_48_MASK (0x4000U)
+#define PMU_EXT_SEL_REG0_SEL_48_SHIFT (14U)
+/*! SEL_48 - select signal for extra interrupt 48
+ * 0b0..from GPIO_28
+ * 0b1..from GPIO_29
+ */
+#define PMU_EXT_SEL_REG0_SEL_48(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_48_SHIFT)) & PMU_EXT_SEL_REG0_SEL_48_MASK)
+#define PMU_EXT_SEL_REG0_SEL_49_MASK (0x8000U)
+#define PMU_EXT_SEL_REG0_SEL_49_SHIFT (15U)
+/*! SEL_49 - select signal for extra interrupt 49
+ * 0b0..from GPIO_30
+ * 0b1..from GPIO_31
+ */
+#define PMU_EXT_SEL_REG0_SEL_49(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_49_SHIFT)) & PMU_EXT_SEL_REG0_SEL_49_MASK)
+#define PMU_EXT_SEL_REG0_SEL_50_MASK (0x10000U)
+#define PMU_EXT_SEL_REG0_SEL_50_SHIFT (16U)
+/*! SEL_50 - select signal for extra interrupt 50
+ * 0b0..from GPIO_32
+ * 0b1..from GPIO_33
+ */
+#define PMU_EXT_SEL_REG0_SEL_50(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_50_SHIFT)) & PMU_EXT_SEL_REG0_SEL_50_MASK)
+#define PMU_EXT_SEL_REG0_SEL_51_MASK (0x20000U)
+#define PMU_EXT_SEL_REG0_SEL_51_SHIFT (17U)
+/*! SEL_51 - select signal for extra interrupt 51
+ * 0b0..from GPIO_34
+ * 0b1..from GPIO_35
+ */
+#define PMU_EXT_SEL_REG0_SEL_51(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_51_SHIFT)) & PMU_EXT_SEL_REG0_SEL_51_MASK)
+#define PMU_EXT_SEL_REG0_SEL_52_MASK (0x40000U)
+#define PMU_EXT_SEL_REG0_SEL_52_SHIFT (18U)
+/*! SEL_52 - select signal for extra interrupt 52
+ * 0b0..from GPIO_36
+ * 0b1..from GPIO_37
+ */
+#define PMU_EXT_SEL_REG0_SEL_52(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_52_SHIFT)) & PMU_EXT_SEL_REG0_SEL_52_MASK)
+#define PMU_EXT_SEL_REG0_SEL_53_MASK (0x80000U)
+#define PMU_EXT_SEL_REG0_SEL_53_SHIFT (19U)
+/*! SEL_53 - select signal for extra interrupt 53
+ * 0b0..from GPIO_38
+ * 0b1..from GPIO_39
+ */
+#define PMU_EXT_SEL_REG0_SEL_53(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_53_SHIFT)) & PMU_EXT_SEL_REG0_SEL_53_MASK)
+#define PMU_EXT_SEL_REG0_SEL_54_MASK (0x100000U)
+#define PMU_EXT_SEL_REG0_SEL_54_SHIFT (20U)
+/*! SEL_54 - select signal for extra interrupt 54
+ * 0b0..from GPIO_40
+ * 0b1..from GPIO_41
+ */
+#define PMU_EXT_SEL_REG0_SEL_54(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_54_SHIFT)) & PMU_EXT_SEL_REG0_SEL_54_MASK)
+#define PMU_EXT_SEL_REG0_SEL_55_MASK (0x200000U)
+#define PMU_EXT_SEL_REG0_SEL_55_SHIFT (21U)
+/*! SEL_55 - select signal for extra interrupt 55
+ * 0b0..from GPIO_42
+ * 0b1..from GPIO_43
+ */
+#define PMU_EXT_SEL_REG0_SEL_55(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_55_SHIFT)) & PMU_EXT_SEL_REG0_SEL_55_MASK)
+#define PMU_EXT_SEL_REG0_SEL_56_MASK (0x400000U)
+#define PMU_EXT_SEL_REG0_SEL_56_SHIFT (22U)
+/*! SEL_56 - select signal for extra interrupt 56
+ * 0b0..from GPIO_44
+ * 0b1..from GPIO_45
+ */
+#define PMU_EXT_SEL_REG0_SEL_56(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_56_SHIFT)) & PMU_EXT_SEL_REG0_SEL_56_MASK)
+#define PMU_EXT_SEL_REG0_SEL_57_MASK (0x800000U)
+#define PMU_EXT_SEL_REG0_SEL_57_SHIFT (23U)
+/*! SEL_57 - select signal for extra interrupt 57
+ * 0b0..from GPIO_46
+ * 0b1..from GPIO_47
+ */
+#define PMU_EXT_SEL_REG0_SEL_57(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_57_SHIFT)) & PMU_EXT_SEL_REG0_SEL_57_MASK)
+#define PMU_EXT_SEL_REG0_SEL_58_MASK (0x1000000U)
+#define PMU_EXT_SEL_REG0_SEL_58_SHIFT (24U)
+/*! SEL_58 - select signal for extra interrupt 58
+ * 0b0..from GPIO_48
+ * 0b1..from GPIO_49
+ */
+#define PMU_EXT_SEL_REG0_SEL_58(x) (((uint32_t)(((uint32_t)(x)) << PMU_EXT_SEL_REG0_SEL_58_SHIFT)) & PMU_EXT_SEL_REG0_SEL_58_MASK)
+/*! @} */
+
+/*! @name AUPLL_CTRL1 - USB and audio PLL control register */
+/*! @{ */
+#define PMU_AUPLL_CTRL1_PD_OVPROT_MASK (0x1U)
+#define PMU_AUPLL_CTRL1_PD_OVPROT_SHIFT (0U)
+/*! PD_OVPROT - Enable Over-Voltage protection on VCO
+ */
+#define PMU_AUPLL_CTRL1_PD_OVPROT(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_PD_OVPROT_SHIFT)) & PMU_AUPLL_CTRL1_PD_OVPROT_MASK)
+#define PMU_AUPLL_CTRL1_REFCLK_SEL_MASK (0x2U)
+#define PMU_AUPLL_CTRL1_REFCLK_SEL_SHIFT (1U)
+/*! REFCLK_SEL - Reference clock selection
+ */
+#define PMU_AUPLL_CTRL1_REFCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_REFCLK_SEL_SHIFT)) & PMU_AUPLL_CTRL1_REFCLK_SEL_MASK)
+#define PMU_AUPLL_CTRL1_ICP_MASK (0xCU)
+#define PMU_AUPLL_CTRL1_ICP_SHIFT (2U)
+/*! ICP - Charge-Pump current control bits
+ */
+#define PMU_AUPLL_CTRL1_ICP(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_ICP_SHIFT)) & PMU_AUPLL_CTRL1_ICP_MASK)
+#define PMU_AUPLL_CTRL1_ENA_DITHER_MASK (0x10U)
+#define PMU_AUPLL_CTRL1_ENA_DITHER_SHIFT (4U)
+/*! ENA_DITHER - ENA Dither
+ */
+#define PMU_AUPLL_CTRL1_ENA_DITHER(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_ENA_DITHER_SHIFT)) & PMU_AUPLL_CTRL1_ENA_DITHER_MASK)
+#define PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN_MASK (0x60U)
+#define PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN_SHIFT (5U)
+/*! DIV_OCLK_PATTERN - Output clock divider control
+ */
+#define PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN_SHIFT)) & PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN_MASK)
+#define PMU_AUPLL_CTRL1_DIV_OCLK_MODULO_MASK (0x380U)
+#define PMU_AUPLL_CTRL1_DIV_OCLK_MODULO_SHIFT (7U)
+/*! DIV_OCLK_MODULO - Output clock divider control
+ */
+#define PMU_AUPLL_CTRL1_DIV_OCLK_MODULO(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_DIV_OCLK_MODULO_SHIFT)) & PMU_AUPLL_CTRL1_DIV_OCLK_MODULO_MASK)
+#define PMU_AUPLL_CTRL1_DIV_MCLK_MASK (0x3C00U)
+#define PMU_AUPLL_CTRL1_DIV_MCLK_SHIFT (10U)
+/*! DIV_MCLK - MCLK divider
+ */
+#define PMU_AUPLL_CTRL1_DIV_MCLK(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_DIV_MCLK_SHIFT)) & PMU_AUPLL_CTRL1_DIV_MCLK_MASK)
+#define PMU_AUPLL_CTRL1_DIV_FBCCLK_MASK (0xFC000U)
+#define PMU_AUPLL_CTRL1_DIV_FBCCLK_SHIFT (14U)
+/*! DIV_FBCCLK - FBC divider
+ */
+#define PMU_AUPLL_CTRL1_DIV_FBCCLK(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_DIV_FBCCLK_SHIFT)) & PMU_AUPLL_CTRL1_DIV_FBCCLK_MASK)
+#define PMU_AUPLL_CTRL1_ANA_TSTPNT_MASK (0x300000U)
+#define PMU_AUPLL_CTRL1_ANA_TSTPNT_SHIFT (20U)
+/*! ANA_TSTPNT - Analog test select
+ */
+#define PMU_AUPLL_CTRL1_ANA_TSTPNT(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_ANA_TSTPNT_SHIFT)) & PMU_AUPLL_CTRL1_ANA_TSTPNT_MASK)
+#define PMU_AUPLL_CTRL1_DIG_TSTPNT_MASK (0xC00000U)
+#define PMU_AUPLL_CTRL1_DIG_TSTPNT_SHIFT (22U)
+/*! DIG_TSTPNT - Digital test select
+ */
+#define PMU_AUPLL_CTRL1_DIG_TSTPNT(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_DIG_TSTPNT_SHIFT)) & PMU_AUPLL_CTRL1_DIG_TSTPNT_MASK)
+#define PMU_AUPLL_CTRL1_EN_VCOX2_MASK (0x20000000U)
+#define PMU_AUPLL_CTRL1_EN_VCOX2_SHIFT (29U)
+/*! EN_VCOX2 - Enable or Disable VCOCLK_X2
+ */
+#define PMU_AUPLL_CTRL1_EN_VCOX2(x) (((uint32_t)(((uint32_t)(x)) << PMU_AUPLL_CTRL1_EN_VCOX2_SHIFT)) & PMU_AUPLL_CTRL1_EN_VCOX2_MASK)
+/*! @} */
+
+/*! @name CAU_CTRL - CAU Control Register */
+/*! @{ */
+#define PMU_CAU_CTRL_CAU_ACOMP_MCLK_EN_MASK (0x1U)
+#define PMU_CAU_CTRL_CAU_ACOMP_MCLK_EN_SHIFT (0U)
+/*! cau_acomp_mclk_en - cau_acomp module main clock enable signal
+ * 0b0..do not enable
+ * 0b1..
+ */
+#define PMU_CAU_CTRL_CAU_ACOMP_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAU_CTRL_CAU_ACOMP_MCLK_EN_SHIFT)) & PMU_CAU_CTRL_CAU_ACOMP_MCLK_EN_MASK)
+#define PMU_CAU_CTRL_CAU_GPDAC_MCLK_EN_MASK (0x2U)
+#define PMU_CAU_CTRL_CAU_GPDAC_MCLK_EN_SHIFT (1U)
+/*! cau_gpdac_mclk_en - cau_gpdac module main clock enable signal
+ * 0b0..do not enable
+ * 0b1..
+ */
+#define PMU_CAU_CTRL_CAU_GPDAC_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAU_CTRL_CAU_GPDAC_MCLK_EN_SHIFT)) & PMU_CAU_CTRL_CAU_GPDAC_MCLK_EN_MASK)
+#define PMU_CAU_CTRL_CAU_GPADC1_MCLK_EN_MASK (0x4U)
+#define PMU_CAU_CTRL_CAU_GPADC1_MCLK_EN_SHIFT (2U)
+/*! cau_gpadc1_mclk_en - cau_gpadc1 module main clock enable signal
+ * 0b0..do not enable
+ * 0b1..
+ */
+#define PMU_CAU_CTRL_CAU_GPADC1_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAU_CTRL_CAU_GPADC1_MCLK_EN_SHIFT)) & PMU_CAU_CTRL_CAU_GPADC1_MCLK_EN_MASK)
+#define PMU_CAU_CTRL_CAU_GPADC0_MCLK_EN_MASK (0x8U)
+#define PMU_CAU_CTRL_CAU_GPADC0_MCLK_EN_SHIFT (3U)
+/*! cau_gpadc0_mclk_en - cau_gpadc0 module main clock enable signal
+ * 0b0..do not enable
+ * 0b1..
+ */
+#define PMU_CAU_CTRL_CAU_GPADC0_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAU_CTRL_CAU_GPADC0_MCLK_EN_SHIFT)) & PMU_CAU_CTRL_CAU_GPADC0_MCLK_EN_MASK)
+#define PMU_CAU_CTRL_CAU_BG_MCLK_EN_MASK (0x10U)
+#define PMU_CAU_CTRL_CAU_BG_MCLK_EN_SHIFT (4U)
+/*! cau_bg_mclk_en - cau_bg module main clock enable signal
+ * 0b0..do not enable
+ * 0b1..
+ */
+#define PMU_CAU_CTRL_CAU_BG_MCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_CAU_CTRL_CAU_BG_MCLK_EN_SHIFT)) & PMU_CAU_CTRL_CAU_BG_MCLK_EN_MASK)
+/*! @} */
+
+/*! @name RC32K_CTRL0 - RC32k Control 0 Register */
+/*! @{ */
+#define PMU_RC32K_CTRL0_RC32K_CODE_FR_EXT_MASK (0x3FFFU)
+#define PMU_RC32K_CTRL0_RC32K_CODE_FR_EXT_SHIFT (0U)
+/*! rc32k_code_fr_ext - External code In for frequency setting
+ */
+#define PMU_RC32K_CTRL0_RC32K_CODE_FR_EXT(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL0_RC32K_CODE_FR_EXT_SHIFT)) & PMU_RC32K_CTRL0_RC32K_CODE_FR_EXT_MASK)
+#define PMU_RC32K_CTRL0_RC32K_CAL_EN_MASK (0x4000U)
+#define PMU_RC32K_CTRL0_RC32K_CAL_EN_SHIFT (14U)
+/*! rc32k_cal_en - Enable calibration of 32k oscillator
+ */
+#define PMU_RC32K_CTRL0_RC32K_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL0_RC32K_CAL_EN_SHIFT)) & PMU_RC32K_CTRL0_RC32K_CAL_EN_MASK)
+#define PMU_RC32K_CTRL0_RC32K_PD_MASK (0x8000U)
+#define PMU_RC32K_CTRL0_RC32K_PD_SHIFT (15U)
+/*! rc32k_pd - Power down 32k oscillator
+ */
+#define PMU_RC32K_CTRL0_RC32K_PD(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL0_RC32K_PD_SHIFT)) & PMU_RC32K_CTRL0_RC32K_PD_MASK)
+/*! @} */
+
+/*! @name RC32K_CTRL1 - RC32k Control 1 Register */
+/*! @{ */
+#define PMU_RC32K_CTRL1_RC32K_CAL_DONE_MASK (0x1U)
+#define PMU_RC32K_CTRL1_RC32K_CAL_DONE_SHIFT (0U)
+/*! rc32k_cal_done - Asserts high when calibration is done
+ */
+#define PMU_RC32K_CTRL1_RC32K_CAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_CAL_DONE_SHIFT)) & PMU_RC32K_CTRL1_RC32K_CAL_DONE_MASK)
+#define PMU_RC32K_CTRL1_RC32K_RDY_MASK (0x2U)
+#define PMU_RC32K_CTRL1_RC32K_RDY_SHIFT (1U)
+/*! rc32k_rdy - Asserts high when 32k clock is ready upon pwrup
+ */
+#define PMU_RC32K_CTRL1_RC32K_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_RDY_SHIFT)) & PMU_RC32K_CTRL1_RC32K_RDY_MASK)
+#define PMU_RC32K_CTRL1_RC32K_MASK (0x4U)
+#define PMU_RC32K_CTRL1_RC32K_SHIFT (2U)
+/*! rc32k - RC32k
+ */
+#define PMU_RC32K_CTRL1_RC32K(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_SHIFT)) & PMU_RC32K_CTRL1_RC32K_MASK)
+#define PMU_RC32K_CTRL1_RC32K_CAL_INPROGRESS_MASK (0x8U)
+#define PMU_RC32K_CTRL1_RC32K_CAL_INPROGRESS_SHIFT (3U)
+/*! rc32k_cal_inprogress - Asserts high when calibration is in progress
+ */
+#define PMU_RC32K_CTRL1_RC32K_CAL_INPROGRESS(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_CAL_INPROGRESS_SHIFT)) & PMU_RC32K_CTRL1_RC32K_CAL_INPROGRESS_MASK)
+#define PMU_RC32K_CTRL1_RC32K_CODE_FR_CAL_MASK (0x3FFF0U)
+#define PMU_RC32K_CTRL1_RC32K_CODE_FR_CAL_SHIFT (4U)
+/*! rc32k_code_fr_cal - After calibration hold calibrated code
+ */
+#define PMU_RC32K_CTRL1_RC32K_CODE_FR_CAL(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_CODE_FR_CAL_SHIFT)) & PMU_RC32K_CTRL1_RC32K_CODE_FR_CAL_MASK)
+#define PMU_RC32K_CTRL1_RC32K_ALLOW_CAL_MASK (0x40000U)
+#define PMU_RC32K_CTRL1_RC32K_ALLOW_CAL_SHIFT (18U)
+/*! rc32k_allow_cal - Allow calibration to be performed (monitor system clock)
+ */
+#define PMU_RC32K_CTRL1_RC32K_ALLOW_CAL(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_ALLOW_CAL_SHIFT)) & PMU_RC32K_CTRL1_RC32K_ALLOW_CAL_MASK)
+#define PMU_RC32K_CTRL1_RC32K_CAL_DIV_MASK (0x380000U)
+#define PMU_RC32K_CTRL1_RC32K_CAL_DIV_SHIFT (19U)
+/*! rc32k_cal_div - Divider for the clock step during calibration
+ */
+#define PMU_RC32K_CTRL1_RC32K_CAL_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_CAL_DIV_SHIFT)) & PMU_RC32K_CTRL1_RC32K_CAL_DIV_MASK)
+#define PMU_RC32K_CTRL1_RC32K_REFCLK32K_MASK (0x400000U)
+#define PMU_RC32K_CTRL1_RC32K_REFCLK32K_SHIFT (22U)
+/*! rc32k_refclk32k - RC32k Reference Clock
+ */
+#define PMU_RC32K_CTRL1_RC32K_REFCLK32K(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_REFCLK32K_SHIFT)) & PMU_RC32K_CTRL1_RC32K_REFCLK32K_MASK)
+#define PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN_MASK (0x800000U)
+#define PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN_SHIFT (23U)
+/*! rc32k_ext_code_en - Allow external code in to go into the ckt
+ */
+#define PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN_SHIFT)) & PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN_MASK)
+/*! @} */
+
+/*! @name XTAL32K_CTRL - XTAL32k Control Register */
+/*! @{ */
+#define PMU_XTAL32K_CTRL_X32K_RDY_MASK (0x1U)
+#define PMU_XTAL32K_CTRL_X32K_RDY_SHIFT (0U)
+/*! x32k_rdy - Assert high when ready
+ */
+#define PMU_XTAL32K_CTRL_X32K_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_RDY_SHIFT)) & PMU_XTAL32K_CTRL_X32K_RDY_MASK)
+#define PMU_XTAL32K_CTRL_XCLK32K_MASK (0x2U)
+#define PMU_XTAL32K_CTRL_XCLK32K_SHIFT (1U)
+/*! xclk32k - xclk32k
+ */
+#define PMU_XTAL32K_CTRL_XCLK32K(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_XCLK32K_SHIFT)) & PMU_XTAL32K_CTRL_XCLK32K_MASK)
+#define PMU_XTAL32K_CTRL_X32K_STUP_ASSIST_MASK (0xCU)
+#define PMU_XTAL32K_CTRL_X32K_STUP_ASSIST_SHIFT (2U)
+/*! x32k_stup_assist - Use startup assist ckt for 32 kHz xosc
+ */
+#define PMU_XTAL32K_CTRL_X32K_STUP_ASSIST(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_STUP_ASSIST_SHIFT)) & PMU_XTAL32K_CTRL_X32K_STUP_ASSIST_MASK)
+#define PMU_XTAL32K_CTRL_X32K_TEST_EN_MASK (0x10U)
+#define PMU_XTAL32K_CTRL_X32K_TEST_EN_SHIFT (4U)
+/*! x32k_test_en - Test enabling for 32k xtal ckt
+ */
+#define PMU_XTAL32K_CTRL_X32K_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_TEST_EN_SHIFT)) & PMU_XTAL32K_CTRL_X32K_TEST_EN_MASK)
+#define PMU_XTAL32K_CTRL_X32K_TMODE_MASK (0x60U)
+#define PMU_XTAL32K_CTRL_X32K_TMODE_SHIFT (5U)
+/*! x32k_tmode - Test mode enabling for 32k xtal ckt
+ */
+#define PMU_XTAL32K_CTRL_X32K_TMODE(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_TMODE_SHIFT)) & PMU_XTAL32K_CTRL_X32K_TMODE_MASK)
+#define PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL_MASK (0x600U)
+#define PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL_SHIFT (9U)
+/*! x32k_vddxo_cntl - Control VDDXO level
+ */
+#define PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL_SHIFT)) & PMU_XTAL32K_CTRL_X32K_VDDXO_CNTL_MASK)
+#define PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_MASK (0x800U)
+#define PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_SHIFT (11U)
+/*! x32k_ext_osc_en - Enable external oscillator mode for outside clock
+ */
+#define PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_SHIFT)) & PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_MASK)
+#define PMU_XTAL32K_CTRL_X32K_EN_MASK (0x1000U)
+#define PMU_XTAL32K_CTRL_X32K_EN_SHIFT (12U)
+/*! x32k_en - Enable 32k oscillator
+ */
+#define PMU_XTAL32K_CTRL_X32K_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_EN_SHIFT)) & PMU_XTAL32K_CTRL_X32K_EN_MASK)
+#define PMU_XTAL32K_CTRL_X32K_DLY_SEL_MASK (0x6000U)
+#define PMU_XTAL32K_CTRL_X32K_DLY_SEL_SHIFT (13U)
+/*! x32k_dly_sel - 32k Delay Select
+ */
+#define PMU_XTAL32K_CTRL_X32K_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_XTAL32K_CTRL_X32K_DLY_SEL_SHIFT)) & PMU_XTAL32K_CTRL_X32K_DLY_SEL_MASK)
+/*! @} */
+
+/*! @name PMIP_CMP_CTRL - PMIP Comparator Control Register */
+/*! @{ */
+#define PMU_PMIP_CMP_CTRL_COMP_OUT_MASK (0x1U)
+#define PMU_PMIP_CMP_CTRL_COMP_OUT_SHIFT (0U)
+/*! comp_out - Output of AON domain comparator
+ */
+#define PMU_PMIP_CMP_CTRL_COMP_OUT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_CMP_CTRL_COMP_OUT_SHIFT)) & PMU_PMIP_CMP_CTRL_COMP_OUT_MASK)
+#define PMU_PMIP_CMP_CTRL_COMP_RDY_MASK (0x2U)
+#define PMU_PMIP_CMP_CTRL_COMP_RDY_SHIFT (1U)
+/*! comp_rdy - Ready to use AON domain comparator
+ */
+#define PMU_PMIP_CMP_CTRL_COMP_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_CMP_CTRL_COMP_RDY_SHIFT)) & PMU_PMIP_CMP_CTRL_COMP_RDY_MASK)
+#define PMU_PMIP_CMP_CTRL_COMP_REF_SEL_MASK (0x1CU)
+#define PMU_PMIP_CMP_CTRL_COMP_REF_SEL_SHIFT (2U)
+/*! comp_ref_sel - Select comparator reference for single-ended mode
+ */
+#define PMU_PMIP_CMP_CTRL_COMP_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_CMP_CTRL_COMP_REF_SEL_SHIFT)) & PMU_PMIP_CMP_CTRL_COMP_REF_SEL_MASK)
+#define PMU_PMIP_CMP_CTRL_COMP_DIFF_EN_MASK (0x20U)
+#define PMU_PMIP_CMP_CTRL_COMP_DIFF_EN_SHIFT (5U)
+/*! comp_diff_en - Enable Differential mode for AON comparator
+ */
+#define PMU_PMIP_CMP_CTRL_COMP_DIFF_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_CMP_CTRL_COMP_DIFF_EN_SHIFT)) & PMU_PMIP_CMP_CTRL_COMP_DIFF_EN_MASK)
+#define PMU_PMIP_CMP_CTRL_COMP_EN_MASK (0x40U)
+#define PMU_PMIP_CMP_CTRL_COMP_EN_SHIFT (6U)
+/*! comp_en - Enable AON domain comparator
+ */
+#define PMU_PMIP_CMP_CTRL_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_CMP_CTRL_COMP_EN_SHIFT)) & PMU_PMIP_CMP_CTRL_COMP_EN_MASK)
+#define PMU_PMIP_CMP_CTRL_COMP_HYST_MASK (0x180U)
+#define PMU_PMIP_CMP_CTRL_COMP_HYST_SHIFT (7U)
+/*! comp_hyst - Control of comparator hysteresis
+ */
+#define PMU_PMIP_CMP_CTRL_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_CMP_CTRL_COMP_HYST_SHIFT)) & PMU_PMIP_CMP_CTRL_COMP_HYST_MASK)
+#define PMU_PMIP_CMP_CTRL_CAU_REF_EN_MASK (0x200U)
+#define PMU_PMIP_CMP_CTRL_CAU_REF_EN_SHIFT (9U)
+/*! cau_ref_en - CAU Reference Enable
+ */
+#define PMU_PMIP_CMP_CTRL_CAU_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_CMP_CTRL_CAU_REF_EN_SHIFT)) & PMU_PMIP_CMP_CTRL_CAU_REF_EN_MASK)
+/*! @} */
+
+/*! @name PMIP_BRNDET_AV18 - PMIP Brownout AV18 Register */
+/*! @{ */
+#define PMU_PMIP_BRNDET_AV18_DEL_AV18_SEL_MASK (0x3U)
+#define PMU_PMIP_BRNDET_AV18_DEL_AV18_SEL_SHIFT (0U)
+/*! del_av18_sel - Control of rdygen_av18 rising edge delay circiut
+ */
+#define PMU_PMIP_BRNDET_AV18_DEL_AV18_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_DEL_AV18_SEL_SHIFT)) & PMU_PMIP_BRNDET_AV18_DEL_AV18_SEL_MASK)
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_HYST_MASK (0xCU)
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_HYST_SHIFT (2U)
+/*! ldo_aon_av18_hyst - Control of ldo_aon_av18 hysteresis
+ */
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_HYST_SHIFT)) & PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_HYST_MASK)
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_SEL_MASK (0x70U)
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_SEL_SHIFT (4U)
+/*! ldo_aon_av18_sel - Select output voltage of ldo_aon_av18
+ */
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_SEL_SHIFT)) & PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_SEL_MASK)
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_EN_MASK (0x80U)
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_EN_SHIFT (7U)
+/*! ldo_aon_av18_en - Enable ldo_aon_av18
+ */
+#define PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_EN_SHIFT)) & PMU_PMIP_BRNDET_AV18_LDO_AON_AV18_EN_MASK)
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_OUT_MASK (0x100U)
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_OUT_SHIFT (8U)
+/*! brndet_av18_out - Assert high if av18 brnout happened
+ */
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_OUT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_BRNDET_AV18_OUT_SHIFT)) & PMU_PMIP_BRNDET_AV18_BRNDET_AV18_OUT_MASK)
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_RDY_MASK (0x200U)
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_RDY_SHIFT (9U)
+/*! brndet_av18_rdy - Assert high if av18 brnout is rdy --> out can be taken
+ */
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_BRNDET_AV18_RDY_SHIFT)) & PMU_PMIP_BRNDET_AV18_BRNDET_AV18_RDY_MASK)
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_FILT_MASK (0xC00U)
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_FILT_SHIFT (10U)
+/*! brndet_av18_filt - Select filtering level for av18 pulse to av18 brndet
+ */
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_FILT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_BRNDET_AV18_FILT_SHIFT)) & PMU_PMIP_BRNDET_AV18_BRNDET_AV18_FILT_MASK)
+#define PMU_PMIP_BRNDET_AV18_BRNHYST_AV18_CNTL_MASK (0x3000U)
+#define PMU_PMIP_BRNDET_AV18_BRNHYST_AV18_CNTL_SHIFT (12U)
+/*! brnhyst_av18_cntl - Control of av18 brown-out detector hysteresis
+ */
+#define PMU_PMIP_BRNDET_AV18_BRNHYST_AV18_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_BRNHYST_AV18_CNTL_SHIFT)) & PMU_PMIP_BRNDET_AV18_BRNHYST_AV18_CNTL_MASK)
+#define PMU_PMIP_BRNDET_AV18_BRNTRIG_AV18_CNTL_MASK (0x1C000U)
+#define PMU_PMIP_BRNDET_AV18_BRNTRIG_AV18_CNTL_SHIFT (14U)
+/*! brntrig_av18_cntl - Control trigger voltage of av18 brndet
+ */
+#define PMU_PMIP_BRNDET_AV18_BRNTRIG_AV18_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_BRNTRIG_AV18_CNTL_SHIFT)) & PMU_PMIP_BRNDET_AV18_BRNTRIG_AV18_CNTL_MASK)
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_EN_MASK (0x20000U)
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_EN_SHIFT (17U)
+/*! brndet_av18_en - Enable av18 brown-out detector
+ */
+#define PMU_PMIP_BRNDET_AV18_BRNDET_AV18_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_BRNDET_AV18_EN_SHIFT)) & PMU_PMIP_BRNDET_AV18_BRNDET_AV18_EN_MASK)
+#define PMU_PMIP_BRNDET_AV18_DEL_AV18_HYST_MASK (0xC0000U)
+#define PMU_PMIP_BRNDET_AV18_DEL_AV18_HYST_SHIFT (18U)
+/*! del_av18_hyst - Del av18 Hysteresis
+ */
+#define PMU_PMIP_BRNDET_AV18_DEL_AV18_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_AV18_DEL_AV18_HYST_SHIFT)) & PMU_PMIP_BRNDET_AV18_DEL_AV18_HYST_MASK)
+/*! @} */
+
+/*! @name PMIP_BRNDET_VBAT - PMIP Brownout VBAT Register */
+/*! @{ */
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_OUT_MASK (0x1U)
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_OUT_SHIFT (0U)
+/*! mon_vbat_out - Assert high if vbat is lower than ~2.8V trigger level
+ */
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_OUT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_MON_VBAT_OUT_SHIFT)) & PMU_PMIP_BRNDET_VBAT_MON_VBAT_OUT_MASK)
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_RDY_MASK (0x2U)
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_RDY_SHIFT (1U)
+/*! mon_vbat_rdy - Assert high if vbat monitor is rdy--> out can be taken
+ */
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_MON_VBAT_RDY_SHIFT)) & PMU_PMIP_BRNDET_VBAT_MON_VBAT_RDY_MASK)
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_FILT_MASK (0xCU)
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_FILT_SHIFT (2U)
+/*! mon_vbat_filt - Select filtering level for vbat pulse to vbat monitor
+ */
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_FILT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_MON_VBAT_FILT_SHIFT)) & PMU_PMIP_BRNDET_VBAT_MON_VBAT_FILT_MASK)
+#define PMU_PMIP_BRNDET_VBAT_MONHYST_VBAT_CNTL_MASK (0x30U)
+#define PMU_PMIP_BRNDET_VBAT_MONHYST_VBAT_CNTL_SHIFT (4U)
+/*! monhyst_vbat_cntl - Control of vbat monitor hysteresis
+ */
+#define PMU_PMIP_BRNDET_VBAT_MONHYST_VBAT_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_MONHYST_VBAT_CNTL_SHIFT)) & PMU_PMIP_BRNDET_VBAT_MONHYST_VBAT_CNTL_MASK)
+#define PMU_PMIP_BRNDET_VBAT_MONTRIG_VBAT_CNTL_MASK (0x1C0U)
+#define PMU_PMIP_BRNDET_VBAT_MONTRIG_VBAT_CNTL_SHIFT (6U)
+/*! montrig_vbat_cntl - Control trigger voltage of vbat monitor (around 2.8V)
+ */
+#define PMU_PMIP_BRNDET_VBAT_MONTRIG_VBAT_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_MONTRIG_VBAT_CNTL_SHIFT)) & PMU_PMIP_BRNDET_VBAT_MONTRIG_VBAT_CNTL_MASK)
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_EN_MASK (0x200U)
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_EN_SHIFT (9U)
+/*! mon_vbat_en - Enable vbat monitor
+ */
+#define PMU_PMIP_BRNDET_VBAT_MON_VBAT_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_MON_VBAT_EN_SHIFT)) & PMU_PMIP_BRNDET_VBAT_MON_VBAT_EN_MASK)
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_OUT_MASK (0x400U)
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_OUT_SHIFT (10U)
+/*! brndet_vbat_out - Assert high if vbat brnout happened
+ */
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_OUT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_OUT_SHIFT)) & PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_OUT_MASK)
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_RDY_MASK (0x800U)
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_RDY_SHIFT (11U)
+/*! brndet_vbat_rdy - Assert high if vbat brnout is rdy--> out can be taken
+ */
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_RDY_SHIFT)) & PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_RDY_MASK)
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_FILT_MASK (0x3000U)
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_FILT_SHIFT (12U)
+/*! brndet_vbat_filt - Select filtering level for vbat pulse to vbat brndet
+ */
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_FILT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_FILT_SHIFT)) & PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_FILT_MASK)
+#define PMU_PMIP_BRNDET_VBAT_BRNHYST_VBAT_CNTL_MASK (0xC000U)
+#define PMU_PMIP_BRNDET_VBAT_BRNHYST_VBAT_CNTL_SHIFT (14U)
+/*! brnhyst_vbat_cntl - Control of vbat brown-out detector hysteresis
+ */
+#define PMU_PMIP_BRNDET_VBAT_BRNHYST_VBAT_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_BRNHYST_VBAT_CNTL_SHIFT)) & PMU_PMIP_BRNDET_VBAT_BRNHYST_VBAT_CNTL_MASK)
+#define PMU_PMIP_BRNDET_VBAT_BRNTRIG_VBAT_CNTL_MASK (0x70000U)
+#define PMU_PMIP_BRNDET_VBAT_BRNTRIG_VBAT_CNTL_SHIFT (16U)
+/*! brntrig_vbat_cntl - Control trigger voltage of vbat brndet
+ */
+#define PMU_PMIP_BRNDET_VBAT_BRNTRIG_VBAT_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_BRNTRIG_VBAT_CNTL_SHIFT)) & PMU_PMIP_BRNDET_VBAT_BRNTRIG_VBAT_CNTL_MASK)
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_EN_MASK (0x80000U)
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_EN_SHIFT (19U)
+/*! brndet_vbat_en - Enable vbat brown-out detector
+ */
+#define PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_EN_SHIFT)) & PMU_PMIP_BRNDET_VBAT_BRNDET_VBAT_EN_MASK)
+/*! @} */
+
+/*! @name PMIP_BRNDET_V12 - PMIP Brownout V12 Register */
+/*! @{ */
+#define PMU_PMIP_BRNDET_V12_LDO_AON_V12_HYST_MASK (0x3U)
+#define PMU_PMIP_BRNDET_V12_LDO_AON_V12_HYST_SHIFT (0U)
+/*! ldo_aon_v12_hyst - Control of ldo_aon_v12 hysteresis
+ */
+#define PMU_PMIP_BRNDET_V12_LDO_AON_V12_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_V12_LDO_AON_V12_HYST_SHIFT)) & PMU_PMIP_BRNDET_V12_LDO_AON_V12_HYST_MASK)
+#define PMU_PMIP_BRNDET_V12_LDO_AON_V12_SEL_MASK (0x1CU)
+#define PMU_PMIP_BRNDET_V12_LDO_AON_V12_SEL_SHIFT (2U)
+/*! ldo_aon_v12_sel - Select output voltage of ldo_aon_v12
+ */
+#define PMU_PMIP_BRNDET_V12_LDO_AON_V12_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_V12_LDO_AON_V12_SEL_SHIFT)) & PMU_PMIP_BRNDET_V12_LDO_AON_V12_SEL_MASK)
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_OUT_MASK (0x20U)
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_OUT_SHIFT (5U)
+/*! brndet_v12_out - Assert high if v12 brnout happened
+ */
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_OUT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_V12_BRNDET_V12_OUT_SHIFT)) & PMU_PMIP_BRNDET_V12_BRNDET_V12_OUT_MASK)
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_RDY_MASK (0x40U)
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_RDY_SHIFT (6U)
+/*! brndet_v12_rdy - Assert high if v12 brnout is rdy--> out can be taken
+ */
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_V12_BRNDET_V12_RDY_SHIFT)) & PMU_PMIP_BRNDET_V12_BRNDET_V12_RDY_MASK)
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_FILT_MASK (0x180U)
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_FILT_SHIFT (7U)
+/*! brndet_v12_filt - Select filtering level for v12 pulse to v12 brndet
+ */
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_FILT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_V12_BRNDET_V12_FILT_SHIFT)) & PMU_PMIP_BRNDET_V12_BRNDET_V12_FILT_MASK)
+#define PMU_PMIP_BRNDET_V12_BRNHYST_V12_CNTL_MASK (0x600U)
+#define PMU_PMIP_BRNDET_V12_BRNHYST_V12_CNTL_SHIFT (9U)
+/*! brnhyst_v12_cntl - Control of v12 brown-out detector hysteresis
+ */
+#define PMU_PMIP_BRNDET_V12_BRNHYST_V12_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_V12_BRNHYST_V12_CNTL_SHIFT)) & PMU_PMIP_BRNDET_V12_BRNHYST_V12_CNTL_MASK)
+#define PMU_PMIP_BRNDET_V12_BRNTRIG_V12_CNTL_MASK (0x3800U)
+#define PMU_PMIP_BRNDET_V12_BRNTRIG_V12_CNTL_SHIFT (11U)
+/*! brntrig_v12_cntl - Control trigger voltage of v12 brndet
+ */
+#define PMU_PMIP_BRNDET_V12_BRNTRIG_V12_CNTL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_V12_BRNTRIG_V12_CNTL_SHIFT)) & PMU_PMIP_BRNDET_V12_BRNTRIG_V12_CNTL_MASK)
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_EN_MASK (0x4000U)
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_EN_SHIFT (14U)
+/*! brndet_v12_en - Enable v12 brown-out detector
+ */
+#define PMU_PMIP_BRNDET_V12_BRNDET_V12_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_BRNDET_V12_BRNDET_V12_EN_SHIFT)) & PMU_PMIP_BRNDET_V12_BRNDET_V12_EN_MASK)
+/*! @} */
+
+/*! @name PMIP_LDO_CTRL - PMIP LDO Control Register */
+/*! @{ */
+#define PMU_PMIP_LDO_CTRL_LDO_V12_REF_SEL_MASK (0x1U)
+#define PMU_PMIP_LDO_CTRL_LDO_V12_REF_SEL_SHIFT (0U)
+/*! ldo_v12_ref_sel - ldo v12 reference select
+ * 0b0..from igen
+ * 0b1..directly from bandgap
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_V12_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_V12_REF_SEL_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_V12_REF_SEL_MASK)
+#define PMU_PMIP_LDO_CTRL_LDO_V12_SOFTST_EN_MASK (0x2U)
+#define PMU_PMIP_LDO_CTRL_LDO_V12_SOFTST_EN_SHIFT (1U)
+/*! ldo_v12_softst_en - Enable soft-start for ldo_v12
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_V12_SOFTST_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_V12_SOFTST_EN_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_V12_SOFTST_EN_MASK)
+#define PMU_PMIP_LDO_CTRL_LDO_V12_VOUT_SEL_MASK (0x1CU)
+#define PMU_PMIP_LDO_CTRL_LDO_V12_VOUT_SEL_SHIFT (2U)
+/*! ldo_v12_vout_sel - Select output voltage for v12
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_V12_VOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_V12_VOUT_SEL_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_V12_VOUT_SEL_MASK)
+#define PMU_PMIP_LDO_CTRL_LDO_V12_EN_MASK (0x20U)
+#define PMU_PMIP_LDO_CTRL_LDO_V12_EN_SHIFT (5U)
+/*! ldo_v12_en - Enable ldo_v12
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_V12_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_V12_EN_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_V12_EN_MASK)
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_PWRSW_EN_MASK (0x40U)
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_PWRSW_EN_SHIFT (6U)
+/*! ldo_av18_pwrsw_en - Enable bypass (power switch mode) for ldo_av18
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_PWRSW_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_AV18_PWRSW_EN_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_AV18_PWRSW_EN_MASK)
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_SOFTST_EN_MASK (0x80U)
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_SOFTST_EN_SHIFT (7U)
+/*! ldo_av18_softst_en - Enable soft-start for ldo_av18
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_SOFTST_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_AV18_SOFTST_EN_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_AV18_SOFTST_EN_MASK)
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_VOUT_SEL_MASK (0x700U)
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_VOUT_SEL_SHIFT (8U)
+/*! ldo_av18_vout_sel - Select output voltage for ldo_av18
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_VOUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_AV18_VOUT_SEL_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_AV18_VOUT_SEL_MASK)
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_EN_MASK (0x800U)
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_EN_SHIFT (11U)
+/*! ldo_av18_en - Enable ldo_av18
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_AV18_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_AV18_EN_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_AV18_EN_MASK)
+#define PMU_PMIP_LDO_CTRL_LDO_VFL_PWRSW_EN_MASK (0x1000U)
+#define PMU_PMIP_LDO_CTRL_LDO_VFL_PWRSW_EN_SHIFT (12U)
+/*! ldo_vfl_pwrsw_en - Enable bypass (power switch mode) for ldo_vfl
+ */
+#define PMU_PMIP_LDO_CTRL_LDO_VFL_PWRSW_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_LDO_CTRL_LDO_VFL_PWRSW_EN_SHIFT)) & PMU_PMIP_LDO_CTRL_LDO_VFL_PWRSW_EN_MASK)
+/*! @} */
+
+/*! @name PERI_CLK_SRC - PERI Clock Source Register */
+/*! @{ */
+#define PMU_PERI_CLK_SRC_SSP0_AUDIO_SEL_MASK (0x1U)
+#define PMU_PERI_CLK_SRC_SSP0_AUDIO_SEL_SHIFT (0U)
+/*! ssp0_audio_sel - SSP0 Audio Select
+ * 0b0..divided by system clock
+ * 0b1..audio PLL clock
+ */
+#define PMU_PERI_CLK_SRC_SSP0_AUDIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_SSP0_AUDIO_SEL_SHIFT)) & PMU_PERI_CLK_SRC_SSP0_AUDIO_SEL_MASK)
+#define PMU_PERI_CLK_SRC_SSP1_AUDIO_SEL_MASK (0x2U)
+#define PMU_PERI_CLK_SRC_SSP1_AUDIO_SEL_SHIFT (1U)
+/*! ssp1_audio_sel - SSP1 Audio Select
+ * 0b0..divided by system clock
+ * 0b1..audio PLL clock
+ */
+#define PMU_PERI_CLK_SRC_SSP1_AUDIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_SSP1_AUDIO_SEL_SHIFT)) & PMU_PERI_CLK_SRC_SSP1_AUDIO_SEL_MASK)
+#define PMU_PERI_CLK_SRC_SSP2_AUDIO_SEL_MASK (0x4U)
+#define PMU_PERI_CLK_SRC_SSP2_AUDIO_SEL_SHIFT (2U)
+/*! ssp2_audio_sel - SSP2 Audio Select
+ * 0b0..divided by system clock
+ * 0b1..audio PLL clock
+ */
+#define PMU_PERI_CLK_SRC_SSP2_AUDIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_SSP2_AUDIO_SEL_SHIFT)) & PMU_PERI_CLK_SRC_SSP2_AUDIO_SEL_MASK)
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL0_MASK (0x10U)
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL0_SHIFT (4U)
+/*! gpt_int_sel0 - GPT Int Select 0
+ */
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL0(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_GPT_INT_SEL0_SHIFT)) & PMU_PERI_CLK_SRC_GPT_INT_SEL0_MASK)
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL1_MASK (0x20U)
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL1_SHIFT (5U)
+/*! gpt_int_sel1 - GPT Int Select 1
+ */
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL1(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_GPT_INT_SEL1_SHIFT)) & PMU_PERI_CLK_SRC_GPT_INT_SEL1_MASK)
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL2_MASK (0x40U)
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL2_SHIFT (6U)
+/*! gpt_int_sel2 - GPT Int Select 2
+ */
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL2(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_GPT_INT_SEL2_SHIFT)) & PMU_PERI_CLK_SRC_GPT_INT_SEL2_MASK)
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL3_MASK (0x80U)
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL3_SHIFT (7U)
+/*! gpt_int_sel3 - GPT Int Select 3
+ */
+#define PMU_PERI_CLK_SRC_GPT_INT_SEL3(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_GPT_INT_SEL3_SHIFT)) & PMU_PERI_CLK_SRC_GPT_INT_SEL3_MASK)
+#define PMU_PERI_CLK_SRC_GPT0_INT_SEL_MASK (0x100U)
+#define PMU_PERI_CLK_SRC_GPT0_INT_SEL_SHIFT (8U)
+/*! gpt0_int_sel - GPT0 Int Select
+ */
+#define PMU_PERI_CLK_SRC_GPT0_INT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_GPT0_INT_SEL_SHIFT)) & PMU_PERI_CLK_SRC_GPT0_INT_SEL_MASK)
+#define PMU_PERI_CLK_SRC_GPT1_INT_SEL_MASK (0x200U)
+#define PMU_PERI_CLK_SRC_GPT1_INT_SEL_SHIFT (9U)
+/*! gpt1_int_sel - GPT1 Int Select
+ */
+#define PMU_PERI_CLK_SRC_GPT1_INT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_GPT1_INT_SEL_SHIFT)) & PMU_PERI_CLK_SRC_GPT1_INT_SEL_MASK)
+#define PMU_PERI_CLK_SRC_GPT2_INT_SEL_MASK (0x400U)
+#define PMU_PERI_CLK_SRC_GPT2_INT_SEL_SHIFT (10U)
+/*! gpt2_int_sel - GPT2 Int Select
+ */
+#define PMU_PERI_CLK_SRC_GPT2_INT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_GPT2_INT_SEL_SHIFT)) & PMU_PERI_CLK_SRC_GPT2_INT_SEL_MASK)
+#define PMU_PERI_CLK_SRC_GPT3_INT_SEL_MASK (0x800U)
+#define PMU_PERI_CLK_SRC_GPT3_INT_SEL_SHIFT (11U)
+/*! gpt3_int_sel - GPT3 Int Select
+ */
+#define PMU_PERI_CLK_SRC_GPT3_INT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_GPT3_INT_SEL_SHIFT)) & PMU_PERI_CLK_SRC_GPT3_INT_SEL_MASK)
+#define PMU_PERI_CLK_SRC_PDM_AUDIO_SEL_MASK (0x1000U)
+#define PMU_PERI_CLK_SRC_PDM_AUDIO_SEL_SHIFT (12U)
+/*! pdm_audio_sel - PDM Audio Select
+ * 0b0..divided by system clock
+ * 0b1..audio PLL clock
+ */
+#define PMU_PERI_CLK_SRC_PDM_AUDIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_PDM_AUDIO_SEL_SHIFT)) & PMU_PERI_CLK_SRC_PDM_AUDIO_SEL_MASK)
+#define PMU_PERI_CLK_SRC_USIM_AUDIO_SEL_MASK (0x2000U)
+#define PMU_PERI_CLK_SRC_USIM_AUDIO_SEL_SHIFT (13U)
+/*! usim_audio_sel - USIM Audio Select
+ * 0b0..divided by system clock
+ * 0b1..audio PLL clock
+ */
+#define PMU_PERI_CLK_SRC_USIM_AUDIO_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI_CLK_SRC_USIM_AUDIO_SEL_SHIFT)) & PMU_PERI_CLK_SRC_USIM_AUDIO_SEL_MASK)
+/*! @} */
+
+/*! @name PMIP_RSVD - Unused Register */
+/*! @{ */
+#define PMU_PMIP_RSVD_RESERVE_IN_MASK (0x3FFU)
+#define PMU_PMIP_RSVD_RESERVE_IN_SHIFT (0U)
+/*! reserve_in - Unused. Do not change the reset value.
+ */
+#define PMU_PMIP_RSVD_RESERVE_IN(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_RSVD_RESERVE_IN_SHIFT)) & PMU_PMIP_RSVD_RESERVE_IN_MASK)
+#define PMU_PMIP_RSVD_RESERVE_OUT_MASK (0xFC00U)
+#define PMU_PMIP_RSVD_RESERVE_OUT_SHIFT (10U)
+/*! reserve_out - Unused. Do not change the reset value.
+ */
+#define PMU_PMIP_RSVD_RESERVE_OUT(x) (((uint32_t)(((uint32_t)(x)) << PMU_PMIP_RSVD_RESERVE_OUT_SHIFT)) & PMU_PMIP_RSVD_RESERVE_OUT_MASK)
+/*! @} */
+
+/*! @name GPT0_CTRL - GPT0 Control Register */
+/*! @{ */
+#define PMU_GPT0_CTRL_GPT0_CLK_DIV_MASK (0x3FU)
+#define PMU_GPT0_CTRL_GPT0_CLK_DIV_SHIFT (0U)
+/*! gpt0_clk_div - clock divisor
+ */
+#define PMU_GPT0_CTRL_GPT0_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT0_CTRL_GPT0_CLK_DIV_SHIFT)) & PMU_GPT0_CTRL_GPT0_CLK_DIV_MASK)
+#define PMU_GPT0_CTRL_GPT0_FREQ_CHANGE_MASK (0x40U)
+#define PMU_GPT0_CTRL_GPT0_FREQ_CHANGE_SHIFT (6U)
+/*! gpt0_freq_change - frequency change enable
+ */
+#define PMU_GPT0_CTRL_GPT0_FREQ_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT0_CTRL_GPT0_FREQ_CHANGE_SHIFT)) & PMU_GPT0_CTRL_GPT0_FREQ_CHANGE_MASK)
+#define PMU_GPT0_CTRL_GPT0_CLK_SEL1_MASK (0x180U)
+#define PMU_GPT0_CTRL_GPT0_CLK_SEL1_SHIFT (7U)
+/*! gpt0_clk_sel1 - select signal for mux after frequency divisor
+ */
+#define PMU_GPT0_CTRL_GPT0_CLK_SEL1(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT0_CTRL_GPT0_CLK_SEL1_SHIFT)) & PMU_GPT0_CTRL_GPT0_CLK_SEL1_MASK)
+#define PMU_GPT0_CTRL_GPT0_CLK_SEL0_MASK (0x600U)
+#define PMU_GPT0_CTRL_GPT0_CLK_SEL0_SHIFT (9U)
+/*! gpt0_clk_sel0 - select signal for mux before frequency divisor
+ */
+#define PMU_GPT0_CTRL_GPT0_CLK_SEL0(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT0_CTRL_GPT0_CLK_SEL0_SHIFT)) & PMU_GPT0_CTRL_GPT0_CLK_SEL0_MASK)
+/*! @} */
+
+/*! @name GPT1_CTRL - GPT1 Control Register */
+/*! @{ */
+#define PMU_GPT1_CTRL_GPT1_CLK_DIV_MASK (0x3FU)
+#define PMU_GPT1_CTRL_GPT1_CLK_DIV_SHIFT (0U)
+/*! gpt1_clk_div - clock divisor
+ */
+#define PMU_GPT1_CTRL_GPT1_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT1_CTRL_GPT1_CLK_DIV_SHIFT)) & PMU_GPT1_CTRL_GPT1_CLK_DIV_MASK)
+#define PMU_GPT1_CTRL_GPT1_FREQ_CHANGE_MASK (0x40U)
+#define PMU_GPT1_CTRL_GPT1_FREQ_CHANGE_SHIFT (6U)
+/*! gpt1_freq_change - frequency change enable
+ */
+#define PMU_GPT1_CTRL_GPT1_FREQ_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT1_CTRL_GPT1_FREQ_CHANGE_SHIFT)) & PMU_GPT1_CTRL_GPT1_FREQ_CHANGE_MASK)
+#define PMU_GPT1_CTRL_GPT1_CLK_SEL1_MASK (0x180U)
+#define PMU_GPT1_CTRL_GPT1_CLK_SEL1_SHIFT (7U)
+/*! gpt1_clk_sel1 - select signal for mux after frequency divisor
+ */
+#define PMU_GPT1_CTRL_GPT1_CLK_SEL1(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT1_CTRL_GPT1_CLK_SEL1_SHIFT)) & PMU_GPT1_CTRL_GPT1_CLK_SEL1_MASK)
+#define PMU_GPT1_CTRL_GPT1_CLK_SEL0_MASK (0x600U)
+#define PMU_GPT1_CTRL_GPT1_CLK_SEL0_SHIFT (9U)
+/*! gpt1_clk_sel0 - select signal for mux before frequency divisor
+ */
+#define PMU_GPT1_CTRL_GPT1_CLK_SEL0(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT1_CTRL_GPT1_CLK_SEL0_SHIFT)) & PMU_GPT1_CTRL_GPT1_CLK_SEL0_MASK)
+/*! @} */
+
+/*! @name GPT2_CTRL - GPT2 Control Register */
+/*! @{ */
+#define PMU_GPT2_CTRL_GPT2_CLK_DIV_MASK (0x3FU)
+#define PMU_GPT2_CTRL_GPT2_CLK_DIV_SHIFT (0U)
+/*! gpt2_clk_div - clock divisor
+ */
+#define PMU_GPT2_CTRL_GPT2_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT2_CTRL_GPT2_CLK_DIV_SHIFT)) & PMU_GPT2_CTRL_GPT2_CLK_DIV_MASK)
+#define PMU_GPT2_CTRL_GPT2_FREQ_CHANGE_MASK (0x40U)
+#define PMU_GPT2_CTRL_GPT2_FREQ_CHANGE_SHIFT (6U)
+/*! gpt2_freq_change - frequency change enable
+ */
+#define PMU_GPT2_CTRL_GPT2_FREQ_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT2_CTRL_GPT2_FREQ_CHANGE_SHIFT)) & PMU_GPT2_CTRL_GPT2_FREQ_CHANGE_MASK)
+#define PMU_GPT2_CTRL_GPT2_CLK_SEL1_MASK (0x180U)
+#define PMU_GPT2_CTRL_GPT2_CLK_SEL1_SHIFT (7U)
+/*! gpt2_clk_sel1 - select signal for mux after frequency divisor
+ */
+#define PMU_GPT2_CTRL_GPT2_CLK_SEL1(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT2_CTRL_GPT2_CLK_SEL1_SHIFT)) & PMU_GPT2_CTRL_GPT2_CLK_SEL1_MASK)
+#define PMU_GPT2_CTRL_GPT2_CLK_SEL0_MASK (0x600U)
+#define PMU_GPT2_CTRL_GPT2_CLK_SEL0_SHIFT (9U)
+/*! gpt2_clk_sel0 - select signal for mux before frequency divisor
+ */
+#define PMU_GPT2_CTRL_GPT2_CLK_SEL0(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT2_CTRL_GPT2_CLK_SEL0_SHIFT)) & PMU_GPT2_CTRL_GPT2_CLK_SEL0_MASK)
+/*! @} */
+
+/*! @name GPT3_CTRL - GPT3 Control Register */
+/*! @{ */
+#define PMU_GPT3_CTRL_GPT3_CLK_DIV_MASK (0x3FU)
+#define PMU_GPT3_CTRL_GPT3_CLK_DIV_SHIFT (0U)
+/*! gpt3_clk_div - clock divisor
+ */
+#define PMU_GPT3_CTRL_GPT3_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT3_CTRL_GPT3_CLK_DIV_SHIFT)) & PMU_GPT3_CTRL_GPT3_CLK_DIV_MASK)
+#define PMU_GPT3_CTRL_GPT3_FREQ_CHANGE_MASK (0x40U)
+#define PMU_GPT3_CTRL_GPT3_FREQ_CHANGE_SHIFT (6U)
+/*! gpt3_freq_change - frequency change enable
+ */
+#define PMU_GPT3_CTRL_GPT3_FREQ_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT3_CTRL_GPT3_FREQ_CHANGE_SHIFT)) & PMU_GPT3_CTRL_GPT3_FREQ_CHANGE_MASK)
+#define PMU_GPT3_CTRL_GPT3_CLK_SEL1_MASK (0x180U)
+#define PMU_GPT3_CTRL_GPT3_CLK_SEL1_SHIFT (7U)
+/*! gpt3_clk_sel1 - select signal for mux after frequency divisor
+ */
+#define PMU_GPT3_CTRL_GPT3_CLK_SEL1(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT3_CTRL_GPT3_CLK_SEL1_SHIFT)) & PMU_GPT3_CTRL_GPT3_CLK_SEL1_MASK)
+#define PMU_GPT3_CTRL_GPT3_CLK_SEL0_MASK (0x600U)
+#define PMU_GPT3_CTRL_GPT3_CLK_SEL0_SHIFT (9U)
+/*! gpt3_clk_sel0 - select signal for mux before frequency divisor
+ */
+#define PMU_GPT3_CTRL_GPT3_CLK_SEL0(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPT3_CTRL_GPT3_CLK_SEL0_SHIFT)) & PMU_GPT3_CTRL_GPT3_CLK_SEL0_MASK)
+/*! @} */
+
+/*! @name WAKEUP_EDGE_DETECT - Wakeup Edge Detect Register */
+/*! @{ */
+#define PMU_WAKEUP_EDGE_DETECT_WAKEUP0_MASK (0x1U)
+#define PMU_WAKEUP_EDGE_DETECT_WAKEUP0_SHIFT (0U)
+/*! wakeup0 - external pin0 wakeup_edge_detect
+ */
+#define PMU_WAKEUP_EDGE_DETECT_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_EDGE_DETECT_WAKEUP0_SHIFT)) & PMU_WAKEUP_EDGE_DETECT_WAKEUP0_MASK)
+#define PMU_WAKEUP_EDGE_DETECT_WAKEUP1_MASK (0x2U)
+#define PMU_WAKEUP_EDGE_DETECT_WAKEUP1_SHIFT (1U)
+/*! wakeup1 - external pin1 wakeup_edge_detect
+ */
+#define PMU_WAKEUP_EDGE_DETECT_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_EDGE_DETECT_WAKEUP1_SHIFT)) & PMU_WAKEUP_EDGE_DETECT_WAKEUP1_MASK)
+/*! @} */
+
+/*! @name AON_CLK_CTRL - AON Clock Control Register */
+/*! @{ */
+#define PMU_AON_CLK_CTRL_PMU_CLK_DIV_MASK (0xFU)
+#define PMU_AON_CLK_CTRL_PMU_CLK_DIV_SHIFT (0U)
+/*! pmu_clk_div - PMU clock divisor
+ */
+#define PMU_AON_CLK_CTRL_PMU_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_AON_CLK_CTRL_PMU_CLK_DIV_SHIFT)) & PMU_AON_CLK_CTRL_PMU_CLK_DIV_MASK)
+#define PMU_AON_CLK_CTRL_RTC_CLK_EN_MASK (0x10U)
+#define PMU_AON_CLK_CTRL_RTC_CLK_EN_SHIFT (4U)
+/*! rtc_clk_en - RTC clock enable
+ */
+#define PMU_AON_CLK_CTRL_RTC_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_AON_CLK_CTRL_RTC_CLK_EN_SHIFT)) & PMU_AON_CLK_CTRL_RTC_CLK_EN_MASK)
+#define PMU_AON_CLK_CTRL_RTC_INT_SEL_MASK (0x20U)
+#define PMU_AON_CLK_CTRL_RTC_INT_SEL_SHIFT (5U)
+/*! rtc_int_sel - RTC Interrupt Select
+ */
+#define PMU_AON_CLK_CTRL_RTC_INT_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_AON_CLK_CTRL_RTC_INT_SEL_SHIFT)) & PMU_AON_CLK_CTRL_RTC_INT_SEL_MASK)
+#define PMU_AON_CLK_CTRL_DMA_CLK_GATE_EN_MASK (0x40U)
+#define PMU_AON_CLK_CTRL_DMA_CLK_GATE_EN_SHIFT (6U)
+/*! dma_clk_gate_en - DMA Clock Gate Enable
+ */
+#define PMU_AON_CLK_CTRL_DMA_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << PMU_AON_CLK_CTRL_DMA_CLK_GATE_EN_SHIFT)) & PMU_AON_CLK_CTRL_DMA_CLK_GATE_EN_MASK)
+#define PMU_AON_CLK_CTRL_APB0_CLK_DIV_MASK (0x180U)
+#define PMU_AON_CLK_CTRL_APB0_CLK_DIV_SHIFT (7U)
+/*! apb0_clk_div - APB0 clock divisor
+ */
+#define PMU_AON_CLK_CTRL_APB0_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_AON_CLK_CTRL_APB0_CLK_DIV_SHIFT)) & PMU_AON_CLK_CTRL_APB0_CLK_DIV_MASK)
+#define PMU_AON_CLK_CTRL_APB1_CLK_DIV_MASK (0x600U)
+#define PMU_AON_CLK_CTRL_APB1_CLK_DIV_SHIFT (9U)
+/*! apb1_clk_div - APB1 clock divisor
+ */
+#define PMU_AON_CLK_CTRL_APB1_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_AON_CLK_CTRL_APB1_CLK_DIV_SHIFT)) & PMU_AON_CLK_CTRL_APB1_CLK_DIV_MASK)
+/*! @} */
+
+/*! @name PERI3_CTRL - PERI3 Control Register */
+/*! @{ */
+#define PMU_PERI3_CTRL_CAN_DIV_MASK (0x7U)
+#define PMU_PERI3_CTRL_CAN_DIV_SHIFT (0U)
+/*! can_div - CAN clock div ratio
+ */
+#define PMU_PERI3_CTRL_CAN_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_CAN_DIV_SHIFT)) & PMU_PERI3_CTRL_CAN_DIV_MASK)
+#define PMU_PERI3_CTRL_CAN_GATE_MASK (0x8U)
+#define PMU_PERI3_CTRL_CAN_GATE_SHIFT (3U)
+/*! can_gate - CAN clock gate
+ */
+#define PMU_PERI3_CTRL_CAN_GATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_CAN_GATE_SHIFT)) & PMU_PERI3_CTRL_CAN_GATE_MASK)
+#define PMU_PERI3_CTRL_KP_CLK_SEL_MASK (0x10U)
+#define PMU_PERI3_CTRL_KP_CLK_SEL_SHIFT (4U)
+/*! kp_clk_sel - keypad clock select
+ */
+#define PMU_PERI3_CTRL_KP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_KP_CLK_SEL_SHIFT)) & PMU_PERI3_CTRL_KP_CLK_SEL_MASK)
+#define PMU_PERI3_CTRL_KP_GATE_MASK (0x20U)
+#define PMU_PERI3_CTRL_KP_GATE_SHIFT (5U)
+/*! kp_gate - keypad clock gate
+ */
+#define PMU_PERI3_CTRL_KP_GATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_KP_GATE_SHIFT)) & PMU_PERI3_CTRL_KP_GATE_MASK)
+#define PMU_PERI3_CTRL_CB_CLK_SEL_MASK (0x40U)
+#define PMU_PERI3_CTRL_CB_CLK_SEL_SHIFT (6U)
+/*! cb_clk_sel - cbutton clock select
+ */
+#define PMU_PERI3_CTRL_CB_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_CB_CLK_SEL_SHIFT)) & PMU_PERI3_CTRL_CB_CLK_SEL_MASK)
+#define PMU_PERI3_CTRL_CB_GATE_MASK (0x80U)
+#define PMU_PERI3_CTRL_CB_GATE_SHIFT (7U)
+/*! cb_gate - cbutton clock gate
+ */
+#define PMU_PERI3_CTRL_CB_GATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_CB_GATE_SHIFT)) & PMU_PERI3_CTRL_CB_GATE_MASK)
+#define PMU_PERI3_CTRL_GAU_DIV_MASK (0x1F00U)
+#define PMU_PERI3_CTRL_GAU_DIV_SHIFT (8U)
+/*! gau_div - GAU clock div ratio
+ */
+#define PMU_PERI3_CTRL_GAU_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_GAU_DIV_SHIFT)) & PMU_PERI3_CTRL_GAU_DIV_MASK)
+#define PMU_PERI3_CTRL_RC32M_DIV_MASK (0x3E000U)
+#define PMU_PERI3_CTRL_RC32M_DIV_SHIFT (13U)
+/*! rc32m_div - RC32M clock div ratio
+ */
+#define PMU_PERI3_CTRL_RC32M_DIV(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_RC32M_DIV_SHIFT)) & PMU_PERI3_CTRL_RC32M_DIV_MASK)
+#define PMU_PERI3_CTRL_RC32M_GATE_MASK (0x40000U)
+#define PMU_PERI3_CTRL_RC32M_GATE_SHIFT (18U)
+/*! rc32m_gate - RC32M reference clock gate
+ */
+#define PMU_PERI3_CTRL_RC32M_GATE(x) (((uint32_t)(((uint32_t)(x)) << PMU_PERI3_CTRL_RC32M_GATE_SHIFT)) & PMU_PERI3_CTRL_RC32M_GATE_MASK)
+/*! @} */
+
+/*! @name IO_LPM_G03_ - I/O LPM G03 Register */
+/*! @{ */
+#define PMU_IO_LPM_G03__IO_LPM_G03_MASK (0xFFFFFFFFU)
+#define PMU_IO_LPM_G03__IO_LPM_G03_SHIFT (0U)
+/*! io_lpm_G03 - I/O low power mode
+ */
+#define PMU_IO_LPM_G03__IO_LPM_G03(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_LPM_G03__IO_LPM_G03_SHIFT)) & PMU_IO_LPM_G03__IO_LPM_G03_MASK)
+/*! @} */
+
+/*! @name IO_LPM_G47_ - I/O LPM G47 Register */
+/*! @{ */
+#define PMU_IO_LPM_G47__IO_LPM_G47_MASK (0xFFFFFFFFU)
+#define PMU_IO_LPM_G47__IO_LPM_G47_SHIFT (0U)
+/*! io_lpm_G47 - I/O low power mode
+ */
+#define PMU_IO_LPM_G47__IO_LPM_G47(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_LPM_G47__IO_LPM_G47_SHIFT)) & PMU_IO_LPM_G47__IO_LPM_G47_MASK)
+/*! @} */
+
+/*! @name IO_LPM_G811_ - I/O LPM G811 Register */
+/*! @{ */
+#define PMU_IO_LPM_G811__IO_LPM_G811_MASK (0xFFFFFFFFU)
+#define PMU_IO_LPM_G811__IO_LPM_G811_SHIFT (0U)
+/*! io_lpm_G811 - I/O low power mode
+ */
+#define PMU_IO_LPM_G811__IO_LPM_G811(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_LPM_G811__IO_LPM_G811_SHIFT)) & PMU_IO_LPM_G811__IO_LPM_G811_MASK)
+/*! @} */
+
+/*! @name IO_LPM_G1215_ - I/O LPM G1215 Register */
+/*! @{ */
+#define PMU_IO_LPM_G1215__IO_LPM_G1215_MASK (0xFFFFFFFFU)
+#define PMU_IO_LPM_G1215__IO_LPM_G1215_SHIFT (0U)
+/*! io_lpm_G1215 - I/O low power mode
+ */
+#define PMU_IO_LPM_G1215__IO_LPM_G1215(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_LPM_G1215__IO_LPM_G1215_SHIFT)) & PMU_IO_LPM_G1215__IO_LPM_G1215_MASK)
+/*! @} */
+
+/*! @name IO_LPM_G1617_ - I/O LPM G1617 Register */
+/*! @{ */
+#define PMU_IO_LPM_G1617__IO_LPM_G1617_MASK (0xFFFFFFFFU)
+#define PMU_IO_LPM_G1617__IO_LPM_G1617_SHIFT (0U)
+/*! io_lpm_G1617 - I/O low power mode
+ */
+#define PMU_IO_LPM_G1617__IO_LPM_G1617(x) (((uint32_t)(((uint32_t)(x)) << PMU_IO_LPM_G1617__IO_LPM_G1617_SHIFT)) & PMU_IO_LPM_G1617__IO_LPM_G1617_MASK)
+/*! @} */
+
+/*! @name WAKEUP_MASK - Wakeup Mask Interrupt Register */
+/*! @{ */
+#define PMU_WAKEUP_MASK_PIN0_WAKEUP_MASK_MASK (0x8U)
+#define PMU_WAKEUP_MASK_PIN0_WAKEUP_MASK_SHIFT (3U)
+/*! pin0_wakeup_mask - Pin0 Wakeup Mask
+ * 0b0..mask pin0 wakeup interrupt
+ * 0b1..unmask pin0 wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_PIN0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_PIN0_WAKEUP_MASK_SHIFT)) & PMU_WAKEUP_MASK_PIN0_WAKEUP_MASK_MASK)
+#define PMU_WAKEUP_MASK_PIN1_WAKEUP_MASK_MASK (0x10U)
+#define PMU_WAKEUP_MASK_PIN1_WAKEUP_MASK_SHIFT (4U)
+/*! pin1_wakeup_mask - Pin1 Wakeup Mask
+ * 0b0..mask pin1 wakeup interrupt
+ * 0b1..unmask pin1 wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_PIN1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_PIN1_WAKEUP_MASK_SHIFT)) & PMU_WAKEUP_MASK_PIN1_WAKEUP_MASK_MASK)
+#define PMU_WAKEUP_MASK_RTC_WAKEUP_MASK_MASK (0x20U)
+#define PMU_WAKEUP_MASK_RTC_WAKEUP_MASK_SHIFT (5U)
+/*! rtc_wakeup_mask - RTC Wakeup Mask
+ * 0b0..mask RTC wakeup interrupt
+ * 0b1..unmask RTC wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_RTC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_RTC_WAKEUP_MASK_SHIFT)) & PMU_WAKEUP_MASK_RTC_WAKEUP_MASK_MASK)
+#define PMU_WAKEUP_MASK_PMIP_COMP_WAKEUP_MASK_MASK (0x40U)
+#define PMU_WAKEUP_MASK_PMIP_COMP_WAKEUP_MASK_SHIFT (6U)
+/*! pmip_comp_wakeup_mask - PMIP Comparator Wakeup Mask
+ * 0b0..mask PMIP comparator wakeup interrupt
+ * 0b1..unmask PMIP comparator wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_PMIP_COMP_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_PMIP_COMP_WAKEUP_MASK_SHIFT)) & PMU_WAKEUP_MASK_PMIP_COMP_WAKEUP_MASK_MASK)
+#define PMU_WAKEUP_MASK_WL_WAKEUP_MASK_MASK (0x80U)
+#define PMU_WAKEUP_MASK_WL_WAKEUP_MASK_SHIFT (7U)
+/*! wl_wakeup_mask - WLAN Wakeup Mask
+ * 0b0..mask WLAN wakeup interrupt
+ * 0b1..unmask WLAN wakeup interrupt
+ */
+#define PMU_WAKEUP_MASK_WL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << PMU_WAKEUP_MASK_WL_WAKEUP_MASK_SHIFT)) & PMU_WAKEUP_MASK_WL_WAKEUP_MASK_MASK)
+/*! @} */
+
+/*! @name WLAN_CTRL - WLAN Control Register */
+/*! @{ */
+#define PMU_WLAN_CTRL_PD_MASK (0x1U)
+#define PMU_WLAN_CTRL_PD_SHIFT (0U)
+/*! pd - WLAN power down function
+ */
+#define PMU_WLAN_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_PD_SHIFT)) & PMU_WLAN_CTRL_PD_MASK)
+#define PMU_WLAN_CTRL_REFCLK_SYS_REQ_MASK (0x2U)
+#define PMU_WLAN_CTRL_REFCLK_SYS_REQ_SHIFT (1U)
+/*! refclk_sys_req - WLAN SYS reference clock request
+ */
+#define PMU_WLAN_CTRL_REFCLK_SYS_REQ(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_REFCLK_SYS_REQ_SHIFT)) & PMU_WLAN_CTRL_REFCLK_SYS_REQ_MASK)
+#define PMU_WLAN_CTRL_REFCLK_AUD_REQ_MASK (0x4U)
+#define PMU_WLAN_CTRL_REFCLK_AUD_REQ_SHIFT (2U)
+/*! refclk_aud_req - WLAN AUD reference clock request
+ */
+#define PMU_WLAN_CTRL_REFCLK_AUD_REQ(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_REFCLK_AUD_REQ_SHIFT)) & PMU_WLAN_CTRL_REFCLK_AUD_REQ_MASK)
+#define PMU_WLAN_CTRL_REFCLK_USB_REQ_MASK (0x8U)
+#define PMU_WLAN_CTRL_REFCLK_USB_REQ_SHIFT (3U)
+/*! refclk_usb_req - WLAN USB reference clock request
+ */
+#define PMU_WLAN_CTRL_REFCLK_USB_REQ(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_REFCLK_USB_REQ_SHIFT)) & PMU_WLAN_CTRL_REFCLK_USB_REQ_MASK)
+#define PMU_WLAN_CTRL_REFCLK_SYS_RDY_MASK (0x10U)
+#define PMU_WLAN_CTRL_REFCLK_SYS_RDY_SHIFT (4U)
+/*! refclk_sys_rdy - WLAN reference clock ready
+ */
+#define PMU_WLAN_CTRL_REFCLK_SYS_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_REFCLK_SYS_RDY_SHIFT)) & PMU_WLAN_CTRL_REFCLK_SYS_RDY_MASK)
+#define PMU_WLAN_CTRL_REFCLK_AUD_RDY_MASK (0x20U)
+#define PMU_WLAN_CTRL_REFCLK_AUD_RDY_SHIFT (5U)
+/*! refclk_aud_rdy - WLAN reference clock ready
+ */
+#define PMU_WLAN_CTRL_REFCLK_AUD_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_REFCLK_AUD_RDY_SHIFT)) & PMU_WLAN_CTRL_REFCLK_AUD_RDY_MASK)
+#define PMU_WLAN_CTRL_REFCLK_USB_RDY_MASK (0x40U)
+#define PMU_WLAN_CTRL_REFCLK_USB_RDY_SHIFT (6U)
+/*! refclk_usb_rdy - WLAN reference clock ready
+ */
+#define PMU_WLAN_CTRL_REFCLK_USB_RDY(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_REFCLK_USB_RDY_SHIFT)) & PMU_WLAN_CTRL_REFCLK_USB_RDY_MASK)
+#define PMU_WLAN_CTRL_WL_PD_DEL_CFG_MASK (0x3FF80U)
+#define PMU_WLAN_CTRL_WL_PD_DEL_CFG_SHIFT (7U)
+/*! wl_pd_del_cfg - count for 30ms
+ */
+#define PMU_WLAN_CTRL_WL_PD_DEL_CFG(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL_WL_PD_DEL_CFG_SHIFT)) & PMU_WLAN_CTRL_WL_PD_DEL_CFG_MASK)
+/*! @} */
+
+/*! @name WLAN_CTRL1 - WLAN Control 1 Register */
+/*! @{ */
+#define PMU_WLAN_CTRL1_MCI_WL_WAKEUP_MASK (0x800U)
+#define PMU_WLAN_CTRL1_MCI_WL_WAKEUP_SHIFT (11U)
+/*! MCI_WL_WAKEUP - MCI_WL_WAKEUP
+ */
+#define PMU_WLAN_CTRL1_MCI_WL_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << PMU_WLAN_CTRL1_MCI_WL_WAKEUP_SHIFT)) & PMU_WLAN_CTRL1_MCI_WL_WAKEUP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group PMU_Register_Masks */
+
+
+/* PMU - Peripheral instance base addresses */
+/** Peripheral PMU base address */
+#define PMU_BASE (0x480A0000u)
+/** Peripheral PMU base pointer */
+#define PMU ((PMU_Type *)PMU_BASE)
+/** Array initializer of PMU peripheral base addresses */
+#define PMU_BASE_ADDRS { PMU_BASE }
+/** Array initializer of PMU peripheral base pointers */
+#define PMU_BASE_PTRS { PMU }
+/** Interrupt vectors for the PMU peripheral type */
+#define PMU_IRQS { PMU_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- QSPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup QSPI_Peripheral_Access_Layer QSPI Peripheral Access Layer
+ * @{
+ */
+
+/** QSPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CNTL; /**< Serial Interface Control Register, offset: 0x0 */
+ __IO uint32_t CONF; /**< Serial Interface Configuration Register, offset: 0x4 */
+ __IO uint32_t DOUT; /**< Serial Interface Data Out Register, offset: 0x8 */
+ __I uint32_t DIN; /**< Serial Interface Data Input Register, offset: 0xC */
+ __IO uint32_t INSTR; /**< Serial Interface Instruction Register, offset: 0x10 */
+ __IO uint32_t ADDR; /**< Serial Interface Address Register, offset: 0x14 */
+ __IO uint32_t RDMODE; /**< Serial Interface Read Mode Register, offset: 0x18 */
+ __IO uint32_t HDRCNT; /**< Serial Interface Header Count Register, offset: 0x1C */
+ __IO uint32_t DINCNT; /**< Serial Interface Data Input Count Register, offset: 0x20 */
+ __IO uint32_t TIMING; /**< Serial Interface Timing Register, offset: 0x24 */
+ __IO uint32_t CONF2; /**< Serial Interface Configuration 2 Register, offset: 0x28 */
+ __I uint32_t ISR; /**< Serial Interface Interrupt Status Register, offset: 0x2C */
+ __IO uint32_t IMR; /**< Serial Interface Interrupt Mask Register, offset: 0x30 */
+ __I uint32_t IRSR; /**< Serial Interface Interrupt Raw Status Register, offset: 0x34 */
+ __O uint32_t ISC; /**< Serial Interface Interrupt Clear Register, offset: 0x38 */
+} QSPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- QSPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup QSPI_Register_Masks QSPI Register Masks
+ * @{
+ */
+
+/*! @name CNTL - Serial Interface Control Register */
+/*! @{ */
+#define QSPI_CNTL_SS_EN_MASK (0x1U)
+#define QSPI_CNTL_SS_EN_SHIFT (0U)
+/*! SS_EN - Serial Select Enable.
+ * 0b0..Serial select is de-activated, ss_n (serial interface select) output is driven high.
+ * 0b1..Serial select is activated, ss_n (serial interface select) output is driven low
+ */
+#define QSPI_CNTL_SS_EN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_SS_EN_SHIFT)) & QSPI_CNTL_SS_EN_MASK)
+#define QSPI_CNTL_XFER_RDY_MASK (0x2U)
+#define QSPI_CNTL_XFER_RDY_SHIFT (1U)
+/*! XFER_RDY - Serial Interface Transfer Ready.
+ * 0b0..Serial Interface is currently transferring data.
+ * 0b1..Serial Interface is ready for a new transfer.
+ */
+#define QSPI_CNTL_XFER_RDY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_XFER_RDY_SHIFT)) & QSPI_CNTL_XFER_RDY_MASK)
+#define QSPI_CNTL_RFIFO_EMPTY_MASK (0x10U)
+#define QSPI_CNTL_RFIFO_EMPTY_SHIFT (4U)
+/*! RFIFO_EMPTY - Read FIFO Empty.
+ * 0b0..Read FIFO is not emptied.
+ * 0b1..Read FIFO is emptied
+ */
+#define QSPI_CNTL_RFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_RFIFO_EMPTY_SHIFT)) & QSPI_CNTL_RFIFO_EMPTY_MASK)
+#define QSPI_CNTL_RFIFO_FULL_MASK (0x20U)
+#define QSPI_CNTL_RFIFO_FULL_SHIFT (5U)
+/*! RFIFO_FULL - Read FIFO Full.
+ * 0b0..Read FIFO is not fulled.
+ * 0b1..Read FIFO is fulled.
+ */
+#define QSPI_CNTL_RFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_RFIFO_FULL_SHIFT)) & QSPI_CNTL_RFIFO_FULL_MASK)
+#define QSPI_CNTL_WFIFO_EMPTY_MASK (0x40U)
+#define QSPI_CNTL_WFIFO_EMPTY_SHIFT (6U)
+/*! WFIFO_EMPTY - Write FIFO Empty.
+ * 0b0..Write FIFO is not emptied.
+ * 0b1..Write FIFO is emptied.
+ */
+#define QSPI_CNTL_WFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_WFIFO_EMPTY_SHIFT)) & QSPI_CNTL_WFIFO_EMPTY_MASK)
+#define QSPI_CNTL_WFIFO_FULL_MASK (0x80U)
+#define QSPI_CNTL_WFIFO_FULL_SHIFT (7U)
+/*! WFIFO_FULL - Write FIFO Full.
+ * 0b0..Write FIFO is not fulled.
+ * 0b1..Write FIFO is fulled.
+ */
+#define QSPI_CNTL_WFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_WFIFO_FULL_SHIFT)) & QSPI_CNTL_WFIFO_FULL_MASK)
+#define QSPI_CNTL_RFIFO_UNDRFLW_MASK (0x100U)
+#define QSPI_CNTL_RFIFO_UNDRFLW_SHIFT (8U)
+/*! RFIFO_UNDRFLW - Read FIFO Underflow.
+ * 0b0..Read FIFO is not underflowed.
+ * 0b1..Read FIFO is underflowed.
+ */
+#define QSPI_CNTL_RFIFO_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_RFIFO_UNDRFLW_SHIFT)) & QSPI_CNTL_RFIFO_UNDRFLW_MASK)
+#define QSPI_CNTL_RFIFO_OVRFLW_MASK (0x200U)
+#define QSPI_CNTL_RFIFO_OVRFLW_SHIFT (9U)
+/*! RFIFO_OVRFLW - Read FIFO Overflow.
+ * 0b0..Read FIFO is not overflowed.
+ * 0b1..Read FIFO is overflowed
+ */
+#define QSPI_CNTL_RFIFO_OVRFLW(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_RFIFO_OVRFLW_SHIFT)) & QSPI_CNTL_RFIFO_OVRFLW_MASK)
+#define QSPI_CNTL_WFIFO_UNDRFLW_MASK (0x400U)
+#define QSPI_CNTL_WFIFO_UNDRFLW_SHIFT (10U)
+/*! WFIFO_UNDRFLW - Write FIFO Underflow.
+ * 0b0..Write FIFO is not underflowed.
+ * 0b1..Write FIFO is underflowed.
+ */
+#define QSPI_CNTL_WFIFO_UNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_WFIFO_UNDRFLW_SHIFT)) & QSPI_CNTL_WFIFO_UNDRFLW_MASK)
+#define QSPI_CNTL_WFIFO_OVERFLW_MASK (0x800U)
+#define QSPI_CNTL_WFIFO_OVERFLW_SHIFT (11U)
+/*! WFIFO_OVERFLW - Write FIFO Overflow.
+ * 0b0..Write FIFO is not overflowed.
+ * 0b1..Write FIFO is overflowed.
+ */
+#define QSPI_CNTL_WFIFO_OVERFLW(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CNTL_WFIFO_OVERFLW_SHIFT)) & QSPI_CNTL_WFIFO_OVERFLW_MASK)
+/*! @} */
+
+/*! @name CONF - Serial Interface Configuration Register */
+/*! @{ */
+#define QSPI_CONF_CLK_PRESCALE_MASK (0x1FU)
+#define QSPI_CONF_CLK_PRESCALE_SHIFT (0U)
+/*! CLK_PRESCALE - Serial Interface Clock Prescaler (from SPI clock)
+ * 0b00000..SPI clock/1
+ * 0b00001..SPI clock/1
+ * 0b00010..SPI clock/2
+ * 0b00011..SPI clock/3
+ * 0b00100..SPI clock/4
+ * 0b00101..SPI clock/5
+ * 0b01101..SPI clock/13
+ * 0b01110..SPI clock/14
+ * 0b01111..SPI clock/15
+ * 0b10000..SPI clock/2
+ * 0b10001..SPI clock/2
+ * 0b10010..SPI clock/4
+ * 0b10011..SPI clock/6
+ * 0b10100..SPI clock/8
+ * 0b10101..SPI clock/10
+ * 0b11101..SPI clock/26
+ * 0b11110..SPI clock/28
+ * 0b11111..SPI clock/30
+ */
+#define QSPI_CONF_CLK_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_CLK_PRESCALE_SHIFT)) & QSPI_CONF_CLK_PRESCALE_MASK)
+#define QSPI_CONF_BYTE_LEN_MASK (0x20U)
+#define QSPI_CONF_BYTE_LEN_SHIFT (5U)
+/*! BYTE_LEN - Byte Length
+ * 0b0..1 byte.
+ * 0b1..4 bytes.
+ */
+#define QSPI_CONF_BYTE_LEN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_BYTE_LEN_SHIFT)) & QSPI_CONF_BYTE_LEN_MASK)
+#define QSPI_CONF_CLK_PHA_MASK (0x80U)
+#define QSPI_CONF_CLK_PHA_SHIFT (7U)
+/*! CLK_PHA - Serial Interface Clock Phase
+ * 0b0..Data is latched at the rising edge of the serial interface clock when CLK_POL (R04h [8]) = 0, and at the
+ * falling edge of the serial interface clock when CLK_POL = 1.
+ * 0b1..Data is latched at the falling edge of the serial interface clock when
+ */
+#define QSPI_CONF_CLK_PHA(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_CLK_PHA_SHIFT)) & QSPI_CONF_CLK_PHA_MASK)
+#define QSPI_CONF_CLK_POL_MASK (0x100U)
+#define QSPI_CONF_CLK_POL_SHIFT (8U)
+/*! CLK_POL - Serial Interface Clock Polarity
+ * 0b0..Serial interface clock is low when inactive.
+ * 0b1..Serial interface clock is high when inactive.
+ */
+#define QSPI_CONF_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_CLK_POL_SHIFT)) & QSPI_CONF_CLK_POL_MASK)
+#define QSPI_CONF_FIFO_FLUSH_MASK (0x200U)
+#define QSPI_CONF_FIFO_FLUSH_SHIFT (9U)
+/*! FIFO_FLUSH - Flush Read and Write FIFOs
+ * 0b0..Read and Write FIFOs are not flushed.
+ * 0b1..Read and Write FIFOs are flushed.
+ */
+#define QSPI_CONF_FIFO_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_FIFO_FLUSH_SHIFT)) & QSPI_CONF_FIFO_FLUSH_MASK)
+#define QSPI_CONF_DATA_PIN_MASK (0xC00U)
+#define QSPI_CONF_DATA_PIN_SHIFT (10U)
+/*! DATA_PIN - Data Transfer Pin
+ * 0b00..Use 1 serial interface pin (use in single mode).
+ * 0b01..Use 2 serial interface pins (use in dual mode).
+ * 0b10..Use 4 serial interface pins (use in quad mode).
+ * 0b11..Reserved.
+ */
+#define QSPI_CONF_DATA_PIN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_DATA_PIN_SHIFT)) & QSPI_CONF_DATA_PIN_MASK)
+#define QSPI_CONF_ADDR_PIN_MASK (0x1000U)
+#define QSPI_CONF_ADDR_PIN_SHIFT (12U)
+/*! ADDR_PIN - Address Transfer Pin
+ * 0b0..Use one serial interface pin.
+ * 0b1..Use the number of pins as indicated in DATA_PIN (R04h [11:10]).
+ */
+#define QSPI_CONF_ADDR_PIN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_ADDR_PIN_SHIFT)) & QSPI_CONF_ADDR_PIN_MASK)
+#define QSPI_CONF_RW_EN_MASK (0x2000U)
+#define QSPI_CONF_RW_EN_SHIFT (13U)
+/*! RW_EN - Read Write Enable.
+ * 0b0..Read data from the serial interface.
+ * 0b1..Write data to the serial interface.
+ */
+#define QSPI_CONF_RW_EN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_RW_EN_SHIFT)) & QSPI_CONF_RW_EN_MASK)
+#define QSPI_CONF_XFER_STOP_MASK (0x4000U)
+#define QSPI_CONF_XFER_STOP_SHIFT (14U)
+/*! XFER_STOP - Transfer Stop
+ * 0b0..Continue current transfer
+ * 0b1..Stop current transfer.
+ */
+#define QSPI_CONF_XFER_STOP(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_XFER_STOP_SHIFT)) & QSPI_CONF_XFER_STOP_MASK)
+#define QSPI_CONF_XFER_START_MASK (0x8000U)
+#define QSPI_CONF_XFER_START_SHIFT (15U)
+/*! XFER_START - Transfer Start.
+ * 0b0..Transfer has completed.
+ * 0b1..Transfer has started.
+ */
+#define QSPI_CONF_XFER_START(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF_XFER_START_SHIFT)) & QSPI_CONF_XFER_START_MASK)
+/*! @} */
+
+/*! @name DOUT - Serial Interface Data Out Register */
+/*! @{ */
+#define QSPI_DOUT_DATA_OUT_MASK (0xFFFFFFFFU)
+#define QSPI_DOUT_DATA_OUT_SHIFT (0U)
+/*! DATA_OUT - Serial Interface Data Out.
+ */
+#define QSPI_DOUT_DATA_OUT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DOUT_DATA_OUT_SHIFT)) & QSPI_DOUT_DATA_OUT_MASK)
+/*! @} */
+
+/*! @name DIN - Serial Interface Data Input Register */
+/*! @{ */
+#define QSPI_DIN_DATA_IN_MASK (0xFFFFFFFFU)
+#define QSPI_DIN_DATA_IN_SHIFT (0U)
+/*! DATA_IN - Serial Interface Data In.
+ */
+#define QSPI_DIN_DATA_IN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DIN_DATA_IN_SHIFT)) & QSPI_DIN_DATA_IN_MASK)
+/*! @} */
+
+/*! @name INSTR - Serial Interface Instruction Register */
+/*! @{ */
+#define QSPI_INSTR_INSTR_MASK (0xFFFFU)
+#define QSPI_INSTR_INSTR_SHIFT (0U)
+/*! INSTR - Instruction
+ */
+#define QSPI_INSTR_INSTR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_INSTR_INSTR_SHIFT)) & QSPI_INSTR_INSTR_MASK)
+/*! @} */
+
+/*! @name ADDR - Serial Interface Address Register */
+/*! @{ */
+#define QSPI_ADDR_ADDR_MASK (0xFFFFFFFFU)
+#define QSPI_ADDR_ADDR_SHIFT (0U)
+/*! ADDR - Serial Interface Address.
+ */
+#define QSPI_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ADDR_ADDR_SHIFT)) & QSPI_ADDR_ADDR_MASK)
+/*! @} */
+
+/*! @name RDMODE - Serial Interface Read Mode Register */
+/*! @{ */
+#define QSPI_RDMODE_RMODE_MASK (0xFFFFU)
+#define QSPI_RDMODE_RMODE_SHIFT (0U)
+/*! RMODE - Serial Interface Read Mode.
+ */
+#define QSPI_RDMODE_RMODE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_RDMODE_RMODE_SHIFT)) & QSPI_RDMODE_RMODE_MASK)
+/*! @} */
+
+/*! @name HDRCNT - Serial Interface Header Count Register */
+/*! @{ */
+#define QSPI_HDRCNT_INSTR_CNT_MASK (0x3U)
+#define QSPI_HDRCNT_INSTR_CNT_SHIFT (0U)
+/*! INSTR_CNT - Instruction Count.
+ * 0b00..0 byte.
+ * 0b01..1 byte.
+ * 0b10..2 bytes.
+ * 0b11..Reserved.
+ */
+#define QSPI_HDRCNT_INSTR_CNT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_HDRCNT_INSTR_CNT_SHIFT)) & QSPI_HDRCNT_INSTR_CNT_MASK)
+#define QSPI_HDRCNT_ADDR_CNT_MASK (0x70U)
+#define QSPI_HDRCNT_ADDR_CNT_SHIFT (4U)
+/*! ADDR_CNT - Address Count.
+ * 0b000..0 byte.
+ * 0b001..1 byte.
+ * 0b010..2 bytes.
+ * 0b011..3 bytes.
+ * 0b100..4 bytes.
+ */
+#define QSPI_HDRCNT_ADDR_CNT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_HDRCNT_ADDR_CNT_SHIFT)) & QSPI_HDRCNT_ADDR_CNT_MASK)
+#define QSPI_HDRCNT_RM_CNT_MASK (0x300U)
+#define QSPI_HDRCNT_RM_CNT_SHIFT (8U)
+/*! RM_CNT - Read Mode Count.
+ * 0b00..0 byte.
+ * 0b01..1 byte.
+ * 0b10..2 bytes.
+ * 0b11..Reserved.
+ */
+#define QSPI_HDRCNT_RM_CNT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_HDRCNT_RM_CNT_SHIFT)) & QSPI_HDRCNT_RM_CNT_MASK)
+#define QSPI_HDRCNT_DUMMY_CNT_MASK (0x3000U)
+#define QSPI_HDRCNT_DUMMY_CNT_SHIFT (12U)
+/*! DUMMY_CNT - Dummy Count.
+ * 0b00..0 byte.
+ * 0b01..1 byte.
+ * 0b10..2 bytes.
+ * 0b11..3 bytes.
+ */
+#define QSPI_HDRCNT_DUMMY_CNT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_HDRCNT_DUMMY_CNT_SHIFT)) & QSPI_HDRCNT_DUMMY_CNT_MASK)
+/*! @} */
+
+/*! @name DINCNT - Serial Interface Data Input Count Register */
+/*! @{ */
+#define QSPI_DINCNT_DATA_IN_CNT_MASK (0xFFFFFU)
+#define QSPI_DINCNT_DATA_IN_CNT_SHIFT (0U)
+/*! DATA_IN_CNT - Serial Interface Data In Count.
+ */
+#define QSPI_DINCNT_DATA_IN_CNT(x) (((uint32_t)(((uint32_t)(x)) << QSPI_DINCNT_DATA_IN_CNT_SHIFT)) & QSPI_DINCNT_DATA_IN_CNT_MASK)
+/*! @} */
+
+/*! @name TIMING - Serial Interface Timing Register */
+/*! @{ */
+#define QSPI_TIMING_DATA_IN_DLY_MASK (0x3U)
+#define QSPI_TIMING_DATA_IN_DLY_SHIFT (0U)
+/*! DATA_IN_DLY - Serial Interface Data Input Delay
+ * 0b00..No delay.
+ * 0b01..1 serial interface clock delay.
+ * 0b10..2 serial interface clock delay.
+ * 0b11..Reserved
+ */
+#define QSPI_TIMING_DATA_IN_DLY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_TIMING_DATA_IN_DLY_SHIFT)) & QSPI_TIMING_DATA_IN_DLY_MASK)
+#define QSPI_TIMING_CLK_IN_DLY_MASK (0x30U)
+#define QSPI_TIMING_CLK_IN_DLY_SHIFT (4U)
+/*! CLK_IN_DLY - Serial Interface Clock In Delay.
+ * 0b00..No delay.
+ * 0b01..Add 0.2 ns delay.
+ * 0b10..Add 0.4 ns delay
+ * 0b11..Add 0.6 ns delay
+ */
+#define QSPI_TIMING_CLK_IN_DLY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_TIMING_CLK_IN_DLY_SHIFT)) & QSPI_TIMING_CLK_IN_DLY_MASK)
+#define QSPI_TIMING_CLK_CAPT_EDGE_MASK (0x40U)
+#define QSPI_TIMING_CLK_CAPT_EDGE_SHIFT (6U)
+/*! CLK_CAPT_EDGE - Serial Interface Capture Clock Edge.
+ * 0b0..rising edge
+ * 0b1..falling edge
+ */
+#define QSPI_TIMING_CLK_CAPT_EDGE(x) (((uint32_t)(((uint32_t)(x)) << QSPI_TIMING_CLK_CAPT_EDGE_SHIFT)) & QSPI_TIMING_CLK_CAPT_EDGE_MASK)
+#define QSPI_TIMING_CLK_OUT_DLY_MASK (0x300U)
+#define QSPI_TIMING_CLK_OUT_DLY_SHIFT (8U)
+/*! CLK_OUT_DLY - Serial Interface Clock Out Delay.
+ * 0b00..No delay.
+ * 0b01..Add 0.2 ns delay.
+ * 0b10..Add 0.4 ns delay.
+ * 0b11..Add 0.6 ns delay.
+ */
+#define QSPI_TIMING_CLK_OUT_DLY(x) (((uint32_t)(((uint32_t)(x)) << QSPI_TIMING_CLK_OUT_DLY_SHIFT)) & QSPI_TIMING_CLK_OUT_DLY_MASK)
+/*! @} */
+
+/*! @name CONF2 - Serial Interface Configuration 2 Register */
+/*! @{ */
+#define QSPI_CONF2_SRST_MASK (0x1U)
+#define QSPI_CONF2_SRST_SHIFT (0U)
+/*! SRST - Soft Reset.
+ * 0b0..Hardware is not in reset.
+ * 0b1..Hardware is in reset.
+ */
+#define QSPI_CONF2_SRST(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF2_SRST_SHIFT)) & QSPI_CONF2_SRST_MASK)
+#define QSPI_CONF2_DMA_RD_EN_MASK (0x2U)
+#define QSPI_CONF2_DMA_RD_EN_SHIFT (1U)
+/*! DMA_RD_EN - DMA Read Enable.
+ * 0b0..DMA read is disabled.
+ * 0b1..DMA read is enabled.
+ */
+#define QSPI_CONF2_DMA_RD_EN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF2_DMA_RD_EN_SHIFT)) & QSPI_CONF2_DMA_RD_EN_MASK)
+#define QSPI_CONF2_DMA_WR_EN_MASK (0x4U)
+#define QSPI_CONF2_DMA_WR_EN_SHIFT (2U)
+/*! DMA_WR_EN - DMA Write Enable.
+ * 0b0..DMA write is disabled.
+ * 0b1..DMA write is enabled.
+ */
+#define QSPI_CONF2_DMA_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF2_DMA_WR_EN_SHIFT)) & QSPI_CONF2_DMA_WR_EN_MASK)
+#define QSPI_CONF2_DMA_RD_BURST_MASK (0x300U)
+#define QSPI_CONF2_DMA_RD_BURST_SHIFT (8U)
+/*! DMA_RD_BURST - DMA Read Burst.
+ * 0b00..1 data.
+ * 0b01..4 data.
+ * 0b10..8 data.
+ * 0b11..Reserved.
+ */
+#define QSPI_CONF2_DMA_RD_BURST(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF2_DMA_RD_BURST_SHIFT)) & QSPI_CONF2_DMA_RD_BURST_MASK)
+#define QSPI_CONF2_DMA_WR_BURST_MASK (0x3000U)
+#define QSPI_CONF2_DMA_WR_BURST_SHIFT (12U)
+/*! DMA_WR_BURST - DMA Write Burst.
+ * 0b00..1 data.
+ * 0b01..4 data.
+ * 0b10..8 data.
+ * 0b11..Reserved.
+ */
+#define QSPI_CONF2_DMA_WR_BURST(x) (((uint32_t)(((uint32_t)(x)) << QSPI_CONF2_DMA_WR_BURST_SHIFT)) & QSPI_CONF2_DMA_WR_BURST_MASK)
+/*! @} */
+
+/*! @name ISR - Serial Interface Interrupt Status Register */
+/*! @{ */
+#define QSPI_ISR_XFER_DONE_IS_MASK (0x1U)
+#define QSPI_ISR_XFER_DONE_IS_SHIFT (0U)
+/*! XFER_DONE_IS - Transfer Done Interrupt Status.
+ * 0b0..Transfer has not completed after masking.
+ * 0b1..Transfer has completed after masking.
+ */
+#define QSPI_ISR_XFER_DONE_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_XFER_DONE_IS_SHIFT)) & QSPI_ISR_XFER_DONE_IS_MASK)
+#define QSPI_ISR_XFER_RDY_IS_MASK (0x2U)
+#define QSPI_ISR_XFER_RDY_IS_SHIFT (1U)
+/*! XFER_RDY_IS - Serial Interface Transfer Ready Interrupt Status
+ * 0b0..Serial interface is currently transferring data after masking.
+ * 0b1..Serial interface is ready for a new transfer after masking.
+ */
+#define QSPI_ISR_XFER_RDY_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_XFER_RDY_IS_SHIFT)) & QSPI_ISR_XFER_RDY_IS_MASK)
+#define QSPI_ISR_RFIFO_DMA_BURST_IS_MASK (0x4U)
+#define QSPI_ISR_RFIFO_DMA_BURST_IS_SHIFT (2U)
+/*! RFIFO_DMA_BURST_IS - Read FIFO DMA Burst Interrupt Status.
+ * 0b0..Number of available data in the Read FIFO is less than DMA_RD_BURST (R28h [9:8]) after masking.
+ * 0b1..Number of available data in the Read FIFO is greater than or equal to DMA_RD_BURST (R28h [9:8]) after masking.
+ */
+#define QSPI_ISR_RFIFO_DMA_BURST_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_RFIFO_DMA_BURST_IS_SHIFT)) & QSPI_ISR_RFIFO_DMA_BURST_IS_MASK)
+#define QSPI_ISR_WFIFO_DMA_BURST_IS_MASK (0x8U)
+#define QSPI_ISR_WFIFO_DMA_BURST_IS_SHIFT (3U)
+/*! WFIFO_DMA_BURST_IS - Write FIFO DMA burst Interrupt Status.
+ * 0b0..Number of unused entries in the Write FIFO is less than DMA_WR_BURST (R28h [13:12]) after masking.
+ * 0b1..Number of unused entries in the Write FIFO is greater than or equal to DMA_WR_BURST (R28h [13:12]) after masking.
+ */
+#define QSPI_ISR_WFIFO_DMA_BURST_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_WFIFO_DMA_BURST_IS_SHIFT)) & QSPI_ISR_WFIFO_DMA_BURST_IS_MASK)
+#define QSPI_ISR_RFIFO_EMPTY_IS_MASK (0x10U)
+#define QSPI_ISR_RFIFO_EMPTY_IS_SHIFT (4U)
+/*! RFIFO_EMPTY_IS - Read FIFO Empty Interrupt Status.
+ * 0b0..Read FIFO is not emptied after masking.
+ * 0b1..Read FIFO is empty after masking.
+ */
+#define QSPI_ISR_RFIFO_EMPTY_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_RFIFO_EMPTY_IS_SHIFT)) & QSPI_ISR_RFIFO_EMPTY_IS_MASK)
+#define QSPI_ISR_RFIFO_FULL_IS_MASK (0x20U)
+#define QSPI_ISR_RFIFO_FULL_IS_SHIFT (5U)
+/*! RFIFO_FULL_IS - Read FIFO Full Interrupt Status.
+ * 0b0..Read FIFO is not fulled after masking.
+ * 0b1..Read FIFO is fulled after masking.
+ */
+#define QSPI_ISR_RFIFO_FULL_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_RFIFO_FULL_IS_SHIFT)) & QSPI_ISR_RFIFO_FULL_IS_MASK)
+#define QSPI_ISR_WFIFO_EMPTY_IS_MASK (0x40U)
+#define QSPI_ISR_WFIFO_EMPTY_IS_SHIFT (6U)
+/*! WFIFO_EMPTY_IS - Write FIFO Empty Interrupt Status.
+ * 0b0..Write FIFO is not emptied after masking.
+ * 0b1..Write FIFO is emptied after masking.
+ */
+#define QSPI_ISR_WFIFO_EMPTY_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_WFIFO_EMPTY_IS_SHIFT)) & QSPI_ISR_WFIFO_EMPTY_IS_MASK)
+#define QSPI_ISR_WFIFO_FULL_IS_MASK (0x80U)
+#define QSPI_ISR_WFIFO_FULL_IS_SHIFT (7U)
+/*! WFIFO_FULL_IS - Write FIFO Full Interrupt Status.
+ * 0b0..Write FIFO is not fulled after masking.
+ * 0b1..Write FIFO is fulled after masking.
+ */
+#define QSPI_ISR_WFIFO_FULL_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_WFIFO_FULL_IS_SHIFT)) & QSPI_ISR_WFIFO_FULL_IS_MASK)
+#define QSPI_ISR_RFIFO_UNDRFLW_IS_MASK (0x100U)
+#define QSPI_ISR_RFIFO_UNDRFLW_IS_SHIFT (8U)
+/*! RFIFO_UNDRFLW_IS - Read FIFO Underflow Interrupt Status.
+ * 0b0..Read FIFO is not underflowed after masking.
+ * 0b1..Read FIFO is underflowed after masking.
+ */
+#define QSPI_ISR_RFIFO_UNDRFLW_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_RFIFO_UNDRFLW_IS_SHIFT)) & QSPI_ISR_RFIFO_UNDRFLW_IS_MASK)
+#define QSPI_ISR_RFIFO_OVRFLW_IS_MASK (0x200U)
+#define QSPI_ISR_RFIFO_OVRFLW_IS_SHIFT (9U)
+/*! RFIFO_OVRFLW_IS - Read FIFO Overflow Interrupt Status.
+ * 0b0..Read FIFO is not overflowed after masking.
+ * 0b1..Read FIFO is overflowed after masking.
+ */
+#define QSPI_ISR_RFIFO_OVRFLW_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_RFIFO_OVRFLW_IS_SHIFT)) & QSPI_ISR_RFIFO_OVRFLW_IS_MASK)
+#define QSPI_ISR_WFIFO_UNDRFLW_IS_MASK (0x400U)
+#define QSPI_ISR_WFIFO_UNDRFLW_IS_SHIFT (10U)
+/*! WFIFO_UNDRFLW_IS - Write FIFO Underflow Interrupt Status.
+ * 0b0..Write FIFO is not underflowed after masking.
+ * 0b1..Write FIFO is underflowed after masking.
+ */
+#define QSPI_ISR_WFIFO_UNDRFLW_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_WFIFO_UNDRFLW_IS_SHIFT)) & QSPI_ISR_WFIFO_UNDRFLW_IS_MASK)
+#define QSPI_ISR_WFIFO_OVRFLW_IS_MASK (0x800U)
+#define QSPI_ISR_WFIFO_OVRFLW_IS_SHIFT (11U)
+/*! WFIFO_OVRFLW_IS - Write FIFO Overflow Interrupt Status.
+ * 0b0..Write FIFO is not overflowed after masking.
+ * 0b1..Write FIFO is overflowed after masking.
+ */
+#define QSPI_ISR_WFIFO_OVRFLW_IS(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISR_WFIFO_OVRFLW_IS_SHIFT)) & QSPI_ISR_WFIFO_OVRFLW_IS_MASK)
+/*! @} */
+
+/*! @name IMR - Serial Interface Interrupt Mask Register */
+/*! @{ */
+#define QSPI_IMR_XFER_DONE_IM_MASK (0x1U)
+#define QSPI_IMR_XFER_DONE_IM_SHIFT (0U)
+/*! XFER_DONE_IM - Transfer Done Interrupt Mask.
+ * 0b0..Transfer done interrupt is not masked.
+ * 0b1..Transfer done interrupt is masked.
+ */
+#define QSPI_IMR_XFER_DONE_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_XFER_DONE_IM_SHIFT)) & QSPI_IMR_XFER_DONE_IM_MASK)
+#define QSPI_IMR_XFER_RDY_IM_MASK (0x2U)
+#define QSPI_IMR_XFER_RDY_IM_SHIFT (1U)
+/*! XFER_RDY_IM - Serial Interface Transfer Ready Mask.
+ * 0b0..Transfer ready interrupt is not masked.
+ * 0b1..Transfer ready interrupt is masked.
+ */
+#define QSPI_IMR_XFER_RDY_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_XFER_RDY_IM_SHIFT)) & QSPI_IMR_XFER_RDY_IM_MASK)
+#define QSPI_IMR_RFIFO_DMA_BURST_IM_MASK (0x4U)
+#define QSPI_IMR_RFIFO_DMA_BURST_IM_SHIFT (2U)
+/*! RFIFO_DMA_BURST_IM - Read FIFO DMA Burst Interrupt Mask.
+ * 0b0..Read FIFO DMA burst interrupt is not masked.
+ * 0b1..Read FIFO DMA burst interrupt is masked.
+ */
+#define QSPI_IMR_RFIFO_DMA_BURST_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_RFIFO_DMA_BURST_IM_SHIFT)) & QSPI_IMR_RFIFO_DMA_BURST_IM_MASK)
+#define QSPI_IMR_WFIFO_DMA_BURST_IM_MASK (0x8U)
+#define QSPI_IMR_WFIFO_DMA_BURST_IM_SHIFT (3U)
+/*! WFIFO_DMA_BURST_IM - Write FIFO DMA Burst Interrupt Mask.
+ * 0b0..Write FIFO DMA burst interrupt is not masked.
+ * 0b1..Write FIFO DMA burst interrupt is masked.
+ */
+#define QSPI_IMR_WFIFO_DMA_BURST_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_WFIFO_DMA_BURST_IM_SHIFT)) & QSPI_IMR_WFIFO_DMA_BURST_IM_MASK)
+#define QSPI_IMR_RFIFO_EMPTY_IM_MASK (0x10U)
+#define QSPI_IMR_RFIFO_EMPTY_IM_SHIFT (4U)
+/*! RFIFO_EMPTY_IM - Read FIFO Empty Interrupt Mask.
+ * 0b0..Read FIFO empty interrupt is not masked.
+ * 0b1..Read FIFO empty interrupt is masked.
+ */
+#define QSPI_IMR_RFIFO_EMPTY_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_RFIFO_EMPTY_IM_SHIFT)) & QSPI_IMR_RFIFO_EMPTY_IM_MASK)
+#define QSPI_IMR_RFIFO_FULL_IM_MASK (0x20U)
+#define QSPI_IMR_RFIFO_FULL_IM_SHIFT (5U)
+/*! RFIFO_FULL_IM - Read FIFO Full Interrupt Mask.
+ * 0b0..Read FIFO full interrupt is not masked.
+ * 0b1..Read FIFO full interrupt is masked.
+ */
+#define QSPI_IMR_RFIFO_FULL_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_RFIFO_FULL_IM_SHIFT)) & QSPI_IMR_RFIFO_FULL_IM_MASK)
+#define QSPI_IMR_WFIFO_EMPTY_IM_MASK (0x40U)
+#define QSPI_IMR_WFIFO_EMPTY_IM_SHIFT (6U)
+/*! WFIFO_EMPTY_IM - Write FIFO Empty Interrupt Mask.
+ * 0b0..Write FIFO empty interrupt is not masked.
+ * 0b1..Write FIFO empty interrupt is masked.
+ */
+#define QSPI_IMR_WFIFO_EMPTY_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_WFIFO_EMPTY_IM_SHIFT)) & QSPI_IMR_WFIFO_EMPTY_IM_MASK)
+#define QSPI_IMR_WFIFO_FULL_IM_MASK (0x80U)
+#define QSPI_IMR_WFIFO_FULL_IM_SHIFT (7U)
+/*! WFIFO_FULL_IM - Write FIFO Full Interrupt Mask.
+ * 0b0..Write FIFO full interrupt is not masked.
+ * 0b1..Write FIFO full interrupt is masked.
+ */
+#define QSPI_IMR_WFIFO_FULL_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_WFIFO_FULL_IM_SHIFT)) & QSPI_IMR_WFIFO_FULL_IM_MASK)
+#define QSPI_IMR_RFIFO_UNDRFLW_IM_MASK (0x100U)
+#define QSPI_IMR_RFIFO_UNDRFLW_IM_SHIFT (8U)
+/*! RFIFO_UNDRFLW_IM - Read FIFO Underflow Interrupt Mask.
+ * 0b0..Read FIFO underflow interrupt is not masked.
+ * 0b1..Read FIFO underflow interrupt is masked.
+ */
+#define QSPI_IMR_RFIFO_UNDRFLW_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_RFIFO_UNDRFLW_IM_SHIFT)) & QSPI_IMR_RFIFO_UNDRFLW_IM_MASK)
+#define QSPI_IMR_RFIFO_OVRFLW_IM_MASK (0x200U)
+#define QSPI_IMR_RFIFO_OVRFLW_IM_SHIFT (9U)
+/*! RFIFO_OVRFLW_IM - Read FIFO Overflow Interrupt Mask.
+ * 0b0..Read FIFO overflow interrupt is not masked.
+ * 0b1..Read FIFO overflow interrupt is masked.
+ */
+#define QSPI_IMR_RFIFO_OVRFLW_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_RFIFO_OVRFLW_IM_SHIFT)) & QSPI_IMR_RFIFO_OVRFLW_IM_MASK)
+#define QSPI_IMR_WFIFO_UNDRFLW_IM_MASK (0x400U)
+#define QSPI_IMR_WFIFO_UNDRFLW_IM_SHIFT (10U)
+/*! WFIFO_UNDRFLW_IM - Write FIFO Underflow Interrupt Mask.
+ * 0b0..Write FIFO underflow interrupt is not masked.
+ * 0b1..Write FIFO underflow interrupt is masked.
+ */
+#define QSPI_IMR_WFIFO_UNDRFLW_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_WFIFO_UNDRFLW_IM_SHIFT)) & QSPI_IMR_WFIFO_UNDRFLW_IM_MASK)
+#define QSPI_IMR_WFIFO_OVRFLW_IM_MASK (0x800U)
+#define QSPI_IMR_WFIFO_OVRFLW_IM_SHIFT (11U)
+/*! WFIFO_OVRFLW_IM - Write FIFO Overflow Interrupt Mask.
+ * 0b0..Write FIFO overflow interrupt is not masked.
+ * 0b1..Write FIFO overflow interrupt is masked.
+ */
+#define QSPI_IMR_WFIFO_OVRFLW_IM(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IMR_WFIFO_OVRFLW_IM_SHIFT)) & QSPI_IMR_WFIFO_OVRFLW_IM_MASK)
+/*! @} */
+
+/*! @name IRSR - Serial Interface Interrupt Raw Status Register */
+/*! @{ */
+#define QSPI_IRSR_XFER_DONE_IR_MASK (0x1U)
+#define QSPI_IRSR_XFER_DONE_IR_SHIFT (0U)
+/*! XFER_DONE_IR - Transfer Done Interrupt Raw.
+ * 0b0..Transfer has not completed before masking.
+ * 0b1..Transfer has completed before masking.
+ */
+#define QSPI_IRSR_XFER_DONE_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_XFER_DONE_IR_SHIFT)) & QSPI_IRSR_XFER_DONE_IR_MASK)
+#define QSPI_IRSR_XFER_RDY_IR_MASK (0x2U)
+#define QSPI_IRSR_XFER_RDY_IR_SHIFT (1U)
+/*! XFER_RDY_IR - Serial Interface Transfer Ready Raw.
+ * 0b0..Serial interface is currently transferring data before masking.
+ * 0b1..Serial interface is ready for a new transfer before masking.
+ */
+#define QSPI_IRSR_XFER_RDY_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_XFER_RDY_IR_SHIFT)) & QSPI_IRSR_XFER_RDY_IR_MASK)
+#define QSPI_IRSR_RFIFO_DMA_BURST_IR_MASK (0x4U)
+#define QSPI_IRSR_RFIFO_DMA_BURST_IR_SHIFT (2U)
+/*! RFIFO_DMA_BURST_IR - Read FIFO DMA Burst Interrupt Raw.
+ * 0b0..Number of available data in the Read FIFO is less than DMA_RD_BURST (R28h [9:8]) before masking.
+ * 0b1..Number of available data in the Read FIFO is greater than or equal to DMA_RD_BURST (R28h [9:8]) before masking.
+ */
+#define QSPI_IRSR_RFIFO_DMA_BURST_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_RFIFO_DMA_BURST_IR_SHIFT)) & QSPI_IRSR_RFIFO_DMA_BURST_IR_MASK)
+#define QSPI_IRSR_WFIFO_DMA_BURST_IR_MASK (0x8U)
+#define QSPI_IRSR_WFIFO_DMA_BURST_IR_SHIFT (3U)
+/*! WFIFO_DMA_BURST_IR - Write FIFO DMA Burst Interrupt Raw.
+ * 0b0..Number of unused entries in the Write FIFO is less than DMA_WR_BURST (R28h [13:12]) before masking.
+ * 0b1..Number of unused entries in the Write FIFO is greater than or equal to DMA_WR_BURST (R28h [13:12]) before masking.
+ */
+#define QSPI_IRSR_WFIFO_DMA_BURST_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_WFIFO_DMA_BURST_IR_SHIFT)) & QSPI_IRSR_WFIFO_DMA_BURST_IR_MASK)
+#define QSPI_IRSR_RFIFO_EMPTY_IR_MASK (0x10U)
+#define QSPI_IRSR_RFIFO_EMPTY_IR_SHIFT (4U)
+/*! RFIFO_EMPTY_IR - Read FIFO Empty Interrupt Raw.
+ * 0b0..Read FIFO is not emptied before masking.
+ * 0b1..Read FIFO is empty before masking.
+ */
+#define QSPI_IRSR_RFIFO_EMPTY_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_RFIFO_EMPTY_IR_SHIFT)) & QSPI_IRSR_RFIFO_EMPTY_IR_MASK)
+#define QSPI_IRSR_RFIFO_FULL_IR_MASK (0x20U)
+#define QSPI_IRSR_RFIFO_FULL_IR_SHIFT (5U)
+/*! RFIFO_FULL_IR - Read FIFO Full Interrupt Raw.
+ * 0b0..Read FIFO is not fulled before masking.
+ * 0b1..Read FIFO is fulled before masking.
+ */
+#define QSPI_IRSR_RFIFO_FULL_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_RFIFO_FULL_IR_SHIFT)) & QSPI_IRSR_RFIFO_FULL_IR_MASK)
+#define QSPI_IRSR_WFIFO_EMPTY_IR_MASK (0x40U)
+#define QSPI_IRSR_WFIFO_EMPTY_IR_SHIFT (6U)
+/*! WFIFO_EMPTY_IR - Write FIFO Empty Interrupt Raw.
+ * 0b0..Write FIFO is not emptied before masking.
+ * 0b1..Write FIFO is emptied before masking.
+ */
+#define QSPI_IRSR_WFIFO_EMPTY_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_WFIFO_EMPTY_IR_SHIFT)) & QSPI_IRSR_WFIFO_EMPTY_IR_MASK)
+#define QSPI_IRSR_WFIFO_FULL_IR_MASK (0x80U)
+#define QSPI_IRSR_WFIFO_FULL_IR_SHIFT (7U)
+/*! WFIFO_FULL_IR - Write FIFO Full Interrupt Raw.
+ * 0b0..Write FIFO is not fulled before masking.
+ * 0b1..Write FIFO is fulled before masking.
+ */
+#define QSPI_IRSR_WFIFO_FULL_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_WFIFO_FULL_IR_SHIFT)) & QSPI_IRSR_WFIFO_FULL_IR_MASK)
+#define QSPI_IRSR_RFIFO_UNDRFLW_IR_MASK (0x100U)
+#define QSPI_IRSR_RFIFO_UNDRFLW_IR_SHIFT (8U)
+/*! RFIFO_UNDRFLW_IR - Read FIFO Underflow Interrupt Raw.
+ * 0b0..Read FIFO is not underflowed before masking.
+ * 0b1..Read FIFO is underflowed before masking.
+ */
+#define QSPI_IRSR_RFIFO_UNDRFLW_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_RFIFO_UNDRFLW_IR_SHIFT)) & QSPI_IRSR_RFIFO_UNDRFLW_IR_MASK)
+#define QSPI_IRSR_RFIFO_OVRFLW_IR_MASK (0x200U)
+#define QSPI_IRSR_RFIFO_OVRFLW_IR_SHIFT (9U)
+/*! RFIFO_OVRFLW_IR - Read FIFO Overflow Interrupt Raw.
+ * 0b0..Read FIFO is not overflowed before masking.
+ * 0b1..Read FIFO is overflowed before masking.
+ */
+#define QSPI_IRSR_RFIFO_OVRFLW_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_RFIFO_OVRFLW_IR_SHIFT)) & QSPI_IRSR_RFIFO_OVRFLW_IR_MASK)
+#define QSPI_IRSR_WFIFO_UNDRFLW_IR_MASK (0x400U)
+#define QSPI_IRSR_WFIFO_UNDRFLW_IR_SHIFT (10U)
+/*! WFIFO_UNDRFLW_IR - Write FIFO Underflow Interrupt Raw.
+ * 0b0..Write FIFO is not underflowed before masking.
+ * 0b1..Write FIFO is underflowed before masking.
+ */
+#define QSPI_IRSR_WFIFO_UNDRFLW_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_WFIFO_UNDRFLW_IR_SHIFT)) & QSPI_IRSR_WFIFO_UNDRFLW_IR_MASK)
+#define QSPI_IRSR_WFIFO_OVRFLW_IR_MASK (0x800U)
+#define QSPI_IRSR_WFIFO_OVRFLW_IR_SHIFT (11U)
+/*! WFIFO_OVRFLW_IR - Write FIFO Overflow Interrupt Raw.
+ * 0b0..Write FIFO is not overflowed before masking.
+ * 0b1..Write FIFO is overflowed before masking.
+ */
+#define QSPI_IRSR_WFIFO_OVRFLW_IR(x) (((uint32_t)(((uint32_t)(x)) << QSPI_IRSR_WFIFO_OVRFLW_IR_SHIFT)) & QSPI_IRSR_WFIFO_OVRFLW_IR_MASK)
+/*! @} */
+
+/*! @name ISC - Serial Interface Interrupt Clear Register */
+/*! @{ */
+#define QSPI_ISC_XFER_DONE_IC_MASK (0x1U)
+#define QSPI_ISC_XFER_DONE_IC_SHIFT (0U)
+/*! XFER_DONE_IC - Transfer Done Interrupt Clear.
+ * 0b0..Transfer done interrupt is not cleared.
+ * 0b1..Transfer done interrupt is cleared.
+ */
+#define QSPI_ISC_XFER_DONE_IC(x) (((uint32_t)(((uint32_t)(x)) << QSPI_ISC_XFER_DONE_IC_SHIFT)) & QSPI_ISC_XFER_DONE_IC_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group QSPI_Register_Masks */
+
+
+/* QSPI - Peripheral instance base addresses */
+/** Peripheral QSPI base address */
+#define QSPI_BASE (0x46010000u)
+/** Peripheral QSPI base pointer */
+#define QSPI ((QSPI_Type *)QSPI_BASE)
+/** Array initializer of QSPI peripheral base addresses */
+#define QSPI_BASE_ADDRS { QSPI_BASE }
+/** Array initializer of QSPI peripheral base pointers */
+#define QSPI_BASE_PTRS { QSPI }
+/** Interrupt vectors for the QSPI peripheral type */
+#define QSPI_IRQS { QSPI_IRQn }
+
+/*!
+ * @}
+ */ /* end of group QSPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RC32 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RC32_Peripheral_Access_Layer RC32 Peripheral Access Layer
+ * @{
+ */
+
+/** RC32 - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */
+ __I uint32_t STATUS; /**< Status Register, offset: 0x4 */
+ __I uint32_t ISR; /**< Interrupt Status Register, offset: 0x8 */
+ __IO uint32_t IMR; /**< Interrupt Mask Register, offset: 0xC */
+ __I uint32_t IRSR; /**< Interrupt Raw Status Register, offset: 0x10 */
+ __IO uint32_t ICR; /**< Interrupt Clear Register, offset: 0x14 */
+ __IO uint32_t CLK; /**< Clock Register, offset: 0x18 */
+ __IO uint32_t RST; /**< Soft Reset Register, offset: 0x1C */
+} RC32_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RC32 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RC32_Register_Masks RC32 Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define RC32_CTRL_EN_MASK (0x1U)
+#define RC32_CTRL_EN_SHIFT (0U)
+/*! en - Calibration reference clock enable
+ * 0b0..
+ * 0b1..
+ */
+#define RC32_CTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << RC32_CTRL_EN_SHIFT)) & RC32_CTRL_EN_MASK)
+#define RC32_CTRL_CAL_EN_MASK (0x2U)
+#define RC32_CTRL_CAL_EN_SHIFT (1U)
+/*! cal_en - Calibration enable
+ * 0b0..
+ * 0b1..
+ */
+#define RC32_CTRL_CAL_EN(x) (((uint32_t)(((uint32_t)(x)) << RC32_CTRL_CAL_EN_SHIFT)) & RC32_CTRL_CAL_EN_MASK)
+#define RC32_CTRL_EXT_CODE_EN_MASK (0x4U)
+#define RC32_CTRL_EXT_CODE_EN_SHIFT (2U)
+/*! ext_code_en - Calibration code from external enable
+ * 0b0..calibration code from internal
+ * 0b1..calibration code from external
+ */
+#define RC32_CTRL_EXT_CODE_EN(x) (((uint32_t)(((uint32_t)(x)) << RC32_CTRL_EXT_CODE_EN_SHIFT)) & RC32_CTRL_EXT_CODE_EN_MASK)
+#define RC32_CTRL_PD_MASK (0x8U)
+#define RC32_CTRL_PD_SHIFT (3U)
+/*! pd - Clock Power down
+ * 0b0..Power up.
+ * 0b1..Power down
+ */
+#define RC32_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << RC32_CTRL_PD_SHIFT)) & RC32_CTRL_PD_MASK)
+#define RC32_CTRL_CODE_FR_EXT_MASK (0xFF0U)
+#define RC32_CTRL_CODE_FR_EXT_SHIFT (4U)
+/*! code_fr_ext - External code input for calibration.
+ */
+#define RC32_CTRL_CODE_FR_EXT(x) (((uint32_t)(((uint32_t)(x)) << RC32_CTRL_CODE_FR_EXT_SHIFT)) & RC32_CTRL_CODE_FR_EXT_MASK)
+/*! @} */
+
+/*! @name STATUS - Status Register */
+/*! @{ */
+#define RC32_STATUS_CLK_RDY_MASK (0x1U)
+#define RC32_STATUS_CLK_RDY_SHIFT (0U)
+/*! clk_rdy - Clock Ready
+ */
+#define RC32_STATUS_CLK_RDY(x) (((uint32_t)(((uint32_t)(x)) << RC32_STATUS_CLK_RDY_SHIFT)) & RC32_STATUS_CLK_RDY_MASK)
+#define RC32_STATUS_CAL_DONE_MASK (0x2U)
+#define RC32_STATUS_CAL_DONE_SHIFT (1U)
+/*! cal_done - Calibration finish flag
+ * 0b0..calibration not done
+ * 0b1..calibration done
+ */
+#define RC32_STATUS_CAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << RC32_STATUS_CAL_DONE_SHIFT)) & RC32_STATUS_CAL_DONE_MASK)
+#define RC32_STATUS_CODE_FR_CAL_MASK (0x3FCU)
+#define RC32_STATUS_CODE_FR_CAL_SHIFT (2U)
+/*! code_fr_cal - Calibration code
+ */
+#define RC32_STATUS_CODE_FR_CAL(x) (((uint32_t)(((uint32_t)(x)) << RC32_STATUS_CODE_FR_CAL_SHIFT)) & RC32_STATUS_CODE_FR_CAL_MASK)
+/*! @} */
+
+/*! @name ISR - Interrupt Status Register */
+/*! @{ */
+#define RC32_ISR_CALDON_INT_MASK (0x1U)
+#define RC32_ISR_CALDON_INT_SHIFT (0U)
+/*! caldon_int - Calibration Done Interrupt
+ */
+#define RC32_ISR_CALDON_INT(x) (((uint32_t)(((uint32_t)(x)) << RC32_ISR_CALDON_INT_SHIFT)) & RC32_ISR_CALDON_INT_MASK)
+#define RC32_ISR_CKRDY_INT_MASK (0x2U)
+#define RC32_ISR_CKRDY_INT_SHIFT (1U)
+/*! ckrdy_int - Clock Ready Interrupt
+ */
+#define RC32_ISR_CKRDY_INT(x) (((uint32_t)(((uint32_t)(x)) << RC32_ISR_CKRDY_INT_SHIFT)) & RC32_ISR_CKRDY_INT_MASK)
+/*! @} */
+
+/*! @name IMR - Interrupt Mask Register */
+/*! @{ */
+#define RC32_IMR_CALDON_INT_MSK_MASK (0x1U)
+#define RC32_IMR_CALDON_INT_MSK_SHIFT (0U)
+/*! caldon_int_msk - Calibration Done Interrupt Mask
+ */
+#define RC32_IMR_CALDON_INT_MSK(x) (((uint32_t)(((uint32_t)(x)) << RC32_IMR_CALDON_INT_MSK_SHIFT)) & RC32_IMR_CALDON_INT_MSK_MASK)
+#define RC32_IMR_CKRDY_INT_MSK_MASK (0x2U)
+#define RC32_IMR_CKRDY_INT_MSK_SHIFT (1U)
+/*! ckrdy_int_msk - Clock Ready Interrupt Mask
+ */
+#define RC32_IMR_CKRDY_INT_MSK(x) (((uint32_t)(((uint32_t)(x)) << RC32_IMR_CKRDY_INT_MSK_SHIFT)) & RC32_IMR_CKRDY_INT_MSK_MASK)
+/*! @} */
+
+/*! @name IRSR - Interrupt Raw Status Register */
+/*! @{ */
+#define RC32_IRSR_CALDON_INT_RAW_MASK (0x1U)
+#define RC32_IRSR_CALDON_INT_RAW_SHIFT (0U)
+/*! caldon_int_raw - Calibration Done Interrupt Raw
+ */
+#define RC32_IRSR_CALDON_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << RC32_IRSR_CALDON_INT_RAW_SHIFT)) & RC32_IRSR_CALDON_INT_RAW_MASK)
+#define RC32_IRSR_CKRDY_INT_RAW_MASK (0x2U)
+#define RC32_IRSR_CKRDY_INT_RAW_SHIFT (1U)
+/*! ckrdy_int_raw - Clock Ready Interrupt Raw
+ */
+#define RC32_IRSR_CKRDY_INT_RAW(x) (((uint32_t)(((uint32_t)(x)) << RC32_IRSR_CKRDY_INT_RAW_SHIFT)) & RC32_IRSR_CKRDY_INT_RAW_MASK)
+/*! @} */
+
+/*! @name ICR - Interrupt Clear Register */
+/*! @{ */
+#define RC32_ICR_CALDON_INT_CLR_MASK (0x1U)
+#define RC32_ICR_CALDON_INT_CLR_SHIFT (0U)
+/*! caldon_int_clr - Calibration Done Interrupt Raw
+ */
+#define RC32_ICR_CALDON_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << RC32_ICR_CALDON_INT_CLR_SHIFT)) & RC32_ICR_CALDON_INT_CLR_MASK)
+#define RC32_ICR_CKRDY_INT_CLR_MASK (0x2U)
+#define RC32_ICR_CKRDY_INT_CLR_SHIFT (1U)
+/*! ckrdy_int_clr - Clock Ready Interrupt Clear
+ */
+#define RC32_ICR_CKRDY_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << RC32_ICR_CKRDY_INT_CLR_SHIFT)) & RC32_ICR_CKRDY_INT_CLR_MASK)
+/*! @} */
+
+/*! @name CLK - Clock Register */
+/*! @{ */
+#define RC32_CLK_REF_SEL_MASK (0x4U)
+#define RC32_CLK_REF_SEL_SHIFT (2U)
+/*! ref_sel - Reference clock frequency select.
+ * 0b0..Half-divided reference clock
+ * 0b1..Original reference clock
+ */
+#define RC32_CLK_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << RC32_CLK_REF_SEL_SHIFT)) & RC32_CLK_REF_SEL_MASK)
+#define RC32_CLK_SOFT_CLK_RST_MASK (0x8U)
+#define RC32_CLK_SOFT_CLK_RST_SHIFT (3U)
+/*! soft_clk_rst - Soft reset for clock divider
+ * 0b0..No action
+ * 0b1..
+ */
+#define RC32_CLK_SOFT_CLK_RST(x) (((uint32_t)(((uint32_t)(x)) << RC32_CLK_SOFT_CLK_RST_SHIFT)) & RC32_CLK_SOFT_CLK_RST_MASK)
+/*! @} */
+
+/*! @name RST - Soft Reset Register */
+/*! @{ */
+#define RC32_RST_SOFT_RST_MASK (0x1U)
+#define RC32_RST_SOFT_RST_SHIFT (0U)
+/*! soft_rst - Soft reset for module, active high
+ * 0b0..No action
+ * 0b1..
+ */
+#define RC32_RST_SOFT_RST(x) (((uint32_t)(((uint32_t)(x)) << RC32_RST_SOFT_RST_SHIFT)) & RC32_RST_SOFT_RST_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RC32_Register_Masks */
+
+
+/* RC32 - Peripheral instance base addresses */
+/** Peripheral RC32 base address */
+#define RC32_BASE (0x460A0000u)
+/** Peripheral RC32 base pointer */
+#define RC32 ((RC32_Type *)RC32_BASE)
+/** Array initializer of RC32 peripheral base addresses */
+#define RC32_BASE_ADDRS { RC32_BASE }
+/** Array initializer of RC32 peripheral base pointers */
+#define RC32_BASE_PTRS { RC32 }
+/** Interrupt vectors for the RC32 peripheral type */
+#define RC32_IRQS { RC32M_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RC32_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CNT_EN_REG; /**< Counter Enable Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t INT_RAW_REG; /**< Interrupt Raw Register, offset: 0x20 */
+ __I uint32_t INT_REG; /**< Interrupt Register, offset: 0x24 */
+ __IO uint32_t INT_MSK_REG; /**< Interrupt Mask Register, offset: 0x28 */
+ uint8_t RESERVED_1[20];
+ __IO uint32_t CNT_CNTL_REG; /**< Counter Control Register, offset: 0x40 */
+ uint8_t RESERVED_2[12];
+ __I uint32_t CNT_VAL_REG; /**< Counter Value Register, offset: 0x50 */
+ uint8_t RESERVED_3[12];
+ __IO uint32_t CNT_UPP_VAL_REG; /**< Counter Upper Value Register, offset: 0x60 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t CNT_ALARM_VAL_REG; /**< Counter Alarm Value Register, offset: 0x70 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t CLK_CNTL_REG; /**< Clock control register, offset: 0x80 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CNT_EN_REG - Counter Enable Register */
+/*! @{ */
+#define RTC_CNT_EN_REG_CNT_START_MASK (0x1U)
+#define RTC_CNT_EN_REG_CNT_START_SHIFT (0U)
+/*! CNT_START - Counter Enable
+ * 0b0..No action
+ * 0b1..Enable the counter (poll CNT_RUN for 1 to confirm that the counter is enabled internally)
+ */
+#define RTC_CNT_EN_REG_CNT_START(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_EN_REG_CNT_START_SHIFT)) & RTC_CNT_EN_REG_CNT_START_MASK)
+#define RTC_CNT_EN_REG_CNT_STOP_MASK (0x2U)
+#define RTC_CNT_EN_REG_CNT_STOP_SHIFT (1U)
+/*! CNT_STOP - Counter Disable
+ * 0b0..No action
+ * 0b1..Disable the counter (poll CNT_RUN for 0 to confirm that the counter is disabled internally)
+ */
+#define RTC_CNT_EN_REG_CNT_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_EN_REG_CNT_STOP_SHIFT)) & RTC_CNT_EN_REG_CNT_STOP_MASK)
+#define RTC_CNT_EN_REG_CNT_RESET_MASK (0x4U)
+#define RTC_CNT_EN_REG_CNT_RESET_SHIFT (2U)
+/*! CNT_RESET - Counter Reset
+ * 0b0..No action
+ * 0b1..Reset the counter (counter is reset to 0; channel output states are reset to 0; poll CNT_RST_DONE for 1
+ * before writing to any other registers)
+ */
+#define RTC_CNT_EN_REG_CNT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_EN_REG_CNT_RESET_SHIFT)) & RTC_CNT_EN_REG_CNT_RESET_MASK)
+#define RTC_CNT_EN_REG_CNT_RUN_MASK (0x10000U)
+#define RTC_CNT_EN_REG_CNT_RUN_SHIFT (16U)
+/*! CNT_RUN - Counter Enabled Status
+ * 0b0..Counter is disabled
+ * 0b1..Counter is enabled
+ */
+#define RTC_CNT_EN_REG_CNT_RUN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_EN_REG_CNT_RUN_SHIFT)) & RTC_CNT_EN_REG_CNT_RUN_MASK)
+#define RTC_CNT_EN_REG_CNT_RST_DONE_MASK (0x20000U)
+#define RTC_CNT_EN_REG_CNT_RST_DONE_SHIFT (17U)
+/*! CNT_RST_DONE - Counter Reset Done Status
+ * 0b0..Indicates that the counter is still resetting
+ * 0b1..Indicates that the counter has been reset
+ */
+#define RTC_CNT_EN_REG_CNT_RST_DONE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_EN_REG_CNT_RST_DONE_SHIFT)) & RTC_CNT_EN_REG_CNT_RST_DONE_MASK)
+#define RTC_CNT_EN_REG_STS_RESETN_MASK (0x40000U)
+#define RTC_CNT_EN_REG_STS_RESETN_SHIFT (18U)
+/*! STS_RESETN - System Reset Status
+ * 0b0..Indicates that the system reset is still asserted
+ * 0b1..Indicates that the system reset is deasserted
+ */
+#define RTC_CNT_EN_REG_STS_RESETN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_EN_REG_STS_RESETN_SHIFT)) & RTC_CNT_EN_REG_STS_RESETN_MASK)
+/*! @} */
+
+/*! @name INT_RAW_REG - Interrupt Raw Register */
+/*! @{ */
+#define RTC_INT_RAW_REG_CNT_ALARM_INT_MASK (0x8000U)
+#define RTC_INT_RAW_REG_CNT_ALARM_INT_SHIFT (15U)
+/*! CNT_ALARM_INT - Counter-Reach-Alarm Interrupt Status
+ * 0b0..Status cleared
+ * 0b1..Counter has reached ALARM_VAL
+ */
+#define RTC_INT_RAW_REG_CNT_ALARM_INT(x) (((uint32_t)(((uint32_t)(x)) << RTC_INT_RAW_REG_CNT_ALARM_INT_SHIFT)) & RTC_INT_RAW_REG_CNT_ALARM_INT_MASK)
+#define RTC_INT_RAW_REG_CNT_UPP_INT_MASK (0x10000U)
+#define RTC_INT_RAW_REG_CNT_UPP_INT_SHIFT (16U)
+/*! CNT_UPP_INT - Counter-Reach-Upper Interrupt Status
+ * 0b0..Status cleared
+ * 0b1..Counter has reached UPP_VAL
+ */
+#define RTC_INT_RAW_REG_CNT_UPP_INT(x) (((uint32_t)(((uint32_t)(x)) << RTC_INT_RAW_REG_CNT_UPP_INT_SHIFT)) & RTC_INT_RAW_REG_CNT_UPP_INT_MASK)
+/*! @} */
+
+/*! @name INT_REG - Interrupt Register */
+/*! @{ */
+#define RTC_INT_REG_CNT_ALARM_INTR_MASK (0x8000U)
+#define RTC_INT_REG_CNT_ALARM_INTR_SHIFT (15U)
+/*! CNT_ALARM_INTR - Masked Signal of CNT_ALARM_INT
+ */
+#define RTC_INT_REG_CNT_ALARM_INTR(x) (((uint32_t)(((uint32_t)(x)) << RTC_INT_REG_CNT_ALARM_INTR_SHIFT)) & RTC_INT_REG_CNT_ALARM_INTR_MASK)
+#define RTC_INT_REG_CNT_UPP_INTR_MASK (0x10000U)
+#define RTC_INT_REG_CNT_UPP_INTR_SHIFT (16U)
+/*! CNT_UPP_INTR - Masked Signal of CNT_UPP_INT
+ */
+#define RTC_INT_REG_CNT_UPP_INTR(x) (((uint32_t)(((uint32_t)(x)) << RTC_INT_REG_CNT_UPP_INTR_SHIFT)) & RTC_INT_REG_CNT_UPP_INTR_MASK)
+/*! @} */
+
+/*! @name INT_MSK_REG - Interrupt Mask Register */
+/*! @{ */
+#define RTC_INT_MSK_REG_CNT_ALARM_MSK_MASK (0x8000U)
+#define RTC_INT_MSK_REG_CNT_ALARM_MSK_SHIFT (15U)
+/*! CNT_ALARM_MSK - CNT_ALARM_INT Interrupt Mask
+ * 0b0..Do not mask CNT_ALARM_INT
+ * 0b1..Mask interrupt CNT_ALARM_INT
+ */
+#define RTC_INT_MSK_REG_CNT_ALARM_MSK(x) (((uint32_t)(((uint32_t)(x)) << RTC_INT_MSK_REG_CNT_ALARM_MSK_SHIFT)) & RTC_INT_MSK_REG_CNT_ALARM_MSK_MASK)
+#define RTC_INT_MSK_REG_CNT_UPP_MSK_MASK (0x10000U)
+#define RTC_INT_MSK_REG_CNT_UPP_MSK_SHIFT (16U)
+/*! CNT_UPP_MSK - CNT_UPP_INT Interrupt Mask
+ * 0b0..Do not mask CNT_UPP_INT
+ * 0b1..Mask interrupt CNT_UPP_INT
+ */
+#define RTC_INT_MSK_REG_CNT_UPP_MSK(x) (((uint32_t)(((uint32_t)(x)) << RTC_INT_MSK_REG_CNT_UPP_MSK_SHIFT)) & RTC_INT_MSK_REG_CNT_UPP_MSK_MASK)
+/*! @} */
+
+/*! @name CNT_CNTL_REG - Counter Control Register */
+/*! @{ */
+#define RTC_CNT_CNTL_REG_CNT_DBG_ACT_MASK (0x10U)
+#define RTC_CNT_CNTL_REG_CNT_DBG_ACT_SHIFT (4U)
+/*! CNT_DBG_ACT - Counter Debug Mode Action Mask
+ * 0b0..In debug mode, stop the counters
+ * 0b1..In debug mode, counters are not affected
+ */
+#define RTC_CNT_CNTL_REG_CNT_DBG_ACT(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_CNTL_REG_CNT_DBG_ACT_SHIFT)) & RTC_CNT_CNTL_REG_CNT_DBG_ACT_MASK)
+#define RTC_CNT_CNTL_REG_CNT_UPDT_MOD_MASK (0x300U)
+#define RTC_CNT_CNTL_REG_CNT_UPDT_MOD_SHIFT (8U)
+/*! CNT_UPDT_MOD - Counter Update Mode
+ * 0b00..Update off
+ * 0b01..Reserved.
+ * 0b10..Auto-update (use when counter clock is at least 5 times slower than the register bus clock)
+ * 0b11..Reserved
+ */
+#define RTC_CNT_CNTL_REG_CNT_UPDT_MOD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_CNTL_REG_CNT_UPDT_MOD_SHIFT)) & RTC_CNT_CNTL_REG_CNT_UPDT_MOD_MASK)
+/*! @} */
+
+/*! @name CNT_VAL_REG - Counter Value Register */
+/*! @{ */
+#define RTC_CNT_VAL_REG_CNT_VAL_MASK (0xFFFFFFFFU)
+#define RTC_CNT_VAL_REG_CNT_VAL_SHIFT (0U)
+/*! CNT_VAL - Counter Value
+ */
+#define RTC_CNT_VAL_REG_CNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_VAL_REG_CNT_VAL_SHIFT)) & RTC_CNT_VAL_REG_CNT_VAL_MASK)
+/*! @} */
+
+/*! @name CNT_UPP_VAL_REG - Counter Upper Value Register */
+/*! @{ */
+#define RTC_CNT_UPP_VAL_REG_UPP_VAL_MASK (0xFFFFFFFFU)
+#define RTC_CNT_UPP_VAL_REG_UPP_VAL_SHIFT (0U)
+/*! UPP_VAL - Counter Upper Value
+ */
+#define RTC_CNT_UPP_VAL_REG_UPP_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_UPP_VAL_REG_UPP_VAL_SHIFT)) & RTC_CNT_UPP_VAL_REG_UPP_VAL_MASK)
+/*! @} */
+
+/*! @name CNT_ALARM_VAL_REG - Counter Alarm Value Register */
+/*! @{ */
+#define RTC_CNT_ALARM_VAL_REG_ALARM_VAL_MASK (0xFFFFFFFFU)
+#define RTC_CNT_ALARM_VAL_REG_ALARM_VAL_SHIFT (0U)
+/*! ALARM_VAL - Counter Alarm Value
+ */
+#define RTC_CNT_ALARM_VAL_REG_ALARM_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_ALARM_VAL_REG_ALARM_VAL_SHIFT)) & RTC_CNT_ALARM_VAL_REG_ALARM_VAL_MASK)
+/*! @} */
+
+/*! @name CLK_CNTL_REG - Clock control register */
+/*! @{ */
+#define RTC_CLK_CNTL_REG_CLK_DIV_MASK (0xF00U)
+#define RTC_CLK_CNTL_REG_CLK_DIV_SHIFT (8U)
+/*! CLK_DIV - Clock Divider
+ */
+#define RTC_CLK_CNTL_REG_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << RTC_CLK_CNTL_REG_CLK_DIV_SHIFT)) & RTC_CLK_CNTL_REG_CLK_DIV_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x48090000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDIOC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIOC_Peripheral_Access_Layer SDIOC Peripheral Access Layer
+ * @{
+ */
+
+/** SDIOC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MM4_SYSADDR; /**< MMC4 System Address Register, offset: 0x0 */
+ __IO uint32_t MM4_BLK_CNTL; /**< MMC4 Block Control Register, offset: 0x4 */
+ __IO uint32_t MM4_ARG; /**< MMC4 Command Argument Register, offset: 0x8 */
+ __IO uint32_t MM4_CMD_XFRMD; /**< MMC4 Command and Transfer Mode Register, offset: 0xC */
+ __I uint32_t MM4_RESP0; /**< MMC4 Command Response Register0, offset: 0x10 */
+ __I uint32_t MM4_RESP1; /**< MMC4 Command Response Register1, offset: 0x14 */
+ __I uint32_t MM4_RESP2; /**< MMC4 Command Response Register2, offset: 0x18 */
+ __I uint32_t MM4_RESP3; /**< MMC4 Command Response Register3, offset: 0x1C */
+ __IO uint32_t MM4_DP; /**< MMC4 Buffer Data Port Register, offset: 0x20 */
+ __I uint32_t MM4_STATE; /**< MMC4 Present State Register, offset: 0x24 */
+ __IO uint32_t MM4_CNTL1; /**< MMC4 Host Control Register 1, offset: 0x28 */
+ __IO uint32_t MM4_CNTL2; /**< MMC4 Host Control Register 2, offset: 0x2C */
+ __IO uint32_t MM4_I_STAT; /**< Align Detection Timeout Value Register, offset: 0x30 */
+ __IO uint32_t MM4_I_STAT_EN; /**< MMC4 Interrupt Status Enable Register, offset: 0x34 */
+ __IO uint32_t MM4_I_SIG_EN; /**< MMC4 Interrupt Signal Enable Register, offset: 0x38 */
+ __I uint32_t MM4_ACMD12_ER; /**< MMC4 Auto CMD12 Error Status Register, offset: 0x3C */
+ __I uint32_t MM4_CAP0; /**< MMC4 Capabilities Register 0, offset: 0x40 */
+ uint8_t RESERVED_0[4];
+ __I uint32_t MM4_CUR_CAP0; /**< MMC4 Maximum Current Capabilities Register 0, offset: 0x48 */
+ uint8_t RESERVED_1[176];
+ __I uint32_t MM4_VER; /**< MMC4 Controller Version Status, offset: 0xFC */
+} SDIOC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SDIOC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIOC_Register_Masks SDIOC Register Masks
+ * @{
+ */
+
+/*! @name MM4_SYSADDR - MMC4 System Address Register */
+/*! @{ */
+#define SDIOC_MM4_SYSADDR_SYSADDR_MASK (0xFFFFFFFFU)
+#define SDIOC_MM4_SYSADDR_SYSADDR_SHIFT (0U)
+/*! SYSADDR - SYSADDR
+ */
+#define SDIOC_MM4_SYSADDR_SYSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_SYSADDR_SYSADDR_SHIFT)) & SDIOC_MM4_SYSADDR_SYSADDR_MASK)
+/*! @} */
+
+/*! @name MM4_BLK_CNTL - MMC4 Block Control Register */
+/*! @{ */
+#define SDIOC_MM4_BLK_CNTL_XFR_BLKSZ_MASK (0xFFFU)
+#define SDIOC_MM4_BLK_CNTL_XFR_BLKSZ_SHIFT (0U)
+/*! XFR_BLKSZ - XFR_BLKSZ
+ */
+#define SDIOC_MM4_BLK_CNTL_XFR_BLKSZ(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_BLK_CNTL_XFR_BLKSZ_SHIFT)) & SDIOC_MM4_BLK_CNTL_XFR_BLKSZ_MASK)
+#define SDIOC_MM4_BLK_CNTL_DMA_BUFSZ_MASK (0x7000U)
+#define SDIOC_MM4_BLK_CNTL_DMA_BUFSZ_SHIFT (12U)
+/*! DMA_BUFSZ - DMA_BUFSZ
+ */
+#define SDIOC_MM4_BLK_CNTL_DMA_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_BLK_CNTL_DMA_BUFSZ_SHIFT)) & SDIOC_MM4_BLK_CNTL_DMA_BUFSZ_MASK)
+#define SDIOC_MM4_BLK_CNTL_BLK_CNT_MASK (0xFFFF0000U)
+#define SDIOC_MM4_BLK_CNTL_BLK_CNT_SHIFT (16U)
+/*! BLK_CNT - BLK_CNT
+ */
+#define SDIOC_MM4_BLK_CNTL_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_BLK_CNTL_BLK_CNT_SHIFT)) & SDIOC_MM4_BLK_CNTL_BLK_CNT_MASK)
+/*! @} */
+
+/*! @name MM4_ARG - MMC4 Command Argument Register */
+/*! @{ */
+#define SDIOC_MM4_ARG_ARG_MASK (0xFFFFFFFFU)
+#define SDIOC_MM4_ARG_ARG_SHIFT (0U)
+/*! ARG - ARG
+ */
+#define SDIOC_MM4_ARG_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_ARG_ARG_SHIFT)) & SDIOC_MM4_ARG_ARG_MASK)
+/*! @} */
+
+/*! @name MM4_CMD_XFRMD - MMC4 Command and Transfer Mode Register */
+/*! @{ */
+#define SDIOC_MM4_CMD_XFRMD_DMA_EN_MASK (0x1U)
+#define SDIOC_MM4_CMD_XFRMD_DMA_EN_SHIFT (0U)
+/*! DMA_EN - DMA_EN
+ */
+#define SDIOC_MM4_CMD_XFRMD_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_DMA_EN_SHIFT)) & SDIOC_MM4_CMD_XFRMD_DMA_EN_MASK)
+#define SDIOC_MM4_CMD_XFRMD_BLKCNTEN_MASK (0x2U)
+#define SDIOC_MM4_CMD_XFRMD_BLKCNTEN_SHIFT (1U)
+/*! BLKCNTEN - BLKCNTEN
+ */
+#define SDIOC_MM4_CMD_XFRMD_BLKCNTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_BLKCNTEN_SHIFT)) & SDIOC_MM4_CMD_XFRMD_BLKCNTEN_MASK)
+#define SDIOC_MM4_CMD_XFRMD_AUTOCMD12_MASK (0x4U)
+#define SDIOC_MM4_CMD_XFRMD_AUTOCMD12_SHIFT (2U)
+/*! AUTOCMD12 - AUTOCMD12
+ */
+#define SDIOC_MM4_CMD_XFRMD_AUTOCMD12(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_AUTOCMD12_SHIFT)) & SDIOC_MM4_CMD_XFRMD_AUTOCMD12_MASK)
+#define SDIOC_MM4_CMD_XFRMD_DXFRDIR_MASK (0x10U)
+#define SDIOC_MM4_CMD_XFRMD_DXFRDIR_SHIFT (4U)
+/*! DXFRDIR - DXFRDIR
+ */
+#define SDIOC_MM4_CMD_XFRMD_DXFRDIR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_DXFRDIR_SHIFT)) & SDIOC_MM4_CMD_XFRMD_DXFRDIR_MASK)
+#define SDIOC_MM4_CMD_XFRMD_MS_BLKSEL_MASK (0x20U)
+#define SDIOC_MM4_CMD_XFRMD_MS_BLKSEL_SHIFT (5U)
+/*! MS_BLKSEL - MS_BLKSEL
+ */
+#define SDIOC_MM4_CMD_XFRMD_MS_BLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_MS_BLKSEL_SHIFT)) & SDIOC_MM4_CMD_XFRMD_MS_BLKSEL_MASK)
+#define SDIOC_MM4_CMD_XFRMD_CMD_COMP_ATA_MASK (0x40U)
+#define SDIOC_MM4_CMD_XFRMD_CMD_COMP_ATA_SHIFT (6U)
+/*! CMD_COMP_ATA - CMD_COMP_ATA
+ */
+#define SDIOC_MM4_CMD_XFRMD_CMD_COMP_ATA(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_CMD_COMP_ATA_SHIFT)) & SDIOC_MM4_CMD_XFRMD_CMD_COMP_ATA_MASK)
+#define SDIOC_MM4_CMD_XFRMD_RES_TYPE_MASK (0x30000U)
+#define SDIOC_MM4_CMD_XFRMD_RES_TYPE_SHIFT (16U)
+/*! RES_TYPE - RES_TYPE
+ */
+#define SDIOC_MM4_CMD_XFRMD_RES_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_RES_TYPE_SHIFT)) & SDIOC_MM4_CMD_XFRMD_RES_TYPE_MASK)
+#define SDIOC_MM4_CMD_XFRMD_CRCCHKEN_MASK (0x80000U)
+#define SDIOC_MM4_CMD_XFRMD_CRCCHKEN_SHIFT (19U)
+/*! CRCCHKEN - CRCCHKEN
+ */
+#define SDIOC_MM4_CMD_XFRMD_CRCCHKEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_CRCCHKEN_SHIFT)) & SDIOC_MM4_CMD_XFRMD_CRCCHKEN_MASK)
+#define SDIOC_MM4_CMD_XFRMD_IDXCHKEN_MASK (0x100000U)
+#define SDIOC_MM4_CMD_XFRMD_IDXCHKEN_SHIFT (20U)
+/*! IDXCHKEN - IDXCHKEN
+ */
+#define SDIOC_MM4_CMD_XFRMD_IDXCHKEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_IDXCHKEN_SHIFT)) & SDIOC_MM4_CMD_XFRMD_IDXCHKEN_MASK)
+#define SDIOC_MM4_CMD_XFRMD_DPSEL_MASK (0x200000U)
+#define SDIOC_MM4_CMD_XFRMD_DPSEL_SHIFT (21U)
+/*! DPSEL - DPSEL
+ */
+#define SDIOC_MM4_CMD_XFRMD_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_DPSEL_SHIFT)) & SDIOC_MM4_CMD_XFRMD_DPSEL_MASK)
+#define SDIOC_MM4_CMD_XFRMD_CMD_TYPE_MASK (0xC00000U)
+#define SDIOC_MM4_CMD_XFRMD_CMD_TYPE_SHIFT (22U)
+/*! CMD_TYPE - CMD_TYPE
+ */
+#define SDIOC_MM4_CMD_XFRMD_CMD_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_CMD_TYPE_SHIFT)) & SDIOC_MM4_CMD_XFRMD_CMD_TYPE_MASK)
+#define SDIOC_MM4_CMD_XFRMD_CMD_IDX_MASK (0x3F000000U)
+#define SDIOC_MM4_CMD_XFRMD_CMD_IDX_SHIFT (24U)
+/*! CMD_IDX - CMD_IDX
+ */
+#define SDIOC_MM4_CMD_XFRMD_CMD_IDX(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CMD_XFRMD_CMD_IDX_SHIFT)) & SDIOC_MM4_CMD_XFRMD_CMD_IDX_MASK)
+/*! @} */
+
+/*! @name MM4_RESP0 - MMC4 Command Response Register0 */
+/*! @{ */
+#define SDIOC_MM4_RESP0_RESP_31_0_MASK (0xFFFFFFFFU)
+#define SDIOC_MM4_RESP0_RESP_31_0_SHIFT (0U)
+/*! RESP_31_0 - RESP[31:0]
+ */
+#define SDIOC_MM4_RESP0_RESP_31_0(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_RESP0_RESP_31_0_SHIFT)) & SDIOC_MM4_RESP0_RESP_31_0_MASK)
+/*! @} */
+
+/*! @name MM4_RESP1 - MMC4 Command Response Register1 */
+/*! @{ */
+#define SDIOC_MM4_RESP1_RESP_63_32_MASK (0xFFFFFFFFU)
+#define SDIOC_MM4_RESP1_RESP_63_32_SHIFT (0U)
+/*! RESP_63_32 - RESP[63:32]
+ */
+#define SDIOC_MM4_RESP1_RESP_63_32(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_RESP1_RESP_63_32_SHIFT)) & SDIOC_MM4_RESP1_RESP_63_32_MASK)
+/*! @} */
+
+/*! @name MM4_RESP2 - MMC4 Command Response Register2 */
+/*! @{ */
+#define SDIOC_MM4_RESP2_RESP_95_64_MASK (0xFFFFFFFFU)
+#define SDIOC_MM4_RESP2_RESP_95_64_SHIFT (0U)
+/*! RESP_95_64 - RESP[95:64]
+ */
+#define SDIOC_MM4_RESP2_RESP_95_64(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_RESP2_RESP_95_64_SHIFT)) & SDIOC_MM4_RESP2_RESP_95_64_MASK)
+/*! @} */
+
+/*! @name MM4_RESP3 - MMC4 Command Response Register3 */
+/*! @{ */
+#define SDIOC_MM4_RESP3_RESP_127_96_MASK (0xFFFFFFFFU)
+#define SDIOC_MM4_RESP3_RESP_127_96_SHIFT (0U)
+/*! RESP_127_96 - RESP[127:96]
+ */
+#define SDIOC_MM4_RESP3_RESP_127_96(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_RESP3_RESP_127_96_SHIFT)) & SDIOC_MM4_RESP3_RESP_127_96_MASK)
+/*! @} */
+
+/*! @name MM4_DP - MMC4 Buffer Data Port Register */
+/*! @{ */
+#define SDIOC_MM4_DP_BFR_DATA_MASK (0xFFFFFFFFU)
+#define SDIOC_MM4_DP_BFR_DATA_SHIFT (0U)
+/*! BFR_DATA - BFR_DATA
+ */
+#define SDIOC_MM4_DP_BFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_DP_BFR_DATA_SHIFT)) & SDIOC_MM4_DP_BFR_DATA_MASK)
+/*! @} */
+
+/*! @name MM4_STATE - MMC4 Present State Register */
+/*! @{ */
+#define SDIOC_MM4_STATE_CCMDINHBT_MASK (0x1U)
+#define SDIOC_MM4_STATE_CCMDINHBT_SHIFT (0U)
+/*! CCMDINHBT - CCMDINHBT
+ */
+#define SDIOC_MM4_STATE_CCMDINHBT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_CCMDINHBT_SHIFT)) & SDIOC_MM4_STATE_CCMDINHBT_MASK)
+#define SDIOC_MM4_STATE_DCMDINHBT_MASK (0x2U)
+#define SDIOC_MM4_STATE_DCMDINHBT_SHIFT (1U)
+/*! DCMDINHBT - DCMDINHBT
+ */
+#define SDIOC_MM4_STATE_DCMDINHBT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_DCMDINHBT_SHIFT)) & SDIOC_MM4_STATE_DCMDINHBT_MASK)
+#define SDIOC_MM4_STATE_DATACTV_MASK (0x4U)
+#define SDIOC_MM4_STATE_DATACTV_SHIFT (2U)
+/*! DATACTV - DATACTV
+ */
+#define SDIOC_MM4_STATE_DATACTV(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_DATACTV_SHIFT)) & SDIOC_MM4_STATE_DATACTV_MASK)
+#define SDIOC_MM4_STATE_WRACTV_MASK (0x100U)
+#define SDIOC_MM4_STATE_WRACTV_SHIFT (8U)
+/*! WRACTV - WRACTV
+ */
+#define SDIOC_MM4_STATE_WRACTV(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_WRACTV_SHIFT)) & SDIOC_MM4_STATE_WRACTV_MASK)
+#define SDIOC_MM4_STATE_RDACTV_MASK (0x200U)
+#define SDIOC_MM4_STATE_RDACTV_SHIFT (9U)
+/*! RDACTV - RDACTV
+ */
+#define SDIOC_MM4_STATE_RDACTV(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_RDACTV_SHIFT)) & SDIOC_MM4_STATE_RDACTV_MASK)
+#define SDIOC_MM4_STATE_BUFWREN_MASK (0x400U)
+#define SDIOC_MM4_STATE_BUFWREN_SHIFT (10U)
+/*! BUFWREN - BUFWREN
+ */
+#define SDIOC_MM4_STATE_BUFWREN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_BUFWREN_SHIFT)) & SDIOC_MM4_STATE_BUFWREN_MASK)
+#define SDIOC_MM4_STATE_BUFRDEN_MASK (0x800U)
+#define SDIOC_MM4_STATE_BUFRDEN_SHIFT (11U)
+/*! BUFRDEN - BUFRDEN
+ */
+#define SDIOC_MM4_STATE_BUFRDEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_BUFRDEN_SHIFT)) & SDIOC_MM4_STATE_BUFRDEN_MASK)
+#define SDIOC_MM4_STATE_CDINSTD_MASK (0x10000U)
+#define SDIOC_MM4_STATE_CDINSTD_SHIFT (16U)
+/*! CDINSTD - CDINSTD
+ */
+#define SDIOC_MM4_STATE_CDINSTD(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_CDINSTD_SHIFT)) & SDIOC_MM4_STATE_CDINSTD_MASK)
+#define SDIOC_MM4_STATE_CDSTBL_MASK (0x20000U)
+#define SDIOC_MM4_STATE_CDSTBL_SHIFT (17U)
+/*! CDSTBL - CDSTBL
+ */
+#define SDIOC_MM4_STATE_CDSTBL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_CDSTBL_SHIFT)) & SDIOC_MM4_STATE_CDSTBL_MASK)
+#define SDIOC_MM4_STATE_CDDETLVL_MASK (0x40000U)
+#define SDIOC_MM4_STATE_CDDETLVL_SHIFT (18U)
+/*! CDDETLVL - CDDETLVL
+ */
+#define SDIOC_MM4_STATE_CDDETLVL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_CDDETLVL_SHIFT)) & SDIOC_MM4_STATE_CDDETLVL_MASK)
+#define SDIOC_MM4_STATE_WPSWLVL_MASK (0x80000U)
+#define SDIOC_MM4_STATE_WPSWLVL_SHIFT (19U)
+/*! WPSWLVL - WPSWLVL
+ */
+#define SDIOC_MM4_STATE_WPSWLVL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_WPSWLVL_SHIFT)) & SDIOC_MM4_STATE_WPSWLVL_MASK)
+#define SDIOC_MM4_STATE_LWRDATLVL_MASK (0xF00000U)
+#define SDIOC_MM4_STATE_LWRDATLVL_SHIFT (20U)
+/*! LWRDATLVL - LWRDATLVL
+ */
+#define SDIOC_MM4_STATE_LWRDATLVL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_LWRDATLVL_SHIFT)) & SDIOC_MM4_STATE_LWRDATLVL_MASK)
+#define SDIOC_MM4_STATE_CMDLVL_MASK (0x1000000U)
+#define SDIOC_MM4_STATE_CMDLVL_SHIFT (24U)
+/*! CMDLVL - CMDLVL
+ */
+#define SDIOC_MM4_STATE_CMDLVL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_CMDLVL_SHIFT)) & SDIOC_MM4_STATE_CMDLVL_MASK)
+#define SDIOC_MM4_STATE_UPRDATLVL_MASK (0x1E000000U)
+#define SDIOC_MM4_STATE_UPRDATLVL_SHIFT (25U)
+/*! UPRDATLVL - UPRDATLVL
+ */
+#define SDIOC_MM4_STATE_UPRDATLVL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_STATE_UPRDATLVL_SHIFT)) & SDIOC_MM4_STATE_UPRDATLVL_MASK)
+/*! @} */
+
+/*! @name MM4_CNTL1 - MMC4 Host Control Register 1 */
+/*! @{ */
+#define SDIOC_MM4_CNTL1_LEDCNTL_MASK (0x1U)
+#define SDIOC_MM4_CNTL1_LEDCNTL_SHIFT (0U)
+/*! LEDCNTL - LEDCNTL
+ */
+#define SDIOC_MM4_CNTL1_LEDCNTL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1_LEDCNTL_SHIFT)) & SDIOC_MM4_CNTL1_LEDCNTL_MASK)
+#define SDIOC_MM4_CNTL1__4BITMD_MASK (0x2U)
+#define SDIOC_MM4_CNTL1__4BITMD_SHIFT (1U)
+/*! _4BITMD - 4BITMD
+ */
+#define SDIOC_MM4_CNTL1__4BITMD(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1__4BITMD_SHIFT)) & SDIOC_MM4_CNTL1__4BITMD_MASK)
+#define SDIOC_MM4_CNTL1_HISPEED_MASK (0x4U)
+#define SDIOC_MM4_CNTL1_HISPEED_SHIFT (2U)
+/*! HISPEED - HISPEED
+ */
+#define SDIOC_MM4_CNTL1_HISPEED(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1_HISPEED_SHIFT)) & SDIOC_MM4_CNTL1_HISPEED_MASK)
+#define SDIOC_MM4_CNTL1__8BITMD_MASK (0x20U)
+#define SDIOC_MM4_CNTL1__8BITMD_SHIFT (5U)
+/*! _8BITMD - 8BITMD
+ */
+#define SDIOC_MM4_CNTL1__8BITMD(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1__8BITMD_SHIFT)) & SDIOC_MM4_CNTL1__8BITMD_MASK)
+#define SDIOC_MM4_CNTL1_BUSPWR_MASK (0x100U)
+#define SDIOC_MM4_CNTL1_BUSPWR_SHIFT (8U)
+/*! BUSPWR - BUSPWR
+ */
+#define SDIOC_MM4_CNTL1_BUSPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1_BUSPWR_SHIFT)) & SDIOC_MM4_CNTL1_BUSPWR_MASK)
+#define SDIOC_MM4_CNTL1_VLTGSEL_MASK (0xE00U)
+#define SDIOC_MM4_CNTL1_VLTGSEL_SHIFT (9U)
+/*! VLTGSEL - VLTGSEL
+ */
+#define SDIOC_MM4_CNTL1_VLTGSEL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1_VLTGSEL_SHIFT)) & SDIOC_MM4_CNTL1_VLTGSEL_MASK)
+#define SDIOC_MM4_CNTL1_BGREQSTP_MASK (0x10000U)
+#define SDIOC_MM4_CNTL1_BGREQSTP_SHIFT (16U)
+/*! BGREQSTP - BGREQSTP
+ */
+#define SDIOC_MM4_CNTL1_BGREQSTP(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1_BGREQSTP_SHIFT)) & SDIOC_MM4_CNTL1_BGREQSTP_MASK)
+#define SDIOC_MM4_CNTL1_CONTREQ_MASK (0x20000U)
+#define SDIOC_MM4_CNTL1_CONTREQ_SHIFT (17U)
+/*! CONTREQ - CONTREQ
+ */
+#define SDIOC_MM4_CNTL1_CONTREQ(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1_CONTREQ_SHIFT)) & SDIOC_MM4_CNTL1_CONTREQ_MASK)
+#define SDIOC_MM4_CNTL1_RDWTCNTL_MASK (0x40000U)
+#define SDIOC_MM4_CNTL1_RDWTCNTL_SHIFT (18U)
+/*! RDWTCNTL - RDWTCNTL
+ */
+#define SDIOC_MM4_CNTL1_RDWTCNTL(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1_RDWTCNTL_SHIFT)) & SDIOC_MM4_CNTL1_RDWTCNTL_MASK)
+#define SDIOC_MM4_CNTL1_BGIRQEN_MASK (0x80000U)
+#define SDIOC_MM4_CNTL1_BGIRQEN_SHIFT (19U)
+/*! BGIRQEN - BGIRQEN
+ */
+#define SDIOC_MM4_CNTL1_BGIRQEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL1_BGIRQEN_SHIFT)) & SDIOC_MM4_CNTL1_BGIRQEN_MASK)
+/*! @} */
+
+/*! @name MM4_CNTL2 - MMC4 Host Control Register 2 */
+/*! @{ */
+#define SDIOC_MM4_CNTL2_INTCLKEN_MASK (0x1U)
+#define SDIOC_MM4_CNTL2_INTCLKEN_SHIFT (0U)
+/*! INTCLKEN - INTCLKEN
+ */
+#define SDIOC_MM4_CNTL2_INTCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL2_INTCLKEN_SHIFT)) & SDIOC_MM4_CNTL2_INTCLKEN_MASK)
+#define SDIOC_MM4_CNTL2_MM4CLKEN_MASK (0x4U)
+#define SDIOC_MM4_CNTL2_MM4CLKEN_SHIFT (2U)
+/*! MM4CLKEN - MM4CLKEN
+ */
+#define SDIOC_MM4_CNTL2_MM4CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL2_MM4CLKEN_SHIFT)) & SDIOC_MM4_CNTL2_MM4CLKEN_MASK)
+#define SDIOC_MM4_CNTL2_SDFREQ_MASK (0xFF00U)
+#define SDIOC_MM4_CNTL2_SDFREQ_SHIFT (8U)
+/*! SDFREQ - SDFREQ
+ */
+#define SDIOC_MM4_CNTL2_SDFREQ(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL2_SDFREQ_SHIFT)) & SDIOC_MM4_CNTL2_SDFREQ_MASK)
+#define SDIOC_MM4_CNTL2_DTOCNTR_MASK (0xF0000U)
+#define SDIOC_MM4_CNTL2_DTOCNTR_SHIFT (16U)
+/*! DTOCNTR - DTOCNTR
+ */
+#define SDIOC_MM4_CNTL2_DTOCNTR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL2_DTOCNTR_SHIFT)) & SDIOC_MM4_CNTL2_DTOCNTR_MASK)
+#define SDIOC_MM4_CNTL2_MSWRST_MASK (0x1000000U)
+#define SDIOC_MM4_CNTL2_MSWRST_SHIFT (24U)
+/*! MSWRST - MSWRST
+ */
+#define SDIOC_MM4_CNTL2_MSWRST(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL2_MSWRST_SHIFT)) & SDIOC_MM4_CNTL2_MSWRST_MASK)
+#define SDIOC_MM4_CNTL2_CMDSWRST_MASK (0x2000000U)
+#define SDIOC_MM4_CNTL2_CMDSWRST_SHIFT (25U)
+/*! CMDSWRST - CMDSWRST
+ */
+#define SDIOC_MM4_CNTL2_CMDSWRST(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL2_CMDSWRST_SHIFT)) & SDIOC_MM4_CNTL2_CMDSWRST_MASK)
+#define SDIOC_MM4_CNTL2_DATSWRST_MASK (0x4000000U)
+#define SDIOC_MM4_CNTL2_DATSWRST_SHIFT (26U)
+/*! DATSWRST - DATSWRST
+ */
+#define SDIOC_MM4_CNTL2_DATSWRST(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CNTL2_DATSWRST_SHIFT)) & SDIOC_MM4_CNTL2_DATSWRST_MASK)
+/*! @} */
+
+/*! @name MM4_I_STAT - Align Detection Timeout Value Register */
+/*! @{ */
+#define SDIOC_MM4_I_STAT_CMDCOMP_MASK (0x1U)
+#define SDIOC_MM4_I_STAT_CMDCOMP_SHIFT (0U)
+/*! CMDCOMP - CMDCOMP
+ */
+#define SDIOC_MM4_I_STAT_CMDCOMP(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_CMDCOMP_SHIFT)) & SDIOC_MM4_I_STAT_CMDCOMP_MASK)
+#define SDIOC_MM4_I_STAT_XFRCOMP_MASK (0x2U)
+#define SDIOC_MM4_I_STAT_XFRCOMP_SHIFT (1U)
+/*! XFRCOMP - XFRCOMP
+ */
+#define SDIOC_MM4_I_STAT_XFRCOMP(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_XFRCOMP_SHIFT)) & SDIOC_MM4_I_STAT_XFRCOMP_MASK)
+#define SDIOC_MM4_I_STAT_BGEVNT_MASK (0x4U)
+#define SDIOC_MM4_I_STAT_BGEVNT_SHIFT (2U)
+/*! BGEVNT - BGEVNT
+ */
+#define SDIOC_MM4_I_STAT_BGEVNT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_BGEVNT_SHIFT)) & SDIOC_MM4_I_STAT_BGEVNT_MASK)
+#define SDIOC_MM4_I_STAT_DMAINT_MASK (0x8U)
+#define SDIOC_MM4_I_STAT_DMAINT_SHIFT (3U)
+/*! DMAINT - DMAINT
+ */
+#define SDIOC_MM4_I_STAT_DMAINT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_DMAINT_SHIFT)) & SDIOC_MM4_I_STAT_DMAINT_MASK)
+#define SDIOC_MM4_I_STAT_BUFWRRDY_MASK (0x10U)
+#define SDIOC_MM4_I_STAT_BUFWRRDY_SHIFT (4U)
+/*! BUFWRRDY - BUFWRRDY
+ */
+#define SDIOC_MM4_I_STAT_BUFWRRDY(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_BUFWRRDY_SHIFT)) & SDIOC_MM4_I_STAT_BUFWRRDY_MASK)
+#define SDIOC_MM4_I_STAT_BUFRDRDY_MASK (0x20U)
+#define SDIOC_MM4_I_STAT_BUFRDRDY_SHIFT (5U)
+/*! BUFRDRDY - BUFRDRDY
+ */
+#define SDIOC_MM4_I_STAT_BUFRDRDY(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_BUFRDRDY_SHIFT)) & SDIOC_MM4_I_STAT_BUFRDRDY_MASK)
+#define SDIOC_MM4_I_STAT_CDINS_MASK (0x40U)
+#define SDIOC_MM4_I_STAT_CDINS_SHIFT (6U)
+/*! CDINS - CDINS
+ */
+#define SDIOC_MM4_I_STAT_CDINS(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_CDINS_SHIFT)) & SDIOC_MM4_I_STAT_CDINS_MASK)
+#define SDIOC_MM4_I_STAT_CDREM_MASK (0x80U)
+#define SDIOC_MM4_I_STAT_CDREM_SHIFT (7U)
+/*! CDREM - CDREM
+ */
+#define SDIOC_MM4_I_STAT_CDREM(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_CDREM_SHIFT)) & SDIOC_MM4_I_STAT_CDREM_MASK)
+#define SDIOC_MM4_I_STAT_CDINT_MASK (0x100U)
+#define SDIOC_MM4_I_STAT_CDINT_SHIFT (8U)
+/*! CDINT - CDINT
+ */
+#define SDIOC_MM4_I_STAT_CDINT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_CDINT_SHIFT)) & SDIOC_MM4_I_STAT_CDINT_MASK)
+#define SDIOC_MM4_I_STAT_ERRINT_MASK (0x8000U)
+#define SDIOC_MM4_I_STAT_ERRINT_SHIFT (15U)
+/*! ERRINT - ERRINT
+ */
+#define SDIOC_MM4_I_STAT_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_ERRINT_SHIFT)) & SDIOC_MM4_I_STAT_ERRINT_MASK)
+#define SDIOC_MM4_I_STAT_CTOERR_MASK (0x10000U)
+#define SDIOC_MM4_I_STAT_CTOERR_SHIFT (16U)
+/*! CTOERR - CTOERR
+ */
+#define SDIOC_MM4_I_STAT_CTOERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_CTOERR_SHIFT)) & SDIOC_MM4_I_STAT_CTOERR_MASK)
+#define SDIOC_MM4_I_STAT_CCRCERR_MASK (0x20000U)
+#define SDIOC_MM4_I_STAT_CCRCERR_SHIFT (17U)
+/*! CCRCERR - CCRCERR
+ */
+#define SDIOC_MM4_I_STAT_CCRCERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_CCRCERR_SHIFT)) & SDIOC_MM4_I_STAT_CCRCERR_MASK)
+#define SDIOC_MM4_I_STAT_CENDERR_MASK (0x40000U)
+#define SDIOC_MM4_I_STAT_CENDERR_SHIFT (18U)
+/*! CENDERR - CENDERR
+ */
+#define SDIOC_MM4_I_STAT_CENDERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_CENDERR_SHIFT)) & SDIOC_MM4_I_STAT_CENDERR_MASK)
+#define SDIOC_MM4_I_STAT_CIDXERR_MASK (0x80000U)
+#define SDIOC_MM4_I_STAT_CIDXERR_SHIFT (19U)
+/*! CIDXERR - CIDXERR
+ */
+#define SDIOC_MM4_I_STAT_CIDXERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_CIDXERR_SHIFT)) & SDIOC_MM4_I_STAT_CIDXERR_MASK)
+#define SDIOC_MM4_I_STAT_DTOERR_MASK (0x100000U)
+#define SDIOC_MM4_I_STAT_DTOERR_SHIFT (20U)
+/*! DTOERR - DTOERR
+ */
+#define SDIOC_MM4_I_STAT_DTOERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_DTOERR_SHIFT)) & SDIOC_MM4_I_STAT_DTOERR_MASK)
+#define SDIOC_MM4_I_STAT_DCRCERR_MASK (0x200000U)
+#define SDIOC_MM4_I_STAT_DCRCERR_SHIFT (21U)
+/*! DCRCERR - DCRCERR
+ */
+#define SDIOC_MM4_I_STAT_DCRCERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_DCRCERR_SHIFT)) & SDIOC_MM4_I_STAT_DCRCERR_MASK)
+#define SDIOC_MM4_I_STAT_DENDERR_MASK (0x400000U)
+#define SDIOC_MM4_I_STAT_DENDERR_SHIFT (22U)
+/*! DENDERR - DENDERR
+ */
+#define SDIOC_MM4_I_STAT_DENDERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_DENDERR_SHIFT)) & SDIOC_MM4_I_STAT_DENDERR_MASK)
+#define SDIOC_MM4_I_STAT_ILMTERR_MASK (0x800000U)
+#define SDIOC_MM4_I_STAT_ILMTERR_SHIFT (23U)
+/*! ILMTERR - ILMTERR
+ */
+#define SDIOC_MM4_I_STAT_ILMTERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_ILMTERR_SHIFT)) & SDIOC_MM4_I_STAT_ILMTERR_MASK)
+#define SDIOC_MM4_I_STAT_AC12ERR_MASK (0x1000000U)
+#define SDIOC_MM4_I_STAT_AC12ERR_SHIFT (24U)
+/*! AC12ERR - AC12ERR
+ */
+#define SDIOC_MM4_I_STAT_AC12ERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_AC12ERR_SHIFT)) & SDIOC_MM4_I_STAT_AC12ERR_MASK)
+#define SDIOC_MM4_I_STAT_AHBTERR_MASK (0x10000000U)
+#define SDIOC_MM4_I_STAT_AHBTERR_SHIFT (28U)
+/*! AHBTERR - AHBTERR
+ */
+#define SDIOC_MM4_I_STAT_AHBTERR(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_AHBTERR_SHIFT)) & SDIOC_MM4_I_STAT_AHBTERR_MASK)
+/*! @} */
+
+/*! @name MM4_I_STAT_EN - MMC4 Interrupt Status Enable Register */
+/*! @{ */
+#define SDIOC_MM4_I_STAT_EN_CMDCOMPSTEN_MASK (0x1U)
+#define SDIOC_MM4_I_STAT_EN_CMDCOMPSTEN_SHIFT (0U)
+/*! CMDCOMPSTEN - CMDCOMPSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_CMDCOMPSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_CMDCOMPSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_CMDCOMPSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_XFRCOMPSTEN_MASK (0x2U)
+#define SDIOC_MM4_I_STAT_EN_XFRCOMPSTEN_SHIFT (1U)
+/*! XFRCOMPSTEN - XFRCOMPSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_XFRCOMPSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_XFRCOMPSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_XFRCOMPSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_BGEVNTSTEN_MASK (0x4U)
+#define SDIOC_MM4_I_STAT_EN_BGEVNTSTEN_SHIFT (2U)
+/*! BGEVNTSTEN - BGEVNTSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_BGEVNTSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_BGEVNTSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_BGEVNTSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_DMAINTSTEN_MASK (0x8U)
+#define SDIOC_MM4_I_STAT_EN_DMAINTSTEN_SHIFT (3U)
+/*! DMAINTSTEN - DMAINTSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_DMAINTSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_DMAINTSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_DMAINTSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_BUFWRRDYSTEN_MASK (0x10U)
+#define SDIOC_MM4_I_STAT_EN_BUFWRRDYSTEN_SHIFT (4U)
+/*! BUFWRRDYSTEN - BUFWRRDYSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_BUFWRRDYSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_BUFWRRDYSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_BUFWRRDYSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_BUFRDRDYSTEN_MASK (0x20U)
+#define SDIOC_MM4_I_STAT_EN_BUFRDRDYSTEN_SHIFT (5U)
+/*! BUFRDRDYSTEN - BUFRDRDYSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_BUFRDRDYSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_BUFRDRDYSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_BUFRDRDYSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_CDINSSTEN_MASK (0x40U)
+#define SDIOC_MM4_I_STAT_EN_CDINSSTEN_SHIFT (6U)
+/*! CDINSSTEN - CDINSSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_CDINSSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_CDINSSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_CDINSSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_CDREMSTEN_MASK (0x80U)
+#define SDIOC_MM4_I_STAT_EN_CDREMSTEN_SHIFT (7U)
+/*! CDREMSTEN - CDREMSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_CDREMSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_CDREMSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_CDREMSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_CDINTSTEN_MASK (0x100U)
+#define SDIOC_MM4_I_STAT_EN_CDINTSTEN_SHIFT (8U)
+/*! CDINTSTEN - CDINTSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_CDINTSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_CDINTSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_CDINTSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_CTOSTEN_MASK (0x10000U)
+#define SDIOC_MM4_I_STAT_EN_CTOSTEN_SHIFT (16U)
+/*! CTOSTEN - CTOSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_CTOSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_CTOSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_CTOSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_CCRCSTEN_MASK (0x20000U)
+#define SDIOC_MM4_I_STAT_EN_CCRCSTEN_SHIFT (17U)
+/*! CCRCSTEN - CCRCSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_CCRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_CCRCSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_CCRCSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_CENDSTEN_MASK (0x40000U)
+#define SDIOC_MM4_I_STAT_EN_CENDSTEN_SHIFT (18U)
+/*! CENDSTEN - CENDSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_CENDSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_CENDSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_CENDSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_CIDXSTEN_MASK (0x80000U)
+#define SDIOC_MM4_I_STAT_EN_CIDXSTEN_SHIFT (19U)
+/*! CIDXSTEN - CIDXSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_CIDXSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_CIDXSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_CIDXSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_DTOSTEN_MASK (0x100000U)
+#define SDIOC_MM4_I_STAT_EN_DTOSTEN_SHIFT (20U)
+/*! DTOSTEN - DTOSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_DTOSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_DTOSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_DTOSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_DCRCSTEN_MASK (0x200000U)
+#define SDIOC_MM4_I_STAT_EN_DCRCSTEN_SHIFT (21U)
+/*! DCRCSTEN - DCRCSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_DCRCSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_DCRCSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_DCRCSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_DENDSTEN_MASK (0x400000U)
+#define SDIOC_MM4_I_STAT_EN_DENDSTEN_SHIFT (22U)
+/*! DENDSTEN - DENDSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_DENDSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_DENDSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_DENDSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_ILMTSTEN_MASK (0x800000U)
+#define SDIOC_MM4_I_STAT_EN_ILMTSTEN_SHIFT (23U)
+/*! ILMTSTEN - ILMTSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_ILMTSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_ILMTSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_ILMTSTEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_AC12STEN_MASK (0x1000000U)
+#define SDIOC_MM4_I_STAT_EN_AC12STEN_SHIFT (24U)
+/*! AC12STEN - AC12STEN
+ */
+#define SDIOC_MM4_I_STAT_EN_AC12STEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_AC12STEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_AC12STEN_MASK)
+#define SDIOC_MM4_I_STAT_EN_ATERRSTEN_MASK (0x10000000U)
+#define SDIOC_MM4_I_STAT_EN_ATERRSTEN_SHIFT (28U)
+/*! ATERRSTEN - ATERRSTEN
+ */
+#define SDIOC_MM4_I_STAT_EN_ATERRSTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_STAT_EN_ATERRSTEN_SHIFT)) & SDIOC_MM4_I_STAT_EN_ATERRSTEN_MASK)
+/*! @} */
+
+/*! @name MM4_I_SIG_EN - MMC4 Interrupt Signal Enable Register */
+/*! @{ */
+#define SDIOC_MM4_I_SIG_EN_CMDCOMPSGEN_MASK (0x1U)
+#define SDIOC_MM4_I_SIG_EN_CMDCOMPSGEN_SHIFT (0U)
+/*! CMDCOMPSGEN - CMDCOMPSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_CMDCOMPSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_CMDCOMPSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_CMDCOMPSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_XFRCOMPSGEN_MASK (0x2U)
+#define SDIOC_MM4_I_SIG_EN_XFRCOMPSGEN_SHIFT (1U)
+/*! XFRCOMPSGEN - XFRCOMPSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_XFRCOMPSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_XFRCOMPSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_XFRCOMPSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_BGEVNTSGEN_MASK (0x4U)
+#define SDIOC_MM4_I_SIG_EN_BGEVNTSGEN_SHIFT (2U)
+/*! BGEVNTSGEN - BGEVNTSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_BGEVNTSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_BGEVNTSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_BGEVNTSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_DMAINTSGEN_MASK (0x8U)
+#define SDIOC_MM4_I_SIG_EN_DMAINTSGEN_SHIFT (3U)
+/*! DMAINTSGEN - DMAINTSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_DMAINTSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_DMAINTSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_DMAINTSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_BUFWRRDYSGEN_MASK (0x10U)
+#define SDIOC_MM4_I_SIG_EN_BUFWRRDYSGEN_SHIFT (4U)
+/*! BUFWRRDYSGEN - BUFWRRDYSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_BUFWRRDYSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_BUFWRRDYSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_BUFWRRDYSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_BUFRDRDYSGEN_MASK (0x20U)
+#define SDIOC_MM4_I_SIG_EN_BUFRDRDYSGEN_SHIFT (5U)
+/*! BUFRDRDYSGEN - BUFRDRDYSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_BUFRDRDYSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_BUFRDRDYSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_BUFRDRDYSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_CDINSSGEN_MASK (0x40U)
+#define SDIOC_MM4_I_SIG_EN_CDINSSGEN_SHIFT (6U)
+/*! CDINSSGEN - CDINSSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_CDINSSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_CDINSSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_CDINSSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_CDREMSGEN_MASK (0x80U)
+#define SDIOC_MM4_I_SIG_EN_CDREMSGEN_SHIFT (7U)
+/*! CDREMSGEN - CDREMSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_CDREMSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_CDREMSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_CDREMSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_CDINTSGEN_MASK (0x100U)
+#define SDIOC_MM4_I_SIG_EN_CDINTSGEN_SHIFT (8U)
+/*! CDINTSGEN - CDINTSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_CDINTSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_CDINTSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_CDINTSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_CTOSGEN_MASK (0x10000U)
+#define SDIOC_MM4_I_SIG_EN_CTOSGEN_SHIFT (16U)
+/*! CTOSGEN - CTOSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_CTOSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_CTOSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_CTOSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_CCRCSGEN_MASK (0x20000U)
+#define SDIOC_MM4_I_SIG_EN_CCRCSGEN_SHIFT (17U)
+/*! CCRCSGEN - CCRCSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_CCRCSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_CCRCSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_CCRCSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_CENDSGEN_MASK (0x40000U)
+#define SDIOC_MM4_I_SIG_EN_CENDSGEN_SHIFT (18U)
+/*! CENDSGEN - CENDSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_CENDSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_CENDSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_CENDSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_CIDXSGEN_MASK (0x80000U)
+#define SDIOC_MM4_I_SIG_EN_CIDXSGEN_SHIFT (19U)
+/*! CIDXSGEN - CIDXSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_CIDXSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_CIDXSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_CIDXSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_DTOSGEN_MASK (0x100000U)
+#define SDIOC_MM4_I_SIG_EN_DTOSGEN_SHIFT (20U)
+/*! DTOSGEN - DTOSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_DTOSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_DTOSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_DTOSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_DCRCSGEN_MASK (0x200000U)
+#define SDIOC_MM4_I_SIG_EN_DCRCSGEN_SHIFT (21U)
+/*! DCRCSGEN - DCRCSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_DCRCSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_DCRCSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_DCRCSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_DENDSGEN_MASK (0x400000U)
+#define SDIOC_MM4_I_SIG_EN_DENDSGEN_SHIFT (22U)
+/*! DENDSGEN - DENDSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_DENDSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_DENDSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_DENDSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_ILMTSGEN_MASK (0x800000U)
+#define SDIOC_MM4_I_SIG_EN_ILMTSGEN_SHIFT (23U)
+/*! ILMTSGEN - ILMTSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_ILMTSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_ILMTSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_ILMTSGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_AC12SGEN_MASK (0x1000000U)
+#define SDIOC_MM4_I_SIG_EN_AC12SGEN_SHIFT (24U)
+/*! AC12SGEN - AC12SGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_AC12SGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_AC12SGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_AC12SGEN_MASK)
+#define SDIOC_MM4_I_SIG_EN_ATERRSGEN_MASK (0x10000000U)
+#define SDIOC_MM4_I_SIG_EN_ATERRSGEN_SHIFT (28U)
+/*! ATERRSGEN - ATERRSGEN
+ */
+#define SDIOC_MM4_I_SIG_EN_ATERRSGEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_I_SIG_EN_ATERRSGEN_SHIFT)) & SDIOC_MM4_I_SIG_EN_ATERRSGEN_MASK)
+/*! @} */
+
+/*! @name MM4_ACMD12_ER - MMC4 Auto CMD12 Error Status Register */
+/*! @{ */
+#define SDIOC_MM4_ACMD12_ER_AC12NEXE_MASK (0x1U)
+#define SDIOC_MM4_ACMD12_ER_AC12NEXE_SHIFT (0U)
+/*! AC12NEXE - AC12NEXE
+ */
+#define SDIOC_MM4_ACMD12_ER_AC12NEXE(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_ACMD12_ER_AC12NEXE_SHIFT)) & SDIOC_MM4_ACMD12_ER_AC12NEXE_MASK)
+#define SDIOC_MM4_ACMD12_ER_AC12TOER_MASK (0x2U)
+#define SDIOC_MM4_ACMD12_ER_AC12TOER_SHIFT (1U)
+/*! AC12TOER - AC12TOER
+ */
+#define SDIOC_MM4_ACMD12_ER_AC12TOER(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_ACMD12_ER_AC12TOER_SHIFT)) & SDIOC_MM4_ACMD12_ER_AC12TOER_MASK)
+#define SDIOC_MM4_ACMD12_ER_AC12CRCER_MASK (0x4U)
+#define SDIOC_MM4_ACMD12_ER_AC12CRCER_SHIFT (2U)
+/*! AC12CRCER - AC12CRCER
+ */
+#define SDIOC_MM4_ACMD12_ER_AC12CRCER(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_ACMD12_ER_AC12CRCER_SHIFT)) & SDIOC_MM4_ACMD12_ER_AC12CRCER_MASK)
+#define SDIOC_MM4_ACMD12_ER_AC12ENDER_MASK (0x8U)
+#define SDIOC_MM4_ACMD12_ER_AC12ENDER_SHIFT (3U)
+/*! AC12ENDER - AC12ENDER
+ */
+#define SDIOC_MM4_ACMD12_ER_AC12ENDER(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_ACMD12_ER_AC12ENDER_SHIFT)) & SDIOC_MM4_ACMD12_ER_AC12ENDER_MASK)
+#define SDIOC_MM4_ACMD12_ER_AC12IDXER_MASK (0x10U)
+#define SDIOC_MM4_ACMD12_ER_AC12IDXER_SHIFT (4U)
+/*! AC12IDXER - AC12IDXER
+ */
+#define SDIOC_MM4_ACMD12_ER_AC12IDXER(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_ACMD12_ER_AC12IDXER_SHIFT)) & SDIOC_MM4_ACMD12_ER_AC12IDXER_MASK)
+#define SDIOC_MM4_ACMD12_ER_CMDNISUD_MASK (0x80U)
+#define SDIOC_MM4_ACMD12_ER_CMDNISUD_SHIFT (7U)
+/*! CMDNISUD - CMDNISUD
+ */
+#define SDIOC_MM4_ACMD12_ER_CMDNISUD(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_ACMD12_ER_CMDNISUD_SHIFT)) & SDIOC_MM4_ACMD12_ER_CMDNISUD_MASK)
+/*! @} */
+
+/*! @name MM4_CAP0 - MMC4 Capabilities Register 0 */
+/*! @{ */
+#define SDIOC_MM4_CAP0_TOCLKFREQ_MASK (0x3FU)
+#define SDIOC_MM4_CAP0_TOCLKFREQ_SHIFT (0U)
+/*! TOCLKFREQ - TOCLKFREQ
+ */
+#define SDIOC_MM4_CAP0_TOCLKFREQ(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0_TOCLKFREQ_SHIFT)) & SDIOC_MM4_CAP0_TOCLKFREQ_MASK)
+#define SDIOC_MM4_CAP0_TOCLKUNIT_MASK (0x80U)
+#define SDIOC_MM4_CAP0_TOCLKUNIT_SHIFT (7U)
+/*! TOCLKUNIT - TOCLKUNIT
+ */
+#define SDIOC_MM4_CAP0_TOCLKUNIT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0_TOCLKUNIT_SHIFT)) & SDIOC_MM4_CAP0_TOCLKUNIT_MASK)
+#define SDIOC_MM4_CAP0_BSCLKFREQ_MASK (0x3F00U)
+#define SDIOC_MM4_CAP0_BSCLKFREQ_SHIFT (8U)
+/*! BSCLKFREQ - BSCLKFREQ
+ */
+#define SDIOC_MM4_CAP0_BSCLKFREQ(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0_BSCLKFREQ_SHIFT)) & SDIOC_MM4_CAP0_BSCLKFREQ_MASK)
+#define SDIOC_MM4_CAP0_MAXBLEN_MASK (0x30000U)
+#define SDIOC_MM4_CAP0_MAXBLEN_SHIFT (16U)
+/*! MAXBLEN - MAXBLEN
+ */
+#define SDIOC_MM4_CAP0_MAXBLEN(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0_MAXBLEN_SHIFT)) & SDIOC_MM4_CAP0_MAXBLEN_MASK)
+#define SDIOC_MM4_CAP0_HISPDSPRT_MASK (0x200000U)
+#define SDIOC_MM4_CAP0_HISPDSPRT_SHIFT (21U)
+/*! HISPDSPRT - HISPDSPRT
+ */
+#define SDIOC_MM4_CAP0_HISPDSPRT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0_HISPDSPRT_SHIFT)) & SDIOC_MM4_CAP0_HISPDSPRT_MASK)
+#define SDIOC_MM4_CAP0_DMASPRT_MASK (0x400000U)
+#define SDIOC_MM4_CAP0_DMASPRT_SHIFT (22U)
+/*! DMASPRT - DMASPRT
+ */
+#define SDIOC_MM4_CAP0_DMASPRT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0_DMASPRT_SHIFT)) & SDIOC_MM4_CAP0_DMASPRT_MASK)
+#define SDIOC_MM4_CAP0_SUSP_RES_MASK (0x800000U)
+#define SDIOC_MM4_CAP0_SUSP_RES_SHIFT (23U)
+/*! SUSP_RES - SUSP/RES
+ */
+#define SDIOC_MM4_CAP0_SUSP_RES(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0_SUSP_RES_SHIFT)) & SDIOC_MM4_CAP0_SUSP_RES_MASK)
+#define SDIOC_MM4_CAP0__3_3VSPRT_MASK (0x1000000U)
+#define SDIOC_MM4_CAP0__3_3VSPRT_SHIFT (24U)
+/*! _3_3VSPRT - 3.3VSPRT
+ */
+#define SDIOC_MM4_CAP0__3_3VSPRT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0__3_3VSPRT_SHIFT)) & SDIOC_MM4_CAP0__3_3VSPRT_MASK)
+#define SDIOC_MM4_CAP0__3_0VSPRT_MASK (0x2000000U)
+#define SDIOC_MM4_CAP0__3_0VSPRT_SHIFT (25U)
+/*! _3_0VSPRT - 3.0VSPRT
+ */
+#define SDIOC_MM4_CAP0__3_0VSPRT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0__3_0VSPRT_SHIFT)) & SDIOC_MM4_CAP0__3_0VSPRT_MASK)
+#define SDIOC_MM4_CAP0__1_8VSPRT_MASK (0x4000000U)
+#define SDIOC_MM4_CAP0__1_8VSPRT_SHIFT (26U)
+/*! _1_8VSPRT - 1.8VSPRT
+ */
+#define SDIOC_MM4_CAP0__1_8VSPRT(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0__1_8VSPRT_SHIFT)) & SDIOC_MM4_CAP0__1_8VSPRT_MASK)
+#define SDIOC_MM4_CAP0_IRQMODE_MASK (0x8000000U)
+#define SDIOC_MM4_CAP0_IRQMODE_SHIFT (27U)
+/*! IRQMODE - IRQMODE
+ */
+#define SDIOC_MM4_CAP0_IRQMODE(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CAP0_IRQMODE_SHIFT)) & SDIOC_MM4_CAP0_IRQMODE_MASK)
+/*! @} */
+
+/*! @name MM4_CUR_CAP0 - MMC4 Maximum Current Capabilities Register 0 */
+/*! @{ */
+#define SDIOC_MM4_CUR_CAP0__3_3VMAXI_MASK (0xFFU)
+#define SDIOC_MM4_CUR_CAP0__3_3VMAXI_SHIFT (0U)
+/*! _3_3VMAXI - 3.3VMAXI
+ */
+#define SDIOC_MM4_CUR_CAP0__3_3VMAXI(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CUR_CAP0__3_3VMAXI_SHIFT)) & SDIOC_MM4_CUR_CAP0__3_3VMAXI_MASK)
+#define SDIOC_MM4_CUR_CAP0__3_0VMAXI_MASK (0xFF00U)
+#define SDIOC_MM4_CUR_CAP0__3_0VMAXI_SHIFT (8U)
+/*! _3_0VMAXI - 3.0VMAXI
+ */
+#define SDIOC_MM4_CUR_CAP0__3_0VMAXI(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CUR_CAP0__3_0VMAXI_SHIFT)) & SDIOC_MM4_CUR_CAP0__3_0VMAXI_MASK)
+#define SDIOC_MM4_CUR_CAP0__1_8VMAXI_MASK (0xFF0000U)
+#define SDIOC_MM4_CUR_CAP0__1_8VMAXI_SHIFT (16U)
+/*! _1_8VMAXI - 1.8VMAXI
+ */
+#define SDIOC_MM4_CUR_CAP0__1_8VMAXI(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_CUR_CAP0__1_8VMAXI_SHIFT)) & SDIOC_MM4_CUR_CAP0__1_8VMAXI_MASK)
+/*! @} */
+
+/*! @name MM4_VER - MMC4 Controller Version Status */
+/*! @{ */
+#define SDIOC_MM4_VER_SPECVER_MASK (0xFF0000U)
+#define SDIOC_MM4_VER_SPECVER_SHIFT (16U)
+/*! SPECVER - SPECVER
+ */
+#define SDIOC_MM4_VER_SPECVER(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_VER_SPECVER_SHIFT)) & SDIOC_MM4_VER_SPECVER_MASK)
+#define SDIOC_MM4_VER_VNDRVER_MASK (0xFF000000U)
+#define SDIOC_MM4_VER_VNDRVER_SHIFT (24U)
+/*! VNDRVER - VNDRVER
+ */
+#define SDIOC_MM4_VER_VNDRVER(x) (((uint32_t)(((uint32_t)(x)) << SDIOC_MM4_VER_VNDRVER_SHIFT)) & SDIOC_MM4_VER_VNDRVER_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SDIOC_Register_Masks */
+
+
+/* SDIOC - Peripheral instance base addresses */
+/** Peripheral SDIOC base address */
+#define SDIOC_BASE (0x44002000u)
+/** Peripheral SDIOC base pointer */
+#define SDIOC ((SDIOC_Type *)SDIOC_BASE)
+/** Array initializer of SDIOC peripheral base addresses */
+#define SDIOC_BASE_ADDRS { SDIOC_BASE }
+/** Array initializer of SDIOC peripheral base pointers */
+#define SDIOC_BASE_PTRS { SDIOC }
+/** Interrupt vectors for the SDIOC peripheral type */
+#define SDIOC_IRQS { SDIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDIOC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SSP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SSP_Peripheral_Access_Layer SSP Peripheral Access Layer
+ * @{
+ */
+
+/** SSP - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SSP_SSCR0; /**< SSP Control Register 0, offset: 0x0 */
+ __IO uint32_t SSP_SSCR1; /**< SSP Control Register 1, offset: 0x4 */
+ __IO uint32_t SSP_SSSR; /**< SSP Status Register, offset: 0x8 */
+ __IO uint32_t SSP_SSITR; /**< SSP Interrupt Test Register, offset: 0xC */
+ __IO uint32_t SSP_SSDR; /**< SSP Data Register, offset: 0x10 */
+ uint8_t RESERVED_0[20];
+ __IO uint32_t SSP_SSTO; /**< SSP Time Out Register, offset: 0x28 */
+ __IO uint32_t SSP_SSPSP; /**< SSP Programmable Serial Protocol Register, offset: 0x2C */
+ __IO uint32_t SSP_SSTSA; /**< SSP TX Time Slot Active Register, offset: 0x30 */
+ __IO uint32_t SSP_SSRSA; /**< SSP RX Time Slot Active Register, offset: 0x34 */
+ __I uint32_t SSP_SSTSS; /**< SSP Time Slot Status Register, offset: 0x38 */
+ __IO uint32_t SSP_SSACD; /**< SSP Audio Clock Divider Register, offset: 0x3C */
+ __IO uint32_t SSP_SSACDD; /**< SSP Audio Clock Dither Divider Register, offset: 0x40 */
+} SSP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SSP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SSP_Register_Masks SSP Register Masks
+ * @{
+ */
+
+/*! @name SSP_SSCR0 - SSP Control Register 0 */
+/*! @{ */
+#define SSP_SSP_SSCR0_DSS_MASK (0xFU)
+#define SSP_SSP_SSCR0_DSS_SHIFT (0U)
+/*! DSS - Data Size Select
+ */
+#define SSP_SSP_SSCR0_DSS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_DSS_SHIFT)) & SSP_SSP_SSCR0_DSS_MASK)
+#define SSP_SSP_SSCR0_FRF_MASK (0x30U)
+#define SSP_SSP_SSCR0_FRF_SHIFT (4U)
+/*! FRF - Frame Format
+ * 0b00..Motorola* Serial Peripheral Interface (SPI)
+ * 0b01..Texas Instruments* Synchronous Serial Protocol (SSP)
+ * 0b10..National Semiconductor Microwire*
+ * 0b11..Programmable Serial Protocol (PSP)
+ */
+#define SSP_SSP_SSCR0_FRF(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_FRF_SHIFT)) & SSP_SSP_SSCR0_FRF_MASK)
+#define SSP_SSP_SSCR0_ECS_MASK (0x40U)
+#define SSP_SSP_SSCR0_ECS_SHIFT (6U)
+/*! ECS - External Clock Select
+ * 0b0..On-chip SSPx Clock is used in the serial clock rate formula (above) to produce the SSPx port's SSPSCLKx
+ * 0b1..SSPEXTCLKx (GPIO pin) is used in the serial clock rate formula to produce the SSPx port's SSPSCLKx
+ */
+#define SSP_SSP_SSCR0_ECS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_ECS_SHIFT)) & SSP_SSP_SSCR0_ECS_MASK)
+#define SSP_SSP_SSCR0_SSE_MASK (0x80U)
+#define SSP_SSP_SSCR0_SSE_SHIFT (7U)
+/*! SSE - Synchronous Serial Port Enable
+ * 0b0..SSPx port is disabled
+ * 0b1..SSPx port is enabled
+ */
+#define SSP_SSP_SSCR0_SSE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_SSE_SHIFT)) & SSP_SSP_SSCR0_SSE_MASK)
+#define SSP_SSP_SSCR0_SCR_MASK (0xFFF00U)
+#define SSP_SSP_SSCR0_SCR_SHIFT (8U)
+/*! SCR - Serial Clock Rate
+ */
+#define SSP_SSP_SSCR0_SCR(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_SCR_SHIFT)) & SSP_SSP_SSCR0_SCR_MASK)
+#define SSP_SSP_SSCR0_EDSS_MASK (0x100000U)
+#define SSP_SSP_SSCR0_EDSS_SHIFT (20U)
+/*! EDSS - Extended Data Size Select
+ * 0b0..A 0 is pre-appended to the DSS value to set the DSS range from 8 to 16 bits.
+ * 0b1..A 1 is pre-appended to the DSS value to set the DSS range from 18 to 32 bits.
+ */
+#define SSP_SSP_SSCR0_EDSS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_EDSS_SHIFT)) & SSP_SSP_SSCR0_EDSS_MASK)
+#define SSP_SSP_SSCR0_NCS_MASK (0x200000U)
+#define SSP_SSP_SSCR0_NCS_SHIFT (21U)
+/*! NCS - Network Clock Select
+ * 0b0..Clock selection is determined by the field
+ * 0b1..Network clock is used to create the SSP's serial clock (SSPSCLKx)
+ */
+#define SSP_SSP_SSCR0_NCS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_NCS_SHIFT)) & SSP_SSP_SSCR0_NCS_MASK)
+#define SSP_SSP_SSCR0_RIM_MASK (0x400000U)
+#define SSP_SSP_SSCR0_RIM_SHIFT (22U)
+/*! RIM - Receive FIFO Overrun Interrupt Mask
+ * 0b0..ROR events generate an SSP interrupt
+ * 0b1..ROR events do NOT generate an SSP interrupt
+ */
+#define SSP_SSP_SSCR0_RIM(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_RIM_SHIFT)) & SSP_SSP_SSCR0_RIM_MASK)
+#define SSP_SSP_SSCR0_TIM_MASK (0x800000U)
+#define SSP_SSP_SSCR0_TIM_SHIFT (23U)
+/*! TIM - Transmit FIFO Underrun Interrupt Mask
+ * 0b0..TUR events generate an SSP interrupt
+ * 0b1..TUR events do NOT generate an SSP interrupt
+ */
+#define SSP_SSP_SSCR0_TIM(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_TIM_SHIFT)) & SSP_SSP_SSCR0_TIM_MASK)
+#define SSP_SSP_SSCR0_FRDC_MASK (0x7000000U)
+#define SSP_SSP_SSCR0_FRDC_SHIFT (24U)
+/*! FRDC - Frame Rate Divider Control
+ */
+#define SSP_SSP_SSCR0_FRDC(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_FRDC_SHIFT)) & SSP_SSP_SSCR0_FRDC_MASK)
+#define SSP_SSP_SSCR0_MCRT_MASK (0x8000000U)
+#define SSP_SSP_SSCR0_MCRT_SHIFT (27U)
+/*! MCRT - Master Clock Return
+ * 0b0..not seclect master return_clock
+ * 0b1..master clock delay
+ */
+#define SSP_SSP_SSCR0_MCRT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_MCRT_SHIFT)) & SSP_SSP_SSCR0_MCRT_MASK)
+#define SSP_SSP_SSCR0_RHCD_MASK (0x10000000U)
+#define SSP_SSP_SSCR0_RHCD_SHIFT (28U)
+/*! RHCD - RX half cycle delay
+ * 0b0..not seclect RX half cycle delay
+ * 0b1..receive data delay half cycle
+ */
+#define SSP_SSP_SSCR0_RHCD(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_RHCD_SHIFT)) & SSP_SSP_SSCR0_RHCD_MASK)
+#define SSP_SSP_SSCR0_FPCKE_MASK (0x20000000U)
+#define SSP_SSP_SSCR0_FPCKE_SHIFT (29U)
+/*! FPCKE - FIFO Packing Enable
+ * 0b0..FIFO packing mode disabled
+ * 0b1..FIFO packing mode enabled
+ */
+#define SSP_SSP_SSCR0_FPCKE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_FPCKE_SHIFT)) & SSP_SSP_SSCR0_FPCKE_MASK)
+#define SSP_SSP_SSCR0_ACS_MASK (0x40000000U)
+#define SSP_SSP_SSCR0_ACS_SHIFT (30U)
+/*! ACS - Audio Clock Select
+ * 0b0..Clock selection is determined by the and fields
+ * 0b1..Audio clock (and audio clock divider) are used to create the SSP serial bit clock (SSPSCLKx)
+ */
+#define SSP_SSP_SSCR0_ACS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_ACS_SHIFT)) & SSP_SSP_SSCR0_ACS_MASK)
+#define SSP_SSP_SSCR0_MOD_MASK (0x80000000U)
+#define SSP_SSP_SSCR0_MOD_SHIFT (31U)
+/*! MOD - Mode
+ * 0b0..Normal SSP mode
+ * 0b1..Network mode
+ */
+#define SSP_SSP_SSCR0_MOD(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR0_MOD_SHIFT)) & SSP_SSP_SSCR0_MOD_MASK)
+/*! @} */
+
+/*! @name SSP_SSCR1 - SSP Control Register 1 */
+/*! @{ */
+#define SSP_SSP_SSCR1_RIE_MASK (0x1U)
+#define SSP_SSP_SSCR1_RIE_SHIFT (0U)
+/*! RIE - Receive FIFO Interrupt Enable
+ * 0b0..RXFIFO threshold-level-reached interrupt is disabled.
+ * 0b1..RXFIFO threshold-level-reached interrupt is enabled.
+ */
+#define SSP_SSP_SSCR1_RIE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_RIE_SHIFT)) & SSP_SSP_SSCR1_RIE_MASK)
+#define SSP_SSP_SSCR1_TIE_MASK (0x2U)
+#define SSP_SSP_SSCR1_TIE_SHIFT (1U)
+/*! TIE - Transmit FIFO Interrupt Enable
+ * 0b0..TXFIFO threshold-level-reached interrupt is disabled.
+ * 0b1..TXFIFO threshold-level-reached interrupt is enabled.
+ */
+#define SSP_SSP_SSCR1_TIE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_TIE_SHIFT)) & SSP_SSP_SSCR1_TIE_MASK)
+#define SSP_SSP_SSCR1_LBM_MASK (0x4U)
+#define SSP_SSP_SSCR1_LBM_SHIFT (2U)
+/*! LBM - Loopback Mode
+ * 0b0..Normal serial port operation is enabled.
+ * 0b1..Output of TX serial shifter is internally connected to input of RX serial shifter.
+ */
+#define SSP_SSP_SSCR1_LBM(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_LBM_SHIFT)) & SSP_SSP_SSCR1_LBM_MASK)
+#define SSP_SSP_SSCR1_SPO_MASK (0x8U)
+#define SSP_SSP_SSCR1_SPO_SHIFT (3U)
+/*! SPO - Motorola SPI SSPSCLK Polarity Setting
+ * 0b0..The inactive or idle state of SSPSCLKx is low.
+ * 0b1..The inactive or idle state of SSPSCLKx is high.
+ */
+#define SSP_SSP_SSCR1_SPO(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_SPO_SHIFT)) & SSP_SSP_SSCR1_SPO_MASK)
+#define SSP_SSP_SSCR1_SPH_MASK (0x10U)
+#define SSP_SSP_SSCR1_SPH_SHIFT (4U)
+/*! SPH - Motorola SPI SSPSCLK phase setting
+ * 0b0..SSPSCLKx is inactive until one cycle after the start of a frame and active until 1/2 cycle before the end of a frame.
+ * 0b1..SSPSCLKx is inactive until 1/2 cycle after the start of a frame and active until one cycle
+ */
+#define SSP_SSP_SSCR1_SPH(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_SPH_SHIFT)) & SSP_SSP_SSCR1_SPH_MASK)
+#define SSP_SSP_SSCR1_TFT_MASK (0x3C0U)
+#define SSP_SSP_SSCR1_TFT_SHIFT (6U)
+/*! TFT - TXFIFO Trigger Threshold
+ */
+#define SSP_SSP_SSCR1_TFT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_TFT_SHIFT)) & SSP_SSP_SSCR1_TFT_MASK)
+#define SSP_SSP_SSCR1_RFT_MASK (0x3C00U)
+#define SSP_SSP_SSCR1_RFT_SHIFT (10U)
+/*! RFT - RXFIFO Trigger Threshold
+ */
+#define SSP_SSP_SSCR1_RFT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_RFT_SHIFT)) & SSP_SSP_SSCR1_RFT_MASK)
+#define SSP_SSP_SSCR1_EFWR_MASK (0x4000U)
+#define SSP_SSP_SSCR1_EFWR_SHIFT (14U)
+/*! EFWR - Enable FIFO Write/read
+ * 0b0..FIFO write/read special function is disabled (normal SSPx operational mode).
+ * 0b1..FIFO write/read special function is enabled.
+ */
+#define SSP_SSP_SSCR1_EFWR(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_EFWR_SHIFT)) & SSP_SSP_SSCR1_EFWR_MASK)
+#define SSP_SSP_SSCR1_STRF_MASK (0x8000U)
+#define SSP_SSP_SSCR1_STRF_SHIFT (15U)
+/*! STRF - Select FIFO For Efwr
+ * 0b0..TXFIFO is selected for both writes and reads through the SSP Data Register.
+ * 0b1..RXFIFO is selected for both writes and reads through the SSP Data Register.
+ */
+#define SSP_SSP_SSCR1_STRF(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_STRF_SHIFT)) & SSP_SSP_SSCR1_STRF_MASK)
+#define SSP_SSP_SSCR1_IFS_MASK (0x10000U)
+#define SSP_SSP_SSCR1_IFS_SHIFT (16U)
+/*! IFS - Invert Frame Signal
+ * 0b0..SSPSFRMx polarity is determined by the PSP polarity bits.
+ * 0b1..SSPSFRMx is inverted from normal-SSPSFRMx (as defined by the PSP polarity bits). (Works in all frame formats: SPI, SSP, and PSP)
+ */
+#define SSP_SSP_SSCR1_IFS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_IFS_SHIFT)) & SSP_SSP_SSCR1_IFS_MASK)
+#define SSP_SSP_SSCR1_PDM_MASK (0x20000U)
+#define SSP_SSP_SSCR1_PDM_SHIFT (17U)
+/*! PDM - Pulse Desity Modulation Enable
+ * 0b0..PDM function is disabled.
+ * 0b1..PDM function is enabled ,ignore all the ssp module configration but sse bit .
+ */
+#define SSP_SSP_SSCR1_PDM(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_PDM_SHIFT)) & SSP_SSP_SSCR1_PDM_MASK)
+#define SSP_SSP_SSCR1_PINTE_MASK (0x40000U)
+#define SSP_SSP_SSCR1_PINTE_SHIFT (18U)
+/*! PINTE - Peripheral Trailing Byte Interrupt Enable
+ * 0b0..Peripheral trailing byte interrupt is disabled.
+ * 0b1..Peripheral trailing byte interrupt is enabled.
+ */
+#define SSP_SSP_SSCR1_PINTE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_PINTE_SHIFT)) & SSP_SSP_SSCR1_PINTE_MASK)
+#define SSP_SSP_SSCR1_TINTE_MASK (0x80000U)
+#define SSP_SSP_SSCR1_TINTE_SHIFT (19U)
+/*! TINTE - Receiver Time-out Interrupt Enable
+ * 0b0..Receiver time-out interrupt is disabled.
+ * 0b1..Receiver time-out interrupt is enabled.
+ */
+#define SSP_SSP_SSCR1_TINTE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_TINTE_SHIFT)) & SSP_SSP_SSCR1_TINTE_MASK)
+#define SSP_SSP_SSCR1_RSRE_MASK (0x100000U)
+#define SSP_SSP_SSCR1_RSRE_SHIFT (20U)
+/*! RSRE - Receive Service Request Enable
+ * 0b0..DMA service request is disabled
+ * 0b1..DMA service request is enabled
+ */
+#define SSP_SSP_SSCR1_RSRE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_RSRE_SHIFT)) & SSP_SSP_SSCR1_RSRE_MASK)
+#define SSP_SSP_SSCR1_TSRE_MASK (0x200000U)
+#define SSP_SSP_SSCR1_TSRE_SHIFT (21U)
+/*! TSRE - Transmit Service Request Enable
+ * 0b0..DMA service request is disabled
+ * 0b1..DMA service request is enabled
+ */
+#define SSP_SSP_SSCR1_TSRE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_TSRE_SHIFT)) & SSP_SSP_SSCR1_TSRE_MASK)
+#define SSP_SSP_SSCR1_TRAIL_MASK (0x400000U)
+#define SSP_SSP_SSCR1_TRAIL_SHIFT (22U)
+/*! TRAIL - Trailing Byte
+ * 0b0..Trailing bytes are handled by the Aspen (88AP168) Processor
+ * 0b1..Trailing bytes are handled by DMA bursts
+ */
+#define SSP_SSP_SSCR1_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_TRAIL_SHIFT)) & SSP_SSP_SSCR1_TRAIL_MASK)
+#define SSP_SSP_SSCR1_RWOT_MASK (0x800000U)
+#define SSP_SSP_SSCR1_RWOT_SHIFT (23U)
+/*! RWOT - Receive Without Transmit
+ * 0b0..Transmit/Receive mode
+ * 0b1..Receive without Transmit mode
+ */
+#define SSP_SSP_SSCR1_RWOT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_RWOT_SHIFT)) & SSP_SSP_SSCR1_RWOT_MASK)
+#define SSP_SSP_SSCR1_SFRMDIR_MASK (0x1000000U)
+#define SSP_SSP_SSCR1_SFRMDIR_SHIFT (24U)
+/*! SFRMDIR - SSP Frame (SSPSFRMx) Direction
+ * 0b0..Master mode, SSPx port drives SSPSFRMx
+ * 0b1..Slave mode, SSPx port receives SSPSFRMx
+ */
+#define SSP_SSP_SSCR1_SFRMDIR(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_SFRMDIR_SHIFT)) & SSP_SSP_SSCR1_SFRMDIR_MASK)
+#define SSP_SSP_SSCR1_SCLKDIR_MASK (0x2000000U)
+#define SSP_SSP_SSCR1_SCLKDIR_SHIFT (25U)
+/*! SCLKDIR - SSP Serial Bit Rate Clock (SSPSCLKx) Direction
+ * 0b0..Master mode, SSPx port drives SSPSCLKx
+ * 0b1..Slave mode, SSPx port receives SSPSCLKx
+ */
+#define SSP_SSP_SSCR1_SCLKDIR(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_SCLKDIR_SHIFT)) & SSP_SSP_SSCR1_SCLKDIR_MASK)
+#define SSP_SSP_SSCR1_ECRB_MASK (0x4000000U)
+#define SSP_SSP_SSCR1_ECRB_SHIFT (26U)
+/*! ECRB - Enable Clock Request B
+ * 0b0..Clock request from other SSPx is disabled.
+ * 0b1..Clock request from other SSPx is enabled.
+ */
+#define SSP_SSP_SSCR1_ECRB(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_ECRB_SHIFT)) & SSP_SSP_SSCR1_ECRB_MASK)
+#define SSP_SSP_SSCR1_ECRA_MASK (0x8000000U)
+#define SSP_SSP_SSCR1_ECRA_SHIFT (27U)
+/*! ECRA - Enable Clock Request A
+ * 0b0..Clock request from other SSPx is disabled.
+ * 0b1..Clock request from other SSPx is enabled.
+ */
+#define SSP_SSP_SSCR1_ECRA(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_ECRA_SHIFT)) & SSP_SSP_SSCR1_ECRA_MASK)
+#define SSP_SSP_SSCR1_SCFR_MASK (0x10000000U)
+#define SSP_SSP_SSCR1_SCFR_SHIFT (28U)
+/*! SCFR - Slave Clock Free Running
+ * 0b0..Clock input to SSPSCLKx is continuously running
+ * 0b1..Clock input to SSPSCLKx is only active during data transfers. (ob1 Required for slave mode.)
+ */
+#define SSP_SSP_SSCR1_SCFR(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_SCFR_SHIFT)) & SSP_SSP_SSCR1_SCFR_MASK)
+#define SSP_SSP_SSCR1_EBCEI_MASK (0x20000000U)
+#define SSP_SSP_SSCR1_EBCEI_SHIFT (29U)
+/*! EBCEI - Enable Bit Count Error Interrupt
+ * 0b0..Interrupt due to a bit count error is disabled.
+ * 0b1..Interrupt due to a bit count error is enabled.
+ */
+#define SSP_SSP_SSCR1_EBCEI(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_EBCEI_SHIFT)) & SSP_SSP_SSCR1_EBCEI_MASK)
+#define SSP_SSP_SSCR1_TTE_MASK (0x40000000U)
+#define SSP_SSP_SSCR1_TTE_SHIFT (30U)
+/*! TTE - TXD Three-State Enable
+ * 0b0..TXDx output signal is not three-stated.
+ * 0b1..TXD is three-stated when not transmitting data.
+ */
+#define SSP_SSP_SSCR1_TTE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_TTE_SHIFT)) & SSP_SSP_SSCR1_TTE_MASK)
+#define SSP_SSP_SSCR1_TTELP_MASK (0x80000000U)
+#define SSP_SSP_SSCR1_TTELP_SHIFT (31U)
+/*! TTELP - TXD Three-state Enable On Last Phase
+ * 0b0..TXDx is three-stated 1/2 clock cycle after the beginning of the LSB.
+ * 0b1..TXDx output signal is three-stated on the clock edge that ends the LSB.
+ */
+#define SSP_SSP_SSCR1_TTELP(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSCR1_TTELP_SHIFT)) & SSP_SSP_SSCR1_TTELP_MASK)
+/*! @} */
+
+/*! @name SSP_SSSR - SSP Status Register */
+/*! @{ */
+#define SSP_SSP_SSSR_TNF_MASK (0x4U)
+#define SSP_SSP_SSSR_TNF_SHIFT (2U)
+/*! TNF - Transmit FIFO Not Full
+ * 0b0..TXFIFO is full.
+ * 0b1..TXFIFO is not full.
+ */
+#define SSP_SSP_SSSR_TNF(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_TNF_SHIFT)) & SSP_SSP_SSSR_TNF_MASK)
+#define SSP_SSP_SSSR_RNE_MASK (0x8U)
+#define SSP_SSP_SSSR_RNE_SHIFT (3U)
+/*! RNE - Receive FIFO Not Empty
+ * 0b0..RXFIFO is empty.
+ * 0b1..RXFIFO is not empty.
+ */
+#define SSP_SSP_SSSR_RNE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_RNE_SHIFT)) & SSP_SSP_SSSR_RNE_MASK)
+#define SSP_SSP_SSSR_BSY_MASK (0x10U)
+#define SSP_SSP_SSSR_BSY_SHIFT (4U)
+/*! BSY - SSP Busy
+ * 0b0..SSPx port is idle or disabled.
+ * 0b1..SSPx port is currently transmitting or receiving framed data.
+ */
+#define SSP_SSP_SSSR_BSY(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_BSY_SHIFT)) & SSP_SSP_SSSR_BSY_MASK)
+#define SSP_SSP_SSSR_TFS_MASK (0x20U)
+#define SSP_SSP_SSSR_TFS_SHIFT (5U)
+/*! TFS - Transmit FIFO Service Request
+ * 0b0..TX FIFO level exceeds the TFT threshold (TFT + 1), or SSPx port disabled.
+ * 0b1..TXFIFO level is at or below TFT threshold (TFT + 1), causes an interrupt request.
+ */
+#define SSP_SSP_SSSR_TFS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_TFS_SHIFT)) & SSP_SSP_SSSR_TFS_MASK)
+#define SSP_SSP_SSSR_RFS_MASK (0x40U)
+#define SSP_SSP_SSSR_RFS_SHIFT (6U)
+/*! RFS - Receive FIFO Service Request
+ * 0b0..RXFIFO level is at or below RFT threshold (RFT), or SSPx port is disabled
+ * 0b1..RXFIFO level exceeds RFT threshold (RFT), causes an interrupt request
+ */
+#define SSP_SSP_SSSR_RFS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_RFS_SHIFT)) & SSP_SSP_SSSR_RFS_MASK)
+#define SSP_SSP_SSSR_ROR_MASK (0x80U)
+#define SSP_SSP_SSSR_ROR_SHIFT (7U)
+/*! ROR - Receive FIFO Overrun
+ * 0b0..RXFIFO has not experienced an overrun.
+ * 0b1..Attempted data write to full RXFIFO, causes an interrupt request.
+ */
+#define SSP_SSP_SSSR_ROR(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_ROR_SHIFT)) & SSP_SSP_SSSR_ROR_MASK)
+#define SSP_SSP_SSSR_TFL_MASK (0xF00U)
+#define SSP_SSP_SSSR_TFL_SHIFT (8U)
+/*! TFL - Transmit FIFO Level
+ */
+#define SSP_SSP_SSSR_TFL(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_TFL_SHIFT)) & SSP_SSP_SSSR_TFL_MASK)
+#define SSP_SSP_SSSR_RFL_MASK (0xF000U)
+#define SSP_SSP_SSSR_RFL_SHIFT (12U)
+/*! RFL - Receive FIFO Level
+ */
+#define SSP_SSP_SSSR_RFL(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_RFL_SHIFT)) & SSP_SSP_SSSR_RFL_MASK)
+#define SSP_SSP_SSSR_PINT_MASK (0x40000U)
+#define SSP_SSP_SSSR_PINT_SHIFT (18U)
+/*! PINT - Peripheral Trailing Byte Interrupt
+ * 0b0..No peripheral trailing byte interrupt is pending.
+ * 0b1..Peripheral trailing byte interrupt is pending.
+ */
+#define SSP_SSP_SSSR_PINT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_PINT_SHIFT)) & SSP_SSP_SSSR_PINT_MASK)
+#define SSP_SSP_SSSR_TINT_MASK (0x80000U)
+#define SSP_SSP_SSSR_TINT_SHIFT (19U)
+/*! TINT - Receiver Time-out Interrupt
+ * 0b0..No receiver time-out is pending.
+ * 0b1..Receiver time-out pending, causes an interrupt request.
+ */
+#define SSP_SSP_SSSR_TINT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_TINT_SHIFT)) & SSP_SSP_SSSR_TINT_MASK)
+#define SSP_SSP_SSSR_EOC_MASK (0x100000U)
+#define SSP_SSP_SSSR_EOC_SHIFT (20U)
+/*! EOC - End Of Chain
+ * 0b0..DMA has not signaled an end of chain condition.
+ * 0b1..DMA has signaled an end of chain condition.
+ */
+#define SSP_SSP_SSSR_EOC(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_EOC_SHIFT)) & SSP_SSP_SSSR_EOC_MASK)
+#define SSP_SSP_SSSR_TUR_MASK (0x200000U)
+#define SSP_SSP_SSSR_TUR_SHIFT (21U)
+/*! TUR - Transmit FIFO Underrun
+ * 0b0..The TXFIFO has not experienced an underrun.
+ * 0b1..A read from the TXFIFO was attempted when the TXFIFO was empty, causes an interrupt if it is enabled
+ * ( in the SSP Control Register 0 is 0).
+ */
+#define SSP_SSP_SSSR_TUR(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_TUR_SHIFT)) & SSP_SSP_SSSR_TUR_MASK)
+#define SSP_SSP_SSSR_CSS_MASK (0x400000U)
+#define SSP_SSP_SSSR_CSS_SHIFT (22U)
+/*! CSS - Clock Synchronization Status
+ * 0b0..The SSPx port is ready for slave clock operations.
+ * 0b1..The SSPx port is currently busy synchronizing slave mode signals.
+ */
+#define SSP_SSP_SSSR_CSS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_CSS_SHIFT)) & SSP_SSP_SSSR_CSS_MASK)
+#define SSP_SSP_SSSR_BCE_MASK (0x800000U)
+#define SSP_SSP_SSSR_BCE_SHIFT (23U)
+/*! BCE - Bit Count Error
+ * 0b0..The SSPx port has not experienced a bit count error.
+ * 0b1..The SSPSFRMx signal was asserted when the bit counter was not zero.
+ */
+#define SSP_SSP_SSSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_BCE_SHIFT)) & SSP_SSP_SSSR_BCE_MASK)
+#define SSP_SSP_SSSR_TX_OSS_MASK (0x40000000U)
+#define SSP_SSP_SSSR_TX_OSS_SHIFT (30U)
+/*! TX_OSS - TX FIFO Odd Sample Status
+ * 0b0..TxFIFO entry has an even number of samples
+ * 0b1..TxFIFO entry has an odd number of sample.
+ */
+#define SSP_SSP_SSSR_TX_OSS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_TX_OSS_SHIFT)) & SSP_SSP_SSSR_TX_OSS_MASK)
+#define SSP_SSP_SSSR_OSS_MASK (0x80000000U)
+#define SSP_SSP_SSSR_OSS_SHIFT (31U)
+/*! OSS - Odd Sample Status
+ * 0b0..RxFIFO entry has 2 samples
+ * 0b1..RxFIFO entry has 1 sample.
+ */
+#define SSP_SSP_SSSR_OSS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSSR_OSS_SHIFT)) & SSP_SSP_SSSR_OSS_MASK)
+/*! @} */
+
+/*! @name SSP_SSITR - SSP Interrupt Test Register */
+/*! @{ */
+#define SSP_SSP_SSITR_TTFS_MASK (0x20U)
+#define SSP_SSP_SSITR_TTFS_SHIFT (5U)
+/*! TTFS - Test TXFIFO Service Request
+ * 0b0..No TXFIFO-service request
+ * 0b1..Generates a non-maskable TXFIFO-service interrupt request and DMA request
+ */
+#define SSP_SSP_SSITR_TTFS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSITR_TTFS_SHIFT)) & SSP_SSP_SSITR_TTFS_MASK)
+#define SSP_SSP_SSITR_TRFS_MASK (0x40U)
+#define SSP_SSP_SSITR_TRFS_SHIFT (6U)
+/*! TRFS - Test RXFIFO Service Request
+ * 0b0..No RXFIFO-service request.
+ * 0b1..Generates a non-maskable RXFIFO-service interrupt request and DMA request
+ */
+#define SSP_SSP_SSITR_TRFS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSITR_TRFS_SHIFT)) & SSP_SSP_SSITR_TRFS_MASK)
+#define SSP_SSP_SSITR_TROR_MASK (0x80U)
+#define SSP_SSP_SSITR_TROR_SHIFT (7U)
+/*! TROR - Test RXFIFO Overrun
+ * 0b0..No RXFIFO-overrun service request.
+ * 0b1..Generates a non-maskable RXFIFO-overrun interrupt request. No DMA request is generated
+ */
+#define SSP_SSP_SSITR_TROR(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSITR_TROR_SHIFT)) & SSP_SSP_SSITR_TROR_MASK)
+/*! @} */
+
+/*! @name SSP_SSDR - SSP Data Register */
+/*! @{ */
+#define SSP_SSP_SSDR_DATA_MASK (0xFFFFFFFFU)
+#define SSP_SSP_SSDR_DATA_SHIFT (0U)
+/*! DATA - DATA
+ */
+#define SSP_SSP_SSDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSDR_DATA_SHIFT)) & SSP_SSP_SSDR_DATA_MASK)
+/*! @} */
+
+/*! @name SSP_SSTO - SSP Time Out Register */
+/*! @{ */
+#define SSP_SSP_SSTO_TIMEOUT_MASK (0xFFFFFFU)
+#define SSP_SSP_SSTO_TIMEOUT_SHIFT (0U)
+/*! TIMEOUT - Timeout Value
+ */
+#define SSP_SSP_SSTO_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSTO_TIMEOUT_SHIFT)) & SSP_SSP_SSTO_TIMEOUT_MASK)
+/*! @} */
+
+/*! @name SSP_SSPSP - SSP Programmable Serial Protocol Register */
+/*! @{ */
+#define SSP_SSP_SSPSP_SCMODE_MASK (0x3U)
+#define SSP_SSP_SSPSP_SCMODE_SHIFT (0U)
+/*! SCMODE - Serial Bit-rate Clock Mode
+ * 0b00..Data Driven (Falling), Data Sampled (Rising), Idle State (Low)
+ * 0b01..Data Driven (Rising), Data Sampled (Falling), Idle State (Low)
+ * 0b10..Data Driven (Rising), Data Sampled (Falling), Idle State (High)
+ * 0b11..Data Driven (Falling), Data Sampled (Rising), Idle State (High)
+ */
+#define SSP_SSP_SSPSP_SCMODE(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_SCMODE_SHIFT)) & SSP_SSP_SSPSP_SCMODE_MASK)
+#define SSP_SSP_SSPSP_SFRMP_MASK (0x4U)
+#define SSP_SSP_SSPSP_SFRMP_SHIFT (2U)
+/*! SFRMP - Serial Frame Polarity
+ * 0b0..SSPSFRMx is active low (0b0).
+ * 0b1..SSPSFRMx is active high (0b1).
+ */
+#define SSP_SSP_SSPSP_SFRMP(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_SFRMP_SHIFT)) & SSP_SSP_SSPSP_SFRMP_MASK)
+#define SSP_SSP_SSPSP_ETDS_MASK (0x8U)
+#define SSP_SSP_SSPSP_ETDS_SHIFT (3U)
+/*! ETDS - End Of Transfer Data State
+ */
+#define SSP_SSP_SSPSP_ETDS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_ETDS_SHIFT)) & SSP_SSP_SSPSP_ETDS_MASK)
+#define SSP_SSP_SSPSP_STRTDLY_MASK (0x70U)
+#define SSP_SSP_SSPSP_STRTDLY_SHIFT (4U)
+/*! STRTDLY - Start Delay
+ */
+#define SSP_SSP_SSPSP_STRTDLY(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_STRTDLY_SHIFT)) & SSP_SSP_SSPSP_STRTDLY_MASK)
+#define SSP_SSP_SSPSP_DMYSTRT_MASK (0x180U)
+#define SSP_SSP_SSPSP_DMYSTRT_SHIFT (7U)
+/*! DMYSTRT - Dummy Start
+ */
+#define SSP_SSP_SSPSP_DMYSTRT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_DMYSTRT_SHIFT)) & SSP_SSP_SSPSP_DMYSTRT_MASK)
+#define SSP_SSP_SSPSP_SFRMDLY_MASK (0xFE00U)
+#define SSP_SSP_SSPSP_SFRMDLY_SHIFT (9U)
+/*! SFRMDLY - Serial Frame Delay
+ */
+#define SSP_SSP_SSPSP_SFRMDLY(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_SFRMDLY_SHIFT)) & SSP_SSP_SSPSP_SFRMDLY_MASK)
+#define SSP_SSP_SSPSP_SFRMWDTH_MASK (0x3F0000U)
+#define SSP_SSP_SSPSP_SFRMWDTH_SHIFT (16U)
+/*! SFRMWDTH - Serial Frame Width
+ */
+#define SSP_SSP_SSPSP_SFRMWDTH(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_SFRMWDTH_SHIFT)) & SSP_SSP_SSPSP_SFRMWDTH_MASK)
+#define SSP_SSP_SSPSP_DMYSTOP_MASK (0x1800000U)
+#define SSP_SSP_SSPSP_DMYSTOP_SHIFT (23U)
+/*! DMYSTOP - Dummy Stop
+ */
+#define SSP_SSP_SSPSP_DMYSTOP(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_DMYSTOP_SHIFT)) & SSP_SSP_SSPSP_DMYSTOP_MASK)
+#define SSP_SSP_SSPSP_FSRT_MASK (0x2000000U)
+#define SSP_SSP_SSPSP_FSRT_SHIFT (25U)
+/*! FSRT - Frame Sync Relative Timing Bit
+ * 0b0..Next frame is asserted after the end of the DMTSTOP timing.
+ * 0b1..Next frame is asserted with the LSB of the previous frame.
+ */
+#define SSP_SSP_SSPSP_FSRT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_FSRT_SHIFT)) & SSP_SSP_SSPSP_FSRT_MASK)
+#define SSP_SSP_SSPSP_EDMYSTRT_MASK (0xC000000U)
+#define SSP_SSP_SSPSP_EDMYSTRT_SHIFT (26U)
+/*! EDMYSTRT - Extended Dummy Start
+ */
+#define SSP_SSP_SSPSP_EDMYSTRT(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_EDMYSTRT_SHIFT)) & SSP_SSP_SSPSP_EDMYSTRT_MASK)
+#define SSP_SSP_SSPSP_EDMYSTOP_MASK (0x70000000U)
+#define SSP_SSP_SSPSP_EDMYSTOP_SHIFT (28U)
+/*! EDMYSTOP - Extended Dummy Stop
+ */
+#define SSP_SSP_SSPSP_EDMYSTOP(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSPSP_EDMYSTOP_SHIFT)) & SSP_SSP_SSPSP_EDMYSTOP_MASK)
+/*! @} */
+
+/*! @name SSP_SSTSA - SSP TX Time Slot Active Register */
+/*! @{ */
+#define SSP_SSP_SSTSA_TTSA_MASK (0xFFU)
+#define SSP_SSP_SSTSA_TTSA_SHIFT (0U)
+/*! TTSA - TX Time Slot Active
+ * 0b00000000..SSPx port does NOT transmit data in this time slot.
+ * 0b00000001..SSPx port does transmit data in this time slot.
+ */
+#define SSP_SSP_SSTSA_TTSA(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSTSA_TTSA_SHIFT)) & SSP_SSP_SSTSA_TTSA_MASK)
+/*! @} */
+
+/*! @name SSP_SSRSA - SSP RX Time Slot Active Register */
+/*! @{ */
+#define SSP_SSP_SSRSA_RTSA_MASK (0xFFU)
+#define SSP_SSP_SSRSA_RTSA_SHIFT (0U)
+/*! RTSA - RX Time Slot Active
+ * 0b00000000..SSPx port does not receive data in this time slot.
+ * 0b00000001..SSPx port receives data in this time slot.
+ */
+#define SSP_SSP_SSRSA_RTSA(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSRSA_RTSA_SHIFT)) & SSP_SSP_SSRSA_RTSA_MASK)
+/*! @} */
+
+/*! @name SSP_SSTSS - SSP Time Slot Status Register */
+/*! @{ */
+#define SSP_SSP_SSTSS_TSS_MASK (0x7U)
+#define SSP_SSP_SSTSS_TSS_SHIFT (0U)
+/*! TSS - Time Slot Status
+ */
+#define SSP_SSP_SSTSS_TSS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSTSS_TSS_SHIFT)) & SSP_SSP_SSTSS_TSS_MASK)
+#define SSP_SSP_SSTSS_NMBSY_MASK (0x80000000U)
+#define SSP_SSP_SSTSS_NMBSY_SHIFT (31U)
+/*! NMBSY - Network Mode Busy
+ * 0b0..SSPx port is in network mode and no frame is currently active.
+ * 0b1..SSPx port is in network mode and a frame is currently active.
+ */
+#define SSP_SSP_SSTSS_NMBSY(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSTSS_NMBSY_SHIFT)) & SSP_SSP_SSTSS_NMBSY_MASK)
+/*! @} */
+
+/*! @name SSP_SSACD - SSP Audio Clock Divider Register */
+/*! @{ */
+#define SSP_SSP_SSACD_ACDS_MASK (0x7U)
+#define SSP_SSP_SSACD_ACDS_SHIFT (0U)
+/*! ACDS - Audio Clock Divider Select
+ */
+#define SSP_SSP_SSACD_ACDS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSACD_ACDS_SHIFT)) & SSP_SSP_SSACD_ACDS_MASK)
+#define SSP_SSP_SSACD_SCDB_MASK (0x8U)
+#define SSP_SSP_SSACD_SCDB_SHIFT (3U)
+/*! SCDB - SYSCLK Divider Bypass
+ * 0b0..SYSCLK is divided by 4 (if SCDX8=0) or 8 (if SCDX8=1) to generate internal audio clock.
+ * 0b1..SYSCLK is not divided.
+ */
+#define SSP_SSP_SSACD_SCDB(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSACD_SCDB_SHIFT)) & SSP_SSP_SSACD_SCDB_MASK)
+#define SSP_SSP_SSACD_ACPS_MASK (0x70U)
+#define SSP_SSP_SSACD_ACPS_SHIFT (4U)
+/*! ACPS - Audio Clock PLL Select
+ */
+#define SSP_SSP_SSACD_ACPS(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSACD_ACPS_SHIFT)) & SSP_SSP_SSACD_ACPS_MASK)
+#define SSP_SSP_SSACD_SCDX8_MASK (0x80U)
+#define SSP_SSP_SSACD_SCDX8_SHIFT (7U)
+/*! SCDX8 - SYSCLK Divided By 8
+ * 0b0..SYSCLK is divided by 4 to generate internal audio clock.
+ * 0b1..SYSCLK is divided by 8 to generate internal audio clock.
+ */
+#define SSP_SSP_SSACD_SCDX8(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSACD_SCDX8_SHIFT)) & SSP_SSP_SSACD_SCDX8_MASK)
+/*! @} */
+
+/*! @name SSP_SSACDD - SSP Audio Clock Dither Divider Register */
+/*! @{ */
+#define SSP_SSP_SSACDD_DEN_MASK (0xFFFU)
+#define SSP_SSP_SSACDD_DEN_SHIFT (0U)
+/*! DEN - Denominator
+ */
+#define SSP_SSP_SSACDD_DEN(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSACDD_DEN_SHIFT)) & SSP_SSP_SSACDD_DEN_MASK)
+#define SSP_SSP_SSACDD_NUM_MASK (0x7FFF0000U)
+#define SSP_SSP_SSACDD_NUM_SHIFT (16U)
+/*! NUM - Numerator
+ */
+#define SSP_SSP_SSACDD_NUM(x) (((uint32_t)(((uint32_t)(x)) << SSP_SSP_SSACDD_NUM_SHIFT)) & SSP_SSP_SSACDD_NUM_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SSP_Register_Masks */
+
+
+/* SSP - Peripheral instance base addresses */
+/** Peripheral SSP0 base address */
+#define SSP0_BASE (0x46020000u)
+/** Peripheral SSP0 base pointer */
+#define SSP0 ((SSP_Type *)SSP0_BASE)
+/** Peripheral SSP1 base address */
+#define SSP1_BASE (0x460D0000u)
+/** Peripheral SSP1 base pointer */
+#define SSP1 ((SSP_Type *)SSP1_BASE)
+/** Peripheral SSP2 base address */
+#define SSP2_BASE (0x48000000u)
+/** Peripheral SSP2 base pointer */
+#define SSP2 ((SSP_Type *)SSP2_BASE)
+/** Array initializer of SSP peripheral base addresses */
+#define SSP_BASE_ADDRS { SSP0_BASE, SSP1_BASE, SSP2_BASE }
+/** Array initializer of SSP peripheral base pointers */
+#define SSP_BASE_PTRS { SSP0, SSP1, SSP2 }
+/** Interrupt vectors for the SSP peripheral type */
+#define SSP_IRQS { SSP0_IRQn, SSP1_IRQn, SSP2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SSP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SYS_CTL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYS_CTL_Peripheral_Access_Layer SYS_CTL Peripheral Access Layer
+ * @{
+ */
+
+/** SYS_CTL - Register Layout Typedef */
+typedef struct {
+ __I uint32_t REV_ID; /**< Chip Revision Register, offset: 0x0 */
+ __IO uint32_t MEM; /**< Memory Space Configuration Register, offset: 0x4 */
+ __IO uint32_t RAM0; /**< RAM0 Control Register, offset: 0x8 */
+ __IO uint32_t RAM1; /**< RAM1 Control Register, offset: 0xC */
+ __IO uint32_t RAM2; /**< RAM2 Control Register, offset: 0x10 */
+ __IO uint32_t RAM3; /**< RAM3 Control Register, offset: 0x14 */
+ uint8_t RESERVED_0[16];
+ __IO uint32_t ROM; /**< ROM Control Register, offset: 0x28 */
+ __IO uint32_t AON_MEM; /**< AON_MEM Control Register, offset: 0x2C */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t GPT_IN; /**< GPT Pin-in Selection Register, offset: 0x34 */
+ __IO uint32_t CAL; /**< Calibration channel selection register, offset: 0x38 */
+ __IO uint32_t PERI_SW_RST; /**< Peripheral Software Reset register, offset: 0x3C */
+ __IO uint32_t USB_CTRL; /**< USB Control Register, offset: 0x40 */
+ uint8_t RESERVED_2[8];
+ __IO uint32_t MMC_TC; /**< SDIO Timing Control Register, offset: 0x4C */
+ __IO uint32_t EXT_FLASH_SEL; /**< External Flash select register, offset: 0x50 */
+} SYS_CTL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SYS_CTL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYS_CTL_Register_Masks SYS_CTL Register Masks
+ * @{
+ */
+
+/*! @name REV_ID - Chip Revision Register */
+/*! @{ */
+#define SYS_CTL_REV_ID_REV_ID_MASK (0xFFFFFFFFU)
+#define SYS_CTL_REV_ID_REV_ID_SHIFT (0U)
+/*! REV_ID - Chip revision ID
+ */
+#define SYS_CTL_REV_ID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_REV_ID_REV_ID_SHIFT)) & SYS_CTL_REV_ID_REV_ID_MASK)
+/*! @} */
+
+/*! @name MEM - Memory Space Configuration Register */
+/*! @{ */
+#define SYS_CTL_MEM_CFG_MASK (0x3U)
+#define SYS_CTL_MEM_CFG_SHIFT (0U)
+/*! CFG - Memory space configuration
+ */
+#define SYS_CTL_MEM_CFG(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_MEM_CFG_SHIFT)) & SYS_CTL_MEM_CFG_MASK)
+/*! @} */
+
+/*! @name RAM0 - RAM0 Control Register */
+/*! @{ */
+#define SYS_CTL_RAM0_RTC_MASK (0x3U)
+#define SYS_CTL_RAM0_RTC_SHIFT (0U)
+/*! RTC - RTC
+ */
+#define SYS_CTL_RAM0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_RAM0_RTC_SHIFT)) & SYS_CTL_RAM0_RTC_MASK)
+#define SYS_CTL_RAM0_WTC_MASK (0xCU)
+#define SYS_CTL_RAM0_WTC_SHIFT (2U)
+/*! WTC - WTC
+ */
+#define SYS_CTL_RAM0_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_RAM0_WTC_SHIFT)) & SYS_CTL_RAM0_WTC_MASK)
+/*! @} */
+
+/*! @name RAM1 - RAM1 Control Register */
+/*! @{ */
+#define SYS_CTL_RAM1_RTC_MASK (0x3U)
+#define SYS_CTL_RAM1_RTC_SHIFT (0U)
+/*! RTC - RTC
+ */
+#define SYS_CTL_RAM1_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_RAM1_RTC_SHIFT)) & SYS_CTL_RAM1_RTC_MASK)
+#define SYS_CTL_RAM1_WTC_MASK (0xCU)
+#define SYS_CTL_RAM1_WTC_SHIFT (2U)
+/*! WTC - WTC
+ */
+#define SYS_CTL_RAM1_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_RAM1_WTC_SHIFT)) & SYS_CTL_RAM1_WTC_MASK)
+/*! @} */
+
+/*! @name RAM2 - RAM2 Control Register */
+/*! @{ */
+#define SYS_CTL_RAM2_RTC_MASK (0x3U)
+#define SYS_CTL_RAM2_RTC_SHIFT (0U)
+/*! RTC - RTC
+ */
+#define SYS_CTL_RAM2_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_RAM2_RTC_SHIFT)) & SYS_CTL_RAM2_RTC_MASK)
+#define SYS_CTL_RAM2_WTC_MASK (0xCU)
+#define SYS_CTL_RAM2_WTC_SHIFT (2U)
+/*! WTC - WTC
+ */
+#define SYS_CTL_RAM2_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_RAM2_WTC_SHIFT)) & SYS_CTL_RAM2_WTC_MASK)
+/*! @} */
+
+/*! @name RAM3 - RAM3 Control Register */
+/*! @{ */
+#define SYS_CTL_RAM3_RTC_MASK (0x3U)
+#define SYS_CTL_RAM3_RTC_SHIFT (0U)
+/*! RTC - RTC
+ */
+#define SYS_CTL_RAM3_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_RAM3_RTC_SHIFT)) & SYS_CTL_RAM3_RTC_MASK)
+#define SYS_CTL_RAM3_WTC_MASK (0xCU)
+#define SYS_CTL_RAM3_WTC_SHIFT (2U)
+/*! WTC - WTC
+ */
+#define SYS_CTL_RAM3_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_RAM3_WTC_SHIFT)) & SYS_CTL_RAM3_WTC_MASK)
+/*! @} */
+
+/*! @name ROM - ROM Control Register */
+/*! @{ */
+#define SYS_CTL_ROM_RTC_MASK (0x7U)
+#define SYS_CTL_ROM_RTC_SHIFT (0U)
+/*! RTC - RTC Reference
+ */
+#define SYS_CTL_ROM_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_ROM_RTC_SHIFT)) & SYS_CTL_ROM_RTC_MASK)
+#define SYS_CTL_ROM_RTC_REF_MASK (0x18U)
+#define SYS_CTL_ROM_RTC_REF_SHIFT (3U)
+/*! RTC_REF - RTC Reference
+ */
+#define SYS_CTL_ROM_RTC_REF(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_ROM_RTC_REF_SHIFT)) & SYS_CTL_ROM_RTC_REF_MASK)
+/*! @} */
+
+/*! @name AON_MEM - AON_MEM Control Register */
+/*! @{ */
+#define SYS_CTL_AON_MEM_RTC_MASK (0x3U)
+#define SYS_CTL_AON_MEM_RTC_SHIFT (0U)
+/*! RTC - RTC
+ */
+#define SYS_CTL_AON_MEM_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_AON_MEM_RTC_SHIFT)) & SYS_CTL_AON_MEM_RTC_MASK)
+#define SYS_CTL_AON_MEM_WTC_MASK (0xCU)
+#define SYS_CTL_AON_MEM_WTC_SHIFT (2U)
+/*! WTC - WTC
+ */
+#define SYS_CTL_AON_MEM_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_AON_MEM_WTC_SHIFT)) & SYS_CTL_AON_MEM_WTC_MASK)
+/*! @} */
+
+/*! @name GPT_IN - GPT Pin-in Selection Register */
+/*! @{ */
+#define SYS_CTL_GPT_IN_SEL_MASK (0x1U)
+#define SYS_CTL_GPT_IN_SEL_SHIFT (0U)
+/*! sel - Select GPT Pin
+ */
+#define SYS_CTL_GPT_IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_GPT_IN_SEL_SHIFT)) & SYS_CTL_GPT_IN_SEL_MASK)
+/*! @} */
+
+/*! @name CAL - Calibration channel selection register */
+/*! @{ */
+#define SYS_CTL_CAL_RTC_DUTY_MASK (0x1U)
+#define SYS_CTL_CAL_RTC_DUTY_SHIFT (0U)
+/*! RTC_Duty - RTC Duty
+ */
+#define SYS_CTL_CAL_RTC_DUTY(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_CAL_RTC_DUTY_SHIFT)) & SYS_CTL_CAL_RTC_DUTY_MASK)
+#define SYS_CTL_CAL_RTC_TRIG_MASK (0x2U)
+#define SYS_CTL_CAL_RTC_TRIG_SHIFT (1U)
+/*! RTC_Trig - RTC Trigger
+ */
+#define SYS_CTL_CAL_RTC_TRIG(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_CAL_RTC_TRIG_SHIFT)) & SYS_CTL_CAL_RTC_TRIG_MASK)
+/*! @} */
+
+/*! @name PERI_SW_RST - Peripheral Software Reset register */
+/*! @{ */
+#define SYS_CTL_PERI_SW_RST_WDT_RSTN_EN_MASK (0x1U)
+#define SYS_CTL_PERI_SW_RST_WDT_RSTN_EN_SHIFT (0U)
+/*! wdt_rstn_en - WDT Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_WDT_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_WDT_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_WDT_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_USB_RSTN_EN_MASK (0x2U)
+#define SYS_CTL_PERI_SW_RST_USB_RSTN_EN_SHIFT (1U)
+/*! usb_rstn_en - USB Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_USB_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_USB_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_USB_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_SDIO1_RSTN_EN_MASK (0x4U)
+#define SYS_CTL_PERI_SW_RST_SDIO1_RSTN_EN_SHIFT (2U)
+/*! sdio1_rstn_en - SDIO1 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_SDIO1_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_SDIO1_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_SDIO1_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_SDIO0_RSTN_EN_MASK (0x8U)
+#define SYS_CTL_PERI_SW_RST_SDIO0_RSTN_EN_SHIFT (3U)
+/*! sdio0_rstn_en - SDIO0 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_SDIO0_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_SDIO0_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_SDIO0_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_GPT3_RSTN_EN_MASK (0x10U)
+#define SYS_CTL_PERI_SW_RST_GPT3_RSTN_EN_SHIFT (4U)
+/*! gpt3_rstn_en - GPT3 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_GPT3_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_GPT3_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_GPT3_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_GPT2_RSTN_EN_MASK (0x20U)
+#define SYS_CTL_PERI_SW_RST_GPT2_RSTN_EN_SHIFT (5U)
+/*! gpt2_rstn_en - GPT2 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_GPT2_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_GPT2_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_GPT2_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_GPT1_RSTN_EN_MASK (0x40U)
+#define SYS_CTL_PERI_SW_RST_GPT1_RSTN_EN_SHIFT (6U)
+/*! gpt1_rstn_en - GPT1 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_GPT1_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_GPT1_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_GPT1_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_GPT0_RSTN_EN_MASK (0x80U)
+#define SYS_CTL_PERI_SW_RST_GPT0_RSTN_EN_SHIFT (7U)
+/*! gpt0_rstn_en - GPT0 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_GPT0_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_GPT0_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_GPT0_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_SSP2_RSTN_EN_MASK (0x100U)
+#define SYS_CTL_PERI_SW_RST_SSP2_RSTN_EN_SHIFT (8U)
+/*! ssp2_rstn_en - SSP2 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_SSP2_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_SSP2_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_SSP2_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_SSP1_RSTN_EN_MASK (0x200U)
+#define SYS_CTL_PERI_SW_RST_SSP1_RSTN_EN_SHIFT (9U)
+/*! ssp1_rstn_en - SSP01 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_SSP1_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_SSP1_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_SSP1_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_SSP0_RSTN_EN_MASK (0x400U)
+#define SYS_CTL_PERI_SW_RST_SSP0_RSTN_EN_SHIFT (10U)
+/*! ssp0_rstn_en - SSP0 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_SSP0_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_SSP0_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_SSP0_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_I2C2_RSTN_EN_MASK (0x800U)
+#define SYS_CTL_PERI_SW_RST_I2C2_RSTN_EN_SHIFT (11U)
+/*! i2c2_rstn_en - I2C2 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_I2C2_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_I2C2_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_I2C2_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_I2C1_RSTN_EN_MASK (0x1000U)
+#define SYS_CTL_PERI_SW_RST_I2C1_RSTN_EN_SHIFT (12U)
+/*! i2c1_rstn_en - I2C1 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_I2C1_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_I2C1_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_I2C1_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_I2C0_RSTN_EN_MASK (0x2000U)
+#define SYS_CTL_PERI_SW_RST_I2C0_RSTN_EN_SHIFT (13U)
+/*! i2c0_rstn_en - I2C0 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_I2C0_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_I2C0_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_I2C0_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_UART3_RSTN_EN_MASK (0x4000U)
+#define SYS_CTL_PERI_SW_RST_UART3_RSTN_EN_SHIFT (14U)
+/*! uart3_rstn_en - UART3 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_UART3_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_UART3_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_UART3_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_UART2_RSTN_EN_MASK (0x8000U)
+#define SYS_CTL_PERI_SW_RST_UART2_RSTN_EN_SHIFT (15U)
+/*! uart2_rstn_en - UART2 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_UART2_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_UART2_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_UART2_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_KEYPAD_RSTN_EN_MASK (0x10000U)
+#define SYS_CTL_PERI_SW_RST_KEYPAD_RSTN_EN_SHIFT (16U)
+/*! keypad_rstn_en - Keypad Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_KEYPAD_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_KEYPAD_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_KEYPAD_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_UART0_RSTN_EN_MASK (0x20000U)
+#define SYS_CTL_PERI_SW_RST_UART0_RSTN_EN_SHIFT (17U)
+/*! uart0_rstn_en - UART0 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_UART0_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_UART0_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_UART0_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_FLASH_QSPI_RSTN_EN_MASK (0x40000U)
+#define SYS_CTL_PERI_SW_RST_FLASH_QSPI_RSTN_EN_SHIFT (18U)
+/*! flash_qspi_rstn_en - Flash QSPI Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_FLASH_QSPI_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_FLASH_QSPI_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_FLASH_QSPI_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_QSPI1_RSTN_EN_MASK (0x80000U)
+#define SYS_CTL_PERI_SW_RST_QSPI1_RSTN_EN_SHIFT (19U)
+/*! qspi1_rstn_en - QSPI1 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_QSPI1_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_QSPI1_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_QSPI1_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_QSPI0_RSTN_EN_MASK (0x100000U)
+#define SYS_CTL_PERI_SW_RST_QSPI0_RSTN_EN_SHIFT (20U)
+/*! qspi0_rstn_en - QSPI0 Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_QSPI0_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_QSPI0_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_QSPI0_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_IR_RSTN_EN_MASK (0x200000U)
+#define SYS_CTL_PERI_SW_RST_IR_RSTN_EN_SHIFT (21U)
+/*! ir_rstn_en - IR Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_IR_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_IR_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_IR_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_PDM_RSTN_EN_MASK (0x400000U)
+#define SYS_CTL_PERI_SW_RST_PDM_RSTN_EN_SHIFT (22U)
+/*! pdm_rstn_en - PDM Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_PDM_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_PDM_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_PDM_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_USIM_RSTN_EN_MASK (0x800000U)
+#define SYS_CTL_PERI_SW_RST_USIM_RSTN_EN_SHIFT (23U)
+/*! usim_rstn_en - USIM Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_USIM_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_USIM_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_USIM_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_CB_RSTN_EN_MASK (0x1000000U)
+#define SYS_CTL_PERI_SW_RST_CB_RSTN_EN_SHIFT (24U)
+/*! cb_rstn_en - CB Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_CB_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_CB_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_CB_RSTN_EN_MASK)
+#define SYS_CTL_PERI_SW_RST_GAU_RSTN_EN_MASK (0x4000000U)
+#define SYS_CTL_PERI_SW_RST_GAU_RSTN_EN_SHIFT (26U)
+/*! gau_rstn_en - GAU Reset_n Enable
+ */
+#define SYS_CTL_PERI_SW_RST_GAU_RSTN_EN(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_PERI_SW_RST_GAU_RSTN_EN_SHIFT)) & SYS_CTL_PERI_SW_RST_GAU_RSTN_EN_MASK)
+/*! @} */
+
+/*! @name USB_CTRL - USB Control Register */
+/*! @{ */
+#define SYS_CTL_USB_CTRL_USB_PU_PLL_MASK (0x1U)
+#define SYS_CTL_USB_CTRL_USB_PU_PLL_SHIFT (0U)
+/*! usb_PU_PLL - USB PU PLL
+ */
+#define SYS_CTL_USB_CTRL_USB_PU_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_USB_PU_PLL_SHIFT)) & SYS_CTL_USB_CTRL_USB_PU_PLL_MASK)
+#define SYS_CTL_USB_CTRL_USB_PU_OTG_MASK (0x2U)
+#define SYS_CTL_USB_CTRL_USB_PU_OTG_SHIFT (1U)
+/*! usb_PU_OTG - USB PU OTG
+ */
+#define SYS_CTL_USB_CTRL_USB_PU_OTG(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_USB_PU_OTG_SHIFT)) & SYS_CTL_USB_CTRL_USB_PU_OTG_MASK)
+#define SYS_CTL_USB_CTRL_USB_PU_MASK (0x4U)
+#define SYS_CTL_USB_CTRL_USB_PU_SHIFT (2U)
+/*! usb_PU - USB PU
+ */
+#define SYS_CTL_USB_CTRL_USB_PU(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_USB_PU_SHIFT)) & SYS_CTL_USB_CTRL_USB_PU_MASK)
+#define SYS_CTL_USB_CTRL_REG_RX_PDFVSSM_MASK (0x8U)
+#define SYS_CTL_USB_CTRL_REG_RX_PDFVSSM_SHIFT (3U)
+/*! reg_rx_pdfvssm - reg_rx_pdfvssm
+ */
+#define SYS_CTL_USB_CTRL_REG_RX_PDFVSSM(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_REG_RX_PDFVSSM_SHIFT)) & SYS_CTL_USB_CTRL_REG_RX_PDFVSSM_MASK)
+#define SYS_CTL_USB_CTRL_REG_RX_PDLVMC_MASK (0x10U)
+#define SYS_CTL_USB_CTRL_REG_RX_PDLVMC_SHIFT (4U)
+/*! reg_rx_pdlvmc - reg_rx_pdlvmc
+ */
+#define SYS_CTL_USB_CTRL_REG_RX_PDLVMC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_REG_RX_PDLVMC_SHIFT)) & SYS_CTL_USB_CTRL_REG_RX_PDLVMC_MASK)
+#define SYS_CTL_USB_CTRL_REG_TX_PDFVSSM_MASK (0x20U)
+#define SYS_CTL_USB_CTRL_REG_TX_PDFVSSM_SHIFT (5U)
+/*! reg_tx_pdfvssm - reg_tx_pdfvssm
+ */
+#define SYS_CTL_USB_CTRL_REG_TX_PDFVSSM(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_REG_TX_PDFVSSM_SHIFT)) & SYS_CTL_USB_CTRL_REG_TX_PDFVSSM_MASK)
+#define SYS_CTL_USB_CTRL_REG_TX_PDLVMC_MASK (0x40U)
+#define SYS_CTL_USB_CTRL_REG_TX_PDLVMC_SHIFT (6U)
+/*! reg_tx_pdlvmc - reg_tx_pdlvmc
+ */
+#define SYS_CTL_USB_CTRL_REG_TX_PDLVMC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_REG_TX_PDLVMC_SHIFT)) & SYS_CTL_USB_CTRL_REG_TX_PDLVMC_MASK)
+#define SYS_CTL_USB_CTRL_REG_RX_BUF_RTC_MASK (0x180U)
+#define SYS_CTL_USB_CTRL_REG_RX_BUF_RTC_SHIFT (7U)
+/*! reg_rx_buf_rtc - reg_rx_buf_rtc
+ */
+#define SYS_CTL_USB_CTRL_REG_RX_BUF_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_REG_RX_BUF_RTC_SHIFT)) & SYS_CTL_USB_CTRL_REG_RX_BUF_RTC_MASK)
+#define SYS_CTL_USB_CTRL_REG_RX_BUF_WTC_MASK (0x600U)
+#define SYS_CTL_USB_CTRL_REG_RX_BUF_WTC_SHIFT (9U)
+/*! reg_rx_buf_wtc - reg_rx_buf_wtc
+ */
+#define SYS_CTL_USB_CTRL_REG_RX_BUF_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_REG_RX_BUF_WTC_SHIFT)) & SYS_CTL_USB_CTRL_REG_RX_BUF_WTC_MASK)
+#define SYS_CTL_USB_CTRL_REG_TX_BUF_RTC_MASK (0x1800U)
+#define SYS_CTL_USB_CTRL_REG_TX_BUF_RTC_SHIFT (11U)
+/*! reg_tx_buf_rtc - reg_tx_buf_rtc
+ */
+#define SYS_CTL_USB_CTRL_REG_TX_BUF_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_REG_TX_BUF_RTC_SHIFT)) & SYS_CTL_USB_CTRL_REG_TX_BUF_RTC_MASK)
+#define SYS_CTL_USB_CTRL_REG_TX_BUF_WTC_MASK (0x6000U)
+#define SYS_CTL_USB_CTRL_REG_TX_BUF_WTC_SHIFT (13U)
+/*! reg_tx_buf_wtc - reg_tx_buf_wtc
+ */
+#define SYS_CTL_USB_CTRL_REG_TX_BUF_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_REG_TX_BUF_WTC_SHIFT)) & SYS_CTL_USB_CTRL_REG_TX_BUF_WTC_MASK)
+#define SYS_CTL_USB_CTRL_USB_RESUME_MASK (0x8000U)
+#define SYS_CTL_USB_CTRL_USB_RESUME_SHIFT (15U)
+/*! usb_resume - USB Resume
+ */
+#define SYS_CTL_USB_CTRL_USB_RESUME(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_USB_RESUME_SHIFT)) & SYS_CTL_USB_CTRL_USB_RESUME_MASK)
+#define SYS_CTL_USB_CTRL_IDDQ_TEST_MASK (0x10000U)
+#define SYS_CTL_USB_CTRL_IDDQ_TEST_SHIFT (16U)
+/*! iddq_test - iddq Test
+ */
+#define SYS_CTL_USB_CTRL_IDDQ_TEST(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_IDDQ_TEST_SHIFT)) & SYS_CTL_USB_CTRL_IDDQ_TEST_MASK)
+#define SYS_CTL_USB_CTRL_SOFT_PHY_RESET_MASK (0x20000U)
+#define SYS_CTL_USB_CTRL_SOFT_PHY_RESET_SHIFT (17U)
+/*! soft_phy_reset - Soft PHY Reset
+ */
+#define SYS_CTL_USB_CTRL_SOFT_PHY_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_SOFT_PHY_RESET_SHIFT)) & SYS_CTL_USB_CTRL_SOFT_PHY_RESET_MASK)
+#define SYS_CTL_USB_CTRL_PHY_RESET_SEL_MASK (0x40000U)
+#define SYS_CTL_USB_CTRL_PHY_RESET_SEL_SHIFT (18U)
+/*! phy_reset_sel - PHY Reset Select
+ */
+#define SYS_CTL_USB_CTRL_PHY_RESET_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_PHY_RESET_SEL_SHIFT)) & SYS_CTL_USB_CTRL_PHY_RESET_SEL_MASK)
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_SESSEND_MASK (0x80000U)
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_SESSEND_SHIFT (19U)
+/*! soft_utmi_sessend - Soft UTMI sessend
+ */
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_SOFT_UTMI_SESSEND_SHIFT)) & SYS_CTL_USB_CTRL_SOFT_UTMI_SESSEND_MASK)
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_XVALID_MASK (0x100000U)
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_XVALID_SHIFT (20U)
+/*! soft_utmi_xvalid - Soft UTMI xvalid
+ */
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_XVALID(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_SOFT_UTMI_XVALID_SHIFT)) & SYS_CTL_USB_CTRL_SOFT_UTMI_XVALID_MASK)
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_IDDIG_MASK (0x200000U)
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_IDDIG_SHIFT (21U)
+/*! soft_utmi_iddig - Soft UTMI iddig
+ */
+#define SYS_CTL_USB_CTRL_SOFT_UTMI_IDDIG(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_SOFT_UTMI_IDDIG_SHIFT)) & SYS_CTL_USB_CTRL_SOFT_UTMI_IDDIG_MASK)
+#define SYS_CTL_USB_CTRL_MAC_CTRL_SEL_MASK (0x400000U)
+#define SYS_CTL_USB_CTRL_MAC_CTRL_SEL_SHIFT (22U)
+/*! mac_ctrl_sel - MAC Control Select
+ */
+#define SYS_CTL_USB_CTRL_MAC_CTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_USB_CTRL_MAC_CTRL_SEL_SHIFT)) & SYS_CTL_USB_CTRL_MAC_CTRL_SEL_MASK)
+/*! @} */
+
+/*! @name MMC_TC - SDIO Timing Control Register */
+/*! @{ */
+#define SYS_CTL_MMC_TC_MMC_RTC_MASK (0x3U)
+#define SYS_CTL_MMC_TC_MMC_RTC_SHIFT (0U)
+/*! mmc_rtc - MMC RTC
+ */
+#define SYS_CTL_MMC_TC_MMC_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_MMC_TC_MMC_RTC_SHIFT)) & SYS_CTL_MMC_TC_MMC_RTC_MASK)
+#define SYS_CTL_MMC_TC_MMC_WTC_MASK (0xCU)
+#define SYS_CTL_MMC_TC_MMC_WTC_SHIFT (2U)
+/*! mmc_wtc - MMC WTC
+ */
+#define SYS_CTL_MMC_TC_MMC_WTC(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_MMC_TC_MMC_WTC_SHIFT)) & SYS_CTL_MMC_TC_MMC_WTC_MASK)
+/*! @} */
+
+/*! @name EXT_FLASH_SEL - External Flash select register */
+/*! @{ */
+#define SYS_CTL_EXT_FLASH_SEL_EXTERNAL_FLASH_SEL_MASK (0x1U)
+#define SYS_CTL_EXT_FLASH_SEL_EXTERNAL_FLASH_SEL_SHIFT (0U)
+/*! external_flash_sel - Flash Controller Connect
+ * 0b0..in-package FLASH
+ * 0b1..external FLASH
+ */
+#define SYS_CTL_EXT_FLASH_SEL_EXTERNAL_FLASH_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYS_CTL_EXT_FLASH_SEL_EXTERNAL_FLASH_SEL_SHIFT)) & SYS_CTL_EXT_FLASH_SEL_EXTERNAL_FLASH_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group SYS_CTL_Register_Masks */
+
+
+/* SYS_CTL - Peripheral instance base addresses */
+/** Peripheral SYS_CTL base address */
+#define SYS_CTL_BASE (0x480B0000u)
+/** Peripheral SYS_CTL base pointer */
+#define SYS_CTL ((SYS_CTL_Type *)SYS_CTL_BASE)
+/** Array initializer of SYS_CTL peripheral base addresses */
+#define SYS_CTL_BASE_ADDRS { SYS_CTL_BASE }
+/** Array initializer of SYS_CTL peripheral base pointers */
+#define SYS_CTL_BASE_PTRS { SYS_CTL }
+
+/*!
+ * @}
+ */ /* end of group SYS_CTL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ __IO uint32_t DLL; /**< Divisor Latch Low Byte Registers, offset: 0x0 */
+ __I uint32_t RBR; /**< Receive Buffer Register, offset: 0x0 */
+ __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */
+ };
+ union { /* offset: 0x4 */
+ __IO uint32_t DLH; /**< Divisor Latch High Byte Registers, offset: 0x4 */
+ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */
+ };
+ union { /* offset: 0x8 */
+ __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */
+ __I uint32_t IIR; /**< Interrupt Identification Register, offset: 0x8 */
+ };
+ __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */
+ __IO uint32_t MCR; /**< Modem Control Register, offset: 0x10 */
+ __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */
+ __I uint32_t MSR; /**< Modem Status Register, offset: 0x18 */
+ __IO uint32_t SCR; /**< Scratchpad Register, offset: 0x1C */
+ __IO uint32_t ISR; /**< Infrared Selection Register, offset: 0x20 */
+ __I uint32_t RFOR; /**< Receive FIFO Occupancy Register, offset: 0x24 */
+ __IO uint32_t ABR; /**< Auto-Baud Control Register, offset: 0x28 */
+ __I uint32_t ACR; /**< Auto-Baud Count Register, offset: 0x2C */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/*! @name DLL - Divisor Latch Low Byte Registers */
+/*! @{ */
+#define UART_DLL_DLL_MASK (0xFFU)
+#define UART_DLL_DLL_SHIFT (0U)
+/*! DLL - DLL, Low-byte compare value to generate baud rate
+ */
+#define UART_DLL_DLL(x) (((uint32_t)(((uint32_t)(x)) << UART_DLL_DLL_SHIFT)) & UART_DLL_DLL_MASK)
+/*! @} */
+
+/*! @name RBR - Receive Buffer Register */
+/*! @{ */
+#define UART_RBR_BYTE_0_MASK (0xFFU)
+#define UART_RBR_BYTE_0_SHIFT (0U)
+/*! BYTE_0 - Byte 0
+ */
+#define UART_RBR_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << UART_RBR_BYTE_0_SHIFT)) & UART_RBR_BYTE_0_MASK)
+#define UART_RBR_BYTE_1_MASK (0xFF00U)
+#define UART_RBR_BYTE_1_SHIFT (8U)
+/*! BYTE_1 - Byte 1(valid only in 32-bit peripheral bus mode)
+ */
+#define UART_RBR_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << UART_RBR_BYTE_1_SHIFT)) & UART_RBR_BYTE_1_MASK)
+#define UART_RBR_BYTE_2_MASK (0xFF0000U)
+#define UART_RBR_BYTE_2_SHIFT (16U)
+/*! BYTE_2 - Byte 2(valid only in 32-bit peripheral bus mode)
+ */
+#define UART_RBR_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << UART_RBR_BYTE_2_SHIFT)) & UART_RBR_BYTE_2_MASK)
+#define UART_RBR_BYTE_3_MASK (0xFF000000U)
+#define UART_RBR_BYTE_3_SHIFT (24U)
+/*! BYTE_3 - Byte 3(valid only in 32-bit peripheral bus mode)
+ */
+#define UART_RBR_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << UART_RBR_BYTE_3_SHIFT)) & UART_RBR_BYTE_3_MASK)
+/*! @} */
+
+/*! @name THR - Transmit Holding Register */
+/*! @{ */
+#define UART_THR_BYTE_0_MASK (0xFFU)
+#define UART_THR_BYTE_0_SHIFT (0U)
+/*! BYTE_0 - Byte 0
+ */
+#define UART_THR_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << UART_THR_BYTE_0_SHIFT)) & UART_THR_BYTE_0_MASK)
+#define UART_THR_BYTE_1_MASK (0xFF00U)
+#define UART_THR_BYTE_1_SHIFT (8U)
+/*! BYTE_1 - Byte 1 (valid only in 32-bit peripheral bus mode)
+ */
+#define UART_THR_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << UART_THR_BYTE_1_SHIFT)) & UART_THR_BYTE_1_MASK)
+#define UART_THR_BYTE_2_MASK (0xFF0000U)
+#define UART_THR_BYTE_2_SHIFT (16U)
+/*! BYTE_2 - Byte 2 (valid only in 32-bit peripheral bus mode)
+ */
+#define UART_THR_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << UART_THR_BYTE_2_SHIFT)) & UART_THR_BYTE_2_MASK)
+#define UART_THR_BYTE_3_MASK (0xFF000000U)
+#define UART_THR_BYTE_3_SHIFT (24U)
+/*! BYTE_3 - Byte 3 (valid only in 32-bit peripheral bus mode)
+ */
+#define UART_THR_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << UART_THR_BYTE_3_SHIFT)) & UART_THR_BYTE_3_MASK)
+/*! @} */
+
+/*! @name DLH - Divisor Latch High Byte Registers */
+/*! @{ */
+#define UART_DLH_DLH_MASK (0xFFU)
+#define UART_DLH_DLH_SHIFT (0U)
+/*! DLH - DLH, High-byte compare value to generate baud rate
+ */
+#define UART_DLH_DLH(x) (((uint32_t)(((uint32_t)(x)) << UART_DLH_DLH_SHIFT)) & UART_DLH_DLH_MASK)
+/*! @} */
+
+/*! @name IER - Interrupt Enable Register */
+/*! @{ */
+#define UART_IER_RAVIE_MASK (0x1U)
+#define UART_IER_RAVIE_SHIFT (0U)
+/*! RAVIE - Receiver Data Available Interrupt Enable (Source IIR[IID])
+ * 0b0..Receiver data availble(trigger threshold reached) interrupt disabled
+ * 0b1..Receiver data availble(trigger threshold reached) interrupt enabled
+ */
+#define UART_IER_RAVIE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RAVIE_SHIFT)) & UART_IER_RAVIE_MASK)
+#define UART_IER_TIE_MASK (0x2U)
+#define UART_IER_TIE_SHIFT (1U)
+/*! TIE - Transmit Data Request Interrupt Enable(Source IIR[IID])
+ * 0b0..Transmit FIFO data request interrupt disabled
+ * 0b1..Transmit FIFO data request interrupt enabled
+ */
+#define UART_IER_TIE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_TIE_SHIFT)) & UART_IER_TIE_MASK)
+#define UART_IER_RLSE_MASK (0x4U)
+#define UART_IER_RLSE_SHIFT (2U)
+/*! RLSE - Receiver Line Status Interrupt Enable (Source IIR[IID])
+ * 0b0..Receiver line status interrupt disabled
+ * 0b1..Receiver line status interrupt enabled
+ */
+#define UART_IER_RLSE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RLSE_SHIFT)) & UART_IER_RLSE_MASK)
+#define UART_IER_MIE_MASK (0x8U)
+#define UART_IER_MIE_SHIFT (3U)
+/*! MIE - Modem Interrupt Enable (Source IIR[IID])
+ * 0b0..Modem status interrupt disabled
+ * 0b1..Modem status interrupt enabled
+ */
+#define UART_IER_MIE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_MIE_SHIFT)) & UART_IER_MIE_MASK)
+#define UART_IER_RTOIE_MASK (0x10U)
+#define UART_IER_RTOIE_SHIFT (4U)
+/*! RTOIE - Receiver Time-out Interrupt Enable (Source IIR[TOD])
+ * 0b0..Receiver data time-out interrupt disabled
+ * 0b1..Receiver data time-out interrupt enabled
+ */
+#define UART_IER_RTOIE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_RTOIE_SHIFT)) & UART_IER_RTOIE_MASK)
+#define UART_IER_NRZE_MASK (0x20U)
+#define UART_IER_NRZE_SHIFT (5U)
+/*! NRZE - NRZ Coding Enable
+ * 0b0..NRZ coding disabled
+ * 0b1..NRZ coding enabled
+ */
+#define UART_IER_NRZE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_NRZE_SHIFT)) & UART_IER_NRZE_MASK)
+#define UART_IER_UUE_MASK (0x40U)
+#define UART_IER_UUE_SHIFT (6U)
+/*! UUE - UART Unit Enable
+ * 0b0..the unit is disabled
+ * 0b1..the unit is enabled
+ */
+#define UART_IER_UUE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_UUE_SHIFT)) & UART_IER_UUE_MASK)
+#define UART_IER_DMAE_MASK (0x80U)
+#define UART_IER_DMAE_SHIFT (7U)
+/*! DMAE - DMA Requests Enable
+ * 0b0..DMA requests are disabled
+ * 0b1..DMA requests are enabled
+ */
+#define UART_IER_DMAE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_DMAE_SHIFT)) & UART_IER_DMAE_MASK)
+#define UART_IER_HSE_MASK (0x100U)
+#define UART_IER_HSE_SHIFT (8U)
+/*! HSE - High Speed UART Enable (HSE)
+ */
+#define UART_IER_HSE(x) (((uint32_t)(((uint32_t)(x)) << UART_IER_HSE_SHIFT)) & UART_IER_HSE_MASK)
+/*! @} */
+
+/*! @name FCR - FIFO Control Register */
+/*! @{ */
+#define UART_FCR_TRFIFOE_MASK (0x1U)
+#define UART_FCR_TRFIFOE_SHIFT (0U)
+/*! TRFIFOE - Transmit and Receive FIFO Enable
+ * 0b0..FIFOs are disabled
+ * 0b1..FIFOs are enabled
+ */
+#define UART_FCR_TRFIFOE(x) (((uint32_t)(((uint32_t)(x)) << UART_FCR_TRFIFOE_SHIFT)) & UART_FCR_TRFIFOE_MASK)
+#define UART_FCR_RESETRF_MASK (0x2U)
+#define UART_FCR_RESETRF_SHIFT (1U)
+/*! RESETRF - Reset Receive FIFO
+ * 0b0..Writing 0 has no effect
+ * 0b1..The receive FIFO is cleared
+ */
+#define UART_FCR_RESETRF(x) (((uint32_t)(((uint32_t)(x)) << UART_FCR_RESETRF_SHIFT)) & UART_FCR_RESETRF_MASK)
+#define UART_FCR_RESETTF_MASK (0x4U)
+#define UART_FCR_RESETTF_SHIFT (2U)
+/*! RESETTF - Reset Transmit FIFO
+ * 0b0..Writing 0 has no effect
+ * 0b1..The transmit FIFO is cleared
+ */
+#define UART_FCR_RESETTF(x) (((uint32_t)(((uint32_t)(x)) << UART_FCR_RESETTF_SHIFT)) & UART_FCR_RESETTF_MASK)
+#define UART_FCR_TIL_MASK (0x8U)
+#define UART_FCR_TIL_SHIFT (3U)
+/*! TIL - Transmitter Interrupt Level
+ * 0b0..Interrupt/DMA request when FIFO is half empty
+ * 0b1..Interrupt/DMA request when FIFO is empty
+ */
+#define UART_FCR_TIL(x) (((uint32_t)(((uint32_t)(x)) << UART_FCR_TIL_SHIFT)) & UART_FCR_TIL_MASK)
+#define UART_FCR_BUS_MASK (0x20U)
+#define UART_FCR_BUS_SHIFT (5U)
+/*! BUS - 32-Bit Peripheral Bus
+ * 0b0..8-bit peripheral bus
+ * 0b1..32-bit peripheral bus, Transmit and Receive FIFO need to be enabled in this mode
+ */
+#define UART_FCR_BUS(x) (((uint32_t)(((uint32_t)(x)) << UART_FCR_BUS_SHIFT)) & UART_FCR_BUS_MASK)
+#define UART_FCR_ITL_MASK (0xC0U)
+#define UART_FCR_ITL_SHIFT (6U)
+/*! ITL - Interrupt Trigger Level
+ * 0b00..1 byte or more in FIFO causes interrupt (Not valid in DMA mode)
+ * 0b01..8 bytes or more in FIFO cause interrupt and DMA request
+ * 0b10..16 bytes or more in FIFO causes interrupt and DMA request
+ * 0b11..32 bytes or more in FIFO causes interrupt and DMA request
+ */
+#define UART_FCR_ITL(x) (((uint32_t)(((uint32_t)(x)) << UART_FCR_ITL_SHIFT)) & UART_FCR_ITL_MASK)
+/*! @} */
+
+/*! @name IIR - Interrupt Identification Register */
+/*! @{ */
+#define UART_IIR_NIP_MASK (0x1U)
+#define UART_IIR_NIP_SHIFT (0U)
+/*! NIP - Interrupt is pending
+ * 0b0..Interrupt is pending (active low)
+ * 0b1..No interrupt is pending
+ */
+#define UART_IIR_NIP(x) (((uint32_t)(((uint32_t)(x)) << UART_IIR_NIP_SHIFT)) & UART_IIR_NIP_MASK)
+#define UART_IIR_IID10_MASK (0x6U)
+#define UART_IIR_IID10_SHIFT (1U)
+/*! IID10 - Interrupt Source Encoded
+ * 0b00..Modern Status (CTS)
+ * 0b01..Transmit FIFO request data
+ * 0b10..Receive data available
+ * 0b11..Receive error (overrun)
+ */
+#define UART_IIR_IID10(x) (((uint32_t)(((uint32_t)(x)) << UART_IIR_IID10_SHIFT)) & UART_IIR_IID10_MASK)
+#define UART_IIR_TOD_MASK (0x8U)
+#define UART_IIR_TOD_SHIFT (3U)
+/*! TOD - Timeout Detected
+ * 0b0..No timeout interrupt is pending
+ * 0b1..Timeout interrupt is pending (FIFO mode only)
+ */
+#define UART_IIR_TOD(x) (((uint32_t)(((uint32_t)(x)) << UART_IIR_TOD_SHIFT)) & UART_IIR_TOD_MASK)
+#define UART_IIR_ABL_MASK (0x10U)
+#define UART_IIR_ABL_SHIFT (4U)
+/*! ABL - Auto-baud Lock
+ * 0b0..Auto-baud circuitry has not programmed Divisor Latch registers (DLR)
+ * 0b1..Divisor Latch registers (DLR) programmed by auto-baud circuitry
+ */
+#define UART_IIR_ABL(x) (((uint32_t)(((uint32_t)(x)) << UART_IIR_ABL_SHIFT)) & UART_IIR_ABL_MASK)
+#define UART_IIR_EOC_MASK (0x20U)
+#define UART_IIR_EOC_SHIFT (5U)
+/*! EOC - DMA End of Descriptor Chain
+ * 0b0..DMA has not signaled the end of its programmed Descriptor Chain
+ * 0b1..DMA has signaled the end of its programmed Descriptor Chain
+ */
+#define UART_IIR_EOC(x) (((uint32_t)(((uint32_t)(x)) << UART_IIR_EOC_SHIFT)) & UART_IIR_EOC_MASK)
+#define UART_IIR_FIFOES10_MASK (0xC0U)
+#define UART_IIR_FIFOES10_SHIFT (6U)
+/*! FIFOES10 - FIFO Mode Enable Status
+ * 0b00..Non-FIFO mode is selected
+ * 0b01..reserved
+ * 0b10..reserved
+ * 0b11..FIFO mode is selected
+ */
+#define UART_IIR_FIFOES10(x) (((uint32_t)(((uint32_t)(x)) << UART_IIR_FIFOES10_SHIFT)) & UART_IIR_FIFOES10_MASK)
+/*! @} */
+
+/*! @name LCR - Line Control Register */
+/*! @{ */
+#define UART_LCR_WLS10_MASK (0x3U)
+#define UART_LCR_WLS10_SHIFT (0U)
+/*! WLS10 - World Length Select
+ * 0b00..5-bit character
+ * 0b01..6-bit character
+ * 0b10..7-bit character
+ * 0b11..8-bit character
+ */
+#define UART_LCR_WLS10(x) (((uint32_t)(((uint32_t)(x)) << UART_LCR_WLS10_SHIFT)) & UART_LCR_WLS10_MASK)
+#define UART_LCR_STB_MASK (0x4U)
+#define UART_LCR_STB_SHIFT (2U)
+/*! STB - Stop Bits
+ * 0b0..1 stop bit
+ * 0b1..2 stop bit
+ */
+#define UART_LCR_STB(x) (((uint32_t)(((uint32_t)(x)) << UART_LCR_STB_SHIFT)) & UART_LCR_STB_MASK)
+#define UART_LCR_PEN_MASK (0x8U)
+#define UART_LCR_PEN_SHIFT (3U)
+/*! PEN - Parity Enable
+ * 0b0..No parity
+ * 0b1..
+ */
+#define UART_LCR_PEN(x) (((uint32_t)(((uint32_t)(x)) << UART_LCR_PEN_SHIFT)) & UART_LCR_PEN_MASK)
+#define UART_LCR_EPS_MASK (0x10U)
+#define UART_LCR_EPS_SHIFT (4U)
+/*! EPS - Even Parity Select
+ * 0b0..Sends or checks for odd parity
+ * 0b1..Sends or checks for even parity
+ */
+#define UART_LCR_EPS(x) (((uint32_t)(((uint32_t)(x)) << UART_LCR_EPS_SHIFT)) & UART_LCR_EPS_MASK)
+#define UART_LCR_STKYP_MASK (0x20U)
+#define UART_LCR_STKYP_SHIFT (5U)
+/*! STKYP - Sticky Parity
+ * 0b0..no effect on parity bit
+ * 0b1..forces parity bit to be opposite of EPS bit value
+ */
+#define UART_LCR_STKYP(x) (((uint32_t)(((uint32_t)(x)) << UART_LCR_STKYP_SHIFT)) & UART_LCR_STKYP_MASK)
+#define UART_LCR_SB_MASK (0x40U)
+#define UART_LCR_SB_SHIFT (6U)
+/*! SB - Set Break
+ * 0b0..no effect on TXD output
+ * 0b1..forces TXD output to 0
+ */
+#define UART_LCR_SB(x) (((uint32_t)(((uint32_t)(x)) << UART_LCR_SB_SHIFT)) & UART_LCR_SB_MASK)
+#define UART_LCR_DLAB_MASK (0x80U)
+#define UART_LCR_DLAB_SHIFT (7U)
+/*! DLAB - Divisor Latch Access
+ * 0b0..access Transmit Holding Register, Receive Buffer Register, and Interrupt Enable Register
+ * 0b1..access Divisor Latch Registers
+ */
+#define UART_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << UART_LCR_DLAB_SHIFT)) & UART_LCR_DLAB_MASK)
+/*! @} */
+
+/*! @name MCR - Modem Control Register */
+/*! @{ */
+#define UART_MCR_DTR_MASK (0x1U)
+#define UART_MCR_DTR_SHIFT (0U)
+/*! DTR - Data Terminal Ready
+ * 0b0..nDTR pin is 1
+ * 0b1..nDTR pin is 0
+ */
+#define UART_MCR_DTR(x) (((uint32_t)(((uint32_t)(x)) << UART_MCR_DTR_SHIFT)) & UART_MCR_DTR_MASK)
+#define UART_MCR_RTS_MASK (0x2U)
+#define UART_MCR_RTS_SHIFT (1U)
+/*! RTS - Request to Send
+ * 0b0..non-auto-flow mode
+ * 0b1..auto-flow mode
+ */
+#define UART_MCR_RTS(x) (((uint32_t)(((uint32_t)(x)) << UART_MCR_RTS_SHIFT)) & UART_MCR_RTS_MASK)
+#define UART_MCR_OUT1_MASK (0x4U)
+#define UART_MCR_OUT1_SHIFT (2U)
+/*! OUT1 - Test Bit
+ * 0b0..Force MSR[RI] forced to 0
+ * 0b1..Force MSR[RI] forced to 1
+ */
+#define UART_MCR_OUT1(x) (((uint32_t)(((uint32_t)(x)) << UART_MCR_OUT1_SHIFT)) & UART_MCR_OUT1_MASK)
+#define UART_MCR_OUT2_MASK (0x8U)
+#define UART_MCR_OUT2_SHIFT (3U)
+/*! OUT2 - OUT2 Signal Control
+ * 0b0..UART interrupt is disabled when loop is clear; otherwise MSR[DCD] forced to 0
+ * 0b1..UART interrupt is enabled when loop is clear; otherwise 1 = MSR[DCD] forced to 1
+ */
+#define UART_MCR_OUT2(x) (((uint32_t)(((uint32_t)(x)) << UART_MCR_OUT2_SHIFT)) & UART_MCR_OUT2_MASK)
+#define UART_MCR_LOOP_MASK (0x10U)
+#define UART_MCR_LOOP_SHIFT (4U)
+/*! LOOP - Loopback Mode
+ * 0b0..normal UART operation
+ * 0b1..loopback mode UART operation
+ */
+#define UART_MCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_MCR_LOOP_SHIFT)) & UART_MCR_LOOP_MASK)
+#define UART_MCR_AFE_MASK (0x20U)
+#define UART_MCR_AFE_SHIFT (5U)
+/*! AFE - Auto-flow Control Enable
+ * 0b0..auto-RTS and auto-CTS are disabled
+ * 0b1..auto-RTS and auto-CTS are enabled
+ */
+#define UART_MCR_AFE(x) (((uint32_t)(((uint32_t)(x)) << UART_MCR_AFE_SHIFT)) & UART_MCR_AFE_MASK)
+/*! @} */
+
+/*! @name LSR - Line Status Register */
+/*! @{ */
+#define UART_LSR_DR_MASK (0x1U)
+#define UART_LSR_DR_SHIFT (0U)
+/*! DR - Data Ready
+ * 0b0..No data has been received
+ * 0b1..Data is available in RBR or the FIFO
+ */
+#define UART_LSR_DR(x) (((uint32_t)(((uint32_t)(x)) << UART_LSR_DR_SHIFT)) & UART_LSR_DR_MASK)
+#define UART_LSR_OE_MASK (0x2U)
+#define UART_LSR_OE_SHIFT (1U)
+/*! OE - Overrun Error
+ * 0b0..No data has been lost
+ * 0b1..Receive data has been lost
+ */
+#define UART_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << UART_LSR_OE_SHIFT)) & UART_LSR_OE_MASK)
+#define UART_LSR_PE_MASK (0x4U)
+#define UART_LSR_PE_SHIFT (2U)
+/*! PE - Parity Error
+ * 0b0..No parity error
+ * 0b1..Parity error has been detected
+ */
+#define UART_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << UART_LSR_PE_SHIFT)) & UART_LSR_PE_MASK)
+#define UART_LSR_FE_MASK (0x8U)
+#define UART_LSR_FE_SHIFT (3U)
+/*! FE - Framing Error
+ * 0b0..No Framing error
+ * 0b1..Invalid stop bit has been detected
+ */
+#define UART_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << UART_LSR_FE_SHIFT)) & UART_LSR_FE_MASK)
+#define UART_LSR_BI_MASK (0x10U)
+#define UART_LSR_BI_SHIFT (4U)
+/*! BI - Break Interrupt
+ * 0b0..No break signal has been received
+ * 0b1..Break signal received
+ */
+#define UART_LSR_BI(x) (((uint32_t)(((uint32_t)(x)) << UART_LSR_BI_SHIFT)) & UART_LSR_BI_MASK)
+#define UART_LSR_TDRQ_MASK (0x20U)
+#define UART_LSR_TDRQ_SHIFT (5U)
+/*! TDRQ - Transmit Data Request
+ * 0b0..There is data in the holding register or FIFO waiting to be shifted out
+ * 0b1..transmit FIFO has half or less then half data
+ */
+#define UART_LSR_TDRQ(x) (((uint32_t)(((uint32_t)(x)) << UART_LSR_TDRQ_SHIFT)) & UART_LSR_TDRQ_MASK)
+#define UART_LSR_TEMT_MASK (0x40U)
+#define UART_LSR_TEMT_SHIFT (6U)
+/*! TEMT - Transmitter Empty
+ * 0b0..There is data in the transmit shift register, the Transmit Holding Register, or the FIFO
+ * 0b1..All the data in the transmitter has been shifted out
+ */
+#define UART_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << UART_LSR_TEMT_SHIFT)) & UART_LSR_TEMT_MASK)
+#define UART_LSR_FIFOE_MASK (0x80U)
+#define UART_LSR_FIFOE_SHIFT (7U)
+/*! FIFOE - FIFO Error Status
+ * 0b0..No FIFO or no errors in receive FIFO
+ * 0b1..At least one character in receive FIFO has errors
+ */
+#define UART_LSR_FIFOE(x) (((uint32_t)(((uint32_t)(x)) << UART_LSR_FIFOE_SHIFT)) & UART_LSR_FIFOE_MASK)
+/*! @} */
+
+/*! @name MSR - Modem Status Register */
+/*! @{ */
+#define UART_MSR_DCTS_MASK (0x1U)
+#define UART_MSR_DCTS_SHIFT (0U)
+/*! DCTS - Delta Clear to Send
+ * 0b0..No change in nCTS pin since last read of MSR
+ * 0b1..nCTS pin has changed state
+ */
+#define UART_MSR_DCTS(x) (((uint32_t)(((uint32_t)(x)) << UART_MSR_DCTS_SHIFT)) & UART_MSR_DCTS_MASK)
+#define UART_MSR_DDSR_MASK (0x2U)
+#define UART_MSR_DDSR_SHIFT (1U)
+/*! DDSR - Delta Data Set Ready
+ * 0b0..No change in nDSR pin since last read of MSR
+ * 0b1..nDSR pin has changed state
+ */
+#define UART_MSR_DDSR(x) (((uint32_t)(((uint32_t)(x)) << UART_MSR_DDSR_SHIFT)) & UART_MSR_DDSR_MASK)
+#define UART_MSR_TERI_MASK (0x4U)
+#define UART_MSR_TERI_SHIFT (2U)
+/*! TERI - Trailing Edge Ring Indicator
+ * 0b0..nRI pin has not changed from 0 to 1 since last read of MSR
+ * 0b1..nRI has changed state
+ */
+#define UART_MSR_TERI(x) (((uint32_t)(((uint32_t)(x)) << UART_MSR_TERI_SHIFT)) & UART_MSR_TERI_MASK)
+#define UART_MSR_DDCD_MASK (0x8U)
+#define UART_MSR_DDCD_SHIFT (3U)
+/*! DDCD - Delta Data Carrier Detect
+ * 0b0..No change in nDCD pin since last read of MSR
+ * 0b1..nDCD pin has changed state
+ */
+#define UART_MSR_DDCD(x) (((uint32_t)(((uint32_t)(x)) << UART_MSR_DDCD_SHIFT)) & UART_MSR_DDCD_MASK)
+#define UART_MSR_CTS_MASK (0x10U)
+#define UART_MSR_CTS_SHIFT (4U)
+/*! CTS - Clear to Send
+ * 0b0..nCTS pin is 1
+ * 0b1..nCTS pin is 0
+ */
+#define UART_MSR_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_MSR_CTS_SHIFT)) & UART_MSR_CTS_MASK)
+#define UART_MSR_DSR_MASK (0x20U)
+#define UART_MSR_DSR_SHIFT (5U)
+/*! DSR - Data Set Ready
+ * 0b0..nDSR pin is 1
+ * 0b1..nDSR pin is 0
+ */
+#define UART_MSR_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_MSR_DSR_SHIFT)) & UART_MSR_DSR_MASK)
+#define UART_MSR_RI_MASK (0x40U)
+#define UART_MSR_RI_SHIFT (6U)
+/*! RI - Ring Indicator
+ * 0b0..nRI pin is 1
+ * 0b1..nRI pin is 0
+ */
+#define UART_MSR_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_MSR_RI_SHIFT)) & UART_MSR_RI_MASK)
+#define UART_MSR_DCD_MASK (0x80U)
+#define UART_MSR_DCD_SHIFT (7U)
+/*! DCD - Data Carrier Detect
+ * 0b0..nDCD pin is 1
+ * 0b1..nDCD pin is 0
+ */
+#define UART_MSR_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_MSR_DCD_SHIFT)) & UART_MSR_DCD_MASK)
+/*! @} */
+
+/*! @name SCR - Scratchpad Register */
+/*! @{ */
+#define UART_SCR_SCRATCHPAD_MASK (0xFFU)
+#define UART_SCR_SCRATCHPAD_SHIFT (0U)
+/*! SCRATCHPAD - No effect on UART functions
+ */
+#define UART_SCR_SCRATCHPAD(x) (((uint32_t)(((uint32_t)(x)) << UART_SCR_SCRATCHPAD_SHIFT)) & UART_SCR_SCRATCHPAD_MASK)
+/*! @} */
+
+/*! @name ISR - Infrared Selection Register */
+/*! @{ */
+#define UART_ISR_XMITIR_MASK (0x1U)
+#define UART_ISR_XMITIR_SHIFT (0U)
+/*! XMITIR - Transmitter SIR Enable
+ * 0b0..Transmitter is in UART mode
+ * 0b1..Transmitter is in infrared mode
+ */
+#define UART_ISR_XMITIR(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_XMITIR_SHIFT)) & UART_ISR_XMITIR_MASK)
+#define UART_ISR_RCVEIR_MASK (0x2U)
+#define UART_ISR_RCVEIR_SHIFT (1U)
+/*! RCVEIR - Receiver SIR Enable
+ * 0b0..Receiver is in UART mode
+ * 0b1..Receiver is in infrared mode
+ */
+#define UART_ISR_RCVEIR(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RCVEIR_SHIFT)) & UART_ISR_RCVEIR_MASK)
+#define UART_ISR_XMODE_MASK (0x4U)
+#define UART_ISR_XMODE_SHIFT (2U)
+/*! XMODE - Transmit Pulse Width Select
+ * 0b0..Transmit pulse width is 3/16 of a bit time wide
+ * 0b1..Transmit pulse width is 1.6 ms
+ */
+#define UART_ISR_XMODE(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_XMODE_SHIFT)) & UART_ISR_XMODE_MASK)
+#define UART_ISR_TXPL_MASK (0x8U)
+#define UART_ISR_TXPL_SHIFT (3U)
+/*! TXPL - Transmit Data Polarity
+ * 0b0..SIR encoder generates a positive pulse for a data bit of 0
+ * 0b1..SIR encoder generates a negetive pulse for a data bit of 0
+ */
+#define UART_ISR_TXPL(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_TXPL_SHIFT)) & UART_ISR_TXPL_MASK)
+#define UART_ISR_RXPL_MASK (0x10U)
+#define UART_ISR_RXPL_SHIFT (4U)
+/*! RXPL - Receive Data Polarity
+ * 0b0..SIR decoder takes positive pulses as 0s
+ * 0b1..SIR decoder takes negative pulses as 0s
+ */
+#define UART_ISR_RXPL(x) (((uint32_t)(((uint32_t)(x)) << UART_ISR_RXPL_SHIFT)) & UART_ISR_RXPL_MASK)
+/*! @} */
+
+/*! @name RFOR - Receive FIFO Occupancy Register */
+/*! @{ */
+#define UART_RFOR_BYTE_COUNT_MASK (0x3FU)
+#define UART_RFOR_BYTE_COUNT_SHIFT (0U)
+/*! BYTE_COUNT - Number of bytes (0-63) remaining in receive FIFO
+ */
+#define UART_RFOR_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << UART_RFOR_BYTE_COUNT_SHIFT)) & UART_RFOR_BYTE_COUNT_MASK)
+/*! @} */
+
+/*! @name ABR - Auto-Baud Control Register */
+/*! @{ */
+#define UART_ABR_ABE_MASK (0x1U)
+#define UART_ABR_ABE_SHIFT (0U)
+/*! ABE - Auto-baud enable
+ * 0b0..auto-baud disabled
+ * 0b1..auto-baud enabled
+ */
+#define UART_ABR_ABE(x) (((uint32_t)(((uint32_t)(x)) << UART_ABR_ABE_SHIFT)) & UART_ABR_ABE_MASK)
+#define UART_ABR_ABLIE_MASK (0x2U)
+#define UART_ABR_ABLIE_SHIFT (1U)
+/*! ABLIE - Auto-baud-lock interrupt enable
+ * 0b0..auto-baud-lock interrupt is disabled
+ * 0b1..auto-baud-lock interrupt is enabled
+ */
+#define UART_ABR_ABLIE(x) (((uint32_t)(((uint32_t)(x)) << UART_ABR_ABLIE_SHIFT)) & UART_ABR_ABLIE_MASK)
+#define UART_ABR_ABUP_MASK (0x4U)
+#define UART_ABR_ABUP_SHIFT (2U)
+/*! ABUP - Auto-baud programmer select
+ * 0b0..CPU programs Divisor Latch register
+ * 0b1..UART programs Divisor Latch register
+ */
+#define UART_ABR_ABUP(x) (((uint32_t)(((uint32_t)(x)) << UART_ABR_ABUP_SHIFT)) & UART_ABR_ABUP_MASK)
+#define UART_ABR_ABT_MASK (0x8U)
+#define UART_ABR_ABT_SHIFT (3U)
+/*! ABT - Auto-Baud table
+ * 0b0..Formula used to calculate baud rates
+ * 0b1..Table used to calculate baud rates, which limits UART to choosing common baud rates
+ */
+#define UART_ABR_ABT(x) (((uint32_t)(((uint32_t)(x)) << UART_ABR_ABT_SHIFT)) & UART_ABR_ABT_MASK)
+/*! @} */
+
+/*! @name ACR - Auto-Baud Count Register */
+/*! @{ */
+#define UART_ACR_COUNT_VALUE_MASK (0xFFFFU)
+#define UART_ACR_COUNT_VALUE_SHIFT (0U)
+/*! COUNT_VALUE - Number of 14.857 MHz clock cycles within a Start-Bit pulse
+ */
+#define UART_ACR_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UART_ACR_COUNT_VALUE_SHIFT)) & UART_ACR_COUNT_VALUE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x46040000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x460C0000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x48020000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { UART0, UART1, UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_IRQS { UART0_IRQn, UART1_IRQn, UART2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBC_Peripheral_Access_Layer USBC Peripheral Access Layer
+ * @{
+ */
+
+/** USBC - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ID; /**< , offset: 0x0 */
+ __I uint32_t HWGENERAL; /**< , offset: 0x4 */
+ __I uint32_t HWHOST; /**< , offset: 0x8 */
+ __I uint32_t HWDEVICE; /**< , offset: 0xC */
+ __I uint32_t HWTXBUF; /**< , offset: 0x10 */
+ __I uint32_t HWRXBUF; /**< , offset: 0x14 */
+ __IO uint32_t HWTXBUF0; /**< , offset: 0x18 */
+ __IO uint32_t HWTXBUF1; /**< , offset: 0x1C */
+ uint8_t RESERVED_0[96];
+ __IO uint32_t GPTIMER0LD; /**< , offset: 0x80 */
+ __IO uint32_t GPTIMER0CTRL; /**< , offset: 0x84 */
+ __IO uint32_t GPTTIMER1LD; /**< , offset: 0x88 */
+ __IO uint32_t GPTIMER1CTRL; /**< , offset: 0x8C */
+ __IO uint32_t SBUSCFG; /**< , offset: 0x90 */
+ uint8_t RESERVED_1[108];
+ __I uint32_t CAPLENGTH; /**< , offset: 0x100 */
+ __I uint32_t HCSPARAMS; /**< , offset: 0x104 */
+ __I uint32_t HCCPARAMS; /**< , offset: 0x108 */
+ uint8_t RESERVED_2[20];
+ __I uint32_t DCIVERSION; /**< , offset: 0x120 */
+ __I uint32_t DCCPARAMS; /**< , offset: 0x124 */
+ __IO uint32_t DEVLPMCSR; /**< , offset: 0x128 */
+ uint8_t RESERVED_3[20];
+ __IO uint32_t USBCMD; /**< , offset: 0x140 */
+ __IO uint32_t USBSTS; /**< , offset: 0x144 */
+ __IO uint32_t USBINTR; /**< , offset: 0x148 */
+ __IO uint32_t FRINDEX; /**< , offset: 0x14C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t PERIODICLISTBASE; /**< , offset: 0x154 */
+ __IO uint32_t ASYNCLISTADDR; /**< , offset: 0x158 */
+ __IO uint32_t TTCTRL; /**< , offset: 0x15C */
+ __IO uint32_t BURSTSIZE; /**< , offset: 0x160 */
+ __IO uint32_t TXFILLTUNING; /**< , offset: 0x164 */
+ __IO uint32_t TXTTFILLTUNING; /**< , offset: 0x168 */
+ __IO uint32_t IC_USB; /**< , offset: 0x16C */
+ __IO uint32_t ULPI_VIEWPORT; /**< , offset: 0x170 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t ENDPTNAK; /**< , offset: 0x178 */
+ __IO uint32_t ENDPTNAKEN; /**< , offset: 0x17C */
+ uint8_t RESERVED_6[4];
+ __IO uint32_t PORTSC1; /**< , offset: 0x184 */
+ __IO uint32_t PORTSC2; /**< , offset: 0x188 */
+ __IO uint32_t PORTSC3; /**< , offset: 0x18C */
+ __IO uint32_t PORTSC4; /**< , offset: 0x190 */
+ __IO uint32_t PORTSC5; /**< , offset: 0x194 */
+ __IO uint32_t PORTSC6; /**< , offset: 0x198 */
+ __IO uint32_t PORTSC7; /**< , offset: 0x19C */
+ __IO uint32_t PORTSC8; /**< , offset: 0x1A0 */
+ __IO uint32_t OTGSC; /**< , offset: 0x1A4 */
+ __IO uint32_t USBMODE; /**< , offset: 0x1A8 */
+ __I uint32_t ENDPTSETUPSTAT; /**< , offset: 0x1AC */
+ __I uint32_t ENDPTPRIME; /**< , offset: 0x1B0 */
+ __I uint32_t ENDPTFLUSH; /**< , offset: 0x1B4 */
+ __I uint32_t ENDPTSTAT; /**< , offset: 0x1B8 */
+ __I uint32_t ENDPTCOMPLETE; /**< , offset: 0x1BC */
+ __IO uint32_t ENDPTCTRL0; /**< , offset: 0x1C0 */
+ __IO uint32_t ENDPTCTRL1; /**< , offset: 0x1C4 */
+ __IO uint32_t ENDPTCTRL2; /**< , offset: 0x1C8 */
+ __IO uint32_t ENDPTCTRL3; /**< , offset: 0x1CC */
+ __IO uint32_t ENDPTCTRL4; /**< , offset: 0x1D0 */
+ __IO uint32_t ENDPTCTRL5; /**< , offset: 0x1D4 */
+ __IO uint32_t ENDPTCTRL6; /**< , offset: 0x1D8 */
+ __IO uint32_t ENDPTCTRL7; /**< , offset: 0x1DC */
+ __IO uint32_t ENDPTCTRL8; /**< , offset: 0x1E0 */
+ __IO uint32_t ENDPTCTRL9; /**< , offset: 0x1E4 */
+ __IO uint32_t ENDPTCTRL10; /**< , offset: 0x1E8 */
+ __IO uint32_t ENDPTCTRL11; /**< , offset: 0x1EC */
+ __IO uint32_t ENDPTCTRL12; /**< , offset: 0x1F0 */
+ __IO uint32_t ENDPTCTRL13; /**< , offset: 0x1F4 */
+ __IO uint32_t ENDPTCTRL14; /**< , offset: 0x1F8 */
+ __IO uint32_t ENDPTCTRL15; /**< , offset: 0x1FC */
+ __I uint32_t PHY_ID; /**< , offset: 0x200 */
+ __IO uint32_t PLL_CONTROL_0; /**< , offset: 0x204 */
+ __IO uint32_t PLL_CONTROL_1; /**< , offset: 0x208 */
+ __I uint32_t RESERVED_ADDR3; /**< , offset: 0x20C */
+ __IO uint32_t TX_CHANNEL_CONTRL_0; /**< , offset: 0x210 */
+ __IO uint32_t TX_CHANNEL_CONTRL_1; /**< , offset: 0x214 */
+ __IO uint32_t TX_CHANNEL_CONTRL_2; /**< , offset: 0x218 */
+ __I uint32_t RESERVED_ADDR7; /**< , offset: 0x21C */
+ __IO uint32_t RX_CHANNEL_CONTRL_0; /**< , offset: 0x220 */
+ __IO uint32_t RX_CHANNEL_CONTRL_1; /**< , offset: 0x224 */
+ __IO uint32_t RX_CHANNEL_CONTRL_2; /**< , offset: 0x228 */
+ uint8_t RESERVED_7[4];
+ __IO uint32_t ANA_CONTRL_0; /**< , offset: 0x230 */
+ __IO uint32_t ANA_CONTRL_1; /**< , offset: 0x234 */
+ __IO uint32_t RESERVED_ADDR_C; /**< , offset: 0x238 */
+ __IO uint32_t DIGITAL_CONTROL_0; /**< , offset: 0x23C */
+ __IO uint32_t DIGITAL_CONTROL_1; /**< , offset: 0x240 */
+ __IO uint32_t DIGITAL_CONTROL_2; /**< , offset: 0x244 */
+ __I uint32_t RESERVED_ADDR_12H; /**< , offset: 0x248 */
+ __IO uint32_t TEST_CONTRL_AND_STATUS_0; /**< , offset: 0x24C */
+ __IO uint32_t TEST_CONTRL_AND_STATUS_1; /**< , offset: 0x250 */
+ __I uint32_t RESERVED_ADDR_15H; /**< , offset: 0x254 */
+ __IO uint32_t PHY_REG_CHGDTC_CONTRL; /**< , offset: 0x258 */
+ __IO uint32_t PHY_REG_OTG_CONTROL; /**< , offset: 0x25C */
+ __IO uint32_t USB2_PHY_MON0; /**< , offset: 0x260 */
+ __IO uint32_t PHY_REG_CHGDTC_CONTRL_1; /**< , offset: 0x264 */
+ __I uint32_t RESERVED_ADDR_1AH; /**< , offset: 0x268 */
+ __I uint32_t RESERVED_ADDR_1BH; /**< , offset: 0x26C */
+ __I uint32_t RESERVED_ADDR_1CH; /**< , offset: 0x270 */
+ __I uint32_t RESERVED_ADDR_1DH; /**< , offset: 0x274 */
+ __I uint32_t INTERNAL_CID; /**< , offset: 0x278 */
+ __I uint32_t USB2_ICID_REG1; /**< , offset: 0x27C */
+} USBC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBC_Register_Masks USBC Register Masks
+ * @{
+ */
+
+/*! @name ID - */
+/*! @{ */
+#define USBC_ID_ID_MASK (0x3FU)
+#define USBC_ID_ID_SHIFT (0U)
+#define USBC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBC_ID_ID_SHIFT)) & USBC_ID_ID_MASK)
+#define USBC_ID_NID_MASK (0x3F00U)
+#define USBC_ID_NID_SHIFT (8U)
+#define USBC_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBC_ID_NID_SHIFT)) & USBC_ID_NID_MASK)
+#define USBC_ID_TAG_MASK (0x1F0000U)
+#define USBC_ID_TAG_SHIFT (16U)
+#define USBC_ID_TAG(x) (((uint32_t)(((uint32_t)(x)) << USBC_ID_TAG_SHIFT)) & USBC_ID_TAG_MASK)
+#define USBC_ID_REVISION_MASK (0x1E00000U)
+#define USBC_ID_REVISION_SHIFT (21U)
+#define USBC_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBC_ID_REVISION_SHIFT)) & USBC_ID_REVISION_MASK)
+#define USBC_ID_VERSION_MASK (0x1E000000U)
+#define USBC_ID_VERSION_SHIFT (25U)
+#define USBC_ID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << USBC_ID_VERSION_SHIFT)) & USBC_ID_VERSION_MASK)
+#define USBC_ID_CIVERSION_MASK (0xE0000000U)
+#define USBC_ID_CIVERSION_SHIFT (29U)
+#define USBC_ID_CIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USBC_ID_CIVERSION_SHIFT)) & USBC_ID_CIVERSION_MASK)
+/*! @} */
+
+/*! @name HWGENERAL - */
+/*! @{ */
+#define USBC_HWGENERAL_RT_MASK (0x1U)
+#define USBC_HWGENERAL_RT_SHIFT (0U)
+#define USBC_HWGENERAL_RT(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_RT_SHIFT)) & USBC_HWGENERAL_RT_MASK)
+#define USBC_HWGENERAL_CLKC_MASK (0x6U)
+#define USBC_HWGENERAL_CLKC_SHIFT (1U)
+#define USBC_HWGENERAL_CLKC(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_CLKC_SHIFT)) & USBC_HWGENERAL_CLKC_MASK)
+#define USBC_HWGENERAL_BWT_MASK (0x8U)
+#define USBC_HWGENERAL_BWT_SHIFT (3U)
+#define USBC_HWGENERAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_BWT_SHIFT)) & USBC_HWGENERAL_BWT_MASK)
+#define USBC_HWGENERAL_PHYW_MASK (0x30U)
+#define USBC_HWGENERAL_PHYW_SHIFT (4U)
+#define USBC_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_PHYW_SHIFT)) & USBC_HWGENERAL_PHYW_MASK)
+#define USBC_HWGENERAL_PHYM_MASK (0x3C0U)
+#define USBC_HWGENERAL_PHYM_SHIFT (6U)
+#define USBC_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_PHYM_SHIFT)) & USBC_HWGENERAL_PHYM_MASK)
+#define USBC_HWGENERAL_SM_MASK (0xC00U)
+#define USBC_HWGENERAL_SM_SHIFT (10U)
+#define USBC_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_SM_SHIFT)) & USBC_HWGENERAL_SM_MASK)
+#define USBC_HWGENERAL_RESERVED_12_MASK (0xFFFFF000U)
+#define USBC_HWGENERAL_RESERVED_12_SHIFT (12U)
+#define USBC_HWGENERAL_RESERVED_12(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWGENERAL_RESERVED_12_SHIFT)) & USBC_HWGENERAL_RESERVED_12_MASK)
+/*! @} */
+
+/*! @name HWHOST - */
+/*! @{ */
+#define USBC_HWHOST_HC_MASK (0x1U)
+#define USBC_HWHOST_HC_SHIFT (0U)
+#define USBC_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_HC_SHIFT)) & USBC_HWHOST_HC_MASK)
+#define USBC_HWHOST_NPORT_MASK (0xEU)
+#define USBC_HWHOST_NPORT_SHIFT (1U)
+#define USBC_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_NPORT_SHIFT)) & USBC_HWHOST_NPORT_MASK)
+#define USBC_HWHOST_RESERVED_4_MASK (0xFFF0U)
+#define USBC_HWHOST_RESERVED_4_SHIFT (4U)
+#define USBC_HWHOST_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_RESERVED_4_SHIFT)) & USBC_HWHOST_RESERVED_4_MASK)
+#define USBC_HWHOST_TTASY_MASK (0xFF0000U)
+#define USBC_HWHOST_TTASY_SHIFT (16U)
+#define USBC_HWHOST_TTASY(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_TTASY_SHIFT)) & USBC_HWHOST_TTASY_MASK)
+#define USBC_HWHOST_TTPER_MASK (0xFF000000U)
+#define USBC_HWHOST_TTPER_SHIFT (24U)
+#define USBC_HWHOST_TTPER(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWHOST_TTPER_SHIFT)) & USBC_HWHOST_TTPER_MASK)
+/*! @} */
+
+/*! @name HWDEVICE - */
+/*! @{ */
+#define USBC_HWDEVICE_DC_MASK (0x1U)
+#define USBC_HWDEVICE_DC_SHIFT (0U)
+#define USBC_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWDEVICE_DC_SHIFT)) & USBC_HWDEVICE_DC_MASK)
+#define USBC_HWDEVICE_DEVEP_MASK (0x3EU)
+#define USBC_HWDEVICE_DEVEP_SHIFT (1U)
+#define USBC_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWDEVICE_DEVEP_SHIFT)) & USBC_HWDEVICE_DEVEP_MASK)
+#define USBC_HWDEVICE_RESERVED_6_MASK (0xFFFFFFC0U)
+#define USBC_HWDEVICE_RESERVED_6_SHIFT (6U)
+#define USBC_HWDEVICE_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWDEVICE_RESERVED_6_SHIFT)) & USBC_HWDEVICE_RESERVED_6_MASK)
+/*! @} */
+
+/*! @name HWTXBUF - */
+/*! @{ */
+#define USBC_HWTXBUF_TXBURST_MASK (0xFFU)
+#define USBC_HWTXBUF_TXBURST_SHIFT (0U)
+#define USBC_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_TXBURST_SHIFT)) & USBC_HWTXBUF_TXBURST_MASK)
+#define USBC_HWTXBUF_TXADD_MASK (0xFF00U)
+#define USBC_HWTXBUF_TXADD_SHIFT (8U)
+#define USBC_HWTXBUF_TXADD(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_TXADD_SHIFT)) & USBC_HWTXBUF_TXADD_MASK)
+#define USBC_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
+#define USBC_HWTXBUF_TXCHANADD_SHIFT (16U)
+#define USBC_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_TXCHANADD_SHIFT)) & USBC_HWTXBUF_TXCHANADD_MASK)
+#define USBC_HWTXBUF_RESERVED_24_MASK (0x7F000000U)
+#define USBC_HWTXBUF_RESERVED_24_SHIFT (24U)
+#define USBC_HWTXBUF_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF_RESERVED_24_SHIFT)) & USBC_HWTXBUF_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name HWRXBUF - */
+/*! @{ */
+#define USBC_HWRXBUF_RXBURST_MASK (0xFFU)
+#define USBC_HWRXBUF_RXBURST_SHIFT (0U)
+#define USBC_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWRXBUF_RXBURST_SHIFT)) & USBC_HWRXBUF_RXBURST_MASK)
+#define USBC_HWRXBUF_RXADD_MASK (0xFF00U)
+#define USBC_HWRXBUF_RXADD_SHIFT (8U)
+#define USBC_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWRXBUF_RXADD_SHIFT)) & USBC_HWRXBUF_RXADD_MASK)
+#define USBC_HWRXBUF_RESERVED_16_MASK (0xFFFF0000U)
+#define USBC_HWRXBUF_RESERVED_16_SHIFT (16U)
+#define USBC_HWRXBUF_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWRXBUF_RESERVED_16_SHIFT)) & USBC_HWRXBUF_RESERVED_16_MASK)
+/*! @} */
+
+/*! @name HWTXBUF0 - */
+/*! @{ */
+#define USBC_HWTXBUF0_TXBURST_MASK (0xFFFFFFFFU)
+#define USBC_HWTXBUF0_TXBURST_SHIFT (0U)
+#define USBC_HWTXBUF0_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF0_TXBURST_SHIFT)) & USBC_HWTXBUF0_TXBURST_MASK)
+/*! @} */
+
+/*! @name HWTXBUF1 - */
+/*! @{ */
+#define USBC_HWTXBUF1_TXBURST_MASK (0xFFFFFFFFU)
+#define USBC_HWTXBUF1_TXBURST_SHIFT (0U)
+#define USBC_HWTXBUF1_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBC_HWTXBUF1_TXBURST_SHIFT)) & USBC_HWTXBUF1_TXBURST_MASK)
+/*! @} */
+
+/*! @name GPTIMER0LD - */
+/*! @{ */
+#define USBC_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
+#define USBC_GPTIMER0LD_GPTLD_SHIFT (0U)
+#define USBC_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0LD_GPTLD_SHIFT)) & USBC_GPTIMER0LD_GPTLD_MASK)
+#define USBC_GPTIMER0LD_RESERVED_24_MASK (0xFF000000U)
+#define USBC_GPTIMER0LD_RESERVED_24_SHIFT (24U)
+#define USBC_GPTIMER0LD_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0LD_RESERVED_24_SHIFT)) & USBC_GPTIMER0LD_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name GPTIMER0CTRL - */
+/*! @{ */
+#define USBC_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
+#define USBC_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
+#define USBC_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_GPTCNT_SHIFT)) & USBC_GPTIMER0CTRL_GPTCNT_MASK)
+#define USBC_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
+#define USBC_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
+#define USBC_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_GPTMODE_SHIFT)) & USBC_GPTIMER0CTRL_GPTMODE_MASK)
+#define USBC_GPTIMER0CTRL_RESERVED_25_MASK (0x3E000000U)
+#define USBC_GPTIMER0CTRL_RESERVED_25_SHIFT (25U)
+#define USBC_GPTIMER0CTRL_RESERVED_25(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_RESERVED_25_SHIFT)) & USBC_GPTIMER0CTRL_RESERVED_25_MASK)
+#define USBC_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
+#define USBC_GPTIMER0CTRL_GPTRST_SHIFT (30U)
+#define USBC_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_GPTRST_SHIFT)) & USBC_GPTIMER0CTRL_GPTRST_MASK)
+#define USBC_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
+#define USBC_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
+#define USBC_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER0CTRL_GPTRUN_SHIFT)) & USBC_GPTIMER0CTRL_GPTRUN_MASK)
+/*! @} */
+
+/*! @name GPTTIMER1LD - */
+/*! @{ */
+#define USBC_GPTTIMER1LD_GPTLD_MASK (0xFFFFFFU)
+#define USBC_GPTTIMER1LD_GPTLD_SHIFT (0U)
+#define USBC_GPTTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTTIMER1LD_GPTLD_SHIFT)) & USBC_GPTTIMER1LD_GPTLD_MASK)
+#define USBC_GPTTIMER1LD_RESERVED_24_MASK (0xFF000000U)
+#define USBC_GPTTIMER1LD_RESERVED_24_SHIFT (24U)
+#define USBC_GPTTIMER1LD_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTTIMER1LD_RESERVED_24_SHIFT)) & USBC_GPTTIMER1LD_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name GPTIMER1CTRL - */
+/*! @{ */
+#define USBC_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
+#define USBC_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
+#define USBC_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_GPTCNT_SHIFT)) & USBC_GPTIMER1CTRL_GPTCNT_MASK)
+#define USBC_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
+#define USBC_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
+#define USBC_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_GPTMODE_SHIFT)) & USBC_GPTIMER1CTRL_GPTMODE_MASK)
+#define USBC_GPTIMER1CTRL_RESERVED_25_MASK (0x3E000000U)
+#define USBC_GPTIMER1CTRL_RESERVED_25_SHIFT (25U)
+#define USBC_GPTIMER1CTRL_RESERVED_25(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_RESERVED_25_SHIFT)) & USBC_GPTIMER1CTRL_RESERVED_25_MASK)
+#define USBC_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
+#define USBC_GPTIMER1CTRL_GPTRST_SHIFT (30U)
+#define USBC_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_GPTRST_SHIFT)) & USBC_GPTIMER1CTRL_GPTRST_MASK)
+#define USBC_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
+#define USBC_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
+#define USBC_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USBC_GPTIMER1CTRL_GPTRUN_SHIFT)) & USBC_GPTIMER1CTRL_GPTRUN_MASK)
+/*! @} */
+
+/*! @name SBUSCFG - */
+/*! @{ */
+#define USBC_SBUSCFG_AHBBRST_MASK (0x7U)
+#define USBC_SBUSCFG_AHBBRST_SHIFT (0U)
+#define USBC_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USBC_SBUSCFG_AHBBRST_SHIFT)) & USBC_SBUSCFG_AHBBRST_MASK)
+#define USBC_SBUSCFG_RESERVED_3_MASK (0xFFFFFFF8U)
+#define USBC_SBUSCFG_RESERVED_3_SHIFT (3U)
+#define USBC_SBUSCFG_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << USBC_SBUSCFG_RESERVED_3_SHIFT)) & USBC_SBUSCFG_RESERVED_3_MASK)
+/*! @} */
+
+/*! @name CAPLENGTH - */
+/*! @{ */
+#define USBC_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
+#define USBC_CAPLENGTH_CAPLENGTH_SHIFT (0U)
+#define USBC_CAPLENGTH_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBC_CAPLENGTH_CAPLENGTH_SHIFT)) & USBC_CAPLENGTH_CAPLENGTH_MASK)
+#define USBC_CAPLENGTH_HCIVERSION_MASK (0xFFFF0000U)
+#define USBC_CAPLENGTH_HCIVERSION_SHIFT (16U)
+#define USBC_CAPLENGTH_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USBC_CAPLENGTH_HCIVERSION_SHIFT)) & USBC_CAPLENGTH_HCIVERSION_MASK)
+/*! @} */
+
+/*! @name HCSPARAMS - */
+/*! @{ */
+#define USBC_HCSPARAMS_N_PORTS_MASK (0xFU)
+#define USBC_HCSPARAMS_N_PORTS_SHIFT (0U)
+#define USBC_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_PORTS_SHIFT)) & USBC_HCSPARAMS_N_PORTS_MASK)
+#define USBC_HCSPARAMS_PPC_MASK (0x10U)
+#define USBC_HCSPARAMS_PPC_SHIFT (4U)
+#define USBC_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_PPC_SHIFT)) & USBC_HCSPARAMS_PPC_MASK)
+#define USBC_HCSPARAMS_RESERVED_5_MASK (0xE0U)
+#define USBC_HCSPARAMS_RESERVED_5_SHIFT (5U)
+#define USBC_HCSPARAMS_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_RESERVED_5_SHIFT)) & USBC_HCSPARAMS_RESERVED_5_MASK)
+#define USBC_HCSPARAMS_N_PCC_MASK (0xF00U)
+#define USBC_HCSPARAMS_N_PCC_SHIFT (8U)
+#define USBC_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_PCC_SHIFT)) & USBC_HCSPARAMS_N_PCC_MASK)
+#define USBC_HCSPARAMS_N_CC_MASK (0xF000U)
+#define USBC_HCSPARAMS_N_CC_SHIFT (12U)
+#define USBC_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_CC_SHIFT)) & USBC_HCSPARAMS_N_CC_MASK)
+#define USBC_HCSPARAMS_PI_MASK (0x10000U)
+#define USBC_HCSPARAMS_PI_SHIFT (16U)
+#define USBC_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_PI_SHIFT)) & USBC_HCSPARAMS_PI_MASK)
+#define USBC_HCSPARAMS_RESERVED_17_MASK (0xE0000U)
+#define USBC_HCSPARAMS_RESERVED_17_SHIFT (17U)
+#define USBC_HCSPARAMS_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_RESERVED_17_SHIFT)) & USBC_HCSPARAMS_RESERVED_17_MASK)
+#define USBC_HCSPARAMS_N_PTT_MASK (0xF00000U)
+#define USBC_HCSPARAMS_N_PTT_SHIFT (20U)
+#define USBC_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_PTT_SHIFT)) & USBC_HCSPARAMS_N_PTT_MASK)
+#define USBC_HCSPARAMS_N_TT_MASK (0xF000000U)
+#define USBC_HCSPARAMS_N_TT_SHIFT (24U)
+#define USBC_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_N_TT_SHIFT)) & USBC_HCSPARAMS_N_TT_MASK)
+#define USBC_HCSPARAMS_RESERVED_28_MASK (0xF0000000U)
+#define USBC_HCSPARAMS_RESERVED_28_SHIFT (28U)
+#define USBC_HCSPARAMS_RESERVED_28(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCSPARAMS_RESERVED_28_SHIFT)) & USBC_HCSPARAMS_RESERVED_28_MASK)
+/*! @} */
+
+/*! @name HCCPARAMS - */
+/*! @{ */
+#define USBC_HCCPARAMS_ADC_MASK (0x1U)
+#define USBC_HCCPARAMS_ADC_SHIFT (0U)
+#define USBC_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_ADC_SHIFT)) & USBC_HCCPARAMS_ADC_MASK)
+#define USBC_HCCPARAMS_PFL_MASK (0x2U)
+#define USBC_HCCPARAMS_PFL_SHIFT (1U)
+#define USBC_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_PFL_SHIFT)) & USBC_HCCPARAMS_PFL_MASK)
+#define USBC_HCCPARAMS_ASP_MASK (0x4U)
+#define USBC_HCCPARAMS_ASP_SHIFT (2U)
+#define USBC_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_ASP_SHIFT)) & USBC_HCCPARAMS_ASP_MASK)
+#define USBC_HCCPARAMS_RESERVED_3_MASK (0x8U)
+#define USBC_HCCPARAMS_RESERVED_3_SHIFT (3U)
+#define USBC_HCCPARAMS_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_RESERVED_3_SHIFT)) & USBC_HCCPARAMS_RESERVED_3_MASK)
+#define USBC_HCCPARAMS_IST_MASK (0xF0U)
+#define USBC_HCCPARAMS_IST_SHIFT (4U)
+#define USBC_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_IST_SHIFT)) & USBC_HCCPARAMS_IST_MASK)
+#define USBC_HCCPARAMS_EECP_MASK (0xFF00U)
+#define USBC_HCCPARAMS_EECP_SHIFT (8U)
+#define USBC_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_EECP_SHIFT)) & USBC_HCCPARAMS_EECP_MASK)
+#define USBC_HCCPARAMS_RESERVED_16_MASK (0xFFFF0000U)
+#define USBC_HCCPARAMS_RESERVED_16_SHIFT (16U)
+#define USBC_HCCPARAMS_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << USBC_HCCPARAMS_RESERVED_16_SHIFT)) & USBC_HCCPARAMS_RESERVED_16_MASK)
+/*! @} */
+
+/*! @name DCIVERSION - */
+/*! @{ */
+#define USBC_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
+#define USBC_DCIVERSION_DCIVERSION_SHIFT (0U)
+#define USBC_DCIVERSION_DCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USBC_DCIVERSION_DCIVERSION_SHIFT)) & USBC_DCIVERSION_DCIVERSION_MASK)
+/*! @} */
+
+/*! @name DCCPARAMS - */
+/*! @{ */
+#define USBC_DCCPARAMS_DEN_MASK (0x1FU)
+#define USBC_DCCPARAMS_DEN_SHIFT (0U)
+#define USBC_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_DEN_SHIFT)) & USBC_DCCPARAMS_DEN_MASK)
+#define USBC_DCCPARAMS_RESERVED_5_MASK (0x60U)
+#define USBC_DCCPARAMS_RESERVED_5_SHIFT (5U)
+#define USBC_DCCPARAMS_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_RESERVED_5_SHIFT)) & USBC_DCCPARAMS_RESERVED_5_MASK)
+#define USBC_DCCPARAMS_DC_MASK (0x80U)
+#define USBC_DCCPARAMS_DC_SHIFT (7U)
+#define USBC_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_DC_SHIFT)) & USBC_DCCPARAMS_DC_MASK)
+#define USBC_DCCPARAMS_HC_MASK (0x100U)
+#define USBC_DCCPARAMS_HC_SHIFT (8U)
+#define USBC_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_HC_SHIFT)) & USBC_DCCPARAMS_HC_MASK)
+#define USBC_DCCPARAMS_RESERVED_9_MASK (0x7FFFFE00U)
+#define USBC_DCCPARAMS_RESERVED_9_SHIFT (9U)
+#define USBC_DCCPARAMS_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_RESERVED_9_SHIFT)) & USBC_DCCPARAMS_RESERVED_9_MASK)
+#define USBC_DCCPARAMS_LPM_EN_MASK (0x80000000U)
+#define USBC_DCCPARAMS_LPM_EN_SHIFT (31U)
+#define USBC_DCCPARAMS_LPM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DCCPARAMS_LPM_EN_SHIFT)) & USBC_DCCPARAMS_LPM_EN_MASK)
+/*! @} */
+
+/*! @name DEVLPMCSR - */
+/*! @{ */
+#define USBC_DEVLPMCSR_INT_L1RSM_MASK (0x1U)
+#define USBC_DEVLPMCSR_INT_L1RSM_SHIFT (0U)
+#define USBC_DEVLPMCSR_INT_L1RSM(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_INT_L1RSM_SHIFT)) & USBC_DEVLPMCSR_INT_L1RSM_MASK)
+#define USBC_DEVLPMCSR_INT_LPMPKT_MASK (0x2U)
+#define USBC_DEVLPMCSR_INT_LPMPKT_SHIFT (1U)
+#define USBC_DEVLPMCSR_INT_LPMPKT(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_INT_LPMPKT_SHIFT)) & USBC_DEVLPMCSR_INT_LPMPKT_MASK)
+#define USBC_DEVLPMCSR_INT_LPMACK_MASK (0x4U)
+#define USBC_DEVLPMCSR_INT_LPMACK_SHIFT (2U)
+#define USBC_DEVLPMCSR_INT_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_INT_LPMACK_SHIFT)) & USBC_DEVLPMCSR_INT_LPMACK_MASK)
+#define USBC_DEVLPMCSR_INT_LPMERR_MASK (0x8U)
+#define USBC_DEVLPMCSR_INT_LPMERR_SHIFT (3U)
+#define USBC_DEVLPMCSR_INT_LPMERR(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_INT_LPMERR_SHIFT)) & USBC_DEVLPMCSR_INT_LPMERR_MASK)
+#define USBC_DEVLPMCSR_IE_L1RSM_MASK (0x10U)
+#define USBC_DEVLPMCSR_IE_L1RSM_SHIFT (4U)
+#define USBC_DEVLPMCSR_IE_L1RSM(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_L1RSM_SHIFT)) & USBC_DEVLPMCSR_IE_L1RSM_MASK)
+#define USBC_DEVLPMCSR_IE_LPMPKT_MASK (0x20U)
+#define USBC_DEVLPMCSR_IE_LPMPKT_SHIFT (5U)
+#define USBC_DEVLPMCSR_IE_LPMPKT(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_LPMPKT_SHIFT)) & USBC_DEVLPMCSR_IE_LPMPKT_MASK)
+#define USBC_DEVLPMCSR_IE_LPMACK_MASK (0x40U)
+#define USBC_DEVLPMCSR_IE_LPMACK_SHIFT (6U)
+#define USBC_DEVLPMCSR_IE_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_LPMACK_SHIFT)) & USBC_DEVLPMCSR_IE_LPMACK_MASK)
+#define USBC_DEVLPMCSR_IE_LPMERR_MASK (0x80U)
+#define USBC_DEVLPMCSR_IE_LPMERR_SHIFT (7U)
+#define USBC_DEVLPMCSR_IE_LPMERR(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_LPMERR_SHIFT)) & USBC_DEVLPMCSR_IE_LPMERR_MASK)
+#define USBC_DEVLPMCSR_RWAKE_EN_MASK (0x100U)
+#define USBC_DEVLPMCSR_RWAKE_EN_SHIFT (8U)
+#define USBC_DEVLPMCSR_RWAKE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_RWAKE_EN_SHIFT)) & USBC_DEVLPMCSR_RWAKE_EN_MASK)
+#define USBC_DEVLPMCSR_L1STATE_MASK (0x200U)
+#define USBC_DEVLPMCSR_L1STATE_SHIFT (9U)
+#define USBC_DEVLPMCSR_L1STATE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_L1STATE_SHIFT)) & USBC_DEVLPMCSR_L1STATE_MASK)
+#define USBC_DEVLPMCSR_IE_L1STATE_MASK (0x400U)
+#define USBC_DEVLPMCSR_IE_L1STATE_SHIFT (10U)
+#define USBC_DEVLPMCSR_IE_L1STATE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_IE_L1STATE_SHIFT)) & USBC_DEVLPMCSR_IE_L1STATE_MASK)
+#define USBC_DEVLPMCSR_ACK_OK_MASK (0x800U)
+#define USBC_DEVLPMCSR_ACK_OK_SHIFT (11U)
+#define USBC_DEVLPMCSR_ACK_OK(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_ACK_OK_SHIFT)) & USBC_DEVLPMCSR_ACK_OK_MASK)
+#define USBC_DEVLPMCSR_STALL_OK_MASK (0x1000U)
+#define USBC_DEVLPMCSR_STALL_OK_SHIFT (12U)
+#define USBC_DEVLPMCSR_STALL_OK(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_STALL_OK_SHIFT)) & USBC_DEVLPMCSR_STALL_OK_MASK)
+#define USBC_DEVLPMCSR_MIN_SLP_EN_MASK (0x2000U)
+#define USBC_DEVLPMCSR_MIN_SLP_EN_SHIFT (13U)
+#define USBC_DEVLPMCSR_MIN_SLP_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_MIN_SLP_EN_SHIFT)) & USBC_DEVLPMCSR_MIN_SLP_EN_MASK)
+#define USBC_DEVLPMCSR_ALWAYS_LOG_MASK (0x4000U)
+#define USBC_DEVLPMCSR_ALWAYS_LOG_SHIFT (14U)
+#define USBC_DEVLPMCSR_ALWAYS_LOG(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_ALWAYS_LOG_SHIFT)) & USBC_DEVLPMCSR_ALWAYS_LOG_MASK)
+#define USBC_DEVLPMCSR_LPM_ON_MASK (0x8000U)
+#define USBC_DEVLPMCSR_LPM_ON_SHIFT (15U)
+#define USBC_DEVLPMCSR_LPM_ON(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LPM_ON_SHIFT)) & USBC_DEVLPMCSR_LPM_ON_MASK)
+#define USBC_DEVLPMCSR_HST_RSM_EN_MASK (0x10000U)
+#define USBC_DEVLPMCSR_HST_RSM_EN_SHIFT (16U)
+#define USBC_DEVLPMCSR_HST_RSM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_HST_RSM_EN_SHIFT)) & USBC_DEVLPMCSR_HST_RSM_EN_MASK)
+#define USBC_DEVLPMCSR_LPM_ANY_EP_MASK (0x20000U)
+#define USBC_DEVLPMCSR_LPM_ANY_EP_SHIFT (17U)
+#define USBC_DEVLPMCSR_LPM_ANY_EP(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LPM_ANY_EP_SHIFT)) & USBC_DEVLPMCSR_LPM_ANY_EP_MASK)
+#define USBC_DEVLPMCSR_RESERVED_18_MASK (0xC0000U)
+#define USBC_DEVLPMCSR_RESERVED_18_SHIFT (18U)
+#define USBC_DEVLPMCSR_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_RESERVED_18_SHIFT)) & USBC_DEVLPMCSR_RESERVED_18_MASK)
+#define USBC_DEVLPMCSR_HIRD_MASK (0xF00000U)
+#define USBC_DEVLPMCSR_HIRD_SHIFT (20U)
+#define USBC_DEVLPMCSR_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_HIRD_SHIFT)) & USBC_DEVLPMCSR_HIRD_MASK)
+#define USBC_DEVLPMCSR_LINKSTATE_MASK (0xF000000U)
+#define USBC_DEVLPMCSR_LINKSTATE_SHIFT (24U)
+#define USBC_DEVLPMCSR_LINKSTATE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LINKSTATE_SHIFT)) & USBC_DEVLPMCSR_LINKSTATE_MASK)
+#define USBC_DEVLPMCSR_BRMTWAKE_MASK (0x10000000U)
+#define USBC_DEVLPMCSR_BRMTWAKE_SHIFT (28U)
+#define USBC_DEVLPMCSR_BRMTWAKE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_BRMTWAKE_SHIFT)) & USBC_DEVLPMCSR_BRMTWAKE_MASK)
+#define USBC_DEVLPMCSR_LPM_PHCD_ONLY_MASK (0x20000000U)
+#define USBC_DEVLPMCSR_LPM_PHCD_ONLY_SHIFT (29U)
+#define USBC_DEVLPMCSR_LPM_PHCD_ONLY(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LPM_PHCD_ONLY_SHIFT)) & USBC_DEVLPMCSR_LPM_PHCD_ONLY_MASK)
+#define USBC_DEVLPMCSR_LPM_RSP_MASK (0xC0000000U)
+#define USBC_DEVLPMCSR_LPM_RSP_SHIFT (30U)
+#define USBC_DEVLPMCSR_LPM_RSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_DEVLPMCSR_LPM_RSP_SHIFT)) & USBC_DEVLPMCSR_LPM_RSP_MASK)
+/*! @} */
+
+/*! @name USBCMD - */
+/*! @{ */
+#define USBC_USBCMD_RS_MASK (0x1U)
+#define USBC_USBCMD_RS_SHIFT (0U)
+#define USBC_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_RS_SHIFT)) & USBC_USBCMD_RS_MASK)
+#define USBC_USBCMD_RST_MASK (0x2U)
+#define USBC_USBCMD_RST_SHIFT (1U)
+#define USBC_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_RST_SHIFT)) & USBC_USBCMD_RST_MASK)
+#define USBC_USBCMD_FS0_MASK (0x4U)
+#define USBC_USBCMD_FS0_SHIFT (2U)
+/*! FS0 - HOST only
+ */
+#define USBC_USBCMD_FS0(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_FS0_SHIFT)) & USBC_USBCMD_FS0_MASK)
+#define USBC_USBCMD_FS1_MASK (0x8U)
+#define USBC_USBCMD_FS1_SHIFT (3U)
+/*! FS1 - HOST only
+ */
+#define USBC_USBCMD_FS1(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_FS1_SHIFT)) & USBC_USBCMD_FS1_MASK)
+#define USBC_USBCMD_PSE_MASK (0x10U)
+#define USBC_USBCMD_PSE_SHIFT (4U)
+/*! PSE - HOST only
+ */
+#define USBC_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_PSE_SHIFT)) & USBC_USBCMD_PSE_MASK)
+#define USBC_USBCMD_ASE_MASK (0x20U)
+#define USBC_USBCMD_ASE_SHIFT (5U)
+/*! ASE - HOST only
+ */
+#define USBC_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ASE_SHIFT)) & USBC_USBCMD_ASE_MASK)
+#define USBC_USBCMD_IAA_MASK (0x40U)
+#define USBC_USBCMD_IAA_SHIFT (6U)
+/*! IAA - HOST only
+ */
+#define USBC_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_IAA_SHIFT)) & USBC_USBCMD_IAA_MASK)
+#define USBC_USBCMD_LR_MASK (0x80U)
+#define USBC_USBCMD_LR_SHIFT (7U)
+#define USBC_USBCMD_LR(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_LR_SHIFT)) & USBC_USBCMD_LR_MASK)
+#define USBC_USBCMD_ASP0_MASK (0x100U)
+#define USBC_USBCMD_ASP0_SHIFT (8U)
+/*! ASP0 - HOST only
+ */
+#define USBC_USBCMD_ASP0(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ASP0_SHIFT)) & USBC_USBCMD_ASP0_MASK)
+#define USBC_USBCMD_ASP1_MASK (0x200U)
+#define USBC_USBCMD_ASP1_SHIFT (9U)
+/*! ASP1 - HOST only
+ */
+#define USBC_USBCMD_ASP1(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ASP1_SHIFT)) & USBC_USBCMD_ASP1_MASK)
+#define USBC_USBCMD_RESERVED_10_MASK (0x400U)
+#define USBC_USBCMD_RESERVED_10_SHIFT (10U)
+#define USBC_USBCMD_RESERVED_10(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_RESERVED_10_SHIFT)) & USBC_USBCMD_RESERVED_10_MASK)
+#define USBC_USBCMD_ASPE_MASK (0x800U)
+#define USBC_USBCMD_ASPE_SHIFT (11U)
+/*! ASPE - HOST only
+ */
+#define USBC_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ASPE_SHIFT)) & USBC_USBCMD_ASPE_MASK)
+#define USBC_USBCMD_RESERVED_12_MASK (0x1000U)
+#define USBC_USBCMD_RESERVED_12_SHIFT (12U)
+#define USBC_USBCMD_RESERVED_12(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_RESERVED_12_SHIFT)) & USBC_USBCMD_RESERVED_12_MASK)
+#define USBC_USBCMD_SUTW_MASK (0x2000U)
+#define USBC_USBCMD_SUTW_SHIFT (13U)
+#define USBC_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_SUTW_SHIFT)) & USBC_USBCMD_SUTW_MASK)
+#define USBC_USBCMD_ATDTW_MASK (0x4000U)
+#define USBC_USBCMD_ATDTW_SHIFT (14U)
+#define USBC_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ATDTW_SHIFT)) & USBC_USBCMD_ATDTW_MASK)
+#define USBC_USBCMD_FS2_MASK (0x8000U)
+#define USBC_USBCMD_FS2_SHIFT (15U)
+/*! FS2 - HOST only
+ */
+#define USBC_USBCMD_FS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_FS2_SHIFT)) & USBC_USBCMD_FS2_MASK)
+#define USBC_USBCMD_ITC_MASK (0xFF0000U)
+#define USBC_USBCMD_ITC_SHIFT (16U)
+#define USBC_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_ITC_SHIFT)) & USBC_USBCMD_ITC_MASK)
+#define USBC_USBCMD_RESERVED_24_MASK (0xFF000000U)
+#define USBC_USBCMD_RESERVED_24_SHIFT (24U)
+#define USBC_USBCMD_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBCMD_RESERVED_24_SHIFT)) & USBC_USBCMD_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name USBSTS - */
+/*! @{ */
+#define USBC_USBSTS_UI_MASK (0x1U)
+#define USBC_USBSTS_UI_SHIFT (0U)
+/*! UI - rwc
+ */
+#define USBC_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UI_SHIFT)) & USBC_USBSTS_UI_MASK)
+#define USBC_USBSTS_UEI_MASK (0x2U)
+#define USBC_USBSTS_UEI_SHIFT (1U)
+/*! UEI - rwc
+ */
+#define USBC_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UEI_SHIFT)) & USBC_USBSTS_UEI_MASK)
+#define USBC_USBSTS_PCI_MASK (0x4U)
+#define USBC_USBSTS_PCI_SHIFT (2U)
+/*! PCI - rwc
+ */
+#define USBC_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_PCI_SHIFT)) & USBC_USBSTS_PCI_MASK)
+#define USBC_USBSTS_FRI_MASK (0x8U)
+#define USBC_USBSTS_FRI_SHIFT (3U)
+/*! FRI - rwc
+ */
+#define USBC_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_FRI_SHIFT)) & USBC_USBSTS_FRI_MASK)
+#define USBC_USBSTS_SEI_MASK (0x10U)
+#define USBC_USBSTS_SEI_SHIFT (4U)
+/*! SEI - rwc
+ */
+#define USBC_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_SEI_SHIFT)) & USBC_USBSTS_SEI_MASK)
+#define USBC_USBSTS_AAI_MASK (0x20U)
+#define USBC_USBSTS_AAI_SHIFT (5U)
+/*! AAI - rwc
+ */
+#define USBC_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_AAI_SHIFT)) & USBC_USBSTS_AAI_MASK)
+#define USBC_USBSTS_URI_MASK (0x40U)
+#define USBC_USBSTS_URI_SHIFT (6U)
+/*! URI - rwc
+ */
+#define USBC_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_URI_SHIFT)) & USBC_USBSTS_URI_MASK)
+#define USBC_USBSTS_SRI_MASK (0x80U)
+#define USBC_USBSTS_SRI_SHIFT (7U)
+/*! SRI - rwc
+ */
+#define USBC_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_SRI_SHIFT)) & USBC_USBSTS_SRI_MASK)
+#define USBC_USBSTS_SLI_MASK (0x100U)
+#define USBC_USBSTS_SLI_SHIFT (8U)
+/*! SLI - rwc
+ */
+#define USBC_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_SLI_SHIFT)) & USBC_USBSTS_SLI_MASK)
+#define USBC_USBSTS_RESERVED_9_MASK (0x200U)
+#define USBC_USBSTS_RESERVED_9_SHIFT (9U)
+#define USBC_USBSTS_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_RESERVED_9_SHIFT)) & USBC_USBSTS_RESERVED_9_MASK)
+#define USBC_USBSTS_ULPII_MASK (0x400U)
+#define USBC_USBSTS_ULPII_SHIFT (10U)
+/*! ULPII - rwc
+ */
+#define USBC_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_ULPII_SHIFT)) & USBC_USBSTS_ULPII_MASK)
+#define USBC_USBSTS_RESERVED_11_MASK (0x800U)
+#define USBC_USBSTS_RESERVED_11_SHIFT (11U)
+#define USBC_USBSTS_RESERVED_11(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_RESERVED_11_SHIFT)) & USBC_USBSTS_RESERVED_11_MASK)
+#define USBC_USBSTS_HCH_MASK (0x1000U)
+#define USBC_USBSTS_HCH_SHIFT (12U)
+/*! HCH - HOST only
+ */
+#define USBC_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_HCH_SHIFT)) & USBC_USBSTS_HCH_MASK)
+#define USBC_USBSTS_RCL_MASK (0x2000U)
+#define USBC_USBSTS_RCL_SHIFT (13U)
+#define USBC_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_RCL_SHIFT)) & USBC_USBSTS_RCL_MASK)
+#define USBC_USBSTS_PS_MASK (0x4000U)
+#define USBC_USBSTS_PS_SHIFT (14U)
+#define USBC_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_PS_SHIFT)) & USBC_USBSTS_PS_MASK)
+#define USBC_USBSTS_AS_MASK (0x8000U)
+#define USBC_USBSTS_AS_SHIFT (15U)
+#define USBC_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_AS_SHIFT)) & USBC_USBSTS_AS_MASK)
+#define USBC_USBSTS_NAKI_MASK (0x10000U)
+#define USBC_USBSTS_NAKI_SHIFT (16U)
+#define USBC_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_NAKI_SHIFT)) & USBC_USBSTS_NAKI_MASK)
+#define USBC_USBSTS_RESERVED_17_MASK (0x20000U)
+#define USBC_USBSTS_RESERVED_17_SHIFT (17U)
+#define USBC_USBSTS_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_RESERVED_17_SHIFT)) & USBC_USBSTS_RESERVED_17_MASK)
+#define USBC_USBSTS_UAI_MASK (0x40000U)
+#define USBC_USBSTS_UAI_SHIFT (18U)
+/*! UAI - rwc
+ */
+#define USBC_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UAI_SHIFT)) & USBC_USBSTS_UAI_MASK)
+#define USBC_USBSTS_UPI_MASK (0x80000U)
+#define USBC_USBSTS_UPI_SHIFT (19U)
+/*! UPI - rwc
+ */
+#define USBC_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_UPI_SHIFT)) & USBC_USBSTS_UPI_MASK)
+#define USBC_USBSTS_RESERVED_20_MASK (0xF00000U)
+#define USBC_USBSTS_RESERVED_20_SHIFT (20U)
+#define USBC_USBSTS_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_RESERVED_20_SHIFT)) & USBC_USBSTS_RESERVED_20_MASK)
+#define USBC_USBSTS_TI0_MASK (0x1000000U)
+#define USBC_USBSTS_TI0_SHIFT (24U)
+/*! TI0 - rwc
+ */
+#define USBC_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_TI0_SHIFT)) & USBC_USBSTS_TI0_MASK)
+#define USBC_USBSTS_TI1_MASK (0x2000000U)
+#define USBC_USBSTS_TI1_SHIFT (25U)
+/*! TI1 - rwc
+ */
+#define USBC_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_TI1_SHIFT)) & USBC_USBSTS_TI1_MASK)
+#define USBC_USBSTS_RESERVED_26_MASK (0xFC000000U)
+#define USBC_USBSTS_RESERVED_26_SHIFT (26U)
+#define USBC_USBSTS_RESERVED_26(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBSTS_RESERVED_26_SHIFT)) & USBC_USBSTS_RESERVED_26_MASK)
+/*! @} */
+
+/*! @name USBINTR - */
+/*! @{ */
+#define USBC_USBINTR_UE_MASK (0x1U)
+#define USBC_USBINTR_UE_SHIFT (0U)
+#define USBC_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UE_SHIFT)) & USBC_USBINTR_UE_MASK)
+#define USBC_USBINTR_UEE_MASK (0x2U)
+#define USBC_USBINTR_UEE_SHIFT (1U)
+/*! UEE - rwc
+ */
+#define USBC_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UEE_SHIFT)) & USBC_USBINTR_UEE_MASK)
+#define USBC_USBINTR_PCE_MASK (0x4U)
+#define USBC_USBINTR_PCE_SHIFT (2U)
+#define USBC_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_PCE_SHIFT)) & USBC_USBINTR_PCE_MASK)
+#define USBC_USBINTR_FRE_MASK (0x8U)
+#define USBC_USBINTR_FRE_SHIFT (3U)
+/*! FRE - HOST only
+ */
+#define USBC_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_FRE_SHIFT)) & USBC_USBINTR_FRE_MASK)
+#define USBC_USBINTR_SEE_MASK (0x10U)
+#define USBC_USBINTR_SEE_SHIFT (4U)
+#define USBC_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_SEE_SHIFT)) & USBC_USBINTR_SEE_MASK)
+#define USBC_USBINTR_AAE_MASK (0x20U)
+#define USBC_USBINTR_AAE_SHIFT (5U)
+/*! AAE - HOST only
+ */
+#define USBC_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_AAE_SHIFT)) & USBC_USBINTR_AAE_MASK)
+#define USBC_USBINTR_URE_MASK (0x40U)
+#define USBC_USBINTR_URE_SHIFT (6U)
+#define USBC_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_URE_SHIFT)) & USBC_USBINTR_URE_MASK)
+#define USBC_USBINTR_SRE_MASK (0x80U)
+#define USBC_USBINTR_SRE_SHIFT (7U)
+#define USBC_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_SRE_SHIFT)) & USBC_USBINTR_SRE_MASK)
+#define USBC_USBINTR_SLE_MASK (0x100U)
+#define USBC_USBINTR_SLE_SHIFT (8U)
+#define USBC_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_SLE_SHIFT)) & USBC_USBINTR_SLE_MASK)
+#define USBC_USBINTR_RESERVED_9_MASK (0x200U)
+#define USBC_USBINTR_RESERVED_9_SHIFT (9U)
+#define USBC_USBINTR_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_9_SHIFT)) & USBC_USBINTR_RESERVED_9_MASK)
+#define USBC_USBINTR_ULPE_MASK (0x400U)
+#define USBC_USBINTR_ULPE_SHIFT (10U)
+/*! ULPE - ONLY used VUSB_HS_PHY_ULPI =1
+ */
+#define USBC_USBINTR_ULPE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_ULPE_SHIFT)) & USBC_USBINTR_ULPE_MASK)
+#define USBC_USBINTR_RESERVED_11_MASK (0x800U)
+#define USBC_USBINTR_RESERVED_11_SHIFT (11U)
+#define USBC_USBINTR_RESERVED_11(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_11_SHIFT)) & USBC_USBINTR_RESERVED_11_MASK)
+#define USBC_USBINTR_RESERVED_12_MASK (0x1000U)
+#define USBC_USBINTR_RESERVED_12_SHIFT (12U)
+#define USBC_USBINTR_RESERVED_12(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_12_SHIFT)) & USBC_USBINTR_RESERVED_12_MASK)
+#define USBC_USBINTR_RESERVED_13_MASK (0x2000U)
+#define USBC_USBINTR_RESERVED_13_SHIFT (13U)
+/*! Reserved_13 - Not define in DUT,RCL
+ */
+#define USBC_USBINTR_RESERVED_13(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_13_SHIFT)) & USBC_USBINTR_RESERVED_13_MASK)
+#define USBC_USBINTR_RESERVED_14_MASK (0x4000U)
+#define USBC_USBINTR_RESERVED_14_SHIFT (14U)
+/*! Reserved_14 - Not define in DUT, PS
+ */
+#define USBC_USBINTR_RESERVED_14(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_14_SHIFT)) & USBC_USBINTR_RESERVED_14_MASK)
+#define USBC_USBINTR_RESERVED_15_MASK (0x8000U)
+#define USBC_USBINTR_RESERVED_15_SHIFT (15U)
+/*! Reserved_15 - Not define in DUT, AS
+ */
+#define USBC_USBINTR_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_15_SHIFT)) & USBC_USBINTR_RESERVED_15_MASK)
+#define USBC_USBINTR_NAKE_MASK (0x10000U)
+#define USBC_USBINTR_NAKE_SHIFT (16U)
+#define USBC_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_NAKE_SHIFT)) & USBC_USBINTR_NAKE_MASK)
+#define USBC_USBINTR_RESERVED_17_MASK (0x20000U)
+#define USBC_USBINTR_RESERVED_17_SHIFT (17U)
+#define USBC_USBINTR_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_17_SHIFT)) & USBC_USBINTR_RESERVED_17_MASK)
+#define USBC_USBINTR_UAE_MASK (0x40000U)
+#define USBC_USBINTR_UAE_SHIFT (18U)
+/*! UAE - Not use in Device mode
+ */
+#define USBC_USBINTR_UAE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UAE_SHIFT)) & USBC_USBINTR_UAE_MASK)
+#define USBC_USBINTR_UPE_MASK (0x80000U)
+#define USBC_USBINTR_UPE_SHIFT (19U)
+/*! UPE - Not use in Device mode
+ */
+#define USBC_USBINTR_UPE(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_UPE_SHIFT)) & USBC_USBINTR_UPE_MASK)
+#define USBC_USBINTR_RESERVED_20_MASK (0xF00000U)
+#define USBC_USBINTR_RESERVED_20_SHIFT (20U)
+#define USBC_USBINTR_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_20_SHIFT)) & USBC_USBINTR_RESERVED_20_MASK)
+#define USBC_USBINTR_TIE0_MASK (0x1000000U)
+#define USBC_USBINTR_TIE0_SHIFT (24U)
+#define USBC_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_TIE0_SHIFT)) & USBC_USBINTR_TIE0_MASK)
+#define USBC_USBINTR_TIE1_MASK (0x2000000U)
+#define USBC_USBINTR_TIE1_SHIFT (25U)
+#define USBC_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_TIE1_SHIFT)) & USBC_USBINTR_TIE1_MASK)
+#define USBC_USBINTR_RESERVED_26_MASK (0xFC000000U)
+#define USBC_USBINTR_RESERVED_26_SHIFT (26U)
+#define USBC_USBINTR_RESERVED_26(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBINTR_RESERVED_26_SHIFT)) & USBC_USBINTR_RESERVED_26_MASK)
+/*! @} */
+
+/*! @name FRINDEX - */
+/*! @{ */
+#define USBC_FRINDEX_FRINDEX_MASK (0x3FFFU)
+#define USBC_FRINDEX_FRINDEX_SHIFT (0U)
+/*! FRINDEX - device RO, Host RW
+ */
+#define USBC_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBC_FRINDEX_FRINDEX_SHIFT)) & USBC_FRINDEX_FRINDEX_MASK)
+#define USBC_FRINDEX_RESERVED_14_MASK (0xFFFFC000U)
+#define USBC_FRINDEX_RESERVED_14_SHIFT (14U)
+#define USBC_FRINDEX_RESERVED_14(x) (((uint32_t)(((uint32_t)(x)) << USBC_FRINDEX_RESERVED_14_SHIFT)) & USBC_FRINDEX_RESERVED_14_MASK)
+/*! @} */
+
+/*! @name PERIODICLISTBASE - */
+/*! @{ */
+#define USBC_PERIODICLISTBASE_RESERVED_0_MASK (0xFFFFFFU)
+#define USBC_PERIODICLISTBASE_RESERVED_0_SHIFT (0U)
+#define USBC_PERIODICLISTBASE_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_PERIODICLISTBASE_RESERVED_0_SHIFT)) & USBC_PERIODICLISTBASE_RESERVED_0_MASK)
+#define USBC_PERIODICLISTBASE_USBADRA_MASK (0x1000000U)
+#define USBC_PERIODICLISTBASE_USBADRA_SHIFT (24U)
+#define USBC_PERIODICLISTBASE_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PERIODICLISTBASE_USBADRA_SHIFT)) & USBC_PERIODICLISTBASE_USBADRA_MASK)
+#define USBC_PERIODICLISTBASE_USBADR_MASK (0xFE000000U)
+#define USBC_PERIODICLISTBASE_USBADR_SHIFT (25U)
+#define USBC_PERIODICLISTBASE_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PERIODICLISTBASE_USBADR_SHIFT)) & USBC_PERIODICLISTBASE_USBADR_MASK)
+/*! @} */
+
+/*! @name ASYNCLISTADDR - */
+/*! @{ */
+#define USBC_ASYNCLISTADDR_RESERVED_0_MASK (0x7FFU)
+#define USBC_ASYNCLISTADDR_RESERVED_0_SHIFT (0U)
+#define USBC_ASYNCLISTADDR_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_ASYNCLISTADDR_RESERVED_0_SHIFT)) & USBC_ASYNCLISTADDR_RESERVED_0_MASK)
+#define USBC_ASYNCLISTADDR_EPBASE_MASK (0xFFFFF800U)
+#define USBC_ASYNCLISTADDR_EPBASE_SHIFT (11U)
+#define USBC_ASYNCLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ASYNCLISTADDR_EPBASE_SHIFT)) & USBC_ASYNCLISTADDR_EPBASE_MASK)
+/*! @} */
+
+/*! @name TTCTRL - */
+/*! @{ */
+#define USBC_TTCTRL_TTAS_MASK (0x1U)
+#define USBC_TTCTRL_TTAS_SHIFT (0U)
+#define USBC_TTCTRL_TTAS(x) (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_TTAS_SHIFT)) & USBC_TTCTRL_TTAS_MASK)
+#define USBC_TTCTRL_TTAC_MASK (0x2U)
+#define USBC_TTCTRL_TTAC_SHIFT (1U)
+#define USBC_TTCTRL_TTAC(x) (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_TTAC_SHIFT)) & USBC_TTCTRL_TTAC_MASK)
+#define USBC_TTCTRL_RESERVED_2_MASK (0xFFFFFCU)
+#define USBC_TTCTRL_RESERVED_2_SHIFT (2U)
+#define USBC_TTCTRL_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_RESERVED_2_SHIFT)) & USBC_TTCTRL_RESERVED_2_MASK)
+#define USBC_TTCTRL_TTHA_MASK (0x7F000000U)
+#define USBC_TTCTRL_TTHA_SHIFT (24U)
+#define USBC_TTCTRL_TTHA(x) (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_TTHA_SHIFT)) & USBC_TTCTRL_TTHA_MASK)
+#define USBC_TTCTRL_RESERVED_31_MASK (0x80000000U)
+#define USBC_TTCTRL_RESERVED_31_SHIFT (31U)
+#define USBC_TTCTRL_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << USBC_TTCTRL_RESERVED_31_SHIFT)) & USBC_TTCTRL_RESERVED_31_MASK)
+/*! @} */
+
+/*! @name BURSTSIZE - */
+/*! @{ */
+#define USBC_BURSTSIZE_RXPBURST_MASK (0xFFU)
+#define USBC_BURSTSIZE_RXPBURST_SHIFT (0U)
+#define USBC_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBC_BURSTSIZE_RXPBURST_SHIFT)) & USBC_BURSTSIZE_RXPBURST_MASK)
+#define USBC_BURSTSIZE_TXPBURST_MASK (0xFF00U)
+#define USBC_BURSTSIZE_TXPBURST_SHIFT (8U)
+#define USBC_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBC_BURSTSIZE_TXPBURST_SHIFT)) & USBC_BURSTSIZE_TXPBURST_MASK)
+#define USBC_BURSTSIZE_RESERVED_16_MASK (0xFFFF0000U)
+#define USBC_BURSTSIZE_RESERVED_16_SHIFT (16U)
+#define USBC_BURSTSIZE_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << USBC_BURSTSIZE_RESERVED_16_SHIFT)) & USBC_BURSTSIZE_RESERVED_16_MASK)
+/*! @} */
+
+/*! @name TXFILLTUNING - */
+/*! @{ */
+#define USBC_TXFILLTUNING_TXSCHOH_MASK (0x7FU)
+#define USBC_TXFILLTUNING_TXSCHOH_SHIFT (0U)
+/*! TXSCHOH - Only use in HOST & MPH mode
+ */
+#define USBC_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_TXSCHOH_SHIFT)) & USBC_TXFILLTUNING_TXSCHOH_MASK)
+#define USBC_TXFILLTUNING_RESERVED_7_MASK (0x80U)
+#define USBC_TXFILLTUNING_RESERVED_7_SHIFT (7U)
+#define USBC_TXFILLTUNING_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_RESERVED_7_SHIFT)) & USBC_TXFILLTUNING_RESERVED_7_MASK)
+#define USBC_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
+#define USBC_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
+/*! TXSCHHEALTH - Only use in HOST & MPH mode, rwc
+ */
+#define USBC_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBC_TXFILLTUNING_TXSCHHEALTH_MASK)
+#define USBC_TXFILLTUNING_RESERVED_13_MASK (0xE000U)
+#define USBC_TXFILLTUNING_RESERVED_13_SHIFT (13U)
+#define USBC_TXFILLTUNING_RESERVED_13(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_RESERVED_13_SHIFT)) & USBC_TXFILLTUNING_RESERVED_13_MASK)
+#define USBC_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
+#define USBC_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
+/*! TXFIFOTHRES - Only use in HOST & MPH mode
+ */
+#define USBC_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBC_TXFILLTUNING_TXFIFOTHRES_MASK)
+#define USBC_TXFILLTUNING_RESERVED_22_MASK (0xFFC00000U)
+#define USBC_TXFILLTUNING_RESERVED_22_SHIFT (22U)
+#define USBC_TXFILLTUNING_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXFILLTUNING_RESERVED_22_SHIFT)) & USBC_TXFILLTUNING_RESERVED_22_MASK)
+/*! @} */
+
+/*! @name TXTTFILLTUNING - */
+/*! @{ */
+#define USBC_TXTTFILLTUNING_TXTTSCHOH_MASK (0x1FU)
+#define USBC_TXTTFILLTUNING_TXTTSCHOH_SHIFT (0U)
+/*! TXTTSCHOH - Only use in HOST & MPH mode
+ */
+#define USBC_TXTTFILLTUNING_TXTTSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXTTFILLTUNING_TXTTSCHOH_SHIFT)) & USBC_TXTTFILLTUNING_TXTTSCHOH_MASK)
+#define USBC_TXTTFILLTUNING_RESERVED_5_MASK (0xE0U)
+#define USBC_TXTTFILLTUNING_RESERVED_5_SHIFT (5U)
+#define USBC_TXTTFILLTUNING_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXTTFILLTUNING_RESERVED_5_SHIFT)) & USBC_TXTTFILLTUNING_RESERVED_5_MASK)
+#define USBC_TXTTFILLTUNING_TXTTSCHHEALTJ_MASK (0x1F00U)
+#define USBC_TXTTFILLTUNING_TXTTSCHHEALTJ_SHIFT (8U)
+/*! TXTTSCHHEALTJ - Only use in HOST & MPH mode, rwc
+ */
+#define USBC_TXTTFILLTUNING_TXTTSCHHEALTJ(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXTTFILLTUNING_TXTTSCHHEALTJ_SHIFT)) & USBC_TXTTFILLTUNING_TXTTSCHHEALTJ_MASK)
+#define USBC_TXTTFILLTUNING_RESERVED_13_MASK (0xFFFFE000U)
+#define USBC_TXTTFILLTUNING_RESERVED_13_SHIFT (13U)
+#define USBC_TXTTFILLTUNING_RESERVED_13(x) (((uint32_t)(((uint32_t)(x)) << USBC_TXTTFILLTUNING_RESERVED_13_SHIFT)) & USBC_TXTTFILLTUNING_RESERVED_13_MASK)
+/*! @} */
+
+/*! @name IC_USB - */
+/*! @{ */
+#define USBC_IC_USB_IC_VDD1_MASK (0x7U)
+#define USBC_IC_USB_IC_VDD1_SHIFT (0U)
+/*! IC_VDD1 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC_VDD1(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD1_SHIFT)) & USBC_IC_USB_IC_VDD1_MASK)
+#define USBC_IC_USB_IC1_MASK (0x8U)
+#define USBC_IC_USB_IC1_SHIFT (3U)
+/*! IC1 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC1(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC1_SHIFT)) & USBC_IC_USB_IC1_MASK)
+#define USBC_IC_USB_IC_VDD2_MASK (0x70U)
+#define USBC_IC_USB_IC_VDD2_SHIFT (4U)
+/*! IC_VDD2 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC_VDD2(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD2_SHIFT)) & USBC_IC_USB_IC_VDD2_MASK)
+#define USBC_IC_USB_IC2_MASK (0x80U)
+#define USBC_IC_USB_IC2_SHIFT (7U)
+/*! IC2 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC2(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC2_SHIFT)) & USBC_IC_USB_IC2_MASK)
+#define USBC_IC_USB_IC_VDD3_MASK (0x700U)
+#define USBC_IC_USB_IC_VDD3_SHIFT (8U)
+/*! IC_VDD3 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC_VDD3(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD3_SHIFT)) & USBC_IC_USB_IC_VDD3_MASK)
+#define USBC_IC_USB_IC3_MASK (0x800U)
+#define USBC_IC_USB_IC3_SHIFT (11U)
+/*! IC3 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC3(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC3_SHIFT)) & USBC_IC_USB_IC3_MASK)
+#define USBC_IC_USB_IC_VDD4_MASK (0x7000U)
+#define USBC_IC_USB_IC_VDD4_SHIFT (12U)
+/*! IC_VDD4 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC_VDD4(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD4_SHIFT)) & USBC_IC_USB_IC_VDD4_MASK)
+#define USBC_IC_USB_IC4_MASK (0x8000U)
+#define USBC_IC_USB_IC4_SHIFT (15U)
+/*! IC4 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC4(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC4_SHIFT)) & USBC_IC_USB_IC4_MASK)
+#define USBC_IC_USB_IC_VDD5_MASK (0x70000U)
+#define USBC_IC_USB_IC_VDD5_SHIFT (16U)
+/*! IC_VDD5 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC_VDD5(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD5_SHIFT)) & USBC_IC_USB_IC_VDD5_MASK)
+#define USBC_IC_USB_IC5_MASK (0x80000U)
+#define USBC_IC_USB_IC5_SHIFT (19U)
+/*! IC5 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC5(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC5_SHIFT)) & USBC_IC_USB_IC5_MASK)
+#define USBC_IC_USB_IC_VDD6_MASK (0x700000U)
+#define USBC_IC_USB_IC_VDD6_SHIFT (20U)
+/*! IC_VDD6 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC_VDD6(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD6_SHIFT)) & USBC_IC_USB_IC_VDD6_MASK)
+#define USBC_IC_USB_IC6_MASK (0x800000U)
+#define USBC_IC_USB_IC6_SHIFT (23U)
+/*! IC6 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC6(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC6_SHIFT)) & USBC_IC_USB_IC6_MASK)
+#define USBC_IC_USB_IC_VDD7_MASK (0x7000000U)
+#define USBC_IC_USB_IC_VDD7_SHIFT (24U)
+/*! IC_VDD7 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC_VDD7(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD7_SHIFT)) & USBC_IC_USB_IC_VDD7_MASK)
+#define USBC_IC_USB_IC7_MASK (0x8000000U)
+#define USBC_IC_USB_IC7_SHIFT (27U)
+/*! IC7 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC7(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC7_SHIFT)) & USBC_IC_USB_IC7_MASK)
+#define USBC_IC_USB_IC_VDD8_MASK (0x70000000U)
+#define USBC_IC_USB_IC_VDD8_SHIFT (28U)
+/*! IC_VDD8 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC_VDD8(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC_VDD8_SHIFT)) & USBC_IC_USB_IC_VDD8_MASK)
+#define USBC_IC_USB_IC8_MASK (0x80000000U)
+#define USBC_IC_USB_IC8_SHIFT (31U)
+/*! IC8 - available in MPH & VUSB_HS_PHY_IC_USB =1
+ */
+#define USBC_IC_USB_IC8(x) (((uint32_t)(((uint32_t)(x)) << USBC_IC_USB_IC8_SHIFT)) & USBC_IC_USB_IC8_MASK)
+/*! @} */
+
+/*! @name ULPI_VIEWPORT - */
+/*! @{ */
+#define USBC_ULPI_VIEWPORT_ULPIDATWR_MASK (0xFFU)
+#define USBC_ULPI_VIEWPORT_ULPIDATWR_SHIFT (0U)
+/*! ULPIDATWR - Not available
+ */
+#define USBC_ULPI_VIEWPORT_ULPIDATWR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIDATWR_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIDATWR_MASK)
+#define USBC_ULPI_VIEWPORT_ULPIDATRD_MASK (0xFF00U)
+#define USBC_ULPI_VIEWPORT_ULPIDATRD_SHIFT (8U)
+/*! ULPIDATRD - Not available
+ */
+#define USBC_ULPI_VIEWPORT_ULPIDATRD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIDATRD_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIDATRD_MASK)
+#define USBC_ULPI_VIEWPORT_ULPIADDR_MASK (0xFF0000U)
+#define USBC_ULPI_VIEWPORT_ULPIADDR_SHIFT (16U)
+/*! ULPIADDR - Not available
+ */
+#define USBC_ULPI_VIEWPORT_ULPIADDR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIADDR_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIADDR_MASK)
+#define USBC_ULPI_VIEWPORT_ULPIPORT_MASK (0x7000000U)
+#define USBC_ULPI_VIEWPORT_ULPIPORT_SHIFT (24U)
+/*! ULPIPORT - Not available
+ */
+#define USBC_ULPI_VIEWPORT_ULPIPORT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIPORT_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIPORT_MASK)
+#define USBC_ULPI_VIEWPORT_ULPISS_MASK (0x8000000U)
+#define USBC_ULPI_VIEWPORT_ULPISS_SHIFT (27U)
+/*! ULPISS - Not available
+ */
+#define USBC_ULPI_VIEWPORT_ULPISS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPISS_SHIFT)) & USBC_ULPI_VIEWPORT_ULPISS_MASK)
+#define USBC_ULPI_VIEWPORT_RESERVED_28_MASK (0x10000000U)
+#define USBC_ULPI_VIEWPORT_RESERVED_28_SHIFT (28U)
+/*! Reserved_28 - Not available
+ */
+#define USBC_ULPI_VIEWPORT_RESERVED_28(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_RESERVED_28_SHIFT)) & USBC_ULPI_VIEWPORT_RESERVED_28_MASK)
+#define USBC_ULPI_VIEWPORT_ULPIRW_MASK (0x20000000U)
+#define USBC_ULPI_VIEWPORT_ULPIRW_SHIFT (29U)
+/*! ULPIRW - Not available
+ */
+#define USBC_ULPI_VIEWPORT_ULPIRW(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIRW_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIRW_MASK)
+#define USBC_ULPI_VIEWPORT_ULPIRUN_MASK (0x40000000U)
+#define USBC_ULPI_VIEWPORT_ULPIRUN_SHIFT (30U)
+/*! ULPIRUN - Not available
+ */
+#define USBC_ULPI_VIEWPORT_ULPIRUN(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIRUN_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIRUN_MASK)
+#define USBC_ULPI_VIEWPORT_ULPIWU_MASK (0x80000000U)
+#define USBC_ULPI_VIEWPORT_ULPIWU_SHIFT (31U)
+/*! ULPIWU - Not available
+ */
+#define USBC_ULPI_VIEWPORT_ULPIWU(x) (((uint32_t)(((uint32_t)(x)) << USBC_ULPI_VIEWPORT_ULPIWU_SHIFT)) & USBC_ULPI_VIEWPORT_ULPIWU_MASK)
+/*! @} */
+
+/*! @name ENDPTNAK - */
+/*! @{ */
+#define USBC_ENDPTNAK_EPRN_MASK (0xFFFFU)
+#define USBC_ENDPTNAK_EPRN_SHIFT (0U)
+/*! EPRN - rwc
+ */
+#define USBC_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTNAK_EPRN_SHIFT)) & USBC_ENDPTNAK_EPRN_MASK)
+#define USBC_ENDPTNAK_EPTN_MASK (0xFFFF0000U)
+#define USBC_ENDPTNAK_EPTN_SHIFT (16U)
+/*! EPTN - rwc
+ */
+#define USBC_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTNAK_EPTN_SHIFT)) & USBC_ENDPTNAK_EPTN_MASK)
+/*! @} */
+
+/*! @name ENDPTNAKEN - */
+/*! @{ */
+#define USBC_ENDPTNAKEN_EPRNE_MASK (0xFFFFU)
+#define USBC_ENDPTNAKEN_EPRNE_SHIFT (0U)
+/*! EPRNE - Only 3 PHY max
+ */
+#define USBC_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTNAKEN_EPRNE_SHIFT)) & USBC_ENDPTNAKEN_EPRNE_MASK)
+#define USBC_ENDPTNAKEN_EPTNE_MASK (0xFFFF0000U)
+#define USBC_ENDPTNAKEN_EPTNE_SHIFT (16U)
+/*! EPTNE - Only 3 PHY max
+ */
+#define USBC_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTNAKEN_EPTNE_SHIFT)) & USBC_ENDPTNAKEN_EPTNE_MASK)
+/*! @} */
+
+/*! @name PORTSC1 - */
+/*! @{ */
+#define USBC_PORTSC1_CCS_MASK (0x1U)
+#define USBC_PORTSC1_CCS_SHIFT (0U)
+#define USBC_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_CCS_SHIFT)) & USBC_PORTSC1_CCS_MASK)
+#define USBC_PORTSC1_CSC_MASK (0x2U)
+#define USBC_PORTSC1_CSC_SHIFT (1U)
+/*! CSC - rwc
+ */
+#define USBC_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_CSC_SHIFT)) & USBC_PORTSC1_CSC_MASK)
+#define USBC_PORTSC1_PE_MASK (0x4U)
+#define USBC_PORTSC1_PE_SHIFT (2U)
+/*! PE - rwc
+ */
+#define USBC_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PE_SHIFT)) & USBC_PORTSC1_PE_MASK)
+#define USBC_PORTSC1_PEC_MASK (0x8U)
+#define USBC_PORTSC1_PEC_SHIFT (3U)
+/*! PEC - rwc
+ */
+#define USBC_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PEC_SHIFT)) & USBC_PORTSC1_PEC_MASK)
+#define USBC_PORTSC1_OCA_MASK (0x10U)
+#define USBC_PORTSC1_OCA_SHIFT (4U)
+#define USBC_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_OCA_SHIFT)) & USBC_PORTSC1_OCA_MASK)
+#define USBC_PORTSC1_OCC_MASK (0x20U)
+#define USBC_PORTSC1_OCC_SHIFT (5U)
+#define USBC_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_OCC_SHIFT)) & USBC_PORTSC1_OCC_MASK)
+#define USBC_PORTSC1_FPR_MASK (0x40U)
+#define USBC_PORTSC1_FPR_SHIFT (6U)
+#define USBC_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_FPR_SHIFT)) & USBC_PORTSC1_FPR_MASK)
+#define USBC_PORTSC1_SUSP_MASK (0x80U)
+#define USBC_PORTSC1_SUSP_SHIFT (7U)
+#define USBC_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_SUSP_SHIFT)) & USBC_PORTSC1_SUSP_MASK)
+#define USBC_PORTSC1_PR_MASK (0x100U)
+#define USBC_PORTSC1_PR_SHIFT (8U)
+#define USBC_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PR_SHIFT)) & USBC_PORTSC1_PR_MASK)
+#define USBC_PORTSC1_HSP_MASK (0x200U)
+#define USBC_PORTSC1_HSP_SHIFT (9U)
+#define USBC_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_HSP_SHIFT)) & USBC_PORTSC1_HSP_MASK)
+#define USBC_PORTSC1_LS_MASK (0xC00U)
+#define USBC_PORTSC1_LS_SHIFT (10U)
+#define USBC_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_LS_SHIFT)) & USBC_PORTSC1_LS_MASK)
+#define USBC_PORTSC1_PP_MASK (0x1000U)
+#define USBC_PORTSC1_PP_SHIFT (12U)
+#define USBC_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PP_SHIFT)) & USBC_PORTSC1_PP_MASK)
+#define USBC_PORTSC1_PO_MASK (0x2000U)
+#define USBC_PORTSC1_PO_SHIFT (13U)
+#define USBC_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PO_SHIFT)) & USBC_PORTSC1_PO_MASK)
+#define USBC_PORTSC1_PIC_MASK (0xC000U)
+#define USBC_PORTSC1_PIC_SHIFT (14U)
+#define USBC_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PIC_SHIFT)) & USBC_PORTSC1_PIC_MASK)
+#define USBC_PORTSC1_PTC_MASK (0xF0000U)
+#define USBC_PORTSC1_PTC_SHIFT (16U)
+#define USBC_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PTC_SHIFT)) & USBC_PORTSC1_PTC_MASK)
+#define USBC_PORTSC1_WKCN_MASK (0x100000U)
+#define USBC_PORTSC1_WKCN_SHIFT (20U)
+#define USBC_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_WKCN_SHIFT)) & USBC_PORTSC1_WKCN_MASK)
+#define USBC_PORTSC1_WKDS_MASK (0x200000U)
+#define USBC_PORTSC1_WKDS_SHIFT (21U)
+#define USBC_PORTSC1_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_WKDS_SHIFT)) & USBC_PORTSC1_WKDS_MASK)
+#define USBC_PORTSC1_WKOC_MASK (0x400000U)
+#define USBC_PORTSC1_WKOC_SHIFT (22U)
+#define USBC_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_WKOC_SHIFT)) & USBC_PORTSC1_WKOC_MASK)
+#define USBC_PORTSC1_PHCD_MASK (0x800000U)
+#define USBC_PORTSC1_PHCD_SHIFT (23U)
+#define USBC_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PHCD_SHIFT)) & USBC_PORTSC1_PHCD_MASK)
+#define USBC_PORTSC1_PFSC_MASK (0x1000000U)
+#define USBC_PORTSC1_PFSC_SHIFT (24U)
+#define USBC_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PFSC_SHIFT)) & USBC_PORTSC1_PFSC_MASK)
+#define USBC_PORTSC1_PTS2_MASK (0x2000000U)
+#define USBC_PORTSC1_PTS2_SHIFT (25U)
+#define USBC_PORTSC1_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PTS2_SHIFT)) & USBC_PORTSC1_PTS2_MASK)
+#define USBC_PORTSC1_PSPD_MASK (0xC000000U)
+#define USBC_PORTSC1_PSPD_SHIFT (26U)
+#define USBC_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PSPD_SHIFT)) & USBC_PORTSC1_PSPD_MASK)
+#define USBC_PORTSC1_PTW_MASK (0x10000000U)
+#define USBC_PORTSC1_PTW_SHIFT (28U)
+#define USBC_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PTW_SHIFT)) & USBC_PORTSC1_PTW_MASK)
+#define USBC_PORTSC1_STS_MASK (0x20000000U)
+#define USBC_PORTSC1_STS_SHIFT (29U)
+#define USBC_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_STS_SHIFT)) & USBC_PORTSC1_STS_MASK)
+#define USBC_PORTSC1_PTS_MASK (0xC0000000U)
+#define USBC_PORTSC1_PTS_SHIFT (30U)
+#define USBC_PORTSC1_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC1_PTS_SHIFT)) & USBC_PORTSC1_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC2 - */
+/*! @{ */
+#define USBC_PORTSC2_CCS_MASK (0x1U)
+#define USBC_PORTSC2_CCS_SHIFT (0U)
+#define USBC_PORTSC2_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_CCS_SHIFT)) & USBC_PORTSC2_CCS_MASK)
+#define USBC_PORTSC2_CSC_MASK (0x2U)
+#define USBC_PORTSC2_CSC_SHIFT (1U)
+/*! CSC - rwc
+ */
+#define USBC_PORTSC2_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_CSC_SHIFT)) & USBC_PORTSC2_CSC_MASK)
+#define USBC_PORTSC2_PE_MASK (0x4U)
+#define USBC_PORTSC2_PE_SHIFT (2U)
+/*! PE - rwc
+ */
+#define USBC_PORTSC2_PE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PE_SHIFT)) & USBC_PORTSC2_PE_MASK)
+#define USBC_PORTSC2_PEC_MASK (0x8U)
+#define USBC_PORTSC2_PEC_SHIFT (3U)
+/*! PEC - rwc
+ */
+#define USBC_PORTSC2_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PEC_SHIFT)) & USBC_PORTSC2_PEC_MASK)
+#define USBC_PORTSC2_OCA_MASK (0x10U)
+#define USBC_PORTSC2_OCA_SHIFT (4U)
+#define USBC_PORTSC2_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_OCA_SHIFT)) & USBC_PORTSC2_OCA_MASK)
+#define USBC_PORTSC2_OCC_MASK (0x20U)
+#define USBC_PORTSC2_OCC_SHIFT (5U)
+#define USBC_PORTSC2_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_OCC_SHIFT)) & USBC_PORTSC2_OCC_MASK)
+#define USBC_PORTSC2_FPR_MASK (0x40U)
+#define USBC_PORTSC2_FPR_SHIFT (6U)
+#define USBC_PORTSC2_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_FPR_SHIFT)) & USBC_PORTSC2_FPR_MASK)
+#define USBC_PORTSC2_SUSP_MASK (0x80U)
+#define USBC_PORTSC2_SUSP_SHIFT (7U)
+#define USBC_PORTSC2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_SUSP_SHIFT)) & USBC_PORTSC2_SUSP_MASK)
+#define USBC_PORTSC2_PR_MASK (0x100U)
+#define USBC_PORTSC2_PR_SHIFT (8U)
+#define USBC_PORTSC2_PR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PR_SHIFT)) & USBC_PORTSC2_PR_MASK)
+#define USBC_PORTSC2_HSP_MASK (0x200U)
+#define USBC_PORTSC2_HSP_SHIFT (9U)
+#define USBC_PORTSC2_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_HSP_SHIFT)) & USBC_PORTSC2_HSP_MASK)
+#define USBC_PORTSC2_LS_MASK (0xC00U)
+#define USBC_PORTSC2_LS_SHIFT (10U)
+#define USBC_PORTSC2_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_LS_SHIFT)) & USBC_PORTSC2_LS_MASK)
+#define USBC_PORTSC2_PP_MASK (0x1000U)
+#define USBC_PORTSC2_PP_SHIFT (12U)
+#define USBC_PORTSC2_PP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PP_SHIFT)) & USBC_PORTSC2_PP_MASK)
+#define USBC_PORTSC2_PO_MASK (0x2000U)
+#define USBC_PORTSC2_PO_SHIFT (13U)
+#define USBC_PORTSC2_PO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PO_SHIFT)) & USBC_PORTSC2_PO_MASK)
+#define USBC_PORTSC2_PIC_MASK (0xC000U)
+#define USBC_PORTSC2_PIC_SHIFT (14U)
+#define USBC_PORTSC2_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PIC_SHIFT)) & USBC_PORTSC2_PIC_MASK)
+#define USBC_PORTSC2_PTC_MASK (0xF0000U)
+#define USBC_PORTSC2_PTC_SHIFT (16U)
+#define USBC_PORTSC2_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PTC_SHIFT)) & USBC_PORTSC2_PTC_MASK)
+#define USBC_PORTSC2_WKCN_MASK (0x100000U)
+#define USBC_PORTSC2_WKCN_SHIFT (20U)
+#define USBC_PORTSC2_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_WKCN_SHIFT)) & USBC_PORTSC2_WKCN_MASK)
+#define USBC_PORTSC2_WKDS_MASK (0x200000U)
+#define USBC_PORTSC2_WKDS_SHIFT (21U)
+#define USBC_PORTSC2_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_WKDS_SHIFT)) & USBC_PORTSC2_WKDS_MASK)
+#define USBC_PORTSC2_WKOC_MASK (0x400000U)
+#define USBC_PORTSC2_WKOC_SHIFT (22U)
+#define USBC_PORTSC2_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_WKOC_SHIFT)) & USBC_PORTSC2_WKOC_MASK)
+#define USBC_PORTSC2_PHCD_MASK (0x800000U)
+#define USBC_PORTSC2_PHCD_SHIFT (23U)
+#define USBC_PORTSC2_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PHCD_SHIFT)) & USBC_PORTSC2_PHCD_MASK)
+#define USBC_PORTSC2_PFSC_MASK (0x1000000U)
+#define USBC_PORTSC2_PFSC_SHIFT (24U)
+#define USBC_PORTSC2_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PFSC_SHIFT)) & USBC_PORTSC2_PFSC_MASK)
+#define USBC_PORTSC2_PTS2_MASK (0x2000000U)
+#define USBC_PORTSC2_PTS2_SHIFT (25U)
+#define USBC_PORTSC2_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PTS2_SHIFT)) & USBC_PORTSC2_PTS2_MASK)
+#define USBC_PORTSC2_PSPD_MASK (0xC000000U)
+#define USBC_PORTSC2_PSPD_SHIFT (26U)
+#define USBC_PORTSC2_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PSPD_SHIFT)) & USBC_PORTSC2_PSPD_MASK)
+#define USBC_PORTSC2_PTW_MASK (0x10000000U)
+#define USBC_PORTSC2_PTW_SHIFT (28U)
+#define USBC_PORTSC2_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PTW_SHIFT)) & USBC_PORTSC2_PTW_MASK)
+#define USBC_PORTSC2_STS_MASK (0x20000000U)
+#define USBC_PORTSC2_STS_SHIFT (29U)
+#define USBC_PORTSC2_STS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_STS_SHIFT)) & USBC_PORTSC2_STS_MASK)
+#define USBC_PORTSC2_PTS_MASK (0xC0000000U)
+#define USBC_PORTSC2_PTS_SHIFT (30U)
+#define USBC_PORTSC2_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC2_PTS_SHIFT)) & USBC_PORTSC2_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC3 - */
+/*! @{ */
+#define USBC_PORTSC3_CCS_MASK (0x1U)
+#define USBC_PORTSC3_CCS_SHIFT (0U)
+#define USBC_PORTSC3_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_CCS_SHIFT)) & USBC_PORTSC3_CCS_MASK)
+#define USBC_PORTSC3_CSC_MASK (0x2U)
+#define USBC_PORTSC3_CSC_SHIFT (1U)
+/*! CSC - rwc
+ */
+#define USBC_PORTSC3_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_CSC_SHIFT)) & USBC_PORTSC3_CSC_MASK)
+#define USBC_PORTSC3_PE_MASK (0x4U)
+#define USBC_PORTSC3_PE_SHIFT (2U)
+/*! PE - rwc
+ */
+#define USBC_PORTSC3_PE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PE_SHIFT)) & USBC_PORTSC3_PE_MASK)
+#define USBC_PORTSC3_PEC_MASK (0x8U)
+#define USBC_PORTSC3_PEC_SHIFT (3U)
+/*! PEC - rwc
+ */
+#define USBC_PORTSC3_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PEC_SHIFT)) & USBC_PORTSC3_PEC_MASK)
+#define USBC_PORTSC3_OCA_MASK (0x10U)
+#define USBC_PORTSC3_OCA_SHIFT (4U)
+#define USBC_PORTSC3_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_OCA_SHIFT)) & USBC_PORTSC3_OCA_MASK)
+#define USBC_PORTSC3_OCC_MASK (0x20U)
+#define USBC_PORTSC3_OCC_SHIFT (5U)
+#define USBC_PORTSC3_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_OCC_SHIFT)) & USBC_PORTSC3_OCC_MASK)
+#define USBC_PORTSC3_FPR_MASK (0x40U)
+#define USBC_PORTSC3_FPR_SHIFT (6U)
+#define USBC_PORTSC3_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_FPR_SHIFT)) & USBC_PORTSC3_FPR_MASK)
+#define USBC_PORTSC3_SUSP_MASK (0x80U)
+#define USBC_PORTSC3_SUSP_SHIFT (7U)
+#define USBC_PORTSC3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_SUSP_SHIFT)) & USBC_PORTSC3_SUSP_MASK)
+#define USBC_PORTSC3_PR_MASK (0x100U)
+#define USBC_PORTSC3_PR_SHIFT (8U)
+#define USBC_PORTSC3_PR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PR_SHIFT)) & USBC_PORTSC3_PR_MASK)
+#define USBC_PORTSC3_HSP_MASK (0x200U)
+#define USBC_PORTSC3_HSP_SHIFT (9U)
+#define USBC_PORTSC3_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_HSP_SHIFT)) & USBC_PORTSC3_HSP_MASK)
+#define USBC_PORTSC3_LS_MASK (0xC00U)
+#define USBC_PORTSC3_LS_SHIFT (10U)
+#define USBC_PORTSC3_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_LS_SHIFT)) & USBC_PORTSC3_LS_MASK)
+#define USBC_PORTSC3_PP_MASK (0x1000U)
+#define USBC_PORTSC3_PP_SHIFT (12U)
+#define USBC_PORTSC3_PP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PP_SHIFT)) & USBC_PORTSC3_PP_MASK)
+#define USBC_PORTSC3_PO_MASK (0x2000U)
+#define USBC_PORTSC3_PO_SHIFT (13U)
+#define USBC_PORTSC3_PO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PO_SHIFT)) & USBC_PORTSC3_PO_MASK)
+#define USBC_PORTSC3_PIC_MASK (0xC000U)
+#define USBC_PORTSC3_PIC_SHIFT (14U)
+#define USBC_PORTSC3_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PIC_SHIFT)) & USBC_PORTSC3_PIC_MASK)
+#define USBC_PORTSC3_PTC_MASK (0xF0000U)
+#define USBC_PORTSC3_PTC_SHIFT (16U)
+#define USBC_PORTSC3_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PTC_SHIFT)) & USBC_PORTSC3_PTC_MASK)
+#define USBC_PORTSC3_WKCN_MASK (0x100000U)
+#define USBC_PORTSC3_WKCN_SHIFT (20U)
+#define USBC_PORTSC3_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_WKCN_SHIFT)) & USBC_PORTSC3_WKCN_MASK)
+#define USBC_PORTSC3_WKDS_MASK (0x200000U)
+#define USBC_PORTSC3_WKDS_SHIFT (21U)
+#define USBC_PORTSC3_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_WKDS_SHIFT)) & USBC_PORTSC3_WKDS_MASK)
+#define USBC_PORTSC3_WKOC_MASK (0x400000U)
+#define USBC_PORTSC3_WKOC_SHIFT (22U)
+#define USBC_PORTSC3_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_WKOC_SHIFT)) & USBC_PORTSC3_WKOC_MASK)
+#define USBC_PORTSC3_PHCD_MASK (0x800000U)
+#define USBC_PORTSC3_PHCD_SHIFT (23U)
+#define USBC_PORTSC3_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PHCD_SHIFT)) & USBC_PORTSC3_PHCD_MASK)
+#define USBC_PORTSC3_PFSC_MASK (0x1000000U)
+#define USBC_PORTSC3_PFSC_SHIFT (24U)
+#define USBC_PORTSC3_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PFSC_SHIFT)) & USBC_PORTSC3_PFSC_MASK)
+#define USBC_PORTSC3_PTS2_MASK (0x2000000U)
+#define USBC_PORTSC3_PTS2_SHIFT (25U)
+#define USBC_PORTSC3_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PTS2_SHIFT)) & USBC_PORTSC3_PTS2_MASK)
+#define USBC_PORTSC3_PSPD_MASK (0xC000000U)
+#define USBC_PORTSC3_PSPD_SHIFT (26U)
+#define USBC_PORTSC3_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PSPD_SHIFT)) & USBC_PORTSC3_PSPD_MASK)
+#define USBC_PORTSC3_PTW_MASK (0x10000000U)
+#define USBC_PORTSC3_PTW_SHIFT (28U)
+#define USBC_PORTSC3_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PTW_SHIFT)) & USBC_PORTSC3_PTW_MASK)
+#define USBC_PORTSC3_STS_MASK (0x20000000U)
+#define USBC_PORTSC3_STS_SHIFT (29U)
+#define USBC_PORTSC3_STS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_STS_SHIFT)) & USBC_PORTSC3_STS_MASK)
+#define USBC_PORTSC3_PTS_MASK (0xC0000000U)
+#define USBC_PORTSC3_PTS_SHIFT (30U)
+#define USBC_PORTSC3_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC3_PTS_SHIFT)) & USBC_PORTSC3_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC4 - */
+/*! @{ */
+#define USBC_PORTSC4_CCS_MASK (0x1U)
+#define USBC_PORTSC4_CCS_SHIFT (0U)
+#define USBC_PORTSC4_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_CCS_SHIFT)) & USBC_PORTSC4_CCS_MASK)
+#define USBC_PORTSC4_CSC_MASK (0x2U)
+#define USBC_PORTSC4_CSC_SHIFT (1U)
+/*! CSC - rwc
+ */
+#define USBC_PORTSC4_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_CSC_SHIFT)) & USBC_PORTSC4_CSC_MASK)
+#define USBC_PORTSC4_PE_MASK (0x4U)
+#define USBC_PORTSC4_PE_SHIFT (2U)
+/*! PE - rwc
+ */
+#define USBC_PORTSC4_PE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PE_SHIFT)) & USBC_PORTSC4_PE_MASK)
+#define USBC_PORTSC4_PEC_MASK (0x8U)
+#define USBC_PORTSC4_PEC_SHIFT (3U)
+/*! PEC - rwc
+ */
+#define USBC_PORTSC4_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PEC_SHIFT)) & USBC_PORTSC4_PEC_MASK)
+#define USBC_PORTSC4_OCA_MASK (0x10U)
+#define USBC_PORTSC4_OCA_SHIFT (4U)
+#define USBC_PORTSC4_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_OCA_SHIFT)) & USBC_PORTSC4_OCA_MASK)
+#define USBC_PORTSC4_OCC_MASK (0x20U)
+#define USBC_PORTSC4_OCC_SHIFT (5U)
+#define USBC_PORTSC4_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_OCC_SHIFT)) & USBC_PORTSC4_OCC_MASK)
+#define USBC_PORTSC4_FPR_MASK (0x40U)
+#define USBC_PORTSC4_FPR_SHIFT (6U)
+#define USBC_PORTSC4_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_FPR_SHIFT)) & USBC_PORTSC4_FPR_MASK)
+#define USBC_PORTSC4_SUSP_MASK (0x80U)
+#define USBC_PORTSC4_SUSP_SHIFT (7U)
+#define USBC_PORTSC4_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_SUSP_SHIFT)) & USBC_PORTSC4_SUSP_MASK)
+#define USBC_PORTSC4_PR_MASK (0x100U)
+#define USBC_PORTSC4_PR_SHIFT (8U)
+#define USBC_PORTSC4_PR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PR_SHIFT)) & USBC_PORTSC4_PR_MASK)
+#define USBC_PORTSC4_HSP_MASK (0x200U)
+#define USBC_PORTSC4_HSP_SHIFT (9U)
+#define USBC_PORTSC4_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_HSP_SHIFT)) & USBC_PORTSC4_HSP_MASK)
+#define USBC_PORTSC4_LS_MASK (0xC00U)
+#define USBC_PORTSC4_LS_SHIFT (10U)
+#define USBC_PORTSC4_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_LS_SHIFT)) & USBC_PORTSC4_LS_MASK)
+#define USBC_PORTSC4_PP_MASK (0x1000U)
+#define USBC_PORTSC4_PP_SHIFT (12U)
+#define USBC_PORTSC4_PP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PP_SHIFT)) & USBC_PORTSC4_PP_MASK)
+#define USBC_PORTSC4_PO_MASK (0x2000U)
+#define USBC_PORTSC4_PO_SHIFT (13U)
+#define USBC_PORTSC4_PO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PO_SHIFT)) & USBC_PORTSC4_PO_MASK)
+#define USBC_PORTSC4_PIC_MASK (0xC000U)
+#define USBC_PORTSC4_PIC_SHIFT (14U)
+#define USBC_PORTSC4_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PIC_SHIFT)) & USBC_PORTSC4_PIC_MASK)
+#define USBC_PORTSC4_PTC_MASK (0xF0000U)
+#define USBC_PORTSC4_PTC_SHIFT (16U)
+#define USBC_PORTSC4_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PTC_SHIFT)) & USBC_PORTSC4_PTC_MASK)
+#define USBC_PORTSC4_WKCN_MASK (0x100000U)
+#define USBC_PORTSC4_WKCN_SHIFT (20U)
+#define USBC_PORTSC4_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_WKCN_SHIFT)) & USBC_PORTSC4_WKCN_MASK)
+#define USBC_PORTSC4_WKDS_MASK (0x200000U)
+#define USBC_PORTSC4_WKDS_SHIFT (21U)
+#define USBC_PORTSC4_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_WKDS_SHIFT)) & USBC_PORTSC4_WKDS_MASK)
+#define USBC_PORTSC4_WKOC_MASK (0x400000U)
+#define USBC_PORTSC4_WKOC_SHIFT (22U)
+#define USBC_PORTSC4_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_WKOC_SHIFT)) & USBC_PORTSC4_WKOC_MASK)
+#define USBC_PORTSC4_PHCD_MASK (0x800000U)
+#define USBC_PORTSC4_PHCD_SHIFT (23U)
+#define USBC_PORTSC4_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PHCD_SHIFT)) & USBC_PORTSC4_PHCD_MASK)
+#define USBC_PORTSC4_PFSC_MASK (0x1000000U)
+#define USBC_PORTSC4_PFSC_SHIFT (24U)
+#define USBC_PORTSC4_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PFSC_SHIFT)) & USBC_PORTSC4_PFSC_MASK)
+#define USBC_PORTSC4_PTS2_MASK (0x2000000U)
+#define USBC_PORTSC4_PTS2_SHIFT (25U)
+#define USBC_PORTSC4_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PTS2_SHIFT)) & USBC_PORTSC4_PTS2_MASK)
+#define USBC_PORTSC4_PSPD_MASK (0xC000000U)
+#define USBC_PORTSC4_PSPD_SHIFT (26U)
+#define USBC_PORTSC4_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PSPD_SHIFT)) & USBC_PORTSC4_PSPD_MASK)
+#define USBC_PORTSC4_PTW_MASK (0x10000000U)
+#define USBC_PORTSC4_PTW_SHIFT (28U)
+#define USBC_PORTSC4_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PTW_SHIFT)) & USBC_PORTSC4_PTW_MASK)
+#define USBC_PORTSC4_STS_MASK (0x20000000U)
+#define USBC_PORTSC4_STS_SHIFT (29U)
+#define USBC_PORTSC4_STS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_STS_SHIFT)) & USBC_PORTSC4_STS_MASK)
+#define USBC_PORTSC4_PTS_MASK (0xC0000000U)
+#define USBC_PORTSC4_PTS_SHIFT (30U)
+#define USBC_PORTSC4_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC4_PTS_SHIFT)) & USBC_PORTSC4_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC5 - */
+/*! @{ */
+#define USBC_PORTSC5_CCS_MASK (0x1U)
+#define USBC_PORTSC5_CCS_SHIFT (0U)
+#define USBC_PORTSC5_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_CCS_SHIFT)) & USBC_PORTSC5_CCS_MASK)
+#define USBC_PORTSC5_CSC_MASK (0x2U)
+#define USBC_PORTSC5_CSC_SHIFT (1U)
+/*! CSC - rwc
+ */
+#define USBC_PORTSC5_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_CSC_SHIFT)) & USBC_PORTSC5_CSC_MASK)
+#define USBC_PORTSC5_PE_MASK (0x4U)
+#define USBC_PORTSC5_PE_SHIFT (2U)
+/*! PE - rwc
+ */
+#define USBC_PORTSC5_PE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PE_SHIFT)) & USBC_PORTSC5_PE_MASK)
+#define USBC_PORTSC5_PEC_MASK (0x8U)
+#define USBC_PORTSC5_PEC_SHIFT (3U)
+/*! PEC - rwc
+ */
+#define USBC_PORTSC5_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PEC_SHIFT)) & USBC_PORTSC5_PEC_MASK)
+#define USBC_PORTSC5_OCA_MASK (0x10U)
+#define USBC_PORTSC5_OCA_SHIFT (4U)
+#define USBC_PORTSC5_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_OCA_SHIFT)) & USBC_PORTSC5_OCA_MASK)
+#define USBC_PORTSC5_OCC_MASK (0x20U)
+#define USBC_PORTSC5_OCC_SHIFT (5U)
+#define USBC_PORTSC5_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_OCC_SHIFT)) & USBC_PORTSC5_OCC_MASK)
+#define USBC_PORTSC5_FPR_MASK (0x40U)
+#define USBC_PORTSC5_FPR_SHIFT (6U)
+#define USBC_PORTSC5_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_FPR_SHIFT)) & USBC_PORTSC5_FPR_MASK)
+#define USBC_PORTSC5_SUSP_MASK (0x80U)
+#define USBC_PORTSC5_SUSP_SHIFT (7U)
+#define USBC_PORTSC5_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_SUSP_SHIFT)) & USBC_PORTSC5_SUSP_MASK)
+#define USBC_PORTSC5_PR_MASK (0x100U)
+#define USBC_PORTSC5_PR_SHIFT (8U)
+#define USBC_PORTSC5_PR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PR_SHIFT)) & USBC_PORTSC5_PR_MASK)
+#define USBC_PORTSC5_HSP_MASK (0x200U)
+#define USBC_PORTSC5_HSP_SHIFT (9U)
+#define USBC_PORTSC5_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_HSP_SHIFT)) & USBC_PORTSC5_HSP_MASK)
+#define USBC_PORTSC5_LS_MASK (0xC00U)
+#define USBC_PORTSC5_LS_SHIFT (10U)
+#define USBC_PORTSC5_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_LS_SHIFT)) & USBC_PORTSC5_LS_MASK)
+#define USBC_PORTSC5_PP_MASK (0x1000U)
+#define USBC_PORTSC5_PP_SHIFT (12U)
+#define USBC_PORTSC5_PP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PP_SHIFT)) & USBC_PORTSC5_PP_MASK)
+#define USBC_PORTSC5_PO_MASK (0x2000U)
+#define USBC_PORTSC5_PO_SHIFT (13U)
+#define USBC_PORTSC5_PO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PO_SHIFT)) & USBC_PORTSC5_PO_MASK)
+#define USBC_PORTSC5_PIC_MASK (0xC000U)
+#define USBC_PORTSC5_PIC_SHIFT (14U)
+#define USBC_PORTSC5_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PIC_SHIFT)) & USBC_PORTSC5_PIC_MASK)
+#define USBC_PORTSC5_PTC_MASK (0xF0000U)
+#define USBC_PORTSC5_PTC_SHIFT (16U)
+#define USBC_PORTSC5_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PTC_SHIFT)) & USBC_PORTSC5_PTC_MASK)
+#define USBC_PORTSC5_WKCN_MASK (0x100000U)
+#define USBC_PORTSC5_WKCN_SHIFT (20U)
+#define USBC_PORTSC5_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_WKCN_SHIFT)) & USBC_PORTSC5_WKCN_MASK)
+#define USBC_PORTSC5_WKDS_MASK (0x200000U)
+#define USBC_PORTSC5_WKDS_SHIFT (21U)
+#define USBC_PORTSC5_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_WKDS_SHIFT)) & USBC_PORTSC5_WKDS_MASK)
+#define USBC_PORTSC5_WKOC_MASK (0x400000U)
+#define USBC_PORTSC5_WKOC_SHIFT (22U)
+#define USBC_PORTSC5_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_WKOC_SHIFT)) & USBC_PORTSC5_WKOC_MASK)
+#define USBC_PORTSC5_PHCD_MASK (0x800000U)
+#define USBC_PORTSC5_PHCD_SHIFT (23U)
+#define USBC_PORTSC5_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PHCD_SHIFT)) & USBC_PORTSC5_PHCD_MASK)
+#define USBC_PORTSC5_PFSC_MASK (0x1000000U)
+#define USBC_PORTSC5_PFSC_SHIFT (24U)
+#define USBC_PORTSC5_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PFSC_SHIFT)) & USBC_PORTSC5_PFSC_MASK)
+#define USBC_PORTSC5_PTS2_MASK (0x2000000U)
+#define USBC_PORTSC5_PTS2_SHIFT (25U)
+#define USBC_PORTSC5_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PTS2_SHIFT)) & USBC_PORTSC5_PTS2_MASK)
+#define USBC_PORTSC5_PSPD_MASK (0xC000000U)
+#define USBC_PORTSC5_PSPD_SHIFT (26U)
+#define USBC_PORTSC5_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PSPD_SHIFT)) & USBC_PORTSC5_PSPD_MASK)
+#define USBC_PORTSC5_PTW_MASK (0x10000000U)
+#define USBC_PORTSC5_PTW_SHIFT (28U)
+#define USBC_PORTSC5_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PTW_SHIFT)) & USBC_PORTSC5_PTW_MASK)
+#define USBC_PORTSC5_STS_MASK (0x20000000U)
+#define USBC_PORTSC5_STS_SHIFT (29U)
+#define USBC_PORTSC5_STS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_STS_SHIFT)) & USBC_PORTSC5_STS_MASK)
+#define USBC_PORTSC5_PTS_MASK (0xC0000000U)
+#define USBC_PORTSC5_PTS_SHIFT (30U)
+#define USBC_PORTSC5_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC5_PTS_SHIFT)) & USBC_PORTSC5_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC6 - */
+/*! @{ */
+#define USBC_PORTSC6_CCS_MASK (0x1U)
+#define USBC_PORTSC6_CCS_SHIFT (0U)
+#define USBC_PORTSC6_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_CCS_SHIFT)) & USBC_PORTSC6_CCS_MASK)
+#define USBC_PORTSC6_CSC_MASK (0x2U)
+#define USBC_PORTSC6_CSC_SHIFT (1U)
+/*! CSC - rwc
+ */
+#define USBC_PORTSC6_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_CSC_SHIFT)) & USBC_PORTSC6_CSC_MASK)
+#define USBC_PORTSC6_PE_MASK (0x4U)
+#define USBC_PORTSC6_PE_SHIFT (2U)
+/*! PE - rwc
+ */
+#define USBC_PORTSC6_PE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PE_SHIFT)) & USBC_PORTSC6_PE_MASK)
+#define USBC_PORTSC6_PEC_MASK (0x8U)
+#define USBC_PORTSC6_PEC_SHIFT (3U)
+/*! PEC - rwc
+ */
+#define USBC_PORTSC6_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PEC_SHIFT)) & USBC_PORTSC6_PEC_MASK)
+#define USBC_PORTSC6_OCA_MASK (0x10U)
+#define USBC_PORTSC6_OCA_SHIFT (4U)
+#define USBC_PORTSC6_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_OCA_SHIFT)) & USBC_PORTSC6_OCA_MASK)
+#define USBC_PORTSC6_OCC_MASK (0x20U)
+#define USBC_PORTSC6_OCC_SHIFT (5U)
+#define USBC_PORTSC6_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_OCC_SHIFT)) & USBC_PORTSC6_OCC_MASK)
+#define USBC_PORTSC6_FPR_MASK (0x40U)
+#define USBC_PORTSC6_FPR_SHIFT (6U)
+#define USBC_PORTSC6_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_FPR_SHIFT)) & USBC_PORTSC6_FPR_MASK)
+#define USBC_PORTSC6_SUSP_MASK (0x80U)
+#define USBC_PORTSC6_SUSP_SHIFT (7U)
+#define USBC_PORTSC6_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_SUSP_SHIFT)) & USBC_PORTSC6_SUSP_MASK)
+#define USBC_PORTSC6_PR_MASK (0x100U)
+#define USBC_PORTSC6_PR_SHIFT (8U)
+#define USBC_PORTSC6_PR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PR_SHIFT)) & USBC_PORTSC6_PR_MASK)
+#define USBC_PORTSC6_HSP_MASK (0x200U)
+#define USBC_PORTSC6_HSP_SHIFT (9U)
+#define USBC_PORTSC6_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_HSP_SHIFT)) & USBC_PORTSC6_HSP_MASK)
+#define USBC_PORTSC6_LS_MASK (0xC00U)
+#define USBC_PORTSC6_LS_SHIFT (10U)
+#define USBC_PORTSC6_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_LS_SHIFT)) & USBC_PORTSC6_LS_MASK)
+#define USBC_PORTSC6_PP_MASK (0x1000U)
+#define USBC_PORTSC6_PP_SHIFT (12U)
+#define USBC_PORTSC6_PP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PP_SHIFT)) & USBC_PORTSC6_PP_MASK)
+#define USBC_PORTSC6_PO_MASK (0x2000U)
+#define USBC_PORTSC6_PO_SHIFT (13U)
+#define USBC_PORTSC6_PO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PO_SHIFT)) & USBC_PORTSC6_PO_MASK)
+#define USBC_PORTSC6_PIC_MASK (0xC000U)
+#define USBC_PORTSC6_PIC_SHIFT (14U)
+#define USBC_PORTSC6_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PIC_SHIFT)) & USBC_PORTSC6_PIC_MASK)
+#define USBC_PORTSC6_PTC_MASK (0xF0000U)
+#define USBC_PORTSC6_PTC_SHIFT (16U)
+#define USBC_PORTSC6_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PTC_SHIFT)) & USBC_PORTSC6_PTC_MASK)
+#define USBC_PORTSC6_WKCN_MASK (0x100000U)
+#define USBC_PORTSC6_WKCN_SHIFT (20U)
+#define USBC_PORTSC6_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_WKCN_SHIFT)) & USBC_PORTSC6_WKCN_MASK)
+#define USBC_PORTSC6_WKDS_MASK (0x200000U)
+#define USBC_PORTSC6_WKDS_SHIFT (21U)
+#define USBC_PORTSC6_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_WKDS_SHIFT)) & USBC_PORTSC6_WKDS_MASK)
+#define USBC_PORTSC6_WKOC_MASK (0x400000U)
+#define USBC_PORTSC6_WKOC_SHIFT (22U)
+#define USBC_PORTSC6_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_WKOC_SHIFT)) & USBC_PORTSC6_WKOC_MASK)
+#define USBC_PORTSC6_PHCD_MASK (0x800000U)
+#define USBC_PORTSC6_PHCD_SHIFT (23U)
+#define USBC_PORTSC6_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PHCD_SHIFT)) & USBC_PORTSC6_PHCD_MASK)
+#define USBC_PORTSC6_PFSC_MASK (0x1000000U)
+#define USBC_PORTSC6_PFSC_SHIFT (24U)
+#define USBC_PORTSC6_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PFSC_SHIFT)) & USBC_PORTSC6_PFSC_MASK)
+#define USBC_PORTSC6_PTS2_MASK (0x2000000U)
+#define USBC_PORTSC6_PTS2_SHIFT (25U)
+#define USBC_PORTSC6_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PTS2_SHIFT)) & USBC_PORTSC6_PTS2_MASK)
+#define USBC_PORTSC6_PSPD_MASK (0xC000000U)
+#define USBC_PORTSC6_PSPD_SHIFT (26U)
+#define USBC_PORTSC6_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PSPD_SHIFT)) & USBC_PORTSC6_PSPD_MASK)
+#define USBC_PORTSC6_PTW_MASK (0x10000000U)
+#define USBC_PORTSC6_PTW_SHIFT (28U)
+#define USBC_PORTSC6_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PTW_SHIFT)) & USBC_PORTSC6_PTW_MASK)
+#define USBC_PORTSC6_STS_MASK (0x20000000U)
+#define USBC_PORTSC6_STS_SHIFT (29U)
+#define USBC_PORTSC6_STS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_STS_SHIFT)) & USBC_PORTSC6_STS_MASK)
+#define USBC_PORTSC6_PTS_MASK (0xC0000000U)
+#define USBC_PORTSC6_PTS_SHIFT (30U)
+#define USBC_PORTSC6_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC6_PTS_SHIFT)) & USBC_PORTSC6_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC7 - */
+/*! @{ */
+#define USBC_PORTSC7_CCS_MASK (0x1U)
+#define USBC_PORTSC7_CCS_SHIFT (0U)
+#define USBC_PORTSC7_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_CCS_SHIFT)) & USBC_PORTSC7_CCS_MASK)
+#define USBC_PORTSC7_CSC_MASK (0x2U)
+#define USBC_PORTSC7_CSC_SHIFT (1U)
+/*! CSC - rwc
+ */
+#define USBC_PORTSC7_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_CSC_SHIFT)) & USBC_PORTSC7_CSC_MASK)
+#define USBC_PORTSC7_PE_MASK (0x4U)
+#define USBC_PORTSC7_PE_SHIFT (2U)
+/*! PE - rwc
+ */
+#define USBC_PORTSC7_PE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PE_SHIFT)) & USBC_PORTSC7_PE_MASK)
+#define USBC_PORTSC7_PEC_MASK (0x8U)
+#define USBC_PORTSC7_PEC_SHIFT (3U)
+/*! PEC - rwc
+ */
+#define USBC_PORTSC7_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PEC_SHIFT)) & USBC_PORTSC7_PEC_MASK)
+#define USBC_PORTSC7_OCA_MASK (0x10U)
+#define USBC_PORTSC7_OCA_SHIFT (4U)
+#define USBC_PORTSC7_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_OCA_SHIFT)) & USBC_PORTSC7_OCA_MASK)
+#define USBC_PORTSC7_OCC_MASK (0x20U)
+#define USBC_PORTSC7_OCC_SHIFT (5U)
+#define USBC_PORTSC7_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_OCC_SHIFT)) & USBC_PORTSC7_OCC_MASK)
+#define USBC_PORTSC7_FPR_MASK (0x40U)
+#define USBC_PORTSC7_FPR_SHIFT (6U)
+#define USBC_PORTSC7_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_FPR_SHIFT)) & USBC_PORTSC7_FPR_MASK)
+#define USBC_PORTSC7_SUSP_MASK (0x80U)
+#define USBC_PORTSC7_SUSP_SHIFT (7U)
+#define USBC_PORTSC7_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_SUSP_SHIFT)) & USBC_PORTSC7_SUSP_MASK)
+#define USBC_PORTSC7_PR_MASK (0x100U)
+#define USBC_PORTSC7_PR_SHIFT (8U)
+#define USBC_PORTSC7_PR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PR_SHIFT)) & USBC_PORTSC7_PR_MASK)
+#define USBC_PORTSC7_HSP_MASK (0x200U)
+#define USBC_PORTSC7_HSP_SHIFT (9U)
+#define USBC_PORTSC7_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_HSP_SHIFT)) & USBC_PORTSC7_HSP_MASK)
+#define USBC_PORTSC7_LS_MASK (0xC00U)
+#define USBC_PORTSC7_LS_SHIFT (10U)
+#define USBC_PORTSC7_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_LS_SHIFT)) & USBC_PORTSC7_LS_MASK)
+#define USBC_PORTSC7_PP_MASK (0x1000U)
+#define USBC_PORTSC7_PP_SHIFT (12U)
+#define USBC_PORTSC7_PP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PP_SHIFT)) & USBC_PORTSC7_PP_MASK)
+#define USBC_PORTSC7_PO_MASK (0x2000U)
+#define USBC_PORTSC7_PO_SHIFT (13U)
+#define USBC_PORTSC7_PO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PO_SHIFT)) & USBC_PORTSC7_PO_MASK)
+#define USBC_PORTSC7_PIC_MASK (0xC000U)
+#define USBC_PORTSC7_PIC_SHIFT (14U)
+#define USBC_PORTSC7_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PIC_SHIFT)) & USBC_PORTSC7_PIC_MASK)
+#define USBC_PORTSC7_PTC_MASK (0xF0000U)
+#define USBC_PORTSC7_PTC_SHIFT (16U)
+#define USBC_PORTSC7_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PTC_SHIFT)) & USBC_PORTSC7_PTC_MASK)
+#define USBC_PORTSC7_WKCN_MASK (0x100000U)
+#define USBC_PORTSC7_WKCN_SHIFT (20U)
+#define USBC_PORTSC7_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_WKCN_SHIFT)) & USBC_PORTSC7_WKCN_MASK)
+#define USBC_PORTSC7_WKDS_MASK (0x200000U)
+#define USBC_PORTSC7_WKDS_SHIFT (21U)
+#define USBC_PORTSC7_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_WKDS_SHIFT)) & USBC_PORTSC7_WKDS_MASK)
+#define USBC_PORTSC7_WKOC_MASK (0x400000U)
+#define USBC_PORTSC7_WKOC_SHIFT (22U)
+#define USBC_PORTSC7_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_WKOC_SHIFT)) & USBC_PORTSC7_WKOC_MASK)
+#define USBC_PORTSC7_PHCD_MASK (0x800000U)
+#define USBC_PORTSC7_PHCD_SHIFT (23U)
+#define USBC_PORTSC7_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PHCD_SHIFT)) & USBC_PORTSC7_PHCD_MASK)
+#define USBC_PORTSC7_PFSC_MASK (0x1000000U)
+#define USBC_PORTSC7_PFSC_SHIFT (24U)
+#define USBC_PORTSC7_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PFSC_SHIFT)) & USBC_PORTSC7_PFSC_MASK)
+#define USBC_PORTSC7_PTS2_MASK (0x2000000U)
+#define USBC_PORTSC7_PTS2_SHIFT (25U)
+#define USBC_PORTSC7_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PTS2_SHIFT)) & USBC_PORTSC7_PTS2_MASK)
+#define USBC_PORTSC7_PSPD_MASK (0xC000000U)
+#define USBC_PORTSC7_PSPD_SHIFT (26U)
+#define USBC_PORTSC7_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PSPD_SHIFT)) & USBC_PORTSC7_PSPD_MASK)
+#define USBC_PORTSC7_PTW_MASK (0x10000000U)
+#define USBC_PORTSC7_PTW_SHIFT (28U)
+#define USBC_PORTSC7_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PTW_SHIFT)) & USBC_PORTSC7_PTW_MASK)
+#define USBC_PORTSC7_STS_MASK (0x20000000U)
+#define USBC_PORTSC7_STS_SHIFT (29U)
+#define USBC_PORTSC7_STS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_STS_SHIFT)) & USBC_PORTSC7_STS_MASK)
+#define USBC_PORTSC7_PTS_MASK (0xC0000000U)
+#define USBC_PORTSC7_PTS_SHIFT (30U)
+#define USBC_PORTSC7_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC7_PTS_SHIFT)) & USBC_PORTSC7_PTS_MASK)
+/*! @} */
+
+/*! @name PORTSC8 - */
+/*! @{ */
+#define USBC_PORTSC8_CCS_MASK (0x1U)
+#define USBC_PORTSC8_CCS_SHIFT (0U)
+#define USBC_PORTSC8_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_CCS_SHIFT)) & USBC_PORTSC8_CCS_MASK)
+#define USBC_PORTSC8_CSC_MASK (0x2U)
+#define USBC_PORTSC8_CSC_SHIFT (1U)
+/*! CSC - rwc
+ */
+#define USBC_PORTSC8_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_CSC_SHIFT)) & USBC_PORTSC8_CSC_MASK)
+#define USBC_PORTSC8_PE_MASK (0x4U)
+#define USBC_PORTSC8_PE_SHIFT (2U)
+/*! PE - rwc
+ */
+#define USBC_PORTSC8_PE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PE_SHIFT)) & USBC_PORTSC8_PE_MASK)
+#define USBC_PORTSC8_PEC_MASK (0x8U)
+#define USBC_PORTSC8_PEC_SHIFT (3U)
+/*! PEC - rwc
+ */
+#define USBC_PORTSC8_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PEC_SHIFT)) & USBC_PORTSC8_PEC_MASK)
+#define USBC_PORTSC8_OCA_MASK (0x10U)
+#define USBC_PORTSC8_OCA_SHIFT (4U)
+#define USBC_PORTSC8_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_OCA_SHIFT)) & USBC_PORTSC8_OCA_MASK)
+#define USBC_PORTSC8_OCC_MASK (0x20U)
+#define USBC_PORTSC8_OCC_SHIFT (5U)
+#define USBC_PORTSC8_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_OCC_SHIFT)) & USBC_PORTSC8_OCC_MASK)
+#define USBC_PORTSC8_FPR_MASK (0x40U)
+#define USBC_PORTSC8_FPR_SHIFT (6U)
+#define USBC_PORTSC8_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_FPR_SHIFT)) & USBC_PORTSC8_FPR_MASK)
+#define USBC_PORTSC8_SUSP_MASK (0x80U)
+#define USBC_PORTSC8_SUSP_SHIFT (7U)
+#define USBC_PORTSC8_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_SUSP_SHIFT)) & USBC_PORTSC8_SUSP_MASK)
+#define USBC_PORTSC8_PR_MASK (0x100U)
+#define USBC_PORTSC8_PR_SHIFT (8U)
+#define USBC_PORTSC8_PR(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PR_SHIFT)) & USBC_PORTSC8_PR_MASK)
+#define USBC_PORTSC8_HSP_MASK (0x200U)
+#define USBC_PORTSC8_HSP_SHIFT (9U)
+#define USBC_PORTSC8_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_HSP_SHIFT)) & USBC_PORTSC8_HSP_MASK)
+#define USBC_PORTSC8_LS_MASK (0xC00U)
+#define USBC_PORTSC8_LS_SHIFT (10U)
+#define USBC_PORTSC8_LS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_LS_SHIFT)) & USBC_PORTSC8_LS_MASK)
+#define USBC_PORTSC8_PP_MASK (0x1000U)
+#define USBC_PORTSC8_PP_SHIFT (12U)
+#define USBC_PORTSC8_PP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PP_SHIFT)) & USBC_PORTSC8_PP_MASK)
+#define USBC_PORTSC8_PO_MASK (0x2000U)
+#define USBC_PORTSC8_PO_SHIFT (13U)
+#define USBC_PORTSC8_PO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PO_SHIFT)) & USBC_PORTSC8_PO_MASK)
+#define USBC_PORTSC8_PIC_MASK (0xC000U)
+#define USBC_PORTSC8_PIC_SHIFT (14U)
+#define USBC_PORTSC8_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PIC_SHIFT)) & USBC_PORTSC8_PIC_MASK)
+#define USBC_PORTSC8_PTC_MASK (0xF0000U)
+#define USBC_PORTSC8_PTC_SHIFT (16U)
+#define USBC_PORTSC8_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PTC_SHIFT)) & USBC_PORTSC8_PTC_MASK)
+#define USBC_PORTSC8_WKCN_MASK (0x100000U)
+#define USBC_PORTSC8_WKCN_SHIFT (20U)
+#define USBC_PORTSC8_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_WKCN_SHIFT)) & USBC_PORTSC8_WKCN_MASK)
+#define USBC_PORTSC8_WKDS_MASK (0x200000U)
+#define USBC_PORTSC8_WKDS_SHIFT (21U)
+#define USBC_PORTSC8_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_WKDS_SHIFT)) & USBC_PORTSC8_WKDS_MASK)
+#define USBC_PORTSC8_WKOC_MASK (0x400000U)
+#define USBC_PORTSC8_WKOC_SHIFT (22U)
+#define USBC_PORTSC8_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_WKOC_SHIFT)) & USBC_PORTSC8_WKOC_MASK)
+#define USBC_PORTSC8_PHCD_MASK (0x800000U)
+#define USBC_PORTSC8_PHCD_SHIFT (23U)
+#define USBC_PORTSC8_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PHCD_SHIFT)) & USBC_PORTSC8_PHCD_MASK)
+#define USBC_PORTSC8_PFSC_MASK (0x1000000U)
+#define USBC_PORTSC8_PFSC_SHIFT (24U)
+#define USBC_PORTSC8_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PFSC_SHIFT)) & USBC_PORTSC8_PFSC_MASK)
+#define USBC_PORTSC8_PTS2_MASK (0x2000000U)
+#define USBC_PORTSC8_PTS2_SHIFT (25U)
+#define USBC_PORTSC8_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PTS2_SHIFT)) & USBC_PORTSC8_PTS2_MASK)
+#define USBC_PORTSC8_PSPD_MASK (0xC000000U)
+#define USBC_PORTSC8_PSPD_SHIFT (26U)
+#define USBC_PORTSC8_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PSPD_SHIFT)) & USBC_PORTSC8_PSPD_MASK)
+#define USBC_PORTSC8_PTW_MASK (0x10000000U)
+#define USBC_PORTSC8_PTW_SHIFT (28U)
+#define USBC_PORTSC8_PTW(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PTW_SHIFT)) & USBC_PORTSC8_PTW_MASK)
+#define USBC_PORTSC8_STS_MASK (0x20000000U)
+#define USBC_PORTSC8_STS_SHIFT (29U)
+#define USBC_PORTSC8_STS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_STS_SHIFT)) & USBC_PORTSC8_STS_MASK)
+#define USBC_PORTSC8_PTS_MASK (0xC0000000U)
+#define USBC_PORTSC8_PTS_SHIFT (30U)
+#define USBC_PORTSC8_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PORTSC8_PTS_SHIFT)) & USBC_PORTSC8_PTS_MASK)
+/*! @} */
+
+/*! @name OTGSC - */
+/*! @{ */
+#define USBC_OTGSC_VD_MASK (0x1U)
+#define USBC_OTGSC_VD_SHIFT (0U)
+/*! VD - OTG not enable
+ */
+#define USBC_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_VD_SHIFT)) & USBC_OTGSC_VD_MASK)
+#define USBC_OTGSC_VC_MASK (0x2U)
+#define USBC_OTGSC_VC_SHIFT (1U)
+/*! VC - OTG not enable
+ */
+#define USBC_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_VC_SHIFT)) & USBC_OTGSC_VC_MASK)
+#define USBC_OTGSC_HAAR_MASK (0x4U)
+#define USBC_OTGSC_HAAR_SHIFT (2U)
+/*! HAAR - OTG not enable
+ */
+#define USBC_OTGSC_HAAR(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_HAAR_SHIFT)) & USBC_OTGSC_HAAR_MASK)
+#define USBC_OTGSC_OT_MASK (0x8U)
+#define USBC_OTGSC_OT_SHIFT (3U)
+/*! OT - OTG not enable
+ */
+#define USBC_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_OT_SHIFT)) & USBC_OTGSC_OT_MASK)
+#define USBC_OTGSC_DP_MASK (0x10U)
+#define USBC_OTGSC_DP_SHIFT (4U)
+/*! DP - OTG not enable
+ */
+#define USBC_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_DP_SHIFT)) & USBC_OTGSC_DP_MASK)
+#define USBC_OTGSC_IDPU_MASK (0x20U)
+#define USBC_OTGSC_IDPU_SHIFT (5U)
+/*! IDPU - OTG not enable
+ */
+#define USBC_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_IDPU_SHIFT)) & USBC_OTGSC_IDPU_MASK)
+#define USBC_OTGSC_HADP_MASK (0x40U)
+#define USBC_OTGSC_HADP_SHIFT (6U)
+/*! HADP - OTG not enable
+ */
+#define USBC_OTGSC_HADP(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_HADP_SHIFT)) & USBC_OTGSC_HADP_MASK)
+#define USBC_OTGSC_HABA_MASK (0x80U)
+#define USBC_OTGSC_HABA_SHIFT (7U)
+/*! HABA - OTG not enable
+ */
+#define USBC_OTGSC_HABA(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_HABA_SHIFT)) & USBC_OTGSC_HABA_MASK)
+#define USBC_OTGSC_ID_MASK (0x100U)
+#define USBC_OTGSC_ID_SHIFT (8U)
+/*! ID - OTG not enable
+ */
+#define USBC_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_ID_SHIFT)) & USBC_OTGSC_ID_MASK)
+#define USBC_OTGSC_AVV_MASK (0x200U)
+#define USBC_OTGSC_AVV_SHIFT (9U)
+/*! AVV - OTG not enable
+ */
+#define USBC_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_AVV_SHIFT)) & USBC_OTGSC_AVV_MASK)
+#define USBC_OTGSC_ASV_MASK (0x400U)
+#define USBC_OTGSC_ASV_SHIFT (10U)
+/*! ASV - OTG not enable
+ */
+#define USBC_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_ASV_SHIFT)) & USBC_OTGSC_ASV_MASK)
+#define USBC_OTGSC_BSV_MASK (0x800U)
+#define USBC_OTGSC_BSV_SHIFT (11U)
+/*! BSV - OTG not enable
+ */
+#define USBC_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSV_SHIFT)) & USBC_OTGSC_BSV_MASK)
+#define USBC_OTGSC_BSE_MASK (0x1000U)
+#define USBC_OTGSC_BSE_SHIFT (12U)
+/*! BSE - OTG not enable
+ */
+#define USBC_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSE_SHIFT)) & USBC_OTGSC_BSE_MASK)
+#define USBC_OTGSC_OTGSC_1MST_MASK (0x2000U)
+#define USBC_OTGSC_OTGSC_1MST_SHIFT (13U)
+/*! OTGSC_1msT - OTG not enable
+ */
+#define USBC_OTGSC_OTGSC_1MST(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_OTGSC_1MST_SHIFT)) & USBC_OTGSC_OTGSC_1MST_MASK)
+#define USBC_OTGSC_DPS_MASK (0x4000U)
+#define USBC_OTGSC_DPS_SHIFT (14U)
+/*! DPS - OTG not enable
+ */
+#define USBC_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_DPS_SHIFT)) & USBC_OTGSC_DPS_MASK)
+#define USBC_OTGSC_RESERVED_15_MASK (0x8000U)
+#define USBC_OTGSC_RESERVED_15_SHIFT (15U)
+/*! Reserved_15 - OTG not enable
+ */
+#define USBC_OTGSC_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_RESERVED_15_SHIFT)) & USBC_OTGSC_RESERVED_15_MASK)
+#define USBC_OTGSC_IDIS_MASK (0x10000U)
+#define USBC_OTGSC_IDIS_SHIFT (16U)
+/*! IDIS - rwc
+ */
+#define USBC_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_IDIS_SHIFT)) & USBC_OTGSC_IDIS_MASK)
+#define USBC_OTGSC_AVVIS_MASK (0x20000U)
+#define USBC_OTGSC_AVVIS_SHIFT (17U)
+/*! AVVIS - rwc
+ */
+#define USBC_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_AVVIS_SHIFT)) & USBC_OTGSC_AVVIS_MASK)
+#define USBC_OTGSC_ASVIS_MASK (0x40000U)
+#define USBC_OTGSC_ASVIS_SHIFT (18U)
+/*! ASVIS - rwc
+ */
+#define USBC_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_ASVIS_SHIFT)) & USBC_OTGSC_ASVIS_MASK)
+#define USBC_OTGSC_BSVIS_MASK (0x80000U)
+#define USBC_OTGSC_BSVIS_SHIFT (19U)
+/*! BSVIS - rwc
+ */
+#define USBC_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSVIS_SHIFT)) & USBC_OTGSC_BSVIS_MASK)
+#define USBC_OTGSC_BSEIS_MASK (0x100000U)
+#define USBC_OTGSC_BSEIS_SHIFT (20U)
+/*! BSEIS - rwc
+ */
+#define USBC_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSEIS_SHIFT)) & USBC_OTGSC_BSEIS_MASK)
+#define USBC_OTGSC_OTGSC_1MSS_MASK (0x200000U)
+#define USBC_OTGSC_OTGSC_1MSS_SHIFT (21U)
+/*! OTGSC_1msS - rwc
+ */
+#define USBC_OTGSC_OTGSC_1MSS(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_OTGSC_1MSS_SHIFT)) & USBC_OTGSC_OTGSC_1MSS_MASK)
+#define USBC_OTGSC_DPIS_MASK (0x400000U)
+#define USBC_OTGSC_DPIS_SHIFT (22U)
+/*! DPIS - rwc
+ */
+#define USBC_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_DPIS_SHIFT)) & USBC_OTGSC_DPIS_MASK)
+#define USBC_OTGSC_RESERVED_23_MASK (0x800000U)
+#define USBC_OTGSC_RESERVED_23_SHIFT (23U)
+/*! Reserved_23 - OTG not enable
+ */
+#define USBC_OTGSC_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_RESERVED_23_SHIFT)) & USBC_OTGSC_RESERVED_23_MASK)
+#define USBC_OTGSC_IDIE_MASK (0x1000000U)
+#define USBC_OTGSC_IDIE_SHIFT (24U)
+/*! IDIE - OTG not enable
+ */
+#define USBC_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_IDIE_SHIFT)) & USBC_OTGSC_IDIE_MASK)
+#define USBC_OTGSC_AVVIE_MASK (0x2000000U)
+#define USBC_OTGSC_AVVIE_SHIFT (25U)
+/*! AVVIE - OTG not enable
+ */
+#define USBC_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_AVVIE_SHIFT)) & USBC_OTGSC_AVVIE_MASK)
+#define USBC_OTGSC_ASVIE_MASK (0x4000000U)
+#define USBC_OTGSC_ASVIE_SHIFT (26U)
+/*! ASVIE - OTG not enable
+ */
+#define USBC_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_ASVIE_SHIFT)) & USBC_OTGSC_ASVIE_MASK)
+#define USBC_OTGSC_BSVIE_MASK (0x8000000U)
+#define USBC_OTGSC_BSVIE_SHIFT (27U)
+/*! BSVIE - OTG not enable
+ */
+#define USBC_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSVIE_SHIFT)) & USBC_OTGSC_BSVIE_MASK)
+#define USBC_OTGSC_BSEIE_MASK (0x10000000U)
+#define USBC_OTGSC_BSEIE_SHIFT (28U)
+/*! BSEIE - OTG not enable
+ */
+#define USBC_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_BSEIE_SHIFT)) & USBC_OTGSC_BSEIE_MASK)
+#define USBC_OTGSC_OTGSC_1MSE_MASK (0x20000000U)
+#define USBC_OTGSC_OTGSC_1MSE_SHIFT (29U)
+/*! OTGSC_1msE - OTG not enable
+ */
+#define USBC_OTGSC_OTGSC_1MSE(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_OTGSC_1MSE_SHIFT)) & USBC_OTGSC_OTGSC_1MSE_MASK)
+#define USBC_OTGSC_DPIE_MASK (0x40000000U)
+#define USBC_OTGSC_DPIE_SHIFT (30U)
+/*! DPIE - OTG not enable
+ */
+#define USBC_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_DPIE_SHIFT)) & USBC_OTGSC_DPIE_MASK)
+#define USBC_OTGSC_RESERVED_31_MASK (0x80000000U)
+#define USBC_OTGSC_RESERVED_31_SHIFT (31U)
+/*! Reserved_31 - OTG not enable
+ */
+#define USBC_OTGSC_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << USBC_OTGSC_RESERVED_31_SHIFT)) & USBC_OTGSC_RESERVED_31_MASK)
+/*! @} */
+
+/*! @name USBMODE - */
+/*! @{ */
+#define USBC_USBMODE_CM_MASK (0x3U)
+#define USBC_USBMODE_CM_SHIFT (0U)
+/*! CM - fix device mode
+ */
+#define USBC_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_CM_SHIFT)) & USBC_USBMODE_CM_MASK)
+#define USBC_USBMODE_ES_MASK (0x4U)
+#define USBC_USBMODE_ES_SHIFT (2U)
+#define USBC_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_ES_SHIFT)) & USBC_USBMODE_ES_MASK)
+#define USBC_USBMODE_SLOM_MASK (0x8U)
+#define USBC_USBMODE_SLOM_SHIFT (3U)
+#define USBC_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_SLOM_SHIFT)) & USBC_USBMODE_SLOM_MASK)
+#define USBC_USBMODE_SDIS_MASK (0x10U)
+#define USBC_USBMODE_SDIS_SHIFT (4U)
+#define USBC_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_SDIS_SHIFT)) & USBC_USBMODE_SDIS_MASK)
+#define USBC_USBMODE_VBPS_MASK (0x20U)
+#define USBC_USBMODE_VBPS_SHIFT (5U)
+/*! VBPS - Only used in Host
+ */
+#define USBC_USBMODE_VBPS(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_VBPS_SHIFT)) & USBC_USBMODE_VBPS_MASK)
+#define USBC_USBMODE_RESERVED_6_MASK (0xFC0U)
+#define USBC_USBMODE_RESERVED_6_SHIFT (6U)
+#define USBC_USBMODE_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_RESERVED_6_SHIFT)) & USBC_USBMODE_RESERVED_6_MASK)
+#define USBC_USBMODE_TXHSD_MASK (0x7000U)
+#define USBC_USBMODE_TXHSD_SHIFT (12U)
+#define USBC_USBMODE_TXHSD(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_TXHSD_SHIFT)) & USBC_USBMODE_TXHSD_MASK)
+#define USBC_USBMODE_SRT_MASK (0x8000U)
+#define USBC_USBMODE_SRT_SHIFT (15U)
+#define USBC_USBMODE_SRT(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_SRT_SHIFT)) & USBC_USBMODE_SRT_MASK)
+#define USBC_USBMODE_RESERVED_16_MASK (0xFFFF0000U)
+#define USBC_USBMODE_RESERVED_16_SHIFT (16U)
+#define USBC_USBMODE_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << USBC_USBMODE_RESERVED_16_SHIFT)) & USBC_USBMODE_RESERVED_16_MASK)
+/*! @} */
+
+/*! @name ENDPTSETUPSTAT - */
+/*! @{ */
+#define USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
+#define USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
+/*! ENDPTSETUPSTAT - rwc
+ */
+#define USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USBC_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
+#define USBC_ENDPTSETUPSTAT_RESERVED_16_MASK (0xFFFF0000U)
+#define USBC_ENDPTSETUPSTAT_RESERVED_16_SHIFT (16U)
+#define USBC_ENDPTSETUPSTAT_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTSETUPSTAT_RESERVED_16_SHIFT)) & USBC_ENDPTSETUPSTAT_RESERVED_16_MASK)
+/*! @} */
+
+/*! @name ENDPTPRIME - */
+/*! @{ */
+#define USBC_ENDPTPRIME_PERB_MASK (0xFFFFU)
+#define USBC_ENDPTPRIME_PERB_SHIFT (0U)
+/*! PERB - rws
+ */
+#define USBC_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTPRIME_PERB_SHIFT)) & USBC_ENDPTPRIME_PERB_MASK)
+#define USBC_ENDPTPRIME_PETB_MASK (0xFFFF0000U)
+#define USBC_ENDPTPRIME_PETB_SHIFT (16U)
+/*! PETB - rws
+ */
+#define USBC_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTPRIME_PETB_SHIFT)) & USBC_ENDPTPRIME_PETB_MASK)
+/*! @} */
+
+/*! @name ENDPTFLUSH - */
+/*! @{ */
+#define USBC_ENDPTFLUSH_FERB_MASK (0xFFFFU)
+#define USBC_ENDPTFLUSH_FERB_SHIFT (0U)
+/*! FERB - rws
+ */
+#define USBC_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTFLUSH_FERB_SHIFT)) & USBC_ENDPTFLUSH_FERB_MASK)
+#define USBC_ENDPTFLUSH_FETB_MASK (0xFFFF0000U)
+#define USBC_ENDPTFLUSH_FETB_SHIFT (16U)
+/*! FETB - rws
+ */
+#define USBC_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTFLUSH_FETB_SHIFT)) & USBC_ENDPTFLUSH_FETB_MASK)
+/*! @} */
+
+/*! @name ENDPTSTAT - */
+/*! @{ */
+#define USBC_ENDPTSTAT_ERBR_MASK (0xFFFFU)
+#define USBC_ENDPTSTAT_ERBR_SHIFT (0U)
+#define USBC_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTSTAT_ERBR_SHIFT)) & USBC_ENDPTSTAT_ERBR_MASK)
+#define USBC_ENDPTSTAT_ETBR_MASK (0xFFFF0000U)
+#define USBC_ENDPTSTAT_ETBR_SHIFT (16U)
+#define USBC_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTSTAT_ETBR_SHIFT)) & USBC_ENDPTSTAT_ETBR_MASK)
+/*! @} */
+
+/*! @name ENDPTCOMPLETE - */
+/*! @{ */
+#define USBC_ENDPTCOMPLETE_ERCE_MASK (0xFFFFU)
+#define USBC_ENDPTCOMPLETE_ERCE_SHIFT (0U)
+/*! ERCE - rwc
+ */
+#define USBC_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCOMPLETE_ERCE_SHIFT)) & USBC_ENDPTCOMPLETE_ERCE_MASK)
+#define USBC_ENDPTCOMPLETE_ETCE_MASK (0xFFFF0000U)
+#define USBC_ENDPTCOMPLETE_ETCE_SHIFT (16U)
+/*! ETCE - rwc
+ */
+#define USBC_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCOMPLETE_ETCE_SHIFT)) & USBC_ENDPTCOMPLETE_ETCE_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL0 - */
+/*! @{ */
+#define USBC_ENDPTCTRL0_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL0_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RXS_SHIFT)) & USBC_ENDPTCTRL0_RXS_MASK)
+#define USBC_ENDPTCTRL0_RESERVED_1_MASK (0x2U)
+#define USBC_ENDPTCTRL0_RESERVED_1_SHIFT (1U)
+#define USBC_ENDPTCTRL0_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RESERVED_1_SHIFT)) & USBC_ENDPTCTRL0_RESERVED_1_MASK)
+#define USBC_ENDPTCTRL0_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL0_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RXT_SHIFT)) & USBC_ENDPTCTRL0_RXT_MASK)
+#define USBC_ENDPTCTRL0_RESERVED_4_MASK (0x70U)
+#define USBC_ENDPTCTRL0_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL0_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL0_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL0_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RXE_SHIFT)) & USBC_ENDPTCTRL0_RXE_MASK)
+#define USBC_ENDPTCTRL0_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL0_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL0_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL0_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL0_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL0_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_TXS_SHIFT)) & USBC_ENDPTCTRL0_TXS_MASK)
+#define USBC_ENDPTCTRL0_RESERVED_17_MASK (0x20000U)
+#define USBC_ENDPTCTRL0_RESERVED_17_SHIFT (17U)
+#define USBC_ENDPTCTRL0_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RESERVED_17_SHIFT)) & USBC_ENDPTCTRL0_RESERVED_17_MASK)
+#define USBC_ENDPTCTRL0_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL0_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_TXT_SHIFT)) & USBC_ENDPTCTRL0_TXT_MASK)
+#define USBC_ENDPTCTRL0_RESERVED_20_MASK (0x700000U)
+#define USBC_ENDPTCTRL0_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL0_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL0_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL0_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL0_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_TXE_SHIFT)) & USBC_ENDPTCTRL0_TXE_MASK)
+#define USBC_ENDPTCTRL0_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL0_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL0_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL0_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL0_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL1 - */
+/*! @{ */
+#define USBC_ENDPTCTRL1_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL1_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL1_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RXS_SHIFT)) & USBC_ENDPTCTRL1_RXS_MASK)
+#define USBC_ENDPTCTRL1_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL1_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL1_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RXD_SHIFT)) & USBC_ENDPTCTRL1_RXD_MASK)
+#define USBC_ENDPTCTRL1_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL1_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL1_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RXT_SHIFT)) & USBC_ENDPTCTRL1_RXT_MASK)
+#define USBC_ENDPTCTRL1_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL1_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL1_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL1_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL1_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL1_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL1_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RXI_SHIFT)) & USBC_ENDPTCTRL1_RXI_MASK)
+#define USBC_ENDPTCTRL1_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL1_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL1_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RXR_SHIFT)) & USBC_ENDPTCTRL1_RXR_MASK)
+#define USBC_ENDPTCTRL1_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL1_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL1_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RXE_SHIFT)) & USBC_ENDPTCTRL1_RXE_MASK)
+#define USBC_ENDPTCTRL1_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL1_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL1_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL1_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL1_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL1_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL1_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_TXS_SHIFT)) & USBC_ENDPTCTRL1_TXS_MASK)
+#define USBC_ENDPTCTRL1_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL1_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL1_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_TXD_SHIFT)) & USBC_ENDPTCTRL1_TXD_MASK)
+#define USBC_ENDPTCTRL1_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL1_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL1_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_TXT_SHIFT)) & USBC_ENDPTCTRL1_TXT_MASK)
+#define USBC_ENDPTCTRL1_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL1_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL1_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL1_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL1_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL1_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL1_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_TXI_SHIFT)) & USBC_ENDPTCTRL1_TXI_MASK)
+#define USBC_ENDPTCTRL1_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL1_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL1_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_TXR_SHIFT)) & USBC_ENDPTCTRL1_TXR_MASK)
+#define USBC_ENDPTCTRL1_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL1_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL1_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_TXE_SHIFT)) & USBC_ENDPTCTRL1_TXE_MASK)
+#define USBC_ENDPTCTRL1_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL1_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL1_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL1_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL1_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL2 - */
+/*! @{ */
+#define USBC_ENDPTCTRL2_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL2_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL2_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RXS_SHIFT)) & USBC_ENDPTCTRL2_RXS_MASK)
+#define USBC_ENDPTCTRL2_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL2_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL2_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RXD_SHIFT)) & USBC_ENDPTCTRL2_RXD_MASK)
+#define USBC_ENDPTCTRL2_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL2_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL2_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RXT_SHIFT)) & USBC_ENDPTCTRL2_RXT_MASK)
+#define USBC_ENDPTCTRL2_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL2_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL2_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL2_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL2_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL2_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL2_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RXI_SHIFT)) & USBC_ENDPTCTRL2_RXI_MASK)
+#define USBC_ENDPTCTRL2_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL2_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL2_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RXR_SHIFT)) & USBC_ENDPTCTRL2_RXR_MASK)
+#define USBC_ENDPTCTRL2_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL2_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL2_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RXE_SHIFT)) & USBC_ENDPTCTRL2_RXE_MASK)
+#define USBC_ENDPTCTRL2_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL2_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL2_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL2_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL2_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL2_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL2_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_TXS_SHIFT)) & USBC_ENDPTCTRL2_TXS_MASK)
+#define USBC_ENDPTCTRL2_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL2_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL2_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_TXD_SHIFT)) & USBC_ENDPTCTRL2_TXD_MASK)
+#define USBC_ENDPTCTRL2_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL2_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL2_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_TXT_SHIFT)) & USBC_ENDPTCTRL2_TXT_MASK)
+#define USBC_ENDPTCTRL2_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL2_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL2_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL2_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL2_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL2_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL2_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_TXI_SHIFT)) & USBC_ENDPTCTRL2_TXI_MASK)
+#define USBC_ENDPTCTRL2_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL2_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL2_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_TXR_SHIFT)) & USBC_ENDPTCTRL2_TXR_MASK)
+#define USBC_ENDPTCTRL2_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL2_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL2_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_TXE_SHIFT)) & USBC_ENDPTCTRL2_TXE_MASK)
+#define USBC_ENDPTCTRL2_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL2_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL2_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL2_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL2_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL3 - */
+/*! @{ */
+#define USBC_ENDPTCTRL3_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL3_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL3_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RXS_SHIFT)) & USBC_ENDPTCTRL3_RXS_MASK)
+#define USBC_ENDPTCTRL3_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL3_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL3_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RXD_SHIFT)) & USBC_ENDPTCTRL3_RXD_MASK)
+#define USBC_ENDPTCTRL3_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL3_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL3_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RXT_SHIFT)) & USBC_ENDPTCTRL3_RXT_MASK)
+#define USBC_ENDPTCTRL3_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL3_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL3_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL3_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL3_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL3_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL3_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RXI_SHIFT)) & USBC_ENDPTCTRL3_RXI_MASK)
+#define USBC_ENDPTCTRL3_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL3_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL3_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RXR_SHIFT)) & USBC_ENDPTCTRL3_RXR_MASK)
+#define USBC_ENDPTCTRL3_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL3_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL3_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RXE_SHIFT)) & USBC_ENDPTCTRL3_RXE_MASK)
+#define USBC_ENDPTCTRL3_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL3_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL3_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL3_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL3_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL3_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL3_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_TXS_SHIFT)) & USBC_ENDPTCTRL3_TXS_MASK)
+#define USBC_ENDPTCTRL3_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL3_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL3_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_TXD_SHIFT)) & USBC_ENDPTCTRL3_TXD_MASK)
+#define USBC_ENDPTCTRL3_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL3_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL3_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_TXT_SHIFT)) & USBC_ENDPTCTRL3_TXT_MASK)
+#define USBC_ENDPTCTRL3_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL3_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL3_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL3_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL3_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL3_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL3_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_TXI_SHIFT)) & USBC_ENDPTCTRL3_TXI_MASK)
+#define USBC_ENDPTCTRL3_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL3_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL3_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_TXR_SHIFT)) & USBC_ENDPTCTRL3_TXR_MASK)
+#define USBC_ENDPTCTRL3_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL3_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL3_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_TXE_SHIFT)) & USBC_ENDPTCTRL3_TXE_MASK)
+#define USBC_ENDPTCTRL3_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL3_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL3_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL3_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL3_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL4 - */
+/*! @{ */
+#define USBC_ENDPTCTRL4_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL4_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL4_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RXS_SHIFT)) & USBC_ENDPTCTRL4_RXS_MASK)
+#define USBC_ENDPTCTRL4_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL4_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL4_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RXD_SHIFT)) & USBC_ENDPTCTRL4_RXD_MASK)
+#define USBC_ENDPTCTRL4_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL4_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL4_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RXT_SHIFT)) & USBC_ENDPTCTRL4_RXT_MASK)
+#define USBC_ENDPTCTRL4_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL4_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL4_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL4_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL4_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL4_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RXI_SHIFT)) & USBC_ENDPTCTRL4_RXI_MASK)
+#define USBC_ENDPTCTRL4_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL4_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL4_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RXR_SHIFT)) & USBC_ENDPTCTRL4_RXR_MASK)
+#define USBC_ENDPTCTRL4_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL4_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL4_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RXE_SHIFT)) & USBC_ENDPTCTRL4_RXE_MASK)
+#define USBC_ENDPTCTRL4_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL4_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL4_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL4_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL4_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL4_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL4_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_TXS_SHIFT)) & USBC_ENDPTCTRL4_TXS_MASK)
+#define USBC_ENDPTCTRL4_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL4_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL4_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_TXD_SHIFT)) & USBC_ENDPTCTRL4_TXD_MASK)
+#define USBC_ENDPTCTRL4_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL4_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL4_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_TXT_SHIFT)) & USBC_ENDPTCTRL4_TXT_MASK)
+#define USBC_ENDPTCTRL4_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL4_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL4_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL4_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL4_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL4_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL4_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_TXI_SHIFT)) & USBC_ENDPTCTRL4_TXI_MASK)
+#define USBC_ENDPTCTRL4_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL4_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL4_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_TXR_SHIFT)) & USBC_ENDPTCTRL4_TXR_MASK)
+#define USBC_ENDPTCTRL4_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL4_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL4_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_TXE_SHIFT)) & USBC_ENDPTCTRL4_TXE_MASK)
+#define USBC_ENDPTCTRL4_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL4_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL4_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL4_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL5 - */
+/*! @{ */
+#define USBC_ENDPTCTRL5_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL5_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL5_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RXS_SHIFT)) & USBC_ENDPTCTRL5_RXS_MASK)
+#define USBC_ENDPTCTRL5_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL5_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL5_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RXD_SHIFT)) & USBC_ENDPTCTRL5_RXD_MASK)
+#define USBC_ENDPTCTRL5_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL5_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL5_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RXT_SHIFT)) & USBC_ENDPTCTRL5_RXT_MASK)
+#define USBC_ENDPTCTRL5_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL5_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL5_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL5_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL5_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL5_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RXI_SHIFT)) & USBC_ENDPTCTRL5_RXI_MASK)
+#define USBC_ENDPTCTRL5_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL5_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL5_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RXR_SHIFT)) & USBC_ENDPTCTRL5_RXR_MASK)
+#define USBC_ENDPTCTRL5_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL5_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL5_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RXE_SHIFT)) & USBC_ENDPTCTRL5_RXE_MASK)
+#define USBC_ENDPTCTRL5_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL5_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL5_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL5_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL5_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL5_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL5_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_TXS_SHIFT)) & USBC_ENDPTCTRL5_TXS_MASK)
+#define USBC_ENDPTCTRL5_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL5_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL5_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_TXD_SHIFT)) & USBC_ENDPTCTRL5_TXD_MASK)
+#define USBC_ENDPTCTRL5_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL5_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL5_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_TXT_SHIFT)) & USBC_ENDPTCTRL5_TXT_MASK)
+#define USBC_ENDPTCTRL5_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL5_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL5_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL5_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL5_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL5_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_TXI_SHIFT)) & USBC_ENDPTCTRL5_TXI_MASK)
+#define USBC_ENDPTCTRL5_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL5_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL5_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_TXR_SHIFT)) & USBC_ENDPTCTRL5_TXR_MASK)
+#define USBC_ENDPTCTRL5_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL5_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL5_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_TXE_SHIFT)) & USBC_ENDPTCTRL5_TXE_MASK)
+#define USBC_ENDPTCTRL5_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL5_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL5_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL5_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL5_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL6 - */
+/*! @{ */
+#define USBC_ENDPTCTRL6_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL6_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL6_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RXS_SHIFT)) & USBC_ENDPTCTRL6_RXS_MASK)
+#define USBC_ENDPTCTRL6_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL6_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL6_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RXD_SHIFT)) & USBC_ENDPTCTRL6_RXD_MASK)
+#define USBC_ENDPTCTRL6_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL6_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL6_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RXT_SHIFT)) & USBC_ENDPTCTRL6_RXT_MASK)
+#define USBC_ENDPTCTRL6_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL6_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL6_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL6_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL6_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL6_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL6_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RXI_SHIFT)) & USBC_ENDPTCTRL6_RXI_MASK)
+#define USBC_ENDPTCTRL6_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL6_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL6_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RXR_SHIFT)) & USBC_ENDPTCTRL6_RXR_MASK)
+#define USBC_ENDPTCTRL6_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL6_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL6_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RXE_SHIFT)) & USBC_ENDPTCTRL6_RXE_MASK)
+#define USBC_ENDPTCTRL6_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL6_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL6_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL6_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL6_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL6_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL6_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_TXS_SHIFT)) & USBC_ENDPTCTRL6_TXS_MASK)
+#define USBC_ENDPTCTRL6_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL6_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL6_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_TXD_SHIFT)) & USBC_ENDPTCTRL6_TXD_MASK)
+#define USBC_ENDPTCTRL6_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL6_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL6_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_TXT_SHIFT)) & USBC_ENDPTCTRL6_TXT_MASK)
+#define USBC_ENDPTCTRL6_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL6_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL6_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL6_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL6_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL6_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL6_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_TXI_SHIFT)) & USBC_ENDPTCTRL6_TXI_MASK)
+#define USBC_ENDPTCTRL6_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL6_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL6_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_TXR_SHIFT)) & USBC_ENDPTCTRL6_TXR_MASK)
+#define USBC_ENDPTCTRL6_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL6_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL6_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_TXE_SHIFT)) & USBC_ENDPTCTRL6_TXE_MASK)
+#define USBC_ENDPTCTRL6_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL6_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL6_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL6_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL6_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL7 - */
+/*! @{ */
+#define USBC_ENDPTCTRL7_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL7_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL7_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RXS_SHIFT)) & USBC_ENDPTCTRL7_RXS_MASK)
+#define USBC_ENDPTCTRL7_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL7_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL7_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RXD_SHIFT)) & USBC_ENDPTCTRL7_RXD_MASK)
+#define USBC_ENDPTCTRL7_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL7_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL7_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RXT_SHIFT)) & USBC_ENDPTCTRL7_RXT_MASK)
+#define USBC_ENDPTCTRL7_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL7_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL7_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL7_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL7_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL7_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL7_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RXI_SHIFT)) & USBC_ENDPTCTRL7_RXI_MASK)
+#define USBC_ENDPTCTRL7_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL7_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL7_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RXR_SHIFT)) & USBC_ENDPTCTRL7_RXR_MASK)
+#define USBC_ENDPTCTRL7_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL7_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL7_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RXE_SHIFT)) & USBC_ENDPTCTRL7_RXE_MASK)
+#define USBC_ENDPTCTRL7_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL7_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL7_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL7_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL7_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL7_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL7_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_TXS_SHIFT)) & USBC_ENDPTCTRL7_TXS_MASK)
+#define USBC_ENDPTCTRL7_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL7_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL7_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_TXD_SHIFT)) & USBC_ENDPTCTRL7_TXD_MASK)
+#define USBC_ENDPTCTRL7_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL7_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL7_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_TXT_SHIFT)) & USBC_ENDPTCTRL7_TXT_MASK)
+#define USBC_ENDPTCTRL7_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL7_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL7_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL7_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL7_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL7_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL7_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_TXI_SHIFT)) & USBC_ENDPTCTRL7_TXI_MASK)
+#define USBC_ENDPTCTRL7_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL7_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL7_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_TXR_SHIFT)) & USBC_ENDPTCTRL7_TXR_MASK)
+#define USBC_ENDPTCTRL7_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL7_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL7_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_TXE_SHIFT)) & USBC_ENDPTCTRL7_TXE_MASK)
+#define USBC_ENDPTCTRL7_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL7_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL7_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL7_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL7_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL8 - */
+/*! @{ */
+#define USBC_ENDPTCTRL8_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL8_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL8_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RXS_SHIFT)) & USBC_ENDPTCTRL8_RXS_MASK)
+#define USBC_ENDPTCTRL8_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL8_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL8_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RXD_SHIFT)) & USBC_ENDPTCTRL8_RXD_MASK)
+#define USBC_ENDPTCTRL8_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL8_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL8_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RXT_SHIFT)) & USBC_ENDPTCTRL8_RXT_MASK)
+#define USBC_ENDPTCTRL8_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL8_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL8_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL8_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL8_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL8_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL8_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RXI_SHIFT)) & USBC_ENDPTCTRL8_RXI_MASK)
+#define USBC_ENDPTCTRL8_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL8_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL8_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RXR_SHIFT)) & USBC_ENDPTCTRL8_RXR_MASK)
+#define USBC_ENDPTCTRL8_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL8_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL8_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RXE_SHIFT)) & USBC_ENDPTCTRL8_RXE_MASK)
+#define USBC_ENDPTCTRL8_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL8_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL8_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL8_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL8_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL8_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL8_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_TXS_SHIFT)) & USBC_ENDPTCTRL8_TXS_MASK)
+#define USBC_ENDPTCTRL8_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL8_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL8_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_TXD_SHIFT)) & USBC_ENDPTCTRL8_TXD_MASK)
+#define USBC_ENDPTCTRL8_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL8_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL8_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_TXT_SHIFT)) & USBC_ENDPTCTRL8_TXT_MASK)
+#define USBC_ENDPTCTRL8_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL8_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL8_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL8_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL8_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL8_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL8_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_TXI_SHIFT)) & USBC_ENDPTCTRL8_TXI_MASK)
+#define USBC_ENDPTCTRL8_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL8_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL8_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_TXR_SHIFT)) & USBC_ENDPTCTRL8_TXR_MASK)
+#define USBC_ENDPTCTRL8_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL8_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL8_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_TXE_SHIFT)) & USBC_ENDPTCTRL8_TXE_MASK)
+#define USBC_ENDPTCTRL8_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL8_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL8_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL8_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL8_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL9 - */
+/*! @{ */
+#define USBC_ENDPTCTRL9_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL9_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL9_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RXS_SHIFT)) & USBC_ENDPTCTRL9_RXS_MASK)
+#define USBC_ENDPTCTRL9_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL9_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL9_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RXD_SHIFT)) & USBC_ENDPTCTRL9_RXD_MASK)
+#define USBC_ENDPTCTRL9_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL9_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL9_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RXT_SHIFT)) & USBC_ENDPTCTRL9_RXT_MASK)
+#define USBC_ENDPTCTRL9_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL9_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL9_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL9_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL9_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL9_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL9_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RXI_SHIFT)) & USBC_ENDPTCTRL9_RXI_MASK)
+#define USBC_ENDPTCTRL9_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL9_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL9_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RXR_SHIFT)) & USBC_ENDPTCTRL9_RXR_MASK)
+#define USBC_ENDPTCTRL9_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL9_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL9_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RXE_SHIFT)) & USBC_ENDPTCTRL9_RXE_MASK)
+#define USBC_ENDPTCTRL9_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL9_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL9_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL9_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL9_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL9_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL9_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_TXS_SHIFT)) & USBC_ENDPTCTRL9_TXS_MASK)
+#define USBC_ENDPTCTRL9_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL9_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL9_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_TXD_SHIFT)) & USBC_ENDPTCTRL9_TXD_MASK)
+#define USBC_ENDPTCTRL9_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL9_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL9_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_TXT_SHIFT)) & USBC_ENDPTCTRL9_TXT_MASK)
+#define USBC_ENDPTCTRL9_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL9_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL9_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL9_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL9_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL9_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL9_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_TXI_SHIFT)) & USBC_ENDPTCTRL9_TXI_MASK)
+#define USBC_ENDPTCTRL9_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL9_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL9_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_TXR_SHIFT)) & USBC_ENDPTCTRL9_TXR_MASK)
+#define USBC_ENDPTCTRL9_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL9_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL9_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_TXE_SHIFT)) & USBC_ENDPTCTRL9_TXE_MASK)
+#define USBC_ENDPTCTRL9_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL9_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL9_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL9_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL9_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL10 - */
+/*! @{ */
+#define USBC_ENDPTCTRL10_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL10_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL10_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RXS_SHIFT)) & USBC_ENDPTCTRL10_RXS_MASK)
+#define USBC_ENDPTCTRL10_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL10_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL10_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RXD_SHIFT)) & USBC_ENDPTCTRL10_RXD_MASK)
+#define USBC_ENDPTCTRL10_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL10_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL10_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RXT_SHIFT)) & USBC_ENDPTCTRL10_RXT_MASK)
+#define USBC_ENDPTCTRL10_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL10_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL10_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL10_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL10_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL10_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL10_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RXI_SHIFT)) & USBC_ENDPTCTRL10_RXI_MASK)
+#define USBC_ENDPTCTRL10_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL10_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL10_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RXR_SHIFT)) & USBC_ENDPTCTRL10_RXR_MASK)
+#define USBC_ENDPTCTRL10_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL10_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL10_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RXE_SHIFT)) & USBC_ENDPTCTRL10_RXE_MASK)
+#define USBC_ENDPTCTRL10_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL10_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL10_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL10_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL10_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL10_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL10_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_TXS_SHIFT)) & USBC_ENDPTCTRL10_TXS_MASK)
+#define USBC_ENDPTCTRL10_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL10_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL10_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_TXD_SHIFT)) & USBC_ENDPTCTRL10_TXD_MASK)
+#define USBC_ENDPTCTRL10_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL10_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL10_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_TXT_SHIFT)) & USBC_ENDPTCTRL10_TXT_MASK)
+#define USBC_ENDPTCTRL10_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL10_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL10_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL10_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL10_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL10_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL10_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_TXI_SHIFT)) & USBC_ENDPTCTRL10_TXI_MASK)
+#define USBC_ENDPTCTRL10_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL10_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL10_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_TXR_SHIFT)) & USBC_ENDPTCTRL10_TXR_MASK)
+#define USBC_ENDPTCTRL10_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL10_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL10_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_TXE_SHIFT)) & USBC_ENDPTCTRL10_TXE_MASK)
+#define USBC_ENDPTCTRL10_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL10_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL10_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL10_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL10_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL11 - */
+/*! @{ */
+#define USBC_ENDPTCTRL11_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL11_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL11_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RXS_SHIFT)) & USBC_ENDPTCTRL11_RXS_MASK)
+#define USBC_ENDPTCTRL11_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL11_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL11_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RXD_SHIFT)) & USBC_ENDPTCTRL11_RXD_MASK)
+#define USBC_ENDPTCTRL11_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL11_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL11_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RXT_SHIFT)) & USBC_ENDPTCTRL11_RXT_MASK)
+#define USBC_ENDPTCTRL11_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL11_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL11_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL11_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL11_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL11_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL11_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RXI_SHIFT)) & USBC_ENDPTCTRL11_RXI_MASK)
+#define USBC_ENDPTCTRL11_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL11_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL11_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RXR_SHIFT)) & USBC_ENDPTCTRL11_RXR_MASK)
+#define USBC_ENDPTCTRL11_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL11_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL11_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RXE_SHIFT)) & USBC_ENDPTCTRL11_RXE_MASK)
+#define USBC_ENDPTCTRL11_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL11_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL11_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL11_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL11_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL11_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL11_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_TXS_SHIFT)) & USBC_ENDPTCTRL11_TXS_MASK)
+#define USBC_ENDPTCTRL11_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL11_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL11_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_TXD_SHIFT)) & USBC_ENDPTCTRL11_TXD_MASK)
+#define USBC_ENDPTCTRL11_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL11_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL11_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_TXT_SHIFT)) & USBC_ENDPTCTRL11_TXT_MASK)
+#define USBC_ENDPTCTRL11_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL11_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL11_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL11_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL11_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL11_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL11_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_TXI_SHIFT)) & USBC_ENDPTCTRL11_TXI_MASK)
+#define USBC_ENDPTCTRL11_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL11_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL11_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_TXR_SHIFT)) & USBC_ENDPTCTRL11_TXR_MASK)
+#define USBC_ENDPTCTRL11_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL11_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL11_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_TXE_SHIFT)) & USBC_ENDPTCTRL11_TXE_MASK)
+#define USBC_ENDPTCTRL11_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL11_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL11_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL11_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL11_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL12 - */
+/*! @{ */
+#define USBC_ENDPTCTRL12_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL12_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL12_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RXS_SHIFT)) & USBC_ENDPTCTRL12_RXS_MASK)
+#define USBC_ENDPTCTRL12_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL12_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL12_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RXD_SHIFT)) & USBC_ENDPTCTRL12_RXD_MASK)
+#define USBC_ENDPTCTRL12_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL12_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL12_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RXT_SHIFT)) & USBC_ENDPTCTRL12_RXT_MASK)
+#define USBC_ENDPTCTRL12_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL12_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL12_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL12_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL12_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL12_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL12_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RXI_SHIFT)) & USBC_ENDPTCTRL12_RXI_MASK)
+#define USBC_ENDPTCTRL12_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL12_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL12_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RXR_SHIFT)) & USBC_ENDPTCTRL12_RXR_MASK)
+#define USBC_ENDPTCTRL12_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL12_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL12_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RXE_SHIFT)) & USBC_ENDPTCTRL12_RXE_MASK)
+#define USBC_ENDPTCTRL12_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL12_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL12_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL12_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL12_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL12_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL12_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_TXS_SHIFT)) & USBC_ENDPTCTRL12_TXS_MASK)
+#define USBC_ENDPTCTRL12_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL12_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL12_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_TXD_SHIFT)) & USBC_ENDPTCTRL12_TXD_MASK)
+#define USBC_ENDPTCTRL12_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL12_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL12_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_TXT_SHIFT)) & USBC_ENDPTCTRL12_TXT_MASK)
+#define USBC_ENDPTCTRL12_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL12_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL12_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL12_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL12_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL12_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL12_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_TXI_SHIFT)) & USBC_ENDPTCTRL12_TXI_MASK)
+#define USBC_ENDPTCTRL12_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL12_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL12_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_TXR_SHIFT)) & USBC_ENDPTCTRL12_TXR_MASK)
+#define USBC_ENDPTCTRL12_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL12_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL12_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_TXE_SHIFT)) & USBC_ENDPTCTRL12_TXE_MASK)
+#define USBC_ENDPTCTRL12_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL12_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL12_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL12_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL12_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL13 - */
+/*! @{ */
+#define USBC_ENDPTCTRL13_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL13_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL13_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RXS_SHIFT)) & USBC_ENDPTCTRL13_RXS_MASK)
+#define USBC_ENDPTCTRL13_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL13_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL13_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RXD_SHIFT)) & USBC_ENDPTCTRL13_RXD_MASK)
+#define USBC_ENDPTCTRL13_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL13_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL13_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RXT_SHIFT)) & USBC_ENDPTCTRL13_RXT_MASK)
+#define USBC_ENDPTCTRL13_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL13_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL13_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL13_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL13_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL13_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL13_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RXI_SHIFT)) & USBC_ENDPTCTRL13_RXI_MASK)
+#define USBC_ENDPTCTRL13_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL13_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL13_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RXR_SHIFT)) & USBC_ENDPTCTRL13_RXR_MASK)
+#define USBC_ENDPTCTRL13_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL13_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL13_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RXE_SHIFT)) & USBC_ENDPTCTRL13_RXE_MASK)
+#define USBC_ENDPTCTRL13_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL13_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL13_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL13_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL13_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL13_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL13_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_TXS_SHIFT)) & USBC_ENDPTCTRL13_TXS_MASK)
+#define USBC_ENDPTCTRL13_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL13_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL13_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_TXD_SHIFT)) & USBC_ENDPTCTRL13_TXD_MASK)
+#define USBC_ENDPTCTRL13_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL13_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL13_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_TXT_SHIFT)) & USBC_ENDPTCTRL13_TXT_MASK)
+#define USBC_ENDPTCTRL13_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL13_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL13_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL13_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL13_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL13_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL13_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_TXI_SHIFT)) & USBC_ENDPTCTRL13_TXI_MASK)
+#define USBC_ENDPTCTRL13_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL13_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL13_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_TXR_SHIFT)) & USBC_ENDPTCTRL13_TXR_MASK)
+#define USBC_ENDPTCTRL13_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL13_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL13_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_TXE_SHIFT)) & USBC_ENDPTCTRL13_TXE_MASK)
+#define USBC_ENDPTCTRL13_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL13_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL13_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL13_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL13_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL14 - */
+/*! @{ */
+#define USBC_ENDPTCTRL14_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL14_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL14_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RXS_SHIFT)) & USBC_ENDPTCTRL14_RXS_MASK)
+#define USBC_ENDPTCTRL14_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL14_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL14_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RXD_SHIFT)) & USBC_ENDPTCTRL14_RXD_MASK)
+#define USBC_ENDPTCTRL14_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL14_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL14_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RXT_SHIFT)) & USBC_ENDPTCTRL14_RXT_MASK)
+#define USBC_ENDPTCTRL14_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL14_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL14_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL14_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL14_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL14_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL14_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RXI_SHIFT)) & USBC_ENDPTCTRL14_RXI_MASK)
+#define USBC_ENDPTCTRL14_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL14_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL14_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RXR_SHIFT)) & USBC_ENDPTCTRL14_RXR_MASK)
+#define USBC_ENDPTCTRL14_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL14_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL14_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RXE_SHIFT)) & USBC_ENDPTCTRL14_RXE_MASK)
+#define USBC_ENDPTCTRL14_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL14_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL14_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL14_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL14_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL14_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL14_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_TXS_SHIFT)) & USBC_ENDPTCTRL14_TXS_MASK)
+#define USBC_ENDPTCTRL14_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL14_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL14_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_TXD_SHIFT)) & USBC_ENDPTCTRL14_TXD_MASK)
+#define USBC_ENDPTCTRL14_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL14_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL14_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_TXT_SHIFT)) & USBC_ENDPTCTRL14_TXT_MASK)
+#define USBC_ENDPTCTRL14_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL14_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL14_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL14_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL14_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL14_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL14_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_TXI_SHIFT)) & USBC_ENDPTCTRL14_TXI_MASK)
+#define USBC_ENDPTCTRL14_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL14_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL14_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_TXR_SHIFT)) & USBC_ENDPTCTRL14_TXR_MASK)
+#define USBC_ENDPTCTRL14_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL14_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL14_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_TXE_SHIFT)) & USBC_ENDPTCTRL14_TXE_MASK)
+#define USBC_ENDPTCTRL14_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL14_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL14_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL14_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL14_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name ENDPTCTRL15 - */
+/*! @{ */
+#define USBC_ENDPTCTRL15_RXS_MASK (0x1U)
+#define USBC_ENDPTCTRL15_RXS_SHIFT (0U)
+#define USBC_ENDPTCTRL15_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RXS_SHIFT)) & USBC_ENDPTCTRL15_RXS_MASK)
+#define USBC_ENDPTCTRL15_RXD_MASK (0x2U)
+#define USBC_ENDPTCTRL15_RXD_SHIFT (1U)
+#define USBC_ENDPTCTRL15_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RXD_SHIFT)) & USBC_ENDPTCTRL15_RXD_MASK)
+#define USBC_ENDPTCTRL15_RXT_MASK (0xCU)
+#define USBC_ENDPTCTRL15_RXT_SHIFT (2U)
+#define USBC_ENDPTCTRL15_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RXT_SHIFT)) & USBC_ENDPTCTRL15_RXT_MASK)
+#define USBC_ENDPTCTRL15_RESERVED_4_MASK (0x10U)
+#define USBC_ENDPTCTRL15_RESERVED_4_SHIFT (4U)
+#define USBC_ENDPTCTRL15_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RESERVED_4_SHIFT)) & USBC_ENDPTCTRL15_RESERVED_4_MASK)
+#define USBC_ENDPTCTRL15_RXI_MASK (0x20U)
+#define USBC_ENDPTCTRL15_RXI_SHIFT (5U)
+#define USBC_ENDPTCTRL15_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RXI_SHIFT)) & USBC_ENDPTCTRL15_RXI_MASK)
+#define USBC_ENDPTCTRL15_RXR_MASK (0x40U)
+#define USBC_ENDPTCTRL15_RXR_SHIFT (6U)
+/*! RXR - ws
+ */
+#define USBC_ENDPTCTRL15_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RXR_SHIFT)) & USBC_ENDPTCTRL15_RXR_MASK)
+#define USBC_ENDPTCTRL15_RXE_MASK (0x80U)
+#define USBC_ENDPTCTRL15_RXE_SHIFT (7U)
+#define USBC_ENDPTCTRL15_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RXE_SHIFT)) & USBC_ENDPTCTRL15_RXE_MASK)
+#define USBC_ENDPTCTRL15_RESERVED_8_MASK (0xFF00U)
+#define USBC_ENDPTCTRL15_RESERVED_8_SHIFT (8U)
+#define USBC_ENDPTCTRL15_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RESERVED_8_SHIFT)) & USBC_ENDPTCTRL15_RESERVED_8_MASK)
+#define USBC_ENDPTCTRL15_TXS_MASK (0x10000U)
+#define USBC_ENDPTCTRL15_TXS_SHIFT (16U)
+#define USBC_ENDPTCTRL15_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_TXS_SHIFT)) & USBC_ENDPTCTRL15_TXS_MASK)
+#define USBC_ENDPTCTRL15_TXD_MASK (0x20000U)
+#define USBC_ENDPTCTRL15_TXD_SHIFT (17U)
+#define USBC_ENDPTCTRL15_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_TXD_SHIFT)) & USBC_ENDPTCTRL15_TXD_MASK)
+#define USBC_ENDPTCTRL15_TXT_MASK (0xC0000U)
+#define USBC_ENDPTCTRL15_TXT_SHIFT (18U)
+#define USBC_ENDPTCTRL15_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_TXT_SHIFT)) & USBC_ENDPTCTRL15_TXT_MASK)
+#define USBC_ENDPTCTRL15_RESERVED_20_MASK (0x100000U)
+#define USBC_ENDPTCTRL15_RESERVED_20_SHIFT (20U)
+#define USBC_ENDPTCTRL15_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RESERVED_20_SHIFT)) & USBC_ENDPTCTRL15_RESERVED_20_MASK)
+#define USBC_ENDPTCTRL15_TXI_MASK (0x200000U)
+#define USBC_ENDPTCTRL15_TXI_SHIFT (21U)
+#define USBC_ENDPTCTRL15_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_TXI_SHIFT)) & USBC_ENDPTCTRL15_TXI_MASK)
+#define USBC_ENDPTCTRL15_TXR_MASK (0x400000U)
+#define USBC_ENDPTCTRL15_TXR_SHIFT (22U)
+/*! TXR - ws
+ */
+#define USBC_ENDPTCTRL15_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_TXR_SHIFT)) & USBC_ENDPTCTRL15_TXR_MASK)
+#define USBC_ENDPTCTRL15_TXE_MASK (0x800000U)
+#define USBC_ENDPTCTRL15_TXE_SHIFT (23U)
+#define USBC_ENDPTCTRL15_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_TXE_SHIFT)) & USBC_ENDPTCTRL15_TXE_MASK)
+#define USBC_ENDPTCTRL15_RESERVED_24_MASK (0xFF000000U)
+#define USBC_ENDPTCTRL15_RESERVED_24_SHIFT (24U)
+#define USBC_ENDPTCTRL15_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << USBC_ENDPTCTRL15_RESERVED_24_SHIFT)) & USBC_ENDPTCTRL15_RESERVED_24_MASK)
+/*! @} */
+
+/*! @name PHY_ID - */
+/*! @{ */
+#define USBC_PHY_ID_CID0_MASK (0xFFU)
+#define USBC_PHY_ID_CID0_SHIFT (0U)
+#define USBC_PHY_ID_CID0(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_ID_CID0_SHIFT)) & USBC_PHY_ID_CID0_MASK)
+#define USBC_PHY_ID_CID1_MASK (0xFF00U)
+#define USBC_PHY_ID_CID1_SHIFT (8U)
+#define USBC_PHY_ID_CID1(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_ID_CID1_SHIFT)) & USBC_PHY_ID_CID1_MASK)
+/*! @} */
+
+/*! @name PLL_CONTROL_0 - */
+/*! @{ */
+#define USBC_PLL_CONTROL_0_FBDIV_MASK (0x1FFU)
+#define USBC_PLL_CONTROL_0_FBDIV_SHIFT (0U)
+#define USBC_PLL_CONTROL_0_FBDIV(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_FBDIV_SHIFT)) & USBC_PLL_CONTROL_0_FBDIV_MASK)
+#define USBC_PLL_CONTROL_0_REFDIV_MASK (0x3E00U)
+#define USBC_PLL_CONTROL_0_REFDIV_SHIFT (9U)
+#define USBC_PLL_CONTROL_0_REFDIV(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_REFDIV_SHIFT)) & USBC_PLL_CONTROL_0_REFDIV_MASK)
+#define USBC_PLL_CONTROL_0_PLLVDD18_MASK (0xC000U)
+#define USBC_PLL_CONTROL_0_PLLVDD18_SHIFT (14U)
+#define USBC_PLL_CONTROL_0_PLLVDD18(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_0_PLLVDD18_SHIFT)) & USBC_PLL_CONTROL_0_PLLVDD18_MASK)
+/*! @} */
+
+/*! @name PLL_CONTROL_1 - */
+/*! @{ */
+#define USBC_PLL_CONTROL_1_PLLCAL12_MASK (0x3U)
+#define USBC_PLL_CONTROL_1_PLLCAL12_SHIFT (0U)
+#define USBC_PLL_CONTROL_1_PLLCAL12(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PLLCAL12_SHIFT)) & USBC_PLL_CONTROL_1_PLLCAL12_MASK)
+#define USBC_PLL_CONTROL_1_VCOCAL_START_MASK (0x4U)
+#define USBC_PLL_CONTROL_1_VCOCAL_START_SHIFT (2U)
+#define USBC_PLL_CONTROL_1_VCOCAL_START(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_VCOCAL_START_SHIFT)) & USBC_PLL_CONTROL_1_VCOCAL_START_MASK)
+#define USBC_PLL_CONTROL_1_CLK_BLK_EN_MASK (0x8U)
+#define USBC_PLL_CONTROL_1_CLK_BLK_EN_SHIFT (3U)
+#define USBC_PLL_CONTROL_1_CLK_BLK_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_CLK_BLK_EN_SHIFT)) & USBC_PLL_CONTROL_1_CLK_BLK_EN_MASK)
+#define USBC_PLL_CONTROL_1_KVCO_MASK (0x70U)
+#define USBC_PLL_CONTROL_1_KVCO_SHIFT (4U)
+#define USBC_PLL_CONTROL_1_KVCO(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_KVCO_SHIFT)) & USBC_PLL_CONTROL_1_KVCO_MASK)
+#define USBC_PLL_CONTROL_1_KVCO_EXT_MASK (0x80U)
+#define USBC_PLL_CONTROL_1_KVCO_EXT_SHIFT (7U)
+#define USBC_PLL_CONTROL_1_KVCO_EXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_KVCO_EXT_SHIFT)) & USBC_PLL_CONTROL_1_KVCO_EXT_MASK)
+#define USBC_PLL_CONTROL_1_ICP_MASK (0x700U)
+#define USBC_PLL_CONTROL_1_ICP_SHIFT (8U)
+#define USBC_PLL_CONTROL_1_ICP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_ICP_SHIFT)) & USBC_PLL_CONTROL_1_ICP_MASK)
+#define USBC_PLL_CONTROL_1_DLL_RESET_BLK_MASK (0x800U)
+#define USBC_PLL_CONTROL_1_DLL_RESET_BLK_SHIFT (11U)
+#define USBC_PLL_CONTROL_1_DLL_RESET_BLK(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_DLL_RESET_BLK_SHIFT)) & USBC_PLL_CONTROL_1_DLL_RESET_BLK_MASK)
+#define USBC_PLL_CONTROL_1_PLL_LOCK_BYPASS_MASK (0x1000U)
+#define USBC_PLL_CONTROL_1_PLL_LOCK_BYPASS_SHIFT (12U)
+#define USBC_PLL_CONTROL_1_PLL_LOCK_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PLL_LOCK_BYPASS_SHIFT)) & USBC_PLL_CONTROL_1_PLL_LOCK_BYPASS_MASK)
+#define USBC_PLL_CONTROL_1_PU_PLL_MASK (0x2000U)
+#define USBC_PLL_CONTROL_1_PU_PLL_SHIFT (13U)
+#define USBC_PLL_CONTROL_1_PU_PLL(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PU_PLL_SHIFT)) & USBC_PLL_CONTROL_1_PU_PLL_MASK)
+#define USBC_PLL_CONTROL_1_PLL_CONTRL_BY_PIN_MASK (0x4000U)
+#define USBC_PLL_CONTROL_1_PLL_CONTRL_BY_PIN_SHIFT (14U)
+#define USBC_PLL_CONTROL_1_PLL_CONTRL_BY_PIN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PLL_CONTRL_BY_PIN_SHIFT)) & USBC_PLL_CONTROL_1_PLL_CONTRL_BY_PIN_MASK)
+#define USBC_PLL_CONTROL_1_PLL_READY_MASK (0x8000U)
+#define USBC_PLL_CONTROL_1_PLL_READY_SHIFT (15U)
+#define USBC_PLL_CONTROL_1_PLL_READY(x) (((uint32_t)(((uint32_t)(x)) << USBC_PLL_CONTROL_1_PLL_READY_SHIFT)) & USBC_PLL_CONTROL_1_PLL_READY_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR3 - */
+/*! @{ */
+#define USBC_RESERVED_ADDR3_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR3_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR3_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR3_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR3_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name TX_CHANNEL_CONTRL_0 - */
+/*! @{ */
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_MASK (0xFU)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_SHIFT (0U)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_MASK)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_MASK (0xF0U)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_SHIFT (4U)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_MASK)
+#define USBC_TX_CHANNEL_CONTRL_0_IMPCAL_VTH_MASK (0x700U)
+#define USBC_TX_CHANNEL_CONTRL_0_IMPCAL_VTH_SHIFT (8U)
+#define USBC_TX_CHANNEL_CONTRL_0_IMPCAL_VTH(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_IMPCAL_VTH_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_IMPCAL_VTH_MASK)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_EN_MASK (0x800U)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_EN_SHIFT (11U)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_EXT_FS_RCAL_EN_MASK)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_EN_MASK (0x1000U)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_EN_SHIFT (12U)
+#define USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_EXT_HS_RCAL_EN_MASK)
+#define USBC_TX_CHANNEL_CONTRL_0_RCAL_START_MASK (0x2000U)
+#define USBC_TX_CHANNEL_CONTRL_0_RCAL_START_SHIFT (13U)
+#define USBC_TX_CHANNEL_CONTRL_0_RCAL_START(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_RCAL_START_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_RCAL_START_MASK)
+#define USBC_TX_CHANNEL_CONTRL_0_TXDATA_BLOCK_EN_MASK (0x4000U)
+#define USBC_TX_CHANNEL_CONTRL_0_TXDATA_BLOCK_EN_SHIFT (14U)
+#define USBC_TX_CHANNEL_CONTRL_0_TXDATA_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_TXDATA_BLOCK_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_TXDATA_BLOCK_EN_MASK)
+#define USBC_TX_CHANNEL_CONTRL_0_ND_MASK (0x8000U)
+#define USBC_TX_CHANNEL_CONTRL_0_ND_SHIFT (15U)
+#define USBC_TX_CHANNEL_CONTRL_0_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_0_ND_SHIFT)) & USBC_TX_CHANNEL_CONTRL_0_ND_MASK)
+/*! @} */
+
+/*! @name TX_CHANNEL_CONTRL_1 - */
+/*! @{ */
+#define USBC_TX_CHANNEL_CONTRL_1_CK60_PHSEL_MASK (0xFU)
+#define USBC_TX_CHANNEL_CONTRL_1_CK60_PHSEL_SHIFT (0U)
+#define USBC_TX_CHANNEL_CONTRL_1_CK60_PHSEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_1_CK60_PHSEL_SHIFT)) & USBC_TX_CHANNEL_CONTRL_1_CK60_PHSEL_MASK)
+#define USBC_TX_CHANNEL_CONTRL_1_AMP_MASK (0x70U)
+#define USBC_TX_CHANNEL_CONTRL_1_AMP_SHIFT (4U)
+#define USBC_TX_CHANNEL_CONTRL_1_AMP(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_1_AMP_SHIFT)) & USBC_TX_CHANNEL_CONTRL_1_AMP_MASK)
+#define USBC_TX_CHANNEL_CONTRL_1_LOWVDD_EN_MASK (0x80U)
+#define USBC_TX_CHANNEL_CONTRL_1_LOWVDD_EN_SHIFT (7U)
+#define USBC_TX_CHANNEL_CONTRL_1_LOWVDD_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_1_LOWVDD_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_1_LOWVDD_EN_MASK)
+#define USBC_TX_CHANNEL_CONTRL_1_TXVDD12_MASK (0x300U)
+#define USBC_TX_CHANNEL_CONTRL_1_TXVDD12_SHIFT (8U)
+#define USBC_TX_CHANNEL_CONTRL_1_TXVDD12(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_1_TXVDD12_SHIFT)) & USBC_TX_CHANNEL_CONTRL_1_TXVDD12_MASK)
+#define USBC_TX_CHANNEL_CONTRL_1_TXVDD15_MASK (0xC00U)
+#define USBC_TX_CHANNEL_CONTRL_1_TXVDD15_SHIFT (10U)
+#define USBC_TX_CHANNEL_CONTRL_1_TXVDD15(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_1_TXVDD15_SHIFT)) & USBC_TX_CHANNEL_CONTRL_1_TXVDD15_MASK)
+#define USBC_TX_CHANNEL_CONTRL_1_ND_MASK (0xF000U)
+#define USBC_TX_CHANNEL_CONTRL_1_ND_SHIFT (12U)
+#define USBC_TX_CHANNEL_CONTRL_1_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_1_ND_SHIFT)) & USBC_TX_CHANNEL_CONTRL_1_ND_MASK)
+/*! @} */
+
+/*! @name TX_CHANNEL_CONTRL_2 - */
+/*! @{ */
+#define USBC_TX_CHANNEL_CONTRL_2_HSDRV_EN_MASK (0xFU)
+#define USBC_TX_CHANNEL_CONTRL_2_HSDRV_EN_SHIFT (0U)
+#define USBC_TX_CHANNEL_CONTRL_2_HSDRV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_2_HSDRV_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_2_HSDRV_EN_MASK)
+#define USBC_TX_CHANNEL_CONTRL_2_FSDRV_EN_MASK (0xF0U)
+#define USBC_TX_CHANNEL_CONTRL_2_FSDRV_EN_SHIFT (4U)
+#define USBC_TX_CHANNEL_CONTRL_2_FSDRV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_2_FSDRV_EN_SHIFT)) & USBC_TX_CHANNEL_CONTRL_2_FSDRV_EN_MASK)
+#define USBC_TX_CHANNEL_CONTRL_2_IMP_CAL_DLY_MASK (0x300U)
+#define USBC_TX_CHANNEL_CONTRL_2_IMP_CAL_DLY_SHIFT (8U)
+#define USBC_TX_CHANNEL_CONTRL_2_IMP_CAL_DLY(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_2_IMP_CAL_DLY_SHIFT)) & USBC_TX_CHANNEL_CONTRL_2_IMP_CAL_DLY_MASK)
+#define USBC_TX_CHANNEL_CONTRL_2_DRV_SLEWRATE_MASK (0xC00U)
+#define USBC_TX_CHANNEL_CONTRL_2_DRV_SLEWRATE_SHIFT (10U)
+#define USBC_TX_CHANNEL_CONTRL_2_DRV_SLEWRATE(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_2_DRV_SLEWRATE_SHIFT)) & USBC_TX_CHANNEL_CONTRL_2_DRV_SLEWRATE_MASK)
+#define USBC_TX_CHANNEL_CONTRL_2_ND_MASK (0xF000U)
+#define USBC_TX_CHANNEL_CONTRL_2_ND_SHIFT (12U)
+#define USBC_TX_CHANNEL_CONTRL_2_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_TX_CHANNEL_CONTRL_2_ND_SHIFT)) & USBC_TX_CHANNEL_CONTRL_2_ND_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR7 - */
+/*! @{ */
+#define USBC_RESERVED_ADDR7_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR7_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR7_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR7_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR7_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name RX_CHANNEL_CONTRL_0 - */
+/*! @{ */
+#define USBC_RX_CHANNEL_CONTRL_0_INTPI_MASK (0x3U)
+#define USBC_RX_CHANNEL_CONTRL_0_INTPI_SHIFT (0U)
+#define USBC_RX_CHANNEL_CONTRL_0_INTPI(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_INTPI_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_INTPI_MASK)
+#define USBC_RX_CHANNEL_CONTRL_0_LPF_COEF_MASK (0xCU)
+#define USBC_RX_CHANNEL_CONTRL_0_LPF_COEF_SHIFT (2U)
+#define USBC_RX_CHANNEL_CONTRL_0_LPF_COEF(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_LPF_COEF_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_LPF_COEF_MASK)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH_MASK (0xF0U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH_SHIFT (4U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_THRESH_MASK)
+#define USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH_MASK (0x300U)
+#define USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH_SHIFT (8U)
+#define USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_DISCON_THRESH_MASK)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_LENGTH_MASK (0xC00U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_LENGTH_SHIFT (10U)
+#define USBC_RX_CHANNEL_CONTRL_0_SQ_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_SQ_LENGTH_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_SQ_LENGTH_MASK)
+#define USBC_RX_CHANNEL_CONTRL_0_ACQ_LENGTH_MASK (0x3000U)
+#define USBC_RX_CHANNEL_CONTRL_0_ACQ_LENGTH_SHIFT (12U)
+#define USBC_RX_CHANNEL_CONTRL_0_ACQ_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_ACQ_LENGTH_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_ACQ_LENGTH_MASK)
+#define USBC_RX_CHANNEL_CONTRL_0_USQ_LENGTH_MASK (0x4000U)
+#define USBC_RX_CHANNEL_CONTRL_0_USQ_LENGTH_SHIFT (14U)
+#define USBC_RX_CHANNEL_CONTRL_0_USQ_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_USQ_LENGTH_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_USQ_LENGTH_MASK)
+#define USBC_RX_CHANNEL_CONTRL_0_PHASE_FREEZE_DLY_MASK (0x8000U)
+#define USBC_RX_CHANNEL_CONTRL_0_PHASE_FREEZE_DLY_SHIFT (15U)
+#define USBC_RX_CHANNEL_CONTRL_0_PHASE_FREEZE_DLY(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_0_PHASE_FREEZE_DLY_SHIFT)) & USBC_RX_CHANNEL_CONTRL_0_PHASE_FREEZE_DLY_MASK)
+/*! @} */
+
+/*! @name RX_CHANNEL_CONTRL_1 - */
+/*! @{ */
+#define USBC_RX_CHANNEL_CONTRL_1_S2TO3_DLY_SEL_MASK (0x3U)
+#define USBC_RX_CHANNEL_CONTRL_1_S2TO3_DLY_SEL_SHIFT (0U)
+#define USBC_RX_CHANNEL_CONTRL_1_S2TO3_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_S2TO3_DLY_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_S2TO3_DLY_SEL_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_CDR_FASTLOCK_EN_MASK (0x4U)
+#define USBC_RX_CHANNEL_CONTRL_1_CDR_FASTLOCK_EN_SHIFT (2U)
+#define USBC_RX_CHANNEL_CONTRL_1_CDR_FASTLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_CDR_FASTLOCK_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_CDR_FASTLOCK_EN_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_CDR_COEF_SEL_MASK (0x8U)
+#define USBC_RX_CHANNEL_CONTRL_1_CDR_COEF_SEL_SHIFT (3U)
+#define USBC_RX_CHANNEL_CONTRL_1_CDR_COEF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_CDR_COEF_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_CDR_COEF_SEL_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_SEL_MASK (0x30U)
+#define USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_SEL_SHIFT (4U)
+#define USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_SEL_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_LENGTH_MASK (0xC0U)
+#define USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_LENGTH_SHIFT (6U)
+#define USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_LENGTH_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_LENGTH_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_CAP_SEL_MASK (0x700U)
+#define USBC_RX_CHANNEL_CONTRL_1_CAP_SEL_SHIFT (8U)
+#define USBC_RX_CHANNEL_CONTRL_1_CAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_CAP_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_CAP_SEL_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_EN_MASK (0x800U)
+#define USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_EN_SHIFT (11U)
+#define USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_EDGE_DET_EN_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_EN_MASK (0x1000U)
+#define USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_EN_SHIFT (12U)
+#define USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_RXDATA_BLOCK_EN_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_EARLY_VOS_ON_EN_MASK (0x2000U)
+#define USBC_RX_CHANNEL_CONTRL_1_EARLY_VOS_ON_EN_SHIFT (13U)
+#define USBC_RX_CHANNEL_CONTRL_1_EARLY_VOS_ON_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_EARLY_VOS_ON_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_EARLY_VOS_ON_EN_MASK)
+#define USBC_RX_CHANNEL_CONTRL_1_ND_MASK (0xC000U)
+#define USBC_RX_CHANNEL_CONTRL_1_ND_SHIFT (14U)
+#define USBC_RX_CHANNEL_CONTRL_1_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_1_ND_SHIFT)) & USBC_RX_CHANNEL_CONTRL_1_ND_MASK)
+/*! @} */
+
+/*! @name RX_CHANNEL_CONTRL_2 - */
+/*! @{ */
+#define USBC_RX_CHANNEL_CONTRL_2_RXVDD12_MASK (0x3U)
+#define USBC_RX_CHANNEL_CONTRL_2_RXVDD12_SHIFT (0U)
+#define USBC_RX_CHANNEL_CONTRL_2_RXVDD12(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_2_RXVDD12_SHIFT)) & USBC_RX_CHANNEL_CONTRL_2_RXVDD12_MASK)
+#define USBC_RX_CHANNEL_CONTRL_2_RXVDD18_MASK (0xCU)
+#define USBC_RX_CHANNEL_CONTRL_2_RXVDD18_SHIFT (2U)
+#define USBC_RX_CHANNEL_CONTRL_2_RXVDD18(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_2_RXVDD18_SHIFT)) & USBC_RX_CHANNEL_CONTRL_2_RXVDD18_MASK)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_ALWAYS_ON_MASK (0x10U)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_ALWAYS_ON_SHIFT (4U)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_ALWAYS_ON(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_2_SQ_ALWAYS_ON_SHIFT)) & USBC_RX_CHANNEL_CONTRL_2_SQ_ALWAYS_ON_MASK)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_BUFFER_EN_MASK (0x20U)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_BUFFER_EN_SHIFT (5U)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_BUFFER_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_2_SQ_BUFFER_EN_SHIFT)) & USBC_RX_CHANNEL_CONTRL_2_SQ_BUFFER_EN_MASK)
+#define USBC_RX_CHANNEL_CONTRL_2_SAMPLER_CTRL_MASK (0x40U)
+#define USBC_RX_CHANNEL_CONTRL_2_SAMPLER_CTRL_SHIFT (6U)
+#define USBC_RX_CHANNEL_CONTRL_2_SAMPLER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_2_SAMPLER_CTRL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_2_SAMPLER_CTRL_MASK)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_CM_SEL_MASK (0x80U)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_CM_SEL_SHIFT (7U)
+#define USBC_RX_CHANNEL_CONTRL_2_SQ_CM_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_2_SQ_CM_SEL_SHIFT)) & USBC_RX_CHANNEL_CONTRL_2_SQ_CM_SEL_MASK)
+#define USBC_RX_CHANNEL_CONTRL_2_USQ_FILTER_MASK (0x100U)
+#define USBC_RX_CHANNEL_CONTRL_2_USQ_FILTER_SHIFT (8U)
+#define USBC_RX_CHANNEL_CONTRL_2_USQ_FILTER(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_2_USQ_FILTER_SHIFT)) & USBC_RX_CHANNEL_CONTRL_2_USQ_FILTER_MASK)
+#define USBC_RX_CHANNEL_CONTRL_2_ND_MASK (0xFE00U)
+#define USBC_RX_CHANNEL_CONTRL_2_ND_SHIFT (9U)
+#define USBC_RX_CHANNEL_CONTRL_2_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_RX_CHANNEL_CONTRL_2_ND_SHIFT)) & USBC_RX_CHANNEL_CONTRL_2_ND_MASK)
+/*! @} */
+
+/*! @name ANA_CONTRL_0 - */
+/*! @{ */
+#define USBC_ANA_CONTRL_0_IPTAT_SEL_MASK (0x7U)
+#define USBC_ANA_CONTRL_0_IPTAT_SEL_SHIFT (0U)
+#define USBC_ANA_CONTRL_0_IPTAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_0_IPTAT_SEL_SHIFT)) & USBC_ANA_CONTRL_0_IPTAT_SEL_MASK)
+#define USBC_ANA_CONTRL_0_VDD_USB2_DIG_TOP_SEL_MASK (0x8U)
+#define USBC_ANA_CONTRL_0_VDD_USB2_DIG_TOP_SEL_SHIFT (3U)
+#define USBC_ANA_CONTRL_0_VDD_USB2_DIG_TOP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_0_VDD_USB2_DIG_TOP_SEL_SHIFT)) & USBC_ANA_CONTRL_0_VDD_USB2_DIG_TOP_SEL_MASK)
+#define USBC_ANA_CONTRL_0_TOPVDD18_MASK (0x30U)
+#define USBC_ANA_CONTRL_0_TOPVDD18_SHIFT (4U)
+#define USBC_ANA_CONTRL_0_TOPVDD18(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_0_TOPVDD18_SHIFT)) & USBC_ANA_CONTRL_0_TOPVDD18_MASK)
+#define USBC_ANA_CONTRL_0_DIG_SEL_MASK (0xC0U)
+#define USBC_ANA_CONTRL_0_DIG_SEL_SHIFT (6U)
+#define USBC_ANA_CONTRL_0_DIG_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_0_DIG_SEL_SHIFT)) & USBC_ANA_CONTRL_0_DIG_SEL_MASK)
+#define USBC_ANA_CONTRL_0_BG_VSEL_MASK (0x300U)
+#define USBC_ANA_CONTRL_0_BG_VSEL_SHIFT (8U)
+#define USBC_ANA_CONTRL_0_BG_VSEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_0_BG_VSEL_SHIFT)) & USBC_ANA_CONTRL_0_BG_VSEL_MASK)
+#define USBC_ANA_CONTRL_0_ND_MASK (0xFC00U)
+#define USBC_ANA_CONTRL_0_ND_SHIFT (10U)
+#define USBC_ANA_CONTRL_0_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_0_ND_SHIFT)) & USBC_ANA_CONTRL_0_ND_MASK)
+/*! @} */
+
+/*! @name ANA_CONTRL_1 - */
+/*! @{ */
+#define USBC_ANA_CONTRL_1_TESTMON_ANA_MASK (0x3FU)
+#define USBC_ANA_CONTRL_1_TESTMON_ANA_SHIFT (0U)
+#define USBC_ANA_CONTRL_1_TESTMON_ANA(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_TESTMON_ANA_SHIFT)) & USBC_ANA_CONTRL_1_TESTMON_ANA_MASK)
+#define USBC_ANA_CONTRL_1_STRESS_TEST_MODE_MASK (0x40U)
+#define USBC_ANA_CONTRL_1_STRESS_TEST_MODE_SHIFT (6U)
+#define USBC_ANA_CONTRL_1_STRESS_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_STRESS_TEST_MODE_SHIFT)) & USBC_ANA_CONTRL_1_STRESS_TEST_MODE_MASK)
+#define USBC_ANA_CONTRL_1_R_ROTATE_SEL_MASK (0x80U)
+#define USBC_ANA_CONTRL_1_R_ROTATE_SEL_SHIFT (7U)
+#define USBC_ANA_CONTRL_1_R_ROTATE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_R_ROTATE_SEL_SHIFT)) & USBC_ANA_CONTRL_1_R_ROTATE_SEL_MASK)
+#define USBC_ANA_CONTRL_1_V2I_MASK (0x700U)
+#define USBC_ANA_CONTRL_1_V2I_SHIFT (8U)
+#define USBC_ANA_CONTRL_1_V2I(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_V2I_SHIFT)) & USBC_ANA_CONTRL_1_V2I_MASK)
+#define USBC_ANA_CONTRL_1_V2I_EXT_MASK (0x800U)
+#define USBC_ANA_CONTRL_1_V2I_EXT_SHIFT (11U)
+#define USBC_ANA_CONTRL_1_V2I_EXT(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_V2I_EXT_SHIFT)) & USBC_ANA_CONTRL_1_V2I_EXT_MASK)
+#define USBC_ANA_CONTRL_1_SEL_LPFR_MASK (0x1000U)
+#define USBC_ANA_CONTRL_1_SEL_LPFR_SHIFT (12U)
+#define USBC_ANA_CONTRL_1_SEL_LPFR(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_SEL_LPFR_SHIFT)) & USBC_ANA_CONTRL_1_SEL_LPFR_MASK)
+#define USBC_ANA_CONTRL_1_ANA_CONTRL_BY_PIN_MASK (0x2000U)
+#define USBC_ANA_CONTRL_1_ANA_CONTRL_BY_PIN_SHIFT (13U)
+#define USBC_ANA_CONTRL_1_ANA_CONTRL_BY_PIN(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_ANA_CONTRL_BY_PIN_SHIFT)) & USBC_ANA_CONTRL_1_ANA_CONTRL_BY_PIN_MASK)
+#define USBC_ANA_CONTRL_1_PU_ANA_MASK (0x4000U)
+#define USBC_ANA_CONTRL_1_PU_ANA_SHIFT (14U)
+#define USBC_ANA_CONTRL_1_PU_ANA(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_PU_ANA_SHIFT)) & USBC_ANA_CONTRL_1_PU_ANA_MASK)
+#define USBC_ANA_CONTRL_1_ND_MASK (0x8000U)
+#define USBC_ANA_CONTRL_1_ND_SHIFT (15U)
+#define USBC_ANA_CONTRL_1_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_ANA_CONTRL_1_ND_SHIFT)) & USBC_ANA_CONTRL_1_ND_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR_C - */
+/*! @{ */
+#define USBC_RESERVED_ADDR_C_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR_C_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR_C_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR_C_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR_C_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name DIGITAL_CONTROL_0 - */
+/*! @{ */
+#define USBC_DIGITAL_CONTROL_0_FIFO_FILL_NUM_MASK (0xFU)
+#define USBC_DIGITAL_CONTROL_0_FIFO_FILL_NUM_SHIFT (0U)
+#define USBC_DIGITAL_CONTROL_0_FIFO_FILL_NUM(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_FIFO_FILL_NUM_SHIFT)) & USBC_DIGITAL_CONTROL_0_FIFO_FILL_NUM_MASK)
+#define USBC_DIGITAL_CONTROL_0_SYNC_NUM_MASK (0x30U)
+#define USBC_DIGITAL_CONTROL_0_SYNC_NUM_SHIFT (4U)
+#define USBC_DIGITAL_CONTROL_0_SYNC_NUM(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_SYNC_NUM_SHIFT)) & USBC_DIGITAL_CONTROL_0_SYNC_NUM_MASK)
+#define USBC_DIGITAL_CONTROL_0_HS_DRIBBLE_EN_MASK (0x40U)
+#define USBC_DIGITAL_CONTROL_0_HS_DRIBBLE_EN_SHIFT (6U)
+#define USBC_DIGITAL_CONTROL_0_HS_DRIBBLE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_HS_DRIBBLE_EN_SHIFT)) & USBC_DIGITAL_CONTROL_0_HS_DRIBBLE_EN_MASK)
+#define USBC_DIGITAL_CONTROL_0_CLK_SUSPEND_EN_MASK (0x80U)
+#define USBC_DIGITAL_CONTROL_0_CLK_SUSPEND_EN_SHIFT (7U)
+#define USBC_DIGITAL_CONTROL_0_CLK_SUSPEND_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_CLK_SUSPEND_EN_SHIFT)) & USBC_DIGITAL_CONTROL_0_CLK_SUSPEND_EN_MASK)
+#define USBC_DIGITAL_CONTROL_0_SYNCDET_WINDOW_EN_MASK (0x100U)
+#define USBC_DIGITAL_CONTROL_0_SYNCDET_WINDOW_EN_SHIFT (8U)
+#define USBC_DIGITAL_CONTROL_0_SYNCDET_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_SYNCDET_WINDOW_EN_SHIFT)) & USBC_DIGITAL_CONTROL_0_SYNCDET_WINDOW_EN_MASK)
+#define USBC_DIGITAL_CONTROL_0_EARLY_TX_EN_MASK (0x200U)
+#define USBC_DIGITAL_CONTROL_0_EARLY_TX_EN_SHIFT (9U)
+#define USBC_DIGITAL_CONTROL_0_EARLY_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_EARLY_TX_EN_SHIFT)) & USBC_DIGITAL_CONTROL_0_EARLY_TX_EN_MASK)
+#define USBC_DIGITAL_CONTROL_0_FORCE_END_EN_MASK (0x400U)
+#define USBC_DIGITAL_CONTROL_0_FORCE_END_EN_SHIFT (10U)
+#define USBC_DIGITAL_CONTROL_0_FORCE_END_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_FORCE_END_EN_SHIFT)) & USBC_DIGITAL_CONTROL_0_FORCE_END_EN_MASK)
+#define USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL0_MASK (0x800U)
+#define USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL0_SHIFT (11U)
+#define USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL0(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL0_SHIFT)) & USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL0_MASK)
+#define USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL1_MASK (0x1000U)
+#define USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL1_SHIFT (12U)
+#define USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL1(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL1_SHIFT)) & USBC_DIGITAL_CONTROL_0_HOST_DISCON_SEL1_MASK)
+#define USBC_DIGITAL_CONTROL_0_FS_EOP_MODE_MASK (0x2000U)
+#define USBC_DIGITAL_CONTROL_0_FS_EOP_MODE_SHIFT (13U)
+#define USBC_DIGITAL_CONTROL_0_FS_EOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_FS_EOP_MODE_SHIFT)) & USBC_DIGITAL_CONTROL_0_FS_EOP_MODE_MASK)
+#define USBC_DIGITAL_CONTROL_0_FIFO_OV_MASK (0x4000U)
+#define USBC_DIGITAL_CONTROL_0_FIFO_OV_SHIFT (14U)
+#define USBC_DIGITAL_CONTROL_0_FIFO_OV(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_FIFO_OV_SHIFT)) & USBC_DIGITAL_CONTROL_0_FIFO_OV_MASK)
+#define USBC_DIGITAL_CONTROL_0_FIFO_UF_MASK (0x8000U)
+#define USBC_DIGITAL_CONTROL_0_FIFO_UF_SHIFT (15U)
+#define USBC_DIGITAL_CONTROL_0_FIFO_UF(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_0_FIFO_UF_SHIFT)) & USBC_DIGITAL_CONTROL_0_FIFO_UF_MASK)
+/*! @} */
+
+/*! @name DIGITAL_CONTROL_1 - */
+/*! @{ */
+#define USBC_DIGITAL_CONTROL_1_MON_SEL_MASK (0x3FU)
+#define USBC_DIGITAL_CONTROL_1_MON_SEL_SHIFT (0U)
+#define USBC_DIGITAL_CONTROL_1_MON_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_MON_SEL_SHIFT)) & USBC_DIGITAL_CONTROL_1_MON_SEL_MASK)
+#define USBC_DIGITAL_CONTROL_1_SQ_RST_RX_MASK (0x40U)
+#define USBC_DIGITAL_CONTROL_1_SQ_RST_RX_SHIFT (6U)
+#define USBC_DIGITAL_CONTROL_1_SQ_RST_RX(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_SQ_RST_RX_SHIFT)) & USBC_DIGITAL_CONTROL_1_SQ_RST_RX_MASK)
+#define USBC_DIGITAL_CONTROL_1_SYNC_IGNORE_SQ_MASK (0x80U)
+#define USBC_DIGITAL_CONTROL_1_SYNC_IGNORE_SQ_SHIFT (7U)
+#define USBC_DIGITAL_CONTROL_1_SYNC_IGNORE_SQ(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_SYNC_IGNORE_SQ_SHIFT)) & USBC_DIGITAL_CONTROL_1_SYNC_IGNORE_SQ_MASK)
+#define USBC_DIGITAL_CONTROL_1_DM_PULLDOWN_MASK (0x100U)
+#define USBC_DIGITAL_CONTROL_1_DM_PULLDOWN_SHIFT (8U)
+#define USBC_DIGITAL_CONTROL_1_DM_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_DM_PULLDOWN_SHIFT)) & USBC_DIGITAL_CONTROL_1_DM_PULLDOWN_MASK)
+#define USBC_DIGITAL_CONTROL_1_DP_PULLDOWN_MASK (0x200U)
+#define USBC_DIGITAL_CONTROL_1_DP_PULLDOWN_SHIFT (9U)
+#define USBC_DIGITAL_CONTROL_1_DP_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_DP_PULLDOWN_SHIFT)) & USBC_DIGITAL_CONTROL_1_DP_PULLDOWN_MASK)
+#define USBC_DIGITAL_CONTROL_1_ARC_DPDM_MODE_MASK (0x400U)
+#define USBC_DIGITAL_CONTROL_1_ARC_DPDM_MODE_SHIFT (10U)
+#define USBC_DIGITAL_CONTROL_1_ARC_DPDM_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_ARC_DPDM_MODE_SHIFT)) & USBC_DIGITAL_CONTROL_1_ARC_DPDM_MODE_MASK)
+#define USBC_DIGITAL_CONTROL_1_EXT_TX_CLK_SEL_MASK (0x800U)
+#define USBC_DIGITAL_CONTROL_1_EXT_TX_CLK_SEL_SHIFT (11U)
+#define USBC_DIGITAL_CONTROL_1_EXT_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_EXT_TX_CLK_SEL_SHIFT)) & USBC_DIGITAL_CONTROL_1_EXT_TX_CLK_SEL_MASK)
+#define USBC_DIGITAL_CONTROL_1_CLK_OUT_SEL_MASK (0x1000U)
+#define USBC_DIGITAL_CONTROL_1_CLK_OUT_SEL_SHIFT (12U)
+#define USBC_DIGITAL_CONTROL_1_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_CLK_OUT_SEL_SHIFT)) & USBC_DIGITAL_CONTROL_1_CLK_OUT_SEL_MASK)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE_MASK (0x2000U)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE_SHIFT (13U)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE_SHIFT)) & USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE_MASK)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE1_MASK (0x4000U)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE1_SHIFT (14U)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE1(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE1_SHIFT)) & USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE1_MASK)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE2_MASK (0x8000U)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE2_SHIFT (15U)
+#define USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE2(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE2_SHIFT)) & USBC_DIGITAL_CONTROL_1_FS_RX_ERROR_MODE2_MASK)
+/*! @} */
+
+/*! @name DIGITAL_CONTROL_2 - */
+/*! @{ */
+#define USBC_DIGITAL_CONTROL_2_FS_HDL_OPMD_MASK (0x1U)
+#define USBC_DIGITAL_CONTROL_2_FS_HDL_OPMD_SHIFT (0U)
+#define USBC_DIGITAL_CONTROL_2_FS_HDL_OPMD(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_FS_HDL_OPMD_SHIFT)) & USBC_DIGITAL_CONTROL_2_FS_HDL_OPMD_MASK)
+#define USBC_DIGITAL_CONTROL_2_HS_HDL_SYNC_MASK (0x2U)
+#define USBC_DIGITAL_CONTROL_2_HS_HDL_SYNC_SHIFT (1U)
+#define USBC_DIGITAL_CONTROL_2_HS_HDL_SYNC(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_HS_HDL_SYNC_SHIFT)) & USBC_DIGITAL_CONTROL_2_HS_HDL_SYNC_MASK)
+#define USBC_DIGITAL_CONTROL_2_ALIGN_FS_OUTEN_MASK (0x4U)
+#define USBC_DIGITAL_CONTROL_2_ALIGN_FS_OUTEN_SHIFT (2U)
+#define USBC_DIGITAL_CONTROL_2_ALIGN_FS_OUTEN(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_ALIGN_FS_OUTEN_SHIFT)) & USBC_DIGITAL_CONTROL_2_ALIGN_FS_OUTEN_MASK)
+#define USBC_DIGITAL_CONTROL_2_DISABLE_EL16_MASK (0x8U)
+#define USBC_DIGITAL_CONTROL_2_DISABLE_EL16_SHIFT (3U)
+#define USBC_DIGITAL_CONTROL_2_DISABLE_EL16(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_DISABLE_EL16_SHIFT)) & USBC_DIGITAL_CONTROL_2_DISABLE_EL16_MASK)
+#define USBC_DIGITAL_CONTROL_2_NOVBUS_DPDM00_MASK (0x10U)
+#define USBC_DIGITAL_CONTROL_2_NOVBUS_DPDM00_SHIFT (4U)
+#define USBC_DIGITAL_CONTROL_2_NOVBUS_DPDM00(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_NOVBUS_DPDM00_SHIFT)) & USBC_DIGITAL_CONTROL_2_NOVBUS_DPDM00_MASK)
+#define USBC_DIGITAL_CONTROL_2_LONG_EOP_MASK (0x20U)
+#define USBC_DIGITAL_CONTROL_2_LONG_EOP_SHIFT (5U)
+#define USBC_DIGITAL_CONTROL_2_LONG_EOP(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_LONG_EOP_SHIFT)) & USBC_DIGITAL_CONTROL_2_LONG_EOP_MASK)
+#define USBC_DIGITAL_CONTROL_2_ND_MASK (0xC0U)
+#define USBC_DIGITAL_CONTROL_2_ND_SHIFT (6U)
+#define USBC_DIGITAL_CONTROL_2_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_ND_SHIFT)) & USBC_DIGITAL_CONTROL_2_ND_MASK)
+#define USBC_DIGITAL_CONTROL_2_PAD_STRENGTH_MASK (0x1F00U)
+#define USBC_DIGITAL_CONTROL_2_PAD_STRENGTH_SHIFT (8U)
+#define USBC_DIGITAL_CONTROL_2_PAD_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_PAD_STRENGTH_SHIFT)) & USBC_DIGITAL_CONTROL_2_PAD_STRENGTH_MASK)
+#define USBC_DIGITAL_CONTROL_2_ND_15_13_MASK (0xE000U)
+#define USBC_DIGITAL_CONTROL_2_ND_15_13_SHIFT (13U)
+#define USBC_DIGITAL_CONTROL_2_ND_15_13(x) (((uint32_t)(((uint32_t)(x)) << USBC_DIGITAL_CONTROL_2_ND_15_13_SHIFT)) & USBC_DIGITAL_CONTROL_2_ND_15_13_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR_12H - */
+/*! @{ */
+#define USBC_RESERVED_ADDR_12H_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR_12H_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR_12H_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR_12H_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR_12H_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name TEST_CONTRL_AND_STATUS_0 - */
+/*! @{ */
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_TX_PATTERN_MASK (0xFFU)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_TX_PATTERN_SHIFT (0U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_TX_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_TEST_TX_PATTERN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_TEST_TX_PATTERN_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_MODE_2_0_MASK (0x700U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_MODE_2_0_SHIFT (8U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_MODE_2_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_TEST_MODE_2_0_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_TEST_MODE_2_0_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_BYPASS_MASK (0x800U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_BYPASS_SHIFT (11U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_TEST_BYPASS_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_TEST_BYPASS_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_LENGTH_1_0_MASK (0x3000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_LENGTH_1_0_SHIFT (12U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_LENGTH_1_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_TEST_LENGTH_1_0_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_TEST_LENGTH_1_0_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_ANA_LPBK_MASK (0x4000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_ANA_LPBK_SHIFT (14U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_ANA_LPBK(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_TEST_ANA_LPBK_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_TEST_ANA_LPBK_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_DIG_LPBK_MASK (0x8000U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_DIG_LPBK_SHIFT (15U)
+#define USBC_TEST_CONTRL_AND_STATUS_0_TEST_DIG_LPBK(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_0_TEST_DIG_LPBK_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_0_TEST_DIG_LPBK_MASK)
+/*! @} */
+
+/*! @name TEST_CONTRL_AND_STATUS_1 - */
+/*! @{ */
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_XCVR_SELECT_MASK (0x3U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_XCVR_SELECT_SHIFT (0U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_XCVR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_XCVR_SELECT_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_XCVR_SELECT_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_OP_MODE_MASK (0xCU)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_OP_MODE_SHIFT (2U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_OP_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_OP_MODE_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_OP_MODE_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_TERM_SELECT_MASK (0x10U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_TERM_SELECT_SHIFT (4U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_TERM_SELECT(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_TERM_SELECT_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_TERM_SELECT_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_TX_BITSTUFF_EN_MASK (0x20U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_TX_BITSTUFF_EN_SHIFT (5U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_TX_BITSTUFF_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_TX_BITSTUFF_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_TX_BITSTUFF_EN_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_SUSPENDM_MASK (0x40U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_SUSPENDM_SHIFT (6U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_SUSPENDM_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_SUSPENDM_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_UTMI_SEL_MASK (0x80U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_UTMI_SEL_SHIFT (7U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_UTMI_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_UTMI_SEL_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_UTMI_SEL_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_SKIP_2_0_MASK (0x700U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_SKIP_2_0_SHIFT (8U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_SKIP_2_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_SKIP_2_0_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_SKIP_2_0_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_ND_MASK (0x800U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_ND_SHIFT (11U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_ND_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_ND_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_RESET_MASK (0x1000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_RESET_SHIFT (12U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_RESET(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_RESET_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_RESET_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_EN_MASK (0x2000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_EN_SHIFT (13U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_EN_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_EN_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_FLAG_MASK (0x4000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_FLAG_SHIFT (14U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_FLAG(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_FLAG_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_FLAG_MASK)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_DONE_MASK (0x8000U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_DONE_SHIFT (15U)
+#define USBC_TEST_CONTRL_AND_STATUS_1_TEST_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBC_TEST_CONTRL_AND_STATUS_1_TEST_DONE_SHIFT)) & USBC_TEST_CONTRL_AND_STATUS_1_TEST_DONE_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR_15H - */
+/*! @{ */
+#define USBC_RESERVED_ADDR_15H_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR_15H_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR_15H_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR_15H_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR_15H_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name PHY_REG_CHGDTC_CONTRL - */
+/*! @{ */
+#define USBC_PHY_REG_CHGDTC_CONTRL_TESTMON_CHRGDTC_MASK (0x3U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_TESTMON_CHRGDTC_SHIFT (0U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_TESTMON_CHRGDTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_TESTMON_CHRGDTC_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_TESTMON_CHRGDTC_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_PU_CHRG_DTC_MASK (0x4U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_PU_CHRG_DTC_SHIFT (2U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_PU_CHRG_DTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_PU_CHRG_DTC_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_PU_CHRG_DTC_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_ENABLE_SWITCH_MASK (0x8U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_ENABLE_SWITCH_SHIFT (3U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_ENABLE_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_ENABLE_SWITCH_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_ENABLE_SWITCH_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_ND_MASK (0xFFF0U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_ND_SHIFT (4U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_ND_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_ND_MASK)
+/*! @} */
+
+/*! @name PHY_REG_OTG_CONTROL - */
+/*! @{ */
+#define USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_2_0_MASK (0x7U)
+#define USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_2_0_SHIFT (0U)
+#define USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_2_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_2_0_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_TESTMON_OTG_2_0_MASK)
+#define USBC_PHY_REG_OTG_CONTROL_PU_OTG_MASK (0x8U)
+#define USBC_PHY_REG_OTG_CONTROL_PU_OTG_SHIFT (3U)
+#define USBC_PHY_REG_OTG_CONTROL_PU_OTG(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_PU_OTG_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_PU_OTG_MASK)
+#define USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN_MASK (0x10U)
+#define USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN_SHIFT (4U)
+#define USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_OTG_CONTROL_BY_PIN_MASK)
+#define USBC_PHY_REG_OTG_CONTROL_ND_MASK (0xFFE0U)
+#define USBC_PHY_REG_OTG_CONTROL_ND_SHIFT (5U)
+#define USBC_PHY_REG_OTG_CONTROL_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_OTG_CONTROL_ND_SHIFT)) & USBC_PHY_REG_OTG_CONTROL_ND_MASK)
+/*! @} */
+
+/*! @name USB2_PHY_MON0 - */
+/*! @{ */
+#define USBC_USB2_PHY_MON0_PHY_MON_MASK (0xFFFFU)
+#define USBC_USB2_PHY_MON0_PHY_MON_SHIFT (0U)
+#define USBC_USB2_PHY_MON0_PHY_MON(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_PHY_MON0_PHY_MON_SHIFT)) & USBC_USB2_PHY_MON0_PHY_MON_MASK)
+/*! @} */
+
+/*! @name PHY_REG_CHGDTC_CONTRL_1 - */
+/*! @{ */
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_0_MASK (0x3U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_0_SHIFT (0U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_0_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_0_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN_MASK (0x4U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN_SHIFT (2U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_EN_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN_MASK (0x8U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN_SHIFT (3U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_DCP_EN_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_MASK (0x10U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_SHIFT (4U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_PD_EN_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH_MASK (0x20U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH_SHIFT (5U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_CDP_DM_AUTO_SWITCH_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM_MASK (0x40U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM_SHIFT (6U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DM_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP_MASK (0x80U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP_SHIFT (7U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_ENABLE_SWITCH_DP_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE_MASK (0x300U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE_SHIFT (8U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_VDAT_CHARGE_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE_MASK (0xC00U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE_SHIFT (10U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_VSRC_CHARGE_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PLLVDD12_MASK (0x3000U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PLLVDD12_SHIFT (12U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_PLLVDD12(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_PLLVDD12_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_PLLVDD12_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_14_MASK (0x4000U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_14_SHIFT (14U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_14(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_14_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_RESERVED_14_MASK)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL_MASK (0x8000U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL_SHIFT (15U)
+#define USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL_SHIFT)) & USBC_PHY_REG_CHGDTC_CONTRL_1_DP_DM_SWAP_CTRL_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR_1AH - */
+/*! @{ */
+#define USBC_RESERVED_ADDR_1AH_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR_1AH_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR_1AH_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR_1AH_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR_1AH_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR_1BH - */
+/*! @{ */
+#define USBC_RESERVED_ADDR_1BH_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR_1BH_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR_1BH_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR_1BH_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR_1BH_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR_1CH - */
+/*! @{ */
+#define USBC_RESERVED_ADDR_1CH_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR_1CH_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR_1CH_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR_1CH_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR_1CH_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name RESERVED_ADDR_1DH - */
+/*! @{ */
+#define USBC_RESERVED_ADDR_1DH_RESERVED_BIT_15_0_MASK (0xFFFFU)
+#define USBC_RESERVED_ADDR_1DH_RESERVED_BIT_15_0_SHIFT (0U)
+#define USBC_RESERVED_ADDR_1DH_RESERVED_BIT_15_0(x) (((uint32_t)(((uint32_t)(x)) << USBC_RESERVED_ADDR_1DH_RESERVED_BIT_15_0_SHIFT)) & USBC_RESERVED_ADDR_1DH_RESERVED_BIT_15_0_MASK)
+/*! @} */
+
+/*! @name INTERNAL_CID - */
+/*! @{ */
+#define USBC_INTERNAL_CID_ICID1_MASK (0xFFU)
+#define USBC_INTERNAL_CID_ICID1_SHIFT (0U)
+#define USBC_INTERNAL_CID_ICID1(x) (((uint32_t)(((uint32_t)(x)) << USBC_INTERNAL_CID_ICID1_SHIFT)) & USBC_INTERNAL_CID_ICID1_MASK)
+#define USBC_INTERNAL_CID_ICID0_MASK (0xFF00U)
+#define USBC_INTERNAL_CID_ICID0_SHIFT (8U)
+#define USBC_INTERNAL_CID_ICID0(x) (((uint32_t)(((uint32_t)(x)) << USBC_INTERNAL_CID_ICID0_SHIFT)) & USBC_INTERNAL_CID_ICID0_MASK)
+/*! @} */
+
+/*! @name USB2_ICID_REG1 - */
+/*! @{ */
+#define USBC_USB2_ICID_REG1_PHY_MULTIPORT_MASK (0x1U)
+#define USBC_USB2_ICID_REG1_PHY_MULTIPORT_SHIFT (0U)
+#define USBC_USB2_ICID_REG1_PHY_MULTIPORT(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_ICID_REG1_PHY_MULTIPORT_SHIFT)) & USBC_USB2_ICID_REG1_PHY_MULTIPORT_MASK)
+#define USBC_USB2_ICID_REG1_ND_MASK (0x6U)
+#define USBC_USB2_ICID_REG1_ND_SHIFT (1U)
+#define USBC_USB2_ICID_REG1_ND(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_ICID_REG1_ND_SHIFT)) & USBC_USB2_ICID_REG1_ND_MASK)
+#define USBC_USB2_ICID_REG1_DIG_REGULATOR_MASK (0x8U)
+#define USBC_USB2_ICID_REG1_DIG_REGULATOR_SHIFT (3U)
+#define USBC_USB2_ICID_REG1_DIG_REGULATOR(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_ICID_REG1_DIG_REGULATOR_SHIFT)) & USBC_USB2_ICID_REG1_DIG_REGULATOR_MASK)
+#define USBC_USB2_ICID_REG1_PHY_ULPI_MASK (0x10U)
+#define USBC_USB2_ICID_REG1_PHY_ULPI_SHIFT (4U)
+#define USBC_USB2_ICID_REG1_PHY_ULPI(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_ICID_REG1_PHY_ULPI_SHIFT)) & USBC_USB2_ICID_REG1_PHY_ULPI_MASK)
+#define USBC_USB2_ICID_REG1_PHY_HSIC_MASK (0x20U)
+#define USBC_USB2_ICID_REG1_PHY_HSIC_SHIFT (5U)
+#define USBC_USB2_ICID_REG1_PHY_HSIC(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_ICID_REG1_PHY_HSIC_SHIFT)) & USBC_USB2_ICID_REG1_PHY_HSIC_MASK)
+#define USBC_USB2_ICID_REG1_PHY_CHG_DTC_MASK (0x40U)
+#define USBC_USB2_ICID_REG1_PHY_CHG_DTC_SHIFT (6U)
+#define USBC_USB2_ICID_REG1_PHY_CHG_DTC(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_ICID_REG1_PHY_CHG_DTC_SHIFT)) & USBC_USB2_ICID_REG1_PHY_CHG_DTC_MASK)
+#define USBC_USB2_ICID_REG1_PHY_OTG_MASK (0x80U)
+#define USBC_USB2_ICID_REG1_PHY_OTG_SHIFT (7U)
+#define USBC_USB2_ICID_REG1_PHY_OTG(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_ICID_REG1_PHY_OTG_SHIFT)) & USBC_USB2_ICID_REG1_PHY_OTG_MASK)
+#define USBC_USB2_ICID_REG1_ICID2_MASK (0xFF00U)
+#define USBC_USB2_ICID_REG1_ICID2_SHIFT (8U)
+#define USBC_USB2_ICID_REG1_ICID2(x) (((uint32_t)(((uint32_t)(x)) << USBC_USB2_ICID_REG1_ICID2_SHIFT)) & USBC_USB2_ICID_REG1_ICID2_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group USBC_Register_Masks */
+
+
+/* USBC - Peripheral instance base addresses */
+/** Peripheral USBC base address */
+#define USBC_BASE (0x44001000u)
+/** Peripheral USBC base pointer */
+#define USBC ((USBC_Type *)USBC_BASE)
+/** Array initializer of USBC peripheral base addresses */
+#define USBC_BASE_ADDRS { USBC_BASE }
+/** Array initializer of USBC peripheral base pointers */
+#define USBC_BASE_PTRS { USBC }
+/** Interrupt vectors for the USBC peripheral type */
+#define USBC_IRQS { USB_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDT_Peripheral_Access_Layer WDT Peripheral Access Layer
+ * @{
+ */
+
+/** WDT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t WDT_CR; /**< , offset: 0x0 */
+ __IO uint32_t WDT_TORR; /**< , offset: 0x4 */
+ __I uint32_t WDT_CCVR; /**< , offset: 0x8 */
+ __O uint32_t WDT_CRR; /**< , offset: 0xC */
+ __I uint32_t WDT_STAT; /**< , offset: 0x10 */
+ __I uint32_t WDT_EOI; /**< , offset: 0x14 */
+ uint8_t RESERVED_0[204];
+ __I uint32_t WDT_COMP_PARAM_5; /**< , offset: 0xE4 */
+ __I uint32_t WDT_COMP_PARAM_4; /**< , offset: 0xE8 */
+ __I uint32_t WDT_COMP_PARAM_3; /**< , offset: 0xEC */
+ __I uint32_t WDT_COMP_PARAM_2; /**< , offset: 0xF0 */
+ __I uint32_t WDT_COMP_PARAM_1; /**< , offset: 0xF4 */
+ __I uint32_t WDT_COMP_VERSION; /**< , offset: 0xF8 */
+ __I uint32_t WDT_COMP_TYPE; /**< , offset: 0xFC */
+} WDT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WDT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDT_Register_Masks WDT Register Masks
+ * @{
+ */
+
+/*! @name WDT_CR - */
+/*! @{ */
+#define WDT_WDT_CR_WDT_EN_MASK (0x1U)
+#define WDT_WDT_CR_WDT_EN_SHIFT (0U)
+/*! WDT_EN
+ * 0b0..WDT disabled.
+ * 0b1..WDT enabled.
+ */
+#define WDT_WDT_CR_WDT_EN(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_CR_WDT_EN_SHIFT)) & WDT_WDT_CR_WDT_EN_MASK)
+#define WDT_WDT_CR_RMOD_MASK (0x2U)
+#define WDT_WDT_CR_RMOD_SHIFT (1U)
+/*! RMOD
+ * 0b0..Generate a system reset.
+ * 0b1..First generate an interrupt and if it is not cleared by the time a second timeout occurs then generate a system reset.
+ */
+#define WDT_WDT_CR_RMOD(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_CR_RMOD_SHIFT)) & WDT_WDT_CR_RMOD_MASK)
+#define WDT_WDT_CR_RPL_MASK (0x1CU)
+#define WDT_WDT_CR_RPL_SHIFT (2U)
+/*! RPL
+ * 0b000..2 pclk cycles
+ * 0b001..4 pclk cycles
+ * 0b010..8 pclk cycles
+ * 0b011..16 pclk cycles
+ * 0b100..32 pclk cycles
+ * 0b101..64 pclk cycles
+ * 0b110..128 pclk cycles
+ * 0b111..256 pclk cycles
+ */
+#define WDT_WDT_CR_RPL(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_CR_RPL_SHIFT)) & WDT_WDT_CR_RPL_MASK)
+/*! @} */
+
+/*! @name WDT_TORR - */
+/*! @{ */
+#define WDT_WDT_TORR_TOP_MASK (0xFU)
+#define WDT_WDT_TORR_TOP_SHIFT (0U)
+#define WDT_WDT_TORR_TOP(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_TORR_TOP_SHIFT)) & WDT_WDT_TORR_TOP_MASK)
+#define WDT_WDT_TORR_TOP_INIT_MASK (0xF0U)
+#define WDT_WDT_TORR_TOP_INIT_SHIFT (4U)
+#define WDT_WDT_TORR_TOP_INIT(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_TORR_TOP_INIT_SHIFT)) & WDT_WDT_TORR_TOP_INIT_MASK)
+#define WDT_WDT_TORR_RESERVED_MASK (0xFFFFFF00U)
+#define WDT_WDT_TORR_RESERVED_SHIFT (8U)
+#define WDT_WDT_TORR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_TORR_RESERVED_SHIFT)) & WDT_WDT_TORR_RESERVED_MASK)
+/*! @} */
+
+/*! @name WDT_CCVR - */
+/*! @{ */
+#define WDT_WDT_CCVR_WDT_CCVR_MASK (0xFFFFFFFFU)
+#define WDT_WDT_CCVR_WDT_CCVR_SHIFT (0U)
+#define WDT_WDT_CCVR_WDT_CCVR(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_CCVR_WDT_CCVR_SHIFT)) & WDT_WDT_CCVR_WDT_CCVR_MASK)
+/*! @} */
+
+/*! @name WDT_CRR - */
+/*! @{ */
+#define WDT_WDT_CRR_WDT_CRR_MASK (0xFFU)
+#define WDT_WDT_CRR_WDT_CRR_SHIFT (0U)
+#define WDT_WDT_CRR_WDT_CRR(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_CRR_WDT_CRR_SHIFT)) & WDT_WDT_CRR_WDT_CRR_MASK)
+/*! @} */
+
+/*! @name WDT_STAT - */
+/*! @{ */
+#define WDT_WDT_STAT_WDT_STAT_MASK (0x1U)
+#define WDT_WDT_STAT_WDT_STAT_SHIFT (0U)
+/*! wdt_stat
+ * 0b0..Interrupt is inactive.
+ * 0b1..Interrupt is active regardless of polarity.
+ */
+#define WDT_WDT_STAT_WDT_STAT(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_STAT_WDT_STAT_SHIFT)) & WDT_WDT_STAT_WDT_STAT_MASK)
+/*! @} */
+
+/*! @name WDT_EOI - */
+/*! @{ */
+#define WDT_WDT_EOI_WDT_EOI_MASK (0x1U)
+#define WDT_WDT_EOI_WDT_EOI_SHIFT (0U)
+#define WDT_WDT_EOI_WDT_EOI(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_EOI_WDT_EOI_SHIFT)) & WDT_WDT_EOI_WDT_EOI_MASK)
+/*! @} */
+
+/*! @name WDT_COMP_PARAM_5 - */
+/*! @{ */
+#define WDT_WDT_COMP_PARAM_5_DATA_MASK (0xFFFFFFFFU)
+#define WDT_WDT_COMP_PARAM_5_DATA_SHIFT (0U)
+#define WDT_WDT_COMP_PARAM_5_DATA(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_5_DATA_SHIFT)) & WDT_WDT_COMP_PARAM_5_DATA_MASK)
+/*! @} */
+
+/*! @name WDT_COMP_PARAM_4 - */
+/*! @{ */
+#define WDT_WDT_COMP_PARAM_4_DATA_MASK (0xFFFFFFFFU)
+#define WDT_WDT_COMP_PARAM_4_DATA_SHIFT (0U)
+#define WDT_WDT_COMP_PARAM_4_DATA(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_4_DATA_SHIFT)) & WDT_WDT_COMP_PARAM_4_DATA_MASK)
+/*! @} */
+
+/*! @name WDT_COMP_PARAM_3 - */
+/*! @{ */
+#define WDT_WDT_COMP_PARAM_3_DATA_MASK (0xFFFFFFFFU)
+#define WDT_WDT_COMP_PARAM_3_DATA_SHIFT (0U)
+#define WDT_WDT_COMP_PARAM_3_DATA(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_3_DATA_SHIFT)) & WDT_WDT_COMP_PARAM_3_DATA_MASK)
+/*! @} */
+
+/*! @name WDT_COMP_PARAM_2 - */
+/*! @{ */
+#define WDT_WDT_COMP_PARAM_2_DATA_MASK (0xFFFFFFFFU)
+#define WDT_WDT_COMP_PARAM_2_DATA_SHIFT (0U)
+#define WDT_WDT_COMP_PARAM_2_DATA(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_2_DATA_SHIFT)) & WDT_WDT_COMP_PARAM_2_DATA_MASK)
+/*! @} */
+
+/*! @name WDT_COMP_PARAM_1 - */
+/*! @{ */
+#define WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_MASK (0x1U)
+#define WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_SHIFT (0U)
+#define WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_ALWAYS_EN_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_MASK (0x2U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_SHIFT (1U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_DFLT_RMOD_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_MASK (0x4U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_SHIFT (2U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_DUAL_TOP_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_MASK (0x8U)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_SHIFT (3U)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_HC_RMOD_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_MASK (0x10U)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_SHIFT (4U)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_RPL(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_HC_RPL_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_MASK (0x20U)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_SHIFT (5U)
+#define WDT_WDT_COMP_PARAM_1_WDT_HC_TOP(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_HC_TOP_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_MASK (0x40U)
+#define WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_SHIFT (6U)
+#define WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_PAUSE_MASK (0x80U)
+#define WDT_WDT_COMP_PARAM_1_WDT_PAUSE_SHIFT (7U)
+#define WDT_WDT_COMP_PARAM_1_WDT_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_PAUSE_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_PAUSE_MASK)
+#define WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_MASK (0x300U)
+#define WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_SHIFT (8U)
+#define WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_SHIFT)) & WDT_WDT_COMP_PARAM_1_APB_DATA_WIDTH_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_MASK (0x1C00U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_SHIFT (10U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_DFLT_RPL_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_MASK (0xF0000U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_SHIFT (16U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_MASK (0xF00000U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_SHIFT (20U)
+#define WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_MASK)
+#define WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_MASK (0x1F000000U)
+#define WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_SHIFT (24U)
+#define WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_SHIFT)) & WDT_WDT_COMP_PARAM_1_WDT_CNT_WIDTH_MASK)
+/*! @} */
+
+/*! @name WDT_COMP_VERSION - */
+/*! @{ */
+#define WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_MASK (0xFFFFFFFFU)
+#define WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_SHIFT (0U)
+#define WDT_WDT_COMP_VERSION_WDT_COMP_VERSION(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_SHIFT)) & WDT_WDT_COMP_VERSION_WDT_COMP_VERSION_MASK)
+/*! @} */
+
+/*! @name WDT_COMP_TYPE - */
+/*! @{ */
+#define WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_MASK (0xFFFFFFFFU)
+#define WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_SHIFT (0U)
+#define WDT_WDT_COMP_TYPE_WDT_COMP_TYPE(x) (((uint32_t)(((uint32_t)(x)) << WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_SHIFT)) & WDT_WDT_COMP_TYPE_WDT_COMP_TYPE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group WDT_Register_Masks */
+
+
+/* WDT - Peripheral instance base addresses */
+/** Peripheral WDT base address */
+#define WDT_BASE (0x48040000u)
+/** Peripheral WDT base pointer */
+#define WDT ((WDT_Type *)WDT_BASE)
+/** Array initializer of WDT peripheral base addresses */
+#define WDT_BASE_ADDRS { WDT_BASE }
+/** Array initializer of WDT peripheral base pointers */
+#define WDT_BASE_PTRS { WDT }
+/** Interrupt vectors for the WDT peripheral type */
+#define WDT_IRQS { WDT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic pop
+ #else
+ #pragma pop
+ #endif
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/* No SDK compatibility issues. */
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif /* _88MW320_H_ */
+
diff --git a/devices/88MW320/88MW320_features.h b/devices/88MW320/88MW320_features.h
new file mode 100644
index 000000000..ef3bdddf2
--- /dev/null
+++ b/devices/88MW320/88MW320_features.h
@@ -0,0 +1,90 @@
+/*
+** ###################################################################
+** Version: rev. 1.0, 2020-09-07
+** Build: b201223
+**
+** Abstract:
+** Chip specific module features.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2020-09-07)
+** Initial version.
+**
+** ###################################################################
+*/
+
+#ifndef _88MW320_FEATURES_H_
+#define _88MW320_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ACOMP availability on the SoC. */
+#define FSL_FEATURE_SOC_ACOMP_COUNT (1)
+/* @brief MW_ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_ADC_COUNT (1)
+/* @brief MW_AES availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_AES_COUNT (1)
+/* @brief MW_BG availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_BG_COUNT (1)
+/* @brief MW_CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_CRC_COUNT (1)
+/* @brief MW_DAC availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_DAC_COUNT (1)
+/* @brief MW_DMAC availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_DMAC_COUNT (1)
+/* @brief MW_FLASHC availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_FLASHC_COUNT (1)
+/* @brief MW_GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_GPIO_COUNT (1)
+/* @brief MW_GPT availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_GPT_COUNT (4)
+/* @brief MW_I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_I2C_COUNT (2)
+/* @brief MW_PMU availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_PMU_COUNT (1)
+/* @brief MW_QSPI availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_QSPI_COUNT (1)
+/* @brief MW_PINMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_PINMUX_COUNT (1)
+/* @brief MW_RC32 availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_RC32_COUNT (1)
+/* @brief MW_RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_RTC_COUNT (1)
+/* @brief MW_SSP availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_SSP_COUNT (3)
+/* @brief MW_SYS_CTL availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_SYS_CTL_COUNT (1)
+/* @brief MW_UART availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_UART_COUNT (3)
+/* @brief MW_USBC availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_USBC_COUNT (1)
+/* @brief MW_WDT availability on the SoC. */
+#define FSL_FEATURE_SOC_MW_WDT_COUNT (1)
+/* @brief SDIOC availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIOC_COUNT (1)
+
+/* MW_ACOMP module features */
+
+/* No feature definitions */
+
+/* MW_DMAC module features */
+
+/* @brief Number of DMA channels in the SoC. */
+#define FSL_FEATURE_MW_DMAC_MODULE_CHANNEL (32)
+
+/* MW_GPIO module features */
+
+/* @brief Number of GPIO in the SoC. */
+#define FSL_FEATURE_MW_GPIO_IO_NUMBER (50)
+
+#endif /* _88MW320_FEATURES_H_ */
+
diff --git a/devices/88MW320/all_lib_device_88MW320.cmake b/devices/88MW320/all_lib_device_88MW320.cmake
new file mode 100644
index 000000000..9ff543843
--- /dev/null
+++ b/devices/88MW320/all_lib_device_88MW320.cmake
@@ -0,0 +1,100 @@
+list(APPEND CMAKE_MODULE_PATH
+ ${CMAKE_CURRENT_LIST_DIR}/.
+ ${CMAKE_CURRENT_LIST_DIR}/../../CMSIS/Include
+ ${CMAKE_CURRENT_LIST_DIR}/../../components/boot2_utils
+ ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/mflash
+ ${CMAKE_CURRENT_LIST_DIR}/../../components/flash/mflash/mw320
+ ${CMAKE_CURRENT_LIST_DIR}/../../components/lists
+ ${CMAKE_CURRENT_LIST_DIR}/../../components/osa
+ ${CMAKE_CURRENT_LIST_DIR}/../../components/serial_manager
+ ${CMAKE_CURRENT_LIST_DIR}/../../components/uart
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/common
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/acomp
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/adc
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/aes
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/crc
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/dac
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/dmac
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/flashc
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/gpio
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/gpt
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/i2c
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/qspi
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/rtc
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/sdioc
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/ssp
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/uart
+ ${CMAKE_CURRENT_LIST_DIR}/../../drivers/mw320/wdt
+ ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/lwip
+ ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/mbedtls
+ ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/sdmmc
+ ${CMAKE_CURRENT_LIST_DIR}/../../../middleware/wifi
+ ${CMAKE_CURRENT_LIST_DIR}/../../../rtos/freertos/freertos_kernel
+ ${CMAKE_CURRENT_LIST_DIR}/../../utilities/assert
+ ${CMAKE_CURRENT_LIST_DIR}/../../utilities/debug_console
+ ${CMAKE_CURRENT_LIST_DIR}/../../utilities/misc_utilities
+ ${CMAKE_CURRENT_LIST_DIR}/drivers
+)
+
+
+# Copy the cmake components into projects
+# include(driver_power)
+# include(utilities_misc_utilities)
+# include(middleware_sdmmc_sdio)
+# include(CMSIS_Include_dsp)
+# include(middleware_sdmmc_osa_bm)
+# include(driver_mw_rtc)
+# include(middleware_lwip_apps_lwiperf)
+# include(middleware_mbedtls_port_mw)
+# include(component_lists)
+# include(middleware_sdmmc_common)
+# include(device_system)
+# include(middleware_lwip_apps_httpsrv)
+# include(driver_mw_pinmux)
+# include(driver_mw_uart)
+# include(device_startup)
+# include(driver_clock)
+# include(driver_mw_adc)
+# include(middleware_freertos-kernel_88MW320)
+# include(driver_mw_dac)
+# include(middleware_sdmmc_host_sdioc_freertos)
+# include(driver_mw_crc)
+# include(driver_mw_i2c)
+# include(middleware_sdmmc_host_sdioc)
+# include(middleware_wifi)
+# include(driver_mw_flashc)
+# include(driver_mw_dmac)
+# include(middleware_sdmmc_host_sdioc_interrupt)
+# include(driver_mw_sdioc)
+# include(driver_mw_gpt)
+# include(driver_mw_qspi)
+# include(driver_mw_ssp)
+# include(middleware_freertos-kernel_extension)
+# include(driver_mw_acomp)
+# include(driver_mw_i2c_dmac)
+# include(utility_debug_console)
+# include(device_CMSIS)
+# include(driver_mw_uart_dmac)
+# include(component_mw_uart_adapter)
+# include(component_mflash_file)
+# include(middleware_lwip)
+# include(component_osa_bm)
+# include(driver_mw_ssp_dmac)
+# include(CMSIS_Include_core_cm4)
+# include(middleware_wifi_cli)
+# include(CMSIS_Include_common)
+# include(driver_common)
+# include(component_mflash_common)
+# include(utility_assert)
+# include(component_mflash_mw320)
+# include(driver_mw_wdt)
+# include(middleware_sdmmc_osa_freertos)
+# include(component_osa_free_rtos)
+# include(driver_mw_gpio)
+# include(middleware_mbedtls)
+# include(component_boot2_psm)
+# include(component_serial_manager)
+# include(component_serial_manager_uart)
+# include(driver_mw_aes)
+# include(middleware_freertos-kernel_heap_4)
+# include(component_boot2_partition)
diff --git a/devices/88MW320/device_CMSIS.cmake b/devices/88MW320/device_CMSIS.cmake
new file mode 100644
index 000000000..e3a2a9c1c
--- /dev/null
+++ b/devices/88MW320/device_CMSIS.cmake
@@ -0,0 +1,13 @@
+#Description: device_CMSIS; user_visible: False
+include_guard(GLOBAL)
+message("device_CMSIS component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(CMSIS_Include_core_cm4)
diff --git a/devices/88MW320/device_startup.cmake b/devices/88MW320/device_startup.cmake
new file mode 100644
index 000000000..b214031ba
--- /dev/null
+++ b/devices/88MW320/device_startup.cmake
@@ -0,0 +1,13 @@
+#Description: device_startup; user_visible: False
+include_guard(GLOBAL)
+message("device_startup component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/gcc/startup_88MW320.S
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+)
+
+
+include(device_system)
diff --git a/devices/88MW320/device_system.cmake b/devices/88MW320/device_system.cmake
new file mode 100644
index 000000000..609ed2b3d
--- /dev/null
+++ b/devices/88MW320/device_system.cmake
@@ -0,0 +1,14 @@
+#Description: device_system; user_visible: False
+include_guard(GLOBAL)
+message("device_system component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/system_88MW320.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(device_CMSIS)
diff --git a/devices/88MW320/drivers/driver_clock.cmake b/devices/88MW320/drivers/driver_clock.cmake
new file mode 100644
index 000000000..348471f89
--- /dev/null
+++ b/devices/88MW320/drivers/driver_clock.cmake
@@ -0,0 +1,14 @@
+#Description: Clock Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_clock component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/devices/88MW320/drivers/driver_mw_pinmux.cmake b/devices/88MW320/drivers/driver_mw_pinmux.cmake
new file mode 100644
index 000000000..8a5b92de1
--- /dev/null
+++ b/devices/88MW320/drivers/driver_mw_pinmux.cmake
@@ -0,0 +1,14 @@
+#Description: MW_PINMUX Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_pinmux component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_pinmux.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/devices/88MW320/drivers/driver_power.cmake b/devices/88MW320/drivers/driver_power.cmake
new file mode 100644
index 000000000..b8bcf4632
--- /dev/null
+++ b/devices/88MW320/drivers/driver_power.cmake
@@ -0,0 +1,14 @@
+#Description: POWER Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_power component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_power.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/devices/88MW320/drivers/driver_reset.cmake b/devices/88MW320/drivers/driver_reset.cmake
new file mode 100644
index 000000000..49eb2cb9f
--- /dev/null
+++ b/devices/88MW320/drivers/driver_reset.cmake
@@ -0,0 +1,12 @@
+#Description: Reset Driver; user_visible: False
+include_guard(GLOBAL)
+message("driver_reset component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
diff --git a/devices/88MW320/drivers/fsl_clock.c b/devices/88MW320/drivers/fsl_clock.c
new file mode 100644
index 000000000..2d95dadb6
--- /dev/null
+++ b/devices/88MW320/drivers/fsl_clock.c
@@ -0,0 +1,1102 @@
+/*
+ * Copyright 2020, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_clock.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
+
+#define FRACT_BASE_NUM (4194304U)
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* External crystal MAINXTAL clock frequency. */
+volatile uint32_t g_mainXtalFreq;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Enable the clock for specific IP.
+ *
+ * @param name Which clock to enable, see \ref clock_ip_name_t.
+ */
+void CLOCK_EnableClock(clock_ip_name_t name)
+{
+ uint32_t pos = CLK_OP_POS(name);
+ uint32_t mask = CLK_OP_MASK(name);
+ uint32_t value = CLK_OP_VALUE(name);
+
+ CLK_OP_REG(name) = (CLK_OP_REG(name) & ~(mask << pos)) | (value << pos);
+}
+
+/*!
+ * @brief Disable the clock for specific IP.
+ *
+ * @param name Which clock to disable, see \ref clock_ip_name_t.
+ */
+void CLOCK_DisableClock(clock_ip_name_t name)
+{
+ uint32_t pos = CLK_OP_POS(name);
+ uint32_t mask = CLK_OP_MASK(name);
+ uint32_t value = (~CLK_OP_VALUE(name)) & mask;
+
+ CLK_OP_REG(name) = (CLK_OP_REG(name) & ~(mask << pos)) | (value << pos);
+}
+
+/**
+ * @brief Configure the clock selection muxes.
+ * @param connection : Clock to be configured.
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection)
+{
+ uint32_t pos = CLK_OP_POS(connection);
+ uint32_t mask = CLK_OP_MASK(connection);
+ uint32_t value = CLK_OP_VALUE(connection);
+
+ CLK_OP_REG(connection) = (CLK_OP_REG(connection) & ~(mask << pos)) | (value << pos);
+}
+
+/**
+ * @brief Setup clock dividers.
+ * @param name : Clock divider name
+ * @param divider : Value to be divided.
+ */
+void CLOCK_SetClkDiv(clock_div_name_t name, uint32_t divider)
+{
+ uint32_t pos = CLK_OP_POS(name);
+ uint32_t mask = CLK_OP_MASK(name);
+ uint32_t value = CLK_OP_VALUE(name);
+
+ if (value == 0U)
+ {
+ assert(divider <= mask);
+ CLK_OP_REG(name) = (CLK_OP_REG(name) & ~(mask << pos)) | (divider << pos);
+ }
+ else
+ {
+ /* Special case */
+ switch (name)
+ {
+ case kCLOCK_DivUartFast:
+ case kCLOCK_DivUartSlow:
+ assert(divider <= 0xFFFFFFU);
+ CLK_OP_REG(name) = divider;
+ break;
+ case kCLOCK_DivWdt:
+ assert(divider <= 0x3FU);
+ CLK_OP_REG(name) &= ~(PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3_MASK | PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2_MASK |
+ PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0_MASK);
+ CLK_OP_REG(name) |= ((divider >> 3U) << PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3_SHIFT) |
+ (((divider >> 2U) & 1U) << PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2_SHIFT) |
+ ((divider & 3U) << PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0_SHIFT);
+ break;
+ case kCLOCK_DivGpt3:
+ assert(divider <= 0x3FU);
+ CLK_OP_REG(name) &=
+ ~(PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3_MASK | PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0_MASK);
+ CLK_OP_REG(name) |= ((divider >> 3U) << PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3_SHIFT) |
+ ((divider & 7U) << PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0_SHIFT);
+ break;
+ default:
+ assert(false);
+ break;
+ }
+ }
+}
+
+/*!
+ * @brief Setup UART clock dividers.
+ *
+ * @param name : Clock divider name
+ * @param nom : Nominator for fraction divider.
+ * @param denom : Denominator for fraction divider.
+ */
+void CLOCK_SetUartClkDiv(clock_div_name_t name, uint32_t nom, uint32_t denom)
+{
+ assert(nom < (1UL << 13U));
+ assert(nom < (1UL << 11U));
+
+ CLOCK_SetClkDiv(name, (nom << PMU_UART_FAST_CLK_DIV_NOMINATOR_SHIFT) | denom);
+}
+
+/*!
+ * @brief Get the system clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetSysClkFreq(void)
+{
+ uint32_t src;
+ uint32_t freq;
+
+ src = PMU->CLK_SRC & PMU_CLK_SRC_SYS_CLK_SEL_MASK;
+
+ switch (src)
+ {
+ case (uint32_t)kCLOCK_SysClkSrcSFll:
+ freq = CLOCK_GetSFllFreq();
+ break;
+ case (uint32_t)kCLOCK_SysClkSrcRC32M_1:
+ case (uint32_t)kCLOCK_SysClkSrcRC32M_3:
+ freq = CLOCK_GetRC32MFreq();
+ break;
+ case (uint32_t)kCLOCK_SysClkSrcMainXtal:
+ freq = CLOCK_GetMainXtalFreq();
+ break;
+ default:
+ assert(false);
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/*!
+ * @brief Set the system clock source.
+ *
+ * This function sets the system clock source.
+ *
+ * @param src System clock source to set.
+ */
+void CLOCK_SetSysClkSource(clock_sys_clk_src_t src)
+{
+ uint32_t currSrc;
+ bool rc32mRdy;
+
+ currSrc = PMU->CLK_SRC & PMU_CLK_SRC_SYS_CLK_SEL_MASK;
+ rc32mRdy = (PMU->CLK_RDY & PMU_CLK_RDY_RC32M_RDY_MASK) != 0U;
+
+ switch (src)
+ {
+ case kCLOCK_SysClkSrcSFll:
+ if ((currSrc == (uint32_t)kCLOCK_SysClkSrcMainXtal) && rc32mRdy)
+ {
+ PMU->CLK_SRC =
+ (PMU->CLK_SRC & ~PMU_CLK_SRC_SYS_CLK_SEL_MASK) | PMU_CLK_SRC_SYS_CLK_SEL(kCLOCK_SysClkSrcRC32M_3);
+ currSrc = (uint32_t)kCLOCK_SysClkSrcRC32M_3;
+ }
+ if (currSrc == (uint32_t)kCLOCK_SysClkSrcRC32M_3)
+ {
+ PMU->CLK_SRC =
+ (PMU->CLK_SRC & ~PMU_CLK_SRC_SYS_CLK_SEL_MASK) | PMU_CLK_SRC_SYS_CLK_SEL(kCLOCK_SysClkSrcRC32M_1);
+ }
+ PMU->CLK_SRC =
+ (PMU->CLK_SRC & ~PMU_CLK_SRC_SYS_CLK_SEL_MASK) | PMU_CLK_SRC_SYS_CLK_SEL(kCLOCK_SysClkSrcSFll);
+ break;
+ case kCLOCK_SysClkSrcRC32M_1:
+ case kCLOCK_SysClkSrcRC32M_3:
+ if ((currSrc == (uint32_t)kCLOCK_SysClkSrcSFll) || (currSrc == (uint32_t)kCLOCK_SysClkSrcMainXtal))
+ {
+ PMU->CLK_SRC = (PMU->CLK_SRC & ~PMU_CLK_SRC_SYS_CLK_SEL_MASK) | PMU_CLK_SRC_SYS_CLK_SEL(currSrc + 1U);
+ }
+ break;
+ case kCLOCK_SysClkSrcMainXtal:
+ if ((currSrc == (uint32_t)kCLOCK_SysClkSrcSFll) && rc32mRdy)
+ {
+ PMU->CLK_SRC =
+ (PMU->CLK_SRC & ~PMU_CLK_SRC_SYS_CLK_SEL_MASK) | PMU_CLK_SRC_SYS_CLK_SEL(kCLOCK_SysClkSrcRC32M_1);
+ currSrc = (uint32_t)kCLOCK_SysClkSrcRC32M_1;
+ }
+ if (currSrc == (uint32_t)kCLOCK_SysClkSrcRC32M_1)
+ {
+ PMU->CLK_SRC =
+ (PMU->CLK_SRC & ~PMU_CLK_SRC_SYS_CLK_SEL_MASK) | PMU_CLK_SRC_SYS_CLK_SEL(kCLOCK_SysClkSrcRC32M_3);
+ }
+ PMU->CLK_SRC =
+ (PMU->CLK_SRC & ~PMU_CLK_SRC_SYS_CLK_SEL_MASK) | PMU_CLK_SRC_SYS_CLK_SEL(kCLOCK_SysClkSrcMainXtal);
+ break;
+ default:
+ assert(false);
+ break;
+ }
+}
+
+/*!
+ * @brief Enable the 32K XTAL.
+ *
+ * @param mode Internal or external OSC selection.
+ */
+void CLOCK_EnableXtal32K(clock_osc32k_mode_t mode)
+{
+ PMU->XTAL32K_CTRL =
+ (PMU->XTAL32K_CTRL & ~PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_MASK) | PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN(mode);
+ PMU->XTAL32K_CTRL |= PMU_XTAL32K_CTRL_X32K_EN_MASK;
+ while ((PMU->CLK_RDY & PMU_CLK_RDY_X32K_RDY_MASK) == 0U)
+ {
+ }
+}
+
+/*!
+ * @brief Disable the 32K XTAL output.
+ */
+void CLOCK_DisableXtal32K(void)
+{
+ PMU->XTAL32K_CTRL &= ~PMU_XTAL32K_CTRL_X32K_EN_MASK;
+}
+
+/*!
+ * @brief Enable the RC32M OSC.
+ *
+ * @param halfDiv half-divided reference clock. True for 16MHz and false for original 32MHz output.
+ */
+void CLOCK_EnableRC32M(bool halfDiv)
+{
+ RC32->CLK = (RC32->CLK & ~RC32_CLK_REF_SEL_MASK) | RC32_CLK_REF_SEL(halfDiv ? 0U : 1U);
+ RC32->CTRL &= ~RC32_CTRL_PD_MASK;
+ RC32->CTRL |= RC32_CTRL_EN_MASK;
+ while ((PMU->CLK_RDY & PMU_CLK_RDY_RC32M_RDY_MASK) == 0U)
+ {
+ }
+}
+
+/*!
+ * @brief Disable the RC32M OSC.
+ */
+void CLOCK_DisableRC32M(void)
+{
+ RC32->CTRL &= ~RC32_CTRL_EN_MASK;
+ RC32->CTRL |= RC32_CTRL_PD_MASK;
+}
+
+/*!
+ * @brief RC32M clock calibration function
+ *
+ * @param autoCal Calibration option, true for auto and false for manual
+ * @param manCalCode Select manual way, need input the calibration code
+ * @return return the calibration result
+ * -1, calibration failure
+ * else, internal calibration code
+ *
+ * @note Clock CLK_AUPLL_CAU must be ready before RC32M calibration
+ */
+int32_t CLOCK_CalibrateRC32M(bool autoCal, uint32_t manCalCode)
+{
+ volatile uint32_t localCnt;
+
+ /* Soft reset RC32M */
+ RC32->RST |= RC32_RST_SOFT_RST_MASK;
+
+ for (localCnt = 0U; localCnt < 10U; localCnt++)
+ {
+ __NOP();
+ }
+
+ RC32->RST &= ~RC32_RST_SOFT_RST_MASK;
+
+ /* Power up RC32M */
+ RC32->CTRL &= ~RC32_CTRL_PD_MASK;
+ RC32->CTRL |= RC32_CTRL_EN_MASK;
+
+ localCnt = 0U;
+ while (true)
+ {
+ /* Check RC32M_RDY status */
+ if ((PMU->CLK_RDY & PMU_CLK_RDY_RC32M_RDY_MASK) != 0U)
+ {
+ break;
+ }
+ else if (localCnt > 5000000U)
+ {
+ return -1;
+ }
+
+ localCnt++;
+ }
+
+ if (autoCal)
+ {
+ /* Auto */
+ RC32->CTRL &= ~RC32_CTRL_EXT_CODE_EN_MASK;
+ PMU->RC32M_CTRL |= PMU_RC32M_CTRL_CAL_ALLOW_MASK;
+ RC32->CTRL |= RC32_CTRL_CAL_EN_MASK;
+ }
+ else
+ {
+ /* Manual */
+ RC32->CTRL = (RC32->CTRL & ~RC32_CTRL_CODE_FR_EXT_MASK) | RC32_CTRL_CODE_FR_EXT(manCalCode);
+ RC32->CTRL |= RC32_CTRL_EXT_CODE_EN_MASK;
+ }
+
+ localCnt = 0;
+ while (true)
+ {
+ /* Check CAL_DONE status */
+ if (((RC32->STATUS & RC32_STATUS_CAL_DONE_MASK) != 0U) || ((RC32->CTRL & RC32_CTRL_EXT_CODE_EN_MASK) != 0U))
+ {
+ break;
+ }
+ else if (localCnt > 5000000U)
+ {
+ return -1;
+ }
+
+ localCnt++;
+ }
+
+ RC32->CTRL &= ~RC32_CTRL_CAL_EN_MASK;
+ PMU->RC32M_CTRL &= ~PMU_RC32M_CTRL_CAL_ALLOW_MASK;
+
+ return (int32_t)(uint32_t)((RC32->STATUS & RC32_STATUS_CODE_FR_CAL_MASK) >> RC32_STATUS_CODE_FR_CAL_SHIFT);
+}
+
+/*!
+ * @brief Enable the RC32K OSC.
+ */
+void CLOCK_EnableRC32K(void)
+{
+ PMU->RC32K_CTRL0 &= ~PMU_RC32K_CTRL0_RC32K_PD_MASK;
+ while ((PMU->RC32K_CTRL1 & PMU_RC32K_CTRL1_RC32K_RDY_MASK) == 0U)
+ {
+ }
+}
+
+/*!
+ * @brief Disable the RC32K OSC.
+ */
+void CLOCK_DisableRC32K(void)
+{
+ PMU->RC32K_CTRL0 |= PMU_RC32K_CTRL0_RC32K_PD_MASK;
+}
+
+/*!
+ * @brief RC32K clock calibration function
+ *
+ * @param autoCal Calibration option, true for auto and false for manual
+ * @param manCalCode Select manual way, need input the calibration code
+ * @return return the calibration result
+ * -1, calibration failure
+ * else, internal calibration code
+ *
+ * @note Clock CLK_XTAL32K must be ready before RC32K calibration
+ */
+int32_t CLOCK_CalibrateRC32K(bool autoCal, uint32_t manCalCode)
+{
+ volatile uint32_t localCnt;
+
+ /* Power up RC32K */
+ PMU->RC32K_CTRL0 &= ~PMU_RC32K_CTRL0_RC32K_PD_MASK;
+
+ localCnt = 0;
+ while (true)
+ {
+ /* Check RC32K_RDY and X32K_RDY status */
+ if (((PMU->RC32K_CTRL1 & PMU_RC32K_CTRL1_RC32K_RDY_MASK) != 0U) &&
+ ((PMU->CLK_RDY & PMU_CLK_RDY_X32K_RDY_MASK) != 0U))
+ {
+ break;
+ }
+ else if (localCnt > 5000000U)
+ {
+ return -1;
+ }
+
+ localCnt++;
+ }
+
+ if (autoCal)
+ {
+ PMU->RC32K_CTRL1 &= ~PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN_MASK;
+ PMU->RC32K_CTRL1 |= PMU_RC32K_CTRL1_RC32K_ALLOW_CAL_MASK;
+ }
+ else
+ {
+ PMU->RC32K_CTRL0 = (PMU->RC32K_CTRL0 & ~PMU_RC32K_CTRL0_RC32K_CODE_FR_EXT_MASK) |
+ PMU_RC32K_CTRL0_RC32K_CODE_FR_EXT(manCalCode);
+ PMU->RC32K_CTRL1 |= PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN_MASK;
+ }
+
+ /* Start Calibration */
+ PMU->RC32K_CTRL0 |= PMU_RC32K_CTRL0_RC32K_CAL_EN_MASK;
+
+ /* Add a short delay to prevent auto cal fail */
+ localCnt = 0;
+ while (true)
+ {
+ if (((PMU->RC32K_CTRL1 & PMU_RC32K_CTRL1_RC32K_CAL_DONE_MASK) == 0U) ||
+ ((PMU->RC32K_CTRL1 & PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN_MASK) != 0U))
+ {
+ break;
+ }
+ else if (localCnt > 50000U)
+ {
+ break;
+ }
+ localCnt++;
+ }
+
+ localCnt = 0U;
+ while (true)
+ {
+ /* Check CAL_DONE status */
+ if (((PMU->RC32K_CTRL1 & PMU_RC32K_CTRL1_RC32K_CAL_DONE_MASK) != 0U) ||
+ ((PMU->RC32K_CTRL1 & PMU_RC32K_CTRL1_RC32K_EXT_CODE_EN_MASK) != 0U))
+ {
+ break;
+ }
+ else if (localCnt > 5000000U)
+ {
+ return -1;
+ }
+ localCnt++;
+ }
+
+ localCnt = 0;
+ while (localCnt <= 0x1000U)
+ {
+ localCnt++;
+ }
+
+ PMU->RC32K_CTRL0 &= ~PMU_RC32K_CTRL0_RC32K_CAL_EN_MASK;
+ PMU->RC32K_CTRL1 &= ~PMU_RC32K_CTRL1_RC32K_ALLOW_CAL_MASK;
+
+ return (int32_t)(uint32_t)((PMU->RC32K_CTRL1 & PMU_RC32K_CTRL1_RC32K_CODE_FR_CAL_MASK) >>
+ PMU_RC32K_CTRL1_RC32K_CODE_FR_CAL_SHIFT);
+}
+
+/*!
+ * @brief Enable the REFCLK for SYS/AUD/USB reference.
+ *
+ * @param refclks Or'ed value to select SYS/AUD/USB REFCLK to disable. See \ref clock_refclk_t.
+ */
+void CLOCK_EnableRefClk(uint32_t refclks)
+{
+ assert((refclks & ~((uint32_t)kCLOCK_RefClk_ALL)) == 0U);
+
+ /* Ensure WLAN is powered on */
+ PMU->WLAN_CTRL |= PMU_WLAN_CTRL_PD_MASK;
+ /* Enable reference clock request */
+ PMU->WLAN_CTRL |= refclks;
+ /* Wait reference clock ready */
+ while ((PMU->WLAN_CTRL & (refclks << 3U)) != (refclks << 3U))
+ {
+ }
+}
+
+/*!
+ * @brief Disable the REFCLK for SYS/AUD/USB reference.
+ *
+ * @param refclks Or'ed value to select SYS/AUD/USB REFCLK to disable. See \ref clock_refclk_t.
+ */
+void CLOCK_DisableRefClk(uint32_t refclks)
+{
+ assert((refclks & ~((uint32_t)kCLOCK_RefClk_ALL)) == 0U);
+
+ /* Disable reference clock request */
+ PMU->WLAN_CTRL &= ~refclks;
+}
+
+/*! @brief Initialize the SFLL.
+ * @param config : Configuration to set to SFLL.
+ */
+void CLOCK_InitSFll(const clock_sfll_config_t *config)
+{
+ assert(config);
+
+ /* Accepted sfll reference divider is 2~511 */
+ assert((config->refDiv >= 2U) && (config->refDiv <= 511U));
+
+ /* Accepted sfll feedback divider is 1~511 */
+ assert((config->fbDiv >= 1U) && (config->fbDiv <= 511U));
+
+ /* Accepted sfll kvco is 0~3 */
+ assert(config->kvco <= 3U);
+
+ /* Accepted sfll postdiv is 0~3 */
+ assert(config->postDiv <= 3U);
+
+ PMU->SFLL_CTRL0 = (PMU->SFLL_CTRL0 & ~(PMU_SFLL_CTRL0_SFLL_FBDIV_MASK | PMU_SFLL_CTRL0_SFLL_KVCO_MASK |
+ PMU_SFLL_CTRL0_SFLL_REFCLK_SEL_MASK)) |
+ PMU_SFLL_CTRL0_SFLL_FBDIV(config->fbDiv) | PMU_SFLL_CTRL0_SFLL_KVCO(config->kvco) |
+ PMU_SFLL_CTRL0_SFLL_REFCLK_SEL(config->sfllSrc);
+ PMU->SFLL_CTRL1 = (PMU->SFLL_CTRL1 & ~(PMU_SFLL_CTRL1_SFLL_REFDIV_MASK | PMU_SFLL_CTRL1_SFLL_DIV_SEL_MASK)) |
+ PMU_SFLL_CTRL1_SFLL_REFDIV(config->refDiv) | PMU_SFLL_CTRL1_SFLL_DIV_SEL(config->postDiv);
+
+ /* Power up */
+ PMU->SFLL_CTRL0 |= PMU_SFLL_CTRL0_SFLL_PU_MASK;
+
+ /* Wait PLL ready */
+ while ((PMU->CLK_RDY & PMU_CLK_RDY_PLL_CLK_RDY_MASK) == 0U)
+ {
+ }
+}
+
+/*! @brief Deinit the SFLL.
+ */
+void CLOCK_DeinitSFll(void)
+{
+ /* Power down */
+ PMU->SFLL_CTRL0 &= ~PMU_SFLL_CTRL0_SFLL_PU_MASK;
+}
+
+/*! @brief Initialize the AUPLL.
+ * @param config : Configuration to set to AUPLL.
+ */
+void CLOCK_InitAuPll(const clock_aupll_config_t *config)
+{
+ assert(config);
+ /* check the parameters */
+
+ /* Accepted aupll reference divider is 3~10 */
+ assert((config->refDiv >= 3U) && (config->refDiv <= 10U));
+
+ /* Accepted aupll feedback divider is 27, 29, 31 ~ 36, 38, 39, 42, 46 */
+ assert(((config->fbDiv >= 27U) && (config->fbDiv <= 39U) && (config->fbDiv != 28U) && (config->fbDiv != 30U) &&
+ (config->fbDiv != 37U)) ||
+ (config->fbDiv == 42U) || (config->fbDiv == 46U));
+
+ /* Accepted aupll icp is 0~3 */
+ assert(config->icp <= 3U);
+
+ /* Accepted AUPLL_POSTDIV_PATTERN is 0~2 */
+ assert(config->postDivPattern <= 2U);
+
+ /* Accepted AUPLL_POSTDIV_MODULO is 0 ~ 2, 4, 7 */
+ assert(((config->postDivModulo <= 4U) && (config->postDivModulo != 3U)) || (config->postDivModulo == 7U));
+
+ PMU->AUPLL_CTRL1 = (PMU->AUPLL_CTRL1 & ~(PMU_AUPLL_CTRL1_DIV_MCLK_MASK | PMU_AUPLL_CTRL1_DIV_FBCCLK_MASK |
+ PMU_AUPLL_CTRL1_ICP_MASK | PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN_MASK |
+ PMU_AUPLL_CTRL1_DIV_OCLK_MODULO_MASK | PMU_AUPLL_CTRL1_ENA_DITHER_MASK |
+ PMU_AUPLL_CTRL1_EN_VCOX2_MASK | PMU_AUPLL_CTRL1_REFCLK_SEL_MASK)) |
+ PMU_AUPLL_CTRL1_DIV_MCLK(config->refDiv) | PMU_AUPLL_CTRL1_DIV_FBCCLK(config->fbDiv) |
+ PMU_AUPLL_CTRL1_ICP(config->icp) | PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN(config->postDivPattern) |
+ PMU_AUPLL_CTRL1_DIV_OCLK_MODULO(config->postDivModulo) |
+ PMU_AUPLL_CTRL1_ENA_DITHER(config->enaDither) | PMU_AUPLL_CTRL1_EN_VCOX2(config->enaVcoClkX2) |
+ PMU_AUPLL_CTRL1_REFCLK_SEL(config->aupllSrc);
+
+ PMU->AUPLL_CTRL0 = (PMU->AUPLL_CTRL0 & ~PMU_AUPLL_CTRL0_FRACT_MASK) | PMU_AUPLL_CTRL0_FRACT(config->fract);
+
+ /* Power up */
+ PMU->AUPLL_CTRL0 |= PMU_AUPLL_CTRL0_PU_MASK;
+}
+
+/*! @brief Deinit the AUPLL.
+ */
+void CLOCK_DeinitAuPll(void)
+{
+ /* Power down */
+ PMU->AUPLL_CTRL0 &= ~PMU_AUPLL_CTRL0_PU_MASK;
+}
+
+/*! @brief Update the AUPLL post divider
+ */
+void CLOCK_UpdateAupllPostDiv(uint8_t postDivPattern, uint8_t postDivModulo)
+{
+ /* Accepted AUPLL_POSTDIV_PATTERN is 0~2 */
+ assert(postDivPattern <= 2U);
+
+ /* Accepted AUPLL_POSTDIV_MODULO is 0 ~ 2, 4, 7 */
+ assert(((postDivModulo <= 4U) && (postDivModulo != 3U)) || (postDivModulo == 7U));
+
+ PMU->AUPLL_CTRL1 =
+ (PMU->AUPLL_CTRL1 & ~(PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN_MASK | PMU_AUPLL_CTRL1_DIV_OCLK_MODULO_MASK)) |
+ PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN(postDivPattern) | PMU_AUPLL_CTRL1_DIV_OCLK_MODULO(postDivModulo);
+}
+
+/*! @brief Return Frequency of MAIN XTAL Clock
+ * @return Frequency of MAIN XTAL Clock.
+ */
+uint32_t CLOCK_GetMainXtalFreq(void)
+{
+ uint32_t freq;
+
+ if ((PMU->WLAN_CTRL & PMU_WLAN_CTRL_REFCLK_SYS_RDY_MASK) == 0U)
+ {
+ freq = 0U;
+ }
+ else
+ {
+ freq = g_mainXtalFreq;
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of REFCLK_AUD Clock
+ * @return Frequency of REFCLK_AUD Clock.
+ */
+uint32_t CLOCK_GetRefClkAudFreq(void)
+{
+ uint32_t freq;
+
+ if ((PMU->WLAN_CTRL & PMU_WLAN_CTRL_REFCLK_AUD_RDY_MASK) == 0U)
+ {
+ freq = 0U;
+ }
+ else
+ {
+ freq = g_mainXtalFreq;
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of RC32M Clock
+ * @return Frequency of RC32M Clock.
+ */
+uint32_t CLOCK_GetRC32MFreq(void)
+{
+ uint32_t freq;
+
+ if ((PMU->CLK_RDY & PMU_CLK_RDY_RC32M_RDY_MASK) == 0U)
+ {
+ freq = 0U;
+ }
+ else
+ {
+ freq = ((RC32->CLK & RC32_CLK_REF_SEL_MASK) == 0U) ? (CLK_RC32M_CLK / 2U) : CLK_RC32M_CLK;
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of XTAL32K Clock
+ * @return Frequency of XTAL32K Clock.
+ */
+uint32_t CLOCK_GetXtal32KFreq(void)
+{
+ uint32_t freq;
+
+ if ((PMU->CLK_RDY & PMU_CLK_RDY_X32K_RDY_MASK) == 0U)
+ {
+ freq = 0U;
+ }
+ else
+ {
+ freq = ((PMU->XTAL32K_CTRL & PMU_XTAL32K_CTRL_X32K_EXT_OSC_EN_MASK) == 0U) ? CLOCK_GetRC32KFreq() :
+ CLK_XTAL32K_CLK;
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of RC32K Clock
+ * @return Frequency of RC32K Clock.
+ */
+uint32_t CLOCK_GetRC32KFreq(void)
+{
+ uint32_t freq;
+
+ if ((PMU->RC32K_CTRL1 & PMU_RC32K_CTRL1_RC32K_RDY_MASK) == 0U)
+ {
+ freq = 0U;
+ }
+ else
+ {
+ freq = CLK_RC32K_CLK;
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of SFLL Clock
+ * @return Frequency of SFLL Clock.
+ */
+uint32_t CLOCK_GetSFllFreq(void)
+{
+ uint32_t pllSrcFreq;
+ uint64_t freq;
+
+ if ((PMU->CLK_RDY & PMU_CLK_RDY_PLL_CLK_RDY_MASK) == 0U)
+ {
+ freq = 0U;
+ }
+ else
+ {
+ pllSrcFreq = ((PMU->SFLL_CTRL0 & PMU_SFLL_CTRL0_SFLL_REFCLK_SEL_MASK) == 0U) ? CLOCK_GetRC32MFreq() :
+ CLOCK_GetMainXtalFreq();
+
+ freq = (uint64_t)pllSrcFreq *
+ ((PMU->SFLL_CTRL0 & PMU_SFLL_CTRL0_SFLL_FBDIV_MASK) >> PMU_SFLL_CTRL0_SFLL_FBDIV_SHIFT) * 2U;
+ freq >>= ((PMU->SFLL_CTRL1 & PMU_SFLL_CTRL1_SFLL_DIV_SEL_MASK) >> PMU_SFLL_CTRL1_SFLL_DIV_SEL_SHIFT);
+ freq /= ((PMU->SFLL_CTRL1 & PMU_SFLL_CTRL1_SFLL_REFDIV_MASK) >> PMU_SFLL_CTRL1_SFLL_REFDIV_SHIFT);
+ }
+
+ return (uint32_t)freq;
+}
+
+static uint32_t CLOCK_GetAuPllPostDiv(void)
+{
+ uint32_t mod = (PMU->AUPLL_CTRL1 & PMU_AUPLL_CTRL1_DIV_OCLK_MODULO_MASK) >> PMU_AUPLL_CTRL1_DIV_OCLK_MODULO_SHIFT;
+ uint32_t pat = (PMU->AUPLL_CTRL1 & PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN_MASK) >> PMU_AUPLL_CTRL1_DIV_OCLK_PATTERN_SHIFT;
+ uint32_t code = (mod << 4U) | pat;
+ uint32_t div;
+
+ switch (code)
+ {
+ case 0x30U:
+ div = 1U;
+ break;
+ case 0x50U:
+ div = 2U;
+ break;
+ case 0x00U:
+ div = 4U;
+ break;
+ case 0x11U:
+ div = 6U;
+ break;
+ case 0x10U:
+ div = 8U;
+ break;
+ case 0x12U:
+ div = 9U;
+ break;
+ case 0x21U:
+ div = 12U;
+ break;
+ case 0x20U:
+ div = 16U;
+ break;
+ case 0x22U:
+ div = 18U;
+ break;
+ case 0x41U:
+ div = 24U;
+ break;
+ case 0x42U:
+ div = 36U;
+ break;
+ case 0x61U:
+ div = 48U;
+ break;
+ case 0x62U:
+ div = 72U;
+ break;
+ default:
+ assert(false); /* Wrong post divider value */
+ div = 1U;
+ break;
+ }
+
+ return div;
+}
+
+/*! @brief Return Frequency of AUPLL Clock
+ * @return Frequency of AUPLL Clock.
+ */
+uint32_t CLOCK_GetAuPllFreq(void)
+{
+ uint32_t pllSrcFreq;
+ uint64_t freq;
+
+ if ((PMU->CLK_RDY & PMU_CLK_RDY_PLL_AUDIO_RDY_MASK) == 0U)
+ {
+ freq = 0U;
+ }
+ else
+ {
+ pllSrcFreq = ((PMU->AUPLL_CTRL1 & PMU_AUPLL_CTRL1_REFCLK_SEL_MASK) == 0U) ? CLOCK_GetRC32MFreq() :
+ CLOCK_GetRefClkAudFreq();
+
+ freq = pllSrcFreq / ((PMU->AUPLL_CTRL1 & PMU_AUPLL_CTRL1_DIV_MCLK_MASK) >> PMU_AUPLL_CTRL1_DIV_MCLK_SHIFT);
+ freq *=
+ ((PMU->AUPLL_CTRL1 & PMU_AUPLL_CTRL1_DIV_FBCCLK_MASK) >> PMU_AUPLL_CTRL1_DIV_FBCCLK_SHIFT) * FRACT_BASE_NUM;
+ freq /= (FRACT_BASE_NUM - ((PMU->AUPLL_CTRL0 & PMU_AUPLL_CTRL0_FRACT_MASK) >> PMU_AUPLL_CTRL0_FRACT_SHIFT));
+ freq /= CLOCK_GetAuPllPostDiv();
+ }
+
+ return (uint32_t)freq;
+}
+
+/*! @brief Return Frequency of M4/AHB Clock
+ * @return Frequency of M4/AHB Clock.
+ */
+uint32_t CLOCK_GetCoreBusFreq(void)
+{
+ uint32_t freq = CLOCK_GetSysClkFreq();
+ uint32_t div = (PMU->MCU_CORE_CLK_DIV & PMU_MCU_CORE_CLK_DIV_FCLK_DIV_MASK) >> PMU_MCU_CORE_CLK_DIV_FCLK_DIV_SHIFT;
+
+ div = div == 0U ? 1U : div;
+
+ return freq / div;
+}
+
+/*! @brief Return Frequency of APB Clock
+ *
+ * @param instance APB instance 0-1.
+ * @return Frequency of APB Clock.
+ */
+uint32_t CLOCK_GetApbFreq(uint32_t instance)
+{
+ uint32_t freq = CLOCK_GetSysClkFreq();
+ uint32_t div;
+
+ assert(instance <= 1U);
+
+ div = (PMU->AON_CLK_CTRL & PMU_AON_CLK_CTRL_APB0_CLK_DIV_MASK << (2U * instance)) >>
+ (PMU_AON_CLK_CTRL_APB0_CLK_DIV_SHIFT + 2U * instance);
+
+ return freq >> div;
+}
+
+/*! @brief Return Frequency of UART Clock
+ *
+ * @param instance UART instance 0-2.
+ * @return Frequency of UART Clock.
+ */
+uint32_t CLOCK_GetUartClkFreq(uint32_t instance)
+{
+ uint32_t freq = CLOCK_GetSysClkFreq();
+ uint32_t sel;
+ uint32_t nom, denom;
+
+ assert(instance <= 2U);
+
+ sel = PMU->UART_CLK_SEL & (PMU_UART_CLK_SEL_UART0_CLK_SEL_MASK << instance);
+
+ if (sel == 0U) /* Slow */
+ {
+ nom = (PMU->UART_SLOW_CLK_DIV & PMU_UART_SLOW_CLK_DIV_NOMINATOR_MASK) >> PMU_UART_SLOW_CLK_DIV_NOMINATOR_SHIFT;
+ denom = (PMU->UART_SLOW_CLK_DIV & PMU_UART_SLOW_CLK_DIV_DENOMINATOR_MASK) >>
+ PMU_UART_SLOW_CLK_DIV_DENOMINATOR_SHIFT;
+ }
+ else /* Fast */
+ {
+ nom = (PMU->UART_FAST_CLK_DIV & PMU_UART_FAST_CLK_DIV_NOMINATOR_MASK) >> PMU_UART_FAST_CLK_DIV_NOMINATOR_SHIFT;
+ denom = (PMU->UART_FAST_CLK_DIV & PMU_UART_FAST_CLK_DIV_DENOMINATOR_MASK) >>
+ PMU_UART_FAST_CLK_DIV_DENOMINATOR_SHIFT;
+ }
+
+ assert(nom != 0U);
+
+ return (uint32_t)((uint64_t)freq * denom / nom);
+}
+
+/*! @brief Return Frequency of GPT Clock
+ *
+ * @param instance GPT instance 0-3.
+ * @return Frequency of GPT Clock.
+ */
+uint32_t CLOCK_GetGptClkFreq(uint32_t instance)
+{
+ uint32_t freq;
+ uint32_t reg;
+ uint32_t sel;
+ uint32_t div;
+
+ assert(instance <= 3U);
+
+ switch (instance)
+ {
+ case 0:
+ reg = PMU->GPT0_CTRL;
+ div = (reg & PMU_GPT0_CTRL_GPT0_CLK_DIV_MASK) >> PMU_GPT0_CTRL_GPT0_CLK_DIV_SHIFT;
+ break;
+ case 1:
+ reg = PMU->GPT1_CTRL;
+ div = (reg & PMU_GPT0_CTRL_GPT0_CLK_DIV_MASK) >> PMU_GPT0_CTRL_GPT0_CLK_DIV_SHIFT;
+ break;
+ case 2:
+ reg = PMU->GPT2_CTRL;
+ div = (reg & PMU_GPT0_CTRL_GPT0_CLK_DIV_MASK) >> PMU_GPT0_CTRL_GPT0_CLK_DIV_SHIFT;
+ break;
+ default:
+ reg = PMU->GPT3_CTRL;
+ div = (((PMU->PERI2_CLK_DIV & PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3_MASK) >>
+ PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_5_3_SHIFT)
+ << 3U) |
+ ((PMU->PERI2_CLK_DIV & PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0_MASK) >>
+ PMU_PERI2_CLK_DIV_GPT3_CLK_DIV_2_0_SHIFT);
+ break;
+ }
+
+ sel = (reg & (PMU_GPT0_CTRL_GPT0_CLK_SEL0_MASK | PMU_GPT0_CTRL_GPT0_CLK_SEL1_MASK)) >>
+ PMU_GPT0_CTRL_GPT0_CLK_SEL1_SHIFT;
+ div = div == 0U ? 1U : div;
+
+ switch (sel)
+ {
+ case 0x0:
+ freq = CLOCK_GetSysClkFreq() / div;
+ break;
+ case 0x2:
+ freq = CLOCK_GetRC32KFreq();
+ break;
+ case 0x3:
+ freq = CLOCK_GetXtal32KFreq();
+ break;
+ case 0x8:
+ freq = CLOCK_GetRC32MFreq() / div;
+ break;
+ case 0xC:
+ freq = CLOCK_GetMainXtalFreq() / div;
+ break;
+ default:
+ assert(false);
+ freq = 0U;
+ break;
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of GPT Sample Clock
+ *
+ * @return Frequency of GPT Sample Clock.
+ */
+uint32_t CLOCK_GetGptSampleClkFreq(void)
+{
+ uint32_t freq = CLOCK_GetSysClkFreq();
+ uint32_t div =
+ (PMU->PERI2_CLK_DIV & PMU_PERI2_CLK_DIV_GPT_SAMPLE_CLK_DIV_MASK) >> PMU_PERI2_CLK_DIV_GPT_SAMPLE_CLK_DIV_SHIFT;
+
+ div = div == 0U ? 1U : div;
+
+ return freq / div;
+}
+
+/*! @brief Return Frequency of SSP Clock
+ *
+ * @param instance SSP instance 0-2.
+ * @return Frequency of SSP Clock.
+ */
+uint32_t CLOCK_GetSspClkFreq(uint32_t instance)
+{
+ uint32_t freq;
+ uint32_t sel;
+ uint32_t div;
+
+ assert(instance <= 2U);
+
+ sel = PMU->PERI_CLK_SRC & (PMU_PERI_CLK_SRC_SSP0_AUDIO_SEL_MASK << instance);
+ if (sel == 0U)
+ {
+ freq = CLOCK_GetSysClkFreq();
+ }
+ else
+ {
+ freq = CLOCK_GetAuPllFreq();
+ }
+
+ div = (PMU->PERI0_CLK_DIV & (PMU_PERI0_CLK_DIV_SSP0_CLK_DIV_MASK << (5U * instance))) >> (5U * instance);
+ div = div == 0U ? 1U : div;
+
+ return freq / div;
+}
+
+/*! @brief Return Frequency of GAU Clock
+ * @return Frequency of GAU Clock.
+ */
+uint32_t CLOCK_GetGauClkFreq(void)
+{
+ uint32_t freq;
+ uint32_t div;
+
+ freq = CLOCK_GetAuPllFreq();
+
+ div = (PMU->PERI3_CTRL & PMU_PERI3_CTRL_GAU_DIV_MASK) >> PMU_PERI3_CTRL_GAU_DIV_SHIFT;
+ div = div == 0U ? 1U : div;
+
+ return freq / div;
+}
+
+/*! @brief Return Frequency of RTC Clock
+ * @return Frequency of RTC Clock.
+ */
+uint32_t CLOCK_GetRtcClkFreq(void)
+{
+ uint32_t freq;
+
+ if ((PMU->AON_CLK_CTRL & PMU_AON_CLK_CTRL_RTC_INT_SEL_MASK) == 0U)
+ {
+ freq = CLOCK_GetRC32KFreq();
+ }
+ else
+ {
+ freq = CLOCK_GetXtal32KFreq();
+ }
+
+ return freq;
+}
+
+/*! @brief Return Frequency of I2C Clock
+ * @return Frequency of I2C Clock.
+ */
+uint32_t CLOCK_GetI2cClkFreq(void)
+{
+ uint32_t freq = CLOCK_GetSysClkFreq();
+ uint32_t div = (PMU->PERI2_CLK_DIV & PMU_PERI2_CLK_DIV_I2C_CLK_DIV_MASK) >> PMU_PERI2_CLK_DIV_I2C_CLK_DIV_SHIFT;
+
+ div = div == 0U ? 1U : div;
+
+ return freq / div;
+}
+
+/*! @brief Return Frequency of QSPI Clock
+ * @return Frequency of QSPI Clock.
+ */
+uint32_t CLOCK_GetQspiClkFreq(void)
+{
+ uint32_t freq = CLOCK_GetSysClkFreq();
+ uint32_t div = (PMU->PERI1_CLK_DIV & (7UL << 8U)) >> 8U;
+
+ div = div == 0U ? 1U : div;
+
+ return freq / div;
+}
+
+/*! @brief Return Frequency of FlashC Clock
+ * @return Frequency of FlashC Clock.
+ */
+uint32_t CLOCK_GetFlashCClkFreq(void)
+{
+ uint32_t freq = CLOCK_GetSysClkFreq();
+ uint32_t div = (PMU->PERI1_CLK_DIV & PMU_PERI1_CLK_DIV_FLASH_CLK_DIV_MASK) >> PMU_PERI1_CLK_DIV_FLASH_CLK_DIV_SHIFT;
+
+ div = div == 0U ? 1U : div;
+
+ return freq / div;
+}
+
+/*! @brief Return Frequency of WDT Clock
+ * @return Frequency of WDT Clock.
+ */
+uint32_t CLOCK_GetWdtClkFreq(void)
+{
+ uint32_t freq = CLOCK_GetApbFreq(1U);
+ uint32_t div22 =
+ (PMU->PERI2_CLK_DIV & PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2_MASK) >> PMU_PERI2_CLK_DIV_WDT_CLK_DIV_2_2_SHIFT;
+ uint32_t div10 =
+ (PMU->PERI2_CLK_DIV & PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0_MASK) >> PMU_PERI2_CLK_DIV_WDT_CLK_DIV_1_0_SHIFT;
+ uint32_t div53 =
+ (PMU->PERI2_CLK_DIV & PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3_MASK) >> PMU_PERI2_CLK_DIV_WDT_CLK_DIV_5_3_SHIFT;
+ uint32_t div;
+
+ div = (div53 << 3U) | (div22 << 2U) | div10;
+
+ return freq >> div;
+}
+
+/*! @brief Return Frequency of SDIO Clock
+ * @return Frequency of SDIO Clock.
+ */
+uint32_t CLOCK_GetSdioClkFreq(void)
+{
+ uint32_t freq;
+ uint32_t div;
+
+ freq = CLOCK_GetSysClkFreq();
+
+ div = (PMU->PERI0_CLK_DIV & (0xFUL << 16U)) >> 16U;
+ div = div == 0U ? 1U : div;
+
+ return freq / div;
+}
diff --git a/devices/88MW320/drivers/fsl_clock.h b/devices/88MW320/drivers/fsl_clock.h
new file mode 100644
index 000000000..2b36a8b3b
--- /dev/null
+++ b/devices/88MW320/drivers/fsl_clock.h
@@ -0,0 +1,651 @@
+/*
+ * Copyright 2020, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CLOCK_H_
+#define _FSL_CLOCK_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup clock */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Configurations
+ ******************************************************************************/
+
+/*! @brief Configure whether driver controls clock
+ *
+ * When set to 0, peripheral drivers will enable clock in initialize function
+ * and disable clock in de-initialize function. When set to 1, peripheral
+ * driver will not control the clock, application could control the clock out of
+ * the driver.
+ *
+ * @note All drivers share this feature switcher. If it is set to 1, application
+ * should handle clock enable and disable for all drivers.
+ */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
+#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.0.1. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief External crystal MAINXTAL clock frequency.
+ *
+ * The MAINXTAL clock frequency in Hz. When the clock is set up, use the
+ * function CLOCK_SetMainXtalFreq to set the value in the clock driver. For example,
+ * if MAINXTAL is 38.4 MHz:
+ * @code
+ * CLOCK_SetMainXtalFreq(384000000);
+ * @endcode
+ */
+extern volatile uint32_t g_mainXtalFreq;
+
+/* Definition for delay API in clock driver, users can redefine it to the real application. */
+#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
+#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (200000000UL)
+#endif
+
+/*! @brief Clock ip name array for GPIO. */
+#define GPIO_CLOCKS \
+ { \
+ kCLOCK_Gpio \
+ }
+
+/*! @brief Clock ip name array for I2C. */
+#define I2C_CLOCKS \
+ { \
+ kCLOCK_I2c0, kCLOCK_I2c1 \
+ }
+
+/*! @brief Clock ip name array for QSPI. */
+#define QSPI_CLOCKS \
+ { \
+ kCLOCK_Qspi \
+ }
+
+/*! @brief Clock ip name array for UART. */
+#define UART_CLOCKS \
+ { \
+ kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \
+ }
+
+/*! @brief Clock ip name array for SSP. */
+#define SSP_CLOCKS \
+ { \
+ kCLOCK_Ssp0, kCLOCK_Ssp1, kCLOCK_Ssp2 \
+ }
+
+/*! @brief Clock ip name array for GPT. */
+#define GPT_CLOCKS \
+ { \
+ kCLOCK_Gpt0, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3 \
+ }
+
+/*! @brief Clock ip name array for WDT. */
+#define WDT_CLOCKS \
+ { \
+ kCLOCK_Wdt \
+ }
+
+/*! @brief Clock ip name array for RTC. */
+#define RTC_CLOCKS \
+ { \
+ kCLOCK_Rtc \
+ }
+
+/*! @brief Clock ip name array for ACOMP. */
+#define ACOMP_CLOCKS \
+ { \
+ kCLOCK_AcompMclk \
+ }
+
+/*! @brief Clock ip name array for ADC. */
+#define ADC_CLOCKS \
+ { \
+ kCLOCK_AdcMclk \
+ }
+
+/*! @brief Clock ip name array for DAC. */
+#define DAC_CLOCKS \
+ { \
+ kCLOCK_DacMclk \
+ }
+
+/*! @brief Clock ip name array for DMAC. */
+#define DMAC_CLOCKS \
+ { \
+ kCLOCK_Dma \
+ }
+
+/*! @brief Clock operation code.
+ * [31:16] Register offset from PMU base.
+ * [15:11] Register bit position.
+ * [10: 8] Register bits width to operate.
+ * [ 7: 0] Value to set to the bits.
+ */
+#define CLK_OP_CODE_DEFINE(regOff, bitPos, bitWid, val) \
+ (((regOff) << 16U) | ((bitPos) << 11U) | ((bitWid) << 8U) | (val))
+#define CLK_OP_REG(code) (*((volatile uint32_t *)(PMU_BASE + (((uint32_t)(code)) >> 16U))))
+#define CLK_OP_POS(code) ((((uint32_t)(code)) >> 11U) & 0x1FU)
+#define CLK_OP_MASK(code) ((1UL << ((((uint32_t)(code)) >> 8U) & 0x7U)) - 1U)
+#define CLK_OP_VALUE(code) (((uint32_t)(code)) & 0xFFU)
+
+/*!
+ * @brief Peripheral clock name difinition used for
+ * clock gate.
+ */
+typedef enum _clock_ip_name
+{
+ kCLOCK_IpInvalid = 0U,
+
+ kCLOCK_Qspi = CLK_OP_CODE_DEFINE(0x7CU, 1U, 1U, 0U),
+ kCLOCK_Gpio = CLK_OP_CODE_DEFINE(0x7CU, 4U, 1U, 0U),
+ kCLOCK_Uart0 = CLK_OP_CODE_DEFINE(0x7CU, 5U, 1U, 0U),
+ kCLOCK_Uart1 = CLK_OP_CODE_DEFINE(0x7CU, 6U, 1U, 0U),
+ kCLOCK_Uart2 = CLK_OP_CODE_DEFINE(0x7CU, 15U, 1U, 0U),
+ kCLOCK_I2c0 = CLK_OP_CODE_DEFINE(0x7CU, 7U, 1U, 0U),
+ kCLOCK_I2c1 = CLK_OP_CODE_DEFINE(0x7CU, 19U, 1U, 0U),
+ kCLOCK_I2c2 = CLK_OP_CODE_DEFINE(0x7CU, 20U, 1U, 0U),
+ kCLOCK_Ssp0 = CLK_OP_CODE_DEFINE(0x7CU, 8U, 1U, 0U),
+ kCLOCK_Ssp1 = CLK_OP_CODE_DEFINE(0x7CU, 9U, 1U, 0U),
+ kCLOCK_Ssp2 = CLK_OP_CODE_DEFINE(0x7CU, 17U, 1U, 0U),
+ kCLOCK_Gpt0 = CLK_OP_CODE_DEFINE(0x7CU, 10U, 1U, 0U),
+ kCLOCK_Gpt1 = CLK_OP_CODE_DEFINE(0x7CU, 11U, 1U, 0U),
+ kCLOCK_Gpt2 = CLK_OP_CODE_DEFINE(0x7CU, 21U, 1U, 0U),
+ kCLOCK_Gpt3 = CLK_OP_CODE_DEFINE(0x7CU, 22U, 1U, 0U),
+ kCLOCK_Wdt = CLK_OP_CODE_DEFINE(0x7CU, 23U, 1U, 0U),
+ kCLOCK_Sdio = CLK_OP_CODE_DEFINE(0x7CU, 25U, 1U, 0U),
+ kCLOCK_SdioAhb = CLK_OP_CODE_DEFINE(0x7CU, 31U, 1U, 0U),
+ kCLOCK_Usbc = CLK_OP_CODE_DEFINE(0x7CU, 27U, 1U, 0U),
+ kCLOCK_UsbcAhb = CLK_OP_CODE_DEFINE(0x7CU, 30U, 1U, 0U),
+ kCLOCK_Adc = CLK_OP_CODE_DEFINE(0x7CU, 26U, 1U, 0U),
+
+ kCLOCK_Gau = CLK_OP_CODE_DEFINE(0x9CU, 2U, 1U, 0U),
+
+ kCLOCK_AcompMclk = CLK_OP_CODE_DEFINE(0xB4U, 0U, 1U, 1U),
+ kCLOCK_DacMclk = CLK_OP_CODE_DEFINE(0xB4U, 1U, 1U, 1U),
+ kCLOCK_AdcMclk = CLK_OP_CODE_DEFINE(0xB4U, 3U, 1U, 1U),
+ kCLOCK_BgMclk = CLK_OP_CODE_DEFINE(0xB4U, 4U, 1U, 1U),
+
+ kCLOCK_Rtc = CLK_OP_CODE_DEFINE(0xF8U, 4U, 1U, 0U),
+ kCLOCK_Dma = CLK_OP_CODE_DEFINE(0xF8U, 6U, 1U, 0U),
+
+ kCLOCK_Rc32m = CLK_OP_CODE_DEFINE(0xFCU, 18U, 1U, 0U),
+} clock_ip_name_t;
+
+/*!
+ * @brief Peripheral clock source selection definition.
+ */
+typedef enum _clock_attach_id
+{
+ kSYS_CLK_to_SLOW_UART0 = CLK_OP_CODE_DEFINE(0x88U, 0U, 1U, 0x0U),
+ kSYS_CLK_to_FAST_UART0 = CLK_OP_CODE_DEFINE(0x88U, 0U, 1U, 0x1U),
+
+ kSYS_CLK_to_SLOW_UART1 = CLK_OP_CODE_DEFINE(0x88U, 1U, 1U, 0x0U),
+ kSYS_CLK_to_FAST_UART1 = CLK_OP_CODE_DEFINE(0x88U, 1U, 1U, 0x1U),
+
+ kSYS_CLK_to_SLOW_UART2 = CLK_OP_CODE_DEFINE(0x88U, 2U, 1U, 0x0U),
+ kSYS_CLK_to_FAST_UART2 = CLK_OP_CODE_DEFINE(0x88U, 2U, 1U, 0x1U),
+
+ kSYS_CLK_to_GPT0 = CLK_OP_CODE_DEFINE(0xE4U, 7U, 4U, 0x0U),
+ kRC32K_to_GPT0 = CLK_OP_CODE_DEFINE(0xE4U, 7U, 4U, 0x2U),
+ kXTAL32K_to_GPT0 = CLK_OP_CODE_DEFINE(0xE4U, 7U, 4U, 0x3U),
+ kRC32M_to_GPT0 = CLK_OP_CODE_DEFINE(0xE4U, 7U, 4U, 0x8U),
+ kMAINXTAL_to_GPT0 = CLK_OP_CODE_DEFINE(0xE4U, 7U, 4U, 0xCU),
+
+ kSYS_CLK_to_GPT1 = CLK_OP_CODE_DEFINE(0xE8U, 7U, 4U, 0x0U),
+ kRC32K_to_GPT1 = CLK_OP_CODE_DEFINE(0xE8U, 7U, 4U, 0x2U),
+ kXTAL32K_to_GPT1 = CLK_OP_CODE_DEFINE(0xE8U, 7U, 4U, 0x3U),
+ kRC32M_to_GPT1 = CLK_OP_CODE_DEFINE(0xE8U, 7U, 4U, 0x8U),
+ kMAINXTAL_to_GPT1 = CLK_OP_CODE_DEFINE(0xE8U, 7U, 4U, 0xCU),
+
+ kSYS_CLK_to_GPT2 = CLK_OP_CODE_DEFINE(0xECU, 7U, 4U, 0x0U),
+ kRC32K_to_GPT2 = CLK_OP_CODE_DEFINE(0xECU, 7U, 4U, 0x2U),
+ kXTAL32K_to_GPT2 = CLK_OP_CODE_DEFINE(0xECU, 7U, 4U, 0x3U),
+ kRC32M_to_GPT2 = CLK_OP_CODE_DEFINE(0xECU, 7U, 4U, 0x8U),
+ kMAINXTAL_to_GPT2 = CLK_OP_CODE_DEFINE(0xECU, 7U, 4U, 0xCU),
+
+ kSYS_CLK_to_GPT3 = CLK_OP_CODE_DEFINE(0xF0U, 7U, 4U, 0x0U),
+ kRC32K_to_GPT3 = CLK_OP_CODE_DEFINE(0xF0U, 7U, 4U, 0x2U),
+ kXTAL32K_to_GPT3 = CLK_OP_CODE_DEFINE(0xF0U, 7U, 4U, 0x3U),
+ kRC32M_to_GPT3 = CLK_OP_CODE_DEFINE(0xF0U, 7U, 4U, 0x8U),
+ kMAINXTAL_to_GPT3 = CLK_OP_CODE_DEFINE(0xF0U, 7U, 4U, 0xCU),
+
+ kSYS_CLK_to_SSP0 = CLK_OP_CODE_DEFINE(0xDCU, 0U, 1U, 0x0U),
+ kAUPLL_to_SSP0 = CLK_OP_CODE_DEFINE(0xDCU, 0U, 1U, 0x1U),
+
+ kSYS_CLK_to_SSP1 = CLK_OP_CODE_DEFINE(0xDCU, 1U, 1U, 0x0U),
+ kAUPLL_to_SSP1 = CLK_OP_CODE_DEFINE(0xDCU, 1U, 1U, 0x1U),
+
+ kSYS_CLK_to_SSP2 = CLK_OP_CODE_DEFINE(0xDCU, 2U, 1U, 0x0U),
+ kAUPLL_to_SSP2 = CLK_OP_CODE_DEFINE(0xDCU, 2U, 1U, 0x1U),
+
+ kSYS_CLK_to_GAU = CLK_OP_CODE_DEFINE(0x9CU, 0U, 2U, 0x0U),
+ kRC32M_to_GAU = CLK_OP_CODE_DEFINE(0x9CU, 0U, 2U, 0x1U),
+ kMAINXTAL_to_GAU = CLK_OP_CODE_DEFINE(0x9CU, 0U, 2U, 0x2U),
+ kAUPLL_to_GAU = CLK_OP_CODE_DEFINE(0x9CU, 0U, 2U, 0x3U),
+
+ kRC32K_to_RTC = CLK_OP_CODE_DEFINE(0xF8U, 5U, 1U, 0x0U),
+ kXTAL32K_to_RTC = CLK_OP_CODE_DEFINE(0xF8U, 5U, 1U, 0x1U),
+} clock_attach_id_t;
+
+/*!
+ * @brief Clock divider definition.
+ */
+typedef enum _clock_div_name
+{
+ kCLOCK_DivUartFast = CLK_OP_CODE_DEFINE(0x80U, 0U, 0U, 1U),
+ kCLOCK_DivUartSlow = CLK_OP_CODE_DEFINE(0x84U, 0U, 0U, 1U),
+ kCLOCK_DivCore = CLK_OP_CODE_DEFINE(0x8CU, 0U, 6U, 0U),
+
+ kCLOCK_DivSsp0 = CLK_OP_CODE_DEFINE(0x90U, 0U, 5U, 0U),
+ kCLOCK_DivSsp1 = CLK_OP_CODE_DEFINE(0x90U, 5U, 5U, 0U),
+ kCLOCK_DivSsp2 = CLK_OP_CODE_DEFINE(0x90U, 10U, 5U, 0U),
+ kCLOCK_DivSdio = CLK_OP_CODE_DEFINE(0x90U, 16U, 4U, 0U),
+
+ kCLOCK_DivFlashC = CLK_OP_CODE_DEFINE(0x94U, 4U, 3U, 0U),
+ kCLOCK_DivQspi = CLK_OP_CODE_DEFINE(0x94U, 8U, 3U, 0U),
+
+ kCLOCK_DivI2c = CLK_OP_CODE_DEFINE(0x98U, 20U, 2U, 0U),
+ kCLOCK_DivGptSamp = CLK_OP_CODE_DEFINE(0x98U, 0U, 3U, 0U),
+ kCLOCK_DivWdt = CLK_OP_CODE_DEFINE(0x98U, 24U, 2U, 1U),
+
+ kCLOCK_DivGpt0 = CLK_OP_CODE_DEFINE(0xE4U, 0U, 6U, 0U),
+ kCLOCK_DivGpt1 = CLK_OP_CODE_DEFINE(0xE8U, 0U, 6U, 0U),
+ kCLOCK_DivGpt2 = CLK_OP_CODE_DEFINE(0xECU, 0U, 6U, 0U),
+ kCLOCK_DivGpt3 = CLK_OP_CODE_DEFINE(0x98U, 8U, 3U, 1U),
+
+ kCLOCK_DivApb0 = CLK_OP_CODE_DEFINE(0xF8U, 7U, 2U, 0U),
+ kCLOCK_DivApb1 = CLK_OP_CODE_DEFINE(0xF8U, 9U, 2U, 0U),
+ kCLOCK_DivPmu = CLK_OP_CODE_DEFINE(0xF8U, 0U, 4U, 0U),
+
+ kCLOCK_DivGau = CLK_OP_CODE_DEFINE(0xFCU, 8U, 5U, 0U),
+ kCLOCK_DivRc32mRef = CLK_OP_CODE_DEFINE(0xFCU, 13U, 5U, 0U),
+} clock_div_name_t;
+
+/*!
+ * @brief CLOCK system clock source.
+ */
+typedef enum _clock_sys_clk_src
+{
+ kCLOCK_SysClkSrcSFll = 0U, /*!< SFLL. */
+ kCLOCK_SysClkSrcRC32M_1 = 1U, /*!< RC 32MHz clock. */
+ kCLOCK_SysClkSrcMainXtal = 2U, /*!< XTAL 38.4MHz clock. */
+ kCLOCK_SysClkSrcRC32M_3 = 3U, /*!< RC 32MHz clock. */
+} clock_sys_clk_src_t;
+
+/*!
+ * @brief System reference clock option
+ */
+typedef enum _clock_refclk
+{
+ kCLOCK_RefClk_SYS = (1U << PMU_WLAN_CTRL_REFCLK_SYS_REQ_SHIFT), /*!< REFCLK_SYS */
+ kCLOCK_RefClk_AUD = (1U << PMU_WLAN_CTRL_REFCLK_AUD_REQ_SHIFT), /*!< REFCLK_AUD */
+ kCLOCK_RefClk_USB = (1U << PMU_WLAN_CTRL_REFCLK_USB_REQ_SHIFT), /*!< REFCLK_USB */
+ kCLOCK_RefClk_ALL = (kCLOCK_RefClk_SYS | kCLOCK_RefClk_AUD | kCLOCK_RefClk_USB),
+} clock_refclk_t;
+
+/*!
+ * @brief XTAL32K mode option
+ */
+typedef enum _clock_osc32k_mode
+{
+ kCLOCK_Osc32k_Internal = 0, /*!< Internal oscillator mode */
+ kCLOCK_Osc32k_External = 1, /*!< External oscillator mode */
+} clock_osc32k_mode_t;
+
+/*! @brief SFLL Reference Input Clock Source */
+typedef enum _clock_sfll_src
+{
+ kCLOCK_SFllSrcRC32M = 0U, /*!< RC32M clock */
+ kCLOCK_SFllSrcMainXtal = 1U, /*!< Main XTAL clock */
+} clock_sfll_src_t;
+
+/*! @brief SFLL configuration. */
+typedef struct _clock_sfll_config
+{
+ clock_sfll_src_t sfllSrc; /*!< Reference Input Clock Source */
+ uint16_t refDiv; /*!< Divider for reference clock, 9-bit */
+ /*!< 0.2 MHz <= Fref (frequency of Reference clock / refDiv) <= 0.4 MHz */
+ uint16_t fbDiv; /*!< Divider for feedback clock, 9-bit */
+ uint8_t kvco; /*!< VCO setting, 2-bit */
+ /*!< Select KVCO per VCO target frequency */
+ uint8_t postDiv; /*!< Post divider, 2-bit */
+ /*!< 2'b01, Fout = Fvco/2 */
+ /*!< 2'b10, Fout = Fvco/4 */
+ /*!< 2'b11, Fout = Fvco/8 */
+} clock_sfll_config_t;
+
+/*! @brief AUPLL Reference Input Clock Source */
+typedef enum _clock_aupll_src
+{
+ kCLOCK_AuPllSrcRC32M = 0U, /*!< RC32M clock */
+ kCLOCK_AuPllSrcRefClk = 1U, /*!< REFCLK_AUD clock */
+} clock_aupll_src_t;
+
+/*! @brief AUPLL configuration. */
+typedef struct _clock_aupll_config
+{
+ clock_aupll_src_t aupllSrc; /*!< Reference Input Clock Source */
+ uint8_t refDiv; /*!< Divider for reference clock, 4-bit, range: 3 ~ 10 */
+ uint8_t fbDiv; /*!< Divider for feedback clock, 6-bit, range: 27, 29, 31 ~ 36, 38, 39, 42, 46 */
+ uint8_t icp; /*!< charge pump current control, 2-bit, reserved now */
+ /*!< 2'b00, 2.5 uA */
+ /*!< 2'b01, 5 uA */
+ /*!< 2'b10, 7.5 uA */
+ /*!< 2'b11, 10 uA */
+ uint8_t postDivPattern; /*!< Pattern divider for ouput clock, 2-bit, range: 0 ~ 2 */
+ /*!< 2'b00, pattern = 4.0 */
+ /*!< 2'b01, pattern = 3.0 */
+ /*!< 2'b10, pattern = 4.5 */
+ uint8_t postDivModulo; /*!< Modulo divider for ouput clock, 3-bit, range: 0 ~ 2, 4, 7 */
+ /*!< 3'b000, modulo = 1 */
+ /*!< 3'b001, modulo = 2 */
+ /*!< 3'b010, modulo = 4 */
+ /*!< 3'b100, modulo = 8 */
+ /*!< 3'b111, modulo = 16 */
+ bool enaDither; /* ENA_DITHER status */
+ /*!< 1'b0, Integration only */
+ /*!< 1'b1, Integration + MASH */
+ bool enaVcoClkX2; /* Enable or disable VCOCLK_X2 */
+ /*!< 1'b0, Disable VCOCLK_X2 */
+ /*!< 1'b1, Enable VCOCLK_X2 */
+ uint32_t fract; /*!< Fractional PLL feedback divider 20-bits, range: 0 ~ 0x10000 */
+} clock_aupll_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief Enable the clock for specific IP.
+ *
+ * @param name Which clock to enable, see \ref clock_ip_name_t.
+ */
+void CLOCK_EnableClock(clock_ip_name_t name);
+
+/*!
+ * @brief Disable the clock for specific IP.
+ *
+ * @param name Which clock to disable, see \ref clock_ip_name_t.
+ */
+void CLOCK_DisableClock(clock_ip_name_t name);
+
+/**
+ * @brief Configure the clock selection muxes.
+ * @param connection : Clock to be configured.
+ */
+void CLOCK_AttachClk(clock_attach_id_t connection);
+
+/**
+ * @brief Setup clock dividers.
+ * @param name : Clock divider name
+ * @param divider : Value to be divided.
+ */
+void CLOCK_SetClkDiv(clock_div_name_t name, uint32_t divider);
+
+/*!
+ * @brief Setup UART clock dividers.
+ *
+ * @param name : Clock divider name
+ * @param nom : Nominator for fraction divider.
+ * @param denom : Denominator for fraction divider.
+ */
+void CLOCK_SetUartClkDiv(clock_div_name_t name, uint32_t nom, uint32_t denom);
+
+/*!
+ * @brief Get the system clock frequency.
+ *
+ * @return Clock frequency in Hz.
+ */
+uint32_t CLOCK_GetSysClkFreq(void);
+
+/*!
+ * @brief Set the system clock source.
+ *
+ * This function sets the system clock source.
+ *
+ * @param src System clock source to set.
+ */
+void CLOCK_SetSysClkSource(clock_sys_clk_src_t src);
+
+/*!
+ * @brief Enable the 32K XTAL.
+ *
+ * @param mode Internal or external OSC selection.
+ */
+void CLOCK_EnableXtal32K(clock_osc32k_mode_t mode);
+
+/*!
+ * @brief Disable the 32K XTAL output.
+ */
+void CLOCK_DisableXtal32K(void);
+
+/*!
+ * @brief Enable the RC32M OSC.
+ *
+ * @param halfDiv half-divided reference clock. True for 16MHz and false for original 32MHz output.
+ */
+void CLOCK_EnableRC32M(bool halfDiv);
+
+/*!
+ * @brief Disable the RC32M OSC.
+ */
+void CLOCK_DisableRC32M(void);
+
+/*!
+ * @brief RC32M clock calibration function
+ *
+ * @param autoCal Calibration option, true for auto and false for manual
+ * @param manCalCode Select manual way, need input the calibration code
+ * @return return the calibration result
+ * -1, calibration failure
+ * else, internal calibration code
+ *
+ * @note Clock CLK_AUPLL_CAU must be ready before RC32M calibration
+ */
+int32_t CLOCK_CalibrateRC32M(bool autoCal, uint32_t manCalCode);
+
+/*!
+ * @brief Enable the RC32K OSC.
+ */
+void CLOCK_EnableRC32K(void);
+
+/*!
+ * @brief Disable the RC32K OSC.
+ */
+void CLOCK_DisableRC32K(void);
+
+/*!
+ * @brief RC32K clock calibration function
+ *
+ * @param autoCal Calibration option, true for auto and false for manual
+ * @param manCalCode Select manual way, need input the calibration code
+ * @return return the calibration result
+ * -1, calibration failure
+ * else, internal calibration code
+ *
+ * @note Clock XTAL32K must be ready before RC32K calibration
+ */
+int32_t CLOCK_CalibrateRC32K(bool autoCal, uint32_t manCalCode);
+
+/*!
+ * @brief Enable the REFCLK for SYS/AUD/USB reference.
+ *
+ * @param refclks Or'ed value to select SYS/AUD/USB REFCLK to disable. See \ref clock_refclk_t.
+ */
+void CLOCK_EnableRefClk(uint32_t refclks);
+
+/*!
+ * @brief Disable the REFCLK for SYS/AUD/USB reference.
+ *
+ * @param refclks Or'ed value to select SYS/AUD/USB REFCLK to disable. See \ref clock_refclk_t.
+ */
+void CLOCK_DisableRefClk(uint32_t refclks);
+
+/*! @brief Initialize the SFLL.
+ * @param config : Configuration to set to SFLL.
+ */
+void CLOCK_InitSFll(const clock_sfll_config_t *config);
+
+/*! @brief Deinit the SFLL.
+ */
+void CLOCK_DeinitSFll(void);
+
+/*! @brief Initialize the AUPLL.
+ * @param config : Configuration to set to AUPLL.
+ */
+void CLOCK_InitAuPll(const clock_aupll_config_t *config);
+
+/*! @brief Deinit the AUPLL.
+ */
+void CLOCK_DeinitAuPll(void);
+
+/*! @brief Update the AUPLL post divider
+ */
+void CLOCK_UpdateAupllPostDiv(uint8_t postDivPattern, uint8_t postDivModulo);
+
+/*!
+ * @brief Set the MAIN XTAL frequency based on board setting.
+ *
+ * @param freq : The XTAL input clock frequency in Hz.
+ */
+__STATIC_INLINE void CLOCK_SetMainXtalFreq(uint32_t freq)
+{
+ g_mainXtalFreq = freq;
+}
+
+/*! @brief Return Frequency of MAIN XTAL Clock
+ * @return Frequency of MAIN XTAL Clock.
+ */
+uint32_t CLOCK_GetMainXtalFreq(void);
+
+/*! @brief Return Frequency of REFCLK_AUD Clock
+ * @return Frequency of REFCLK_AUD Clock.
+ */
+uint32_t CLOCK_GetRefClkAudFreq(void);
+
+/*! @brief Return Frequency of RC32M Clock
+ * @return Frequency of RC32M Clock.
+ */
+uint32_t CLOCK_GetRC32MFreq(void);
+
+/*! @brief Return Frequency of XTAL32K Clock
+ * @return Frequency of XTAL32K Clock.
+ */
+uint32_t CLOCK_GetXtal32KFreq(void);
+
+/*! @brief Return Frequency of RC32K Clock
+ * @return Frequency of RC32K Clock.
+ */
+uint32_t CLOCK_GetRC32KFreq(void);
+
+/*! @brief Return Frequency of SFLL Clock
+ * @return Frequency of SFLL Clock.
+ */
+uint32_t CLOCK_GetSFllFreq(void);
+
+/*! @brief Return Frequency of AUPLL Clock
+ * @return Frequency of AUPLL Clock.
+ */
+uint32_t CLOCK_GetAuPllFreq(void);
+
+/*! @brief Return Frequency of M4/AHB Clock
+ * @return Frequency of M4/AHB Clock.
+ */
+uint32_t CLOCK_GetCoreBusFreq(void);
+
+/*! @brief Return Frequency of APB Clock
+ *
+ * @param instance APB instance 0-1.
+ * @return Frequency of APB Clock.
+ */
+uint32_t CLOCK_GetApbFreq(uint32_t instance);
+
+/*! @brief Return Frequency of UART Clock
+ *
+ * @param instance UART instance 0-2.
+ * @return Frequency of UART Clock.
+ */
+uint32_t CLOCK_GetUartClkFreq(uint32_t instance);
+
+/*! @brief Return Frequency of GPT Clock
+ *
+ * @param instance GPT instance 0-3.
+ * @return Frequency of GPT Clock.
+ */
+uint32_t CLOCK_GetGptClkFreq(uint32_t instance);
+
+/*! @brief Return Frequency of GPT Sample Clock
+ *
+ * @return Frequency of GPT Sample Clock.
+ */
+uint32_t CLOCK_GetGptSampleClkFreq(void);
+
+/*! @brief Return Frequency of SSP Clock
+ *
+ * @param instance SSP instance 0-2.
+ * @return Frequency of SSP Clock.
+ */
+uint32_t CLOCK_GetSspClkFreq(uint32_t instance);
+
+/*! @brief Return Frequency of GAU Clock
+ * @return Frequency of GAU Clock.
+ */
+uint32_t CLOCK_GetGauClkFreq(void);
+
+/*! @brief Return Frequency of RTC Clock
+ * @return Frequency of RTC Clock.
+ */
+uint32_t CLOCK_GetRtcClkFreq(void);
+
+/*! @brief Return Frequency of I2C Clock
+ * @return Frequency of I2C Clock.
+ */
+uint32_t CLOCK_GetI2cClkFreq(void);
+
+/*! @brief Return Frequency of QSPI Clock
+ * @return Frequency of QSPI Clock.
+ */
+uint32_t CLOCK_GetQspiClkFreq(void);
+
+/*! @brief Return Frequency of FlashC Clock
+ * @return Frequency of FlashC Clock.
+ */
+uint32_t CLOCK_GetFlashCClkFreq(void);
+
+/*! @brief Return Frequency of WDT Clock
+ * @return Frequency of WDT Clock.
+ */
+uint32_t CLOCK_GetWdtClkFreq(void);
+
+/*! @brief Return Frequency of SDIO Clock
+ * @return Frequency of SDIO Clock.
+ */
+uint32_t CLOCK_GetSdioClkFreq(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CLOCK_H_ */
diff --git a/devices/88MW320/drivers/fsl_pinmux.c b/devices/88MW320/drivers/fsl_pinmux.c
new file mode 100644
index 000000000..8b517fa84
--- /dev/null
+++ b/devices/88MW320/drivers/fsl_pinmux.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_pinmux.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.pinmux"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/**
+ * @brief Sets I/O Pad Control pin mux
+ * @param pin : GPIO pin to mux
+ * @param modefunc : OR'ed values of type PINMUX_*
+ */
+void PINMUX_PinMuxSet(uint32_t pin, uint32_t modefunc)
+{
+ volatile uint32_t *reg = &PIN_MUX->_GPIO0 + pin;
+
+ assert(pin < 50U);
+
+ /* For GPIO6~10, GPIO22~26 and GPIO28~33, function 1 is GPIO function, for other GPIOs, function 0 is GPIO function
+ */
+ if (((pin >= 6U) && (pin <= 10U)) || ((pin >= 22U) && (pin <= 26U)) || ((pin >= 28U) && (pin <= 33U)))
+ {
+ if ((modefunc & PINMUX_FUNC_MASK) != PINMUX_FUNC1)
+ {
+ /* Need to set default pull up for non-GPIO before function switch. */
+ *reg &= ~PINMUX__GPIO0_PIO_PULL_SEL_MASK;
+ }
+ }
+ else
+ {
+ if ((modefunc & PINMUX_FUNC_MASK) != PINMUX_FUNC0)
+ {
+ /* Need to set default pull up for non-GPIO before function switch. */
+ *reg &= ~PINMUX__GPIO0_PIO_PULL_SEL_MASK;
+ }
+ }
+
+ *reg = modefunc;
+}
diff --git a/devices/88MW320/drivers/fsl_pinmux.h b/devices/88MW320/drivers/fsl_pinmux.h
new file mode 100644
index 000000000..3c64abfb3
--- /dev/null
+++ b/devices/88MW320/drivers/fsl_pinmux.h
@@ -0,0 +1,409 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_PINMUX_H_
+#define _FSL_PINMUX_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup pinmux
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief PINMUX driver version 2.0.0. */
+#define FSL_PINMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/**
+ * @brief PINMUX function and mode selection definitions
+ * @note See the User Manual for specific modes and functions supported by the various pins.
+ */
+#define PINMUX_FUNC0 0x0U /*!< Selects pin function 0 */
+#define PINMUX_FUNC1 0x1U /*!< Selects pin function 1 */
+#define PINMUX_FUNC2 0x2U /*!< Selects pin function 2 */
+#define PINMUX_FUNC3 0x3U /*!< Selects pin function 3 */
+#define PINMUX_FUNC4 0x4U /*!< Selects pin function 4 */
+#define PINMUX_FUNC5 0x5U /*!< Selects pin function 5 */
+#define PINMUX_FUNC6 0x6U /*!< Selects pin function 6 */
+#define PINMUX_FUNC7 0x7U /*!< Selects pin function 7 */
+#define PINMUX_FUNC_MASK 0x7U /*!< Pinmux function mask in modefunc */
+
+#define PINMUX_MODE_DEFAULT (0x1U << 3) /*!< Pulled up by default 50 kΩ */
+#define PINMUX_MODE_PULLUP ((0x1U << 3) | (0x1U << 14) | (0x1U << 15)) /*!< Selects pull-up */
+#define PINMUX_MODE_PULLDOWN ((0x1U << 3) | (0x1U << 13) | (0x1U << 15)) /*!< Selects pull-down */
+#define PINMUX_MODE_NOPULL ((0x1U << 3) | (0x1U << 15)) /*!< Selects no pull */
+#define PINMUX_MODE_TRISTATE (0x1U << 15) /*!< Selects tristate */
+
+/* GPIO0 pinmux function define */
+#define PINMUX_GPIO0_GPIO0 PINMUX_FUNC0
+#define PINMUX_GPIO0_GPT0_CH0 PINMUX_FUNC1
+#define PINMUX_GPIO0_UART0_CTSn PINMUX_FUNC2
+#define PINMUX_GPIO0_SSP0_CLK PINMUX_FUNC3
+
+/* GPIO1 pinmux function define */
+#define PINMUX_GPIO1_GPIO1 PINMUX_FUNC0
+#define PINMUX_GPIO1_GPT0_CH1 PINMUX_FUNC1
+#define PINMUX_GPIO1_UART0_RTSn PINMUX_FUNC2
+#define PINMUX_GPIO1_SSP0_FRM PINMUX_FUNC3
+
+/* GPIO2 pinmux function define */
+#define PINMUX_GPIO2_GPIO2 PINMUX_FUNC0
+#define PINMUX_GPIO2_GPT0_CH2 PINMUX_FUNC1
+#define PINMUX_GPIO2_UART0_TXD PINMUX_FUNC2
+#define PINMUX_GPIO2_SSP0_TXD PINMUX_FUNC3
+
+/* GPIO3 pinmux function define */
+#define PINMUX_GPIO3_GPIO3 PINMUX_FUNC0
+#define PINMUX_GPIO3_GPT0_CH3 PINMUX_FUNC1
+#define PINMUX_GPIO3_UART0_RXD PINMUX_FUNC2
+#define PINMUX_GPIO3_SSP0_RXD PINMUX_FUNC3
+
+/* GPIO4 pinmux function define */
+#define PINMUX_GPIO4_GPIO4 PINMUX_FUNC0
+#define PINMUX_GPIO4_GPT0_CH4 PINMUX_FUNC1
+#define PINMUX_GPIO4_I2C0_SDA PINMUX_FUNC2
+#define PINMUX_GPIO4_AUDIO_CLK PINMUX_FUNC3
+
+/* GPIO5 pinmux function define */
+#define PINMUX_GPIO5_GPIO5 PINMUX_FUNC0
+#define PINMUX_GPIO5_GPT0_CH5 PINMUX_FUNC1
+#define PINMUX_GPIO5_I2C0_SCL PINMUX_FUNC2
+
+/* GPIO6 pinmux function define */
+#define PINMUX_GPIO6_TDO PINMUX_FUNC0
+#define PINMUX_GPIO6_GPIO6 PINMUX_FUNC1
+#define PINMUX_GPIO6_I2C1_SDA PINMUX_FUNC2
+#define PINMUX_GPIO6_DIG_POR PINMUX_FUNC3
+#define PINMUX_GPIO6_RC32M PINMUX_FUNC4
+#define PINMUX_GPIO6_AUPLL_DIGTP0 PINMUX_FUNC5
+
+/* GPIO7 pinmux function define */
+#define PINMUX_GPIO7_TCK PINMUX_FUNC0
+#define PINMUX_GPIO7_GPIO7 PINMUX_FUNC1
+#define PINMUX_GPIO7_UART2_CTSn PINMUX_FUNC2
+#define PINMUX_GPIO7_SSP2_CLK PINMUX_FUNC3
+#define PINMUX_GPIO7_I2C0_SDA PINMUX_FUNC4
+#define PINMUX_GPIO7_AUPLL_DIGTP1 PINMUX_FUNC5
+
+/* GPIO8 pinmux function define */
+#define PINMUX_GPIO8_TMS PINMUX_FUNC0
+#define PINMUX_GPIO8_GPIO8 PINMUX_FUNC1
+#define PINMUX_GPIO8_UART2_RTSn PINMUX_FUNC2
+#define PINMUX_GPIO8_SSP2_FRM PINMUX_FUNC3
+#define PINMUX_GPIO8_I2C0_SCL PINMUX_FUNC4
+#define PINMUX_GPIO8_AUPLL_DIGTP2 PINMUX_FUNC5
+
+/* GPIO9 pinmux function define */
+#define PINMUX_GPIO9_TDI PINMUX_FUNC0
+#define PINMUX_GPIO9_GPIO9 PINMUX_FUNC1
+#define PINMUX_GPIO9_UART2_TXD PINMUX_FUNC2
+#define PINMUX_GPIO9_SSP2_TXD PINMUX_FUNC3
+#define PINMUX_GPIO9_I2C1_SDA PINMUX_FUNC4
+#define PINMUX_GPIO9_AUPLL_DIGTP3 PINMUX_FUNC5
+
+/* GPIO10 pinmux function define */
+#define PINMUX_GPIO10_TRST_N PINMUX_FUNC0
+#define PINMUX_GPIO10_GPIO10 PINMUX_FUNC1
+#define PINMUX_GPIO10_UART2_RXD PINMUX_FUNC2
+#define PINMUX_GPIO10_SSP2_RXD PINMUX_FUNC3
+#define PINMUX_GPIO10_I2C1_SCL PINMUX_FUNC4
+#define PINMUX_GPIO10_PHY_MON0 PINMUX_FUNC5
+
+/* GPIO11 pinmux function define */
+#define PINMUX_GPIO11_GPIO11 PINMUX_FUNC0
+#define PINMUX_GPIO11_GPT2_CH0 PINMUX_FUNC1
+#define PINMUX_GPIO11_UART1_CTSn PINMUX_FUNC2
+#define PINMUX_GPIO11_SSP1_CLK PINMUX_FUNC3
+
+/* GPIO12 pinmux function define */
+#define PINMUX_GPIO12_GPIO12 PINMUX_FUNC0
+#define PINMUX_GPIO12_GPT2_CH1 PINMUX_FUNC1
+#define PINMUX_GPIO12_UART1_RTSn PINMUX_FUNC2
+#define PINMUX_GPIO12_SSP1_FRM PINMUX_FUNC3
+
+/* GPIO13 pinmux function define */
+#define PINMUX_GPIO13_GPIO13 PINMUX_FUNC0
+#define PINMUX_GPIO13_GPT2_CH2 PINMUX_FUNC1
+#define PINMUX_GPIO13_UART1_TXD PINMUX_FUNC2
+#define PINMUX_GPIO13_SSP1_TXD PINMUX_FUNC3
+
+/* GPIO14 pinmux function define */
+#define PINMUX_GPIO14_GPIO14 PINMUX_FUNC0
+#define PINMUX_GPIO14_GPT2_CH3 PINMUX_FUNC1
+#define PINMUX_GPIO14_UART1_RXD PINMUX_FUNC2
+#define PINMUX_GPIO14_SSP1_RXD PINMUX_FUNC3
+
+/* GPIO15 pinmux function define */
+#define PINMUX_GPIO15_GPIO15 PINMUX_FUNC0
+#define PINMUX_GPIO15_GPT2_CH4 PINMUX_FUNC1
+
+/* GPIO16 pinmux function define */
+#define PINMUX_GPIO16_GPIO16 PINMUX_FUNC0
+#define PINMUX_GPIO16_STRAP1 PINMUX_FUNC1
+#define PINMUX_GPIO16_AUDIO_CLK PINMUX_FUNC3
+#define PINMUX_GPIO16_PHY_MON7 PINMUX_FUNC5
+
+/* GPIO17 pinmux function define */
+#define PINMUX_GPIO17_GPIO17 PINMUX_FUNC0
+#define PINMUX_GPIO17_GPT3_CH0 PINMUX_FUNC1
+#define PINMUX_GPIO17_I2C1_SCL PINMUX_FUNC2
+
+/* GPIO18 pinmux function define */
+#define PINMUX_GPIO18_GPIO18 PINMUX_FUNC0
+#define PINMUX_GPIO18_GPT3_CH1 PINMUX_FUNC1
+#define PINMUX_GPIO18_I2C1_SDA PINMUX_FUNC2
+#define PINMUX_GPIO18_SSP1_CLK PINMUX_FUNC3
+
+/* GPIO19 pinmux function define */
+#define PINMUX_GPIO19_GPIO19 PINMUX_FUNC0
+#define PINMUX_GPIO19_GPT3_CH2 PINMUX_FUNC1
+#define PINMUX_GPIO19_I2C1_SCL PINMUX_FUNC2
+#define PINMUX_GPIO19_SSP1_FRM PINMUX_FUNC3
+
+/* GPIO20 pinmux function define */
+#define PINMUX_GPIO20_GPIO20 PINMUX_FUNC0
+#define PINMUX_GPIO20_GPT3_CH3 PINMUX_FUNC1
+#define PINMUX_GPIO20_I2C0_SDA PINMUX_FUNC2
+#define PINMUX_GPIO20_SSP1_TXD PINMUX_FUNC3
+
+/* GPIO21 pinmux function define */
+#define PINMUX_GPIO21_GPIO21 PINMUX_FUNC0
+#define PINMUX_GPIO21_GPT3_CH4 PINMUX_FUNC1
+#define PINMUX_GPIO21_I2C0_SCL PINMUX_FUNC2
+#define PINMUX_GPIO21_SSP1_RXD PINMUX_FUNC3
+
+/* GPIO22 pinmux function define */
+#define PINMUX_GPIO22_WAKE_UP0 PINMUX_FUNC0
+#define PINMUX_GPIO22_GPIO22 PINMUX_FUNC1
+
+/* GPIO23 pinmux function define */
+#define PINMUX_GPIO23_WAKE_UP1 PINMUX_FUNC0
+#define PINMUX_GPIO23_GPIO23 PINMUX_FUNC1
+#define PINMUX_GPIO23_UART0_CTSn PINMUX_FUNC2
+#define PINMUX_GPIO23_SFLL_200M PINMUX_FUNC4
+#define PINMUX_GPIO23_COMP_IN_P PINMUX_FUNC5
+
+/* GPIO24 pinmux function define */
+#define PINMUX_GPIO24_OSC32K PINMUX_FUNC0
+#define PINMUX_GPIO24_GPIO24 PINMUX_FUNC1
+#define PINMUX_GPIO24_UART0_RXD PINMUX_FUNC2
+#define PINMUX_GPIO24_GPT1_CH5 PINMUX_FUNC3
+#define PINMUX_GPIO24_COMP_IN_N PINMUX_FUNC5
+
+/* GPIO25 pinmux function define */
+#define PINMUX_GPIO25_XTAL32K_IN PINMUX_FUNC0
+#define PINMUX_GPIO25_GPIO25 PINMUX_FUNC1
+#define PINMUX_GPIO25_I2C1_SDA PINMUX_FUNC2
+
+/* GPIO26 pinmux function define */
+#define PINMUX_GPIO26_XTAL32K_OUT PINMUX_FUNC0
+#define PINMUX_GPIO26_GPIO26 PINMUX_FUNC1
+#define PINMUX_GPIO26_I2C1_SCL PINMUX_FUNC2
+
+/* GPIO27 pinmux function define */
+#define PINMUX_GPIO27_GPIO27 PINMUX_FUNC0
+#define PINMUX_GPIO27_STRAP0 PINMUX_FUNC1
+#define PINMUX_GPIO27_UART0_TXD PINMUX_FUNC2
+#define PINMUX_GPIO27_DRVVBUS PINMUX_FUNC3
+#define PINMUX_GPIO27_RC32K PINMUX_FUNC4
+
+/* GPIO28 pinmux function define */
+#define PINMUX_GPIO28_QSPI_SSn PINMUX_FUNC0
+#define PINMUX_GPIO28_GPIO28 PINMUX_FUNC1
+#define PINMUX_GPIO28_I2C0_SDA PINMUX_FUNC2
+#define PINMUX_GPIO28_PHY_MON1 PINMUX_FUNC4
+#define PINMUX_GPIO28_GPT1_CH0 PINMUX_FUNC5
+
+/* GPIO29 pinmux function define */
+#define PINMUX_GPIO29_QSPI_CLK PINMUX_FUNC0
+#define PINMUX_GPIO29_GPIO29 PINMUX_FUNC1
+#define PINMUX_GPIO29_I2C0_SCL PINMUX_FUNC2
+#define PINMUX_GPIO29_PHY_MON2 PINMUX_FUNC4
+#define PINMUX_GPIO29_GPT1_CH1 PINMUX_FUNC5
+
+/* GPIO30 pinmux function define */
+#define PINMUX_GPIO30_QSPI_D0 PINMUX_FUNC0
+#define PINMUX_GPIO30_GPIO30 PINMUX_FUNC1
+#define PINMUX_GPIO30_UART0_CTSn PINMUX_FUNC2
+#define PINMUX_GPIO30_SSP0_CLK PINMUX_FUNC3
+#define PINMUX_GPIO30_PHY_MON3 PINMUX_FUNC4
+#define PINMUX_GPIO30_GPT1_CH2 PINMUX_FUNC5
+
+/* GPIO31 pinmux function define */
+#define PINMUX_GPIO31_QSPI_D1 PINMUX_FUNC0
+#define PINMUX_GPIO31_GPIO31 PINMUX_FUNC1
+#define PINMUX_GPIO31_UART0_RTSn PINMUX_FUNC2
+#define PINMUX_GPIO31_SSP0_FRM PINMUX_FUNC3
+#define PINMUX_GPIO31_PHY_MON4 PINMUX_FUNC4
+#define PINMUX_GPIO31_GPT1_CH3 PINMUX_FUNC5
+
+/* GPIO32 pinmux function define */
+#define PINMUX_GPIO32_QSPI_D2 PINMUX_FUNC0
+#define PINMUX_GPIO32_GPIO32 PINMUX_FUNC1
+#define PINMUX_GPIO32_UART0_TXD PINMUX_FUNC2
+#define PINMUX_GPIO32_SSP0_TXD PINMUX_FUNC3
+#define PINMUX_GPIO32_PHY_MON5 PINMUX_FUNC4
+#define PINMUX_GPIO32_GPT1_CH4 PINMUX_FUNC5
+
+/* GPIO33 pinmux function define */
+#define PINMUX_GPIO33_QSPI_D3 PINMUX_FUNC0
+#define PINMUX_GPIO33_GPIO33 PINMUX_FUNC1
+#define PINMUX_GPIO33_UART0_RXD PINMUX_FUNC2
+#define PINMUX_GPIO33_SSP0_RXD PINMUX_FUNC3
+#define PINMUX_GPIO33_PHY_MON6 PINMUX_FUNC4
+#define PINMUX_GPIO33_GPT1_CH5 PINMUX_FUNC5
+
+/* GPIO34 pinmux function define */
+#define PINMUX_GPIO34_GPIO34 PINMUX_FUNC0
+#define PINMUX_GPIO34_GPT3_CH5 PINMUX_FUNC1
+
+/* GPIO35 pinmux function define */
+#define PINMUX_GPIO35_GPIO35 PINMUX_FUNC0
+#define PINMUX_GPIO35_GPT0_CLKIN PINMUX_FUNC1
+#define PINMUX_GPIO35_UART1_CTSn PINMUX_FUNC2
+#define PINMUX_GPIO35_SSP1_CLK PINMUX_FUNC3
+
+/* GPIO36 pinmux function define */
+#define PINMUX_GPIO36_GPIO36 PINMUX_FUNC0
+#define PINMUX_GPIO36_GPT1_CLKIN PINMUX_FUNC1
+#define PINMUX_GPIO36_UART1_RTSn PINMUX_FUNC2
+#define PINMUX_GPIO36_SSP1_FRM PINMUX_FUNC3
+
+/* GPIO37 pinmux function define */
+#define PINMUX_GPIO37_GPIO37 PINMUX_FUNC0
+#define PINMUX_GPIO37_GPT2_CH5 PINMUX_FUNC1
+#define PINMUX_GPIO37_UART0_RTSn PINMUX_FUNC2
+
+/* GPIO38 pinmux function define */
+#define PINMUX_GPIO38_GPIO38 PINMUX_FUNC0
+#define PINMUX_GPIO38_GPT2_CLKIN PINMUX_FUNC1
+#define PINMUX_GPIO38_UART1_TXD PINMUX_FUNC2
+#define PINMUX_GPIO38_SSP1_TXD PINMUX_FUNC3
+
+/* GPIO39 pinmux function define */
+#define PINMUX_GPIO39_GPIO39 PINMUX_FUNC0
+#define PINMUX_GPIO39_GPT3_CLKIN PINMUX_FUNC1
+#define PINMUX_GPIO39_UART1_RXD PINMUX_FUNC2
+#define PINMUX_GPIO39_SSP1_RXD PINMUX_FUNC3
+#define PINMUX_GPIO39_RC32M_CLKIN PINMUX_FUNC5
+
+/* GPIO40 pinmux function define */
+#define PINMUX_GPIO40_GPIO40 PINMUX_FUNC0
+#define PINMUX_GPIO40_GAU_TRIGGER0 PINMUX_FUNC1
+#define PINMUX_GPIO40_ACOMP0_GPIO_OUT PINMUX_FUNC2
+#define PINMUX_GPIO40_ACOMP1_GPIO_OUT PINMUX_FUNC3
+
+/* GPIO41 pinmux function define */
+#define PINMUX_GPIO41_GPIO41 PINMUX_FUNC0
+#define PINMUX_GPIO41_GAU_TRIGGER1 PINMUX_FUNC1
+#define PINMUX_GPIO41_ACOMP0_EDGE_PULSE PINMUX_FUNC2
+#define PINMUX_GPIO41_ACOMP1_EDGE_PULSE PINMUX_FUNC3
+#define PINMUX_GPIO41_TRACE_CLKOUT PINMUX_FUNC5
+
+/* GPIO42 pinmux function define */
+#define PINMUX_GPIO42_GPIO42 PINMUX_FUNC0
+#define PINMUX_GPIO42_ADC0_IN0 PINMUX_FUNC1
+#define PINMUX_GPIO42_ACOMP_IN0 PINMUX_FUNC1
+#define PINMUX_GPIO42_TS_INP PINMUX_FUNC1
+#define PINMUX_GPIO42_VOICE_P PINMUX_FUNC1
+#define PINMUX_GPIO42_UART1_CTSn PINMUX_FUNC2
+#define PINMUX_GPIO42_SSP1_CLK PINMUX_FUNC3
+#define PINMUX_GPIO42_TRACE_DATA0 PINMUX_FUNC4
+#define PINMUX_GPIO42_PHY_MON8 PINMUX_FUNC5
+
+/* GPIO43 pinmux function define */
+#define PINMUX_GPIO43_GPIO43 PINMUX_FUNC0
+#define PINMUX_GPIO43_ADC0_IN1 PINMUX_FUNC1
+#define PINMUX_GPIO43_ACOMP_IN1 PINMUX_FUNC1
+#define PINMUX_GPIO43_TS_INN PINMUX_FUNC1
+#define PINMUX_GPIO43_DACB PINMUX_FUNC1
+#define PINMUX_GPIO43_VOICE_N PINMUX_FUNC1
+#define PINMUX_GPIO43_UART1_RTSn PINMUX_FUNC2
+#define PINMUX_GPIO43_SSP1_FRM PINMUX_FUNC3
+#define PINMUX_GPIO43_TRACE_DATA1 PINMUX_FUNC4
+#define PINMUX_GPIO43_PHY_MON9 PINMUX_FUNC5
+
+/* GPIO44 pinmux function define */
+#define PINMUX_GPIO44_GPIO44 PINMUX_FUNC0
+#define PINMUX_GPIO44_ADC0_IN2 PINMUX_FUNC1
+#define PINMUX_GPIO44_ACOMP_IN2 PINMUX_FUNC1
+#define PINMUX_GPIO44_DACA PINMUX_FUNC1
+#define PINMUX_GPIO44_DEBUG_P PINMUX_FUNC1
+#define PINMUX_GPIO44_UART1_TXD PINMUX_FUNC2
+#define PINMUX_GPIO44_SSP1_TXD PINMUX_FUNC3
+#define PINMUX_GPIO43_TRACE_DATA2 PINMUX_FUNC4
+#define PINMUX_GPIO44_PHY_MON10 PINMUX_FUNC5
+
+/* GPIO45 pinmux function define */
+#define PINMUX_GPIO45_GPIO45 PINMUX_FUNC0
+#define PINMUX_GPIO45_ADC0_IN3 PINMUX_FUNC1
+#define PINMUX_GPIO45_ACOMP_IN3 PINMUX_FUNC1
+#define PINMUX_GPIO45_EXT_VREF PINMUX_FUNC1
+#define PINMUX_GPIO45_UART1_RXD PINMUX_FUNC2
+#define PINMUX_GPIO45_SSP1_RXD PINMUX_FUNC3
+#define PINMUX_GPIO43_TRACE_DATA3 PINMUX_FUNC4
+#define PINMUX_GPIO45_PHY_MON11 PINMUX_FUNC5
+
+/* GPIO46 pinmux function define */
+#define PINMUX_GPIO46_GPIO46 PINMUX_FUNC0
+#define PINMUX_GPIO46_ADC0_IN4 PINMUX_FUNC1
+#define PINMUX_GPIO46_ACOMP_IN4 PINMUX_FUNC1
+#define PINMUX_GPIO46_UART2_CTSn PINMUX_FUNC2
+#define PINMUX_GPIO46_SSP2_CLK PINMUX_FUNC3
+#define PINMUX_GPIO46_PHY_MON12 PINMUX_FUNC5
+
+/* GPIO47 pinmux function define */
+#define PINMUX_GPIO47_GPIO47 PINMUX_FUNC0
+#define PINMUX_GPIO47_ADC0_IN5 PINMUX_FUNC1
+#define PINMUX_GPIO47_ACOMP_IN5 PINMUX_FUNC1
+#define PINMUX_GPIO47_UART2_RTSn PINMUX_FUNC2
+#define PINMUX_GPIO47_SSP2_FRM PINMUX_FUNC3
+#define PINMUX_GPIO47_PHY_MON13 PINMUX_FUNC5
+
+/* GPIO48 pinmux function define */
+#define PINMUX_GPIO48_GPIO48 PINMUX_FUNC0
+#define PINMUX_GPIO48_ADC0_IN6 PINMUX_FUNC1
+#define PINMUX_GPIO48_ACOMP_IN6 PINMUX_FUNC1
+#define PINMUX_GPIO48_UART2_TXD PINMUX_FUNC2
+#define PINMUX_GPIO48_SSP2_TXD PINMUX_FUNC3
+#define PINMUX_GPIO48_PHY_MON14 PINMUX_FUNC5
+
+/* GPIO49 pinmux function define */
+#define PINMUX_GPIO49_GPIO49 PINMUX_FUNC0
+#define PINMUX_GPIO49_ADC0_IN7 PINMUX_FUNC1
+#define PINMUX_GPIO49_ACOMP_IN7 PINMUX_FUNC1
+#define PINMUX_GPIO49_UART2_RXD PINMUX_FUNC2
+#define PINMUX_GPIO49_SSP2_RXD PINMUX_FUNC3
+#define PINMUX_GPIO49_PHY_MON15 PINMUX_FUNC5
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @brief Sets I/O Pad Control pin mux
+ * @param pin : GPIO pin to mux
+ * @param modefunc : OR'ed values of mode and function, type PINMUX_*
+ */
+void PINMUX_PinMuxSet(uint32_t pin, uint32_t modefunc);
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_PINMUX_H_ */
diff --git a/devices/88MW320/drivers/fsl_power.c b/devices/88MW320/drivers/fsl_power.c
new file mode 100644
index 000000000..d0e75ebe6
--- /dev/null
+++ b/devices/88MW320/drivers/fsl_power.c
@@ -0,0 +1,953 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_power.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.power"
+#endif
+
+typedef struct _power_nvic_context
+{
+ uint32_t PriorityGroup;
+ uint32_t ISER[2];
+ uint8_t IP[64];
+ uint8_t SHP[12];
+ uint32_t ICSR;
+ uint32_t VTOR;
+ uint32_t AIRCR;
+ uint32_t SCR;
+ uint32_t CCR;
+ uint32_t SHCSR;
+ uint32_t MMFAR;
+ uint32_t BFAR;
+ uint32_t CPACR;
+} power_nvic_context_t;
+
+typedef struct _power_systick_context
+{
+ uint32_t CTRL;
+ uint32_t LOAD;
+} power_systick_context_t;
+
+typedef struct _power_clock_context
+{
+ uint32_t CLK_SRC;
+ uint32_t WLAN_CTRL;
+ uint32_t SFLL_CTRL0;
+ uint32_t SFLL_CTRL1;
+ uint32_t AUPLL_CTRL0;
+ uint32_t AUPLL_CTRL1;
+ uint32_t UART_CLK_SEL;
+ uint32_t GPT0_CTRL;
+ uint32_t GPT1_CTRL;
+ uint32_t GPT2_CTRL;
+ uint32_t GPT3_CTRL;
+ uint32_t PERI_CLK_SRC;
+ uint32_t CAU_CLK_SEL;
+ uint32_t UART_FAST_CLK_DIV;
+ uint32_t UART_SLOW_CLK_DIV;
+ uint32_t MCU_CORE_CLK_DIV;
+ uint32_t PERI0_CLK_DIV;
+ uint32_t PERI1_CLK_DIV;
+ uint32_t PERI2_CLK_DIV;
+ uint32_t PERI3_CTRL;
+} power_clock_context_t;
+
+typedef struct _power_flash_context
+{
+ /* FLASHC */
+ uint32_t FCCR;
+ uint32_t FCTR;
+ uint32_t FCACR;
+ uint32_t FAOFFR;
+ /* QSPI */
+ uint32_t CONF;
+ uint32_t TIMING;
+} power_flash_context_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static power_nvic_context_t s_nvicContext;
+static power_systick_context_t s_systickContext;
+static power_clock_context_t s_clockContext;
+static power_flash_context_t s_flashContext;
+static uint32_t s_ioPadPwrCfg;
+#if defined(__ICCARM__)
+uint32_t *pm3_entryaddr;
+#elif defined(__GNUC__)
+__attribute__((used)) uint32_t *pm3_entryaddr;
+#else
+#error unsupported compiler
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void POWER_SaveNvicState(void)
+{
+ uint32_t i;
+ uint32_t irqRegs;
+ uint32_t irqNum;
+
+ irqRegs = (SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) + 1;
+ irqNum = irqRegs * 32;
+
+ assert(irqRegs <= ARRAY_SIZE(s_nvicContext.ISER));
+ assert(irqNum <= ARRAY_SIZE(s_nvicContext.IP));
+
+ s_nvicContext.PriorityGroup = NVIC_GetPriorityGrouping();
+
+ for (i = 0; i < irqRegs; i++)
+ {
+ s_nvicContext.ISER[i] = NVIC->ISER[i];
+ }
+
+ for (i = 0; i < irqNum; i++)
+ {
+ s_nvicContext.IP[i] = NVIC->IP[i];
+ }
+
+ /* Save SCB configuration */
+ s_nvicContext.ICSR = SCB->ICSR;
+ s_nvicContext.VTOR = SCB->VTOR;
+ s_nvicContext.AIRCR = SCB->AIRCR;
+ s_nvicContext.SCR = SCB->SCR;
+ s_nvicContext.CCR = SCB->CCR;
+
+ s_nvicContext.SHCSR = SCB->SHCSR;
+ s_nvicContext.MMFAR = SCB->MMFAR;
+ s_nvicContext.BFAR = SCB->BFAR;
+ s_nvicContext.CPACR = SCB->CPACR;
+
+ s_nvicContext.SHP[0] = SCB->SHP[0]; /* MemManage */
+ s_nvicContext.SHP[1] = SCB->SHP[1]; /* BusFault */
+ s_nvicContext.SHP[2] = SCB->SHP[2]; /* UsageFault */
+ s_nvicContext.SHP[7] = SCB->SHP[7]; /* SVCall */
+ s_nvicContext.SHP[8] = SCB->SHP[8]; /* DebugMonitor */
+ s_nvicContext.SHP[10] = SCB->SHP[10]; /* PendSV */
+ s_nvicContext.SHP[11] = SCB->SHP[11]; /* SysTick */
+}
+
+static void POWER_RestoreNvicState(void)
+{
+ uint32_t i;
+ uint32_t irqRegs;
+ uint32_t irqNum;
+
+ irqRegs = (SCnSCB->ICTR & SCnSCB_ICTR_INTLINESNUM_Msk) + 1;
+ irqNum = irqRegs * 32;
+
+ NVIC_SetPriorityGrouping(s_nvicContext.PriorityGroup);
+
+ for (i = 0; i < irqRegs; i++)
+ {
+ NVIC->ISER[i] = s_nvicContext.ISER[i];
+ }
+
+ for (i = 0; i < irqNum; i++)
+ {
+ NVIC->IP[i] = s_nvicContext.IP[i];
+ }
+
+ /* Restore SCB configuration */
+ SCB->ICSR = s_nvicContext.ICSR;
+ SCB->VTOR = s_nvicContext.VTOR;
+ SCB->AIRCR = s_nvicContext.AIRCR;
+ SCB->SCR = s_nvicContext.SCR;
+ SCB->CCR = s_nvicContext.CCR;
+
+ SCB->SHCSR = s_nvicContext.SHCSR;
+ SCB->MMFAR = s_nvicContext.MMFAR;
+ SCB->BFAR = s_nvicContext.BFAR;
+ SCB->CPACR = s_nvicContext.CPACR;
+
+ SCB->SHP[0] = s_nvicContext.SHP[0]; /* MemManage */
+ SCB->SHP[1] = s_nvicContext.SHP[1]; /* BusFault */
+ SCB->SHP[2] = s_nvicContext.SHP[2]; /* UsageFault */
+ SCB->SHP[7] = s_nvicContext.SHP[7]; /* SVCall */
+ SCB->SHP[8] = s_nvicContext.SHP[8]; /* DebugMonitor */
+ SCB->SHP[10] = s_nvicContext.SHP[10]; /* PendSV */
+ SCB->SHP[11] = s_nvicContext.SHP[11]; /* SysTick */
+}
+
+/**
+ * @brief Power on IO domain pad regulator.
+ * @param domain : IO domain to power on.
+ */
+void POWER_PowerOnVddioPad(power_vddio_t domain)
+{
+ if (domain == kPOWER_VddIoAon)
+ {
+ PMU->IO_PAD_PWR_CFG |= PMU_IO_PAD_PWR_CFG_GPIO_AON_PDB_MASK;
+ }
+ else
+ {
+ assert(domain <= kPOWER_VddIo3);
+ /* Both pad regulator and IO domain powered on */
+ PMU->IO_PAD_PWR_CFG |= ((1UL << (PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_SHIFT + (uint32_t)domain)) |
+ (1UL << (PMU_IO_PAD_PWR_CFG_GPIO0_PDB_SHIFT + (uint32_t)domain)));
+ }
+}
+
+/**
+ * @brief Power off IO domain pad regulator.
+ * @param domain : IO domain to power off.
+ */
+void POWER_PowerOffVddioPad(power_vddio_t domain)
+{
+ if (domain == kPOWER_VddIoAon)
+ {
+ PMU->IO_PAD_PWR_CFG &= ~PMU_IO_PAD_PWR_CFG_GPIO_AON_PDB_MASK;
+ }
+ else
+ {
+ assert(domain <= kPOWER_VddIo3);
+ PMU->IO_PAD_PWR_CFG &= ~(1UL << (PMU_IO_PAD_PWR_CFG_GPIO0_PDB_SHIFT + (uint32_t)domain));
+ }
+}
+
+/**
+ * @brief Set IO domain pad voltage.
+ * @param domain : IO domain.
+ * @param volt : Voltage level to be set.
+ */
+void POWER_SetVddioPadVolt(power_vddio_t domain, power_vddio_volt_t volt)
+{
+ uint32_t regVal = (uint32_t)volt;
+
+ if (domain == kPOWER_VddIoAon)
+ {
+ regVal = ((regVal >> 3U) | (regVal & 0x1U)) << PMU_IO_PAD_PWR_CFG_GPIO_AON_V25_SHIFT;
+ PMU->IO_PAD_PWR_CFG =
+ (PMU->IO_PAD_PWR_CFG & ~(PMU_IO_PAD_PWR_CFG_GPIO_AON_V18_MASK | PMU_IO_PAD_PWR_CFG_GPIO_AON_V25_MASK)) |
+ regVal;
+ }
+ else
+ {
+ assert(domain <= kPOWER_VddIo3);
+
+ regVal <<= (PMU_IO_PAD_PWR_CFG_GPIO0_V25_SHIFT + (uint32_t)domain);
+ PMU->IO_PAD_PWR_CFG =
+ (PMU->IO_PAD_PWR_CFG &
+ ~(((uint32_t)PMU_IO_PAD_PWR_CFG_GPIO0_V18_MASK | (uint32_t)PMU_IO_PAD_PWR_CFG_GPIO0_V25_MASK)
+ << (uint32_t)domain)) |
+ regVal;
+ }
+}
+
+/**
+ * @brief Attach GPIO interrupt to NVIC vector table.
+ * Since 2 GPIO pins shares 1 IRQ number. Attaching one GPIO IRQ implicits
+ * detaching the sibling GPIO IRQ.
+ * @param pin : GPIO index.
+ */
+void POWER_AttachGpioIrq(uint32_t pin)
+{
+ uint32_t bit;
+ uint32_t value;
+
+ assert(pin < 50U);
+
+ bit = pin / 2U;
+ value = (pin & 1U) ^ 1U;
+
+ PMU->EXT_SEL_REG0 = (PMU->EXT_SEL_REG0 & ~(1UL << bit)) | (value << bit);
+}
+
+/**
+ * @brief Enable AON Domain Comparator.
+ * @param config : AON Comparator config data.
+ */
+void POWER_EnableAonComp(const power_aon_comp_config_t *config)
+{
+ assert(config);
+
+ PMU->PMIP_CMP_CTRL =
+ (PMU->PMIP_CMP_CTRL & ~(PMU_PMIP_CMP_CTRL_COMP_REF_SEL_MASK | PMU_PMIP_CMP_CTRL_COMP_DIFF_EN_MASK |
+ PMU_PMIP_CMP_CTRL_COMP_HYST_MASK)) |
+ PMU_PMIP_CMP_CTRL_COMP_REF_SEL(config->ref) | PMU_PMIP_CMP_CTRL_COMP_DIFF_EN(config->mode) |
+ PMU_PMIP_CMP_CTRL_COMP_HYST(config->hyst);
+ PMU->PMIP_CMP_CTRL |= PMU_PMIP_CMP_CTRL_COMP_EN_MASK;
+
+ while ((PMU->PMIP_CMP_CTRL & PMU_PMIP_CMP_CTRL_COMP_RDY_MASK) == 0U)
+ {
+ }
+}
+
+/**
+ * @brief Disable AON Domain Comparator.
+ */
+void POWER_DisableAonComp(void)
+{
+ PMU->PMIP_CMP_CTRL &= ~PMU_PMIP_CMP_CTRL_COMP_EN_MASK;
+}
+
+/**
+ * @brief Get AON Domain Comparator result.
+ * @return AON Comparator output value
+ */
+uint32_t POWER_GetAonCompValue(void)
+{
+ return (PMU->PMIP_CMP_CTRL & PMU_PMIP_CMP_CTRL_COMP_OUT_MASK) >> PMU_PMIP_CMP_CTRL_COMP_OUT_SHIFT;
+}
+
+/**
+ * @brief Set sleep mode on idle.
+ * @param mode : 0 ~ 4 stands for PM0 ~ PM4.
+ */
+void POWER_SetSleepMode(uint32_t mode)
+{
+ assert(mode <= 4U);
+
+ if (mode == 0U)
+ {
+ mode = 1U; /* PM0/PM1 is same */
+ }
+ /* set PMU basic mode */
+ PMU->PWR_MODE = PMU_PWR_MODE_PWR_MODE(mode - 1);
+
+ /* select deepsleep or not */
+ if (mode == 1U)
+ {
+ SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
+ }
+ else
+ {
+ SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+ }
+}
+
+/* Remove flash from continuous read mode and disable flash controller */
+static void FLASHC_Disable(void)
+{
+ uint32_t cacheMode;
+
+ if ((FLASHC->FCCR & FLASHC_FCCR_FLASHC_PAD_EN_MASK) != 0U)
+ {
+ cacheMode = FLASHC->FCCR & FLASHC_FCCR_CACHE_EN_MASK;
+ FLASHC->FCCR &= ~FLASHC_FCCR_CACHE_EN_MASK;
+
+ /* Check if continuous read mode is enabled */
+ if ((FLASHC->FCCR & FLASHC_FCCR_CMD_TYPE_MASK) == FLASHC_FCCR_CMD_TYPE(7U))
+ {
+ FLASHC->FCSR = FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK;
+ FLASHC->FCCR = (FLASHC->FCCR & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(13U);
+ while ((FLASHC->FCSR & FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK) == 0)
+ {
+ }
+ }
+ FLASHC->FCCR |= cacheMode;
+ PMU->LOW_PWR_CTRL &= ~PMU_LOW_PWR_CTRL_CACHE_LINE_FLUSH_MASK;
+ FLASHC->FCCR &= ~FLASHC_FCCR_FLASHC_PAD_EN_MASK;
+ }
+}
+
+static void FLASHC_Enable(void)
+{
+ FLASHC->FCCR &= ~FLASHC_FCCR_CACHE_LINE_FLUSH_MASK;
+ PMU->LOW_PWR_CTRL |= PMU_LOW_PWR_CTRL_CACHE_LINE_FLUSH_MASK;
+}
+
+static void FLASH_PowerDown(bool powerDown)
+{
+ /* Clear QSPI1 FIFO */
+ QSPI->CONF |= QSPI_CONF_FIFO_FLUSH_MASK;
+ while ((QSPI->CONF & QSPI_CONF_FIFO_FLUSH_MASK) != 0U)
+ {
+ }
+
+ /* Set Header count register: instruction counter, address counter, read mode counter and dummy counter */
+ QSPI->HDRCNT = 0x1U;
+ /* Set data in counter */
+ QSPI->DINCNT = 0U;
+
+ if (powerDown)
+ {
+ /* Set instruction */
+ QSPI->INSTR = 0xB9U;
+ }
+ else
+ {
+ /* Set instruction */
+ QSPI->INSTR = 0xABU;
+ }
+
+ /* Set QSPI1 write */
+ QSPI->CNTL |= QSPI_CNTL_SS_EN_MASK;
+ QSPI->CONF |= QSPI_CONF_RW_EN_MASK;
+ QSPI->CONF |= QSPI_CONF_XFER_START_MASK;
+
+ /* Stop QSPI1 transfer */
+ while ((QSPI->CNTL & (QSPI_CNTL_XFER_RDY_MASK | QSPI_CNTL_WFIFO_EMPTY_MASK)) !=
+ (QSPI_CNTL_XFER_RDY_MASK | QSPI_CNTL_WFIFO_EMPTY_MASK))
+ {
+ }
+ QSPI->CONF |= QSPI_CONF_XFER_STOP_MASK;
+ while ((QSPI->CONF & QSPI_CONF_XFER_START_MASK) == QSPI_CONF_XFER_START_MASK)
+ {
+ }
+ QSPI->CNTL &= ~QSPI_CNTL_SS_EN_MASK;
+}
+
+static void POWER_SwitchOffIo(uint32_t mode, uint32_t excludeIo)
+{
+ s_ioPadPwrCfg = PMU->IO_PAD_PWR_CFG;
+
+ /* Turn OFF different power domains. */
+ /* This is done to make wakeup from PM2
+ * uisng Ext Pin 0 and Ext Pin 1.
+ * Please note that PM3 wakeup does
+ * not work after this change.
+ */
+ PMU->IO_PAD_PWR_CFG &= ~PMU_IO_PAD_PWR_CFG_GPIO_AON_PDB_MASK;
+ if (mode == 2U)
+ {
+ PMU->IO_PAD_PWR_CFG &= ~((~excludeIo & 0xFU) << PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_SHIFT);
+ }
+ else
+ {
+ PMU->IO_PAD_PWR_CFG &= ~(0xFUL << PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_SHIFT);
+ }
+}
+
+static void POWER_RestoreIo(void)
+{
+ PMU->IO_PAD_PWR_CFG = s_ioPadPwrCfg;
+}
+
+static void POWER_SaveDeviceState(uint32_t mode)
+{
+ s_clockContext.WLAN_CTRL = PMU->WLAN_CTRL;
+ s_clockContext.SFLL_CTRL0 = PMU->SFLL_CTRL0;
+ s_clockContext.SFLL_CTRL1 = PMU->SFLL_CTRL1;
+ s_clockContext.AUPLL_CTRL0 = PMU->AUPLL_CTRL0;
+ s_clockContext.AUPLL_CTRL1 = PMU->AUPLL_CTRL1;
+ s_clockContext.CLK_SRC = PMU->CLK_SRC;
+
+ if (mode == 3U)
+ {
+ /* Save Flash controller configuration
+ * This needs to be restored on exit from PM3
+ */
+ s_flashContext.FCCR = FLASHC->FCCR;
+ s_flashContext.FCTR = FLASHC->FCTR;
+ s_flashContext.FCACR = FLASHC->FCACR;
+ s_flashContext.FAOFFR = FLASHC->FAOFFR;
+ /* Save QSPI configuration */
+ s_flashContext.CONF = QSPI->CONF;
+ s_flashContext.TIMING = QSPI->TIMING;
+ /* Save clock source and div setting for peripherals */
+ s_clockContext.UART_CLK_SEL = PMU->UART_CLK_SEL;
+ s_clockContext.GPT0_CTRL = PMU->GPT0_CTRL;
+ s_clockContext.GPT1_CTRL = PMU->GPT1_CTRL;
+ s_clockContext.GPT2_CTRL = PMU->GPT2_CTRL;
+ s_clockContext.GPT3_CTRL = PMU->GPT3_CTRL;
+ s_clockContext.PERI_CLK_SRC = PMU->PERI_CLK_SRC;
+ s_clockContext.CAU_CLK_SEL = PMU->CAU_CLK_SEL;
+ s_clockContext.UART_FAST_CLK_DIV = PMU->UART_FAST_CLK_DIV;
+ s_clockContext.UART_SLOW_CLK_DIV = PMU->UART_SLOW_CLK_DIV;
+ s_clockContext.MCU_CORE_CLK_DIV = PMU->MCU_CORE_CLK_DIV;
+ s_clockContext.PERI0_CLK_DIV = PMU->PERI0_CLK_DIV;
+ s_clockContext.PERI1_CLK_DIV = PMU->PERI1_CLK_DIV;
+ s_clockContext.PERI2_CLK_DIV = PMU->PERI2_CLK_DIV;
+ s_clockContext.PERI3_CTRL = PMU->PERI3_CTRL;
+ }
+}
+
+static void POWER_RestoreDeviceState(uint32_t mode)
+{
+ uint32_t refClk;
+
+ if (mode == 3U)
+ {
+ /* Restore clock source and div setting for peripherals */
+ PMU->UART_CLK_SEL = s_clockContext.UART_CLK_SEL;
+ PMU->GPT0_CTRL = s_clockContext.GPT0_CTRL;
+ PMU->GPT1_CTRL = s_clockContext.GPT1_CTRL;
+ PMU->GPT2_CTRL = s_clockContext.GPT2_CTRL;
+ PMU->GPT3_CTRL = s_clockContext.GPT3_CTRL;
+ PMU->PERI_CLK_SRC = s_clockContext.PERI_CLK_SRC;
+ PMU->CAU_CLK_SEL = s_clockContext.CAU_CLK_SEL;
+ PMU->UART_FAST_CLK_DIV = s_clockContext.UART_FAST_CLK_DIV;
+ PMU->UART_SLOW_CLK_DIV = s_clockContext.UART_SLOW_CLK_DIV;
+ PMU->MCU_CORE_CLK_DIV = s_clockContext.MCU_CORE_CLK_DIV;
+ PMU->PERI0_CLK_DIV = s_clockContext.PERI0_CLK_DIV;
+ PMU->PERI1_CLK_DIV = s_clockContext.PERI1_CLK_DIV;
+ PMU->PERI2_CLK_DIV = s_clockContext.PERI2_CLK_DIV;
+ PMU->PERI3_CTRL = s_clockContext.PERI3_CTRL;
+ /* Restore Flash controller configuration. */
+ FLASHC->FCTR = s_flashContext.FCTR;
+ FLASHC->FCACR = s_flashContext.FCACR;
+ FLASHC->FAOFFR = s_flashContext.FAOFFR;
+ FLASHC->FCCR = s_flashContext.FCCR;
+ /* Restore QSPI configuration */
+ QSPI->CONF = s_flashContext.CONF;
+ QSPI->TIMING = s_flashContext.TIMING;
+ }
+
+ refClk = s_clockContext.WLAN_CTRL & (7UL << PMU_WLAN_CTRL_REFCLK_SYS_REQ_SHIFT);
+ PMU->WLAN_CTRL = s_clockContext.WLAN_CTRL;
+ /* Wait reference clock ready */
+ while ((PMU->WLAN_CTRL & (refClk << 3U)) != (refClk << 3U))
+ {
+ }
+
+ PMU->SFLL_CTRL1 = s_clockContext.SFLL_CTRL1;
+ PMU->SFLL_CTRL0 = s_clockContext.SFLL_CTRL0;
+ if ((s_clockContext.SFLL_CTRL0 & PMU_SFLL_CTRL0_SFLL_PU_MASK) != 0U)
+ {
+ /* Wait PLL ready */
+ while ((PMU->CLK_RDY & PMU_CLK_RDY_PLL_CLK_RDY_MASK) == 0U)
+ {
+ }
+ }
+
+ PMU->AUPLL_CTRL1 = s_clockContext.AUPLL_CTRL1;
+ PMU->AUPLL_CTRL0 = s_clockContext.AUPLL_CTRL0;
+ if ((s_clockContext.AUPLL_CTRL0 & PMU_AUPLL_CTRL0_PU_MASK) != 0U)
+ {
+ /* Wait PLL ready */
+ while ((PMU->CLK_RDY & PMU_CLK_RDY_PLL_AUDIO_RDY_MASK) == 0U)
+ {
+ }
+ }
+ if ((s_clockContext.CLK_SRC & PMU_CLK_SRC_SYS_CLK_SEL_MASK) == (uint32_t)kCLOCK_SysClkSrcMainXtal)
+ {
+ PMU->CLK_SRC = PMU_CLK_SRC_SYS_CLK_SEL(kCLOCK_SysClkSrcRC32M_3);
+ }
+ PMU->CLK_SRC = s_clockContext.CLK_SRC;
+}
+
+/* Prepare to go to low power
+ * Change clock source to RC32M
+ * Switch off PLLs, XTAL
+ * Set Deep sleep bit in SRC register
+ * Initiate state change
+ */
+static void POWER_PrePowerMode(uint32_t mode, uint32_t excludeIo)
+{
+ assert((mode >= 1U) && (mode <= 4U));
+ /* Turn off Systick to avoid interrupt
+ * when entering low power state
+ */
+ s_systickContext.CTRL = SysTick->CTRL;
+ s_systickContext.LOAD = SysTick->LOAD;
+ SysTick->CTRL = 0;
+ SysTick->LOAD = 0;
+
+ if (mode >= 2U)
+ {
+ POWER_SaveDeviceState(mode);
+
+ if (mode == 3U)
+ {
+ /* On exit from PM3 bootrom jumps to address
+ * in pm3_entryaddr in NVRAM.
+ */
+ pm3_entryaddr = (uint32_t *)0x480C0000;
+ POWER_SaveNvicState();
+ FLASHC_Disable();
+ }
+
+ /* Switch clock source to RC 32Mhz */
+ PMU->CLK_SRC |= 1U;
+
+ /* Disable xtal */
+ PMU->WLAN_CTRL &= ~(PMU_WLAN_CTRL_REFCLK_SYS_REQ_MASK | PMU_WLAN_CTRL_REFCLK_AUD_REQ_MASK |
+ PMU_WLAN_CTRL_REFCLK_USB_REQ_MASK);
+
+ /* Power down analog unit */
+ if (mode == 2U)
+ {
+ PMU->ANA_GRP_CTRL0 &= ~PMU_ANA_GRP_CTRL0_PU_MASK;
+ }
+
+ /* Disable Audio PLL */
+ PMU->AUPLL_CTRL0 &= ~PMU_AUPLL_CTRL0_PU_MASK;
+
+ /* Disable System PLL */
+ PMU->SFLL_CTRL0 &= ~PMU_SFLL_CTRL0_SFLL_PU_MASK;
+
+ FLASH_PowerDown(true);
+
+ POWER_SwitchOffIo(mode, excludeIo);
+ }
+
+ POWER_SetSleepMode(mode);
+}
+
+static void POWER_PostPowerMode(uint32_t mode)
+{
+ assert((mode >= 1U) && (mode <= 4U));
+
+ POWER_SetSleepMode(1U);
+
+ if (mode >= 2U)
+ {
+ if (mode == 2U)
+ {
+ PMU->ANA_GRP_CTRL0 |= PMU_ANA_GRP_CTRL0_PU_MASK;
+ }
+
+ POWER_RestoreIo();
+
+ FLASH_PowerDown(false);
+
+ POWER_RestoreDeviceState(mode);
+
+ if (mode == 3U)
+ {
+ POWER_RestoreNvicState();
+ FLASHC_Enable();
+ }
+ }
+
+ SysTick->CTRL = s_systickContext.CTRL;
+ SysTick->LOAD = s_systickContext.LOAD;
+}
+
+#if defined(__GNUC__)
+void asm_mcu_pm3()
+{
+ /* Address: 0x480C0008 is the address in NVRAM which holds address
+ * where control returns after exit from PM3*/
+ /* All general purpose registers and special registers
+ * are saved by pushing them on current thread's stack
+ * (psp is being used as sp) and finally SP is saved in NVRAM location*/
+
+ __asm volatile(
+ "push {r1}\n"
+ "mrs r1 , msp\n"
+ "push {r1}\n"
+ "mrs r1 , basepri\n"
+ "push {r1}\n"
+ "mrs r1 , primask\n"
+ "push {r1}\n"
+ "mrs r1 , faultmask\n"
+ "push {r1}\n"
+ "mrs r1 , control\n"
+ "push {r1}\n"
+ "push {r0-r12}\n"
+ "push {lr}\n"
+ "ldr r0 , =0x480C0040\n"
+ "str sp , [r0]\n"
+ "ldr r0 , =pm3_entryaddr\n"
+ "mov r1 , pc\n"
+ "add r1 , r1 , #20\n"
+ "ldr r2 , [r0]\n"
+ "str r1 , [r2]\n");
+ /*
+ * Execute WFI to generate a state change
+ * and system is in an unresponsive state
+ * press wakeup key to get it out of standby
+ * If time_to_standby is set to valid value
+ * RTC is programmed and RTC generates
+ * a wakeup signal.
+ */
+ __asm volatile("wfi");
+
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+
+ /* When system exits PM3 all registers need to be
+ * restored as they are lost.
+ * After exit from PM3, control register is 0
+ * This indicates that msp is being used as sp
+ * psp is populated with saved_sp_addr value.
+ * When control register is popped, system starts using
+ * psp as sp and thread stack is now accessible.
+ */
+
+ /*
+ * When MCU enters PM3 all Core registers
+ * r0-r12
+ * lr
+ * control
+ * primask
+ * faultmask
+ * basepri
+ * psp
+ * msp
+ * are lost (ZERO) as MCU power is tuned off
+ * On wakeup from PM3, this piece of code restores
+ * these registers which were saved before entry.
+ * The location of saving this register was on stack
+ * This stack was addressed as "sp" -> "psp".
+ * On exit "control" register becomes zero.
+ * Bit 1 of control register determines which register
+ * of "msp" or "psp" is mapped to "sp".
+ * If "control" register bit 1 is ZERO then use "msp"
+ * mapped to "sp" and restore the registers by popping them.
+ * If "control" register bit 1 is not ZERO then use "psp"
+ * mapped to "sp" and restore the registers by popping them.
+ *
+ */
+ __asm volatile(
+ "mrs r0 , control\n"
+ "and r0 , #0x2\n"
+ "cmp r0 , #0x2\n"
+ "beq.w psp_lbl\n"
+ "ldr r0 , =0x480C0040\n"
+ "ldr sp , [r0]\n"
+ "pop {lr}\n"
+ "ldr r1 , [r0]\n"
+ "msr psp , r1\n"
+ "pop { r0-r12}\n"
+ "mov r1 , sp\n"
+ "add r1 , r1, #4\n"
+ "msr psp , r1\n"
+ "pop {r1}\n"
+ "msr control , r1\n"
+ "pop {r1}\n"
+ "msr faultmask , r1\n"
+ "pop {r1}\n"
+ "msr primask , r1\n"
+ "pop {r1}\n"
+ "msr basepri , r1\n"
+ "pop {r1}\n"
+ "msr msp , r1\n"
+ "pop {r1}\n"
+ "b.w exit_lbl\n"
+ "psp_lbl:\n"
+ "pop {lr}\n"
+ "pop {r0-r12}\n"
+ "pop {r1}\n"
+ "pop {r1}\n"
+ "msr faultmask , r1\n"
+ "pop {r1}\n"
+ "msr primask , r1\n"
+ "pop {r1}\n"
+ "msr basepri , r1\n"
+ "pop {r1}\n"
+ "msr msp , r1\n"
+ "pop {r1}\n"
+ "exit_lbl:\n");
+ /* In the assembly code above adding 4 in r1 is done to
+ * populate "psp" before "control" register is popped.
+ * This is needed as "control" register has bit 1 set to 1
+ * and it indicates that "sp" will be mapped to "psp" after
+ * the instruction that pops "control" register.
+ */
+}
+#elif defined(__ICCARM__)
+void asm_mcu_pm3()
+{
+ __asm volatile("push {r0-r12}");
+ /* Address: 0x480C0008 is the address in NVRAM which holds address
+ * where control returns after exit from PM3*/
+ /* All general purpose registers and special registers
+ * are saved by pushing them on current thread's stack
+ * (psp is being used as sp) and finally SP is saved in NVRAM location*/
+
+ /* Important Note:
+ * IAR tool chain does not allow following syntax
+ *
+ * LDR Rx, =variable_name
+ * or
+ * LDR Ry, =0x10000000
+ *
+ * To overcome this issue a workaround is done to
+ * Load 0x480C0040 in a register using
+ * following instructions
+ *
+ * MOV, LSL and ADD
+ *
+ * 0x480C0040 will hold Stack Pointer
+ * before entering PM3
+ */
+
+ __asm volatile("mov r5, %0\n" : : "r"(&pm3_entryaddr));
+
+ __asm volatile(
+ "push {r1}\n"
+ "mrs r1 , msp\n"
+ "push {r1}\n"
+ "mrs r1 , basepri\n"
+ "push {r1}\n"
+ "mrs r1 , primask\n"
+ "push {r1}\n"
+ "mrs r1 , faultmask\n"
+ "push {r1}\n"
+ "mrs r1 , control\n"
+ "push {r1}\n"
+ "push {r0-r12}\n"
+ "push {lr}\n"
+ "mov r0 , #0x480C\n"
+ "lsl r0 , r0 , #16\n"
+ "add r0 , r0 , #0x0040\n"
+ "str sp , [r0]\n"
+ "mov r0 , r5\n"
+ "mov r1 , pc\n"
+ "add r1 , r1 , #20\n"
+ "ldr r2 , [r0]\n"
+ "str r1 , [r2]\n");
+ /*
+ * Execute WFI to generate a state change
+ * and system is in an unresponsive state
+ * press wakeup key to get it out of standby
+ * If time_to_standby is set to valid value
+ * RTC is programmed and RTC generates
+ * a wakeup signal.
+ */
+ __asm volatile("wfi");
+
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+ __asm volatile("nop");
+
+ /* When system exits PM3 all registers need to be
+ * restored as they are lost.
+ * After exit from PM3, control register is 0
+ * This indicates that msp is being used as sp
+ * psp is populated with saved_sp_addr value.
+ * When control register is popped, system starts using
+ * psp as sp and thread stack is now accessible.
+ */
+
+ /*
+ * When MCU enters PM3 all Core registers
+ * r0-r12
+ * lr
+ * control
+ * primask
+ * faultmask
+ * basepri
+ * psp
+ * msp
+ * are lost (ZERO) as MCU power is tuned off
+ * On wakeup from PM3, this piece of code restores
+ * these registers which were saved before entry.
+ * The location of saving this register was on stack
+ * This stack was addressed as "sp" -> "psp".
+ * On exit "control" register becomes zero.
+ * Bit 1 of control register determines which register
+ * of "msp" or "psp" is mapped to "sp".
+ * If "control" register bit 1 is ZERO then use "msp"
+ * mapped to "sp" and restore the registers by popping them.
+ * If "control" register bit 1 is not ZERO then use "psp"
+ * mapped to "sp" and restore the registers by popping them.
+ *
+ */
+ __asm volatile(
+ "mrs r0 , control\n"
+ "and r0 , r0 , #0x2\n"
+ "cmp r0 , #0x2\n"
+ "beq.w psp_lbl\n"
+ "mov r0 , #0x480C\n"
+ "lsl r0 , r0 , #16\n"
+ "add r0 , r0 , #0x0040\n"
+ "ldr sp , [r0]\n"
+ "pop {lr}\n"
+ "ldr r1 , [r0]\n"
+ "msr psp , r1\n"
+ "pop { r0-r12}\n"
+ "mov r1 , sp\n"
+ "add r1 , r1, #4\n"
+ "msr psp , r1\n"
+ "pop {r1}\n"
+ "msr control , r1\n"
+ "pop {r1}\n"
+ "msr faultmask , r1\n"
+ "pop {r1}\n"
+ "msr primask , r1\n"
+ "pop {r1}\n"
+ "msr basepri , r1\n"
+ "pop {r1}\n"
+ "msr msp , r1\n"
+ "pop {r1}\n"
+ "b.w exit_lbl\n"
+ "psp_lbl:\n"
+ "pop {lr}\n"
+ "pop {r0-r12}\n"
+ "pop {r1}\n"
+ "pop {r1}\n"
+ "msr faultmask , r1\n"
+ "pop {r1}\n"
+ "msr primask , r1\n"
+ "pop {r1}\n"
+ "msr basepri , r1\n"
+ "pop {r1}\n"
+ "msr msp , r1\n"
+ "pop {r1}\n"
+ "exit_lbl:\n");
+ __asm volatile("pop {r0-r12}");
+ /* In the assembly code above adding 4 in r1 is done to
+ * populate "psp" before "control" register is popped.
+ * This is needed as "control" register has bit 1 set to 1
+ * and it indicates that "sp" will be mapped to "psp" after
+ * the instruction that pops "control" register.
+ */
+}
+#else
+#error compiler not supported
+#endif
+
+static void ps_wait(int cycle)
+{
+ __asm volatile(
+ "loop:\n"
+ "nop\n"
+ "SUB r0 , r0 , #1\n"
+ "CMP r0 , #0\n"
+ "BNE.W loop\n");
+}
+
+void POWER_EnterPowerMode(uint32_t mode, uint32_t excludeIo)
+{
+ assert(mode <= 4U);
+
+ if (mode >= 1U)
+ {
+ POWER_PrePowerMode(mode, excludeIo);
+ if (mode >= 2U)
+ {
+ ps_wait(10);
+ }
+ if (mode == 3U)
+ {
+ asm_mcu_pm3();
+ }
+ else
+ {
+ __WFI();
+ }
+ POWER_PostPowerMode(mode);
+ }
+}
+
+void POWER_TrimBandgapRefVoltage(power_bandgap_ref_voltage_t refVoltage)
+{
+ uint32_t tmp32;
+
+ tmp32 = BG->CTRL;
+ tmp32 &= ~BG_CTRL_RES_TRIM_MASK;
+ tmp32 |= BG_CTRL_RES_TRIM(refVoltage);
+ BG->CTRL = tmp32;
+}
diff --git a/devices/88MW320/drivers/fsl_power.h b/devices/88MW320/drivers/fsl_power.h
new file mode 100644
index 000000000..c7d46117e
--- /dev/null
+++ b/devices/88MW320/drivers/fsl_power.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup power
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief POWER driver version 2.1.0. */
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*@}*/
+
+/*!
+ * @brief Pin edge for wakeup.
+ */
+typedef enum _power_wakeup_edge
+{
+ kPOWER_WakeupEdgeLow = 0U, /*!< Wakeup on pin low level. */
+ kPOWER_WakeupEdgeHigh = 1U, /*!< Wakeup on pin high level. */
+} power_wakeup_edge_t;
+
+/*!
+ * @brief Wakeup pin.
+ */
+typedef enum _power_wakeup_pin
+{
+ kPOWER_WakeupPin0 = 0U, /*!< Wakeup0 pin - GPIO22. */
+ kPOWER_WakeupPin1 = 1U, /*!< Wakeup1 pin - GPIO23. */
+} power_wakeup_pin_t;
+
+/*!
+ * @brief Reset cause.
+ */
+typedef enum _power_reset_cause
+{
+ kPOWER_ResetCauseVbatBrownout = 1U << 0U, /*!< VBAT power brown-out detected. */
+ kPOWER_ResetCauseAv12Brownout = 1U << 1U, /*!< AV12 power brown-out detected. */
+ kPOWER_ResetCauseAv18Brownout = 1U << 2U, /*!< AV18 power brown-out detected. */
+ kPOWER_ResetCauseSysResetReq = 1U << 3U, /*!< CM4 system soft reset request. */
+ kPOWER_ResetCauseLockup = 1U << 4U, /*!< CM4 locked up. */
+ kPOWER_ResetCauseWdt = 1U << 5U, /*!< watchdog timer. */
+ kPOWER_ResetCauseAll = 0x3FU, /*!< All reset causes. Used in POWER_ClearResetCause(). */
+} power_reset_cause_t;
+
+/*!
+ * @brief Wakeup source.
+ */
+typedef enum _power_wakeup_src
+{
+ kPOWER_WakeupSrcPin0 = 1U << 0U, /*!< Wakeup0 pin. */
+ kPOWER_WakeupSrcPin1 = 1U << 1U, /*!< Wakeup1 pin. */
+ kPOWER_WakeupSrcWlan = 1U << 2U, /*!< WLAN interrupt. */
+ kPOWER_WakeupSrcRtc = 1U << 3U, /*!< RTC interrupt. */
+ kPOWER_WakeupSrcComp = 1U << 4U, /*!< PMIP Comp interrupt. */
+ kPOWER_WakeupSrcAll = 0x1FU, /*!< All wakeup sources. Used in POWER_ClearWakeupSource(). */
+} power_wakeup_src_t;
+
+/*!
+ * @brief Wakeup interrupt mask.
+ */
+typedef enum _power_wakeup_mask
+{
+ kPOWER_WakeupMaskPin0 = 1U << 3U, /*!< Wakeup0 pin. */
+ kPOWER_WakeupMaskPin1 = 1U << 4U, /*!< Wakeup1 pin. */
+ kPOWER_WakeupMaskRtc = 1U << 5U, /*!< RTC interrupt. */
+ kPOWER_WakeupMaskComp = 1U << 6U, /*!< PMIP Comp interrupt. */
+ kPOWER_WakeupMaskWlan = 1U << 7U, /*!< WLAN interrupt. */
+ kPOWER_WakeupMaskAll = 0xF8U, /*!< All wakeup interrupt mask. */
+} power_wakeup_mask_t;
+
+/*!
+ * @brief IO domain.
+ */
+typedef enum _power_vddio
+{
+ kPOWER_VddIo0 = 0U, /*!< VDDIO0 pad group. */
+ kPOWER_VddIo1 = 1U, /*!< VDDIO1 pad group. */
+ kPOWER_VddIo2 = 2U, /*!< VDDIO2 pad group. */
+ kPOWER_VddIo3 = 3U, /*!< VDDIO3 pad group. */
+ kPOWER_VddIoAon = 19U, /*!< Always on pad group. */
+} power_vddio_t;
+
+/*!
+ * @brief IO domain voltage level.
+ */
+typedef enum _power_vddio_volt
+{
+ kPOWER_VddioVolt3V3 = 0x00U, /*!< VDDIO 3.3V */
+ kPOWER_VddioVolt2V5 = 0x01U, /*!< VDDIO 2.5V */
+ kPOWER_VddioVolt1V8 = 0x10U, /*!< VDDIO 1.8V */
+} power_vddio_volt_t;
+
+/**
+ * @brief AON Comparator Hysteresis list
+ */
+typedef enum _power_aon_comp_hyst
+{
+ kPOWER_AonCompHyst_0 = 0x0, /*!< Ulpcomp hysteresis level 0 */
+ kPOWER_AonCompHyst_1 = 0x1, /*!< Ulpcomp hysteresis level 1 */
+ kPOWER_AonCompHyst_2 = 0x2, /*!< Ulpcomp hysteresis level 2 */
+ kPOWER_AonCompHyst_3 = 0x3, /*!< Ulpcomp hysteresis level 3 */
+} power_aon_comp_hyst_t;
+
+/*!
+ * @brief AON Comparator mode.
+ */
+typedef enum _power_aon_comp_mode
+{
+ kPOWER_AonCompMode_SingleEnded = 0U,
+ kPOWER_AonCompMode_Differential = 1U,
+} power_aon_comp_mode_t;
+
+/*!
+ * @brief AON Comparator Reference for Single-Ended mode.
+ */
+typedef enum _power_aon_comp_ref
+{
+ kPOWER_AonCompRef_0V2 = 0U, /*!< 0.2V */
+ kPOWER_AonCompRef_0V4 = 1U, /*!< 0.4 */
+ kPOWER_AonCompRef_0V6 = 2U, /*!< 0.6V */
+ kPOWER_AonCompRef_0V8 = 3U, /*!< 0.8V */
+ kPOWER_AonCompRef_1V0 = 4U, /*!< 1.0V */
+ kPOWER_AonCompRef_1V2 = 5U, /*!< 1.2V */
+ kPOWER_AonCompRef_1V4 = 6U, /*!< 1.4V */
+ kPOWER_AonCompRef_1V6 = 7U, /*!< 1.6V */
+} power_aon_comp_ref_t;
+
+/*!
+ * @brief Internal bandgap reference voltage trim value.
+ */
+typedef enum _power_bandgap_ref_voltage
+{
+ kPOWER_BGRefVoltage1P159V = 0U, /*!< Trim reference voltage to 1.159V. */
+ kPOWER_BGRefVoltage1P163V, /*!< Trim reference voltage to 1.163V. */
+ kPOWER_BGRefVoltage1P168V, /*!< Trim reference voltage to 1.168V. */
+ kPOWER_BGRefVoltage1P172V, /*!< Trim reference voltage to 1.172V. */
+ kPOWER_BGRefVoltage1P177V, /*!< Trim reference voltage to 1.177V. */
+ kPOWER_BGRefVoltage1P181V, /*!< Trim reference voltage to 1.181V. */
+ kPOWER_BGRefVoltage1P186V, /*!< Trim reference voltage to 1.186V. */
+ kPOWER_BGRefVoltage1P190V, /*!< Trim reference voltage to 1.190V. */
+ kPOWER_BGRefVoltage1P194V, /*!< Trim reference voltage to 1.194V. */
+ kPOWER_BGRefVoltage1P199V, /*!< Trim reference voltage to 1.199V. */
+ kPOWER_BGRefVoltage1P204V, /*!< Trim reference voltage to 1.204V. */
+ kPOWER_BGRefVoltage1P208, /*!< Trim reference voltage to 1.208V. */
+ kPOWER_BGRefVoltage1P213V, /*!< Trim reference voltage to 1.213V. */
+ kPOWER_BGRefVoltage1P217V, /*!< Trim reference voltage to 1.217V. */
+ kPOWER_BGRefVoltage1P222V, /*!< Trim reference voltage to 1.222V. */
+ kPOWER_BGRefVoltage1P226V, /*!< Trim reference voltage to 1.226V. */
+} power_bandgap_ref_voltage_t;
+
+/*!
+ * @brief AON Comparator config structure.
+ */
+typedef struct _power_aon_comp_config
+{
+ power_aon_comp_hyst_t hyst;
+ power_aon_comp_mode_t mode;
+ power_aon_comp_ref_t ref;
+} power_aon_comp_config_t;
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @brief Configure pin edge for wakeup
+ * @param pin : Wakeup pin
+ * @param edge : Pin level for wakeup
+ */
+__STATIC_INLINE void POWER_ConfigWakeupPin(power_wakeup_pin_t pin, power_wakeup_edge_t edge)
+{
+ PMU->WAKEUP_EDGE_DETECT = (PMU->WAKEUP_EDGE_DETECT & ~(1U << (uint8_t)pin)) | ((uint8_t)edge << (uint8_t)pin);
+}
+
+/**
+ * @brief Get last reset cause
+ * @return Or'ed cause of \ref power_reset_cause_t
+ */
+__STATIC_INLINE uint32_t POWER_GetResetCause(void)
+{
+ return PMU->LAST_RST_CAUSE & (uint32_t)kPOWER_ResetCauseAll;
+}
+
+/**
+ * @brief Clear last reset cause
+ * @param cause : A bitmask of of \ref power_reset_cause_t
+ */
+__STATIC_INLINE void POWER_ClearResetCause(uint32_t cause)
+{
+ assert((cause & ~(uint32_t)kPOWER_ResetCauseAll) == 0U);
+
+ PMU->LAST_RST_CLR = cause;
+}
+
+/**
+ * @brief Get last wakeup source
+ * @return Bitmask of \ref power_wakeup_src_t
+ */
+__STATIC_INLINE uint32_t POWER_GetWakeupSource(void)
+{
+ return PMU->WAKEUP_STATUS & (uint32_t)kPOWER_WakeupSrcAll;
+}
+
+/**
+ * @brief Clear wakeup source
+ * @param src : A bitmask of \ref power_wakeup_src_t
+ */
+__STATIC_INLINE void POWER_ClearWakeupSource(uint32_t src)
+{
+ assert((src & ~(uint32_t)kPOWER_WakeupSrcAll) == 0U);
+
+ PMU->WAKE_SRC_CLR = src;
+}
+
+/**
+ * @brief Enable the Wakeup interrupts.
+ * @param interruptMask : A bitmask of interrupts to enable. See \ref power_wakeup_mask_t.
+ */
+__STATIC_INLINE void POWER_EnableWakeup(uint32_t interruptMask)
+{
+ assert((interruptMask & ~(uint32_t)kPOWER_WakeupMaskAll) == 0U);
+
+ PMU->WAKEUP_MASK |= interruptMask;
+}
+
+/**
+ * @brief Disable the Wakeup interrupts.
+ * @param interruptMask : A bitmask of interrupts to disable. See \ref power_wakeup_mask_t.
+ */
+__STATIC_INLINE void POWER_DisableWakeup(uint32_t interruptMask)
+{
+ assert((interruptMask & ~(uint32_t)kPOWER_WakeupMaskAll) == 0U);
+
+ PMU->WAKEUP_MASK &= ~interruptMask;
+}
+
+/**
+ * @brief Set sleep mode on idle.
+ * @param mode : 0 ~ 4 stands for PM0 ~ PM4.
+ */
+void POWER_SetSleepMode(uint32_t mode);
+
+/**
+ * @brief Switch system into certain power mode.
+ * @param mode : 0 ~ 4 stands for PM0 ~ PM4.
+ * @param excludeIo: IO domains bitmask to keep unchanged during PM2.
+ */
+void POWER_EnterPowerMode(uint32_t mode, uint32_t excludeIo);
+
+/**
+ * @brief Power on IO domain.
+ * @param domain : IO domain to power on.
+ */
+__STATIC_INLINE void POWER_PowerOnVddio(power_vddio_t domain)
+{
+ assert(domain <= kPOWER_VddIo3);
+
+ PMU->IO_PAD_PWR_CFG |= (1UL << (PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_SHIFT + (uint32_t)domain));
+}
+
+/**
+ * @brief Power off IO domain.
+ * @param domain : IO domain to power off.
+ */
+__STATIC_INLINE void POWER_PowerOffVddio(power_vddio_t domain)
+{
+ assert(domain <= kPOWER_VddIo3);
+
+ /* Both pad regulator and IO domain powered off */
+ PMU->IO_PAD_PWR_CFG &= ~((1UL << (PMU_IO_PAD_PWR_CFG_GPIO0_LOW_VDDB_SHIFT + (uint32_t)domain)) |
+ (1UL << (PMU_IO_PAD_PWR_CFG_GPIO0_PDB_SHIFT + (uint32_t)domain)));
+}
+
+/**
+ * @brief Power on IO domain pad regulator.
+ * @param domain : IO domain to power on.
+ */
+void POWER_PowerOnVddioPad(power_vddio_t domain);
+
+/**
+ * @brief Power off IO domain pad regulator.
+ * @param domain : IO domain to power off.
+ */
+void POWER_PowerOffVddioPad(power_vddio_t domain);
+
+/**
+ * @brief Set IO domain pad voltage.
+ * @param domain : IO domain.
+ * @param volt : Voltage level to be set.
+ */
+void POWER_SetVddioPadVolt(power_vddio_t domain, power_vddio_volt_t volt);
+
+/**
+ * @brief Power on WLAN.
+ */
+__STATIC_INLINE void POWER_PowerOnWlan(void)
+{
+ PMU->WLAN_CTRL |= PMU_WLAN_CTRL_PD_MASK;
+}
+
+/**
+ * @brief Power off WLAN.
+ */
+__STATIC_INLINE void POWER_PowerOffWlan(void)
+{
+ PMU->WLAN_CTRL &= ~PMU_WLAN_CTRL_PD_MASK;
+}
+
+/**
+ * @brief Enable MCI wakeup WLAN
+ */
+__STATIC_INLINE void PMU_EnableWlanWakeup(void)
+{
+ PMU->WLAN_CTRL1 |= PMU_WLAN_CTRL1_MCI_WL_WAKEUP_MASK;
+}
+
+/**
+ * @brief Disable MCI wakeup WLAN
+ */
+__STATIC_INLINE void PMU_DisableWlanWakeup(void)
+{
+ PMU->WLAN_CTRL1 &= ~PMU_WLAN_CTRL1_MCI_WL_WAKEUP_MASK;
+}
+
+/**
+ * @brief Attach GPIO interrupt to NVIC vector table.
+ * Since 2 GPIO pins shares 1 IRQ number. Attaching one GPIO IRQ implicits
+ * detaching the sibling GPIO IRQ.
+ * @param pin : GPIO index.
+ */
+void POWER_AttachGpioIrq(uint32_t pin);
+
+/**
+ * @brief Enable AON Domain Comparator.
+ * @param config : AON Comparator config data.
+ */
+void POWER_EnableAonComp(const power_aon_comp_config_t *config);
+
+/**
+ * @brief Disable AON Domain Comparator.
+ */
+void POWER_DisableAonComp(void);
+
+/**
+ * @brief Get AON Domain Comparator result.
+ * @return AON Comparator output value
+ */
+uint32_t POWER_GetAonCompValue(void);
+
+/**
+ * @brief Power up internal bandgap.
+ */
+__STATIC_INLINE void POWER_PowerUpBandgap(void)
+{
+ BG->CTRL &= ~BG_CTRL_PD_MASK;
+}
+
+/**
+ * @brief Power down internal bandgap.
+ */
+__STATIC_INLINE void POWER_PowerDownBandgap(void)
+{
+ BG->CTRL |= BG_CTRL_PD_MASK;
+}
+
+/**
+ * @brief Trim internal bandgap reference voltage.
+ *
+ * @param refVoltage The reference voltage value to trim, please refer to @ref power_bandgap_ref_voltage_t for details.
+ */
+void POWER_TrimBandgapRefVoltage(power_bandgap_ref_voltage_t refVoltage);
+
+/**
+ * @brief Check internal bandgap ready status
+ *
+ * @retval true Internal bandgap is ready.
+ * @retval false Internal bandgap is not ready.
+ */
+__STATIC_INLINE bool POWER_CheckBandgapReady(void)
+{
+ return ((BG->STATUS & BG_STATUS_RDY_MASK) == BG_STATUS_RDY_MASK);
+}
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_POWER_H_ */
diff --git a/devices/88MW320/fsl_device_registers.h b/devices/88MW320/fsl_device_registers.h
new file mode 100644
index 000000000..2243de411
--- /dev/null
+++ b/devices/88MW320/fsl_device_registers.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_88MW320_A0_NAPC))
+
+#define MW320_SERIES
+
+/* CMSIS-style register definitions */
+#include "88MW320.h"
+/* CPU specific feature definitions */
+#include "88MW320_features.h"
+
+#else
+#error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/
diff --git a/devices/88MW320/gcc/88MW320_xx_xxxx_flash.ld b/devices/88MW320/gcc/88MW320_xx_xxxx_flash.ld
new file mode 100644
index 000000000..f760a92e7
--- /dev/null
+++ b/devices/88MW320/gcc/88MW320_xx_xxxx_flash.ld
@@ -0,0 +1,272 @@
+/*
+** ###################################################################
+** Processor: 88MW320_A0_NAPC
+** Compiler: GNU C Compiler
+** Reference manual: 88MW320-88MW322, Rev.3, July 2020
+** Version: rev. 1.0, 2020-09-07
+** Build: b210107
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2021 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x00000180 : 0;
+_nvram_start = 0x480C0000;
+
+/* The SRAM region [0x15EFC0-0x15EFFF] is reserved for entropy store. */
+/* The SRAM region [0x15F000-0x15FFFF] is reserved for keystore. */
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x1F000100, LENGTH = 0x00000180
+ m_text (RX) : ORIGIN = 0x1F000280, LENGTH = 0x0008FD80
+ m_data0 (RW) : ORIGIN = 0x00100000, LENGTH = 0x0005EFC0
+ m_data1 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_nvram (RW) : ORIGIN = 0x480C0044, LENGTH = 0x00000FBC
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(EXCLUDE_FILE(
+ /* Exclude flash and frequently executed functions from XIP */
+ */fsl_clock.c.obj
+ */clock_config.c.obj
+ */fsl_qspi.c.obj
+ */fsl_flashc.c.obj
+ */fsl_power.c.obj
+ */mflash_drv.c.obj
+ ) .text) /* .text sections (code) */
+ *(EXCLUDE_FILE(
+ /* Exclude flash and frequently executed functions from XIP */
+ */fsl_clock.c.obj
+ */clock_config.c.obj
+ */fsl_qspi.c.obj
+ */fsl_flashc.c.obj
+ */fsl_power.c.obj
+ */mflash_drv.c.obj
+ ) .text*) /* .text* sections (code) */
+ *(EXCLUDE_FILE(
+ /* Exclude flash and frequently executed functions from XIP */
+ */fsl_clock.c.obj
+ */clock_config.c.obj
+ */fsl_qspi.c.obj
+ */fsl_flashc.c.obj
+ */fsl_power.c.obj
+ */mflash_drv.c.obj
+ ) .rodata) /* .rodata sections (constants, strings, etc.) */
+ *(EXCLUDE_FILE(
+ /* Exclude flash and frequently executed functions from XIP */
+ */fsl_clock.c.obj
+ */clock_config.c.obj
+ */fsl_qspi.c.obj
+ */fsl_flashc.c.obj
+ */fsl_power.c.obj
+ */mflash_drv.c.obj
+ ) .rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .interrupts_ram :
+ {
+ . = ALIGN(4);
+ __VECTOR_RAM__ = .;
+ __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+ *(.m_interrupts_ram) /* This is a user defined section */
+ . += M_VECTOR_RAM_SIZE;
+ . = ALIGN(4);
+ __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+ } > m_data0
+
+ __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+ __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(CodeQuickAccess) /* CodeQuickAccess sections */
+ *(DataQuickAccess) /* DataQuickAccess sections */
+ /* Explicit placement of flash and frequently executed functions in RAM */
+ */fsl_clock.c.obj(.text .text* .rodata .rodata*)
+ */clock_config.c.obj(.text .text* .rodata .rodata*)
+ */fsl_qspi.c.obj(.text .text* .rodata .rodata*)
+ */fsl_flashc.c.obj(.text .text* .rodata .rodata*)
+ */fsl_power.c.obj(.text .text* .rodata .rodata*)
+ */mflash_drv.c.obj(.text .text* .rodata .rodata*)
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data0
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data0
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data1
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data1
+
+ .nvram :
+ {
+ . = ALIGN(4);
+ __nvram_start__ = .; /* create a global symbol at nvram start */
+ *(.nvram*) /* .nvram* sections */
+ *(.nvram_uninit*) /* .nvram_uninit* sections */
+ . = ALIGN(4);
+ __nvram_end__ = .; /* define a global symbol at nvram end */
+ } > m_nvram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data1) + LENGTH(m_data1);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data1 overflowed with stack and heap")
+}
+
diff --git a/devices/88MW320/gcc/88MW320_xx_xxxx_ram.ld b/devices/88MW320/gcc/88MW320_xx_xxxx_ram.ld
new file mode 100644
index 000000000..b5be5dcfa
--- /dev/null
+++ b/devices/88MW320/gcc/88MW320_xx_xxxx_ram.ld
@@ -0,0 +1,217 @@
+/*
+** ###################################################################
+** Processor: 88MW320_A0_NAPC
+** Compiler: GNU C Compiler
+** Reference manual: 88MW320-88MW322, Rev.3, July 2020
+** Version: rev. 1.0, 2020-09-07
+** Build: b201229
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
+_nvram_start = 0x480C0000;
+
+/* The SRAM region [0x15EFC0-0x15EFFF] is reserved for entropy store. */
+/* The SRAM region [0x15F000-0x15FFFF] is reserved for keystore. */
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x00100000, LENGTH = 0x00000180
+ m_text (RX) : ORIGIN = 0x00100180, LENGTH = 0x0005EE40
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000
+ m_nvram (RW) : ORIGIN = 0x480C0044, LENGTH = 0x00000FBC
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ __VECTOR_TABLE = .;
+ __Vectors = .;
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ __VECTOR_RAM = ORIGIN(m_interrupts);
+ __RAM_VECTOR_TABLE_SIZE_BYTES = 0x0;
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ .nvram :
+ {
+ . = ALIGN(4);
+ __nvram_start__ = .; /* create a global symbol at nvram start */
+ *(.nvram*) /* .nvram* sections */
+ *(.nvram_uninit*) /* .nvram_uninit* sections */
+ . = ALIGN(4);
+ __nvram_end__ = .; /* define a global symbol at nvram end */
+ } > m_nvram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/devices/88MW320/gcc/startup_88MW320.S b/devices/88MW320/gcc/startup_88MW320.S
new file mode 100644
index 000000000..a2beb880f
--- /dev/null
+++ b/devices/88MW320/gcc/startup_88MW320.S
@@ -0,0 +1,429 @@
+/* ------------------------------------------------------------------------- */
+/* @file: startup_88MW320.s */
+/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
+/* 88MW320 */
+/* @version: 1.0 */
+/* @date: 2020-9-7 */
+/* @build: b210108 */
+/* ------------------------------------------------------------------------- */
+/* */
+/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
+/* Copyright 2016-2021 NXP */
+/* All rights reserved. */
+/* */
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*****************************************************************************/
+/* Version: GCC for ARM Embedded Processors */
+/*****************************************************************************/
+ .syntax unified
+ .arch armv7-m
+
+ .section .isr_vector, "a"
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler*/
+ .long HardFault_Handler /* Hard Fault Handler*/
+ .long MemManage_Handler /* MPU Fault Handler*/
+ .long BusFault_Handler /* Bus Fault Handler*/
+ .long UsageFault_Handler /* Usage Fault Handler*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long 0 /* Reserved*/
+ .long SVC_Handler /* SVCall Handler*/
+ .long DebugMon_Handler /* Debug Monitor Handler*/
+ .long 0 /* Reserved*/
+ .long PendSV_Handler /* PendSV Handler*/
+ .long SysTick_Handler /* SysTick Handler*/
+
+ /* External Interrupts*/
+ .long EXTPIN0_IRQHandler /* Ext. Pin 0*/
+ .long EXTPIN1_IRQHandler /* Ext. Pin 1*/
+ .long RTC_IRQHandler /* RTC INT*/
+ .long CRC_IRQHandler /* CRC INT*/
+ .long AES_IRQHandler /* AES INT*/
+ .long I2C0_IRQHandler /* I2C0 INT*/
+ .long I2C1_IRQHandler /* I2C1 INT*/
+ .long Reserved23_IRQHandler /* Reserved interrupt*/
+ .long DMAC_IRQHandler /* DMAC INT*/
+ .long GPIO_IRQHandler /* GPIO INT*/
+ .long SSP0_IRQHandler /* SSP0 INT*/
+ .long SSP1_IRQHandler /* SSP1 INT*/
+ .long SSP2_IRQHandler /* SSP2 INT*/
+ .long QSPI_IRQHandler /* QSPI INT*/
+ .long GPT0_IRQHandler /* GPT0 INT*/
+ .long GPT1_IRQHandler /* GPT1 INT*/
+ .long GPT2_IRQHandler /* GPT2 INT*/
+ .long GPT3_IRQHandler /* GPT3 INT*/
+ .long UART0_IRQHandler /* UART0 INT*/
+ .long UART1_IRQHandler /* UART1 INT*/
+ .long UART2_IRQHandler /* UART2 INT*/
+ .long Reserved37_IRQHandler /* Reserved interrupt*/
+ .long WDT_IRQHandler /* WDT INT*/
+ .long Reserved39_IRQHandler /* Reserved interrupt*/
+ .long ADC0_IRQHandler /* ADC0 INT*/
+ .long DAC_IRQHandler /* DAC INT*/
+ .long ACOMP_WAKEUP_IRQHandler /* ACOMP Wake-up INT*/
+ .long ACOMP_IRQHandler /* ACOMP INT*/
+ .long SDIO_IRQHandler /* SDIO INT*/
+ .long USB_IRQHandler /* USB INT*/
+ .long Reserved46_IRQHandler /* Reserved interrupt*/
+ .long PLL_IRQHandler /* PLL INT*/
+ .long Reserved48_IRQHandler /* Reserved interrupt*/
+ .long RC32M_IRQHandler /* RC32M INT FUNC*/
+ .long GPIO_0_1_IRQHandler /* External Pin 0 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_2_3_IRQHandler /* External Pin 1 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_4_5_IRQHandler /* External Pin 2 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_6_7_IRQHandler /* External Pin 3 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_8_9_IRQHandler /* External Pin 4 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_10_11_IRQHandler /* External Pin 5 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_12_13_IRQHandler /* External Pin 6 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_14_15_IRQHandler /* External Pin 7 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_16_17_IRQHandler /* External Pin 8 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_18_19_IRQHandler /* External Pin 9 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_20_21_IRQHandler /* External Pin 10 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_22_23_IRQHandler /* External Pin 11 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_24_25_IRQHandler /* External Pin 12 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_26_27_IRQHandler /* External Pin 13 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_28_29_IRQHandler /* External Pin 14 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_30_31_IRQHandler /* External Pin 15 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_32_33_IRQHandler /* External Pin 16 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_34_35_IRQHandler /* External Pin 17 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_36_37_IRQHandler /* External Pin 18 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_38_39_IRQHandler /* External Pin 19 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_40_41_IRQHandler /* External Pin 20 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_42_43_IRQHandler /* External Pin 21 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_44_45_IRQHandler /* External Pin 22 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_46_47_IRQHandler /* External Pin 23 selected by PMU.EXT_SEL_REG*/
+ .long GPIO_48_49_IRQHandler /* External Pin 24 selected by PMU.EXT_SEL_REG*/
+ .long Reserved75_IRQHandler /* Reserved interrupt*/
+ .long PMU_IRQHandler /* ULP COMP*/
+ .long BRNOUT_IRQHandler /* Brnout INT*/
+ .long WIFIWKUP_IRQHandler /* WiFi Wakeup INT*/
+
+ .size __isr_vector, . - __isr_vector
+
+ .text
+ .thumb
+
+/* Reset Handler */
+
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ cpsid i /* Mask interrupts */
+ .equ VTOR, 0xE000ED08
+ ldr r0, =VTOR
+ ldr r1, =__isr_vector
+ str r1, [r0]
+ ldr r2, [r1]
+ msr msp, r2
+#ifndef __NO_SYSTEM_INIT
+ ldr r0,=SystemInit
+ blx r0
+#endif
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+#ifdef __PERFORMANCE_IMPLEMENTATION
+/* Here are two copies of loop implementations. First one favors performance
+ * and the second one favors code size. Default uses the second one.
+ * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
+ subs r3, r2
+ ble .LC1
+.LC0:
+ subs r3, #4
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ bgt .LC0
+.LC1:
+#else /* code size implemenation */
+.LC0:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0
+#endif
+
+#ifdef __STARTUP_CLEAR_BSS
+/* This part of work usually is done in C library startup code. Otherwise,
+ * define this macro to enable it in this startup.
+ *
+ * Loop to zero out BSS section, which uses following symbols
+ * in linker script:
+ * __bss_start__: start of BSS section. Must align to 4
+ * __bss_end__: end of BSS section. Must align to 4
+ */
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+
+ movs r0, 0
+.LC2:
+ cmp r1, r2
+ itt lt
+ strlt r0, [r1], #4
+ blt .LC2
+#endif /* __STARTUP_CLEAR_BSS */
+
+ cpsie i /* Unmask interrupts */
+#ifndef __START
+#define __START _start
+#endif
+#ifndef __ATOLLIC__
+ ldr r0,=__START
+ blx r0
+#else
+ ldr r0,=__libc_init_array
+ blx r0
+ ldr r0,=main
+ bx r0
+#endif
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .align 1
+ .thumb_func
+ .weak DefaultISR
+ .type DefaultISR, %function
+DefaultISR:
+ b DefaultISR
+ .size DefaultISR, . - DefaultISR
+
+ .align 1
+ .thumb_func
+ .weak NMI_Handler
+ .type NMI_Handler, %function
+NMI_Handler:
+ ldr r0,=NMI_Handler
+ bx r0
+ .size NMI_Handler, . - NMI_Handler
+
+ .align 1
+ .thumb_func
+ .weak HardFault_Handler
+ .type HardFault_Handler, %function
+HardFault_Handler:
+ ldr r0,=HardFault_Handler
+ bx r0
+ .size HardFault_Handler, . - HardFault_Handler
+
+ .align 1
+ .thumb_func
+ .weak SVC_Handler
+ .type SVC_Handler, %function
+SVC_Handler:
+ ldr r0,=SVC_Handler
+ bx r0
+ .size SVC_Handler, . - SVC_Handler
+
+ .align 1
+ .thumb_func
+ .weak PendSV_Handler
+ .type PendSV_Handler, %function
+PendSV_Handler:
+ ldr r0,=PendSV_Handler
+ bx r0
+ .size PendSV_Handler, . - PendSV_Handler
+
+ .align 1
+ .thumb_func
+ .weak SysTick_Handler
+ .type SysTick_Handler, %function
+SysTick_Handler:
+ ldr r0,=SysTick_Handler
+ bx r0
+ .size SysTick_Handler, . - SysTick_Handler
+
+ .align 1
+ .thumb_func
+ .weak I2C0_IRQHandler
+ .type I2C0_IRQHandler, %function
+I2C0_IRQHandler:
+ ldr r0,=I2C0_DriverIRQHandler
+ bx r0
+ .size I2C0_IRQHandler, . - I2C0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak I2C1_IRQHandler
+ .type I2C1_IRQHandler, %function
+I2C1_IRQHandler:
+ ldr r0,=I2C1_DriverIRQHandler
+ bx r0
+ .size I2C1_IRQHandler, . - I2C1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak DMAC_IRQHandler
+ .type DMAC_IRQHandler, %function
+DMAC_IRQHandler:
+ ldr r0,=DMAC_DriverIRQHandler
+ bx r0
+ .size DMAC_IRQHandler, . - DMAC_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SSP0_IRQHandler
+ .type SSP0_IRQHandler, %function
+SSP0_IRQHandler:
+ ldr r0,=SSP0_DriverIRQHandler
+ bx r0
+ .size SSP0_IRQHandler, . - SSP0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SSP1_IRQHandler
+ .type SSP1_IRQHandler, %function
+SSP1_IRQHandler:
+ ldr r0,=SSP1_DriverIRQHandler
+ bx r0
+ .size SSP1_IRQHandler, . - SSP1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SSP2_IRQHandler
+ .type SSP2_IRQHandler, %function
+SSP2_IRQHandler:
+ ldr r0,=SSP2_DriverIRQHandler
+ bx r0
+ .size SSP2_IRQHandler, . - SSP2_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak QSPI_IRQHandler
+ .type QSPI_IRQHandler, %function
+QSPI_IRQHandler:
+ ldr r0,=QSPI_DriverIRQHandler
+ bx r0
+ .size QSPI_IRQHandler, . - QSPI_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak UART0_IRQHandler
+ .type UART0_IRQHandler, %function
+UART0_IRQHandler:
+ ldr r0,=UART0_DriverIRQHandler
+ bx r0
+ .size UART0_IRQHandler, . - UART0_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak UART1_IRQHandler
+ .type UART1_IRQHandler, %function
+UART1_IRQHandler:
+ ldr r0,=UART1_DriverIRQHandler
+ bx r0
+ .size UART1_IRQHandler, . - UART1_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak UART2_IRQHandler
+ .type UART2_IRQHandler, %function
+UART2_IRQHandler:
+ ldr r0,=UART2_DriverIRQHandler
+ bx r0
+ .size UART2_IRQHandler, . - UART2_IRQHandler
+
+ .align 1
+ .thumb_func
+ .weak SDIO_IRQHandler
+ .type SDIO_IRQHandler, %function
+SDIO_IRQHandler:
+ ldr r0,=SDIO_DriverIRQHandler
+ bx r0
+ .size SDIO_IRQHandler, . - SDIO_IRQHandler
+
+
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_irq_handler handler_name
+ .weak \handler_name
+ .set \handler_name, DefaultISR
+ .endm
+
+/* Exception Handlers */
+ def_irq_handler MemManage_Handler
+ def_irq_handler BusFault_Handler
+ def_irq_handler UsageFault_Handler
+ def_irq_handler DebugMon_Handler
+ def_irq_handler EXTPIN0_IRQHandler
+ def_irq_handler EXTPIN1_IRQHandler
+ def_irq_handler RTC_IRQHandler
+ def_irq_handler CRC_IRQHandler
+ def_irq_handler AES_IRQHandler
+ def_irq_handler I2C0_DriverIRQHandler
+ def_irq_handler I2C1_DriverIRQHandler
+ def_irq_handler Reserved23_IRQHandler
+ def_irq_handler DMAC_DriverIRQHandler
+ def_irq_handler GPIO_IRQHandler
+ def_irq_handler SSP0_DriverIRQHandler
+ def_irq_handler SSP1_DriverIRQHandler
+ def_irq_handler SSP2_DriverIRQHandler
+ def_irq_handler QSPI_DriverIRQHandler
+ def_irq_handler GPT0_IRQHandler
+ def_irq_handler GPT1_IRQHandler
+ def_irq_handler GPT2_IRQHandler
+ def_irq_handler GPT3_IRQHandler
+ def_irq_handler UART0_DriverIRQHandler
+ def_irq_handler UART1_DriverIRQHandler
+ def_irq_handler UART2_DriverIRQHandler
+ def_irq_handler Reserved37_IRQHandler
+ def_irq_handler WDT_IRQHandler
+ def_irq_handler Reserved39_IRQHandler
+ def_irq_handler ADC0_IRQHandler
+ def_irq_handler DAC_IRQHandler
+ def_irq_handler ACOMP_WAKEUP_IRQHandler
+ def_irq_handler ACOMP_IRQHandler
+ def_irq_handler SDIO_DriverIRQHandler
+ def_irq_handler USB_IRQHandler
+ def_irq_handler Reserved46_IRQHandler
+ def_irq_handler PLL_IRQHandler
+ def_irq_handler Reserved48_IRQHandler
+ def_irq_handler RC32M_IRQHandler
+ def_irq_handler GPIO_0_1_IRQHandler
+ def_irq_handler GPIO_2_3_IRQHandler
+ def_irq_handler GPIO_4_5_IRQHandler
+ def_irq_handler GPIO_6_7_IRQHandler
+ def_irq_handler GPIO_8_9_IRQHandler
+ def_irq_handler GPIO_10_11_IRQHandler
+ def_irq_handler GPIO_12_13_IRQHandler
+ def_irq_handler GPIO_14_15_IRQHandler
+ def_irq_handler GPIO_16_17_IRQHandler
+ def_irq_handler GPIO_18_19_IRQHandler
+ def_irq_handler GPIO_20_21_IRQHandler
+ def_irq_handler GPIO_22_23_IRQHandler
+ def_irq_handler GPIO_24_25_IRQHandler
+ def_irq_handler GPIO_26_27_IRQHandler
+ def_irq_handler GPIO_28_29_IRQHandler
+ def_irq_handler GPIO_30_31_IRQHandler
+ def_irq_handler GPIO_32_33_IRQHandler
+ def_irq_handler GPIO_34_35_IRQHandler
+ def_irq_handler GPIO_36_37_IRQHandler
+ def_irq_handler GPIO_38_39_IRQHandler
+ def_irq_handler GPIO_40_41_IRQHandler
+ def_irq_handler GPIO_42_43_IRQHandler
+ def_irq_handler GPIO_44_45_IRQHandler
+ def_irq_handler GPIO_46_47_IRQHandler
+ def_irq_handler GPIO_48_49_IRQHandler
+ def_irq_handler Reserved75_IRQHandler
+ def_irq_handler PMU_IRQHandler
+ def_irq_handler BRNOUT_IRQHandler
+ def_irq_handler WIFIWKUP_IRQHandler
+
+ .end
diff --git a/devices/88MW320/mcuxpresso/startup_88mw320.c b/devices/88MW320/mcuxpresso/startup_88mw320.c
new file mode 100644
index 000000000..89406a0f4
--- /dev/null
+++ b/devices/88MW320/mcuxpresso/startup_88mw320.c
@@ -0,0 +1,720 @@
+//*****************************************************************************
+// 88MW320 startup code for use with MCUXpresso IDE
+//
+// Version : 231220
+//*****************************************************************************
+//
+// Copyright 2016-2020 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize ("Og")
+#endif // (DEBUG)
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+#include
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+#if defined (__USE_CMSIS)
+extern void SystemInit(void);
+#endif // (__USE_CMSIS)
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void);
+WEAK void Reserved17_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void CRC_IRQHandler(void);
+WEAK void AES_IRQHandler(void);
+WEAK void I2C0_IRQHandler(void);
+WEAK void I2C1_IRQHandler(void);
+WEAK void Reserved23_IRQHandler(void);
+WEAK void DMAC_IRQHandler(void);
+WEAK void GPIO_IRQHandler(void);
+WEAK void SSP0_IRQHandler(void);
+WEAK void SSP1_IRQHandler(void);
+WEAK void SSP2_IRQHandler(void);
+WEAK void QSPI_IRQHandler(void);
+WEAK void GPT0_IRQHandler(void);
+WEAK void GPT1_IRQHandler(void);
+WEAK void GPT2_IRQHandler(void);
+WEAK void GPT3_IRQHandler(void);
+WEAK void UART0_IRQHandler(void);
+WEAK void UART1_IRQHandler(void);
+WEAK void UART2_IRQHandler(void);
+WEAK void Reserved37_IRQHandler(void);
+WEAK void WDT_IRQHandler(void);
+WEAK void Reserved39_IRQHandler(void);
+WEAK void ADC0_IRQHandler(void);
+WEAK void DAC_IRQHandler(void);
+WEAK void ACOMP_WAKEUP_IRQHandler(void);
+WEAK void ACOMP_IRQHandler(void);
+WEAK void SDIO_IRQHandler(void);
+WEAK void USB_IRQHandler(void);
+WEAK void Reserved46_IRQHandler(void);
+WEAK void Reserved47_IRQHandler(void);
+WEAK void Reserved48_IRQHandler(void);
+WEAK void RC32M_IRQHandler(void);
+WEAK void Reserved50_IRQHandler(void);
+WEAK void Reserved51_IRQHandler(void);
+WEAK void Reserved52_IRQHandler(void);
+WEAK void Reserved53_IRQHandler(void);
+WEAK void Reserved54_IRQHandler(void);
+WEAK void Reserved55_IRQHandler(void);
+WEAK void Reserved56_IRQHandler(void);
+WEAK void Reserved57_IRQHandler(void);
+WEAK void Reserved58_IRQHandler(void);
+WEAK void Reserved59_IRQHandler(void);
+WEAK void Reserved60_IRQHandler(void);
+WEAK void Reserved61_IRQHandler(void);
+WEAK void Reserved62_IRQHandler(void);
+WEAK void Reserved63_IRQHandler(void);
+WEAK void Reserved64_IRQHandler(void);
+WEAK void Reserved65_IRQHandler(void);
+WEAK void Reserved66_IRQHandler(void);
+WEAK void Reserved67_IRQHandler(void);
+WEAK void Reserved68_IRQHandler(void);
+WEAK void Reserved69_IRQHandler(void);
+WEAK void Reserved70_IRQHandler(void);
+WEAK void Reserved71_IRQHandler(void);
+WEAK void Reserved72_IRQHandler(void);
+WEAK void Reserved73_IRQHandler(void);
+WEAK void Reserved74_IRQHandler(void);
+WEAK void Reserved75_IRQHandler(void);
+WEAK void PMU_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void Reserved16_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved17_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void AES_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved23_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMAC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void QSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved37_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WDT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DAC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ACOMP_WAKEUP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ACOMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved48_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RC32M_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved50_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved51_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved52_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved53_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved54_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved55_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved56_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved57_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved58_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved62_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved63_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved64_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved65_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved66_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved67_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved69_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved71_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved72_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved73_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved74_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved75_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PMU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+
+
+
+extern void (* const g_pfnVectors[])(void);
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
+
+__attribute__ ((used, section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM4
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+
+ // Chip Level - 88MW320
+ Reserved16_IRQHandler, // 16: Reserved interrupt
+ Reserved17_IRQHandler, // 17: Reserved interrupt
+ RTC_IRQHandler, // 18: RTC INT
+ CRC_IRQHandler, // 19: CRC INT
+ AES_IRQHandler, // 20: AES INT
+ I2C0_IRQHandler, // 21: I2C0 INT
+ I2C1_IRQHandler, // 22: I2C1 INT
+ Reserved23_IRQHandler, // 23: Reserved interrupt
+ DMAC_IRQHandler, // 24: DMAC INT
+ GPIO_IRQHandler, // 25: GPIO INT
+ SSP0_IRQHandler, // 26: SSP0 INT
+ SSP1_IRQHandler, // 27: SSP1 INT
+ SSP2_IRQHandler, // 28: SSP2 INT
+ QSPI_IRQHandler, // 29: QSPI INT
+ GPT0_IRQHandler, // 30: GPT0 INT
+ GPT1_IRQHandler, // 31: GPT1 INT
+ GPT2_IRQHandler, // 32: GPT2 INT
+ GPT3_IRQHandler, // 33: GPT3 INT
+ UART0_IRQHandler, // 34: UART0 INT
+ UART1_IRQHandler, // 35: UART1 INT
+ UART2_IRQHandler, // 36: UART2 INT
+ Reserved37_IRQHandler, // 37: Reserved interrupt
+ WDT_IRQHandler, // 38: WDT INT
+ Reserved39_IRQHandler, // 39: Reserved interrupt
+ ADC0_IRQHandler, // 40: ADC0 INT
+ DAC_IRQHandler, // 41: DAC INT
+ ACOMP_WAKEUP_IRQHandler, // 42: ACOMP Wake-up INT
+ ACOMP_IRQHandler, // 43: ACOMP INT
+ SDIO_IRQHandler, // 44: SDIO INT
+ USB_IRQHandler, // 45: USB INT
+ Reserved46_IRQHandler, // 46: Reserved interrupt
+ Reserved47_IRQHandler, // 47: Reserved interrupt
+ Reserved48_IRQHandler, // 48: Reserved interrupt
+ RC32M_IRQHandler, // 49: RC32M INT FUNC
+ Reserved50_IRQHandler, // 50: Reserved interrupt
+ Reserved51_IRQHandler, // 51: Reserved interrupt
+ Reserved52_IRQHandler, // 52: Reserved interrupt
+ Reserved53_IRQHandler, // 53: Reserved interrupt
+ Reserved54_IRQHandler, // 54: Reserved interrupt
+ Reserved55_IRQHandler, // 55: Reserved interrupt
+ Reserved56_IRQHandler, // 56: Reserved interrupt
+ Reserved57_IRQHandler, // 57: Reserved interrupt
+ Reserved58_IRQHandler, // 58: Reserved interrupt
+ Reserved59_IRQHandler, // 59: Reserved interrupt
+ Reserved60_IRQHandler, // 60: Reserved interrupt
+ Reserved61_IRQHandler, // 61: Reserved interrupt
+ Reserved62_IRQHandler, // 62: Reserved interrupt
+ Reserved63_IRQHandler, // 63: Reserved interrupt
+ Reserved64_IRQHandler, // 64: Reserved interrupt
+ Reserved65_IRQHandler, // 65: Reserved interrupt
+ Reserved66_IRQHandler, // 66: Reserved interrupt
+ Reserved67_IRQHandler, // 67: Reserved interrupt
+ Reserved68_IRQHandler, // 68: Reserved interrupt
+ Reserved69_IRQHandler, // 69: Reserved interrupt
+ Reserved70_IRQHandler, // 70: Reserved interrupt
+ Reserved71_IRQHandler, // 71: Reserved interrupt
+ Reserved72_IRQHandler, // 72: Reserved interrupt
+ Reserved73_IRQHandler, // 73: Reserved interrupt
+ Reserved74_IRQHandler, // 74: Reserved interrupt
+ Reserved75_IRQHandler, // 75: Reserved interrupt
+ PMU_IRQHandler, // 76: ULP COMP
+
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.init_data")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors.init_bss")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR(void) {
+
+ // Disable interrupts
+ __asm volatile ("cpsid i");
+
+
+#if defined (__USE_CMSIS)
+// If __USE_CMSIS defined, then call CMSIS SystemInit code
+ SystemInit();
+
+#endif // (__USE_CMSIS)
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will enable the FPU
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+ //
+ // Code to enable the Cortex-M4 FPU only included
+ // if appropriate build options have been selected.
+ // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+ //
+ // Read CPACR (located at address 0xE000ED88)
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ // Write back the modified value to the CPACR
+ asm volatile ("LDR.W R0, =0xE000ED88\n\t"
+ "LDR R1, [R0]\n\t"
+ "ORR R1, R1, #(0xF << 20)\n\t"
+ "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+#endif // (__USE_CMSIS)
+
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will setup the VTOR register
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+#endif // (__USE_CMSIS)
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+ // Reenable interrupts
+ __asm volatile ("cpsie i");
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main();
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void)
+{ Reserved16_DriverIRQHandler();
+}
+
+WEAK void Reserved17_IRQHandler(void)
+{ Reserved17_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{ RTC_DriverIRQHandler();
+}
+
+WEAK void CRC_IRQHandler(void)
+{ CRC_DriverIRQHandler();
+}
+
+WEAK void AES_IRQHandler(void)
+{ AES_DriverIRQHandler();
+}
+
+WEAK void I2C0_IRQHandler(void)
+{ I2C0_DriverIRQHandler();
+}
+
+WEAK void I2C1_IRQHandler(void)
+{ I2C1_DriverIRQHandler();
+}
+
+WEAK void Reserved23_IRQHandler(void)
+{ Reserved23_DriverIRQHandler();
+}
+
+WEAK void DMAC_IRQHandler(void)
+{ DMAC_DriverIRQHandler();
+}
+
+WEAK void GPIO_IRQHandler(void)
+{ GPIO_DriverIRQHandler();
+}
+
+WEAK void SSP0_IRQHandler(void)
+{ SSP0_DriverIRQHandler();
+}
+
+WEAK void SSP1_IRQHandler(void)
+{ SSP1_DriverIRQHandler();
+}
+
+WEAK void SSP2_IRQHandler(void)
+{ SSP2_DriverIRQHandler();
+}
+
+WEAK void QSPI_IRQHandler(void)
+{ QSPI_DriverIRQHandler();
+}
+
+WEAK void GPT0_IRQHandler(void)
+{ GPT0_DriverIRQHandler();
+}
+
+WEAK void GPT1_IRQHandler(void)
+{ GPT1_DriverIRQHandler();
+}
+
+WEAK void GPT2_IRQHandler(void)
+{ GPT2_DriverIRQHandler();
+}
+
+WEAK void GPT3_IRQHandler(void)
+{ GPT3_DriverIRQHandler();
+}
+
+WEAK void UART0_IRQHandler(void)
+{ UART0_DriverIRQHandler();
+}
+
+WEAK void UART1_IRQHandler(void)
+{ UART1_DriverIRQHandler();
+}
+
+WEAK void UART2_IRQHandler(void)
+{ UART2_DriverIRQHandler();
+}
+
+WEAK void Reserved37_IRQHandler(void)
+{ Reserved37_DriverIRQHandler();
+}
+
+WEAK void WDT_IRQHandler(void)
+{ WDT_DriverIRQHandler();
+}
+
+WEAK void Reserved39_IRQHandler(void)
+{ Reserved39_DriverIRQHandler();
+}
+
+WEAK void ADC0_IRQHandler(void)
+{ ADC0_DriverIRQHandler();
+}
+
+WEAK void DAC_IRQHandler(void)
+{ DAC_DriverIRQHandler();
+}
+
+WEAK void ACOMP_WAKEUP_IRQHandler(void)
+{ ACOMP_WAKEUP_DriverIRQHandler();
+}
+
+WEAK void ACOMP_IRQHandler(void)
+{ ACOMP_DriverIRQHandler();
+}
+
+WEAK void SDIO_IRQHandler(void)
+{ SDIO_DriverIRQHandler();
+}
+
+WEAK void USB_IRQHandler(void)
+{ USB_DriverIRQHandler();
+}
+
+WEAK void Reserved46_IRQHandler(void)
+{ Reserved46_DriverIRQHandler();
+}
+
+WEAK void Reserved47_IRQHandler(void)
+{ Reserved47_DriverIRQHandler();
+}
+
+WEAK void Reserved48_IRQHandler(void)
+{ Reserved48_DriverIRQHandler();
+}
+
+WEAK void RC32M_IRQHandler(void)
+{ RC32M_DriverIRQHandler();
+}
+
+WEAK void Reserved50_IRQHandler(void)
+{ Reserved50_DriverIRQHandler();
+}
+
+WEAK void Reserved51_IRQHandler(void)
+{ Reserved51_DriverIRQHandler();
+}
+
+WEAK void Reserved52_IRQHandler(void)
+{ Reserved52_DriverIRQHandler();
+}
+
+WEAK void Reserved53_IRQHandler(void)
+{ Reserved53_DriverIRQHandler();
+}
+
+WEAK void Reserved54_IRQHandler(void)
+{ Reserved54_DriverIRQHandler();
+}
+
+WEAK void Reserved55_IRQHandler(void)
+{ Reserved55_DriverIRQHandler();
+}
+
+WEAK void Reserved56_IRQHandler(void)
+{ Reserved56_DriverIRQHandler();
+}
+
+WEAK void Reserved57_IRQHandler(void)
+{ Reserved57_DriverIRQHandler();
+}
+
+WEAK void Reserved58_IRQHandler(void)
+{ Reserved58_DriverIRQHandler();
+}
+
+WEAK void Reserved59_IRQHandler(void)
+{ Reserved59_DriverIRQHandler();
+}
+
+WEAK void Reserved60_IRQHandler(void)
+{ Reserved60_DriverIRQHandler();
+}
+
+WEAK void Reserved61_IRQHandler(void)
+{ Reserved61_DriverIRQHandler();
+}
+
+WEAK void Reserved62_IRQHandler(void)
+{ Reserved62_DriverIRQHandler();
+}
+
+WEAK void Reserved63_IRQHandler(void)
+{ Reserved63_DriverIRQHandler();
+}
+
+WEAK void Reserved64_IRQHandler(void)
+{ Reserved64_DriverIRQHandler();
+}
+
+WEAK void Reserved65_IRQHandler(void)
+{ Reserved65_DriverIRQHandler();
+}
+
+WEAK void Reserved66_IRQHandler(void)
+{ Reserved66_DriverIRQHandler();
+}
+
+WEAK void Reserved67_IRQHandler(void)
+{ Reserved67_DriverIRQHandler();
+}
+
+WEAK void Reserved68_IRQHandler(void)
+{ Reserved68_DriverIRQHandler();
+}
+
+WEAK void Reserved69_IRQHandler(void)
+{ Reserved69_DriverIRQHandler();
+}
+
+WEAK void Reserved70_IRQHandler(void)
+{ Reserved70_DriverIRQHandler();
+}
+
+WEAK void Reserved71_IRQHandler(void)
+{ Reserved71_DriverIRQHandler();
+}
+
+WEAK void Reserved72_IRQHandler(void)
+{ Reserved72_DriverIRQHandler();
+}
+
+WEAK void Reserved73_IRQHandler(void)
+{ Reserved73_DriverIRQHandler();
+}
+
+WEAK void Reserved74_IRQHandler(void)
+{ Reserved74_DriverIRQHandler();
+}
+
+WEAK void Reserved75_IRQHandler(void)
+{ Reserved75_DriverIRQHandler();
+}
+
+WEAK void PMU_IRQHandler(void)
+{ PMU_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)
diff --git a/devices/88MW320/mcuxpresso/startup_88mw320.cpp b/devices/88MW320/mcuxpresso/startup_88mw320.cpp
new file mode 100644
index 000000000..89406a0f4
--- /dev/null
+++ b/devices/88MW320/mcuxpresso/startup_88mw320.cpp
@@ -0,0 +1,720 @@
+//*****************************************************************************
+// 88MW320 startup code for use with MCUXpresso IDE
+//
+// Version : 231220
+//*****************************************************************************
+//
+// Copyright 2016-2020 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize ("Og")
+#endif // (DEBUG)
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+ extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+#include
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+#if defined (__USE_CMSIS)
+extern void SystemInit(void);
+#endif // (__USE_CMSIS)
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+ void ResetISR(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void);
+WEAK void Reserved17_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void CRC_IRQHandler(void);
+WEAK void AES_IRQHandler(void);
+WEAK void I2C0_IRQHandler(void);
+WEAK void I2C1_IRQHandler(void);
+WEAK void Reserved23_IRQHandler(void);
+WEAK void DMAC_IRQHandler(void);
+WEAK void GPIO_IRQHandler(void);
+WEAK void SSP0_IRQHandler(void);
+WEAK void SSP1_IRQHandler(void);
+WEAK void SSP2_IRQHandler(void);
+WEAK void QSPI_IRQHandler(void);
+WEAK void GPT0_IRQHandler(void);
+WEAK void GPT1_IRQHandler(void);
+WEAK void GPT2_IRQHandler(void);
+WEAK void GPT3_IRQHandler(void);
+WEAK void UART0_IRQHandler(void);
+WEAK void UART1_IRQHandler(void);
+WEAK void UART2_IRQHandler(void);
+WEAK void Reserved37_IRQHandler(void);
+WEAK void WDT_IRQHandler(void);
+WEAK void Reserved39_IRQHandler(void);
+WEAK void ADC0_IRQHandler(void);
+WEAK void DAC_IRQHandler(void);
+WEAK void ACOMP_WAKEUP_IRQHandler(void);
+WEAK void ACOMP_IRQHandler(void);
+WEAK void SDIO_IRQHandler(void);
+WEAK void USB_IRQHandler(void);
+WEAK void Reserved46_IRQHandler(void);
+WEAK void Reserved47_IRQHandler(void);
+WEAK void Reserved48_IRQHandler(void);
+WEAK void RC32M_IRQHandler(void);
+WEAK void Reserved50_IRQHandler(void);
+WEAK void Reserved51_IRQHandler(void);
+WEAK void Reserved52_IRQHandler(void);
+WEAK void Reserved53_IRQHandler(void);
+WEAK void Reserved54_IRQHandler(void);
+WEAK void Reserved55_IRQHandler(void);
+WEAK void Reserved56_IRQHandler(void);
+WEAK void Reserved57_IRQHandler(void);
+WEAK void Reserved58_IRQHandler(void);
+WEAK void Reserved59_IRQHandler(void);
+WEAK void Reserved60_IRQHandler(void);
+WEAK void Reserved61_IRQHandler(void);
+WEAK void Reserved62_IRQHandler(void);
+WEAK void Reserved63_IRQHandler(void);
+WEAK void Reserved64_IRQHandler(void);
+WEAK void Reserved65_IRQHandler(void);
+WEAK void Reserved66_IRQHandler(void);
+WEAK void Reserved67_IRQHandler(void);
+WEAK void Reserved68_IRQHandler(void);
+WEAK void Reserved69_IRQHandler(void);
+WEAK void Reserved70_IRQHandler(void);
+WEAK void Reserved71_IRQHandler(void);
+WEAK void Reserved72_IRQHandler(void);
+WEAK void Reserved73_IRQHandler(void);
+WEAK void Reserved74_IRQHandler(void);
+WEAK void Reserved75_IRQHandler(void);
+WEAK void PMU_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void Reserved16_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved17_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CRC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void AES_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void I2C1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved23_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMAC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SSP2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void QSPI_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GPT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UART0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UART1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UART2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved37_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void WDT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved39_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DAC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ACOMP_WAKEUP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ACOMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved46_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved48_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RC32M_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved50_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved51_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved52_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved53_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved54_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved55_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved56_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved57_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved58_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved62_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved63_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved64_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved65_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved66_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved67_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved69_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved70_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved71_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved72_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved73_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved74_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved75_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PMU_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+
+
+
+extern void (* const g_pfnVectors[])(void);
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
+
+__attribute__ ((used, section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+ // Core Level - CM4
+ &_vStackTop, // The initial stack pointer
+ ResetISR, // The reset handler
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+ 0, // Reserved
+
+ // Chip Level - 88MW320
+ Reserved16_IRQHandler, // 16: Reserved interrupt
+ Reserved17_IRQHandler, // 17: Reserved interrupt
+ RTC_IRQHandler, // 18: RTC INT
+ CRC_IRQHandler, // 19: CRC INT
+ AES_IRQHandler, // 20: AES INT
+ I2C0_IRQHandler, // 21: I2C0 INT
+ I2C1_IRQHandler, // 22: I2C1 INT
+ Reserved23_IRQHandler, // 23: Reserved interrupt
+ DMAC_IRQHandler, // 24: DMAC INT
+ GPIO_IRQHandler, // 25: GPIO INT
+ SSP0_IRQHandler, // 26: SSP0 INT
+ SSP1_IRQHandler, // 27: SSP1 INT
+ SSP2_IRQHandler, // 28: SSP2 INT
+ QSPI_IRQHandler, // 29: QSPI INT
+ GPT0_IRQHandler, // 30: GPT0 INT
+ GPT1_IRQHandler, // 31: GPT1 INT
+ GPT2_IRQHandler, // 32: GPT2 INT
+ GPT3_IRQHandler, // 33: GPT3 INT
+ UART0_IRQHandler, // 34: UART0 INT
+ UART1_IRQHandler, // 35: UART1 INT
+ UART2_IRQHandler, // 36: UART2 INT
+ Reserved37_IRQHandler, // 37: Reserved interrupt
+ WDT_IRQHandler, // 38: WDT INT
+ Reserved39_IRQHandler, // 39: Reserved interrupt
+ ADC0_IRQHandler, // 40: ADC0 INT
+ DAC_IRQHandler, // 41: DAC INT
+ ACOMP_WAKEUP_IRQHandler, // 42: ACOMP Wake-up INT
+ ACOMP_IRQHandler, // 43: ACOMP INT
+ SDIO_IRQHandler, // 44: SDIO INT
+ USB_IRQHandler, // 45: USB INT
+ Reserved46_IRQHandler, // 46: Reserved interrupt
+ Reserved47_IRQHandler, // 47: Reserved interrupt
+ Reserved48_IRQHandler, // 48: Reserved interrupt
+ RC32M_IRQHandler, // 49: RC32M INT FUNC
+ Reserved50_IRQHandler, // 50: Reserved interrupt
+ Reserved51_IRQHandler, // 51: Reserved interrupt
+ Reserved52_IRQHandler, // 52: Reserved interrupt
+ Reserved53_IRQHandler, // 53: Reserved interrupt
+ Reserved54_IRQHandler, // 54: Reserved interrupt
+ Reserved55_IRQHandler, // 55: Reserved interrupt
+ Reserved56_IRQHandler, // 56: Reserved interrupt
+ Reserved57_IRQHandler, // 57: Reserved interrupt
+ Reserved58_IRQHandler, // 58: Reserved interrupt
+ Reserved59_IRQHandler, // 59: Reserved interrupt
+ Reserved60_IRQHandler, // 60: Reserved interrupt
+ Reserved61_IRQHandler, // 61: Reserved interrupt
+ Reserved62_IRQHandler, // 62: Reserved interrupt
+ Reserved63_IRQHandler, // 63: Reserved interrupt
+ Reserved64_IRQHandler, // 64: Reserved interrupt
+ Reserved65_IRQHandler, // 65: Reserved interrupt
+ Reserved66_IRQHandler, // 66: Reserved interrupt
+ Reserved67_IRQHandler, // 67: Reserved interrupt
+ Reserved68_IRQHandler, // 68: Reserved interrupt
+ Reserved69_IRQHandler, // 69: Reserved interrupt
+ Reserved70_IRQHandler, // 70: Reserved interrupt
+ Reserved71_IRQHandler, // 71: Reserved interrupt
+ Reserved72_IRQHandler, // 72: Reserved interrupt
+ Reserved73_IRQHandler, // 73: Reserved interrupt
+ Reserved74_IRQHandler, // 74: Reserved interrupt
+ Reserved75_IRQHandler, // 75: Reserved interrupt
+ PMU_IRQHandler, // 76: ULP COMP
+
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.init_data")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int *pulSrc = (unsigned int*) romstart;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors.init_bss")))
+void bss_init(unsigned int start, unsigned int len) {
+ unsigned int *pulDest = (unsigned int*) start;
+ unsigned int loop;
+ for (loop = 0; loop < len; loop = loop + 4)
+ *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR(void) {
+
+ // Disable interrupts
+ __asm volatile ("cpsid i");
+
+
+#if defined (__USE_CMSIS)
+// If __USE_CMSIS defined, then call CMSIS SystemInit code
+ SystemInit();
+
+#endif // (__USE_CMSIS)
+
+ //
+ // Copy the data sections from flash to SRAM.
+ //
+ unsigned int LoadAddr, ExeAddr, SectionLen;
+ unsigned int *SectionTableAddr;
+
+ // Load base address of Global Section Table
+ SectionTableAddr = &__data_section_table;
+
+ // Copy the data sections from flash to SRAM.
+ while (SectionTableAddr < &__data_section_table_end) {
+ LoadAddr = *SectionTableAddr++;
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ data_init(LoadAddr, ExeAddr, SectionLen);
+ }
+
+ // At this point, SectionTableAddr = &__bss_section_table;
+ // Zero fill the bss segment
+ while (SectionTableAddr < &__bss_section_table_end) {
+ ExeAddr = *SectionTableAddr++;
+ SectionLen = *SectionTableAddr++;
+ bss_init(ExeAddr, SectionLen);
+ }
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will enable the FPU
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+ //
+ // Code to enable the Cortex-M4 FPU only included
+ // if appropriate build options have been selected.
+ // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+ //
+ // Read CPACR (located at address 0xE000ED88)
+ // Set bits 20-23 to enable CP10 and CP11 coprocessors
+ // Write back the modified value to the CPACR
+ asm volatile ("LDR.W R0, =0xE000ED88\n\t"
+ "LDR R1, [R0]\n\t"
+ "ORR R1, R1, #(0xF << 20)\n\t"
+ "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+#endif // (__USE_CMSIS)
+
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will setup the VTOR register
+
+ // Check to see if we are running the code from a non-zero
+ // address (eg RAM, external flash), in which case we need
+ // to modify the VTOR register to tell the CPU that the
+ // vector table is located at a non-0x0 address.
+ unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+ if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+ *pSCB_VTOR = (unsigned int)g_pfnVectors;
+ }
+#endif // (__USE_CMSIS)
+#if defined (__cplusplus)
+ //
+ // Call C++ library initialisation
+ //
+ __libc_init_array();
+#endif
+
+ // Reenable interrupts
+ __asm volatile ("cpsie i");
+
+#if defined (__REDLIB__)
+ // Call the Redlib library, which in turn calls main()
+ __main();
+#else
+ main();
+#endif
+
+ //
+ // main() shouldn't return, but if it does, we'll just enter an infinite loop
+ //
+ while (1) {
+ ;
+ }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void Reserved16_IRQHandler(void)
+{ Reserved16_DriverIRQHandler();
+}
+
+WEAK void Reserved17_IRQHandler(void)
+{ Reserved17_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{ RTC_DriverIRQHandler();
+}
+
+WEAK void CRC_IRQHandler(void)
+{ CRC_DriverIRQHandler();
+}
+
+WEAK void AES_IRQHandler(void)
+{ AES_DriverIRQHandler();
+}
+
+WEAK void I2C0_IRQHandler(void)
+{ I2C0_DriverIRQHandler();
+}
+
+WEAK void I2C1_IRQHandler(void)
+{ I2C1_DriverIRQHandler();
+}
+
+WEAK void Reserved23_IRQHandler(void)
+{ Reserved23_DriverIRQHandler();
+}
+
+WEAK void DMAC_IRQHandler(void)
+{ DMAC_DriverIRQHandler();
+}
+
+WEAK void GPIO_IRQHandler(void)
+{ GPIO_DriverIRQHandler();
+}
+
+WEAK void SSP0_IRQHandler(void)
+{ SSP0_DriverIRQHandler();
+}
+
+WEAK void SSP1_IRQHandler(void)
+{ SSP1_DriverIRQHandler();
+}
+
+WEAK void SSP2_IRQHandler(void)
+{ SSP2_DriverIRQHandler();
+}
+
+WEAK void QSPI_IRQHandler(void)
+{ QSPI_DriverIRQHandler();
+}
+
+WEAK void GPT0_IRQHandler(void)
+{ GPT0_DriverIRQHandler();
+}
+
+WEAK void GPT1_IRQHandler(void)
+{ GPT1_DriverIRQHandler();
+}
+
+WEAK void GPT2_IRQHandler(void)
+{ GPT2_DriverIRQHandler();
+}
+
+WEAK void GPT3_IRQHandler(void)
+{ GPT3_DriverIRQHandler();
+}
+
+WEAK void UART0_IRQHandler(void)
+{ UART0_DriverIRQHandler();
+}
+
+WEAK void UART1_IRQHandler(void)
+{ UART1_DriverIRQHandler();
+}
+
+WEAK void UART2_IRQHandler(void)
+{ UART2_DriverIRQHandler();
+}
+
+WEAK void Reserved37_IRQHandler(void)
+{ Reserved37_DriverIRQHandler();
+}
+
+WEAK void WDT_IRQHandler(void)
+{ WDT_DriverIRQHandler();
+}
+
+WEAK void Reserved39_IRQHandler(void)
+{ Reserved39_DriverIRQHandler();
+}
+
+WEAK void ADC0_IRQHandler(void)
+{ ADC0_DriverIRQHandler();
+}
+
+WEAK void DAC_IRQHandler(void)
+{ DAC_DriverIRQHandler();
+}
+
+WEAK void ACOMP_WAKEUP_IRQHandler(void)
+{ ACOMP_WAKEUP_DriverIRQHandler();
+}
+
+WEAK void ACOMP_IRQHandler(void)
+{ ACOMP_DriverIRQHandler();
+}
+
+WEAK void SDIO_IRQHandler(void)
+{ SDIO_DriverIRQHandler();
+}
+
+WEAK void USB_IRQHandler(void)
+{ USB_DriverIRQHandler();
+}
+
+WEAK void Reserved46_IRQHandler(void)
+{ Reserved46_DriverIRQHandler();
+}
+
+WEAK void Reserved47_IRQHandler(void)
+{ Reserved47_DriverIRQHandler();
+}
+
+WEAK void Reserved48_IRQHandler(void)
+{ Reserved48_DriverIRQHandler();
+}
+
+WEAK void RC32M_IRQHandler(void)
+{ RC32M_DriverIRQHandler();
+}
+
+WEAK void Reserved50_IRQHandler(void)
+{ Reserved50_DriverIRQHandler();
+}
+
+WEAK void Reserved51_IRQHandler(void)
+{ Reserved51_DriverIRQHandler();
+}
+
+WEAK void Reserved52_IRQHandler(void)
+{ Reserved52_DriverIRQHandler();
+}
+
+WEAK void Reserved53_IRQHandler(void)
+{ Reserved53_DriverIRQHandler();
+}
+
+WEAK void Reserved54_IRQHandler(void)
+{ Reserved54_DriverIRQHandler();
+}
+
+WEAK void Reserved55_IRQHandler(void)
+{ Reserved55_DriverIRQHandler();
+}
+
+WEAK void Reserved56_IRQHandler(void)
+{ Reserved56_DriverIRQHandler();
+}
+
+WEAK void Reserved57_IRQHandler(void)
+{ Reserved57_DriverIRQHandler();
+}
+
+WEAK void Reserved58_IRQHandler(void)
+{ Reserved58_DriverIRQHandler();
+}
+
+WEAK void Reserved59_IRQHandler(void)
+{ Reserved59_DriverIRQHandler();
+}
+
+WEAK void Reserved60_IRQHandler(void)
+{ Reserved60_DriverIRQHandler();
+}
+
+WEAK void Reserved61_IRQHandler(void)
+{ Reserved61_DriverIRQHandler();
+}
+
+WEAK void Reserved62_IRQHandler(void)
+{ Reserved62_DriverIRQHandler();
+}
+
+WEAK void Reserved63_IRQHandler(void)
+{ Reserved63_DriverIRQHandler();
+}
+
+WEAK void Reserved64_IRQHandler(void)
+{ Reserved64_DriverIRQHandler();
+}
+
+WEAK void Reserved65_IRQHandler(void)
+{ Reserved65_DriverIRQHandler();
+}
+
+WEAK void Reserved66_IRQHandler(void)
+{ Reserved66_DriverIRQHandler();
+}
+
+WEAK void Reserved67_IRQHandler(void)
+{ Reserved67_DriverIRQHandler();
+}
+
+WEAK void Reserved68_IRQHandler(void)
+{ Reserved68_DriverIRQHandler();
+}
+
+WEAK void Reserved69_IRQHandler(void)
+{ Reserved69_DriverIRQHandler();
+}
+
+WEAK void Reserved70_IRQHandler(void)
+{ Reserved70_DriverIRQHandler();
+}
+
+WEAK void Reserved71_IRQHandler(void)
+{ Reserved71_DriverIRQHandler();
+}
+
+WEAK void Reserved72_IRQHandler(void)
+{ Reserved72_DriverIRQHandler();
+}
+
+WEAK void Reserved73_IRQHandler(void)
+{ Reserved73_DriverIRQHandler();
+}
+
+WEAK void Reserved74_IRQHandler(void)
+{ Reserved74_DriverIRQHandler();
+}
+
+WEAK void Reserved75_IRQHandler(void)
+{ Reserved75_DriverIRQHandler();
+}
+
+WEAK void PMU_IRQHandler(void)
+{ PMU_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)
diff --git a/devices/88MW320/project_template/board.c b/devices/88MW320/project_template/board.c
new file mode 100644
index 000000000..30bda70e0
--- /dev/null
+++ b/devices/88MW320/project_template/board.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright 201, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file board.c
+ * @brief Board initialization file.
+ */
+
+/* This is an empty template for board specific configuration.*/
+
+#include
+#include "board.h"
+
+/**
+ * @brief Set up and initialize all required blocks and functions related to the board hardware.
+ */
+void BOARD_InitDebugConsole(void)
+{
+ /* The user initialization should be placed here */
+}
diff --git a/devices/88MW320/project_template/board.h b/devices/88MW320/project_template/board.h
new file mode 100644
index 000000000..b3b5ef0f5
--- /dev/null
+++ b/devices/88MW320/project_template/board.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file board.h
+ * @brief Board initialization header file.
+ */
+
+/* This is an empty template for board specific configuration.*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/**
+ * @brief The board name
+ */
+#define BOARD_NAME "board"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Initialize board specific settings.
+ */
+void BOARD_InitDebugConsole(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
diff --git a/devices/88MW320/project_template/clock_config.c b/devices/88MW320/project_template/clock_config.c
new file mode 100644
index 000000000..8e5b03871
--- /dev/null
+++ b/devices/88MW320/project_template/clock_config.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v4.0
+* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/**
+ * @file clock_config.c
+ * @brief Board clocks initialization file.
+ */
+
+/* This is a empty template for board specific configuration.*/
+
+#include "fsl_common.h"
+#include "clock_config.h"
+
+/**
+ * @brief Set up and initialize all required blocks and functions related to the board hardware.
+ */
+void BOARD_InitBootClocks(void)
+{
+ /* The user initialization should be placed here */
+
+ /* Read core clock setting. */
+ SystemCoreClockUpdate();
+}
diff --git a/devices/88MW320/project_template/clock_config.h b/devices/88MW320/project_template/clock_config.h
new file mode 100644
index 000000000..b706c0dd1
--- /dev/null
+++ b/devices/88MW320/project_template/clock_config.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file clock_config.h
+ * @brief Board clocks header file.
+ */
+
+/* This is an empty template for board specific configuration.*/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Initialize board clocks.
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _CLOCK_CONFIG_H_ */
diff --git a/devices/88MW320/project_template/peripherals.c b/devices/88MW320/project_template/peripherals.c
new file mode 100644
index 000000000..118cdef04
--- /dev/null
+++ b/devices/88MW320/project_template/peripherals.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v1.0
+* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/**
+ * @file peripherals.c
+ * @brief Peripherals initialization file.
+ */
+
+/* This is an empty template for board specific configuration.*/
+
+#include "peripherals.h"
+
+/**
+ * @brief Set up and initialize all required blocks and functions related to the peripherals hardware.
+ */
+void BOARD_InitBootPeripherals(void)
+{
+ /* The user initialization should be placed here */
+}
diff --git a/devices/88MW320/project_template/peripherals.h b/devices/88MW320/project_template/peripherals.h
new file mode 100644
index 000000000..9180d4d63
--- /dev/null
+++ b/devices/88MW320/project_template/peripherals.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file peripherals.h
+ * @brief Peripherals initialization header file.
+ */
+
+/* This is an empty template for board specific configuration.*/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Initialize peripherals specific settings.
+ */
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/devices/88MW320/project_template/pin_mux.c b/devices/88MW320/project_template/pin_mux.c
new file mode 100644
index 000000000..010927e2f
--- /dev/null
+++ b/devices/88MW320/project_template/pin_mux.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v4.0
+* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********/
+
+/**
+ * @file pin_mux.c
+ * @brief Board pins file.
+ */
+
+/* This is an empty template for board specific configuration.*/
+
+#include "pin_mux.h"
+
+/**
+ * @brief Set up and initialize all required blocks and functions related to the board hardware.
+ */
+void BOARD_InitBootPins(void) {
+ /* The user initialization should be placed here */
+}
diff --git a/devices/88MW320/project_template/pin_mux.h b/devices/88MW320/project_template/pin_mux.h
new file mode 100644
index 000000000..13f807dbb
--- /dev/null
+++ b/devices/88MW320/project_template/pin_mux.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/**
+ * @file pin_mux.h
+ * @brief Board pins header file.
+ */
+
+/* This is an empty template for board specific configuration.*/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Initialize board pins.
+ */
+void BOARD_InitBootPins(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _PIN_MUX_H_ */
+
+
diff --git a/devices/88MW320/system_88MW320.c b/devices/88MW320/system_88MW320.c
new file mode 100644
index 000000000..3bab4b114
--- /dev/null
+++ b/devices/88MW320/system_88MW320.c
@@ -0,0 +1,88 @@
+/*
+** ###################################################################
+** Processor: 88MW320_A0_NAPC
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: 88MW320-88MW322, Rev.3, July 2020
+** Version: rev. 1.0, 2020-09-07
+** Build: b201223
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2020-09-07)
+** Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file 88MW320
+ * @version 1.0
+ * @date 231220
+ * @brief Device specific configuration file for 88MW320 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include
+#include "fsl_device_registers.h"
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInit (void)
+{
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+ /* Power off WLAN for clean boot up. */
+ if ((PMU->WLAN_CTRL & PMU_WLAN_CTRL_PD_MASK) != 0U)
+ {
+ PMU->WLAN_CTRL &= ~PMU_WLAN_CTRL_PD_MASK;
+ }
+
+ SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void)
+{
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemInitHook()
+ ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void)
+{
+ /* Void implementation of the weak function. */
+}
diff --git a/devices/88MW320/system_88MW320.h b/devices/88MW320/system_88MW320.h
new file mode 100644
index 000000000..118683e82
--- /dev/null
+++ b/devices/88MW320/system_88MW320.h
@@ -0,0 +1,106 @@
+/*
+** ###################################################################
+** Processor: 88MW320_A0_NAPC
+** Compilers: GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: 88MW320-88MW322, Rev.3, July 2020
+** Version: rev. 1.0, 2020-09-07
+** Build: b201223
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2020 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2020-09-07)
+** Initial version.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file 88MW320
+ * @version 1.0
+ * @date 231220
+ * @brief Device specific configuration file for 88MW320 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+#ifndef _SYSTEM_88MW320_H_
+#define _SYSTEM_88MW320_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include
+
+#define DEFAULT_SYSTEM_CLOCK 200000000u /* Default System clock value */
+#ifndef CLK_MAINXTAL_CLK
+#define CLK_MAINXTAL_CLK 38400000u /* External crystal 38.4M clock */
+#endif
+#define CLK_RC32M_CLK 32000000u /* On-chip RC OSC 32 MHz clock */
+#define CLK_XTAL32K_CLK 32768u /* External crystal 32 kHz clock */
+#define CLK_RC32K_CLK 32768u /* On-chip RC OSC 32 KHz clock */
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit(void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_88MW320_DSP_H_ */
diff --git a/devices/88MW320/utilities/fsl_notifier.c b/devices/88MW320/utilities/fsl_notifier.c
new file mode 100644
index 000000000..7b7c02dc3
--- /dev/null
+++ b/devices/88MW320/utilities/fsl_notifier.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_notifier.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Creates a Notifier handle.
+ *
+ * param notifierHandle A pointer to the notifier handle.
+ * param configs A pointer to an array with references to all configurations which is handled by the Notifier.
+ * param configsNumber Number of configurations. Size of the configuration array.
+ * param callbacks A pointer to an array of callback configurations.
+ * If there are no callbacks to register during Notifier initialization, use NULL value.
+ * param callbacksNumber Number of registered callbacks. Size of the callbacks array.
+ * param userFunction User function.
+ * param userData User data passed to user function.
+ * return An error Code or kStatus_Success.
+ */
+status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle,
+ notifier_user_config_t **configs,
+ uint8_t configsNumber,
+ notifier_callback_config_t *callbacks,
+ uint8_t callbacksNumber,
+ notifier_user_function_t userFunction,
+ void *userData)
+{
+ /* Check input parameter - at least one configuration is required and userFunction must exist */
+ if ((configs == NULL) || (configsNumber == 0U) || (userFunction == NULL))
+ {
+ return kStatus_Fail;
+ }
+ /* Initialize handle structure */
+ (void)memset(notifierHandle, 0, sizeof(notifier_handle_t));
+ /* Store references to user-defined configurations */
+ notifierHandle->configsTable = configs;
+ notifierHandle->configsNumber = configsNumber;
+ /* Store references to user-defined callback configurations */
+ if (callbacks != NULL)
+ {
+ notifierHandle->callbacksTable = callbacks;
+ notifierHandle->callbacksNumber = callbacksNumber;
+ /* If all callbacks return success, then the errorCallbackIndex is callbacksNumber */
+ notifierHandle->errorCallbackIndex = callbacksNumber;
+ }
+ notifierHandle->userFunction = userFunction;
+ notifierHandle->userData = userData;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Switches the configuration according to a pre-defined structure.
+ *
+ * This function sets the system to the target configuration. Before transition,
+ * the Notifier sends notifications to all callbacks registered to the callback table.
+ * Callbacks are invoked in the following order: All registered callbacks are notified
+ * ordered by index in the callbacks array. The same order is used for before and after switch notifications.
+ * The notifications before the configuration switch can be used to obtain confirmation about
+ * the change from registered callbacks. If any registered callback denies the
+ * configuration change, further execution of this function depends on the notifier policy: the
+ * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement).
+ * When configuration change is forced, the result of the before switch notifications are ignored. If an
+ * agreement is required, if any callback returns an error code, further notifications
+ * before switch notifications are cancelled and all already notified callbacks are re-invoked.
+ * The index of the callback which returned error code during pre-switch notifications is stored
+ * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it.
+ * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase
+ * the error occurred is returned when NOTIFIER_SwitchConfig() exits.
+ * param notifierHandle pointer to notifier handle
+ * param configIndex Index of the target configuration.
+ * param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible.
+ *
+ * return An error code or kStatus_Success.
+ *
+ */
+status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy)
+{
+ uint8_t currentStaticCallback = 0U; /* Index to array of statically registered call-backs */
+ status_t returnCode = kStatus_Success; /* Function return */
+
+ notifier_notification_block_t notifyBlock; /* Callback notification block */
+ notifier_callback_config_t *callbackConfig; /* Pointer to callback configuration */
+
+ /* Set errorcallbackindex as callbacksNumber, which means no callback error now */
+ notifierHandle->errorCallbackIndex = notifierHandle->callbacksNumber;
+
+ /* Requested configuration availability check */
+ if (configIndex >= notifierHandle->configsNumber)
+ {
+ return kStatus_OutOfRange;
+ }
+
+ /* Initialization of local variables from the Notifier handle structure */
+
+ notifyBlock.policy = policy;
+ notifyBlock.targetConfig = notifierHandle->configsTable[configIndex];
+ notifyBlock.notifyType = kNOTIFIER_NotifyBefore;
+
+ /* From all statically registered call-backs... */
+ for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; currentStaticCallback++)
+ {
+ callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]);
+ /* ...notify only those which asked to be called before the configuration switch */
+ if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackBefore) != 0U)
+ {
+ /* In case that call-back returned error code mark it, store the call-back handle and eventually cancel
+ * the configuration switch */
+ if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success)
+ {
+ returnCode = (status_t)kStatus_NOTIFIER_ErrorNotificationBefore;
+ notifierHandle->errorCallbackIndex = currentStaticCallback;
+ /* If not forcing configuration switch, call all already notified call-backs to revert their state
+ * as the switch is canceled */
+ if (policy != kNOTIFIER_PolicyForcible)
+ {
+ break;
+ }
+ }
+ }
+ }
+
+ /* Set configuration */
+
+ /* In case that any call-back returned error code and policy doesn't force the configuration set, go to after
+ * switch call-backs */
+ if ((policy == kNOTIFIER_PolicyForcible) || (returnCode == kStatus_Success))
+ {
+ returnCode = notifierHandle->userFunction(notifierHandle->configsTable[configIndex], notifierHandle->userData);
+ if (returnCode != kStatus_Success)
+ {
+ return returnCode;
+ }
+ /* Update current configuration index */
+ notifierHandle->currentConfigIndex = configIndex;
+ notifyBlock.notifyType = kNOTIFIER_NotifyAfter;
+ /* From all statically registered call-backs... */
+ for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber;
+ currentStaticCallback++)
+ {
+ callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]);
+ /* ...notify only those which asked to be called after the configuration switch */
+ if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackAfter) != 0U)
+ {
+ /* In case that call-back returned error code mark it and store the call-back handle */
+ if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success)
+ {
+ returnCode = (status_t)kStatus_NOTIFIER_ErrorNotificationAfter;
+ notifierHandle->errorCallbackIndex = currentStaticCallback;
+ if (policy != kNOTIFIER_PolicyForcible)
+ {
+ break;
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ /* End of unsuccessful switch */
+ notifyBlock.notifyType = kNOTIFIER_NotifyRecover;
+ while (currentStaticCallback-- > 0U)
+ {
+ callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]);
+ if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackBefore) != 0U)
+ {
+ (void)callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData);
+ }
+ }
+ }
+
+ return returnCode;
+}
+
+/*!
+ * brief This function returns the last failed notification callback.
+ *
+ * This function returns an index of the last callback that failed during the configuration switch while
+ * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully
+ * value equal to callbacks number is returned. The returned value represents an index in the array of
+ * static call-backs.
+ *
+ * param notifierHandle Pointer to the notifier handle
+ * return Callback Index of the last failed callback or value equal to callbacks count.
+ */
+uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle)
+{
+ return notifierHandle->errorCallbackIndex;
+}
diff --git a/devices/88MW320/utilities/fsl_notifier.h b/devices/88MW320/utilities/fsl_notifier.h
new file mode 100644
index 000000000..d93578c13
--- /dev/null
+++ b/devices/88MW320/utilities/fsl_notifier.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_NOTIFIER_H_
+#define _FSL_NOTIFIER_H_
+
+#include "fsl_common.h"
+/*!
+ * @addtogroup notifier
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Notifier error codes.
+ *
+ * Used as return value of Notifier functions.
+ */
+enum _notifier_status
+{
+ kStatus_NOTIFIER_ErrorNotificationBefore =
+ MAKE_STATUS(kStatusGroup_NOTIFIER, 0), /*!< An error occurs during send "BEFORE" notification. */
+ kStatus_NOTIFIER_ErrorNotificationAfter =
+ MAKE_STATUS(kStatusGroup_NOTIFIER, 1), /*!< An error occurs during send "AFTER" notification. */
+};
+
+/*!
+ * @brief Notifier policies.
+ *
+ * Defines whether the user function execution is forced or not.
+ * For kNOTIFIER_PolicyForcible, the user function is executed regardless of the callback results,
+ * while kNOTIFIER_PolicyAgreement policy is used to exit NOTIFIER_SwitchConfig()
+ * when any of the callbacks returns error code.
+ * See also NOTIFIER_SwitchConfig() description.
+ */
+typedef enum _notifier_policy
+{
+ kNOTIFIER_PolicyAgreement, /*!< NOTIFIER_SwitchConfig() method is exited when any of the callbacks returns error
+ code. */
+ kNOTIFIER_PolicyForcible, /*!< The user function is executed regardless of the results. */
+} notifier_policy_t;
+
+/*! @brief Notification type. Used to notify registered callbacks */
+typedef enum _notifier_notification_type
+{
+ kNOTIFIER_NotifyRecover = 0x00U, /*!< Notify IP to recover to previous work state. */
+ kNOTIFIER_NotifyBefore = 0x01U, /*!< Notify IP that configuration setting is going to change. */
+ kNOTIFIER_NotifyAfter = 0x02U, /*!< Notify IP that configuration setting has been changed. */
+} notifier_notification_type_t;
+
+/*!
+ * @brief The callback type, which indicates kinds of notification the callback handles.
+ *
+ * Used in the callback configuration structure (notifier_callback_config_t)
+ * to specify when the registered callback is called during configuration switch initiated by the
+ * NOTIFIER_SwitchConfig().
+ * Callback can be invoked in following situations.
+ * - Before the configuration switch (Callback return value can affect NOTIFIER_SwitchConfig()
+ * execution. See the NOTIFIER_SwitchConfig() and notifier_policy_t documentation).
+ * - After an unsuccessful attempt to switch configuration
+ * - After a successful configuration switch
+ */
+typedef enum _notifier_callback_type
+{
+ kNOTIFIER_CallbackBefore = 0x01U, /*!< Callback handles BEFORE notification. */
+ kNOTIFIER_CallbackAfter = 0x02U, /*!< Callback handles AFTER notification. */
+ kNOTIFIER_CallbackBeforeAfter = 0x03U, /*!< Callback handles BEFORE and AFTER notification. */
+} notifier_callback_type_t;
+
+/*! @brief Notifier user configuration type.
+ *
+ * Reference of the user defined configuration is stored in an array; the notifier switches between these configurations
+ * based on this array.
+ */
+typedef void notifier_user_config_t;
+
+/*! @brief Notifier user function prototype
+ * Use this function to execute specific operations in configuration switch.
+ * Before and after this function execution, different notification is sent to registered callbacks.
+ * If this function returns any error code, NOTIFIER_SwitchConfig() exits.
+ *
+ * @param targetConfig target Configuration.
+ * @param userData Refers to other specific data passed to user function.
+ * @return An error code or kStatus_Success.
+ */
+typedef status_t (*notifier_user_function_t)(notifier_user_config_t *targetConfig, void *userData);
+
+/*! @brief notification block passed to the registered callback function. */
+typedef struct _notifier_notification_block
+{
+ notifier_user_config_t *targetConfig; /*!< Pointer to target configuration. */
+ notifier_policy_t policy; /*!< Configure transition policy. */
+ notifier_notification_type_t notifyType; /*!< Configure notification type. */
+} notifier_notification_block_t;
+
+/*!
+ * @brief Callback prototype.
+ *
+ * Declaration of a callback. It is common for registered callbacks.
+ * Reference to function of this type is part of the notifier_callback_config_t callback configuration structure.
+ * Depending on callback type, function of this prototype is called (see NOTIFIER_SwitchConfig())
+ * before configuration switch, after it or in both use cases to notify about
+ * the switch progress (see notifier_callback_type_t). When called, the type of the notification
+ * is passed as a parameter along with the reference to the target configuration structure (see
+ * notifier_notification_block_t) and any data passed during the callback registration. When notified before the
+ * configuration switch, depending on the configuration switch policy (see notifier_policy_t), the callback may deny the
+ * execution of the user function by returning an error code different than kStatus_Success (see
+ * NOTIFIER_SwitchConfig()).
+ *
+ * @param notify Notification block.
+ * @param data Callback data. Refers to the data passed during callback registration. Intended to
+ * pass any driver or application data such as internal state information.
+ * @return An error code or kStatus_Success.
+ */
+typedef status_t (*notifier_callback_t)(notifier_notification_block_t *notify, void *data);
+
+/*!
+ * @brief Callback configuration structure.
+ *
+ * This structure holds the configuration of callbacks.
+ * Callbacks of this type are expected to be statically allocated.
+ * This structure contains the following application-defined data.
+ * callback - pointer to the callback function
+ * callbackType - specifies when the callback is called
+ * callbackData - pointer to the data passed to the callback.
+ */
+typedef struct _notifier_callback_config
+{
+ notifier_callback_t callback; /*!< Pointer to the callback function. */
+ notifier_callback_type_t callbackType; /*!< Callback type. */
+ void *callbackData; /*!< Pointer to the data passed to the callback. */
+} notifier_callback_config_t;
+
+/*!
+ * @brief Notifier handle structure.
+ *
+ * Notifier handle structure. Contains data necessary for the Notifier proper function.
+ * Stores references to registered configurations, callbacks, information about their numbers,
+ * user function, user data, and other internal data.
+ * NOTIFIER_CreateHandle() must be called to initialize this handle.
+ */
+typedef struct _notifier_handle
+{
+ notifier_user_config_t **configsTable; /*!< Pointer to configure table. */
+ uint8_t configsNumber; /*!< Number of configurations. */
+ notifier_callback_config_t *callbacksTable; /*!< Pointer to callback table. */
+ uint8_t callbacksNumber; /*!< Maximum number of callback configurations. */
+ uint8_t errorCallbackIndex; /*!< Index of callback returns error. */
+ uint8_t currentConfigIndex; /*!< Index of current configuration. */
+ notifier_user_function_t userFunction; /*!< User function. */
+ void *userData; /*!< User data passed to user function. */
+} notifier_handle_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Creates a Notifier handle.
+ *
+ * @param notifierHandle A pointer to the notifier handle.
+ * @param configs A pointer to an array with references to all configurations which is handled by the Notifier.
+ * @param configsNumber Number of configurations. Size of the configuration array.
+ * @param callbacks A pointer to an array of callback configurations.
+ * If there are no callbacks to register during Notifier initialization, use NULL value.
+ * @param callbacksNumber Number of registered callbacks. Size of the callbacks array.
+ * @param userFunction User function.
+ * @param userData User data passed to user function.
+ * @return An error Code or kStatus_Success.
+ */
+status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle,
+ notifier_user_config_t **configs,
+ uint8_t configsNumber,
+ notifier_callback_config_t *callbacks,
+ uint8_t callbacksNumber,
+ notifier_user_function_t userFunction,
+ void *userData);
+
+/*!
+ * @brief Switches the configuration according to a pre-defined structure.
+ *
+ * This function sets the system to the target configuration. Before transition,
+ * the Notifier sends notifications to all callbacks registered to the callback table.
+ * Callbacks are invoked in the following order: All registered callbacks are notified
+ * ordered by index in the callbacks array. The same order is used for before and after switch notifications.
+ * The notifications before the configuration switch can be used to obtain confirmation about
+ * the change from registered callbacks. If any registered callback denies the
+ * configuration change, further execution of this function depends on the notifier policy: the
+ * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement).
+ * When configuration change is forced, the result of the before switch notifications are ignored. If an
+ * agreement is required, if any callback returns an error code, further notifications
+ * before switch notifications are cancelled and all already notified callbacks are re-invoked.
+ * The index of the callback which returned error code during pre-switch notifications is stored
+ * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it.
+ * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase
+ * the error occurred is returned when NOTIFIER_SwitchConfig() exits.
+ * @param notifierHandle pointer to notifier handle
+ * @param configIndex Index of the target configuration.
+ * @param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible.
+ *
+ * @return An error code or kStatus_Success.
+ *
+ */
+status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy);
+
+/*!
+ * @brief This function returns the last failed notification callback.
+ *
+ * This function returns an index of the last callback that failed during the configuration switch while
+ * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully
+ * value equal to callbacks number is returned. The returned value represents an index in the array of
+ * static call-backs.
+ *
+ * @param notifierHandle Pointer to the notifier handle
+ * @return Callback Index of the last failed callback or value equal to callbacks count.
+ */
+uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_NOTIFIER_H_ */
diff --git a/devices/88MW320/utilities/fsl_shell.c b/devices/88MW320/utilities/fsl_shell.c
new file mode 100644
index 000000000..167bdc0b3
--- /dev/null
+++ b/devices/88MW320/utilities/fsl_shell.c
@@ -0,0 +1,1081 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * POSIX getopt for Windows
+ * Code given out at the 1985 UNIFORUM conference in Dallas.
+ *
+ * From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985
+ * Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET
+ * Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP
+ * Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix
+ * From: std-unix@ut-sally.UUCP (Moderator, John Quarterman)
+ * Newsgroups: mod.std.unix
+ * Subject: public domain AT&T getopt source
+ * Message-ID: <3352@ut-sally.UUCP>
+ * Date: 3 Nov 85 19:34:15 GMT
+ * Date-Received: 4 Nov 85 12:25:09 GMT
+ * Organization: IEEE/P1003 Portable Operating System Environment Committee
+ * Lines: 91
+ * Approved: jsq@ut-sally.UUC
+ * Here's something you've all been waiting for: the AT&T public domain
+ * source for getopt(3). It is the code which was given out at the 1985
+ * UNIFORUM conference in Dallas. I obtained it by electronic mail
+ * directly from AT&T. The people there assure me that it is indeed
+ * in the public domain
+ * There is no manual page. That is because the one they gave out at
+ * UNIFORUM was slightly different from the current System V Release 2
+ * manual page. The difference apparently involved a note about the
+ * famous rules 5 and 6, recommending using white space between an option
+ * and its first argument, and not grouping options that have arguments.
+ * Getopt itself is currently lenient about both of these things White
+ * space is allowed, but not mandatory, and the last option in a group can
+ * have an argument. That particular version of the man page evidently
+ * has no official existence, and my source at AT&T did not send a copy.
+ * The current SVR2 man page reflects the actual behavor of this getopt.
+ * However, I am not about to post a copy of anything licensed by AT&T.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "fsl_common.h"
+#include "fsl_str.h"
+
+#include "fsl_component_generic_list.h"
+#include "fsl_component_serial_manager.h"
+
+#include "fsl_shell.h"
+
+/*
+ * The OSA_USED macro can only be defined when the OSA component is used.
+ * If the source code of the OSA component does not exist, the OSA_USED cannot be defined.
+ * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED
+ * also cannot be defined.
+ * The source code path of the OSA component is /components/osa.
+ *
+ */
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+#include "fsl_component_common_task.h"
+#else
+#include "fsl_os_abstraction.h"
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define KEY_ESC (0x1BU)
+#define KET_DEL (0x7FU)
+
+#define SHELL_EVENT_DATA_ARRIVED (1U << 0)
+#define SHELL_EVENT_DATA_SENT (1U << 1)
+
+#define SHELL_SPRINTF_BUFFER_SIZE (64U)
+
+/*! @brief A type for the handle special key. */
+typedef enum _fun_key_status
+{
+ kSHELL_Normal = 0U, /*!< Normal key */
+ kSHELL_Special = 1U, /*!< Special key */
+ kSHELL_Function = 2U, /*!< Function key */
+} fun_key_status_t;
+
+/*! @brief Data structure for Shell environment. */
+typedef struct _shell_context_handle
+{
+ list_label_t commandContextListHead; /*!< Command shellContextHandle list queue head */
+ serial_handle_t serialHandle; /*!< Serial manager handle */
+ uint8_t
+ serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; /*!< The buffer for serial manager write handle */
+ serial_write_handle_t serialWriteHandle; /*!< The serial manager write handle */
+ uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; /*!< The buffer for serial manager read handle */
+ serial_read_handle_t serialReadHandle; /*!< The serial manager read handle */
+ char *prompt; /*!< Prompt string */
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+ common_task_message_t commontaskMsg; /*!< Message for common task */
+#else
+ uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */
+ uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */
+#endif
+
+#endif
+
+#endif
+ char line[SHELL_BUFFER_SIZE]; /*!< Consult buffer */
+ char hist_buf[SHELL_HISTORY_COUNT][SHELL_BUFFER_SIZE]; /*!< History buffer*/
+ char printBuffer[SHELL_SPRINTF_BUFFER_SIZE]; /*!< Buffer for print */
+ uint32_t printLength; /*!< All length has been printed */
+ uint16_t hist_current; /*!< Current history command in hist buff*/
+ uint16_t hist_count; /*!< Total history command in hist buff*/
+ enum _fun_key_status stat; /*!< Special key status */
+ uint8_t cmd_num; /*!< Number of user commands */
+ uint8_t l_pos; /*!< Total line position */
+ uint8_t c_pos; /*!< Current line position */
+ volatile uint8_t notificationPost; /*!< The serial manager notification is post */
+ uint8_t exit; /*!< Exit Flag*/
+ uint8_t printBusy; /*!< Print is busy */
+} shell_context_handle_t;
+
+#if 0
+#define SHELL_STRUCT_OFFSET(type, field) ((size_t) & (((type *)0)->field))
+#define SHEEL_COMMAND_POINTER(node) \
+ ((shell_command_t *)(((uint32_t)(node)) - SHELL_STRUCT_OFFSET(shell_command_t, link)))
+#else
+#define SHEEL_COMMAND_POINTER(node) \
+ ((shell_command_t *)(((uint32_t)(node)) - (sizeof(shell_command_t) - sizeof(list_element_t))))
+#endif
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static shell_status_t SHELL_HelpCommand(shell_handle_t shellHandle, int32_t argc, char **argv); /*!< help command */
+
+static shell_status_t SHELL_ExitCommand(shell_handle_t shellHandle, int32_t argc, char **argv); /*!< exit command */
+
+static int32_t SHELL_ParseLine(const char *cmd, uint32_t len, char *argv[]); /*!< parse line command */
+
+static int32_t SHELL_StringCompare(const char *str1, const char *str2, int32_t count); /*!< compare string command */
+
+static void SHELL_ProcessCommand(shell_context_handle_t *shellContextHandle, const char *cmd); /*!< process a command */
+
+static void SHELL_GetHistoryCommand(shell_context_handle_t *shellContextHandle,
+ uint8_t hist_pos); /*!< get commands history */
+
+static void SHELL_AutoComplete(shell_context_handle_t *shellContextHandle); /*!< auto complete command */
+
+static shell_status_t SHELL_GetChar(shell_context_handle_t *shellContextHandle,
+ uint8_t *ch); /*!< get a char from communication interface */
+
+static void SHELL_WriteWithCopy(shell_handle_t shellHandle, const char *buffer, uint32_t length);
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+static void SHELL_Task(void *param); /*!< Shell task*/
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+static SHELL_COMMAND_DEFINE(help, "\r\n\"help\": List all the registered commands\r\n", SHELL_HelpCommand, 0);
+static SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0);
+
+static char s_paramBuffer[SHELL_BUFFER_SIZE];
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+#if defined(OSA_USED)
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+#else
+/*
+ * \brief Defines the serial manager task's stack
+ */
+static OSA_TASK_DEFINE(SHELL_Task, SHELL_TASK_PRIORITY, 1, SHELL_TASK_STACK_SIZE, false);
+#endif
+#endif /* OSA_USED */
+#endif /* SHELL_NON_BLOCKING_MODE */
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+static void SHELL_SerialManagerRxCallback(void *callbackParam,
+ serial_manager_callback_message_t *message,
+ serial_manager_status_t status)
+{
+ shell_context_handle_t *shellHandle;
+
+ assert(callbackParam);
+ assert(message);
+
+ shellHandle = (shell_context_handle_t *)callbackParam;
+
+ if (0U == shellHandle->notificationPost)
+ {
+ shellHandle->notificationPost = 1U;
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+ shellHandle->commontaskMsg.callback = SHELL_Task;
+ shellHandle->commontaskMsg.callbackParam = shellHandle;
+ (void)COMMON_TASK_post_message(&shellHandle->commontaskMsg);
+#else
+ (void)OSA_EventSet((osa_event_handle_t)shellHandle->event, SHELL_EVENT_DATA_ARRIVED);
+#endif
+
+#else
+ SHELL_Task(shellHandle);
+#endif
+ }
+}
+#endif
+
+static void SHELL_WriteBuffer(char *buffer, int32_t *indicator, char val, int len)
+{
+ shell_context_handle_t *shellContextHandle;
+ int i = 0;
+ shellContextHandle = (shell_context_handle_t *)(void *)buffer;
+
+ for (i = 0; i < len; i++)
+ {
+ if ((*indicator + 1) >= (int32_t)SHELL_SPRINTF_BUFFER_SIZE)
+ {
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+ if (NULL == shellContextHandle->serialHandle)
+ {
+ for (uint32_t index = 0; index < ((uint32_t)*indicator); index++)
+ {
+ (void)putchar(shellContextHandle->printBuffer[index]);
+ }
+ }
+ else
+#endif
+ {
+ (void)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle,
+ (uint8_t *)shellContextHandle->printBuffer, (uint32_t)*indicator);
+ }
+
+ shellContextHandle->printLength += (uint32_t)*indicator;
+ *indicator = 0;
+ }
+
+ shellContextHandle->printBuffer[*indicator] = val;
+ (*indicator)++;
+ }
+}
+
+static int SHELL_Sprintf(void *buffer, const char *formatString, va_list ap)
+{
+ shell_context_handle_t *shellContextHandle;
+ uint32_t length;
+ shellContextHandle = (shell_context_handle_t *)buffer;
+
+ length = (uint32_t)StrFormatPrintf(formatString, ap, (char *)buffer, SHELL_WriteBuffer);
+ shellContextHandle->printLength += length;
+ return (int32_t)length;
+}
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+static void SHELL_Task(void *param)
+#else
+void SHELL_Task(shell_handle_t shellHandle)
+#endif
+{
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+ shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)param;
+#else
+ shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle;
+#endif
+ uint8_t ch;
+
+ if (NULL != shellContextHandle)
+ {
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+#else
+ osa_event_flags_t ev = 0;
+
+ do
+ {
+ if (KOSA_StatusSuccess == OSA_EventWait((osa_event_handle_t)shellContextHandle->event, osaEventFlagsAll_c,
+ 0U, osaWaitForever_c, &ev))
+ {
+ if (0U != (ev & SHELL_EVENT_DATA_ARRIVED))
+#endif
+
+#endif
+
+#endif
+ {
+ shellContextHandle->notificationPost = 0;
+ do
+ {
+ if ((bool)shellContextHandle->exit)
+ {
+ if (shellContextHandle->serialReadHandle != NULL)
+ {
+ (void)SerialManager_CloseReadHandle(shellContextHandle->serialReadHandle);
+ shellContextHandle->serialReadHandle = NULL;
+ }
+ if (shellContextHandle->serialWriteHandle != NULL)
+ {
+ (void)SerialManager_CloseWriteHandle(shellContextHandle->serialWriteHandle);
+ shellContextHandle->serialWriteHandle = NULL;
+ }
+ break;
+ }
+ if (kStatus_SHELL_Success != (shell_status_t)SHELL_GetChar(shellContextHandle, &ch))
+ {
+ /* If error occurred when getting a char, exit the task and waiting the new data arriving. */
+ break;
+ }
+
+ /* Special key */
+ if (ch == KEY_ESC)
+ {
+ shellContextHandle->stat = kSHELL_Special;
+ continue;
+ }
+ else if (shellContextHandle->stat == kSHELL_Special)
+ {
+ /* Function key */
+ if ((char)ch == '[')
+ {
+ shellContextHandle->stat = kSHELL_Function;
+ continue;
+ }
+ shellContextHandle->stat = kSHELL_Normal;
+ }
+ else if (shellContextHandle->stat == kSHELL_Function)
+ {
+ shellContextHandle->stat = kSHELL_Normal;
+
+ switch ((char)ch)
+ {
+ /* History operation here */
+ case 'A': /* Up key */
+ SHELL_GetHistoryCommand(shellContextHandle, (uint8_t)shellContextHandle->hist_current);
+ if (shellContextHandle->hist_current < (shellContextHandle->hist_count - 1U))
+ {
+ shellContextHandle->hist_current++;
+ }
+ break;
+ case 'B': /* Down key */
+ SHELL_GetHistoryCommand(shellContextHandle, (uint8_t)shellContextHandle->hist_current);
+ if (shellContextHandle->hist_current > 0U)
+ {
+ shellContextHandle->hist_current--;
+ }
+ break;
+ case 'D': /* Left key */
+ if ((bool)shellContextHandle->c_pos)
+ {
+ SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+ shellContextHandle->c_pos--;
+ }
+ break;
+ case 'C': /* Right key */
+ if (shellContextHandle->c_pos < shellContextHandle->l_pos)
+ {
+ (void)SHELL_Write(shellContextHandle,
+ &shellContextHandle->line[shellContextHandle->c_pos], 1);
+ shellContextHandle->c_pos++;
+ }
+ break;
+ default:
+ /* MISRA C-2012 Rule 16.4 */
+ break;
+ }
+ continue;
+ }
+ /* Handle tab key */
+ else if ((char)ch == '\t')
+ {
+#if SHELL_AUTO_COMPLETE
+ /* Move the cursor to the beginning of line */
+ uint32_t i;
+ for (i = 0; i < (uint32_t)shellContextHandle->c_pos; i++)
+ {
+ SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+ }
+ /* Do auto complete */
+ SHELL_AutoComplete(shellContextHandle);
+ /* Move position to end */
+ shellContextHandle->l_pos = (uint8_t)strlen(shellContextHandle->line);
+ shellContextHandle->c_pos = shellContextHandle->l_pos;
+#endif
+ continue;
+ }
+ /* Handle backspace key */
+ else if ((ch == KET_DEL) || ((char)ch == '\b'))
+ {
+ /* There must be at last one char */
+ if (shellContextHandle->c_pos == 0U)
+ {
+ continue;
+ }
+
+ shellContextHandle->l_pos--;
+ shellContextHandle->c_pos--;
+
+ if (shellContextHandle->l_pos > shellContextHandle->c_pos)
+ {
+ (void)memmove(&shellContextHandle->line[shellContextHandle->c_pos],
+ &shellContextHandle->line[shellContextHandle->c_pos + 1U],
+ (uint32_t)shellContextHandle->l_pos - (uint32_t)shellContextHandle->c_pos);
+ shellContextHandle->line[shellContextHandle->l_pos] = '\0';
+ SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+ (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->c_pos],
+ strlen(&shellContextHandle->line[shellContextHandle->c_pos]));
+ SHELL_WriteWithCopy(shellContextHandle, " \b", 3);
+
+ /* Reset position */
+ uint32_t i;
+ for (i = (uint32_t)shellContextHandle->c_pos; i <= (uint32_t)shellContextHandle->l_pos; i++)
+ {
+ SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+ }
+ }
+ else /* Normal backspace operation */
+ {
+ SHELL_WriteWithCopy(shellContextHandle, "\b \b", 3);
+ shellContextHandle->line[shellContextHandle->l_pos] = '\0';
+ }
+ continue;
+ }
+ else
+ {
+ /* MISRA C-2012 Rule 15.7 */
+ }
+
+ /* Input too long */
+ if (shellContextHandle->l_pos >= (SHELL_BUFFER_SIZE - 1U))
+ {
+ shellContextHandle->l_pos = 0U;
+ }
+
+ /* Handle end of line, break */
+ if (((char)ch == '\r') || ((char)ch == '\n'))
+ {
+ static char endoflinechar = '\0';
+
+ if (((uint8_t)endoflinechar != 0U) && ((uint8_t)endoflinechar != ch))
+ {
+ continue;
+ }
+ else
+ {
+ endoflinechar = (char)ch;
+ /* If command line is not NULL, will start process it. */
+ if (0U != strlen(shellContextHandle->line))
+ {
+ SHELL_ProcessCommand(shellContextHandle, shellContextHandle->line);
+ }
+ /* Reset all params */
+ shellContextHandle->c_pos = shellContextHandle->l_pos = 0;
+ shellContextHandle->hist_current = 0;
+ SHELL_PrintPrompt(shellContextHandle);
+ (void)memset(shellContextHandle->line, 0, sizeof(shellContextHandle->line));
+ continue;
+ }
+ }
+
+ /* Normal character */
+ if (shellContextHandle->c_pos < shellContextHandle->l_pos)
+ {
+ (void)memmove(&shellContextHandle->line[shellContextHandle->c_pos + 1U],
+ &shellContextHandle->line[shellContextHandle->c_pos],
+ (uint32_t)shellContextHandle->l_pos - (uint32_t)shellContextHandle->c_pos);
+ shellContextHandle->line[shellContextHandle->c_pos] = (char)ch;
+ (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->c_pos],
+ strlen(&shellContextHandle->line[shellContextHandle->c_pos]));
+ /* Move the cursor to new position */
+ uint32_t i;
+ for (i = (uint32_t)shellContextHandle->c_pos; i < (uint32_t)shellContextHandle->l_pos; i++)
+ {
+ SHELL_WriteWithCopy(shellContextHandle, "\b", 1);
+ }
+ }
+ else
+ {
+ shellContextHandle->line[shellContextHandle->l_pos] = (char)ch;
+ (void)SHELL_Write(shellContextHandle, &shellContextHandle->line[shellContextHandle->l_pos], 1);
+ }
+
+ ch = 0;
+ shellContextHandle->l_pos++;
+ shellContextHandle->c_pos++;
+ } while (0U == shellContextHandle->exit);
+ }
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+#else
+ }
+ } while (1U == gUseRtos_c); /* USE_RTOS = 0 for BareMetal and 1 for OS */
+#endif
+
+#endif
+
+#endif
+ }
+}
+
+static shell_status_t SHELL_HelpCommand(shell_handle_t shellHandle, int32_t argc, char **argv)
+{
+ shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle;
+ shell_command_t *shellCommandContextHandle;
+ list_element_handle_t p = LIST_GetHead(&shellContextHandle->commandContextListHead);
+
+ while (p != NULL)
+ {
+ shellCommandContextHandle = SHEEL_COMMAND_POINTER(p);
+ if ((shellCommandContextHandle->pcHelpString != NULL) && (bool)strlen(shellCommandContextHandle->pcHelpString))
+ {
+ (void)SHELL_Write(shellContextHandle, shellCommandContextHandle->pcHelpString,
+ strlen(shellCommandContextHandle->pcHelpString));
+ }
+
+ p = LIST_GetNext(p);
+ }
+ return kStatus_SHELL_Success;
+}
+
+static shell_status_t SHELL_ExitCommand(shell_handle_t shellHandle, int32_t argc, char **argv)
+{
+ shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle;
+ /* Skip warning */
+ SHELL_WriteWithCopy(shellContextHandle, "\r\nSHELL exited\r\n", strlen("\r\nSHELL exited\r\n"));
+ shellContextHandle->exit = (uint8_t) true;
+ return kStatus_SHELL_Success;
+}
+
+static void SHELL_ProcessCommand(shell_context_handle_t *shellContextHandle, const char *cmd)
+{
+ shell_command_t *tmpCommand = NULL;
+ const char *tmpCommandString;
+ int32_t argc;
+ char *argv[SHELL_BUFFER_SIZE] = {0};
+ list_element_handle_t p;
+ uint8_t flag = 1;
+ uint8_t tmpCommandLen;
+ uint8_t tmpLen;
+ uint8_t i = 0;
+
+ tmpLen = (uint8_t)strlen(cmd);
+ argc = SHELL_ParseLine(cmd, tmpLen, argv);
+
+ if ((argc > 0))
+ {
+ p = LIST_GetHead(&shellContextHandle->commandContextListHead);
+ while (p != NULL)
+ {
+ tmpCommand = SHEEL_COMMAND_POINTER(p);
+ tmpCommandString = tmpCommand->pcCommand;
+ tmpCommandLen = (uint8_t)strlen(tmpCommandString);
+ /* Compare with space or end of string */
+ if ((cmd[tmpCommandLen] == ' ') || (cmd[tmpCommandLen] == (char)0x00))
+ {
+ if (SHELL_StringCompare(tmpCommandString, argv[0], (int32_t)tmpCommandLen) == 0)
+ {
+ /* support commands with optional number of parameters */
+ if (tmpCommand->cExpectedNumberOfParameters == (uint8_t)SHELL_IGNORE_PARAMETER_COUNT)
+ {
+ flag = 0;
+ }
+ else if ((tmpCommand->cExpectedNumberOfParameters == 0U) && (argc == 1))
+ {
+ flag = 0;
+ }
+ else if (tmpCommand->cExpectedNumberOfParameters > 0U)
+ {
+ if ((argc - 1) == (int32_t)tmpCommand->cExpectedNumberOfParameters)
+ {
+ flag = 0;
+ }
+ }
+ else
+ {
+ flag = 1;
+ }
+ break;
+ }
+ }
+ p = LIST_GetNext(p);
+ }
+ if (NULL == p)
+ {
+ tmpCommand = NULL;
+ }
+ }
+
+ if ((tmpCommand != NULL) && (flag == 1U))
+ {
+ SHELL_WriteWithCopy(
+ shellContextHandle,
+ "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n",
+ strlen(
+ "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n"));
+ }
+ else if (tmpCommand != NULL)
+ {
+ tmpLen = (uint8_t)strlen(cmd);
+ /* Compare with last command. Push back to history buffer if different */
+ if (tmpLen != (uint8_t)SHELL_StringCompare(cmd, shellContextHandle->hist_buf[0], (int32_t)strlen(cmd)))
+ {
+ for (i = SHELL_HISTORY_COUNT - 1U; i > 0U; i--)
+ {
+ (void)memset(shellContextHandle->hist_buf[i], (int)'\0', SHELL_BUFFER_SIZE);
+ tmpLen = (uint8_t)strlen(shellContextHandle->hist_buf[i - 1U]);
+ (void)memcpy(shellContextHandle->hist_buf[i], shellContextHandle->hist_buf[i - 1U], tmpLen);
+ }
+ (void)memset(shellContextHandle->hist_buf[0], (int)'\0', SHELL_BUFFER_SIZE);
+ tmpLen = (uint8_t)strlen(cmd);
+ (void)memcpy(shellContextHandle->hist_buf[0], cmd, tmpLen);
+ if (shellContextHandle->hist_count < SHELL_HISTORY_COUNT)
+ {
+ shellContextHandle->hist_count++;
+ }
+ }
+ (void)tmpCommand->pFuncCallBack(shellContextHandle, argc, argv);
+ }
+ else
+ {
+ SHELL_WriteWithCopy(
+ shellContextHandle,
+ "\r\nCommand not recognized. Enter 'help' to view a list of available commands.\r\n\r\n",
+ strlen("\r\nCommand not recognized. Enter 'help' to view a list of available commands.\r\n\r\n"));
+ }
+}
+
+static void SHELL_GetHistoryCommand(shell_context_handle_t *shellContextHandle, uint8_t hist_pos)
+{
+ uint32_t i;
+ uint32_t tmp;
+
+ if (shellContextHandle->hist_buf[0][0] == '\0')
+ {
+ shellContextHandle->hist_current = 0;
+ return;
+ }
+
+#if 0 /*hist_pos is passed from hist_current. And hist_current is only changed in case 'A'/'B',as hist_count is 3 \
+ most, it can't be more than 3 */
+ if (hist_pos >= SHELL_HISTORY_COUNT)
+ {
+ hist_pos = SHELL_HISTORY_COUNT - 1U;
+ }
+#endif
+
+ tmp = strlen(shellContextHandle->line);
+ /* Clear current if have */
+ if (tmp > 0U)
+ {
+ (void)memset(shellContextHandle->line, (int)'\0', tmp);
+ for (i = 0U; i < tmp; i++)
+ {
+ SHELL_WriteWithCopy(shellContextHandle, "\b \b", 3);
+ }
+ }
+
+ shellContextHandle->l_pos = (uint8_t)strlen(shellContextHandle->hist_buf[hist_pos]);
+ shellContextHandle->c_pos = shellContextHandle->l_pos;
+ (void)memcpy(shellContextHandle->line, shellContextHandle->hist_buf[hist_pos], shellContextHandle->l_pos);
+ (void)SHELL_Write(shellContextHandle, shellContextHandle->hist_buf[hist_pos],
+ strlen(shellContextHandle->hist_buf[hist_pos]));
+}
+
+static void SHELL_AutoComplete(shell_context_handle_t *shellContextHandle)
+{
+ int32_t minLen;
+ list_element_handle_t p;
+ shell_command_t *tmpCommand = NULL;
+ const char *namePtr;
+ const char *cmdName;
+
+ minLen = (int32_t)SHELL_BUFFER_SIZE;
+ namePtr = NULL;
+
+ /* Empty tab, list all commands */
+ if (shellContextHandle->line[0] == '\0')
+ {
+ (void)SHELL_HelpCommand(shellContextHandle, 0, NULL);
+ return;
+ }
+
+ SHELL_WriteWithCopy(shellContextHandle, "\r\n", 2);
+
+ /* Do auto complete */
+ p = LIST_GetHead(&shellContextHandle->commandContextListHead);
+ while (p != NULL)
+ {
+ tmpCommand = SHEEL_COMMAND_POINTER(p);
+ cmdName = tmpCommand->pcCommand;
+ if (SHELL_StringCompare(shellContextHandle->line, cmdName, (int32_t)strlen(shellContextHandle->line)) == 0)
+ {
+ /* Show possible matches */
+ (void)SHELL_Printf(shellContextHandle, "%s ", cmdName);
+ if (minLen > ((int32_t)strlen(cmdName)))
+ {
+ namePtr = cmdName;
+ minLen = (int32_t)strlen(namePtr);
+ }
+ }
+ p = LIST_GetNext(p);
+ }
+ /* Auto complete string */
+ if (namePtr != NULL)
+ {
+ (void)memcpy(shellContextHandle->line, namePtr, (uint32_t)minLen);
+ }
+ SHELL_PrintPrompt(shellContextHandle);
+ (void)SHELL_Write(shellContextHandle, shellContextHandle->line, strlen(shellContextHandle->line));
+ return;
+}
+
+static int32_t SHELL_StringCompare(const char *str1, const char *str2, int32_t count)
+{
+ while ((bool)(count--))
+ {
+ if (*str1++ != *str2++)
+ {
+ return (int32_t)(*(str1 - 1) - *(str2 - 1));
+ }
+ }
+ return 0;
+}
+
+static int32_t SHELL_ParseLine(const char *cmd, uint32_t len, char *argv[])
+{
+ uint32_t argc;
+ char *p;
+ uint32_t position;
+
+ /* Init params */
+ (void)memset(s_paramBuffer, (int)'\0', len + 1U);
+ (void)memcpy(s_paramBuffer, cmd, len);
+
+ p = s_paramBuffer;
+ position = 0;
+ argc = 0;
+
+ while (position < len)
+ {
+ /* Skip all blanks */
+ while ((position < len) && ((char)(*p) == ' '))
+ {
+ *p = '\0';
+ p++;
+ position++;
+ }
+
+ if (position >= len)
+ {
+ break;
+ }
+
+ /* Process begin of a string */
+ if (*p == '"')
+ {
+ p++;
+ position++;
+ argv[argc] = p;
+ argc++;
+ /* Skip this string */
+ while ((*p != '"') && (position < len))
+ {
+ p++;
+ position++;
+ }
+ /* Skip '"' */
+ *p = '\0';
+ p++;
+ position++;
+ }
+ else /* Normal char */
+ {
+ argv[argc] = p;
+ argc++;
+ while (((char)*p != ' ') && (position < len))
+ {
+ p++;
+ position++;
+ }
+ }
+ }
+ return (int32_t)argc;
+}
+
+static shell_status_t SHELL_GetChar(shell_context_handle_t *shellContextHandle, uint8_t *ch)
+{
+ shell_status_t status;
+
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+ if (NULL == shellContextHandle->serialHandle)
+ {
+ int ret;
+ ret = getchar();
+ if (ret > 0)
+ {
+ *ch = (uint8_t)ret;
+ status = kStatus_SHELL_Success;
+ }
+ else
+ {
+ status = kStatus_SHELL_Error;
+ }
+ }
+ else
+#endif
+ {
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+ uint32_t length = 0;
+
+ (void)SerialManager_TryRead(shellContextHandle->serialReadHandle, ch, 1, &length);
+
+ if (length > 0U)
+ {
+ status = kStatus_SHELL_Success;
+ }
+ else
+ {
+ status = kStatus_SHELL_Error;
+ }
+#else
+ status = (shell_status_t)SerialManager_ReadBlocking(shellContextHandle->serialReadHandle, ch, 1);
+#endif
+ }
+
+ return status;
+}
+
+shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHandle, char *prompt)
+{
+ shell_context_handle_t *shellContextHandle;
+ serial_manager_status_t status = kStatus_SerialManager_Error;
+ (void)status;
+
+ assert(shellHandle);
+#if !(!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+ assert(serialHandle);
+#endif
+ assert(prompt);
+ assert(SHELL_HANDLE_SIZE >= sizeof(shell_context_handle_t));
+
+ shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+ /* memory set for shellHandle */
+ (void)memset(shellHandle, 0, SHELL_HANDLE_SIZE);
+
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+ if (NULL == serialHandle)
+ {
+ }
+ else
+#endif
+ {
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+
+#if defined(OSA_USED)
+
+#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U))
+ (void)COMMON_TASK_init();
+#else
+ if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)shellContextHandle->event, 1U))
+ {
+ return kStatus_SHELL_Error;
+ }
+
+ if (KOSA_StatusSuccess !=
+ OSA_TaskCreate((osa_task_handle_t)shellContextHandle->taskId, OSA_TASK(SHELL_Task), shellContextHandle))
+ {
+ return kStatus_SHELL_Error;
+ }
+#endif
+
+#endif
+
+#endif
+ }
+
+ shellContextHandle->prompt = prompt;
+ shellContextHandle->serialHandle = serialHandle;
+
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+ if (NULL == serialHandle)
+ {
+ }
+ else
+#endif
+ {
+ shellContextHandle->serialWriteHandle = (serial_write_handle_t)&shellContextHandle->serialWriteHandleBuffer[0];
+ status = SerialManager_OpenWriteHandle(shellContextHandle->serialHandle, shellContextHandle->serialWriteHandle);
+ assert(kStatus_SerialManager_Success == status);
+
+ shellContextHandle->serialReadHandle = (serial_read_handle_t)&shellContextHandle->serialReadHandleBuffer[0];
+ status = SerialManager_OpenReadHandle(shellContextHandle->serialHandle, shellContextHandle->serialReadHandle);
+ assert(kStatus_SerialManager_Success == status);
+
+#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+ status = SerialManager_InstallRxCallback(shellContextHandle->serialReadHandle, SHELL_SerialManagerRxCallback,
+ shellContextHandle);
+ assert(kStatus_SerialManager_Success == status);
+#endif
+ (void)status;
+ }
+
+ (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(help));
+ (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(exit));
+
+ SHELL_WriteWithCopy(shellContextHandle, "\r\nSHELL build: ", strlen("\r\nSHELL build: "));
+ SHELL_WriteWithCopy(shellContextHandle, __DATE__, strlen(__DATE__));
+ SHELL_WriteWithCopy(shellContextHandle, "\r\nCopyright 2020 NXP\r\n", strlen("\r\nCopyright 2020 NXP\r\n"));
+ SHELL_PrintPrompt(shellContextHandle);
+
+ return kStatus_SHELL_Success;
+}
+
+shell_status_t SHELL_RegisterCommand(shell_handle_t shellHandle, shell_command_t *shellCommand)
+{
+ shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle;
+ assert(shellHandle);
+ assert(shellCommand);
+
+ /* memory set for shellHandle */
+ (void)memset(&shellCommand->link, 0, sizeof(shellCommand->link));
+
+ (void)LIST_AddTail(&shellContextHandle->commandContextListHead, &shellCommand->link);
+
+ return kStatus_SHELL_Success;
+}
+
+shell_status_t SHELL_UnregisterCommand(shell_command_t *shellCommand)
+{
+ assert(shellCommand);
+
+ (void)LIST_RemoveElement(&shellCommand->link);
+
+ /* memory set for shellHandle */
+ (void)memset(&shellCommand->link, 0, sizeof(shellCommand->link));
+
+ return kStatus_SHELL_Success;
+}
+
+shell_status_t SHELL_Write(shell_handle_t shellHandle, char *buffer, uint32_t length)
+{
+ shell_context_handle_t *shellContextHandle;
+ uint32_t primask;
+ shell_status_t status;
+
+ assert(shellHandle);
+ assert(buffer);
+
+ if (!(bool)length)
+ {
+ return kStatus_SHELL_Success;
+ }
+
+ shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+ primask = DisableGlobalIRQ();
+ if ((bool)shellContextHandle->printBusy)
+ {
+ EnableGlobalIRQ(primask);
+ return kStatus_SHELL_Error;
+ }
+ shellContextHandle->printBusy = 1U;
+ EnableGlobalIRQ(primask);
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+ if (NULL == shellContextHandle->serialHandle)
+ {
+ status = kStatus_SHELL_Success;
+ for (uint32_t index = 0; index < length; index++)
+ {
+ (void)putchar(buffer[index]);
+ }
+ }
+ else
+#endif
+ {
+ status = (shell_status_t)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle, (uint8_t *)buffer,
+ length);
+ }
+
+ shellContextHandle->printBusy = 0U;
+
+ return status;
+}
+
+/* For MISRA to fix const */
+static void SHELL_WriteWithCopy(shell_handle_t shellHandle, const char *buffer, uint32_t length)
+{
+ char s_shellWriteCopyBuffer[128];
+
+ assert(length <= 128UL);
+
+ (void)memcpy(s_shellWriteCopyBuffer, buffer, length);
+ (void)SHELL_Write(shellHandle, s_shellWriteCopyBuffer, length);
+}
+
+int SHELL_Printf(shell_handle_t shellHandle, const char *formatString, ...)
+{
+ shell_context_handle_t *shellContextHandle;
+ uint32_t length;
+ uint32_t primask;
+ va_list ap;
+
+ assert(shellHandle);
+ assert(formatString);
+
+ shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+ primask = DisableGlobalIRQ();
+ if ((bool)shellContextHandle->printBusy)
+ {
+ EnableGlobalIRQ(primask);
+ return -1;
+ }
+ shellContextHandle->printBusy = 1U;
+ EnableGlobalIRQ(primask);
+
+ va_start(ap, formatString);
+
+ shellContextHandle->printLength = 0U;
+ length = (uint32_t)SHELL_Sprintf(shellHandle, formatString, ap);
+#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1)))
+ if (NULL == shellContextHandle->serialHandle)
+ {
+ for (uint32_t index = 0; index < length; index++)
+ {
+ (void)putchar(shellContextHandle->printBuffer[index]);
+ }
+ }
+ else
+#endif
+ {
+ (void)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle,
+ (uint8_t *)shellContextHandle->printBuffer, length);
+ }
+ va_end(ap);
+
+ shellContextHandle->printBusy = 0U;
+ return (int32_t)shellContextHandle->printLength;
+}
+
+void SHELL_ChangePrompt(shell_handle_t shellHandle, char *prompt)
+{
+ shell_context_handle_t *shellContextHandle;
+ assert(shellHandle);
+ assert(prompt);
+
+ shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+ shellContextHandle->prompt = prompt;
+ SHELL_PrintPrompt(shellContextHandle);
+}
+
+void SHELL_PrintPrompt(shell_handle_t shellHandle)
+{
+ shell_context_handle_t *shellContextHandle;
+ assert(shellHandle);
+
+ shellContextHandle = (shell_context_handle_t *)shellHandle;
+
+ SHELL_WriteWithCopy(shellContextHandle, "\r\n", 2U); /* MISRA C-2012 Rule 7.4 */
+ (void)SHELL_Write(shellContextHandle, shellContextHandle->prompt, strlen(shellContextHandle->prompt));
+}
diff --git a/devices/88MW320/utilities/fsl_shell.h b/devices/88MW320/utilities/fsl_shell.h
new file mode 100644
index 000000000..28eace717
--- /dev/null
+++ b/devices/88MW320/utilities/fsl_shell.h
@@ -0,0 +1,292 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __FSL_SHELL_H__
+#define __FSL_SHELL_H__
+
+/*!
+ * @addtogroup SHELL
+ * @{
+ */
+
+#include "fsl_common.h"
+#include "fsl_component_serial_manager.h"
+#include "fsl_component_generic_list.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Whether use non-blocking mode. */
+#ifndef SHELL_NON_BLOCKING_MODE
+#define SHELL_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+
+/*! @brief Macro to set on/off auto-complete feature. */
+#define SHELL_AUTO_COMPLETE (1U)
+
+/*! @brief Macro to set console buffer size. */
+#ifndef SHELL_BUFFER_SIZE
+#define SHELL_BUFFER_SIZE (64U)
+#endif
+
+/*! @brief Macro to set maximum arguments in command. */
+#define SHELL_MAX_ARGS (8U)
+
+/*! @brief Macro to set maximum count of history commands. */
+#ifndef SHELL_HISTORY_COUNT
+#define SHELL_HISTORY_COUNT (3U)
+#endif
+
+/*! @brief Macro to bypass arguments check */
+#define SHELL_IGNORE_PARAMETER_COUNT (0xFF)
+
+/*! @brief The handle size of the shell module. It is the sum of the SHELL_HISTORY_COUNT * SHELL_BUFFER_SIZE +
+ * SHELL_BUFFER_SIZE + SERIAL_MANAGER_READ_HANDLE_SIZE + SERIAL_MANAGER_WRITE_HANDLE_SIZE*/
+#define SHELL_HANDLE_SIZE \
+ (160U + SHELL_HISTORY_COUNT * SHELL_BUFFER_SIZE + SHELL_BUFFER_SIZE + SERIAL_MANAGER_READ_HANDLE_SIZE + \
+ SERIAL_MANAGER_WRITE_HANDLE_SIZE)
+
+/*! @brief Macro to determine whether use common task. */
+#ifndef SHELL_USE_COMMON_TASK
+#define SHELL_USE_COMMON_TASK (0U)
+#endif
+
+/*! @brief Macro to set shell task priority. */
+#ifndef SHELL_TASK_PRIORITY
+#define SHELL_TASK_PRIORITY (2U)
+#endif
+
+/*! @brief Macro to set shell task stack size. */
+#ifndef SHELL_TASK_STACK_SIZE
+#define SHELL_TASK_STACK_SIZE (1000U)
+#endif
+
+/*! @brief Shell status */
+typedef enum _shell_status
+{
+ kStatus_SHELL_Success = kStatus_Success, /*!< Success */
+ kStatus_SHELL_Error = MAKE_STATUS(kStatusGroup_SHELL, 1), /*!< Failed */
+ kStatus_SHELL_OpenWriteHandleFailed = MAKE_STATUS(kStatusGroup_SHELL, 2), /*!< Open write handle failed */
+ kStatus_SHELL_OpenReadHandleFailed = MAKE_STATUS(kStatusGroup_SHELL, 3), /*!< Open read handle failed */
+} shell_status_t;
+
+/*! @brief The handle of the shell module */
+typedef void *shell_handle_t;
+
+/*! @brief User command function prototype. */
+typedef shell_status_t (*cmd_function_t)(shell_handle_t shellHandle, int32_t argc, char **argv);
+
+/*! @brief User command data configuration structure. */
+typedef struct _shell_command
+{
+ const char *pcCommand; /*!< The command that is executed. For example "help". It must be all lower case. */
+ char *pcHelpString; /*!< String that describes how to use the command. It should start with the command itself,
+ and end with "\r\n". For example "help: Returns a list of all the commands\r\n". */
+ const cmd_function_t
+ pFuncCallBack; /*!< A pointer to the callback function that returns the output generated by the command. */
+ uint8_t cExpectedNumberOfParameters; /*!< Commands expect a fixed number of parameters, which may be zero. */
+ list_element_t link; /*!< link of the element */
+} shell_command_t;
+
+/*!
+ * @brief Defines the shell handle
+ *
+ * This macro is used to define a 4 byte aligned shell handle.
+ * Then use "(shell_handle_t)name" to get the shell handle.
+ *
+ * The macro should be global and could be optional. You could also define shell handle by yourself.
+ *
+ * This is an example,
+ * @code
+ * SHELL_HANDLE_DEFINE(shellHandle);
+ * @endcode
+ *
+ * @param name The name string of the shell handle.
+ */
+#define SHELL_HANDLE_DEFINE(name) uint32_t name[((SHELL_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]
+
+#if defined(__ICCARM__)
+/* disable misra 19.13 */
+_Pragma("diag_suppress=Pm120")
+#endif
+/*!
+ * @brief Defines the shell command structure
+ *
+ * This macro is used to define the shell command structure #shell_command_t.
+ * And then uses the macro SHELL_COMMAND to get the command structure pointer.
+ * The macro should not be used in any function.
+ *
+ * This is a example,
+ * @code
+ * SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0);
+ * SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(exit));
+ * @endcode
+ *
+ * @param command The command string of the command. The double quotes do not need. Such as exit for "exit",
+ * help for "Help", read for "read".
+ * @param descriptor The description of the command is used for showing the command usage when "help" is typing.
+ * @param callback The callback of the command is used to handle the command line when the input command is matched.
+ * @param paramCount The max parameter count of the current command.
+ */
+#define SHELL_COMMAND_DEFINE(command, descriptor, callback, paramCount) \
+ \
+ shell_command_t g_shellCommand##command = { \
+ (#command), (descriptor), (callback), (paramCount), {0}, \
+ }
+
+/*!
+ * @brief Gets the shell command pointer
+ *
+ * This macro is used to get the shell command pointer. The macro should not be used before the macro
+ * SHELL_COMMAND_DEFINE is used.
+ *
+ * @param command The command string of the command. The double quotes do not need. Such as exit for "exit",
+ * help for "Help", read for "read".
+ */
+#define SHELL_COMMAND(command) &g_shellCommand##command
+
+#if defined(__ICCARM__)
+ _Pragma("diag_default=Pm120")
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+ extern "C"
+{
+#endif /* _cplusplus */
+
+ /*!
+ * @name Shell functional operation
+ * @{
+ */
+
+ /*!
+ * @brief Initializes the shell module
+ *
+ * This function must be called before calling all other Shell functions.
+ * Call operation the Shell commands with user-defined settings.
+ * The example below shows how to set up the Shell and
+ * how to call the SHELL_Init function by passing in these parameters.
+ * This is an example.
+ * @code
+ * static SHELL_HANDLE_DEFINE(s_shellHandle);
+ * SHELL_Init((shell_handle_t)s_shellHandle, (serial_handle_t)s_serialHandle, "Test@SHELL>");
+ * @endcode
+ * @param shellHandle Pointer to point to a memory space of size #SHELL_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices.
+ * You can define the handle in the following two ways:
+ * #SHELL_HANDLE_DEFINE(shellHandle);
+ * or
+ * uint32_t shellHandle[((SHELL_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))];
+ * @param serialHandle The serial manager module handle pointer.
+ * @param prompt The string prompt pointer of Shell. Only the global variable can be passed.
+ * @retval kStatus_SHELL_Success The shell initialization succeed.
+ * @retval kStatus_SHELL_Error An error occurred when the shell is initialized.
+ * @retval kStatus_SHELL_OpenWriteHandleFailed Open the write handle failed.
+ * @retval kStatus_SHELL_OpenReadHandleFailed Open the read handle failed.
+ */
+ shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHandle, char *prompt);
+
+ /*!
+ * @brief Registers the shell command
+ *
+ * This function is used to register the shell command by using the command configuration shell_command_config_t.
+ * This is a example,
+ * @code
+ * SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0);
+ * SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(exit));
+ * @endcode
+ * @param shellHandle The shell module handle pointer.
+ * @param shellCommand The command element.
+ * @retval kStatus_SHELL_Success Successfully register the command.
+ * @retval kStatus_SHELL_Error An error occurred.
+ */
+ shell_status_t SHELL_RegisterCommand(shell_handle_t shellHandle, shell_command_t * shellCommand);
+
+ /*!
+ * @brief Unregisters the shell command
+ *
+ * This function is used to unregister the shell command.
+ *
+ * @param shellCommand The command element.
+ * @retval kStatus_SHELL_Success Successfully unregister the command.
+ */
+ shell_status_t SHELL_UnregisterCommand(shell_command_t * shellCommand);
+
+ /*!
+ * @brief Sends data to the shell output stream.
+ *
+ * This function is used to send data to the shell output stream.
+ *
+ * @param shellHandle The shell module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SHELL_Success Successfully send data.
+ * @retval kStatus_SHELL_Error An error occurred.
+ */
+ shell_status_t SHELL_Write(shell_handle_t shellHandle, char *buffer, uint32_t length);
+
+ /*!
+ * @brief Writes formatted output to the shell output stream.
+ *
+ * Call this function to write a formatted output to the shell output stream.
+ *
+ * @param shellHandle The shell module handle pointer.
+ *
+ * @param formatString Format string.
+ * @return Returns the number of characters printed or a negative value if an error occurs.
+ */
+ int SHELL_Printf(shell_handle_t shellHandle, const char *formatString, ...);
+
+ /*!
+ * @brief Change shell prompt.
+ *
+ * Call this function to change shell prompt.
+ *
+ * @param shellHandle The shell module handle pointer.
+ *
+ * @param prompt The string which will be used for command prompt
+ * @return NULL.
+ */
+ void SHELL_ChangePrompt(shell_handle_t shellHandle, char *prompt);
+
+ /*!
+ * @brief Print shell prompt.
+ *
+ * Call this function to print shell prompt.
+ *
+ * @param shellHandle The shell module handle pointer.
+ *
+ * @return NULL.
+ */
+ void SHELL_PrintPrompt(shell_handle_t shellHandle);
+
+/*!
+ * @brief The task function for Shell.
+ * The task function for Shell; The function should be polled by upper layer.
+ * This function does not return until Shell command exit was called.
+ *
+ * @param shellHandle The shell module handle pointer.
+ */
+#if !(defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U))
+ void SHELL_Task(shell_handle_t shellHandle);
+#endif
+
+ /* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* __FSL_SHELL_H__ */
diff --git a/devices/K32L3A60/device_CMSIS.cmake b/devices/K32L3A60/device_CMSIS.cmake
index 758c02b4d..5b75e7524 100644
--- a/devices/K32L3A60/device_CMSIS.cmake
+++ b/devices/K32L3A60/device_CMSIS.cmake
@@ -5,7 +5,7 @@ if(NOT DEVICE_CMSIS_INCLUDED)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
)
- target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/.
)
diff --git a/devices/LPC54114/device_CMSIS.cmake b/devices/LPC54114/device_CMSIS.cmake
index f3832a66c..377274b5f 100644
--- a/devices/LPC54114/device_CMSIS.cmake
+++ b/devices/LPC54114/device_CMSIS.cmake
@@ -5,7 +5,7 @@ if(NOT DEVICE_CMSIS_INCLUDED)
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
)
- target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/.
)
diff --git a/drivers/common/fsl_common.c b/drivers/common/fsl_common.c
index ec52acbfa..748a6c97f 100644
--- a/drivers/common/fsl_common.c
+++ b/drivers/common/fsl_common.c
@@ -24,16 +24,17 @@ typedef struct _mem_align_control_block
#if defined(ENABLE_RAM_VECTOR_TABLE)
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
-#ifdef __VECTOR_TABLE
-#undef __VECTOR_TABLE
-#endif
-
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
+/* Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h*/
+#ifdef __VECTOR_TABLE
+#undef __VECTOR_TABLE
+#endif
+
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
@@ -63,9 +64,9 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
SCB->VTOR = (uint32_t)__VECTOR_RAM;
}
- ret = __VECTOR_RAM[(int32_t)irq + 16];
+ ret = __VECTOR_RAM[irq + 16];
/* make sure the __VECTOR_RAM is noncachable */
- __VECTOR_RAM[(int32_t)irq + 16] = irqHandler;
+ __VECTOR_RAM[irq + 16] = irqHandler;
EnableGlobalIRQ(irqMaskValue);
SDK_ISR_EXIT_BARRIER;
@@ -76,17 +77,6 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
#endif /* __GIC_PRIO_BITS. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-
-/*
- * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
- * powerlib should be used instead of these functions.
- */
-#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
-
-/*
- * When the SYSCON STARTER registers are discontinuous, these functions are
- * implemented in fsl_power.c.
- */
#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
void EnableDeepSleepIRQ(IRQn_Type interrupt)
@@ -101,15 +91,15 @@ void EnableDeepSleepIRQ(IRQn_Type interrupt)
intNumber -= 32u;
}
- SYSCON->STARTERSET[index] = 1UL << intNumber;
- (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+ SYSCON->STARTERSET[index] = 1u << intNumber;
+ EnableIRQ(interrupt); /* also enable interrupt at NVIC */
}
void DisableDeepSleepIRQ(IRQn_Type interrupt)
{
uint32_t intNumber = (uint32_t)interrupt;
- (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+ DisableIRQ(interrupt); /* also disable interrupt at NVIC */
uint32_t index = 0;
while (intNumber >= 32u)
@@ -118,31 +108,15 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt)
intNumber -= 32u;
}
- SYSCON->STARTERCLR[index] = 1UL << intNumber;
+ SYSCON->STARTERCLR[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
-#endif /* FSL_FEATURE_POWERLIB_EXTEND */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
void *SDK_Malloc(size_t size, size_t alignbytes)
{
mem_align_cb_t *p_cb = NULL;
- uint32_t alignedsize;
-
- /* Check overflow. */
- alignedsize = SDK_SIZEALIGN(size, alignbytes);
- if (alignedsize < size)
- {
- return NULL;
- }
-
- if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
- {
- return NULL;
- }
-
- alignedsize += alignbytes + sizeof(mem_align_cb_t);
-
+ uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
union
{
void *pointer_value;
@@ -191,7 +165,7 @@ void SDK_Free(void *ptr)
* @param count Counts of loop needed for dalay.
*/
#if defined(SDK_DELAY_USE_DWT) && defined(DWT)
-static void enableCpuCycleCounter(void)
+void enableCpuCycleCounter(void)
{
/* Make sure the DWT trace fucntion is enabled. */
if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR))
@@ -209,18 +183,18 @@ static void enableCpuCycleCounter(void)
}
}
-static uint32_t getCpuCycleCount(void)
+uint32_t getCpuCycleCount(void)
{
return DWT->CYCCNT;
}
#elif defined __XCC__
extern uint32_t xthal_get_ccount(void);
-static void enableCpuCycleCounter(void)
+void enableCpuCycleCounter(void)
{
/* do nothing */
}
-static uint32_t getCpuCycleCount(void)
+uint32_t getCpuCycleCount(void)
{
return xthal_get_ccount();
}
@@ -262,17 +236,17 @@ static void DelayLoop(uint32_t count)
/*!
* @brief Delay at least for some time.
* Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have
- * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and
- * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports
+ * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delay_us and
+ * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delay_us only supports
* up to 4294967 in current code. If long time delay is needed, please implement a new delay function.
*
- * @param delayTime_us Delay time in unit of microsecond.
+ * @param delay_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
-void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
+void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz)
{
- assert(0U != delayTime_us);
- uint64_t count = USEC_TO_COUNT(delayTime_us, coreClock_Hz);
+ assert(0U != delay_us);
+ uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz);
assert(count <= UINT32_MAX);
#if defined(SDK_DELAY_USE_DWT) && defined(DWT) || (defined __XCC__) /* Use DWT for better accuracy */
diff --git a/drivers/common/fsl_common.h b/drivers/common/fsl_common.h
index c7da1b526..349f10c0b 100644
--- a/drivers/common/fsl_common.h
+++ b/drivers/common/fsl_common.h
@@ -15,7 +15,7 @@
#include
#include
-#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__)
+#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION))
#include
#endif
@@ -48,7 +48,7 @@
/*! @name Driver version */
/*@{*/
/*! @brief common driver version. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 9))
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 8))
/*@}*/
/* Debug console type definition. */
@@ -172,6 +172,9 @@ enum _status_groups
kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */
kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */
kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */
+ kStatusGroup_SDIOC = 155, /*!< Group number for SDIOC status codes. */
+
+ kStatusGroup_SSP = 156, /*!< Group number for SSP status codes. */
};
/*! \public
@@ -754,7 +757,7 @@ void DefaultISR(void);
}
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
- else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ else if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
{
status = kStatus_Fail;
}
@@ -798,7 +801,7 @@ void DefaultISR(void);
}
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
- else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ else if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
{
status = kStatus_Fail;
}
@@ -879,12 +882,6 @@ void DefaultISR(void);
#endif /* ENABLE_RAM_VECTOR_TABLE. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-
- /*
- * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value,
- * powerlib should be used instead of these functions.
- */
-#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0))
/*!
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
*
@@ -914,7 +911,6 @@ void DefaultISR(void);
* @param interrupt The IRQ number.
*/
void DisableDeepSleepIRQ(IRQn_Type interrupt);
-#endif /* FSL_FEATURE_POWERLIB_EXTEND */
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
/*!
@@ -940,10 +936,10 @@ void DefaultISR(void);
* Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
* if precise delay count was needed, please implement a new delay function with hardware timer.
*
- * @param delayTime_us Delay time in unit of microsecond.
+ * @param delay_us Delay time in unit of microsecond.
* @param coreClock_Hz Core clock frequency with Hz.
*/
- void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
+ void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
#if defined(__cplusplus)
}
diff --git a/drivers/dspi/driver_dspi_freertos.cmake b/drivers/dspi/driver_dspi_freertos.cmake
index cee51beb9..749429d37 100644
--- a/drivers/dspi/driver_dspi_freertos.cmake
+++ b/drivers/dspi/driver_dspi_freertos.cmake
@@ -11,6 +11,9 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
+if(${MCUX_DEVICE} STREQUAL "MK22F51212")
+ include(middleware_freertos-kernel_MK22F51212)
+endif()
if(${MCUX_DEVICE} STREQUAL "MK28FA15")
include(middleware_freertos-kernel_MK28FA15)
endif()
@@ -23,8 +26,5 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
include(middleware_freertos-kernel_MKV31F51212)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
- include(middleware_freertos-kernel_MK22F51212)
-endif()
include(driver_dspi)
diff --git a/drivers/ecspi/driver_ecspi_freertos.cmake b/drivers/ecspi/driver_ecspi_freertos.cmake
index a08b0d031..934cdf60c 100644
--- a/drivers/ecspi/driver_ecspi_freertos.cmake
+++ b/drivers/ecspi/driver_ecspi_freertos.cmake
@@ -11,14 +11,14 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
- include(middleware_freertos-kernel_MIMX8MQ6)
-endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
include(middleware_freertos-kernel_MIMX8MM6)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
include(middleware_freertos-kernel_MIMX8MN6)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
+ include(middleware_freertos-kernel_MIMX8MQ6)
+endif()
include(driver_ecspi)
diff --git a/drivers/enet/driver_enet.cmake b/drivers/enet/driver_enet.cmake
index 0a96ede40..29d0b794a 100644
--- a/drivers/enet/driver_enet.cmake
+++ b/drivers/enet/driver_enet.cmake
@@ -11,18 +11,6 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(driver_common)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(driver_common)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK64F12")
- include(driver_common)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
- include(driver_common)
-endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
include(driver_memory)
endif()
@@ -35,10 +23,22 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(driver_common)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+ include(driver_common)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(driver_common)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(driver_common)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(driver_common)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MK64F12")
+ include(driver_common)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MK66F18")
include(driver_common)
endif()
diff --git a/drivers/flexcan/driver_flexcan_edma.cmake b/drivers/flexcan/driver_flexcan_edma.cmake
index 0b09944d5..5b3f4e6a5 100644
--- a/drivers/flexcan/driver_flexcan_edma.cmake
+++ b/drivers/flexcan/driver_flexcan_edma.cmake
@@ -11,23 +11,23 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(driver_edma)
-endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
include(driver_dma3)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
include(driver_dma3)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
- include(driver_edma)
-endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
include(driver_dma3)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(driver_edma)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(driver_edma)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
+ include(driver_edma)
+endif()
include(driver_flexcan)
diff --git a/drivers/flexcomm/driver_flexcomm_i2c_freertos.cmake b/drivers/flexcomm/driver_flexcomm_i2c_freertos.cmake
index 8b905551a..52943a05a 100644
--- a/drivers/flexcomm/driver_flexcomm_i2c_freertos.cmake
+++ b/drivers/flexcomm/driver_flexcomm_i2c_freertos.cmake
@@ -11,30 +11,30 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
+if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+ include(middleware_freertos-kernel_LPC51U68)
+endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4")
include(middleware_freertos-kernel_LPC54114_cm4)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54628")
include(middleware_freertos-kernel_LPC54628)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
- include(middleware_freertos-kernel_LPC55S16)
-endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018")
include(middleware_freertos-kernel_LPC54S018)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
include(middleware_freertos-kernel_LPC54S018M)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
- include(middleware_freertos-kernel_LPC51U68)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
- include(middleware_freertos-kernel_LPC55S69_cm33_core0)
+if(${MCUX_DEVICE} STREQUAL "LPC55S16")
+ include(middleware_freertos-kernel_LPC55S16)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC55S28")
include(middleware_freertos-kernel_LPC55S28)
endif()
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
+ include(middleware_freertos-kernel_LPC55S69_cm33_core0)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
include(middleware_freertos-kernel_MIMXRT685S_cm33)
endif()
diff --git a/drivers/flexcomm/driver_flexcomm_spi_freertos.cmake b/drivers/flexcomm/driver_flexcomm_spi_freertos.cmake
index 0f0e09ece..befc254d0 100644
--- a/drivers/flexcomm/driver_flexcomm_spi_freertos.cmake
+++ b/drivers/flexcomm/driver_flexcomm_spi_freertos.cmake
@@ -11,30 +11,30 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
+if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+ include(middleware_freertos-kernel_LPC51U68)
+endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4")
include(middleware_freertos-kernel_LPC54114_cm4)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54628")
include(middleware_freertos-kernel_LPC54628)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
- include(middleware_freertos-kernel_LPC55S16)
-endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018")
include(middleware_freertos-kernel_LPC54S018)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
include(middleware_freertos-kernel_LPC54S018M)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
- include(middleware_freertos-kernel_LPC51U68)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
- include(middleware_freertos-kernel_LPC55S69_cm33_core0)
+if(${MCUX_DEVICE} STREQUAL "LPC55S16")
+ include(middleware_freertos-kernel_LPC55S16)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC55S28")
include(middleware_freertos-kernel_LPC55S28)
endif()
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
+ include(middleware_freertos-kernel_LPC55S69_cm33_core0)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
include(middleware_freertos-kernel_MIMXRT685S_cm33)
endif()
diff --git a/drivers/flexcomm/driver_flexcomm_usart_freertos.cmake b/drivers/flexcomm/driver_flexcomm_usart_freertos.cmake
index 31c04f36b..e28546fa5 100644
--- a/drivers/flexcomm/driver_flexcomm_usart_freertos.cmake
+++ b/drivers/flexcomm/driver_flexcomm_usart_freertos.cmake
@@ -11,30 +11,30 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
+if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+ include(middleware_freertos-kernel_LPC51U68)
+endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4")
include(middleware_freertos-kernel_LPC54114_cm4)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54628")
include(middleware_freertos-kernel_LPC54628)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
- include(middleware_freertos-kernel_LPC55S16)
-endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018")
include(middleware_freertos-kernel_LPC54S018)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
include(middleware_freertos-kernel_LPC54S018M)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
- include(middleware_freertos-kernel_LPC51U68)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
- include(middleware_freertos-kernel_LPC55S69_cm33_core0)
+if(${MCUX_DEVICE} STREQUAL "LPC55S16")
+ include(middleware_freertos-kernel_LPC55S16)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC55S28")
include(middleware_freertos-kernel_LPC55S28)
endif()
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
+ include(middleware_freertos-kernel_LPC55S69_cm33_core0)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
include(middleware_freertos-kernel_MIMXRT685S_cm33)
endif()
diff --git a/drivers/i2c/driver_i2c_freertos.cmake b/drivers/i2c/driver_i2c_freertos.cmake
index 623441d6b..0a857c215 100644
--- a/drivers/i2c/driver_i2c_freertos.cmake
+++ b/drivers/i2c/driver_i2c_freertos.cmake
@@ -11,32 +11,32 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MK28FA15")
- include(middleware_freertos-kernel_MK28FA15)
-endif()
if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
include(middleware_freertos-kernel_K32L2B31A)
endif()
+if(${MCUX_DEVICE} STREQUAL "MK22F51212")
+ include(middleware_freertos-kernel_MK22F51212)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MK28FA15")
+ include(middleware_freertos-kernel_MK28FA15)
+endif()
if(${MCUX_DEVICE} STREQUAL "MK64F12")
include(middleware_freertos-kernel_MK64F12)
endif()
if(${MCUX_DEVICE} STREQUAL "MK66F18")
include(middleware_freertos-kernel_MK66F18)
endif()
+if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
+ include(middleware_freertos-kernel_MKL27Z644)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+ include(middleware_freertos-kernel_MKM35Z7)
+endif()
if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
include(middleware_freertos-kernel_MKV11Z7)
endif()
if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
include(middleware_freertos-kernel_MKV31F51212)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
- include(middleware_freertos-kernel_MK22F51212)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
- include(middleware_freertos-kernel_MKM35Z7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
- include(middleware_freertos-kernel_MKL27Z644)
-endif()
include(driver_i2c)
diff --git a/drivers/ii2c/driver_ii2c_freertos.cmake b/drivers/ii2c/driver_ii2c_freertos.cmake
index 386507406..ff6f83eab 100644
--- a/drivers/ii2c/driver_ii2c_freertos.cmake
+++ b/drivers/ii2c/driver_ii2c_freertos.cmake
@@ -11,14 +11,14 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
- include(middleware_freertos-kernel_MIMX8MQ6)
-endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
include(middleware_freertos-kernel_MIMX8MM6)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
include(middleware_freertos-kernel_MIMX8MN6)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
+ include(middleware_freertos-kernel_MIMX8MQ6)
+endif()
include(driver_ii2c)
diff --git a/drivers/iuart/driver_iuart_freertos.cmake b/drivers/iuart/driver_iuart_freertos.cmake
index efb8042b6..3cda0051a 100644
--- a/drivers/iuart/driver_iuart_freertos.cmake
+++ b/drivers/iuart/driver_iuart_freertos.cmake
@@ -11,14 +11,14 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
- include(middleware_freertos-kernel_MIMX8MQ6)
-endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
include(middleware_freertos-kernel_MIMX8MM6)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
include(middleware_freertos-kernel_MIMX8MN6)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
+ include(middleware_freertos-kernel_MIMX8MQ6)
+endif()
include(driver_iuart)
diff --git a/drivers/lpi2c/driver_lpi2c_edma.cmake b/drivers/lpi2c/driver_lpi2c_edma.cmake
index 44929abd8..8551062aa 100644
--- a/drivers/lpi2c/driver_lpi2c_edma.cmake
+++ b/drivers/lpi2c/driver_lpi2c_edma.cmake
@@ -11,13 +11,16 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+ include(driver_edma)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
include(driver_edma)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
@@ -29,31 +32,28 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
include(driver_dma3)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
- include(driver_edma)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
include(driver_edma)
endif()
diff --git a/drivers/lpi2c/driver_lpi2c_freertos.cmake b/drivers/lpi2c/driver_lpi2c_freertos.cmake
index 3eb797f53..6c63381dd 100644
--- a/drivers/lpi2c/driver_lpi2c_freertos.cmake
+++ b/drivers/lpi2c/driver_lpi2c_freertos.cmake
@@ -11,17 +11,14 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(middleware_freertos-kernel_MIMXRT1052)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(middleware_freertos-kernel_MIMXRT1064)
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
+ include(middleware_freertos-kernel_K32L2A41A)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
- include(middleware_freertos-kernel_MKE15Z7)
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+ include(middleware_freertos-kernel_K32L3A60_cm4)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
- include(middleware_freertos-kernel_MKE16Z4)
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+ include(middleware_freertos-kernel_MCIMX7U5)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
include(middleware_freertos-kernel_MIMX8QM6_cm4_core0)
@@ -35,20 +32,23 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(middleware_freertos-kernel_MIMXRT1021)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+ include(middleware_freertos-kernel_MIMXRT1024)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(middleware_freertos-kernel_MIMXRT1052)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(middleware_freertos-kernel_MIMXRT1062)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
- include(middleware_freertos-kernel_K32L3A60_cm4)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
- include(middleware_freertos-kernel_MCIMX7U5)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(middleware_freertos-kernel_MIMXRT1064)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
- include(middleware_freertos-kernel_MIMXRT1024)
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
+ include(middleware_freertos-kernel_MKE15Z7)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
- include(middleware_freertos-kernel_K32L2A41A)
+if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
+ include(middleware_freertos-kernel_MKE16Z4)
endif()
include(driver_lpi2c)
diff --git a/drivers/lpspi/driver_lpspi_edma.cmake b/drivers/lpspi/driver_lpspi_edma.cmake
index 201c41b64..d0e5e0fc1 100644
--- a/drivers/lpspi/driver_lpspi_edma.cmake
+++ b/drivers/lpspi/driver_lpspi_edma.cmake
@@ -11,13 +11,16 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+ include(driver_edma)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
include(driver_edma)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
@@ -26,31 +29,28 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
include(driver_dma3)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
- include(driver_edma)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
include(driver_edma)
endif()
diff --git a/drivers/lpspi/driver_lpspi_freertos.cmake b/drivers/lpspi/driver_lpspi_freertos.cmake
index cdb7ac5b4..e4aad1928 100644
--- a/drivers/lpspi/driver_lpspi_freertos.cmake
+++ b/drivers/lpspi/driver_lpspi_freertos.cmake
@@ -11,17 +11,17 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(middleware_freertos-kernel_MIMXRT1052)
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
+ include(middleware_freertos-kernel_K32L2A41A)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(middleware_freertos-kernel_MIMXRT1064)
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
+ include(middleware_freertos-kernel_K32L3A60_cm0plus)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
- include(middleware_freertos-kernel_MKE15Z7)
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+ include(middleware_freertos-kernel_K32L3A60_cm4)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
- include(middleware_freertos-kernel_MKE16Z4)
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+ include(middleware_freertos-kernel_MCIMX7U5)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
include(middleware_freertos-kernel_MIMX8QM6_cm4_core0)
@@ -29,29 +29,29 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
include(middleware_freertos-kernel_MIMX8QM6_cm4_core1)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+ include(middleware_freertos-kernel_MIMXRT1015)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(middleware_freertos-kernel_MIMXRT1021)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
- include(middleware_freertos-kernel_MIMXRT1062)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
- include(middleware_freertos-kernel_K32L3A60_cm0plus)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+ include(middleware_freertos-kernel_MIMXRT1024)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
- include(middleware_freertos-kernel_K32L3A60_cm4)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(middleware_freertos-kernel_MIMXRT1052)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
- include(middleware_freertos-kernel_MCIMX7U5)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
+ include(middleware_freertos-kernel_MIMXRT1062)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
- include(middleware_freertos-kernel_MIMXRT1024)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(middleware_freertos-kernel_MIMXRT1064)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
- include(middleware_freertos-kernel_K32L2A41A)
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
+ include(middleware_freertos-kernel_MKE15Z7)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
- include(middleware_freertos-kernel_MIMXRT1015)
+if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
+ include(middleware_freertos-kernel_MKE16Z4)
endif()
include(driver_lpspi)
diff --git a/drivers/lpuart/driver_lpuart_edma.cmake b/drivers/lpuart/driver_lpuart_edma.cmake
index a36c62401..e53b34212 100644
--- a/drivers/lpuart/driver_lpuart_edma.cmake
+++ b/drivers/lpuart/driver_lpuart_edma.cmake
@@ -11,19 +11,13 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(driver_edma)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(driver_edma)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK28FA15")
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
include(driver_edma)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
@@ -32,37 +26,43 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
include(driver_dma3)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
- include(driver_edma)
+if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
+ include(driver_dma3)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
- include(driver_dma3)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+ include(driver_edma)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(driver_edma)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+ include(driver_edma)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(driver_edma)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+if(${MCUX_DEVICE} STREQUAL "MK22F51212")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+if(${MCUX_DEVICE} STREQUAL "MK28FA15")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+if(${MCUX_DEVICE} STREQUAL "MK66F18")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
include(driver_edma)
endif()
diff --git a/drivers/lpuart/driver_lpuart_freertos.cmake b/drivers/lpuart/driver_lpuart_freertos.cmake
index 2c3df5fff..f83137d8c 100644
--- a/drivers/lpuart/driver_lpuart_freertos.cmake
+++ b/drivers/lpuart/driver_lpuart_freertos.cmake
@@ -11,26 +11,20 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(middleware_freertos-kernel_MIMXRT1052)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(middleware_freertos-kernel_MIMXRT1064)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK28FA15")
- include(middleware_freertos-kernel_MK28FA15)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
- include(middleware_freertos-kernel_MKE15Z7)
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
+ include(middleware_freertos-kernel_K32L2A41A)
endif()
if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
include(middleware_freertos-kernel_K32L2B31A)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
- include(middleware_freertos-kernel_MK66F18)
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
+ include(middleware_freertos-kernel_K32L3A60_cm0plus)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
- include(middleware_freertos-kernel_MKE16Z4)
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+ include(middleware_freertos-kernel_K32L3A60_cm4)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+ include(middleware_freertos-kernel_MCIMX7U5)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
include(middleware_freertos-kernel_MIMX8QM6_cm4_core0)
@@ -38,47 +32,53 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
include(middleware_freertos-kernel_MIMX8QM6_cm4_core1)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
- include(middleware_freertos-kernel_MKV31F51212)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
- include(middleware_freertos-kernel_MK22F51212)
-endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
include(middleware_freertos-kernel_MIMX8QX6)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+ include(middleware_freertos-kernel_MIMXRT1011)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+ include(middleware_freertos-kernel_MIMXRT1015)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(middleware_freertos-kernel_MIMXRT1021)
endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+ include(middleware_freertos-kernel_MIMXRT1024)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(middleware_freertos-kernel_MIMXRT1052)
+endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(middleware_freertos-kernel_MIMXRT1062)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
- include(middleware_freertos-kernel_K32L3A60_cm0plus)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(middleware_freertos-kernel_MIMXRT1064)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
- include(middleware_freertos-kernel_K32L3A60_cm4)
+if(${MCUX_DEVICE} STREQUAL "MK22F51212")
+ include(middleware_freertos-kernel_MK22F51212)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
- include(middleware_freertos-kernel_MKM35Z7)
+if(${MCUX_DEVICE} STREQUAL "MK28FA15")
+ include(middleware_freertos-kernel_MK28FA15)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
- include(middleware_freertos-kernel_MKL27Z644)
+if(${MCUX_DEVICE} STREQUAL "MK66F18")
+ include(middleware_freertos-kernel_MK66F18)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
- include(middleware_freertos-kernel_MCIMX7U5)
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
+ include(middleware_freertos-kernel_MKE15Z7)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
- include(middleware_freertos-kernel_MIMXRT1024)
+if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
+ include(middleware_freertos-kernel_MKE16Z4)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
- include(middleware_freertos-kernel_MIMXRT1011)
+if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
+ include(middleware_freertos-kernel_MKL27Z644)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
- include(middleware_freertos-kernel_K32L2A41A)
+if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+ include(middleware_freertos-kernel_MKM35Z7)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
- include(middleware_freertos-kernel_MIMXRT1015)
+if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
+ include(middleware_freertos-kernel_MKV31F51212)
endif()
include(driver_lpuart)
diff --git a/drivers/mw320/acomp/driver_mw_acomp.cmake b/drivers/mw320/acomp/driver_mw_acomp.cmake
new file mode 100644
index 000000000..61ddd0129
--- /dev/null
+++ b/drivers/mw320/acomp/driver_mw_acomp.cmake
@@ -0,0 +1,14 @@
+#Description: MW_ACOMP Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_acomp component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_acomp.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/acomp/fsl_acomp.c b/drivers/mw320/acomp/fsl_acomp.c
new file mode 100644
index 000000000..915e48718
--- /dev/null
+++ b/drivers/mw320/acomp/fsl_acomp.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_acomp.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.wm_acomp"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#define ACOMP_INTERRUPT_TYPE_MASK (ACOMP_CTRL0_INT_ACT_HI_MASK | ACOMP_CTRL0_EDGE_LEVL_SEL_MASK)
+#define ACOMP_INTERRUPT_TYPE_SHIFT (30U)
+#define ACOMP_INTERRUPT_TYPE(x) \
+ (((uint32_t)(((uint32_t)(x)) << ACOMP_INTERRUPT_TYPE_SHIFT)) & ACOMP_INTERRUPT_TYPE_MASK)
+
+#define ACOMP_EDGE_DETECT_TRIG_SRC_MASK (ACOMP_CTRL0_RIE_MASK | ACOMP_CTRL0_FIE_MASK)
+#define ACOMP_EDGE_DETECT_TRIG_SRC_SHIFT (28U)
+#define ACOMP_EDGE_DETECT_TRIG_SRC(x) \
+ (((uint32_t)(((uint32_t)(x)) << ACOMP_EDGE_DETECT_TRIG_SRC_SHIFT)) & ACOMP_EDGE_DETECT_TRIG_SRC_MASK)
+
+#define ACOMP_GET_BIT_FIELD_VAL(val, mask, shift) (((val) & (mask)) >> (shift))
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+static uint32_t ACOMP_GetInstance(ACOMP_Type *base);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static ACOMP_Type *const s_acompBases[] = ACOMP_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to acomp clocks for each instance. */
+static const clock_ip_name_t s_acompClocks[] = ACOMP_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*!
+ * @brief Get the ACOMP peripheral instance
+ *
+ * @param base ACOMP peripheral base address.
+ * @return The instance of input ACOMP peripheral base address.
+ */
+static uint32_t ACOMP_GetInstance(ACOMP_Type *base)
+{
+ uint32_t instance;
+ uint32_t acompArrayCount = (sizeof(s_acompBases) / sizeof(s_acompBases[0]));
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < acompArrayCount; instance++)
+ {
+ if (s_acompBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < acompArrayCount);
+
+ return instance;
+}
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*!
+ * brief Initializes the module, including warm up time, response mode, inactive value and so on.
+ *
+ * param base ACOMP peripheral base address.
+ * param config The pointer to the structure acomp_config_t.
+ */
+void ACOMP_Init(ACOMP_Type *base, const acomp_config_t *config)
+{
+ assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate the ACOMP clock*/
+ (void)CLOCK_EnableClock(s_acompClocks[ACOMP_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ uint32_t tmp32;
+
+ tmp32 = ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)config->id);
+ tmp32 &= ~(ACOMP_CTRL0_GPIOINV_MASK | ACOMP_CTRL0_WARMTIME_MASK | ACOMP_CTRL0_BIAS_PROG_MASK |
+ ACOMP_CTRL0_INACT_VAL_MASK | ACOMP_CTRL0_RIE_MASK | ACOMP_CTRL0_FIE_MASK | ACOMP_CTRL0_INT_ACT_HI_MASK |
+ ACOMP_CTRL0_EDGE_LEVL_SEL_MASK);
+
+ tmp32 |= ACOMP_CTRL0_WARMTIME(config->warmupTime) | ACOMP_CTRL0_BIAS_PROG(config->responseMode) |
+ ACOMP_INTERRUPT_TYPE(config->intTrigType) | ACOMP_CTRL0_INACT_VAL(config->inactiveValue) |
+ ACOMP_EDGE_DETECT_TRIG_SRC(config->edgeDetectTrigSrc);
+ tmp32 |= ACOMP_CTRL0_GPIOINV((((uint8_t)(config->outPinMode)) & 0x2U) >> 1U);
+
+ /* Reset the acomp module. */
+ ACOMP_DoSoftwareReset(base, config->id);
+
+ ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)config->id) = tmp32;
+
+ tmp32 = ACOMP_GET_REG_VAL(&(base->ROUTE0), (uint8_t)config->id);
+ tmp32 &= ~(ACOMP_ROUTE0_OUTSEL_MASK | ACOMP_ROUTE0_PE_MASK);
+ tmp32 |= ACOMP_ROUTE0_OUTSEL((uint8_t)(config->outPinMode) & 0x1U) |
+ ACOMP_ROUTE0_PE((!((uint8_t)(config->outPinMode) >> 2U)) & 0x1U);
+ ACOMP_GET_REG_VAL(&(base->ROUTE0), (uint8_t)config->id) = tmp32;
+
+ ACOMP_SetInputConfig(base, config->id, config->posInput, config->negInput);
+
+ ACOMP_Enable(base, config->id, config->enable);
+}
+
+/*!
+ * brief Gets the default configuration of ACOMP module.
+ *
+ * code
+ * config->id = kACOMP_Acomp0;
+ * config->enable = false;
+ * config->warmupTime = kACOMP_WarmUpTime1us;
+ * config->responseMode = kACOMP_SlowResponseMode;
+ * config->inactiveValue = kACOMP_ResultLogicLow;
+ * config->intTrigType = kACOMP_HighLevelTrig;
+ * config->edgeDetectTrigSrc = kACOMP_EdgePulseDis;
+ * config->outPinMode = kACOMP_PinOutDisable;
+ * config->posInput = NULL;
+ * config->negInput = NULL;
+ * endcode
+ * param config The pointer to the structure acomp_config_t.
+ */
+void ACOMP_GetDefaultConfig(acomp_config_t *config)
+{
+ assert(config != NULL);
+
+ (void)memset(config, 0U, sizeof(acomp_config_t));
+
+ config->id = kACOMP_Acomp0;
+ config->enable = false;
+ config->warmupTime = kACOMP_WarmUpTime1us;
+ config->responseMode = kACOMP_SlowResponseMode;
+ config->inactiveValue = kACOMP_ResultLogicLow;
+ config->intTrigType = kACOMP_HighLevelTrig;
+ config->edgeDetectTrigSrc = kACOMP_EdgePulseDis;
+ config->outPinMode = kACOMP_PinOutDisable;
+ config->posInput = NULL;
+ config->negInput = NULL;
+}
+
+/*!
+ * @brief De-initializes the module.
+ *
+ * @param base ACOMP peripheral base address.
+ */
+void ACOMP_Deinit(ACOMP_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate the ACOMP clock*/
+ (void)CLOCK_DisableClock(s_acompClocks[ACOMP_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ ACOMP_Enable(base, kACOMP_Acomp0, false);
+ ACOMP_Enable(base, kACOMP_Acomp1, false);
+}
+
+/*!
+ * brief Configures selected comparator's inputs, inclduing input channel and hysteresis level.
+ *
+ * param base ACOMP peripheral base address.
+ * param id The selected acomp comparator's id, please refer to acomp_comparator_id_t.
+ * param posInput The configuration of selected comparator's positive input,
+ * please refer to acomp_positive_input_config_t.
+ * param negInput The configuration of selected comparator's negative input,
+ * please refer to acomp_negative_input_config_t.
+ */
+void ACOMP_SetInputConfig(ACOMP_Type *base,
+ acomp_comparator_id_t id,
+ const acomp_positive_input_config_t *posInput,
+ const acomp_negative_input_config_t *negInput)
+{
+ assert(posInput != NULL);
+ assert(negInput != NULL);
+
+ uint32_t tmp32 = 0UL;
+
+ tmp32 = ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id);
+ tmp32 &= ~(ACOMP_CTRL0_HYST_SELN_MASK | ACOMP_CTRL0_HYST_SELP_MASK | ACOMP_CTRL0_NEG_SEL_MASK |
+ ACOMP_CTRL0_POS_SEL_MASK | ACOMP_CTRL0_LEVEL_SEL_MASK);
+ tmp32 |= ACOMP_CTRL0_HYST_SELN(negInput->hysterLevel) | ACOMP_CTRL0_HYST_SELP(posInput->hysterLevel) |
+ ACOMP_CTRL0_NEG_SEL(negInput->channel) | ACOMP_CTRL0_POS_SEL(posInput->channel);
+ if (negInput->channel >= kACOMP_NegChVIO_0P25)
+ {
+ tmp32 |= ACOMP_CTRL0_LEVEL_SEL((negInput->channel & 0x3U) << 4U);
+ }
+ ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) = tmp32;
+}
+
+/*!
+ * brief Gets status flags, such as ACOMP0 active status flags, ACOMP1 active status flags, and so on.
+ *
+ * param base ACOMP peripheral base address.
+ * return The OR'ed value ACOMP status flags, please refer to _acomp_status_flags for details.
+ */
+uint32_t ACOMP_GetStatusFlags(ACOMP_Type *base)
+{
+ uint32_t tmp32 = 0UL;
+
+ tmp32 |= ACOMP_GET_BIT_FIELD_VAL(base->STATUS0, ACOMP_STATUS0_ACT_MASK, ACOMP_STATUS0_ACT_SHIFT) << 0UL;
+ tmp32 |= ACOMP_GET_BIT_FIELD_VAL(base->ISR0, ACOMP_ISR0_OUT_INT_MASK | ACOMP_ISR0_OUTA_INT_MASK,
+ ACOMP_ISR0_OUT_INT_SHIFT)
+ << 1UL;
+ tmp32 |= ACOMP_GET_BIT_FIELD_VAL(base->IRSR0, ACOMP_IRSR0_OUT_INT_RAW_MASK | ACOMP_IRSR0_OUTA_INT_RAW_MASK,
+ ACOMP_IRSR0_OUT_INT_RAW_SHIFT)
+ << 3UL;
+
+ tmp32 |= ACOMP_GET_BIT_FIELD_VAL(base->STATUS1, ACOMP_STATUS1_ACT_MASK, ACOMP_STATUS1_ACT_SHIFT) << 5UL;
+ tmp32 |= ACOMP_GET_BIT_FIELD_VAL(base->ISR1, ACOMP_ISR1_OUT_INT_MASK | ACOMP_ISR1_OUTA_INT_MASK,
+ ACOMP_ISR1_OUT_INT_SHIFT)
+ << 6UL;
+ tmp32 |= ACOMP_GET_BIT_FIELD_VAL(base->IRSR1, ACOMP_IRSR1_OUT_INT_RAW_MASK | ACOMP_IRSR1_OUTA_INT_RAW_MASK,
+ ACOMP_IRSR1_OUT_INT_RAW_SHIFT)
+ << 8UL;
+
+ return tmp32;
+}
diff --git a/drivers/mw320/acomp/fsl_acomp.h b/drivers/mw320/acomp/fsl_acomp.h
new file mode 100644
index 000000000..bdc7d6979
--- /dev/null
+++ b/drivers/mw320/acomp/fsl_acomp.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_ACOMP_H_
+#define _FSL_ACOMP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup acomp
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief ACOMP driver version */
+#define FSL_ACOMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+
+/*!
+ * @brief The macro to get the address based on start address and acomp id.
+ */
+#define ACOMP_REG_ADDR(startAddr, id) ((uint32_t *)((volatile uint32_t *)(startAddr) + (uint32_t)(id)))
+/*!
+ * @brief The macro to get register value based on start address and acomp id.
+ */
+#define ACOMP_GET_REG_VAL(startAddr, id) (*ACOMP_REG_ADDR((startAddr), (id)))
+/*!
+ * @brief Sets register's bit field.
+ */
+#define ACOMP_SET_REG_BIT(startAddr, id, val) (ACOMP_GET_REG_VAL((startAddr), (id)) |= (val))
+/*!
+ * @brief Clears register's bit field.
+ */
+#define ACOMP_CLEAR_REG_BIT(startAddr, id, val) (ACOMP_GET_REG_VAL((startAddr), (id)) &= ~(val))
+
+/*!
+ * @brief The enumeration of interrupts, including ACOMP0 synchrnized output interrupt,
+ * ACOMP0 asynchrnized output interrupt, ACOMP1 synchrnized output interrupt, and
+ * ACOMP1 asynchrnized output interrupt.
+ */
+enum _acomp_interrupt_enable
+{
+ kACOMP_Out0InterruptEnable = ACOMP_IMR0_OUT_INT_MASK_MASK, /*!< ACOMP0 synchrnized output interrupt enable. */
+ kACOMP_OutA0InterruptEnable = ACOMP_IMR0_OUTA_INT_MASK_MASK, /*!< ACOMP0 asynchrnized output interrupt enable. */
+ kACOMP_Out1InterruptEnable = ACOMP_IMR1_OUT_INT_MASK_MASK << 2U, /*!< ACOMP1 synchrnized output interrupt enable. */
+ kACOMP_OutA1InterruptEnable = ACOMP_IMR1_OUTA_INT_MASK_MASK << 2U, /*!< ACOMP1 asynchrnized
+ output interrupt enable. */
+};
+
+/*!
+ * @brief The enumeration of status flags, including ACOMP0 active staus flag, ACOMP1 active status flag, and so on.
+ */
+enum _acomp_status_flags
+{
+ kACOMP_Acomp0ActiveFlag = 1UL << 0UL, /*!< ACOMP0 active status flag, if this flag is set it means
+ the ACOMP0 is active. */
+ kACOMP_Acomp0OutInterruptFlag = 1UL << 1UL, /*!< ACOMP0 Synchronized output interrupt flags, this flag is set
+ when ACOMP0 synchronized output changes from 0 to 1 and the
+ corresponding interrupt is enabled. */
+ kACOMP_Acomp0OutAInterruptFlag = 1UL << 2UL, /*!< ACOMP0 Asynchronized output interrupt flags, this flag is set
+ when ACOMP0 asynchronized output changes from 0 to 1 and the
+ corresponding interrupt is enabled. */
+ kACOMP_Acomp0RawOutInterruptFlag = 1UL << 3UL, /*!< ACOMP0 raw synchroized output interrrupt flags. */
+ kACOMP_Acomp0RawOutAInterruptFlag = 1UL << 4UL, /*!< ACOMP0 raw asynchroized output interrupt flags. */
+
+ kACOMP_Acomp1ActiveFlag = 1UL << 5UL, /*!< ACOMP1 active status flag, if this flag is set it means
+ the ACOMP0 is active. */
+ kACOMP_Acomp1OutInterruptFlag = 1UL << 6UL, /*!< ACOMP1 Synchronized output interrupt flags, this flag is set
+ when ACOMP1 synchronized output changes from 0 to 1 and the
+ corresponding interrupt is enabled. */
+ kACOMP_Acomp1OutAInterruptFlag = 1UL << 7UL, /*!< ACOMP1 Asynchronized output interrupt flags, this flag is set
+ when ACOMP1 asynchronized output changes from 0 to 1 and the
+ corresponding interrupt is enabled. */
+ kACOMP_Acomp1RawOutInterruptFlag = 1UL << 8UL, /*!< ACOMP1 raw synchroized output interrrupt flags. */
+ kACOMP_Acomp1RawOutAInterruptFlag = 1UL << 9U, /*!< ACOMP1 raw asynchroized output interrupt flags. */
+};
+
+/*!
+ * @brief ACOMP result logical status Type definition
+ */
+typedef enum _acomp_result_logic_status
+{
+ kACOMP_ResultLogicLow = 0U, /*!< The comparsion result is high logic. */
+ kACOMP_ResultLogicHigh = 1U, /*!< The comparsion result is low logic. */
+} acomp_result_logic_status_t;
+
+/*!
+ * @brief ACOMP comparator id.
+ */
+typedef enum _acomp_comparator_id
+{
+ kACOMP_Acomp0, /*!< Index for ACOMP0 */
+ kACOMP_Acomp1 /*!< Index for ACOMP1 */
+} acomp_comparator_id_t;
+
+/*!
+ * @brief The enumeration of wave up time.
+ */
+typedef enum _acomp_warm_up_time
+{
+ kACOMP_WarmUpTime1us = 0U, /*!< Set wave-up time as 1us. */
+ kACOMP_WarmUpTime2us, /*!< Set wave-up time as 2us. */
+ kACOMP_WarmUpTime4us, /*!< Set wave-up time as 4us. */
+ kACOMP_WarmUpTime8us, /*!< Set wave-up time as 8us. */
+} acomp_warm_up_time_t;
+
+/*!
+ * @brief The enumeration of response mode. The response mode will affect the delay from input to output.
+ */
+typedef enum _acomp_response_mode
+{
+ kACOMP_SlowResponseMode = 0U, /*!< Slow response mode also called power mode 1. */
+ kACOMP_MediumResponseMode, /*!< Medium response mode also called power mode 2. */
+ kACOMP_FastResponseMode, /*!< Fast response mode also called power mode 3. */
+} acomp_response_mode_t;
+
+/*!
+ * @brief ACOMP interrupt trigger type definition
+ */
+typedef enum _acomp_interrupt_trigger_type
+{
+ kACOMP_LowLevelTrig = 0U, /*!< Low level trigger interrupt. */
+ kACOMP_HighLevelTrig = 1U, /*!< High level trigger interrupt. */
+ kACOMP_FallingEdgeTrig = 2U, /*!< Falling edge trigger interrupt. */
+ kACOMP_RisingEdgeTrig = 3U, /*!< Rising edge trigger interrupt. */
+} acomp_interrupt_trigger_type_t;
+
+/*!
+ * @brief ACOMP edge pule trigger source type definition
+ */
+typedef enum _acomp_edge_pulse_trig_source
+{
+ kACOMP_EdgePulseDis = 0U, /*!< edge pulse function is disable */
+ kACOMP_EdgePulseRising, /*!< Rising edge can trigger edge pulse */
+ kACOMP_EdgePulseFalling, /*!< Falling edge can trigger edge pulse */
+ kACOMP_EdgePulseBothEdge, /*!< Both edge can trigger edge pulse */
+} acomp_edge_pulse_trig_source_t;
+
+/*!
+ * @brief ACOMP synchronous/asynchronous output type to pin
+ */
+typedef enum _acomp_pin_out_type
+{
+ kACOMP_PinOutSyn = 0U, /*!< Enable ACOMP synchronous pin output */
+ kACOMP_PinOutAsyn = 1U, /*!< Enable ACOMP asynchronous pin output */
+ kACOMP_PinOutSynInverted = 2U, /*!< Enable ACOMP inverted synchronous pin output */
+ kACOMP_PinOutAsynInverted = 3U, /*!< Enable ACOMP inverted asynchronous pin output */
+ kACOMP_PinOutDisable = 4U, /*!< Diable ACOMP pin output */
+} acomp_pin_out_type_t;
+
+/*!
+ * @brief ACOMP positive channel enumeration
+ */
+typedef enum _acomp_positive_channel
+{
+ kACOMP_PosChGPIO42, /*!< Gpio42 selection */
+ kACOMP_PosChGPIO43, /*!< Gpio43 selection */
+ kACOMP_PosChGPIO44, /*!< Gpio44 selection */
+ kACOMP_PosChGPIO45, /*!< Gpio45 selection */
+ kACOMP_PosChGPIO46, /*!< Gpio46 selection */
+ kACOMP_PosChGPIO47, /*!< Gpio47 selection */
+ kACOMP_PosChGPIO48, /*!< Gpio48 selection */
+ kACOMP_PosChGPIO49, /*!< Gpio49 selection */
+ kACOMP_PosChDACA, /*!< DACA selection */
+ kACOMP_PosChDACB, /*!< DACB selection */
+} acomp_positive_channel_t;
+
+/*!
+ * @brief ACOMP negative channel enumeration.
+ */
+typedef enum _acomp_negative_channel
+{
+ kACOMP_NegChGPIO42, /*!< Gpio42 selection */
+ kACOMP_NegChGPIO43, /*!< Gpio43 selection */
+ kACOMP_NegChGPIO44, /*!< Gpio44 selection */
+ kACOMP_NegChGPIO45, /*!< Gpio45 selection */
+ kACOMP_NegChGPIO46, /*!< Gpio46 selection */
+ kACOMP_NegChGPIO47, /*!< Gpio47 selection */
+ kACOMP_NegChGPIO48, /*!< Gpio48 selection */
+ kACOMP_NegChGPIO49, /*!< Gpio49 selection */
+ kACOMP_NegChDACA, /*!< DACA selection */
+ kACOMP_NegChDACB, /*!< DACB selection */
+ kACOMP_NegChVREF1P2, /*!< Vref1p2 selection */
+ kACOMP_NegChAVSS, /*!< AVSS selection */
+ kACOMP_NegChVIO_0P25, /*!< VIO Scaling factor 0.25 */
+ kACOMP_NegChVIO_0P50, /*!< VIO Scaling factor 0.50 */
+ kACOMP_NegChVIO_0P75, /*!< VIO Scaling factor 0.75 */
+ kACOMP_NegChVIO_1P00 /*!< VIO Scaling factor 1.00 */
+} acomp_negative_channel_t;
+
+/*!
+ * @brief ACOMP hysteresis level enumeration
+ */
+typedef enum _acomp_input_hysteresis
+{
+ kACOMP_Hyster0MV, /*!< Hysteresis level = 0mv */
+ kACOMP_Hyster10MV, /*!< Hysteresis level = 10mv */
+ kACOMP_Hyster20MV, /*!< Hysteresis level = 20mv */
+ kACOMP_Hyster30MV, /*!< Hysteresis level = 30mv */
+ kACOMP_Hyster40MV, /*!< Hysteresis level = 40mv */
+ kACOMP_Hyster50MV, /*!< Hysteresis level = 50mv */
+ kACOMP_Hyster60MV, /*!< Hysteresis level = 60mv */
+ kACOMP_Hyster70MV, /*!< Hysteresis level = 70mv */
+} acomp_input_hysteresis_t;
+
+/*!
+ * @brief The configuration of positive input, including channel selection and hysteresis level.
+ */
+typedef struct _acomp_positive_input_config
+{
+ acomp_positive_channel_t channel : 4U; /*!< Positive input channel selection,
+ please refer to @ref acomp_positive_channel_t. */
+ acomp_input_hysteresis_t hysterLevel : 4U; /*!< Positive hysteresis voltage level selection,
+ please refer to @ref acomp_input_hysteresis_t. */
+} acomp_positive_input_config_t;
+
+/*!
+ * @brief The configuration of negative input, including channel selection and hysteresis level.
+ */
+typedef struct _acomp_negative_input_config
+{
+ acomp_negative_channel_t channel : 4U; /*!< Negative input channel selection,
+ please refer to @ref acomp_negative_channel_t. */
+ acomp_input_hysteresis_t hysterLevel : 4U; /*!< Negative hystersis voltage level selection,
+ please refer to @ref acomp_input_hysteresis_t. */
+} acomp_negative_input_config_t;
+
+/*!
+ * @brief The configure structure of acomp, including warm up time, response mode and so on.
+ */
+typedef struct _acomp_config
+{
+ acomp_comparator_id_t id : 1U; /*!< The id of comparator, please refer to @ref acomp_comparator_id_t. */
+ bool enable : 1U; /*!< Enable/Disable the selected ACOMP.
+ - \b true Enable the selected ACOMP.
+ - \b false Disable the selected ACOMP. */
+ acomp_warm_up_time_t warmupTime : 2U; /*!< Configure warm-up time, please refer to @ref acomp_warm_up_time_t. */
+ acomp_response_mode_t responseMode : 2U; /*!< Configure responde mode(power mode),
+ please refer to @ref acomp_response_mode_t for details. */
+ acomp_interrupt_trigger_type_t intTrigType : 2U; /*!< Select interrupt trigger type,
+ please refer to @ref acomp_interrupt_trigger_type_t. */
+ acomp_result_logic_status_t inactiveValue : 1U; /*!< Configure output value for inactive state. */
+ acomp_edge_pulse_trig_source_t edgeDetectTrigSrc : 2U; /*!< Config edge detect trigger source,
+ please refer to @ref acomp_edge_pulse_trig_source_t. */
+ acomp_pin_out_type_t outPinMode : 3U; /*!< Config the output pin mode,
+ please refer to @ref acomp_pin_out_type_t for details. */
+ const acomp_positive_input_config_t *posInput; /*!< The pointer to the configuration structure of positive input,
+ please refer to @ref acomp_positive_input_config_t. */
+ const acomp_negative_input_config_t *negInput; /*!< The pointer to the configuration structure of negative input,
+ please refer to @ref acomp_positive_input_config_t. */
+} acomp_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name ACOMP Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Initializes the module, including warm up time, response mode, inactive value and so on.
+ *
+ * @param base ACOMP peripheral base address.
+ * @param config The pointer to the structure @ref acomp_config_t.
+ */
+void ACOMP_Init(ACOMP_Type *base, const acomp_config_t *config);
+
+/*!
+ * @brief Gets the default configuration of ACOMP module.
+ *
+ * @code
+ * config->id = kACOMP_Acomp0;
+ * config->enable = false;
+ * config->warmupTime = kACOMP_WarmUpTime1us;
+ * config->responseMode = kACOMP_SlowResponseMode;
+ * config->inactiveValue = kACOMP_ResultLogicLow;
+ * config->intTrigType = kACOMP_HighLevelTrig;
+ * config->edgeDetectTrigSrc = kACOMP_EdgePulseDis;
+ * config->outPinMode = kACOMP_PinOutDisable;
+ * config->posInput = NULL;
+ * config->negInput = NULL;
+ * @endcode
+ * @param config The pointer to the structure @ref acomp_config_t.
+ */
+void ACOMP_GetDefaultConfig(acomp_config_t *config);
+
+/*!
+ * @brief De-initializes the module.
+ *
+ * @param base ACOMP peripheral base address.
+ */
+void ACOMP_Deinit(ACOMP_Type *base);
+
+/*!
+ * @brief Configures selected comparator's inputs, inclduing input channel and hysteresis level.
+ *
+ * @param base ACOMP peripheral base address.
+ * @param id The selected acomp comparator's id, please refer to @ref acomp_comparator_id_t.
+ * @param posInput The configuration of selected comparator's positive input,
+ * please refer to @ref acomp_positive_input_config_t.
+ * @param negInput The configuration of selected comparator's negative input,
+ * please refer to @ref acomp_negative_input_config_t.
+ */
+void ACOMP_SetInputConfig(ACOMP_Type *base,
+ acomp_comparator_id_t id,
+ const acomp_positive_input_config_t *posInput,
+ const acomp_negative_input_config_t *negInput);
+
+/*!
+ * @brief Does software reset to the selected ACOMP module.
+ *
+ * @param base ACOMP peripheral base address.
+ * @param id The selected acomp comparator's id, please refer to @ref acomp_comparator_id_t.
+ */
+static inline void ACOMP_DoSoftwareReset(ACOMP_Type *base, acomp_comparator_id_t id)
+{
+ ACOMP_SET_REG_BIT(&(base->RST0), id, ACOMP_RST0_SOFT_RST_MASK);
+ /* Delay */
+ for (uint8_t i = 0U; i < 10U; i++)
+ {
+ __NOP();
+ }
+ ACOMP_CLEAR_REG_BIT(&(base->RST0), id, ACOMP_RST0_SOFT_RST_MASK);
+}
+
+/*!
+ * @brief Enables/Disables ACOMP module.
+ *
+ * @param base ACOMP peripheral base address.
+ * @param id The selected acomp comparator's id, please refer to @ref acomp_comparator_id_t.
+ * @param enable Used to enable/disable module.
+ * - \b true Enable comparator instance.
+ * - \b false Disable comparator instance.
+ */
+static inline void ACOMP_Enable(ACOMP_Type *base, acomp_comparator_id_t id, bool enable)
+{
+ if (enable)
+ {
+ ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) |= ACOMP_CTRL1_MUXEN_MASK;
+ ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) |= ACOMP_CTRL1_EN_MASK;
+ }
+ else
+ {
+ ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) &= ~ACOMP_CTRL1_MUXEN_MASK;
+ ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) &= ~ACOMP_CTRL1_EN_MASK;
+ }
+}
+
+/*!
+ * @brief Resets clock divider.
+ *
+ * @param base ACOMP peripheral base address.
+ */
+static inline void ACOMP_ResetClockDivider(ACOMP_Type *base)
+{
+ base->CLK |= ACOMP_CLK_SOFT_CLK_RST_MASK;
+ for (uint8_t i = 0U; i < 10U; i++)
+ {
+ __NOP();
+ }
+ base->CLK &= ~ACOMP_CLK_SOFT_CLK_RST_MASK;
+}
+
+/*! @} */
+
+/*!
+ * @name ACOMP Result Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the selected acomp conversion result.
+ *
+ * @param base ACOMP peripheral base address.
+ * @param id The selected acomp comparator's id, please refer to @ref acomp_comparator_id_t.
+ * @return The result of the selected acomp instance.
+ */
+static inline acomp_result_logic_status_t ACOMP_GetResult(ACOMP_Type *base, acomp_comparator_id_t id)
+{
+ return (acomp_result_logic_status_t)((ACOMP_GET_REG_VAL(&(base->STATUS0), id) & ACOMP_STATUS0_OUT_MASK) >>
+ ACOMP_STATUS0_OUT_SHIFT);
+}
+
+/*! @} */
+
+/*!
+ * @brief ACOMP Interrupt Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enables interrupts, including acomp0 asynchronized interrupt, acomp0 synchronized interrupt, acomp1
+ * asynchronized interrupt, and acomp1 synchronized interrupt.
+ *
+ * @param base ACOMP peripheral base address.
+ * @param interruptMask The OR'ed value of the interrupts to be enabled, please refer to @ref _acomp_interrupt_enable.
+ */
+static inline void ACOMP_EnableInterrupts(ACOMP_Type *base, uint32_t interruptMask)
+{
+ base->IMR0 &= ~(interruptMask & 0x3UL);
+ base->IMR1 &= ~((interruptMask >> 2UL) & 0x3UL);
+}
+
+/*!
+ * @brief Disables interrupts, including acomp0 asynchronized interrupt, acomp0 synchronized interrupt, acomp1
+ * asynchronized interrupt, and acomp1 synchronized interrupt.
+ *
+ * @param base ACOMP peripheral base address.
+ * @param interruptMask The OR'ed value of the interrupts to be disabled, please refer to @ref _acomp_interrupt_enable.
+ */
+static inline void ACOMP_DisableInterrupt(ACOMP_Type *base, uint32_t interruptMask)
+{
+ base->IMR0 |= (interruptMask & 0x3UL);
+ base->IMR1 |= ((interruptMask >> 2UL) & 0x3UL);
+}
+
+/*! @} */
+
+/*!
+ * @brief ACOMP Status Flag Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Gets status flags, such as ACOMP0 active status flags, ACOMP1 active status flags, and so on.
+ *
+ * @param base ACOMP peripheral base address.
+ * @return The OR'ed value ACOMP status flags, please refer to @ref _acomp_status_flags for details.
+ */
+uint32_t ACOMP_GetStatusFlags(ACOMP_Type *base);
+
+/*!
+ * @brief Clears status flags that can be cleared by software.
+ *
+ * @note Only @ref kACOMP_Acomp0OutInterruptFlag, @ref kACOMP_Acomp0OutAInterruptFlag, @ref
+ * kACOMP_Acomp1OutInterruptFlag, and @ref kACOMP_Acomp1OutAInterruptFlag can be cleared by software.
+ *
+ * @param base ACOMP peripheral base address.
+ * @param statusFlagMask The OR'ed value of the status flags that can be cleared.
+ */
+static inline void ACOMP_ClearStatusFlags(ACOMP_Type *base, uint32_t statusFlagMask)
+{
+ assert((statusFlagMask & (kACOMP_Acomp0ActiveFlag | kACOMP_Acomp1ActiveFlag | kACOMP_Acomp0RawOutInterruptFlag |
+ kACOMP_Acomp1RawOutInterruptFlag | kACOMP_Acomp0RawOutAInterruptFlag |
+ kACOMP_Acomp1RawOutAInterruptFlag)) == 0UL);
+
+ base->ICR0 = (statusFlagMask & (kACOMP_Acomp0OutInterruptFlag | kACOMP_Acomp0OutAInterruptFlag)) >> 1UL;
+ base->ICR1 = (statusFlagMask & (kACOMP_Acomp1OutInterruptFlag | kACOMP_Acomp1OutAInterruptFlag)) >> 6UL;
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_ACOMP_H_ */
diff --git a/drivers/mw320/adc/driver_mw_adc.cmake b/drivers/mw320/adc/driver_mw_adc.cmake
new file mode 100644
index 000000000..0a385b24f
--- /dev/null
+++ b/drivers/mw320/adc/driver_mw_adc.cmake
@@ -0,0 +1,14 @@
+#Description: MW_ADC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_adc component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_adc.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/adc/fsl_adc.c b/drivers/mw320/adc/fsl_adc.c
new file mode 100644
index 000000000..2387f886a
--- /dev/null
+++ b/drivers/mw320/adc/fsl_adc.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_adc.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.wm_adc"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+static uint32_t ADC_GetInstance(ADC_Type *base);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to adc clocks for each instance. */
+static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*!
+ * @brief Get the ADC peripheral instance
+ *
+ * @param base ADC peripheral base address.
+ * @return The instance of input ADC peripheral base address.
+ */
+static uint32_t ADC_GetInstance(ADC_Type *base)
+{
+ uint32_t instance;
+ uint32_t adcArrayCount = (sizeof(s_adcBases) / sizeof(s_adcBases[0]));
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < adcArrayCount; instance++)
+ {
+ if (s_adcBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < adcArrayCount);
+
+ return instance;
+}
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*!
+ * brief Initialize ADC module, including clock divider, power mode, and so on.
+ *
+ * param base ADC peripheral base address.
+ * param config The pointer to the structure adc_config_t.
+ */
+void ADC_Init(ADC_Type *base, const adc_config_t *config)
+{
+ assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate the ADC clock*/
+ (void)CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+ uint32_t tmp32;
+
+ ADC_DoSoftwareReset(base);
+
+ base->ADC_REG_GENERAL = (base->ADC_REG_GENERAL & ~(ADC_ADC_REG_GENERAL_CLK_DIV_RATIO_MASK)) |
+ ADC_ADC_REG_GENERAL_CLK_DIV_RATIO(config->clockDivider);
+
+ tmp32 = base->ADC_REG_CONFIG;
+ tmp32 &=
+ ~(ADC_ADC_REG_CONFIG_TRIGGER_SEL_MASK | ADC_ADC_REG_CONFIG_TRIGGER_EN_MASK |
+ ADC_ADC_REG_CONFIG_CONT_CONV_EN_MASK | ADC_ADC_REG_CONFIG_AVG_SEL_MASK | ADC_ADC_REG_CONFIG_SCAN_LENGTH_MASK);
+ tmp32 |= ADC_ADC_REG_CONFIG_CONT_CONV_EN(config->conversionMode) |
+ ADC_ADC_REG_CONFIG_AVG_SEL(config->averageLength) | ADC_ADC_REG_CONFIG_SCAN_LENGTH(config->scanLength);
+ if (config->triggerSource != kADC_TriggerSourceSoftware)
+ {
+ tmp32 |= ADC_ADC_REG_CONFIG_TRIGGER_EN_MASK | ADC_ADC_REG_CONFIG_TRIGGER_SEL(config->triggerSource);
+ }
+ base->ADC_REG_CONFIG = tmp32;
+
+ tmp32 = base->ADC_REG_INTERVAL;
+ if (config->warmupTime == kADC_WarmUpStateBypass)
+ {
+ tmp32 |= ADC_ADC_REG_INTERVAL_BYPASS_WARMUP_MASK;
+ }
+ else
+ {
+ tmp32 =
+ (tmp32 & ~(ADC_ADC_REG_INTERVAL_WARMUP_TIME_MASK)) | ADC_ADC_REG_INTERVAL_WARMUP_TIME(config->warmupTime);
+ }
+ base->ADC_REG_INTERVAL = tmp32;
+
+ tmp32 = base->ADC_REG_ANA;
+ tmp32 &= ~(ADC_ADC_REG_ANA_VREF_SEL_MASK | ADC_ADC_REG_ANA_SINGLEDIFF_MASK | ADC_ADC_REG_ANA_INBUF_GAIN_MASK |
+ ADC_ADC_REG_ANA_INBUF_EN_MASK | ADC_ADC_REG_ANA_BIAS_SEL_MASK | ADC_ADC_REG_ANA_RES_SEL_MASK);
+ tmp32 |= ADC_ADC_REG_ANA_VREF_SEL(config->vrefSource) | ADC_ADC_REG_ANA_SINGLEDIFF(config->inputMode) |
+ ADC_ADC_REG_ANA_INBUF_GAIN(config->inputGain) | ADC_ADC_REG_ANA_INBUF_EN(config->enableInputGainBuffer) |
+ ADC_ADC_REG_ANA_BIAS_SEL(config->powerMode) | ADC_ADC_REG_ANA_RES_SEL(config->resolution);
+ base->ADC_REG_ANA = tmp32;
+
+ base->ADC_REG_RESULT_BUF = (base->ADC_REG_RESULT_BUF & ~(ADC_ADC_REG_RESULT_BUF_WIDTH_SEL_MASK)) |
+ ADC_ADC_REG_RESULT_BUF_WIDTH_SEL(config->resultWidth);
+
+ tmp32 = base->ADC_REG_DMAR;
+ tmp32 &= ~(ADC_ADC_REG_DMAR_DMA_EN_MASK | ADC_ADC_REG_DMAR_FIFO_THL_MASK);
+ tmp32 |= ADC_ADC_REG_DMAR_FIFO_THL(config->fifoThreshold) | ADC_ADC_REG_DMAR_DMA_EN(config->enableDMA);
+ base->ADC_REG_DMAR = tmp32;
+
+ if (config->enableADC)
+ {
+ base->ADC_REG_GENERAL |= ADC_ADC_REG_GENERAL_GLOBAL_EN_MASK;
+ }
+}
+
+/*!
+ * brief Get default configuration.
+ *
+ * code
+ * config->clockDivider = kADC_ClockDivider1;
+ * config->powerMode = kADC_PowerModeFullBiasingCurrent;
+ * config->resolution = kADC_Resolution12Bit;
+ * config->warmupTime = kADC_WarmUpTime16us;
+ * config->vrefSource = kADC_Vref1P2V;
+ * config->inputMode = kADC_InputSingleEnded;
+ * config->conversionMode = kADC_ConversionContinuous;
+ * config->scanLength = kADC_ScanLength_1;
+ * config->averageLength = kADC_AverageNone;
+ * config->triggerSource = kADC_TriggerSourceSoftware;
+ * config->inputGain = kADC_InputGain1;
+ * config->enableInputGainBuffer = false;
+ * config->resultWidth = kADC_ResultWidth16;
+ * config->fifoThreshold = kADC_FifoThresholdData1;
+ * config->enableDMA = false;
+ * config->enableADC = false;
+ * endcode
+ * param config Pointer to the structure adc_config_t.
+ */
+void ADC_GetDefaultConfig(adc_config_t *config)
+{
+ assert(config != NULL);
+
+ (void)memset(config, 0U, sizeof(adc_config_t));
+
+ config->clockDivider = kADC_ClockDivider1;
+ config->powerMode = kADC_PowerModeFullBiasingCurrent;
+ config->resolution = kADC_Resolution12Bit;
+ config->warmupTime = kADC_WarmUpTime16us;
+
+ config->vrefSource = kADC_Vref1P2V;
+ config->inputMode = kADC_InputSingleEnded;
+ config->conversionMode = kADC_ConversionContinuous;
+ config->scanLength = kADC_ScanLength_1;
+ config->averageLength = kADC_AverageNone;
+ config->triggerSource = kADC_TriggerSourceSoftware;
+ config->inputGain = kADC_InputGain1;
+ config->enableInputGainBuffer = false;
+
+ config->resultWidth = kADC_ResultWidth16;
+ config->fifoThreshold = kADC_FifoThresholdData1;
+ config->enableDMA = false;
+ config->enableADC = false;
+}
+
+/*!
+ * brief De-initialize the ADC module.
+ *
+ * param base ADC peripheral base address.
+ */
+void ADC_Deinit(ADC_Type *base)
+{
+ ADC_DoSoftwareReset(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate the ADC clock*/
+ (void)CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Set scan channel mux source.
+ *
+ * param base ADC peripheral base address.
+ * param scanChannel The selected channel, please refer to adc_scan_channel_t for details.
+ * param channelSource The mux source to be set to the selected channel,
+ * please refer to adc_channel_source_t for details.
+ */
+void ADC_SetScanChannel(ADC_Type *base, adc_scan_channel_t scanChannel, adc_channel_source_t channelSource)
+{
+ if (scanChannel < kADC_ScanChannel8)
+ {
+ base->ADC_REG_SCN1 = (base->ADC_REG_SCN1 & ~(0xFUL << (uint32_t)scanChannel)) |
+ ((uint32_t)channelSource << (uint32_t)scanChannel);
+ }
+ else
+ {
+ base->ADC_REG_SCN2 = (base->ADC_REG_SCN2 & ~(0xFUL << ((uint32_t)scanChannel - 8UL))) |
+ ((uint32_t)channelSource << ((uint32_t)scanChannel - 8UL));
+ }
+}
+
+/*!
+ * brief Do automatic calibration measurement.
+ *
+ * note After auto calibrate successful, user can invoke ADC_GetAutoCalibrationData() to get self offset calibration
+ * value and self gain calibration value.
+ *
+ * param base ADC peripheral base address.
+ * param calVref The inpul reference channel for gain calibration,
+ * please refer to adc_calibration_ref_t for details.
+ * retval kStatus_Success Auto calibrate successfully.
+ * retval kStatus_Fail Auto calibrate failure.
+ */
+status_t ADC_DoAutoCalibration(ADC_Type *base, adc_calibration_ref_t calVref)
+{
+ uint32_t tmp32;
+
+ tmp32 = base->ADC_REG_CONFIG;
+ tmp32 &= ~(ADC_ADC_REG_CONFIG_CAL_VREF_SEL_MASK);
+ tmp32 |= ADC_ADC_REG_CONFIG_CAL_VREF_SEL(calVref);
+ base->ADC_REG_CONFIG = tmp32;
+
+ base->ADC_REG_CMD &= ~ADC_ADC_REG_CMD_CONV_START_MASK;
+ base->ADC_REG_GENERAL |= ADC_ADC_REG_GENERAL_ADC_CAL_EN_MASK;
+ base->ADC_REG_CMD |= ADC_ADC_REG_CMD_CONV_START_MASK;
+
+ /* Wait for self calibration done */
+ for (volatile uint32_t i = 0UL; i < 1000000UL; i++)
+ {
+ if ((base->ADC_REG_GENERAL & ADC_ADC_REG_GENERAL_ADC_CAL_EN_MASK) == 0UL)
+ {
+ base->ADC_REG_CONFIG &= ~ADC_ADC_REG_CONFIG_CAL_DATA_SEL_MASK;
+ base->ADC_REG_CMD &= ~ADC_ADC_REG_CMD_CONV_START_MASK;
+ return kStatus_Success;
+ }
+ }
+
+ return kStatus_Fail;
+}
+
+/*!
+ * brief Configure audio voice level.
+ *
+ * param base ADC peripheral base address.
+ * param enableDetect Used to enable/disable voice level detection.
+ * - \b true Enable voice level detection.
+ * - \b false Disable voice level detection.
+ * param voiceLevel Selected voice level, please refer to adc_audio_voice_level_t.
+ */
+void ADC_ConfigAudioVoiceLevel(ADC_Type *base, bool enableDetect, adc_audio_voice_level_t voiceLevel)
+{
+ uint32_t tmp32;
+
+ tmp32 = base->ADC_REG_VOICE_DET;
+ tmp32 &= ~(ADC_ADC_REG_VOICE_DET_DET_EN_MASK | ADC_ADC_REG_VOICE_DET_LEVEL_SEL_MASK);
+ tmp32 |= ADC_ADC_REG_VOICE_DET_DET_EN(enableDetect) | ADC_ADC_REG_VOICE_DET_LEVEL_SEL(voiceLevel);
+ base->ADC_REG_VOICE_DET = tmp32;
+}
+
+/*!
+ * brief Get status flags, including interrupt flags, raw flags, and so on.
+ *
+ * param base ADC peripheral base address.
+ * return The OR'ed value of ADC status flags, please refer to _adc_status_flags for details.
+ */
+uint32_t ADC_GetStatusFlags(ADC_Type *base)
+{
+ uint32_t tmp32;
+
+ tmp32 = base->ADC_REG_ISR;
+ tmp32 |= (base->ADC_REG_IRSR) << 7UL;
+ tmp32 |= (base->ADC_REG_STATUS) << 14UL;
+
+ return tmp32;
+}
diff --git a/drivers/mw320/adc/fsl_adc.h b/drivers/mw320/adc/fsl_adc.h
new file mode 100644
index 000000000..72768168d
--- /dev/null
+++ b/drivers/mw320/adc/fsl_adc.h
@@ -0,0 +1,798 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_ADC_H_
+#define _FSL_ADC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup adc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief ADC driver version */
+#define FSL_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+
+/*!
+ * @brief The enumeration of interrupts, this enumeration can be used to enable/disable interrupts.
+ */
+enum _adc_interrupt_enable
+{
+ kADC_DataReadyInterruptEnable = ADC_ADC_REG_IMR_RDY_MASK_MASK, /*!< Conversion data ready interrupt. */
+ kADC_GainSaturationInterruptEnable = ADC_ADC_REG_IMR_GAINSAT_MASK_MASK, /*!< Gain correction saturation interrupt */
+ kADC_OffsetSaturationInterruptEnable = ADC_ADC_REG_IMR_OFFSAT_MASK_MASK, /*!< Offset correction
+ saturation interupt enable. */
+ kADC_NegativeSaturationInterruptEnable = ADC_ADC_REG_IMR_DATASAT_NEG_MASK_MASK, /*!< ADC data negative side
+ saturation interrupt enable. */
+ kADC_PositiveSaturationInterruptEnable = ADC_ADC_REG_IMR_DATASAT_POS_MASK_MASK, /*!< ADC data positive side
+ saturation interrupt enable. */
+ kADC_FifoOverrunInterruptEnable = ADC_ADC_REG_IMR_FIFO_OVERRUN_MASK_MASK, /*!< FIFO overrun interrupt enable. */
+ kADC_FifoUnderrunInterruptEnable = ADC_ADC_REG_IMR_FIFO_UNDERRUN_MASK_MASK, /*!< FIFO underrun interrupt enable. */
+};
+
+/*!
+ * @brief The enumeration of adc status flags, including interrupt flags, raw flags, and so on.
+ *
+ * @note The raw flags will be captured regardless the interrupt mask. Both interrupt flags and raw
+ * flags can be cleared.
+ */
+enum _adc_status_flags
+{
+ /* Interrupt flags. */
+ kADC_DataReadyInterruptFlag = 1UL << 0UL, /*!< Conversion Data Ready interrupt flag. */
+ kADC_GainSaturationInterruptFlag = 1UL << 1UL, /*!< Gain correction saturation interrupt flag. */
+ kADC_OffsetSaturationInterruptFlag = 1UL << 2UL, /*!< Offset correction saturation interupt flag. */
+ kADC_NegativeSaturationInterruptFlag = 1UL << 3UL, /*!< ADC data negative side saturation interrupt flag. */
+ kADC_PositiveSaturationInterruptFlag = 1UL << 4UL, /*!< ADC data positive side saturation interrupt flag. */
+ kADC_FifoOverrunInterruptFlag = 1UL << 5UL, /*!< FIFO overrun interrupt flag. */
+ kADC_FifoUnderrunInterruptFlag = 1UL << 6UL, /*!< FIFO underrun interrupt flag. */
+
+ /* Raw flags. */
+ kADC_DataReadyRawFlag = 1UL << 7UL, /*!< Conversion data ready raw flag, this flag will be captured
+ regardless the interrupt mask. */
+ kADC_GainSaturationRawFlag = 1UL << 8UL, /*!< Gain correction saturation raw flag, this flag will be
+ captured regardless the interrupt mask. */
+ kADC_OffsetSaturationRawFlag = 1UL << 9UL, /*!< Offset correction saturation raw flag, this flag will be
+ captured regardless the interrupt mask. */
+ kADC_NegativeSaturationRawFlag = 1UL << 10UL, /*!< ADC data negative side saturation raw flag, this flag will
+ be captured regardless the interrupt mask. */
+ kADC_PositiveSaturationRawFlag = 1UL << 11UL, /*!< ADC data positive side saturation raw flag, this flag will
+ be captured regardless the interrupt mask. */
+ kADC_FifoOverrunRawFlag = 1UL << 12UL, /*!< FIFO overrun raw flag, this flag will be captured
+ regardless the interrupt mask. */
+ kADC_FifoUnderrunRawFlag = 1UL << 13UL, /*!< FIFO underrun interrupt mask, this flag will be captured
+ regardless the interrupt mask. */
+
+ kADC_ActiveStatusFlag = 1UL << 14UL, /*!< ADC conversion active status flag. */
+ kADC_FIFONotEmptyStatusFlag = 1UL << 15UL, /*!< FIFO not empty status flag. */
+ kADC_FifoFullStatusFlag = 1UL << 16UL, /*!< FIFO full status flag. */
+};
+
+/*!
+ * @brief ADC clock divider ratio type
+ */
+typedef enum _adc_clock_divider
+{
+ kADC_ClockDivider1 = 0U, /*!< Clock divider ratio is 1 */
+ kADC_ClockDivider2 = 1U, /*!< Clock divider ratio is 2 */
+ kADC_ClockDivider3 = 2U, /*!< Clock divider ratio is 3 */
+ kADC_ClockDivider4 = 3U, /*!< Clock divider ratio is 4 */
+ kADC_ClockDivider5 = 4U, /*!< Clock divider ratio is 5 */
+ kADC_ClockDivider6 = 5U, /*!< Clock divider ratio is 6 */
+ kADC_ClockDivider7 = 6U, /*!< Clock divider ratio is 7 */
+ kADC_ClockDivider8 = 7U, /*!< Clock divider ratio is 8 */
+ kADC_ClockDivider9 = 8U, /*!< Clock divider ratio is 9 */
+ kADC_ClockDivider10 = 9U, /*!< Clock divider ratio is 10 */
+ kADC_ClockDivider11 = 10U, /*!< Clock divider ratio is 11 */
+ kADC_ClockDivider12 = 11U, /*!< Clock divider ratio is 12 */
+ kADC_ClockDivider13 = 12U, /*!< Clock divider ratio is 13 */
+ kADC_ClockDivider14 = 13U, /*!< Clock divider ratio is 14 */
+ kADC_ClockDivider15 = 14U, /*!< Clock divider ratio is 15 */
+ kADC_ClockDivider16 = 15U, /*!< Clock divider ratio is 16 */
+ kADC_ClockDivider17 = 16U, /*!< Clock divider ratio is 17 */
+ kADC_ClockDivider18 = 17U, /*!< Clock divider ratio is 18 */
+ kADC_ClockDivider19 = 18U, /*!< Clock divider ratio is 19 */
+ kADC_ClockDivider20 = 19U, /*!< Clock divider ratio is 20 */
+ kADC_ClockDivider21 = 20U, /*!< Clock divider ratio is 21 */
+ kADC_ClockDivider22 = 21U, /*!< Clock divider ratio is 22 */
+ kADC_ClockDivider23 = 22U, /*!< Clock divider ratio is 23 */
+ kADC_ClockDivider24 = 23U, /*!< Clock divider ratio is 24 */
+ kADC_ClockDivider25 = 24U, /*!< Clock divider ratio is 25 */
+ kADC_ClockDivider26 = 25U, /*!< Clock divider ratio is 26 */
+ kADC_ClockDivider27 = 26U, /*!< Clock divider ratio is 27 */
+ kADC_ClockDivider28 = 27U, /*!< Clock divider ratio is 28 */
+ kADC_ClockDivider29 = 28U, /*!< Clock divider ratio is 29 */
+ kADC_ClockDivider30 = 29U, /*!< Clock divider ratio is 30 */
+ kADC_ClockDivider31 = 30U, /*!< Clock divider ratio is 31 */
+ kADC_ClockDivider32 = 31U, /*!< Clock divider ratio is 32 */
+} adc_clock_divider_t;
+
+/*!
+ * @brief ADC analog portion low-power mode selection.
+ */
+typedef enum _adc_analog_portion_power_mode
+{
+ kADC_PowerModeFullBiasingCurrent = 0U, /*!< Full biasing current. */
+ kADC_PowerModeHalfBiasingCurrent, /*!< Half biasing current. */
+} adc_analog_portion_power_mode_t;
+
+/*!
+ * @brief ADC resolution type
+ */
+typedef enum _adc_resolution
+{
+ kADC_Resolution12Bit = 0U, /*!< 12-bit resolution */
+ kADC_Resolution14Bit = 1U, /*!< 14-bit resolution */
+ kADC_Resolution16Bit = 2U, /*!< 16-bit resolution */
+ kADC_Resolution16BitAudio = 3U, /*!< 16-bit resolution for audio application */
+} adc_resolution_t;
+
+/*!
+ * @brief The enumeration of adc warm up time, the ADC warm-up state can also bypassed.
+ */
+typedef enum _adc_warm_up_time
+{
+ kADC_WarmUpTime1us = 0U, /*!< ADC warm-up time is 1 us. */
+ kADC_WarmUpTime2us, /*!< ADC warm-up time is 2 us. */
+ kADC_WarmUpTime3us, /*!< ADC warm-up time is 3 us. */
+ kADC_WarmUpTime4us, /*!< ADC warm-up time is 4 us. */
+ kADC_WarmUpTime5us, /*!< ADC warm-up time is 5 us. */
+ kADC_WarmUpTime6us, /*!< ADC warm-up time is 6 us. */
+ kADC_WarmUpTime7us, /*!< ADC warm-up time is 7 us. */
+ kADC_WarmUpTime8us, /*!< ADC warm-up time is 8 us. */
+ kADC_WarmUpTime9us, /*!< ADC warm-up time is 9 us. */
+ kADC_WarmUpTime10us, /*!< ADC warm-up time is 10 us. */
+ kADC_WarmUpTime11us, /*!< ADC warm-up time is 11 us. */
+ kADC_WarmUpTime12us, /*!< ADC warm-up time is 12 us. */
+ kADC_WarmUpTime13us, /*!< ADC warm-up time is 13 us. */
+ kADC_WarmUpTime14us, /*!< ADC warm-up time is 14 us. */
+ kADC_WarmUpTime15us, /*!< ADC warm-up time is 15 us. */
+ kADC_WarmUpTime16us, /*!< ADC warm-up time is 16 us. */
+ kADC_WarmUpTime17us, /*!< ADC warm-up time is 17 us. */
+ kADC_WarmUpTime18us, /*!< ADC warm-up time is 18 us. */
+ kADC_WarmUpTime19us, /*!< ADC warm-up time is 19 us. */
+ kADC_WarmUpTime20us, /*!< ADC warm-up time is 20 us. */
+ kADC_WarmUpTime21us, /*!< ADC warm-up time is 21 us. */
+ kADC_WarmUpTime22us, /*!< ADC warm-up time is 22 us. */
+ kADC_WarmUpTime23us, /*!< ADC warm-up time is 23 us. */
+ kADC_WarmUpTime24us, /*!< ADC warm-up time is 24 us. */
+ kADC_WarmUpTime25us, /*!< ADC warm-up time is 25 us. */
+ kADC_WarmUpTime26us, /*!< ADC warm-up time is 26 us. */
+ kADC_WarmUpTime27us, /*!< ADC warm-up time is 27 us. */
+ kADC_WarmUpTime28us, /*!< ADC warm-up time is 28 us. */
+ kADC_WarmUpTime29us, /*!< ADC warm-up time is 29 us. */
+ kADC_WarmUpTime30us, /*!< ADC warm-up time is 30 us. */
+ kADC_WarmUpTime31us, /*!< ADC warm-up time is 31 us. */
+ kADC_WarmUpTime32us, /*!< ADC warm-up time is 32 us. */
+ kADC_WarmUpStateBypass = 0x20U, /*!< ADC warm-up state bypassed. */
+} adc_warm_up_time_t;
+
+/*!
+ * @brief ADC voltage reference source type
+ */
+typedef enum _adc_vref_source
+{
+ kADC_Vref1P8V = 0U, /*!< Internal 1.8V reference */
+ kADC_Vref1P2V = 1U, /*!< Internal 1.2V reference */
+ kADC_VrefExternal = 2U, /*!< External single-ended reference though ADC_CH3 */
+ kADC_VrefInternal1P2V = 3U, /*!< Internal 1.2V reference with cap filter though ADC_CH3 */
+} adc_vref_source_t;
+
+/*!
+ * @brief ADC input mode type
+ */
+typedef enum _adc_input_mode
+{
+ kADC_InputSingleEnded = 0U, /*!< Single-ended mode */
+ kADC_InputDifferential = 1U, /*!< Differential mode */
+} adc_input_mode_t;
+
+/*!
+ * @brief ADC conversion mode type
+ */
+typedef enum _adc_conversion_mode
+{
+ kADC_ConversionOneShot = 0U, /*!< One shot mode */
+ kADC_ConversionContinuous = 1U, /*!< Continuous mode */
+} adc_conversion_mode_t;
+
+/*!
+ * @brief ADC scan length type
+ */
+typedef enum _adc_scan_length
+{
+ kADC_ScanLength_1 = 0U, /*!< Scan length is 1 */
+ kADC_ScanLength_2 = 1U, /*!< Scan length is 2 */
+ kADC_ScanLength_3 = 2U, /*!< Scan length is 3 */
+ kADC_ScanLength_4 = 3U, /*!< Scan length is 4 */
+ kADC_ScanLength_5 = 4U, /*!< Scan length is 5 */
+ kADC_ScanLength_6 = 5U, /*!< Scan length is 6 */
+ kADC_ScanLength_7 = 6U, /*!< Scan length is 7 */
+ kADC_ScanLength_8 = 7U, /*!< Scan length is 8 */
+ kADC_ScanLength_9 = 8U, /*!< Scan length is 9 */
+ kADC_ScanLength_10 = 9U, /*!< Scan length is 10 */
+ kADC_ScanLength_11 = 10U, /*!< Scan length is 11 */
+ kADC_ScanLength_12 = 11U, /*!< Scan length is 12 */
+ kADC_ScanLength_13 = 12U, /*!< Scan length is 13 */
+ kADC_ScanLength_14 = 13U, /*!< Scan length is 14 */
+ kADC_ScanLength_15 = 14U, /*!< Scan length is 15 */
+ kADC_ScanLength_16 = 15U, /*!< Scan length is 16 */
+} adc_scan_length_t;
+
+/*!
+ * @brief ADC average length type
+ */
+typedef enum _adc_average_length
+{
+ kADC_AverageNone = 0U, /*!< Average length: no average */
+ kADC_Average2 = 1U, /*!< Average length: 2 */
+ kADC_Average4 = 2U, /*!< Average length: 4 */
+ kADC_Average8 = 3U, /*!< Average length: 8 */
+ kADC_Average16 = 4U, /*!< Average length: 16 */
+} adc_average_length_t;
+
+/*!
+ * @brief ADC trigger source, including software trigger and multiple hardware trigger sources.
+ */
+typedef enum _adc_trigger_source
+{
+ kADC_TriggerSourceGpt = 0U, /*!< Hardware trigger, trigger source 0: GPT0 for ADC0 */
+ kADC_TriggerSourceAcomp = 1U, /*!< Hardware trigger, trigger source 1: ACOMP0 for ADC0 */
+ kADC_TriggerSourceGpio40 = 2U, /*!< Hardware trigger, trigger source 2: GPIO40 */
+ kADC_TriggerSourceGpio41 = 3U, /*!< Hardware trigger, trigger source 3: GPIO41 */
+ kADC_TriggerSourceSoftware = 4U, /*!< Software trigger. */
+} adc_trigger_source_t;
+
+/*!
+ * @brief ADC input buffer gain type
+ */
+typedef enum _adc_input_gain
+{
+ kADC_InputGain0P5 = 0U, /*!< Input buffer gain is 0.5 */
+ kADC_InputGain1 = 1U, /*!< Input buffer gain is 1 */
+ kADC_InputGain2 = 2U, /*!< Input buffer gain is 2 */
+} adc_input_gain_t;
+
+/*!
+ * @brief ADC result width type
+ */
+typedef enum _adc_result_width
+{
+ kADC_ResultWidth16 = 0U, /*!< 16-bit final result buffer width */
+ kADC_ResultWidth32 = 1U, /*!< 32-bit final result buffer width */
+} adc_result_width_t;
+
+/*!
+ * @brief The threshold of FIFO.
+ */
+typedef enum _adc_fifo_threshold
+{
+ kADC_FifoThresholdData1 = 0U, /*!< FIFO Threshold is 1 data. */
+ kADC_FifoThresholdData4, /*!< FIFO Threshold is 4 data. */
+ kADC_FifoThresholdData8, /*!< FIFO Threshold is 8 data. */
+ kADC_FifoThresholdData16, /*!< FIFO Threshold is 16 data. */
+} adc_fifo_threshold_t;
+
+/*!
+ * @brief ADC calibration voltage reference type
+ */
+typedef enum _adc_calibration_ref
+{
+ kADC_CalibrationVrefInternal = 0, /*!< Internal vref as input for calibration */
+ kADC_CalibrationVrefExternal = 1, /*!< External vref as input for calibration */
+} adc_calibration_ref_t;
+
+/*!
+ * @brief ADC scan channel type
+ */
+typedef enum _adc_scan_channel
+{
+ kADC_ScanChannel0 = 0U, /*!< Scan channel 0 */
+ kADC_ScanChannel1 = 1U, /*!< Scan channel 1 */
+ kADC_ScanChannel2 = 2U, /*!< Scan channel 2 */
+ kADC_ScanChannel3 = 3U, /*!< Scan channel 3 */
+ kADC_ScanChannel4 = 4U, /*!< Scan channel 4 */
+ kADC_ScanChannel5 = 5U, /*!< Scan channel 5 */
+ kADC_ScanChannel6 = 6U, /*!< Scan channel 6 */
+ kADC_ScanChannel7 = 7U, /*!< Scan channel 7 */
+ kADC_ScanChannel8 = 8U, /*!< Scan channel 8 */
+ kADC_ScanChannel9 = 9U, /*!< Scan channel 9 */
+ kADC_ScanChannel10 = 10U, /*!< Scan channel 10 */
+ kADC_ScanChannel11 = 11U, /*!< Scan channel 11 */
+ kADC_ScanChannel12 = 12U, /*!< Scan channel 12 */
+ kADC_ScanChannel13 = 13U, /*!< Scan channel 13 */
+ kADC_ScanChannel14 = 14U, /*!< Scan channel 14 */
+ kADC_ScanChannel15 = 15U, /*!< Scan channel 15 */
+} adc_scan_channel_t;
+
+/*!
+ * @brief ADC channel source type
+ */
+typedef enum _adc_channel_source
+{
+ kADC_CH0 = 0U, /*!< Single-ended mode, channel[0] and vssa */
+ kADC_CH1 = 1U, /*!< Single-ended mode, channel[1] and vssa */
+ kADC_CH2 = 2U, /*!< Single-ended mode, channel[2] and vssa */
+ kADC_CH3 = 3U, /*!< Single-ended mode, channel[3] and vssa */
+ kADC_CH4 = 4U, /*!< Single-ended mode, channel[4] and vssa */
+ kADC_CH5 = 5U, /*!< Single-ended mode, channel[5] and vssa */
+ kADC_CH6 = 6U, /*!< Single-ended mode, channel[6] and vssa */
+ kADC_CH7 = 7U, /*!< Single-ended mode, channel[7] and vssa */
+ kADC_VBATS = 8U, /*!< Single-ended mode, vbat_s and vssa */
+ kADC_VREF = 9U, /*!< Single-ended mode, vref_12 and vssa */
+ kADC_DACA = 10U, /*!< Single-ended mode, daca and vssa */
+ kADC_DACB = 11U, /*!< Single-ended mode, dacb and vssa */
+ kADC_VSSA = 12U, /*!< Single-ended mode, vssa and vssa */
+ kADC_TEMPP = 15U, /*!< Single-ended mode, temp_p and vssa */
+
+ kADC_CH0_CH1 = 0U, /*!< Differential mode, channel[0] and channel[1] */
+ kADC_CH2_CH3 = 1U, /*!< Differential mode, channel[2] and channel[3] */
+ kADC_CH4_CH5 = 2U, /*!< Differential mode, channel[4] and channel[5] */
+ kADC_CH6_CH7 = 3U, /*!< Differential mode, channel[6] and channel[7] */
+ kADC_DACA_DACB = 4U, /*!< Differential mode, daca and dacb */
+ kADC_VOICEP_VOICEN = 5U, /*!< Differential mode, voice_p and voice_n */
+ kADC_TEMPP_TEMPN = 15U, /*!< Differential mode, temp_p and temp_n */
+} adc_channel_source_t;
+
+/*!
+ * @brief Temperature sensor mode, including internal diode mode and external diode mode.
+ */
+typedef enum _adc_temperature_sensor_mode
+{
+ kADC_TSensorInternal = 0U, /*!< Internal diode mode. */
+ kADC_TSensorExternal, /*!< External diode mode. */
+} adc_temperature_sensor_mode_t;
+
+/*!
+ * @brief ADC audio pga gain type
+ */
+typedef enum _adc_audio_pga_voltage_gain
+{
+ kADC_AudioGain4 = 0U, /*!< Audio pga gain is 4 */
+ kADC_AudioGain8 = 1U, /*!< Audio pga gain is 8 */
+ kADC_AudioGain16 = 2U, /*!< Audio pga gain is 16 */
+ kADC_AudioGain32 = 3U, /*!< Audio pga gain is 32 */
+} adc_audio_pga_voltage_gain_t;
+
+/*!
+ * @brief ADC audio voice level selection.
+ */
+typedef enum _adc_audio_voice_level
+{
+ kADC_VoiceLevel0 = 0U, /*!< Input voice level >+255LSB or <-256LSB */
+ kADC_VoiceLevel1 = 1U, /*!< Input voice level >+511LSB or <-512LSB */
+ kADC_VoiceLevel2 = 2U, /*!< Input voice level >+1023LSB or <-1024LSB */
+ kADC_VoiceLevel3 = 3U, /*!< Input voice level >+2047LSB or <-2048LSB */
+} adc_audio_voice_level_t;
+
+/*!
+ * @brief The structure of adc options, including clock divider, power mode, and so on.
+ */
+typedef struct _adc_config
+{
+ /* ADC module basic options */
+ adc_clock_divider_t clockDivider : 5U; /*!< Analog 64M clock division ratio,
+ please refer to @ref adc_clock_divider_t. */
+ adc_analog_portion_power_mode_t powerMode : 1U;
+ adc_resolution_t resolution : 2U; /*!< Configure ADC resolution, please refer to
+ @ref adc_resolution_t. */
+ adc_warm_up_time_t warmupTime : 6U; /*!< Configure warm-up time. */
+
+ /* ADC conversion related options. */
+ adc_vref_source_t vrefSource : 2U; /*!< Configure voltage reference source,
+ please refer to @ref adc_vref_source_t. */
+ adc_input_mode_t inputMode : 1U; /*!< Configure input mode, such as #kADC_InputSingleEnded
+ or #kADC_InputDifferential. */
+ adc_conversion_mode_t conversionMode : 1U; /*!< Configure convrsion mode, such as
+ #kADC_ConversionOneShot or #kADC_ConversionContinuous. */
+ adc_scan_length_t scanLength : 4U; /*!< Configure the length of scan, please refer to
+ @ref adc_scan_length_t. */
+ adc_average_length_t averageLength : 3U; /*!< Configure hardware average number, please refer to
+ @ref adc_average_length_t */
+ adc_trigger_source_t triggerSource : 3U; /*!< Configure trigger source, the trigger source can be
+ divided into hardware trigger and software trigger,
+ please refer to @ref adc_trigger_source_t for details. */
+ adc_input_gain_t inputGain : 2U; /*!< Configure ADC input buffer gain, please refer to
+ @ref adc_input_gain_t. */
+ bool enableInputGainBuffer : 1U; /*!< Enable/Disable input gain buffer.
+ - \b true Enable input gain buffer.
+ - \b false Disable input gain buffer. */
+
+ /* ADC conversion result related options. */
+ adc_result_width_t resultWidth : 1U; /*!< Select result FIFO data packed format, please
+ refer to @ref adc_result_width_t. */
+ adc_fifo_threshold_t fifoThreshold : 2U; /*!< Configure FIFO threshold, please refer to
+ @ref adc_fifo_threshold_t. */
+ bool enableDMA : 1U; /*!< Enable/Disable DMA reqeust.
+ - \b true Enable DMA request.
+ - \b false Disable DMA request. */
+ bool enableADC : 1U; /*!< Enable/Disable ADC module.
+ - \b true Enable ADC module.
+ - \b false Disable ADC module. */
+} adc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name ADC Basic Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Initialize ADC module, including clock divider, power mode, and so on.
+ *
+ * @param base ADC peripheral base address.
+ * @param config The pointer to the structure @ref adc_config_t.
+ */
+void ADC_Init(ADC_Type *base, const adc_config_t *config);
+
+/*!
+ * @brief Get default configuration.
+ *
+ * @code
+ * config->clockDivider = kADC_ClockDivider1;
+ * config->powerMode = kADC_PowerModeFullBiasingCurrent;
+ * config->resolution = kADC_Resolution12Bit;
+ * config->warmupTime = kADC_WarmUpTime16us;
+ * config->vrefSource = kADC_Vref1P2V;
+ * config->inputMode = kADC_InputSingleEnded;
+ * config->conversionMode = kADC_ConversionContinuous;
+ * config->scanLength = kADC_ScanLength_1;
+ * config->averageLength = kADC_AverageNone;
+ * config->triggerSource = kADC_TriggerSourceSoftware;
+ * config->inputGain = kADC_InputGain1;
+ * config->enableInputGainBuffer = false;
+ * config->resultWidth = kADC_ResultWidth16;
+ * config->fifoThreshold = kADC_FifoThresholdData1;
+ * config->enableDMA = false;
+ * config->enableADC = false;
+ * @endcode
+ *
+ * @param config The Pointer to the structure @ref adc_config_t.
+ */
+void ADC_GetDefaultConfig(adc_config_t *config);
+
+/*!
+ * @brief De-initialize the ADC module.
+ *
+ * @param base ADC peripheral base address.
+ */
+void ADC_Deinit(ADC_Type *base);
+
+/*!
+ * @brief Reset the whole ADC block.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_DoSoftwareReset(ADC_Type *base)
+{
+ base->ADC_REG_CMD |= ADC_ADC_REG_CMD_SOFT_RST_MASK;
+
+ for (uint8_t i = 0U; i < 10U; i++)
+ {
+ __NOP();
+ }
+ base->ADC_REG_CMD &= ~ADC_ADC_REG_CMD_SOFT_RST_MASK;
+}
+
+/*!
+ * @brief Select ADC analog portion power mode.
+ *
+ * @param base ADC peripheral base address.
+ * @param powerMode The power mode to be set, please refer to @ref adc_analog_portion_power_mode_t.
+ */
+static inline void ADC_SelectAnalogPortionPowerMode(ADC_Type *base, adc_analog_portion_power_mode_t powerMode)
+{
+ base->ADC_REG_ANA = (base->ADC_REG_ANA & (~ADC_ADC_REG_ANA_BIAS_SEL_MASK)) | ADC_ADC_REG_ANA_BIAS_SEL(powerMode);
+}
+
+/*! @} */
+
+/*!
+ * @name ADC Calibration Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Do automatic calibration measurement.
+ *
+ * @note After auto calibrate successful, user can invoke ADC_GetAutoCalibrationData() to get self offset calibration
+ * value and self gain calibration value.
+ *
+ * @param base ADC peripheral base address.
+ * @param calVref The inpul reference channel for gain calibration,
+ * please refer to @ref adc_calibration_ref_t for details.
+ * @retval #kStatus_Success Auto calibrate successfully.
+ * @retval #kStatus_Fail Auto calibrate failure.
+ */
+status_t ADC_DoAutoCalibration(ADC_Type *base, adc_calibration_ref_t calVref);
+
+/*!
+ * @brief Get the ADC automatic calibration data.
+ *
+ * @param base ADC peripheral base address.
+ * @param offsetCal Self offset calibration data pointer, evaluate NULL if not requried.
+ * @param gainCal Self gain calibration data pointer, evaluate NULL if not requried.
+ */
+static inline void ADC_GetAutoCalibrationData(ADC_Type *base, uint16_t *offsetCal, uint16_t *gainCal)
+{
+ if (offsetCal != NULL)
+ {
+ *offsetCal = (uint16_t)(base->ADC_REG_OFFSET_CAL & ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_MASK);
+ }
+
+ if (gainCal != NULL)
+ {
+ *gainCal = (uint16_t)(base->ADC_REG_GAIN_CAL & ADC_ADC_REG_GAIN_CAL_GAIN_CAL_MASK);
+ }
+}
+
+/*!
+ * @brief Reset the automatic calibration data.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_ResetAutoCalibrationData(ADC_Type *base)
+{
+ base->ADC_REG_CONFIG |= ADC_ADC_REG_CONFIG_CAL_DATA_RST_MASK;
+ for (volatile uint8_t i = 0U; i < 10U; i++)
+ {
+ __NOP();
+ }
+ base->ADC_REG_CONFIG &= ~ADC_ADC_REG_CONFIG_CAL_DATA_RST_MASK;
+}
+
+/*!
+ * @brief Do user defined calibration.
+ *
+ * @param base ADC peripheral base address.
+ * @param offsetCal User defined offset calibration data.
+ * @param gainCal User defined gain calibration date.
+ */
+static inline void ADC_DoUserCalibration(ADC_Type *base, uint16_t offsetCal, uint16_t gainCal)
+{
+ /* Load user defined offset and gain calibration data */
+ base->ADC_REG_OFFSET_CAL = (base->ADC_REG_OFFSET_CAL & ~(ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR_MASK)) |
+ ADC_ADC_REG_OFFSET_CAL_OFFSET_CAL_USR(offsetCal);
+ base->ADC_REG_GAIN_CAL = (base->ADC_REG_GAIN_CAL & ~(ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR_MASK)) |
+ ADC_ADC_REG_GAIN_CAL_GAIN_CAL_USR(gainCal);
+
+ /* Use user defined calibration data */
+ base->ADC_REG_CONFIG |= ADC_ADC_REG_CONFIG_CAL_DATA_SEL_MASK;
+}
+
+/*! @} */
+
+/*!
+ * @name ADC Temperature Sensor Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enable/disable temperature sensor.
+ *
+ * @note This function is useful only when the channel source is temperature sensor.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Used to enable/disable temperature sensor.
+ * - \b true Enable temperature sensor.
+ * - \b false Disable temperature sensor.
+ */
+static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->ADC_REG_ANA |= ADC_ADC_REG_ANA_TS_EN_MASK;
+ }
+ else
+ {
+ base->ADC_REG_ANA &= ~ADC_ADC_REG_ANA_TS_EN_MASK;
+ }
+}
+
+/*!
+ * @brief Set temperature sensor mode, available selections are internal diode mode and external diode mode.
+ *
+ * @param base ADC peripheral base address.
+ * @param tSensorMode The temperature sensor mode to be set, please refer to @ref adc_temperature_sensor_mode_t.
+ */
+static inline void ADC_SetTemperatureSensorMode(ADC_Type *base, adc_temperature_sensor_mode_t tSensorMode)
+{
+ base->ADC_REG_ANA =
+ (base->ADC_REG_ANA & ~(ADC_ADC_REG_ANA_TSEXT_SEL_MASK)) | ADC_ADC_REG_ANA_TSEXT_SEL(tSensorMode);
+}
+
+/*! @} */
+
+/*!
+ * @name ADC Audio Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enable/disable audio PGA and decimation rate select.
+ *
+ * @param base ADC peripheral base address.
+ * @param enable Used to enable/disable audio PGA and decimation rate select.
+ * - \b true Enable audio PGA and decimation rate select.
+ * - \b false Disable audio PGA and decimation rate select.
+ */
+static inline void ADC_EnableAudio(ADC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->ADC_REG_AUDIO |= ADC_ADC_REG_AUDIO_EN_MASK;
+ }
+ else
+ {
+ base->ADC_REG_AUDIO &= ~ADC_ADC_REG_AUDIO_EN_MASK;
+ }
+}
+
+/*!
+ * @brief Set audio PGA voltage gain.
+ *
+ * @param base ADC peripheral base address.
+ * @param voltageGain The selected audio PGA voltage gain, please refer to @ref adc_audio_pga_voltage_gain_t.
+ */
+static inline void ADC_SetAudioPGAVoltageGain(ADC_Type *base, adc_audio_pga_voltage_gain_t voltageGain)
+{
+ base->ADC_REG_AUDIO =
+ (base->ADC_REG_AUDIO & (~ADC_ADC_REG_AUDIO_PGA_GAIN_MASK)) | ADC_ADC_REG_AUDIO_PGA_GAIN(voltageGain);
+}
+
+/*!
+ * @brief Configure audio voice level.
+ *
+ * @param base ADC peripheral base address.
+ * @param enableDetect Used to enable/disable voice level detection.
+ * - \b true Enable voice level detection.
+ * - \b false Disable voice level detection.
+ * @param voiceLevel Selected voice level, please refer to @ref adc_audio_voice_level_t.
+ */
+void ADC_ConfigAudioVoiceLevel(ADC_Type *base, bool enableDetect, adc_audio_voice_level_t voiceLevel);
+
+/*! @} */
+
+/*!
+ * @name ADC Conversion Related Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Set scan channel mux source.
+ *
+ * @param base ADC peripheral base address.
+ * @param scanChannel The selected channel, please refer to @ref adc_scan_channel_t for details.
+ * @param channelSource The mux source to be set to the selected channel,
+ * please refer to @ref adc_channel_source_t for details.
+ */
+void ADC_SetScanChannel(ADC_Type *base, adc_scan_channel_t scanChannel, adc_channel_source_t channelSource);
+
+/*!
+ * @brief If trigger mode is selected as software trigger, invoking this function to start conversion.
+ *
+ * @note This API will also clear the FIFO.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_DoSoftwareTrigger(ADC_Type *base)
+{
+ base->ADC_REG_CMD |= ADC_ADC_REG_CMD_CONV_START_MASK;
+}
+
+/*!
+ * @brief Invoke this function to stop conversion.
+ *
+ * @param base ADC peripheral base address.
+ */
+static inline void ADC_StopConversion(ADC_Type *base)
+{
+ base->ADC_REG_CMD &= ~ADC_ADC_REG_CMD_CONV_START_MASK;
+}
+
+/*!
+ * @brief Get the 32-bit width packed ADC conversion result.
+ *
+ * @param base ADC peripheral base address.
+ * @return 32-bit width packed ADC conversion result.
+ */
+static inline uint32_t ADC_GetConversionResult(ADC_Type *base)
+{
+ return (uint32_t)(base->ADC_REG_RESULT);
+}
+
+/*!
+ * @brief Get the ADC FIFO data count.
+ *
+ * @param base ADC peripheral base address.
+ * @return ADC FIFO data count.
+ */
+static inline uint8_t ADC_GetFifoDataCount(ADC_Type *base)
+{
+ return (uint8_t)((base->ADC_REG_STATUS & ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_MASK) >>
+ ADC_ADC_REG_STATUS_FIFO_DATA_COUNT_SHIFT);
+}
+
+/*! @} */
+
+/*!
+ * @name ADC Interrupt Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enable interrupts, such as conversion data ready interrupt, gain correction saturation interrupt, FIFO
+ * under run interrupt, and so on.
+ *
+ * @param base ADC peripheral base address.
+ * @param interruptMask The interrupts to be enabled, should be the OR'ed value of @ref _adc_interrupt_enable.
+ */
+static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t interruptMask)
+{
+ base->ADC_REG_IMR &= ~(interruptMask);
+}
+
+/*!
+ * @brief Disable interrupts, such as conversion data ready interrupt, gain correction saturation interrupt, FIFO
+ * under run interrupt, and so on.
+ *
+ * @param base ADC peripheral base address.
+ * @param interruptMask The interrupts to be disabled, should be the OR'ed value of @ref _adc_interrupt_enable.
+ */
+static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t interruptMask)
+{
+ base->ADC_REG_IMR |= interruptMask;
+}
+
+/*! @} */
+
+/*!
+ * @name ADC Status Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Get status flags, including interrupt flags, raw flags, and so on.
+ *
+ * @param base ADC peripheral base address.
+ * @return The OR'ed value of ADC status flags, please refer to @ref _adc_status_flags for details.
+ */
+uint32_t ADC_GetStatusFlags(ADC_Type *base);
+
+/*!
+ * @brief Clear status flags.
+ *
+ * @note Only interrupt flags and raw flags can be cleared.
+ *
+ * @param base ADC peripheral base address.
+ * @param statusFlagsMask The OR'ed value of status flags to be cleared,
+ * please refer to @ref _adc_status_flags for details.
+ */
+static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t statusFlagsMask)
+{
+ base->ADC_REG_ICR = (statusFlagsMask & 0x7FUL) | ((statusFlagsMask >> 7UL) & 0x7FUL);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_ADC_H_ */
diff --git a/drivers/mw320/aes/driver_mw_aes.cmake b/drivers/mw320/aes/driver_mw_aes.cmake
new file mode 100644
index 000000000..3fc6d27bc
--- /dev/null
+++ b/drivers/mw320/aes/driver_mw_aes.cmake
@@ -0,0 +1,14 @@
+#Description: MW_AES Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_aes component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_aes.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/aes/fsl_aes.c b/drivers/mw320/aes/fsl_aes.c
new file mode 100644
index 000000000..fa7e41c8d
--- /dev/null
+++ b/drivers/mw320/aes/fsl_aes.c
@@ -0,0 +1,1491 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_aes.h"
+#include "string.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mw_aes"
+#endif
+
+#define AES_CTRL1_RESET_VALUE (AES_CTRL1_OUT_MSG_MASK | AES_CTRL1_OUT_MIC_MASK)
+#define AES_CTRL2_RESET_VALUE (0U)
+#define AES_ASTR_LEN_RESET_VALUE (0U)
+#define AES_MSTR_LEN_RESET_VALUE (0U)
+#define AES_IV0_RESET_VALUE (0U)
+#define AES_IV1_RESET_VALUE (0U)
+#define AES_IV2_RESET_VALUE (0U)
+#define AES_IV3_RESET_VALUE (0U)
+#define AES_KEY0_RESET_VALUE (0U)
+#define AES_KEY1_RESET_VALUE (0U)
+#define AES_KEY2_RESET_VALUE (0U)
+#define AES_KEY3_RESET_VALUE (0U)
+#define AES_KEY4_RESET_VALUE (0U)
+#define AES_KEY5_RESET_VALUE (0U)
+#define AES_KEY6_RESET_VALUE (0U)
+#define AES_KEY7_RESET_VALUE (0U)
+#define AES_IMR_RESET_VALUE (AES_IMR_MASK_0_MASK | AES_IMR_MASK_1_MASK | AES_IMR_MASK_2_MASK)
+
+/*!
+ * @brief Structure to handle CCM output data array.
+ *
+ * In CCM calculation, the input data is written as 4-byte to AES registers,
+ * and the data should be got from different arrays. The problem is the arrays
+ * might be 4-byte unaligned. For easy operation, the arrays are collected into
+ * a structure, to operate use a common function.
+ */
+typedef struct
+{
+ const uint8_t *data;
+ size_t len;
+} aes_input_data_array_t;
+
+/*!
+ * @brief Structure to handle CCM output data array.
+ *
+ * In CCM calculation, the output data is read as 4-byte from AES registers,
+ * and the data should be saved to different arrays. The problem is the arrays
+ * might be 4-byte unaligned. For easy operation, the arrays are collected into
+ * a structure, to operate use a common function.
+ */
+typedef struct
+{
+ uint8_t *data;
+ size_t len;
+} aes_output_data_array_t;
+
+/*!
+ * @brief Union for bytes and word convertion.
+ */
+typedef union
+{
+ uint32_t word;
+ uint8_t bytes[4];
+} aes_word_byte_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief AES common operation.
+ *
+ * Only used for kAES_ModeEncryptECB, kAES_ModeDecryptECB, kAES_ModeEncryptCBC,
+ * kAES_ModeDecryptCBC, kAES_ModeCTR
+ *
+ * @param base AES peripheral base address.
+ * @param mode AES mode used in this operation.
+ * @param input Input data.
+ * @param output Output data.
+ * @param len Length of input and output data in bytes.
+ * @param inputVector Input vector.
+ * @param outputVector Output vector.
+ */
+static void AES_Operation(AES_Type *base,
+ aes_mode_t mode,
+ const uint8_t *input,
+ uint8_t *output,
+ size_t len,
+ const uint8_t *inputVector,
+ uint8_t *outputVector);
+
+/*!
+ * @brief Read word from a group of arrays.
+ *
+ * This function reads word from a group of arrays. The arrays might not be
+ * 4-byte aligned.
+ *
+ * @param arrays Pointer to the array group.
+ * @param totalArrays Number of the arrays in the group.
+ * @param curArrayIndex Reading from which array currently. This could be set to 0
+ * before the first read, and should not be modified in later read.
+ * @return The word read from arrays. If there is no more data from the array, returns 0.
+ */
+static uint32_t AES_ReadWordFromArray(aes_input_data_array_t arrays[], uint8_t totalArrays, uint8_t *curArrayIndex);
+
+/*!
+ * @brief Write word to a group of arrays.
+ *
+ * This function writes word to a group of arrays. The arrays might not be
+ * 4-byte aligned.
+ *
+ * @param arrays Pointer to the array group.
+ * @param totalArrays Number of the arrays in the group.
+ * @param curArrayIndex Writing to which array currently. This could be set to 0
+ * before the first read, and should not be modified in later write.
+ * @param word The word to write. If no space in the arrays anymore, the word will be dropped.
+ */
+static void AES_WriteWordToArray(aes_output_data_array_t arrays[],
+ uint8_t totalArrays,
+ uint8_t *curArrayIndex,
+ uint32_t word);
+
+/*!
+ * @brief Prepare the CCM operation.
+ *
+ * @param base AES peripheral base address.
+ * @param mode AES mode used in this operation.
+ * @param dataSize Length of plaintext or ciphertext in bytes.
+ * @param iv Input vector.
+ * @param ivSize Length of input vector in bytes.
+ * @param aadSize Length of input additional authentication data in bytes.
+ * @param tagSize Length of tag data in bytes.
+ * @retval kStatus_Success Prepare successfully.
+ * @retval kStatus_InvalidArgument Invalid parameters.
+ */
+static status_t AES_PrepareTagCcm(
+ AES_Type *base, aes_mode_t mode, size_t dataSize, const uint8_t *iv, size_t ivSize, size_t aadSize, size_t tagSize);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static aes_lock_func_t s_aesLockFunc = NULL;
+static aes_unlock_func_t s_aesUnlockFunc = NULL;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t AES_ReadWordFromArray(aes_input_data_array_t arrays[], uint8_t totalArrays, uint8_t *curArrayIndex)
+{
+ uint8_t byteCopyIndex;
+ aes_input_data_array_t *pArray;
+ aes_word_byte_t ret;
+
+ pArray = &arrays[*curArrayIndex];
+
+ if (pArray->len >= sizeof(uint32_t))
+ {
+ ret.word = *(uint32_t *)(pArray->data);
+ pArray->len -= sizeof(uint32_t);
+ pArray->data += sizeof(uint32_t);
+ }
+ else
+ {
+ ret.word = 0;
+ byteCopyIndex = 0;
+
+ while (*curArrayIndex < totalArrays)
+ {
+ while ((byteCopyIndex < sizeof(uint32_t)) && (pArray->len > 0U))
+ {
+ ret.bytes[byteCopyIndex] = *(pArray->data);
+ pArray->len--;
+ pArray->data++;
+ byteCopyIndex++;
+ }
+
+ if (byteCopyIndex == sizeof(uint32_t))
+ {
+ break;
+ }
+ else
+ {
+ (*curArrayIndex)++;
+ pArray++;
+ continue;
+ }
+ }
+ }
+
+ return ret.word;
+}
+
+static void AES_WriteWordToArray(aes_output_data_array_t arrays[],
+ uint8_t totalArrays,
+ uint8_t *curArrayIndex,
+ uint32_t word)
+{
+ uint8_t byteCopyIndex;
+ aes_output_data_array_t *pArray;
+ aes_word_byte_t data;
+
+ pArray = &arrays[*curArrayIndex];
+
+ if (pArray->len >= sizeof(uint32_t))
+ {
+ /* If pArray->data is NULL, drop the data. */
+ if (NULL != pArray->data)
+ {
+ *(uint32_t *)(pArray->data) = word;
+ pArray->data += sizeof(uint32_t);
+ }
+
+ pArray->len -= sizeof(uint32_t);
+ }
+ else
+ {
+ data.word = word;
+ byteCopyIndex = 0;
+
+ while (*curArrayIndex < totalArrays)
+ {
+ while ((byteCopyIndex < sizeof(uint32_t)) && (pArray->len > 0U))
+ {
+ if (NULL != pArray->data)
+ {
+ *pArray->data = data.bytes[byteCopyIndex];
+ pArray->data++;
+ }
+
+ pArray->len--;
+ byteCopyIndex++;
+ }
+
+ if (byteCopyIndex == sizeof(uint32_t))
+ {
+ break;
+ }
+ else
+ {
+ (*curArrayIndex)++;
+ pArray++;
+ continue;
+ }
+ }
+ }
+}
+
+static void AES_Operation(AES_Type *base,
+ aes_mode_t mode,
+ const uint8_t *input,
+ uint8_t *output,
+ size_t len,
+ const uint8_t *inputVector,
+ uint8_t *outputVector)
+{
+ size_t inputSize = len;
+ size_t outputSize = len;
+
+ AES_Reset(base);
+
+ AES_SetMode(base, mode);
+
+ AES_SetMsgLen(base, (uint32_t)len);
+
+ if (inputVector != NULL)
+ {
+ AES_SetInputVector(base, inputVector);
+ }
+
+ AES_EnableOutMsg(base, true);
+
+ AES_Start(base);
+
+ while (outputSize > 0)
+ {
+ if (inputSize > 0)
+ {
+ /* Input FIFO not full, feed data. */
+ if (0U == (AES_GetStatus(base) & kAES_InputFIFOFullFlag))
+ {
+ AES_WriteData(base, *(const uint32_t *)input);
+ input += sizeof(uint32_t);
+ inputSize -= sizeof(uint32_t);
+ }
+ }
+
+ /* Output FIFO not empty, read data. */
+ if (0U == (AES_GetStatus(base) & kAES_OutputFIFOEmptyFlag))
+ {
+ *(uint32_t *)output = AES_ReadData(base);
+ output += sizeof(uint32_t);
+ outputSize -= sizeof(uint32_t);
+ }
+ }
+
+ if (outputVector != NULL)
+ {
+ AES_GetOutputVector(base, outputVector);
+ }
+
+ AES_Stop(base);
+}
+
+static status_t AES_PrepareTagCcm(
+ AES_Type *base, aes_mode_t mode, size_t dataSize, const uint8_t *iv, size_t ivSize, size_t aadSize, size_t tagSize)
+{
+ uint8_t localIV[AES_VECTOR_SIZE] = {0};
+ aes_miclen_t micLen;
+
+ /* Verify parameter. */
+ if ((ivSize < 7) || (ivSize > 13))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ if ((tagSize != 16U) && (tagSize != 8U) && (tagSize != 4U) && (tagSize != 0U))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ AES_Reset(base);
+
+ /* Input vector configuration. */
+ memcpy(localIV, iv, ivSize);
+
+ localIV[13] = 15U - ivSize;
+
+ AES_SetInputVector(base, localIV);
+
+ /* AAD configuration. */
+ AES_SetAadLen(base, aadSize);
+
+ /* TAG configuration. */
+ micLen = (tagSize == 16U) ?
+ kAES_MicBytes16 :
+ ((tagSize == 8U) ? kAES_MicBytes8 : ((tagSize == 4U) ? kAES_MicBytes4 : kAES_MicBytes0));
+
+ AES_SetMode(base, mode);
+
+ AES_SetMICLength(base, micLen);
+
+ if (kAES_ModeDecryptCCM == mode)
+ {
+ AES_AppendMIC(base, false);
+ }
+ else
+ {
+ AES_AppendMIC(base, (kAES_MicBytes0 != micLen));
+ }
+
+ AES_SetMsgLen(base, dataSize);
+
+ AES_EnableOutMsg(base, true);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Initializes AES module.
+ *
+ * Initialize the module, reset the module and set the registers to default status.
+ *
+ * param base AES peripheral base address.
+ */
+void AES_Init(AES_Type *base)
+{
+ AES_Reset(base);
+
+ base->CTRL1 = AES_CTRL1_RESET_VALUE;
+ base->CTRL2 = AES_CTRL2_RESET_VALUE;
+ base->ASTR_LEN = AES_ASTR_LEN_RESET_VALUE;
+ base->MSTR_LEN = AES_MSTR_LEN_RESET_VALUE;
+ base->IV0 = AES_IV0_RESET_VALUE;
+ base->IV1 = AES_IV1_RESET_VALUE;
+ base->IV2 = AES_IV2_RESET_VALUE;
+ base->IV3 = AES_IV3_RESET_VALUE;
+ base->KEY0 = AES_KEY0_RESET_VALUE;
+ base->KEY1 = AES_KEY1_RESET_VALUE;
+ base->KEY2 = AES_KEY2_RESET_VALUE;
+ base->KEY3 = AES_KEY3_RESET_VALUE;
+ base->KEY4 = AES_KEY4_RESET_VALUE;
+ base->KEY5 = AES_KEY5_RESET_VALUE;
+ base->KEY6 = AES_KEY6_RESET_VALUE;
+ base->KEY7 = AES_KEY7_RESET_VALUE;
+ base->IMR = AES_IMR_RESET_VALUE;
+
+ /* Clear interrupt status. */
+ base->ICR = base->IRSR;
+}
+
+/*!
+ * brief Deinitializes AES module.
+ *
+ * Deinitialize the module and reset the module.
+ *
+ * param base AES peripheral base address.
+ */
+void AES_Deinit(AES_Type *base)
+{
+ AES_Reset(base);
+}
+
+/*!
+ * brief Reset AES module.
+ *
+ * Reset the module.
+ *
+ * param base AES peripheral base address.
+ */
+void AES_Reset(AES_Type *base)
+{
+ uint32_t cnt = 0x20;
+
+ base->CTRL2 |= AES_CTRL2_AES_RESET_MASK;
+
+ while (0U != cnt--)
+ {
+ __NOP();
+ }
+
+ base->CTRL2 &= ~AES_CTRL2_AES_RESET_MASK;
+}
+
+/*!
+ * brief Set the AES input vector.
+
+ * param base AES peripheral base address.
+ * param inputVector Input vector.
+ */
+void AES_SetInputVector(AES_Type *base, const uint8_t inputVector[AES_VECTOR_SIZE])
+{
+ base->IV0 = ((uint32_t *)inputVector)[0];
+ base->IV1 = ((uint32_t *)inputVector)[1];
+ base->IV2 = ((uint32_t *)inputVector)[2];
+ base->IV3 = ((uint32_t *)inputVector)[3];
+}
+
+/*!
+ * brief Get the AES output vector.
+ *
+ * param base AES peripheral base address.
+ * param outputVector Array to save the output vector.
+ */
+void AES_GetOutputVector(AES_Type *base, uint8_t outputVector[AES_VECTOR_SIZE])
+{
+ ((uint32_t *)outputVector)[0] = base->OV0;
+ ((uint32_t *)outputVector)[1] = base->OV1;
+ ((uint32_t *)outputVector)[2] = base->OV2;
+ ((uint32_t *)outputVector)[3] = base->OV3;
+}
+
+/*!
+ * brief Read AES CCM MIC output value.
+ *
+ * param base AES peripheral base address.
+ * param micData The memory to save the MIC data.
+ * param len Length of micData in word, the valid range is 1~4.
+ * retval kStatus_InvalidArgument The required length is wrong.
+ * retval kStatus_Success Get MIC successfully.
+ */
+status_t AES_ReadMIC(AES_Type *base, uint32_t *micData, uint8_t len)
+{
+ uint32_t cnt;
+
+ /* check for len */
+ if ((len == 0U) || (len > 4U))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* captured the mic data */
+ for (cnt = 0u; cnt < len; cnt++)
+ {
+ micData[cnt] = (&base->OV0)[cnt];
+ }
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Clear AES input or output FIFO.
+ *
+ * param base AES peripheral base address.
+ * param fifo The FIFO to clear.
+ */
+void AES_ClearFIFO(AES_Type *base, aes_fifo_t fifo)
+{
+ uint32_t tmpCnt = 0x20;
+
+ base->CTRL1 |= (uint32_t)fifo;
+
+ while (0U != tmpCnt--)
+ {
+ __NOP();
+ }
+
+ base->CTRL1 &= ~(uint32_t)fifo;
+}
+
+/*!
+ * brief Sets AES key.
+ *
+ * Sets AES key.
+ *
+ * param base AES peripheral base address
+ * param key Input key to use for encryption or decryption
+ * param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * return Status from Set Key operation
+ */
+status_t AES_SetKey(AES_Type *base, const uint8_t *key, size_t keySize)
+{
+ status_t status = kStatus_Success;
+ aes_keysize_t aesKeySize;
+ uint32_t i;
+
+ switch (keySize)
+ {
+ case 16:
+ aesKeySize = kAES_KeyBytes16;
+ break;
+
+ case 24:
+ aesKeySize = kAES_KeyBytes24;
+ break;
+
+ case 32:
+ aesKeySize = kAES_KeyBytes32;
+ break;
+
+ default:
+ status = kStatus_InvalidArgument;
+ }
+
+ if (kStatus_Success == status)
+ {
+ /* Set aesKeySize. */
+ base->CTRL1 = (base->CTRL1 & ~AES_CTRL1_KEY_SIZE_MASK) | AES_CTRL1_KEY_SIZE(aesKeySize);
+
+ for (i = 0; i < keySize / 4; i++)
+ {
+ (&base->KEY0)[7 - i] = ((const uint32_t *)key)[i];
+ }
+ for (; i < 8; i++)
+ {
+ (&base->KEY0)[7 - i] = 0U;
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * brief Encrypts AES using the ECB block mode.
+ *
+ * Encrypts AES using the ECB block mode.
+ *
+ * param base AES peripheral base address
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from encrypt operation
+ */
+status_t AES_EncryptEcb(AES_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, size_t size)
+{
+ status_t status;
+
+ /* ECB mode, size must be 16-byte multiple */
+ if ((size % 16U) != 0U)
+ {
+ status = kStatus_InvalidArgument;
+ }
+ else
+ {
+ AES_Operation(base, kAES_ModeEncryptECB, plaintext, ciphertext, size, NULL, NULL);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Decrypts AES using the ECB block mode.
+ *
+ * Decrypts AES using the ECB block mode.
+ *
+ * param base AES peripheral base address
+ * param ciphertext Input ciphertext to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from decrypt operation
+ */
+status_t AES_DecryptEcb(AES_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, size_t size)
+{
+ status_t status;
+
+ /* ECB mode, size must be 16-byte multiple */
+ if ((size % 16U) != 0U)
+ {
+ status = kStatus_InvalidArgument;
+ }
+ else
+ {
+ AES_Operation(base, kAES_ModeDecryptECB, ciphertext, plaintext, size, NULL, NULL);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Encrypts AES using CBC block mode.
+ *
+ * param base AES peripheral base address
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * param[out] ov Output vector used for chained operation, could be NULL.
+ * return Status from encrypt operation
+ */
+status_t AES_EncryptCbc(AES_Type *base,
+ const uint8_t *plaintext,
+ uint8_t *ciphertext,
+ size_t size,
+ const uint8_t iv[AES_VECTOR_SIZE],
+ uint8_t ov[AES_VECTOR_SIZE])
+{
+ status_t status;
+
+ /* ECB mode, size must be 16-byte multiple */
+ if ((size % 16U) != 0U)
+ {
+ status = kStatus_InvalidArgument;
+ }
+ else
+ {
+ AES_Operation(base, kAES_ModeEncryptCBC, plaintext, ciphertext, size, iv, ov);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Decrypts AES using CBC block mode.
+ *
+ * param base AES peripheral base address
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * param[out] ov Output vector used for chained operation, could be NULL.
+ * return Status from decrypt operation
+ */
+status_t AES_DecryptCbc(AES_Type *base,
+ const uint8_t *ciphertext,
+ uint8_t *plaintext,
+ size_t size,
+ const uint8_t iv[AES_VECTOR_SIZE],
+ uint8_t ov[AES_VECTOR_SIZE])
+{
+ status_t status;
+
+ /* ECB mode, size must be 16-byte multiple */
+ if ((size % 16U) != 0U)
+ {
+ status = kStatus_InvalidArgument;
+ }
+ else
+ {
+ AES_Operation(base, kAES_ModeDecryptCBC, ciphertext, plaintext, size, iv, ov);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Encrypts or decrypts AES using CTR block mode.
+ *
+ * Encrypts or decrypts AES using CTR block mode.
+ * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * For chained calls, the internal status are saved in the parameters: nonce, streamBlock,
+ * and offset. In this case, initialize nonce to the desired value, and initialize offset to 0
+ * before the first call, in the following calls, the nonce, streamBlock, and offset should be
+ * preserved.
+ *
+ * note The streamBlock contains sensitive data, discard it after used.
+ *
+ * param base AES peripheral base address
+ * param input Input data for CTR block mode
+ * param[out] output Output data for CTR block mode
+ * param size Size of input and output data in bytes
+ * param[in,out] nonce and counter(updates on return)
+ * param[out] streamBlock Saved block for chained CTR calls. NULL can be passed if chained calls are
+ * not used.
+ * param[out] offset Offset in streamBlock. NULL can be passed if chained calls
+ * are not used.
+ * return Status from crypt operation
+ */
+status_t AES_CryptCtr(AES_Type *base,
+ const uint8_t *input,
+ uint8_t *output,
+ size_t size,
+ uint8_t nonce[AES_BLOCK_SIZE],
+ uint8_t streamBlock[AES_BLOCK_SIZE],
+ size_t *offset)
+{
+ size_t n2, n3;
+ size_t localOffset;
+ uint8_t lastBlockIn[AES_BLOCK_SIZE];
+ uint8_t lastBlockOut[AES_BLOCK_SIZE];
+
+ /*
+ * The AES output is divided into three parts, the length of each parts are:
+ * n1, n2, n3.
+ *
+ * n1: If previous calculation is not AES block size aligned, there are valid data in
+ * streamBlock. Input data should first XOR'ed with the data in streamBlock.
+ * n2: After n1, the AES block size aligned data in left data is n2. They are fed into
+ * AES directly.
+ * n3: After n2, the left AES block size unaligned part is n3. They are pad to AES
+ * block size and fed into AES.
+ */
+
+ if ((NULL == streamBlock) || (NULL == offset))
+ {
+ localOffset = 0U;
+ }
+ else
+ {
+ localOffset = *offset;
+ }
+
+ /* Handle the n1 part. */
+ while (0U != size)
+ {
+ if (localOffset == 0U)
+ {
+ break;
+ }
+
+ *output = *input ^ streamBlock[localOffset];
+ output++;
+ input++;
+ size--;
+ localOffset++;
+
+ localOffset &= (AES_BLOCK_SIZE - 1U);
+ }
+
+ if (offset != NULL)
+ {
+ *offset = localOffset;
+ }
+
+ n2 = size & ~(AES_BLOCK_SIZE - 1U);
+ n3 = size - n2;
+
+ /* Handle the n2 part. */
+ if (n2 > 0)
+ {
+ AES_Operation(base, kAES_ModeCTR, input, output, n2, nonce, nonce);
+
+ input += n2;
+ output += n2;
+ }
+
+ /* Handle the n3 part. */
+ if (n3 > 0)
+ {
+ memset(lastBlockIn, 0, sizeof(lastBlockIn));
+ memcpy(lastBlockIn, input, n3);
+
+ AES_Operation(base, kAES_ModeCTR, lastBlockIn, lastBlockOut, AES_BLOCK_SIZE, nonce, nonce);
+
+ memcpy(output, lastBlockOut, n3);
+
+ if (NULL != streamBlock)
+ {
+ memcpy(&streamBlock[n3], &lastBlockOut[n3], AES_BLOCK_SIZE - n3);
+ }
+
+ if (NULL != offset)
+ {
+ *offset = n3;
+ }
+ }
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Encrypts AES and tags using CCM block mode.
+ *
+ * Encrypts AES and optionally tags using CCM block mode.
+ *
+ * param base AES peripheral base address
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text.
+ * param size Size of input and output data in bytes
+ * param iv Input initial vector
+ * param ivSize Size of the iv
+ * param aad Input additional authentication data
+ * param aadSize Input size in bytes of aad.
+ * param[out] tag Output hash tag. Set to NULL to skip tag processing.
+ * param tagSize Input size of the tag to generate, in bytes. Must be 0,4,8, or 16.
+ * return Status from encrypt operation
+ */
+status_t AES_EncryptTagCcm(AES_Type *base,
+ const uint8_t *plaintext,
+ uint8_t *ciphertext,
+ size_t size,
+ const uint8_t *iv,
+ size_t ivSize,
+ const uint8_t *aad,
+ size_t aadSize,
+ uint8_t *tag,
+ size_t tagSize)
+{
+ status_t status;
+ int32_t inputSize, outputSize;
+ uint8_t curOutputArrayIndex;
+ uint8_t curInputArrayIndex;
+ uint32_t inputWord;
+ uint32_t outputWord;
+
+ /* Input: AAD + Plain. */
+ aes_input_data_array_t inputDataArrays[2];
+ /* Output: AAD + Cipher + MIC. */
+ aes_output_data_array_t outputDataArrays[3];
+
+ if (NULL == tag)
+ {
+ tagSize = 0U;
+ }
+
+ status = AES_PrepareTagCcm(base, kAES_ModeEncryptCCM, size, iv, ivSize, aadSize, tagSize);
+
+ if (kStatus_Success != status)
+ {
+ return status;
+ }
+
+ /* Input: AAD + plain. */
+ inputDataArrays[0].data = aad;
+ inputDataArrays[0].len = aadSize;
+ inputDataArrays[1].data = plaintext;
+ inputDataArrays[1].len = size;
+ inputSize = aadSize + size;
+
+ /* Output: AAD + Chiper + MIC. */
+ outputDataArrays[0].data = NULL;
+ outputDataArrays[0].len = aadSize;
+ outputDataArrays[1].data = ciphertext;
+ outputDataArrays[1].len = size;
+ outputDataArrays[2].data = tag;
+ outputDataArrays[2].len = tagSize;
+ outputSize = aadSize + size + tagSize;
+
+ AES_Start(base);
+
+ curOutputArrayIndex = 0;
+ curInputArrayIndex = 0;
+
+ inputWord = AES_ReadWordFromArray(inputDataArrays, ARRAY_SIZE(inputDataArrays), &curInputArrayIndex);
+
+ while (outputSize > 0)
+ {
+ if (inputSize > 0)
+ {
+ /* Input FIFO not full, feed data. */
+ if (0U == (AES_GetStatus(base) & kAES_InputFIFOFullFlag))
+ {
+ AES_WriteData(base, inputWord);
+ inputWord = AES_ReadWordFromArray(inputDataArrays, ARRAY_SIZE(inputDataArrays), &curInputArrayIndex);
+ inputSize -= sizeof(uint32_t);
+ }
+ }
+
+ /* Output FIFO not empty, read data. */
+ if (0U == (AES_GetStatus(base) & kAES_OutputFIFOEmptyFlag))
+ {
+ outputWord = AES_ReadData(base);
+ AES_WriteWordToArray(outputDataArrays, ARRAY_SIZE(outputDataArrays), &curOutputArrayIndex, outputWord);
+ outputSize -= sizeof(uint32_t);
+ }
+ }
+
+ AES_Stop(base);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Decrypts AES and authenticates using CCM block mode.
+ *
+ * Decrypts AES and optionally authenticates using CCM block mode.
+ *
+ * param base AES peripheral base address
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text.
+ * param size Size of input and output data in bytes
+ * param iv Input initial vector
+ * param ivSize Size of the iv
+ * param aad Input additional authentication data
+ * param aadSize Input size in bytes of aad
+ * param tag Input hash tag to compare. Set to NULL to skip tag processing.
+ * param tagSize Input size of the tag to generate, in bytes. Must be 0,4,8, or 16.
+ * return Status from decrypt operation
+ */
+status_t AES_DecryptTagCcm(AES_Type *base,
+ const uint8_t *ciphertext,
+ uint8_t *plaintext,
+ size_t size,
+ const uint8_t *iv,
+ size_t ivSize,
+ const uint8_t *aad,
+ size_t aadSize,
+ const uint8_t *tag,
+ size_t tagSize)
+{
+ status_t status;
+ int32_t inputSize, outputSize;
+ uint8_t curOutputArrayIndex;
+ uint8_t curInputArrayIndex;
+ uint32_t inputWord;
+ uint32_t outputWord;
+
+ /* Input: AAD + Cipher + MIC. */
+ aes_input_data_array_t inputDataArrays[3];
+ /* Output: AAD + Plain. */
+ aes_output_data_array_t outputDataArrays[2];
+
+ if (NULL == tag)
+ {
+ tagSize = 0U;
+ }
+
+ status = AES_PrepareTagCcm(base, kAES_ModeDecryptCCM, size, iv, ivSize, aadSize, tagSize);
+
+ if (kStatus_Success != status)
+ {
+ return status;
+ }
+
+ /* Input: AAD + Chiper + MIC. */
+ inputDataArrays[0].data = aad;
+ inputDataArrays[0].len = aadSize;
+ inputDataArrays[1].data = ciphertext;
+ inputDataArrays[1].len = size;
+ inputDataArrays[2].data = tag;
+ inputDataArrays[2].len = tagSize;
+ inputSize = aadSize + size + tagSize;
+
+ /* Output: AAD + Plain. */
+ outputDataArrays[0].data = NULL;
+ outputDataArrays[0].len = aadSize;
+ outputDataArrays[1].data = plaintext;
+ outputDataArrays[1].len = (plaintext == NULL) ? 0 : size;
+ outputSize = aadSize + size;
+
+ AES_Start(base);
+
+ curOutputArrayIndex = 0;
+ curInputArrayIndex = 0;
+
+ inputWord = AES_ReadWordFromArray(inputDataArrays, ARRAY_SIZE(inputDataArrays), &curInputArrayIndex);
+
+ while (outputSize > 0)
+ {
+ if (0U != (AES_GetStatus(base) & kAES_Error2Flag))
+ {
+ status = kStatus_Fail;
+ break;
+ }
+
+ if (inputSize > 0)
+ {
+ /* Input FIFO not full, feed data. */
+ if (0U == (AES_GetStatus(base) & kAES_InputFIFOFullFlag))
+ {
+ AES_WriteData(base, inputWord);
+ inputWord = AES_ReadWordFromArray(inputDataArrays, ARRAY_SIZE(inputDataArrays), &curInputArrayIndex);
+ inputSize -= sizeof(uint32_t);
+ }
+ }
+
+ /* Output FIFO not empty, read data. */
+ if (0U == (AES_GetStatus(base) & kAES_OutputFIFOEmptyFlag))
+ {
+ outputWord = AES_ReadData(base);
+ AES_WriteWordToArray(outputDataArrays, ARRAY_SIZE(outputDataArrays), &curOutputArrayIndex, outputWord);
+ outputSize -= sizeof(uint32_t);
+ }
+ }
+
+ AES_Stop(base);
+
+ return status;
+}
+
+/*!
+ * brief Calculate the input stream MMO HASH value.
+ *
+ * param base AES peripheral base address
+ * param input Input stream.
+ * param size Length of the stream in bytes.
+ * param[out] hash Hash value of the input stream.
+ * return Status from HASH operation
+ */
+status_t AES_CalculateMMOHash(AES_Type *base, const uint8_t *input, size_t size, uint8_t hash[16])
+{
+ assert(NULL != input);
+ aes_word_byte_t dataToWrite;
+
+ AES_Reset(base);
+
+ AES_SetMode(base, kAES_ModeMMO);
+
+ AES_SetKey(base, hash, 16);
+
+ AES_SetMsgLen(base, size);
+
+ AES_EnableOutMsg(base, false);
+
+ AES_AppendMIC(base, true);
+
+ AES_SetInputVector(base, hash);
+
+ AES_Start(base);
+
+ /* Handle the 4-byte aligned part. */
+ while (size >= sizeof(uint32_t))
+ {
+ dataToWrite.word = *(const uint32_t *)input;
+ input += sizeof(uint32_t);
+ size -= sizeof(uint32_t);
+
+ /* Wait for input FIFO not full. */
+ while (0U != (AES_GetStatus(base) & kAES_InputFIFOFullFlag))
+ {
+ }
+
+ AES_WriteData(base, dataToWrite.word);
+ }
+
+ /* Handle the 4-byte unaligned part. */
+ if (size > 0U)
+ {
+ dataToWrite.word = 0U;
+
+ for (uint8_t i = 0; i < size; i++)
+ {
+ dataToWrite.bytes[i] = *input;
+ input++;
+ }
+
+ /* Wait for input FIFO not full. */
+ while (0U != (AES_GetStatus(base) & kAES_InputFIFOFullFlag))
+ {
+ }
+
+ AES_WriteData(base, dataToWrite.word);
+ }
+
+ /* Wait for proess complete. */
+ while (0U == (AES_GetStatus(base) & kAES_DoneFlag))
+ {
+ }
+
+ AES_Stop(base);
+
+ AES_GetOutputVector(base, hash);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Set the lock functions.
+ *
+ * param lockFunc Lock function.
+ * param unlockFunc Unlock function.
+ */
+void AES_SetLockFunc(aes_lock_func_t lockFunc, aes_unlock_func_t unlockFunc)
+{
+ s_aesLockFunc = lockFunc;
+ s_aesUnlockFunc = unlockFunc;
+}
+
+/*
+ * brief Encrypts AES using the ECB block mode.
+ *
+ * Encrypts AES using the ECB block mode.
+ *
+ * param base AES peripheral base address
+ * param key Input key to use for encryption or decryption
+ * param keySize Size of the input key, in bytes.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from encrypt operation
+ */
+status_t AES_EncryptEcbWithLock(
+ AES_Type *base, const uint8_t *key, size_t keySize, const uint8_t *plaintext, uint8_t *ciphertext, size_t size)
+{
+ status_t status = kStatus_Success;
+
+ if (s_aesLockFunc)
+ {
+ status = s_aesLockFunc();
+ }
+
+ if (kStatus_Success == status)
+ {
+ status = AES_SetKey(base, key, keySize);
+
+ if (kStatus_Success == status)
+ {
+ status = AES_EncryptEcb(base, plaintext, ciphertext, size);
+ }
+
+ if (s_aesUnlockFunc)
+ {
+ s_aesUnlockFunc();
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * brief Decrypts AES using the ECB block mode.
+ *
+ * Decrypts AES using the ECB block mode.
+ *
+ * param base AES peripheral base address
+ * param key Input key to use for encryption or decryption
+ * param keySize Size of the input key, in bytes.
+ * param ciphertext Input ciphertext to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * return Status from decrypt operation
+ */
+status_t AES_DecryptEcbWithLock(
+ AES_Type *base, const uint8_t *key, size_t keySize, const uint8_t *ciphertext, uint8_t *plaintext, size_t size)
+{
+ status_t status = kStatus_Success;
+
+ if (s_aesLockFunc)
+ {
+ status = s_aesLockFunc();
+ }
+
+ if (kStatus_Success == status)
+ {
+ status = AES_SetKey(base, key, keySize);
+
+ if (kStatus_Success == status)
+ {
+ status = AES_DecryptEcb(base, ciphertext, plaintext, size);
+ }
+
+ if (s_aesUnlockFunc)
+ {
+ s_aesUnlockFunc();
+ }
+ }
+
+ return status;
+}
+
+/*
+ * brief Encrypts AES using CBC block mode.
+ *
+ * param base AES peripheral base address
+ * param key Input key to use for encryption or decryption
+ * param keySize Size of the input key, in bytes.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * param[out] ov Output vector used for chained operation, could be NULL.
+ * return Status from encrypt operation
+ */
+status_t AES_EncryptCbcWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *plaintext,
+ uint8_t *ciphertext,
+ size_t size,
+ const uint8_t iv[AES_VECTOR_SIZE],
+ uint8_t ov[AES_VECTOR_SIZE])
+{
+ status_t status = kStatus_Success;
+
+ if (s_aesLockFunc)
+ {
+ status = s_aesLockFunc();
+ }
+
+ if (kStatus_Success == status)
+ {
+ status = AES_SetKey(base, key, keySize);
+
+ if (kStatus_Success == status)
+ {
+ status = AES_EncryptCbc(base, plaintext, ciphertext, size, iv, ov);
+ }
+
+ if (s_aesUnlockFunc)
+ {
+ s_aesUnlockFunc();
+ }
+ }
+
+ return status;
+}
+
+/*
+ * brief Decrypts AES using CBC block mode.
+ *
+ * param base AES peripheral base address
+ * param key Input key to use for encryption or decryption
+ * param keySize Size of the input key, in bytes.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text
+ * param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * param iv Input initial vector to combine with the first input block.
+ * param ov[out] Output vector used for chained operation, could be NULL.
+ * return Status from decrypt operation
+ */
+status_t AES_DecryptCbcWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *ciphertext,
+ uint8_t *plaintext,
+ size_t size,
+ const uint8_t iv[AES_VECTOR_SIZE],
+ uint8_t ov[AES_VECTOR_SIZE])
+{
+ status_t status = kStatus_Success;
+
+ if (s_aesLockFunc)
+ {
+ status = s_aesLockFunc();
+ }
+
+ if (kStatus_Success == status)
+ {
+ status = AES_SetKey(base, key, keySize);
+
+ if (kStatus_Success == status)
+ {
+ status = AES_DecryptCbc(base, ciphertext, plaintext, size, iv, ov);
+ }
+
+ if (s_aesUnlockFunc)
+ {
+ s_aesUnlockFunc();
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * brief Encrypts or decrypts AES using CTR block mode.
+ *
+ * Encrypts or decrypts AES using CTR block mode.
+ * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * For chained calls, the internal status are saved in the parameters: nonce, streamBlock,
+ * and offset. In this case, initialize nonce to the desired value, and initialize offset to 0
+ * before the first call, in the following calls, the nonce, streamBlock, and offset should be
+ * preserved.
+ *
+ * @note The streamBlock contains sensitive data, discard it after used.
+ *
+ * param base AES peripheral base address
+ * param key Input key to use for encryption or decryption
+ * param keySize Size of the input key, in bytes.
+ * param input Input data for CTR block mode
+ * param[out] output Output data for CTR block mode
+ * param size Size of input and output data in bytes
+ * param[in,out] nonce and counter(updates on return)
+ * param[out] streamBlock Saved block for chained CTR calls. NULL can be passed if chained calls are
+ * not used.
+ * param[out] offset Offset in streamBlock. NULL can be passed if chained calls
+ * are not used.
+ * return Status from crypt operation
+ */
+status_t AES_CryptCtrWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *input,
+ uint8_t *output,
+ size_t size,
+ uint8_t nonce[AES_BLOCK_SIZE],
+ uint8_t streamBlock[AES_BLOCK_SIZE],
+ size_t *offset)
+{
+ status_t status = kStatus_Success;
+
+ if (s_aesLockFunc)
+ {
+ status = s_aesLockFunc();
+ }
+
+ if (kStatus_Success == status)
+ {
+ status = AES_SetKey(base, key, keySize);
+
+ if (kStatus_Success == status)
+ {
+ status = AES_CryptCtr(base, input, output, size, nonce, streamBlock, offset);
+ }
+
+ if (s_aesUnlockFunc)
+ {
+ s_aesUnlockFunc();
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * brief Encrypts AES and tags using CCM block mode.
+ *
+ * Encrypts AES and optionally tags using CCM block mode.
+ *
+ * param base AES peripheral base address
+ * param key Input key to use for encryption or decryption
+ * param keySize Size of the input key, in bytes.
+ * param plaintext Input plain text to encrypt
+ * param[out] ciphertext Output cipher text.
+ * param size Size of input and output data in bytes
+ * param iv Input initial vector
+ * param ivSize Size of the iv
+ * param aad Input additional authentication data
+ * param aadSize Input size in bytes of aad.
+ * param[out] tag Output hash tag. Set to NULL to skip tag processing.
+ * param tagSize Input size of the tag to generate, in bytes. Must be 0,4,8, or 16.
+ * return Status from encrypt operation
+ */
+status_t AES_EncryptTagCcmWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *plaintext,
+ uint8_t *ciphertext,
+ size_t size,
+ const uint8_t *iv,
+ size_t ivSize,
+ const uint8_t *aad,
+ size_t aadSize,
+ uint8_t *tag,
+ size_t tagSize)
+{
+ status_t status = kStatus_Success;
+
+ if (s_aesLockFunc)
+ {
+ status = s_aesLockFunc();
+ }
+
+ if (kStatus_Success == status)
+ {
+ status = AES_SetKey(base, key, keySize);
+
+ if (kStatus_Success == status)
+ {
+ status = AES_EncryptTagCcm(base, plaintext, ciphertext, size, iv, ivSize, aad, aadSize, tag, tagSize);
+ }
+
+ if (s_aesUnlockFunc)
+ {
+ s_aesUnlockFunc();
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * brief Decrypts AES and authenticates using CCM block mode.
+ *
+ * Decrypts AES and optionally authenticates using CCM block mode.
+ *
+ * param base AES peripheral base address
+ * param key Input key to use for encryption or decryption
+ * param keySize Size of the input key, in bytes.
+ * param ciphertext Input cipher text to decrypt
+ * param[out] plaintext Output plain text.
+ * param size Size of input and output data in bytes
+ * param iv Input initial vector
+ * param ivSize Size of the iv
+ * param aad Input additional authentication data
+ * param aadSize Input size in bytes of aad
+ * param tag Input hash tag to compare. Set to NULL to skip tag processing.
+ * param tagSize Input size of the tag to generate, in bytes. Must be 0,4,8, or 16.
+ * return Status from decrypt operation
+ */
+status_t AES_DecryptTagCcmWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *ciphertext,
+ uint8_t *plaintext,
+ size_t size,
+ const uint8_t *iv,
+ size_t ivSize,
+ const uint8_t *aad,
+ size_t aadSize,
+ const uint8_t *tag,
+ size_t tagSize)
+{
+ status_t status = kStatus_Success;
+
+ if (s_aesLockFunc)
+ {
+ status = s_aesLockFunc();
+ }
+
+ if (kStatus_Success == status)
+ {
+ status = AES_SetKey(base, key, keySize);
+
+ if (kStatus_Success == status)
+ {
+ status = AES_DecryptTagCcm(base, ciphertext, plaintext, size, iv, ivSize, aad, aadSize, tag, tagSize);
+ }
+
+ if (s_aesUnlockFunc)
+ {
+ s_aesUnlockFunc();
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * brief Calculate the input stream MMO HASH value.
+ *
+ * param base AES peripheral base address
+ * param input Input stream.
+ * param size Length of the stream in bytes.
+ * param[out] hash Hash value of the input stream.
+ * return Status from HASH operation
+ */
+status_t AES_CalculateMMOHashWithLock(AES_Type *base, const uint8_t *input, size_t size, uint8_t hash[16])
+{
+ status_t status = kStatus_Success;
+
+ if (s_aesLockFunc)
+ {
+ status = s_aesLockFunc();
+ }
+
+ if (kStatus_Success == status)
+ {
+ status = AES_CalculateMMOHash(base, input, size, hash);
+
+ if (s_aesUnlockFunc)
+ {
+ s_aesUnlockFunc();
+ }
+ }
+
+ return status;
+}
diff --git a/drivers/mw320/aes/fsl_aes.h b/drivers/mw320/aes/fsl_aes.h
new file mode 100644
index 000000000..99d7d3c9b
--- /dev/null
+++ b/drivers/mw320/aes/fsl_aes.h
@@ -0,0 +1,838 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_AES_H_
+#define _FSL_AES_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup aes
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief Defines AES driver version. */
+#define FSL_AES_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+
+/*! AES block size in bytes */
+#define AES_BLOCK_SIZE 16U
+
+/*! AES Vector size in bytes */
+#define AES_VECTOR_SIZE 16U
+
+/*!
+ * @brief AES work mode definition.
+ */
+typedef enum
+{
+ kAES_ModeEncryptECB = AES_CTRL1_DECRYPT(0) | AES_CTRL1_MODE(0), /*!< ECB encrypt */
+ kAES_ModeDecryptECB = AES_CTRL1_DECRYPT(1) | AES_CTRL1_MODE(0), /*!< ECB decrypt */
+ kAES_ModeEncryptCBC = AES_CTRL1_DECRYPT(0) | AES_CTRL1_MODE(1), /*!< CBC encrypt */
+ kAES_ModeDecryptCBC = AES_CTRL1_DECRYPT(1) | AES_CTRL1_MODE(1), /*!< CBC decrypt */
+ kAES_ModeCTR = AES_CTRL1_DECRYPT(0) | AES_CTRL1_MODE(2), /*!< CTR */
+ kAES_ModeEncryptCCM = AES_CTRL1_DECRYPT(0) | AES_CTRL1_MODE(5), /*!< CCM encrypt */
+ kAES_ModeDecryptCCM = AES_CTRL1_DECRYPT(1) | AES_CTRL1_MODE(5), /*!< CCM decrypt */
+ kAES_ModeMMO = AES_CTRL1_DECRYPT(0) | AES_CTRL1_MODE(6), /*!< AES mode: MMO */
+ kAES_ModeBYPASS = AES_CTRL1_DECRYPT(0) | AES_CTRL1_MODE(7), /*!< AES mode: Bypass */
+} aes_mode_t;
+
+/*!
+ * @brief AES FIFO.
+ */
+typedef enum
+{
+ kAES_InputFIFO = AES_CTRL1_IF_CLR_MASK, /*!< Input FIFO. */
+ kAES_OutputFIFO = AES_CTRL1_OF_CLR_MASK, /*!< Output FIFO. */
+ kAES_AllFIFO = AES_CTRL1_OF_CLR_MASK | AES_CTRL1_IF_CLR_MASK, /*!< Input and output FIFO. */
+} aes_fifo_t;
+
+/*!
+ * @brief AES key size type definition
+ */
+typedef enum
+{
+ kAES_KeyBytes16 = 0, /*!< AES key size select: 16 bytes */
+ kAES_KeyBytes32 = 1, /*!< AES key size select: 32 bytes */
+ kAES_KeyBytes24 = 2, /*!< AES key size select: 24 bytes */
+} aes_keysize_t;
+
+/*!
+ * @brief AES MIC size type definition
+ */
+typedef enum
+{
+ kAES_MicBytes0 = 0, /*!< AES MIC length: 0 bytes */
+ kAES_MicBytes4 = 1, /*!< AES MIC length: 4 bytes */
+ kAES_MicBytes8 = 2, /*!< AES MIC length: 8 bytes */
+ kAES_MicBytes16 = 3, /*!< AES MIC length: 16 bytes */
+} aes_miclen_t;
+
+/*!
+ * @brief AES interrupt type definition
+ * @anchor aes_interrupts
+ */
+typedef enum
+{
+ kAES_InterruptOutputFIFOEmpty, /*!< AES output FIFO empty int flag */
+ kAES_InterruptInputFIFOFull, /*!< AES input FIFO full int flag */
+ kAES_InterruptDone, /*!< AES done int flag */
+} aes_interrupt_t;
+
+/*!
+ * @brief AES status type definition
+ * @anchor aes_status_flags
+ */
+enum
+{
+ kAES_OutputFIFOEmptyFlag = AES_STATUS_OF_EMPTY_MASK, /*!< AES output FIFO empty flag */
+ kAES_InputFIFOFullFlag = AES_STATUS_IF_FULL_MASK, /*!< AES input FIFO full flag */
+ kAES_OutputFIFOReadyFlag = AES_STATUS_OF_RDY_MASK, /*!< AES output FIFO can be read flag */
+ kAES_DoneFlag = AES_STATUS_DONE_MASK, /*!< AES done flag */
+ kAES_Error0Flag = AES_STATUS_STATUS(1U), /*!< Input stream size is less than 16 bytes in CBC&CTR mode */
+ kAES_Error1Flag = AES_STATUS_STATUS(2U), /*!< Data is more than 2^13-1 bytes in MMO mode
+ Data is not multiple of 16 bytes in ECB mode*/
+ kAES_Error2Flag = AES_STATUS_STATUS(4U), /*!< MIC mismatch during decryption in CCM* mode */
+};
+
+/*! @brief AES lock function. */
+typedef status_t (*aes_lock_func_t)(void);
+
+/*! @brief AES lock function. */
+typedef void (*aes_unlock_func_t)(void);
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name Initialization Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Initializes AES module.
+ *
+ * Initialize the module, reset the module and set the registers to default status.
+ *
+ * @param base AES peripheral base address.
+ */
+void AES_Init(AES_Type *base);
+
+/*!
+ * @brief Deinitializes AES module.
+ *
+ * Deinitialize the module and reset the module.
+ *
+ * @param base AES peripheral base address.
+ */
+void AES_Deinit(AES_Type *base);
+
+/*!
+ * @brief Reset AES module.
+ *
+ * Reset the module. This function only resets the AES module internal status,
+ * but does not reset the register configurations.
+ *
+ * @param base AES peripheral base address.
+ */
+void AES_Reset(AES_Type *base);
+
+/* @} */
+
+/*!
+ * @name Module configuration
+ * @{
+ */
+
+/*!
+ * @brief Set AES module work mode.
+ *
+ * @param base AES peripheral base address.
+ * @param mode AES work mode.
+ */
+static inline void AES_SetMode(AES_Type *base, aes_mode_t mode)
+{
+ base->CTRL1 = (base->CTRL1 & ~(AES_CTRL1_MODE_MASK | AES_CTRL1_DECRYPT_MASK)) | (uint32_t)mode;
+}
+
+/*!
+ * @brief Set the AES input vector.
+ *
+ * @param base AES peripheral base address.
+ * @param inputVector Input vector.
+ */
+void AES_SetInputVector(AES_Type *base, const uint8_t inputVector[AES_VECTOR_SIZE]);
+
+/*!
+ * @brief Get the AES output vector.
+ *
+ * @param base AES peripheral base address.
+ * @param outputVector Array to save the output vector.
+ */
+void AES_GetOutputVector(AES_Type *base, uint8_t outputVector[AES_VECTOR_SIZE]);
+
+/*!
+ * @brief Set the input data length.
+ *
+ * @param base AES peripheral base address.
+ * @param msgLen Length of the input data in byte.
+ */
+static inline void AES_SetMsgLen(AES_Type *base, uint32_t msgLen)
+{
+ base->MSTR_LEN = msgLen;
+}
+
+/*!
+ * @brief Set the additional authentication data length in CCM mode.
+ *
+ * @param base AES peripheral base address.
+ * @param len Length in byte.
+ */
+static inline void AES_SetAadLen(AES_Type *base, uint32_t len)
+{
+ base->ASTR_LEN = len;
+}
+
+/*!
+ * @brief Set the CTR mode counter modular.
+ *
+ * @param base AES peripheral base address.
+ * @param modular The modular set to AES register. Valid range is 0~128.
+ * When pass in 0~15, the CTR counter modular is 2^128, when pass in other
+ * values, the CTR counter modular is 2^input value.
+ */
+static inline void AES_SetCTRCountModular(AES_Type *base, uint8_t modular)
+{
+ base->CTRL1 = (base->CTRL1 & ~AES_CTRL1_CTR_MOD_MASK) | AES_CTRL1_CTR_MOD(modular);
+}
+
+/*!
+ * @brief Enable or disable the output stream to output FIFO.
+ *
+ * @param base AES peripheral base address.
+ * @param enable Use \b true to forward output stream to output FIFO, use \b false
+ * to block output stream from output FIFO.
+ */
+static inline void AES_EnableOutMsg(AES_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CTRL1 |= AES_CTRL1_OUT_MSG_MASK;
+ }
+ else
+ {
+ base->CTRL1 &= ~AES_CTRL1_OUT_MSG_MASK;
+ }
+}
+
+/*!
+ * @brief Enable or disable DMA.
+ *
+ * @param base AES peripheral base address.
+ * @param enable Use \b true to enable DMA, use \b false to disable DMA.
+ */
+static inline void AES_EnableDma(AES_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CTRL1 |= AES_CTRL1_DMA_EN_MASK;
+ }
+ else
+ {
+ base->CTRL1 &= ~AES_CTRL1_DMA_EN_MASK;
+ }
+}
+
+/*!
+ * @brief Append MIC/HASH output or not.
+ *
+ * When enabled in CCM mode decryption, the MIC is append at the end of output stream.
+ * When enabled in MMO mode, the HASH is append at the end of output stream.
+ *
+ * @param base AES peripheral base address.
+ * @param append Use \b true to append, otherwise use \b false.
+ */
+static inline void AES_AppendMIC(AES_Type *base, bool append)
+{
+ if (append)
+ {
+ base->CTRL1 |= AES_CTRL1_OUT_MIC_MASK;
+ }
+ else
+ {
+ base->CTRL1 &= ~AES_CTRL1_OUT_MIC_MASK;
+ }
+}
+
+/*!
+ * @brief Set the MIC length in CCM mode.
+ *
+ * @param base AES peripheral base address.
+ * @param len MIC length.
+ */
+static inline void AES_SetMICLength(AES_Type *base, aes_miclen_t len)
+{
+ base->CTRL1 = (base->CTRL1 & ~AES_CTRL1_MIC_LEN_MASK) | AES_CTRL1_MIC_LEN(len);
+}
+
+/*!
+ * @brief Read AES CCM MIC output value.
+ *
+ * @param base AES peripheral base address.
+ * @param micData The memory to save the MIC data.
+ * @param len Length of \p micData in word, the valid range is 1~4.
+ * @retval kStatus_InvalidArgument The required length is wrong.
+ * @retval kStatus_Success Get MIC successfully.
+ */
+status_t AES_ReadMIC(AES_Type *base, uint32_t *micData, uint8_t len);
+
+/*!
+ * @brief Clear AES input or output FIFO.
+ *
+ * @param base AES peripheral base address.
+ * @param fifo The FIFO to clear.
+ */
+void AES_ClearFIFO(AES_Type *base, aes_fifo_t fifo);
+
+/*!
+ * @brief Start the AES calculation.
+ *
+ * Start the calculation based on configurations.
+ *
+ * @param base AES peripheral base address.
+ */
+static inline void AES_Start(AES_Type *base)
+{
+ base->CTRL1 |= AES_CTRL1_START_MASK;
+}
+
+/*!
+ * @brief Stop the AES calculation.
+ *
+ * Stop the calculation.
+ *
+ * @param base AES peripheral base address.
+ */
+static inline void AES_Stop(AES_Type *base)
+{
+ base->CTRL1 &= ~AES_CTRL1_START_MASK;
+}
+
+/*!
+ * @brief Write data to AES input FIFO.
+ *
+ * @param base AES peripheral base address.
+ * @param data Data written to AES FIFO.
+ */
+static inline void AES_WriteData(AES_Type *base, uint32_t data)
+{
+ base->STR_IN = data;
+}
+
+/*!
+ * @brief Read data from AES output FIFO.
+ *
+ * @param base AES peripheral base address.
+ */
+static inline uint32_t AES_ReadData(AES_Type *base)
+{
+ return base->STR_OUT;
+}
+
+/* @} */
+
+/*!
+ * @name Interrupt and status
+ * @{
+ */
+
+/*!
+ * @brief Get the AES status.
+ *
+ * @param base AES peripheral base address.
+ * @return AES status, logical OR'ed value of @ref aes_status_flags.
+ */
+static inline uint32_t AES_GetStatus(AES_Type *base)
+{
+ return base->STATUS;
+}
+
+/*!
+ * @brief Enable AES interrupts.
+ *
+ * @param base AES peripheral base address.
+ * @param interrupts The interrupts to enable, logical OR'ed value of @ref aes_interrupts.
+ */
+static inline void AES_EnableInterrupts(AES_Type *base, uint32_t interrupts)
+{
+ base->IMR &= ~interrupts;
+}
+
+/*!
+ * @brief Disable AES interrupts.
+ *
+ * @param base AES peripheral base address.
+ * @param interrupts The interrupts to disable, logical OR'ed value of @ref aes_interrupts.
+ */
+static inline void AES_DisableInterrupts(AES_Type *base, uint32_t interrupts)
+{
+ base->IMR |= interrupts;
+}
+
+/*!
+ * @brief Get AES interrupt status.
+ *
+ * @param base AES peripheral base address.
+ * @return The interrupt pending status, logical OR'ed value of @ref aes_interrupts.
+ */
+static inline uint32_t AES_GetInterruptStatus(AES_Type *base)
+{
+ return base->ISR;
+}
+
+/*!
+ * @brief Clear AES interrupt status.
+ *
+ * @param base AES peripheral base address.
+ * @param interrupts The interrupt pending status to clear, logical OR'ed value of @ref aes_interrupts.
+ */
+static inline void AES_ClearInterruptStatus(AES_Type *base, uint32_t interrupts)
+{
+ base->ICR = interrupts;
+}
+
+/*!
+ * @brief Get AES raw interrupt status.
+ *
+ * This function is similar with @ref AES_GetInterruptStatus, the difference is
+ * the raw interrupt status is not affected by interrupt enable status.
+ *
+ * @param base AES peripheral base address.
+ * @return The raw interrupt pending status, logical OR'ed value of @ref aes_interrupts.
+ */
+static inline uint32_t AES_GetRawInterruptStatus(AES_Type *base)
+{
+ return base->IRSR;
+}
+
+/* @} */
+
+/*!
+ * @name High level interface
+ * @{
+ */
+
+/*!
+ * @brief Sets AES key.
+ *
+ * Sets AES key.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes. Must be 16, 24, or 32.
+ * @return Status from Set Key operation
+ */
+status_t AES_SetKey(AES_Type *base, const uint8_t *key, size_t keySize);
+
+/*!
+ * @brief Encrypts AES using the ECB block mode.
+ *
+ * Encrypts AES using the ECB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptEcb(AES_Type *base, const uint8_t *plaintext, uint8_t *ciphertext, size_t size);
+
+/*!
+ * @brief Decrypts AES using the ECB block mode.
+ *
+ * Decrypts AES using the ECB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptEcb(AES_Type *base, const uint8_t *ciphertext, uint8_t *plaintext, size_t size);
+
+/*!
+ * @brief Encrypts AES using CBC block mode.
+ *
+ * @param base AES peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @param[out] ov Output vector used for chained operation, could be NULL.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptCbc(AES_Type *base,
+ const uint8_t *plaintext,
+ uint8_t *ciphertext,
+ size_t size,
+ const uint8_t iv[AES_VECTOR_SIZE],
+ uint8_t ov[AES_VECTOR_SIZE]);
+
+/*!
+ * @brief Decrypts AES using CBC block mode.
+ *
+ * @param base AES peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @param[out] ov Output vector used for chained operation, could be NULL.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptCbc(AES_Type *base,
+ const uint8_t *ciphertext,
+ uint8_t *plaintext,
+ size_t size,
+ const uint8_t iv[AES_VECTOR_SIZE],
+ uint8_t ov[AES_VECTOR_SIZE]);
+
+/*!
+ * @brief Encrypts or decrypts AES using CTR block mode.
+ *
+ * Encrypts or decrypts AES using CTR block mode.
+ * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * For chained calls, the internal status are saved in the parameters: @p nonce, @p streamBlock,
+ * and @p offset. In this case, initialize @p nonce to the desired value, and initialize @p offset to 0
+ * before the first call, in the following calls, the @p nonce, @p streamBlock, and @p offset should be
+ * preserved.
+ *
+ * @note The @p streamBlock contains sensitive data, discard it after used.
+ *
+ * @param base AES peripheral base address
+ * @param input Input data for CTR block mode
+ * @param[out] output Output data for CTR block mode
+ * @param size Size of input and output data in bytes
+ * @param[in,out] nonce and counter(updates on return)
+ * @param[out] streamBlock Saved block for chained CTR calls. NULL can be passed if chained calls are
+ * not used.
+ * @param[out] offset Offset in @p streamBlock. NULL can be passed if chained calls
+ * are not used.
+ * @return Status from crypt operation
+ */
+status_t AES_CryptCtr(AES_Type *base,
+ const uint8_t *input,
+ uint8_t *output,
+ size_t size,
+ uint8_t nonce[AES_BLOCK_SIZE],
+ uint8_t streamBlock[AES_BLOCK_SIZE],
+ size_t *offset);
+
+/*!
+ * @brief Encrypts AES and tags using CCM block mode.
+ *
+ * Encrypts AES and optionally tags using CCM block mode.
+ *
+ * @param base AES peripheral base address
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text.
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector
+ * @param ivSize Size of the @p iv
+ * @param aad Input additional authentication data
+ * @param aadSize Input size in bytes of @p aad.
+ * @param[out] tag Output hash tag. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag to generate, in bytes. Must be 0,4,8, or 16.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptTagCcm(AES_Type *base,
+ const uint8_t *plaintext,
+ uint8_t *ciphertext,
+ size_t size,
+ const uint8_t *iv,
+ size_t ivSize,
+ const uint8_t *aad,
+ size_t aadSize,
+ uint8_t *tag,
+ size_t tagSize);
+
+/*!
+ * @brief Decrypts AES and authenticates using CCM block mode.
+ *
+ * Decrypts AES and optionally authenticates using CCM block mode.
+ *
+ * @param base AES peripheral base address
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text.
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector
+ * @param ivSize Size of the @p iv
+ * @param aad Input additional authentication data
+ * @param aadSize Input size in bytes of @p aad
+ * @param tag Input hash tag to compare. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag to generate, in bytes. Must be 0,4,8, or 16.
+ * @retval kStatus_Success Calculation successed.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ * @retval kStatus_Fail Tag does not match.
+ */
+status_t AES_DecryptTagCcm(AES_Type *base,
+ const uint8_t *ciphertext,
+ uint8_t *plaintext,
+ size_t size,
+ const uint8_t *iv,
+ size_t ivSize,
+ const uint8_t *aad,
+ size_t aadSize,
+ const uint8_t *tag,
+ size_t tagSize);
+
+/*!
+ * @brief Calculate the input stream MMO HASH value.
+ *
+ * @param base AES peripheral base address
+ * @param input Input stream.
+ * @param size Length of the stream in bytes.
+ * @param[out] hash Hash value of the input stream.
+ * @return Status from HASH operation
+ */
+status_t AES_CalculateMMOHash(AES_Type *base, const uint8_t *input, size_t size, uint8_t hash[16]);
+
+/* @} */
+
+/*!
+ * @name Function with lock
+ *
+ * AES module might be used by multiple sofware components, to make sure the
+ * on-going proess is not broken by the call from another components, lock is
+ * used to protect the operation.
+ *
+ * To use the lock, set the lock function with @ref AES_SetLockFunc, then when
+ * calling the APIs with suffix WithLock, the lock function will be called by
+ * AES driver.
+ *
+ * @{
+ */
+
+/*!
+ * @brief Set the lock functions.
+ *
+ * @param lockFunc Lock function.
+ * @param unlockFunc Unlock function.
+ */
+void AES_SetLockFunc(aes_lock_func_t lockFunc, aes_unlock_func_t unlockFunc);
+
+/*!
+ * @brief Encrypts AES using the ECB block mode.
+ *
+ * Encrypts AES using the ECB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptEcbWithLock(
+ AES_Type *base, const uint8_t *key, size_t keySize, const uint8_t *plaintext, uint8_t *ciphertext, size_t size);
+
+/*!
+ * @brief Decrypts AES using the ECB block mode.
+ *
+ * Decrypts AES using the ECB block mode.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes.
+ * @param ciphertext Input ciphertext to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptEcbWithLock(
+ AES_Type *base, const uint8_t *key, size_t keySize, const uint8_t *ciphertext, uint8_t *plaintext, size_t size);
+
+/*!
+ * @brief Encrypts AES using CBC block mode.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @param[out] ov Output vector used for chained operation, could be NULL.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptCbcWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *plaintext,
+ uint8_t *ciphertext,
+ size_t size,
+ const uint8_t iv[AES_VECTOR_SIZE],
+ uint8_t ov[AES_VECTOR_SIZE]);
+
+/*!
+ * @brief Decrypts AES using CBC block mode.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @param[out] ov Output vector used for chained operation, could be NULL.
+ * @return Status from decrypt operation
+ */
+status_t AES_DecryptCbcWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *ciphertext,
+ uint8_t *plaintext,
+ size_t size,
+ const uint8_t iv[AES_VECTOR_SIZE],
+ uint8_t ov[AES_VECTOR_SIZE]);
+
+/*!
+ * @brief Encrypts or decrypts AES using CTR block mode.
+ *
+ * Encrypts or decrypts AES using CTR block mode.
+ * AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * For chained calls, the internal status are saved in the parameters: @p nonce, @p streamBlock,
+ * and @p offset. In this case, initialize @p nonce to the desired value, and initialize @p offset to 0
+ * before the first call, in the following calls, the @p nonce, @p streamBlock, and @p offset should be
+ * preserved.
+ *
+ * @note The @p streamBlock contains sensitive data, discard it after used.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes.
+ * @param input Input data for CTR block mode
+ * @param[out] output Output data for CTR block mode
+ * @param size Size of input and output data in bytes
+ * @param[in,out] nonce and counter(updates on return)
+ * @param[out] streamBlock Saved block for chained CTR calls. NULL can be passed if chained calls are
+ * not used.
+ * @param[out] offset Offset in @p streamBlock. NULL can be passed if chained calls
+ * are not used.
+ * @return Status from crypt operation
+ */
+status_t AES_CryptCtrWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *input,
+ uint8_t *output,
+ size_t size,
+ uint8_t nonce[AES_BLOCK_SIZE],
+ uint8_t streamBlock[AES_BLOCK_SIZE],
+ size_t *offset);
+
+/*!
+ * @brief Encrypts AES and tags using CCM block mode.
+ *
+ * Encrypts AES and optionally tags using CCM block mode.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text.
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector
+ * @param ivSize Size of the @p iv
+ * @param aad Input additional authentication data
+ * @param aadSize Input size in bytes of @p aad.
+ * @param[out] tag Output hash tag. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag to generate, in bytes. Must be 0,4,8, or 16.
+ * @return Status from encrypt operation
+ */
+status_t AES_EncryptTagCcmWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *plaintext,
+ uint8_t *ciphertext,
+ size_t size,
+ const uint8_t *iv,
+ size_t ivSize,
+ const uint8_t *aad,
+ size_t aadSize,
+ uint8_t *tag,
+ size_t tagSize);
+
+/*!
+ * @brief Decrypts AES and authenticates using CCM block mode.
+ *
+ * Decrypts AES and optionally authenticates using CCM block mode.
+ *
+ * @param base AES peripheral base address
+ * @param key Input key to use for encryption or decryption
+ * @param keySize Size of the input key, in bytes.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plain text.
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector
+ * @param ivSize Size of the @p iv
+ * @param aad Input additional authentication data
+ * @param aadSize Input size in bytes of @p aad
+ * @param tag Input hash tag to compare. Set to NULL to skip tag processing.
+ * @param tagSize Input size of the tag to generate, in bytes. Must be 0,4,8, or 16.
+ * @retval kStatus_Success Calculation successed.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ * @retval kStatus_Fail Tag does not match.
+ */
+status_t AES_DecryptTagCcmWithLock(AES_Type *base,
+ const uint8_t *key,
+ size_t keySize,
+ const uint8_t *ciphertext,
+ uint8_t *plaintext,
+ size_t size,
+ const uint8_t *iv,
+ size_t ivSize,
+ const uint8_t *aad,
+ size_t aadSize,
+ const uint8_t *tag,
+ size_t tagSize);
+
+/*!
+ * @brief Calculate the input stream MMO HASH value.
+ *
+ * @param base AES peripheral base address
+ * @param input Input stream.
+ * @param size Length of the stream in bytes.
+ * @param[out] hash Hash value of the input stream.
+ * @return Status from HASH operation
+ */
+status_t AES_CalculateMMOHashWithLock(AES_Type *base, const uint8_t *input, size_t size, uint8_t hash[16]);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/ /* end of group aes */
+
+#endif /* _FSL_AES_H_ */
diff --git a/drivers/mw320/crc/driver_mw_crc.cmake b/drivers/mw320/crc/driver_mw_crc.cmake
new file mode 100644
index 000000000..171b01502
--- /dev/null
+++ b/drivers/mw320/crc/driver_mw_crc.cmake
@@ -0,0 +1,14 @@
+#Description: MW_CRC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_crc component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_crc.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/crc/fsl_crc.c b/drivers/mw320/crc/fsl_crc.c
new file mode 100644
index 000000000..a2c927883
--- /dev/null
+++ b/drivers/mw320/crc/fsl_crc.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_crc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mw_crc"
+
+#endif
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Initializes CRC module.
+ *
+ * Call this function to initialize the CRC module.
+ *
+ * param base CRC peripheral base address
+ */
+void CRC_Init(CRC_Type *base)
+{
+ base->CTRL = 0U;
+ base->ICR = CRC_ICR_CLEAR_MASK;
+}
+
+/*!
+ * brief Disable the interrupt and clear all the interrupts
+ * param base RTC peripheral base address
+ */
+void CRC_Deinit(CRC_Type *base)
+{
+ base->CTRL = 0x0;
+ base->ICR = CRC_ICR_CLEAR_MASK;
+}
+
+/*!
+ * brief Calculate the CRC value for input data block.
+ *
+ * param base CRC peripheral base address.
+ * param dataStr input data stream.
+ * param dataLen data length in byte.
+ * return CRC calculation result.
+ */
+uint32_t CRC_Calculate(CRC_Type *base, const uint8_t *dataStr, uint32_t dataLen)
+{
+ uint32_t cnt;
+
+ uint32_t divisor, tail;
+
+ CRC_Enable(base, true);
+
+ /* set data length */
+ base->STREAM_LEN_M1 = dataLen - 1;
+
+ /* Padding first and copy data in */
+ divisor = dataLen / 4;
+ tail = dataLen % 4;
+
+ switch (tail)
+ {
+ case 1:
+ base->STREAM_IN = (((uint32_t)dataStr[0]) << 24);
+ break;
+
+ case 2:
+ base->STREAM_IN = ((((uint32_t)dataStr[0]) << 16) | (((uint32_t)dataStr[1]) << 24));
+ break;
+
+ case 3:
+ base->STREAM_IN =
+ ((((uint32_t)dataStr[0]) << 8) | (((uint32_t)dataStr[1]) << 16) | (((uint32_t)dataStr[2]) << 24));
+ break;
+
+ default:
+ break;
+ }
+
+ /* compose last data from byte to word and copy data in */
+ for (cnt = 0; cnt < divisor; cnt++)
+ {
+ base->STREAM_IN =
+ (((uint32_t)dataStr[4 * cnt + tail]) | (((uint32_t)dataStr[4 * cnt + tail + 1]) << 8) |
+ (((uint32_t)dataStr[4 * cnt + tail + 2]) << 16) | (((uint32_t)dataStr[4 * cnt + tail + 3]) << 24));
+ }
+ /* wait for the result */
+ while (base->IRSR == 0)
+ ;
+
+ /* clear interrupt flag */
+ CRC_ClearInterruptStatus(base);
+
+ /* return the result */
+ return base->RESULT;
+}
diff --git a/drivers/mw320/crc/fsl_crc.h b/drivers/mw320/crc/fsl_crc.h
new file mode 100644
index 000000000..07e7efb1d
--- /dev/null
+++ b/drivers/mw320/crc/fsl_crc.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_CRC_H_
+#define _FSL_CRC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup crc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief CRC mode type definition */
+typedef enum _crc_mode
+{
+ kCRC_16BitsCcitt = 0U, /*!< CRC mode: CRC-16-CCITT */
+ kCRC_16BitsIbm = 1U, /*!< CRC mode: CRC-16-IBM */
+ kCRC_16BitsT10Dif = 2U, /*!< CRC mode: CRC-16-T10-DIF */
+ kCRC_32BitsIeee = 3U, /*!< CRC mode: CRC-32-IEEE */
+ kCRC_16BitsDnp = 4U, /*!< CRC mode: CRC-16-DNP */
+} crc_mode_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Initializes CRC module.
+ *
+ * Call this function to initialize the CRC module.
+ *
+ * @param base CRC peripheral base address
+ */
+void CRC_Init(CRC_Type *base);
+
+/*!
+ * @brief Disable the interrupt and clear all the interrupts
+ *
+ * @param base CRC peripheral base address
+ */
+void CRC_Deinit(CRC_Type *base);
+
+/* @} */
+
+/*!
+ * @name CRC Operation Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Set CRC mode.
+ *
+ * @param base CRC peripheral base address.
+ * @param crcMode The CRC work mode to set.
+ */
+static inline void CRC_SetMode(CRC_Type *base, crc_mode_t crcMode)
+{
+ /* set CRC mode */
+ base->CTRL = CRC_CTRL_MODE(crcMode);
+}
+
+/*!
+ * @brief Enable the CRC module.
+ *
+ * This function enable/disables the CRC.
+ *
+ * @param base CRC peripheral base address.
+ * @param enable Use true to enable, false to disable.
+ */
+static inline void CRC_Enable(CRC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->CTRL |= CRC_CTRL_ENABLE_MASK;
+ }
+ else
+ {
+ base->CTRL &= ~CRC_CTRL_ENABLE_MASK;
+ }
+}
+
+/*!
+ * @brief Feed data in CRC stream.
+ *
+ * @param base CRC peripheral address.
+ * @param data input data.
+ */
+static inline void CRC_FeedData(CRC_Type *base, uint32_t data)
+{
+ /* feed data in CRC stream */
+ base->STREAM_IN = data;
+}
+
+/*!
+ * @brief Set CRC stream length.
+ *
+ * @param base CRC peripheral address.
+ * @param strLen stream length in byte.
+ */
+static inline void CRC_SetStreamLen(CRC_Type *base, uint32_t strLen)
+{
+ /* set CRC stream length */
+ base->STREAM_LEN_M1 = strLen - 1;
+}
+
+/*!
+ * @brief Get CRC result.
+ *
+ * @param base CRC peripheral base address.
+ *
+ * @return CRC calculation result.
+ */
+static inline uint32_t CRC_GetResult(CRC_Type *base)
+{
+ /* return CRC result value */
+ return base->RESULT;
+}
+
+/*!
+ * @brief Calculate the CRC value for input data block.
+ *
+ * @param base CRC peripheral base address.
+ * @param dataStr input data stream.
+ * @param dataLen data length in byte.
+ *
+ * @return CRC calculation result.
+ */
+uint32_t CRC_Calculate(CRC_Type *base, const uint8_t *dataStr, uint32_t dataLen);
+
+/* @} */
+
+/*!
+ * @name Interrupt Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enable the CRC Interrupt.
+ *
+ * @param base CRC peripheral base address.
+ */
+static inline void CRC_EnableInterrupt(CRC_Type *base)
+{
+ base->IMR |= CRC_IMR_MASK_MASK;
+}
+
+/*!
+ * @brief Disable the CRC Interrupt.
+ *
+ * @param base CRC peripheral base address.
+ */
+static inline void CRC_DisableInterrupt(CRC_Type *base)
+{
+ base->IMR &= ~CRC_IMR_MASK_MASK;
+}
+
+/*!
+ * brief Clears interrupt flags.
+ *
+ * @param base CRC peripheral base address.
+ */
+static inline void CRC_ClearInterruptStatus(CRC_Type *base)
+{
+ base->ICR = CRC_ICR_CLEAR_MASK;
+}
+
+/*!
+ * @brief Get base interrupt status.
+ *
+ * @param base CRC peripheral base address.
+ *
+ * @return true if interrupt flag is asserted, else false.
+ *
+ */
+static inline bool CRC_GetInterruptStatus(CRC_Type *base)
+{
+ return ((base->ISR & CRC_ISR_STATUS_MASK) != 0U);
+}
+
+/*!
+ * @brief Get CRC raw interrupt status.
+ *
+ * This function is similar with @ref CRC_GetInterruptStatus, the only
+ * difference is, the raw interrupt status is not affected by interrupt
+ * enable status.
+ *
+ * @param base CRC peripheral base address.
+ *
+ * @return true if CRC status is asserted, else false.
+ */
+static inline bool CRC_GetRawInterruptStatus(CRC_Type *base)
+{
+ return ((base->IRSR & CRC_IRSR_STATUS_RAW_0_MASK) != 0U);
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_CRC_H_ */
diff --git a/drivers/mw320/dac/driver_mw_dac.cmake b/drivers/mw320/dac/driver_mw_dac.cmake
new file mode 100644
index 000000000..b0b13b0b9
--- /dev/null
+++ b/drivers/mw320/dac/driver_mw_dac.cmake
@@ -0,0 +1,14 @@
+#Description: MW_DAC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_dac component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_dac.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/dac/fsl_dac.c b/drivers/mw320/dac/fsl_dac.c
new file mode 100644
index 000000000..2bdba3ccd
--- /dev/null
+++ b/drivers/mw320/dac/fsl_dac.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_dac.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dac"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static uint32_t DAC_GetInstance(DAC_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static DAC_Type *const s_dacBases[] = DAC_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to DAC clocks for each instance. */
+static const clock_ip_name_t s_dacClocks[] = DAC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*!
+ * @brief Get the DAC peripheral instance
+ *
+ * @param base DAC peripheral base address.
+ * @return The instance of input DAC peripheral base address.
+ */
+static uint32_t DAC_GetInstance(DAC_Type *base)
+{
+ uint32_t instance;
+ uint32_t dacArrayCount = (sizeof(s_dacBases) / sizeof(s_dacBases[0]));
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < dacArrayCount; instance++)
+ {
+ if (s_dacBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < dacArrayCount);
+
+ return instance;
+}
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*!
+ * brief Initializes DAC module, including set reference voltage source, set conversion range, and set output voltage
+ * range.
+ *
+ * param base DAC peripheral base address.
+ * param config Pointer to the structure which in type of dac_config_t.
+ */
+void DAC_Init(DAC_Type *base, const dac_config_t *config)
+{
+ assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate the DAC clock*/
+ (void)CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ base->CLK |= DAC_CLK_SOFT_CLK_RST_MASK;
+ for (uint8_t i = 0U; i < 10U; i++)
+ {
+ __NOP();
+ }
+ base->CLK &= ~DAC_CLK_SOFT_CLK_RST_MASK;
+
+ base->CLK = (base->CLK & ~DAC_CLK_CLK_CTRL_MASK) | DAC_CLK_CLK_CTRL(config->conversionRate);
+
+ base->CTRL = (base->CTRL & (~DAC_CTRL_REF_SEL_MASK)) | DAC_CTRL_REF_SEL(config->refSource);
+
+ base->ACTRL = (base->ACTRL & (~DAC_ACTRL_A_RANGE_MASK)) | DAC_ACTRL_A_RANGE(config->rangeSelect);
+}
+
+/*!
+ * brief Gets the default configurations of DAC module.
+ *
+ * code
+ * config->conversionRate = kDAC_ConversionRate62P5KHZ;
+ * config->refSource = kDAC_ReferenceInternalVoltageSource;
+ * config->rangeSelect = kDAC_RangeLarge;
+ * endcode
+ *
+ * param config Pointer to the structure which in the type of dac_config_t.
+ */
+void DAC_GetDefaultConfig(dac_config_t *config)
+{
+ assert(config != NULL);
+
+ (void)memset(config, 0, sizeof(dac_config_t));
+
+ config->conversionRate = kDAC_ConversionRate62P5KHZ;
+ config->refSource = kDAC_ReferenceInternalVoltageSource;
+ config->rangeSelect = kDAC_RangeLarge;
+}
+
+/*!
+ * brief De-initializes the DAC module, including reset clock divider, reset each channel, and so on.
+ *
+ * param base DAC peripheral base address.
+ */
+void DAC_Deinit(DAC_Type *base)
+{
+ /* Reset each channel. */
+ DAC_ResetChannel(base, kDAC_ChannelA | kDAC_ChannelB);
+
+ /* Reset Clock divider. */
+ base->CLK |= DAC_CLK_SOFT_CLK_RST_MASK;
+ for (uint8_t i = 0U; i < 10U; i++)
+ {
+ __NOP();
+ }
+ base->CLK &= ~DAC_CLK_SOFT_CLK_RST_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Gate the DAC clock*/
+ (void)CLOCK_DisableClock(s_dacClocks[DAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Configures the DAC channels, including enable channel conversion, set wave type, set timing mode, and so on.
+ *
+ * param base DAC peripheral base address.
+ * param channelMask The mask of channel, can be the OR'ed value of dac_channel_id_t.
+ * param channelConfig The pointer of structure which in the type of dac_channel_config_t.
+ */
+void DAC_SetChannelConfig(DAC_Type *base, uint32_t channelMask, const dac_channel_config_t *channelConfig)
+{
+ assert(channelConfig != NULL);
+
+ uint32_t tmp32 = 0UL;
+
+ /* Resets DAC channel. */
+ DAC_ResetChannel(base, channelMask);
+
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ assert(IS_DAC_CHANNEL_A_WAVE(channelConfig->waveType));
+
+ tmp32 = base->ACTRL;
+ tmp32 &=
+ ~(DAC_ACTRL_A_EN_MASK | DAC_ACTRL_A_IO_EN_MASK | DAC_ACTRL_A_TRIG_EN_MASK | DAC_ACTRL_A_TRIG_SEL_MASK |
+ DAC_ACTRL_A_TRIG_TYP_MASK | DAC_ACTRL_A_DEN_MASK | DAC_ACTRL_A_TIME_MODE_MASK | DAC_ACTRL_A_WAVE_MASK);
+
+ tmp32 |= DAC_ACTRL_A_EN(channelConfig->enableConversion) | DAC_ACTRL_A_IO_EN(channelConfig->outMode) |
+ DAC_ACTRL_A_TRIG_EN(channelConfig->enableTrigger) |
+ DAC_ACTRL_A_TRIG_SEL(channelConfig->triggerSource) | DAC_ACTRL_A_TRIG_TYP(channelConfig->triggerType) |
+ DAC_ACTRL_A_DEN(channelConfig->enableDMA) | DAC_ACTRL_A_TIME_MODE(channelConfig->timingMode) |
+ DAC_ACTRL_A_WAVE(channelConfig->waveType);
+
+ base->ACTRL = tmp32;
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ assert(IS_DAC_CHANNEL_B_WAVE(channelConfig->waveType));
+
+ tmp32 = base->BCTRL;
+ tmp32 &=
+ ~(DAC_BCTRL_B_EN_MASK | DAC_BCTRL_B_IO_EN_MASK | DAC_BCTRL_B_TRIG_EN_MASK | DAC_BCTRL_B_TRIG_SEL_MASK |
+ DAC_BCTRL_B_TRIG_TYP_MASK | DAC_BCTRL_B_DEN_MASK | DAC_BCTRL_B_TIME_MODE_MASK | DAC_BCTRL_B_WAVE_MASK);
+ tmp32 |= DAC_BCTRL_B_EN(channelConfig->enableConversion) | DAC_BCTRL_B_IO_EN(channelConfig->outMode) |
+ DAC_BCTRL_B_TRIG_EN(channelConfig->enableTrigger) |
+ DAC_BCTRL_B_TRIG_SEL(channelConfig->triggerSource) | DAC_BCTRL_B_TRIG_TYP(channelConfig->triggerType) |
+ DAC_BCTRL_B_DEN(channelConfig->enableDMA) | DAC_BCTRL_B_TIME_MODE(channelConfig->timingMode) |
+ DAC_BCTRL_B_WAVE(channelConfig->waveType);
+
+ base->BCTRL = tmp32;
+ }
+}
+
+/*!
+ * brief Configures the options of triangle waveform.
+ *
+ * note This API should be invoked to set the options of triangle waveform when channel A's output wave type is
+ * selected as kDAC_WaveTriangle.
+ *
+ * param base DAC peripheral base address.
+ * param triangleConfig The pointer of structure which in the type of dac_triangle_config_t.
+ */
+void DAC_SetTriangleConfig(DAC_Type *base, const dac_triangle_config_t *triangleConfig)
+{
+ assert(triangleConfig != NULL);
+
+ uint32_t tmp32;
+
+ tmp32 = base->ACTRL;
+ tmp32 &= ~(DAC_ACTRL_A_TRIA_STEP_SEL_MASK | DAC_ACTRL_A_TRIA_MAMP_SEL_MASK | DAC_ACTRL_A_TRIA_HALF_MASK);
+ tmp32 |= DAC_ACTRL_A_TRIA_STEP_SEL(triangleConfig->triangleStepSize) |
+ DAC_ACTRL_A_TRIA_MAMP_SEL(triangleConfig->triangleMamp) |
+ DAC_ACTRL_A_TRIA_HALF(triangleConfig->triangleWaveform);
+ base->ACTRL = tmp32;
+
+ base->ADATA = DAC_ADATA_A_DATA(triangleConfig->triangleBase);
+}
diff --git a/drivers/mw320/dac/fsl_dac.h b/drivers/mw320/dac/fsl_dac.h
new file mode 100644
index 000000000..40a63714d
--- /dev/null
+++ b/drivers/mw320/dac/fsl_dac.h
@@ -0,0 +1,679 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_DAC_H_
+#define _FSL_DAC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dac
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief DAC driver version */
+#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+
+/*!
+ * @brief DAC channel A wave mode check
+ */
+#define IS_DAC_CHANNEL_A_WAVE(CH_WAVE) ((CH_WAVE) <= kDAC_WaveNoiseDifferential)
+
+/*!
+ * @brief DAC channel B wave mode check
+ */
+#define IS_DAC_CHANNEL_B_WAVE(CH_WAVE) (((CH_WAVE) == kDAC_WaveNormal) || ((CH_WAVE) == kDAC_WaveNoiseDifferential))
+
+/*!
+ * @brief The enumeration of interrupts that DAC support.
+ */
+enum _dac_interrupt_enable
+{
+ kDAC_ChannelAReadyInterruptEnable = DAC_IMR_A_RDY_INT_MSK_MASK, /*!< Enable channel A data ready interrupt. */
+ kDAC_ChannelBReadyInterruptEnable = DAC_IMR_B_RDY_INT_MSK_MASK, /*!< Enable channel B data ready interrupt. */
+ kDAC_ChannelATimeoutInterruptEnable = DAC_IMR_A_TO_INT_MSK_MASK, /*!< Enable channel A time out interrupt. */
+ kDAC_ChannelBTimeoutInterruptEnable = DAC_IMR_B_TO_INT_MSK_MASK, /*!< Enable channel B time out interrupt. */
+ kDAC_TriangleOverflowInterruptEnable = DAC_IMR_TRIA_OVFL_INT_MSK_MASK, /*!< Enable triangle overflow interrupt. */
+};
+
+/*!
+ * @brief The enumeration of DAC status flags, including interrupt status flags, raw status flags, and conversion status
+ * flags.
+ *
+ * @note The interrupt status flags can only be asserted upon both enabling and happening of related interrupts.
+ * Comparatively, the raw status flags will be asserted as long as related events happen regardless of whether
+ * related interrupts are enabled or not.
+ *
+ * @note Only interrupt status flags can be cleared mannually.
+ */
+enum _dac_status_flags
+{
+ kDAC_ChannelADataReadyInterruptFlag = DAC_ISR_A_RDY_INT_MASK, /*!< Channel A data ready. */
+ kDAC_ChannelBDataReadyInterruptFlag = DAC_ISR_B_RDY_INT_MASK, /*!< Channel B data ready. */
+ kDAC_ChannelATimeoutInterruptFlag = DAC_ISR_A_TO_INT_MASK, /*!< Channel A time out. */
+ kDAC_ChannelBTimeoutInterruptFlag = DAC_ISR_B_TO_INT_MASK, /*!< Channel B time out. */
+ kDAC_TriangleOverflowInterruptFlag = DAC_ISR_TRIA_OVFL_INT_MASK, /*!< Triangle overflow. */
+ kDAC_RawChannelADataReadyFlag = DAC_IRSR_A_RDY_INT_RAW_MASK << 5UL, /*!< Channel A data ready raw. */
+ kDAC_RawChannelBDataReadyFlag = DAC_IRSR_B_RDY_INT_RAW_MASK << 5UL, /*!< Channel B data ready raw. */
+ kDAC_RawChannelATimeoutFlag = DAC_IRSR_A_TO_INT_RAW_MASK << 5UL, /*!< Channel A timeout raw. */
+ kDAC_RawChannelBTimeoutFlag = DAC_IRSR_B_TO_INT_RAW_MASK << 5UL, /*!< Channel B timeout raw. */
+ kDAC_RawTriangleOverflowFlag = DAC_IRSR_TRIA_OVFL_INT_RAW_MASK << 5UL, /*!< Triangle overflow raw. */
+ kDAC_ChannelAConversionCompleteFlag = DAC_STATUS_A_DV_MASK << 10UL, /*!< Channel A conversion complete. */
+ kDAC_ChannelBConversionCompleteFlag = DAC_STATUS_B_DV_MASK << 10UL, /*!< Channel B conversion complete. */
+};
+
+/*!
+ * @brief The enumeration of dac channels, including channel A and channel B.
+ */
+typedef enum _dac_channel_id
+{
+ kDAC_ChannelA = 1U << 0U,
+ kDAC_ChannelB = 1U << 1U,
+} dac_channel_id_t;
+
+/*!
+ * @brief The enumeration of dac converion rate, including 62.5 KHz, 125 KHz, 250 KHz, and 500 KHz.
+ */
+typedef enum _dac_conversion_rate
+{
+ kDAC_ConversionRate62P5KHZ = 0U, /*!< DAC Conversion Rate selects as 62.5 KHz. */
+ kDAC_ConversionRate125KHZ, /*!< DAC Conversion Rate selects as 125 KHz. */
+ kDAC_ConversionRate250KHZ, /*!< DAC Conversion Rate selects as 250 KHz. */
+ kDAC_ConversionRate500KHZ, /*!< DAC Conversion Rate selects as 500 KHz. */
+} dac_conversion_rate_t;
+
+/*!
+ * @brief The enumeration of dac reference voltage source.
+ */
+typedef enum _dac_reference_voltage_source
+{
+ kDAC_ReferenceInternalVoltageSource = 0U, /*!< Select internal voltage reference. */
+ kDAC_ReferenceExternalVoltageSource, /*!< Select external voltage reference. */
+} dac_reference_voltage_source_t;
+
+/*!
+ * @brief The enumeration of dac output voltage range.
+ */
+typedef enum _dac_output_voltage_range
+{
+ kDAC_RangeSmall = 0U, /*!< DAC output small range. */
+ kDAC_RangeMiddle = 1U, /*!< DAC output middle range. */
+ kDAC_RangeLarge = 3U, /*!< DAC output large range. */
+} dac_output_voltage_range_t;
+
+/*!
+ * @brief The enumeration of dac channel's output mode.
+ */
+typedef enum _dac_channel_output
+{
+ kDAC_ChannelOutputInternal = 0U, /*!< Enable internal output but disable output to pad */
+ kDAC_ChannelOutputPAD, /*!< Enable output to pad but disable internal output */
+} dac_channel_output_t;
+
+/*!
+ * @brief The enumeration of dac channel's trigger type, including rising edge trigger, falling edge trigger, and both
+ * edge triggers.
+ */
+typedef enum _dac_channel_trigger_type
+{
+ kDAC_RisingEdgeTrigger = 1U, /*!< Rising edge trigger. */
+ kDAC_FallingEdgeTrigger = 2U, /*!< Failing edge trigger. */
+ kDAC_BothEdgeTrigger = 3U /*!< Rising and Failing edge trigger. */
+} dac_channel_trigger_type_t;
+
+/*!
+ * @brief The enumeration of dac channel trigger source.
+ */
+typedef enum _dac_channel_trigger_source
+{
+ kDAC_GPT2Trigger = 0U, /*!< GPT2 trigger source */
+ kDAC_GPT3Trigger = 1U, /*!< GPT3 trigger source */
+ kDAC_GPIO45Trigger = 2U, /*!< GPIO45 trigger source */
+ kDAC_GPIO44Trigger = 3U /*!< GPIO44 trigger source */
+} dac_channel_trigger_source_t;
+
+/*!
+ * @brief The enumeration of dac channel timing mode.
+ */
+typedef enum _dac_channel_timing_mode
+{
+ kDAC_NonTimingCorrelated = 0U, /*!< DAC non-timing-correlated mode. */
+ kDAC_TimingCorrelated, /*!< DAC timing-correlated mode. */
+} dac_channel_timing_mode_t;
+
+/*!
+ * @brief The enumerator of channel output wave type, please note that not all wave types are effective to
+ * A and B channel.
+ */
+typedef enum _dac_channel_wave_type
+{
+ kDAC_WaveNormal = 0U, /*!< No predefined waveform, effective to A or B channel */
+ kDAC_WaveTriangle = 1U, /*!< Triangle wave, effective only to A channel */
+ kDAC_WaveSine = 2U, /*!< Sine wave, effective only to A channel */
+ kDAC_WaveNoiseDifferential = 3U, /*!< Noise wave, effective only to A channel;
+ Differential mode, one's complemental code from A data,
+ effective only to B channel */
+} dac_channel_wave_type_t;
+
+/*!
+ * @brief DAC triangle maximum amplitude type
+ */
+typedef enum _dac_triangle_mamp
+{
+ kDAC_TriangleAmplitude63 = 0U, /*!< DAC triangle amplitude 63 lsb */
+ kDAC_TriangleAmplitude127, /*!< DAC triangle amplitude 127 lsb */
+ kDAC_TriangleAmplitude191, /*!< DAC triangle amplitude 191 lsb */
+ kDAC_TriangleAmplitude255, /*!< DAC triangle amplitude 255 lsb */
+ kDAC_TriangleAmplitude319, /*!< DAC triangle amplitude 319 lsb */
+ kDAC_TriangleAmplitude383, /*!< DAC triangle amplitude 383 lsb */
+ kDAC_TriangleAmplitude447, /*!< DAC triangle amplitude 447 lsb */
+ kDAC_TriangleAmplitude511, /*!< DAC triangle amplitude 511 lsb */
+ kDAC_TriangleAmplitude575, /*!< DAC triangle amplitude 575 lsb */
+ kDAC_TriangleAmplitude639, /*!< DAC triangle amplitude 639 lsb */
+ kDAC_TriangleAmplitude703, /*!< DAC triangle amplitude 703 lsb */
+ kDAC_TriangleAmplitude767, /*!< DAC triangle amplitude 767 lsb */
+ kDAC_TriangleAmplitude831, /*!< DAC triangle amplitude 831 lsb */
+ kDAC_TriangleAmplitude895, /*!< DAC triangle amplitude 895 lsb */
+ kDAC_TriangleAmplitude959, /*!< DAC triangle amplitude 959 lsb */
+ kDAC_TriangleAmplitude1023 /*!< DAC triangle amplitude 1023 lsb */
+} dac_triangle_mamp_t;
+
+/*!
+ * @brief DAC triangle step size type
+ */
+typedef enum _dac_triangle_step_size
+{
+ kDAC_TriangleStepSize1 = 0U, /*!< DAC triangle step size 1 lsb */
+ kDAC_TriangleStepSize3, /*!< DAC triangle step size 3 lsb */
+ kDAC_TriangleStepSize15, /*!< DAC triangle step size 15 lsb */
+ kDAC_TriangleStepSize511 /*!< DAC triangle step size 511 lsb */
+} dac_triangle_step_size_t;
+
+/*!
+ * @brief DAC triangle waveform type
+ */
+typedef enum _dac_triangle_waveform_type
+{
+ kDAC_TriangleFull = 0U, /*!< DAC full triangle waveform */
+ kDAC_TriangleHalf, /*!< DAC half triangle waveform */
+} dac_triangle_waveform_type_t;
+
+/*!
+ * @brief The structure of dac module basic configuration, including conversion rate, output range, and reference
+ * voltage source.
+ */
+typedef struct _dac_config
+{
+ dac_conversion_rate_t conversionRate; /*!< Configure DAC conversion rate,
+ please refer to @ref dac_conversion_rate_t. */
+ dac_reference_voltage_source_t refSource; /*!< Configure DAC vref source,
+ please refer to @ref dac_reference_voltage_source_t. */
+ dac_output_voltage_range_t rangeSelect; /*!< Configure DAC channel output range,
+ please refer to @ref dac_output_voltage_range_t. */
+} dac_config_t;
+
+/*!
+ * @brief The structure of dac channel configuration, such as trigger type, wave type, timing mode, and so on.
+ *
+ */
+typedef struct _dac_channel_config
+{
+ bool enableConversion; /*!< Enable/Disable selected channel's conversion.
+ - \b true Enable selected channel's conversion.
+ - \b false Disable selected channel's conversion. */
+ dac_channel_output_t outMode; /*!< Configure channel output mode, please refer to @ref dac_channel_output_t */
+
+ bool enableDMA; /*!< Enable/Disable channel DAM data transfer.
+ - \b true DMA data transfer enabled.
+ - \b false DMA data transfer disabled. */
+ bool enableTrigger; /*!< Enable/Disable external event trigger. */
+ dac_channel_trigger_type_t triggerType; /*!< Configure the channel trigger type,
+ please refer to @ref dac_channel_trigger_type_t. */
+ dac_channel_trigger_source_t triggerSource; /*!< Configure DAC channel trigger source,
+ please refer to @ref dac_channel_trigger_source_t. */
+
+ dac_channel_timing_mode_t timingMode; /*!< Configure channel timing mode,
+ please refer to @ref dac_channel_timing_mode_t. */
+
+ dac_channel_wave_type_t waveType; /*!< Configure wave type for the selected channel,
+ please refer to @ref dac_channel_wave_type_t. */
+} dac_channel_config_t;
+
+/*!
+ * @brief The structure of triangle waveform, including maximum value, minimum value, step size, and so on.
+ */
+typedef struct _dac_triangle_config
+{
+ dac_triangle_mamp_t triangleMamp; /*!< Configure triangle maximum value. */
+ dac_triangle_step_size_t triangleStepSize; /*!< Configure triangle step size. */
+ dac_triangle_waveform_type_t triangleWaveform; /*!< Configure triangle waveform type. */
+ uint32_t triangleBase; /*!< Configure triangle minimum value. */
+} dac_triangle_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Module Initialization Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Initializes DAC module, including set reference voltage source, set conversion range, and set output voltage
+ * range.
+ *
+ * @param base DAC peripheral base address.
+ * @param config Pointer to the structure which in type of @ref dac_config_t.
+ */
+void DAC_Init(DAC_Type *base, const dac_config_t *config);
+
+/*!
+ * @brief Gets the default configurations of DAC module.
+ *
+ * @code
+ * config->conversionRate = kDAC_ConversionRate62P5KHZ;
+ * config->refSource = kDAC_ReferenceInternalVoltageSource;
+ * config->rangeSelect = kDAC_RangeLarge;
+ * @endcode
+ *
+ * @param config Pointer to the structure which in the type of @ref dac_config_t.
+ */
+void DAC_GetDefaultConfig(dac_config_t *config);
+
+/*!
+ * @brief De-initializes the DAC module, including reset clock divider, reset each channel, and so on.
+ *
+ * @param base DAC peripheral base address.
+ */
+void DAC_Deinit(DAC_Type *base);
+
+/* @} */
+
+/*!
+ * @name Channels Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Configures the DAC channels, including enable channel conversion, set wave type, set timing mode, and so on.
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, can be the OR'ed value of @ref dac_channel_id_t.
+ * @param channelConfig The pointer of structure which in the type of @ref dac_channel_config_t.
+ */
+void DAC_SetChannelConfig(DAC_Type *base, uint32_t channelMask, const dac_channel_config_t *channelConfig);
+
+/*!
+ * @brief Does software reset for the selected DAC channels.
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel to be reset, should be the OR'ed value of @ref dac_channel_id_t.
+ */
+static inline void DAC_ResetChannel(DAC_Type *base, uint32_t channelMask)
+{
+ base->RST = channelMask;
+ for (uint8_t i = 0U; i < 10U; i++)
+ {
+ __NOP();
+ }
+ base->RST = 0UL;
+}
+
+/*!
+ * @brief Enables/Disables selected channel conversion.
+ *
+ * @note To enable/disable the conversions of both channels, invoking this API with the parameter \b channelMask
+ * set as \b kDAC_ChannelA|kDAC_ChannelB .
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel to be reset, can be the OR'ed value of @ref dac_channel_id_t.
+ * @param enable Enable/Disable channel conversion.
+ * - \b true Enable selected channels' conversion.
+ * - \b false Disable selected channels' conversion.
+ */
+static inline void DAC_EnableChannelConversion(DAC_Type *base, uint32_t channelMask, bool enable)
+{
+ if (enable)
+ {
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL |= DAC_ACTRL_A_EN_MASK;
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL |= DAC_BCTRL_B_EN_MASK;
+ }
+ }
+ else
+ {
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL &= ~DAC_ACTRL_A_EN_MASK;
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL &= ~DAC_BCTRL_B_EN_MASK;
+ }
+ }
+}
+
+/*!
+ * @brief Sets channels out mode, including kDAC_ChannelOutputInternal and kDAC_ChannelOutputPad.
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, can be the OR'ed value of @ref dac_channel_id_t.
+ * @param outMode The out mode of selected channels, please refer to @ref dac_channel_output_t for details.
+ */
+static inline void DAC_SetChannelOutMode(DAC_Type *base, uint32_t channelMask, dac_channel_output_t outMode)
+{
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL = (base->ACTRL & ~(DAC_ACTRL_A_IO_EN_MASK)) | DAC_ACTRL_A_IO_EN(outMode);
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL = (base->BCTRL & ~(DAC_BCTRL_B_IO_EN_MASK)) | DAC_BCTRL_B_IO_EN(outMode);
+ }
+}
+
+/*!
+ * @brief Enables/Disables channels trigger mode.
+ *
+ * @note To enable/disable the trigger mode of both two channels, invoking this API with the parameter \b channelMask
+ * set as \b kDAC_ChannelA|kDAC_ChannelB .
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, can be the OR'ed value of @ref dac_channel_id_t.
+ * @param enable Enable/Disable channel trigger mode.
+ * - \b true Channels' conversion triggered by external event enabled.
+ * - \b false Channels' conversion trigged by external event disabled.
+ */
+static inline void DAC_EnableChannelTriggerMode(DAC_Type *base, uint32_t channelMask, bool enable)
+{
+ if (enable)
+ {
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL |= DAC_ACTRL_A_TRIG_EN_MASK;
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL |= DAC_BCTRL_B_TRIG_EN_MASK;
+ }
+ }
+ else
+ {
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL &= ~DAC_ACTRL_A_TRIG_EN_MASK;
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL &= ~DAC_BCTRL_B_TRIG_EN_MASK;
+ }
+ }
+}
+
+/*!
+ * @brief Sets channels trigger source.
+ *
+ * @note To set the same trigger source to both two channels, invoking this API with the parameter \b channelMask
+ * set as \b kDAC_ChannelA|kDAC_ChannelB .
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, can be the OR'ed value of @ref dac_channel_id_t.
+ * @param trigSource The selected trigger source, please refer to @ref dac_channel_trigger_source_t for details.
+ */
+static inline void DAC_SetChannelTrigSource(DAC_Type *base,
+ uint32_t channelMask,
+ dac_channel_trigger_source_t trigSource)
+{
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL = (base->ACTRL & ~(DAC_ACTRL_A_TRIG_SEL_MASK)) | DAC_ACTRL_A_TRIG_SEL(trigSource);
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL = (base->BCTRL & ~(DAC_BCTRL_B_TRIG_SEL_MASK)) | DAC_BCTRL_B_TRIG_SEL(trigSource);
+ }
+}
+
+/*!
+ * @brief Sets channels trigger type, such as rising edge trigger, falling edge trigger, or both edge trigger.
+ *
+ * @note To set the same trigger type to both two channels, invoking this API with the parameter \b channelMask
+ * set as \b kDAC_ChannelA|kDAC_ChannelB .
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, can be the OR'ed value of @ref dac_channel_id_t;
+ * @param trigType The selected trigger type, please refer to @ref dac_channel_trigger_type_t;
+ */
+static inline void DAC_SetChannelTrigType(DAC_Type *base, uint32_t channelMask, dac_channel_trigger_type_t trigType)
+{
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL = (base->ACTRL & ~(DAC_ACTRL_A_TRIG_TYP_MASK)) | DAC_ACTRL_A_TRIG_TYP(trigType);
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL = (base->BCTRL & ~(DAC_BCTRL_B_TRIG_TYP_MASK)) | DAC_BCTRL_B_TRIG_TYP(trigType);
+ }
+}
+
+/*!
+ * @brief Sets channels timing mode, including not-timing related or timing related.
+ *
+ * @note To the same timing mode to both two channels, invoking this API with the parameter \b channelMask
+ * set as \b kDAC_ChannelA|kDAC_ChannelB .
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, can be the OR'ed value of @ref dac_channel_id_t.
+ * @param timingMode The selected timing mode, please refer to @ref dac_channel_timing_mode_t for details.
+ */
+static inline void DAC_SetChannelTimingMode(DAC_Type *base, uint32_t channelMask, dac_channel_timing_mode_t timingMode)
+{
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL = (base->ACTRL & ~(DAC_ACTRL_A_TIME_MODE_MASK)) | DAC_ACTRL_A_TIME_MODE(timingMode);
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL = (base->BCTRL & ~(DAC_BCTRL_B_TIME_MODE_MASK)) | DAC_BCTRL_B_TIME_MODE(timingMode);
+ }
+}
+
+/*!
+ * @brief Enables/Disables channels DMA.
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, can be the OR'ed value of @ref dac_channel_id_t.
+ * @param enable Enable/Disable channel DMA data transfer.
+ * - \b true DMA data transfer enabled.
+ * - \b false DMA data transfer disabled.
+ */
+static inline void DAC_EnableChannelDMA(DAC_Type *base, uint32_t channelMask, bool enable)
+{
+ if (enable)
+ {
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL |= DAC_ACTRL_A_DEN_MASK;
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL |= DAC_BCTRL_B_DEN_MASK;
+ }
+ }
+ else
+ {
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ACTRL &= ~DAC_ACTRL_A_DEN_MASK;
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BCTRL &= ~DAC_BCTRL_B_DEN_MASK;
+ }
+ }
+}
+
+/*!
+ * @brief Sets channels wave type, such as sine, noise, or triangle.
+ *
+ * @note To set the same wave type to both channel, invoking this API with the parameter \b channelMask
+ * set as \b kDAC_ChannelA|kDAC_ChannelB .
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, should be the OR'ed value of @ref dac_channel_id_t.
+ * @param waveType The wave type to set, please refer to @ref dac_channel_wave_type_t.
+ */
+static inline void DAC_SetChannelWaveType(DAC_Type *base, uint32_t channelMask, dac_channel_wave_type_t waveType)
+{
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ assert(IS_DAC_CHANNEL_A_WAVE(waveType));
+ base->ACTRL = (base->ACTRL & ~(DAC_ACTRL_A_WAVE_MASK)) | DAC_ACTRL_A_WAVE(waveType);
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ assert(IS_DAC_CHANNEL_B_WAVE(waveType));
+ base->BCTRL = (base->BCTRL & ~(DAC_BCTRL_B_WAVE_MASK)) | DAC_BCTRL_B_WAVE(waveType);
+ }
+}
+
+/*!
+ * @brief Sets DAC channels data.
+ *
+ * @note To set the same data to both channel, invoking this API with the parameter \b channelMask
+ * set as \b kDAC_ChannelA|kDAC_ChannelB .
+ *
+ * @param base DAC peripheral base address.
+ * @param channelMask The mask of channel, can be the OR'ed value of @ref dac_channel_id_t.
+ * @param data
+ */
+static inline void DAC_SetChannelData(DAC_Type *base, uint32_t channelMask, uint16_t data)
+{
+ if ((channelMask & kDAC_ChannelA) == kDAC_ChannelA)
+ {
+ base->ADATA = DAC_ADATA_A_DATA(data);
+ }
+
+ if ((channelMask & kDAC_ChannelB) == kDAC_ChannelB)
+ {
+ base->BDATA = DAC_BDATA_B_DATA(data);
+ }
+}
+
+/*! @} */
+
+/*!
+ * @name Triangle Waveform Configuration Interface
+ * @{
+ */
+
+/*!
+ * @brief Configures the options of triangle waveform.
+ *
+ * @note This API should be invoked to set the options of triangle waveform when channel A's output wave type is
+ * selected as @ref kDAC_WaveTriangle.
+ *
+ * @param base DAC peripheral base address.
+ * @param triangleConfig The pointer of structure which in the type of @ref dac_triangle_config_t.
+ */
+void DAC_SetTriangleConfig(DAC_Type *base, const dac_triangle_config_t *triangleConfig);
+
+/*! @} */
+
+/*!
+ * @name Interrupts Control Interfaces.
+ * @{
+ */
+
+/*!
+ * @brief Enables interrupts, such as channel A data ready interupt, channel A timeout interrupt, and so on.
+ *
+ * @param base DAC peripheral base address.
+ * @param interruptMask The or'ed value of the interrupts to be enabled, please refer to @ref _dac_interrupt_enable.
+ */
+static inline void DAC_EnableInterrupts(DAC_Type *base, uint32_t interruptMask)
+{
+ base->IMR &= ~interruptMask;
+}
+
+/*!
+ * @brief Disables interrupts, such as channel B data ready interrupt, channel B timeout interrupt, and so on.
+ *
+ * @param base DAC peripheral base address.
+ * @param interruptMask The or'ed value of the interrupts to be disabled, please refer to @ref _dac_interrupt_enable.
+ */
+static inline void DAC_DisableInterrupts(DAC_Type *base, uint32_t interruptMask)
+{
+ base->IMR |= interruptMask;
+}
+
+/*! @} */
+
+/*!
+ * @name Status Flags Control Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Gets the status flags, including interrupt status flags, raw status flags, and conversion status flags.
+ *
+ * @param base DAC peripheral base address.
+ * @return The mask of status flags, please refer to @ref _dac_status_flags.
+ */
+
+static inline uint32_t DAC_GetStatusFlags(DAC_Type *base)
+{
+ return ((base->ISR) | ((base->IRSR) << 5UL) | ((base->STATUS) << 10UL));
+}
+
+/*!
+ * @brief Clears the interrups status flags, such as channel A data ready interrupt flag, channel B data ready interrupt
+ * flag, and so on.
+ *
+ * @param base DAC peripheral base address.
+ * @param statusFlagsMask The mask of the status flags to be cleared, please refer to @ref _dac_status_flags.
+ */
+static inline void DAC_ClearStatusFlags(DAC_Type *base, uint32_t statusFlagsMask)
+{
+ assert(statusFlagsMask <= 0x1FUL);
+
+ base->ICR = statusFlagsMask;
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_DAC_H_ */
diff --git a/drivers/mw320/dmac/driver_mw_dmac.cmake b/drivers/mw320/dmac/driver_mw_dmac.cmake
new file mode 100644
index 000000000..078fe2a2a
--- /dev/null
+++ b/drivers/mw320/dmac/driver_mw_dmac.cmake
@@ -0,0 +1,14 @@
+#Description: MW_DMAC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_dmac component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_dmac.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/dmac/fsl_dmac.c b/drivers/mw320/dmac/fsl_dmac.c
new file mode 100644
index 000000000..4866b5259
--- /dev/null
+++ b/drivers/mw320/dmac/fsl_dmac.c
@@ -0,0 +1,601 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_dmac.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mw_dmac"
+#endif
+
+/*! brief _dmac_transfer_status DMAC transfer status*/
+enum _dmac_transfer_status
+{
+ kDMAC_TransferStatusIdle, /*!< Channel is idle. */
+ kDMAC_TransferStatusBusy, /*!< Channel is busy and can't handle the transfer request. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! brief Array to map DMAC instance number to base pointer. */
+static DMAC_Type *const s_dmacBases[] = DMAC_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! brief Array to map DMAC instance number to clock name. */
+static const clock_ip_name_t s_dmacClockName[] = DMAC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! brief Array to map DMAC instance number to IRQ number. */
+static const IRQn_Type s_dmacIRQNumber[] = DMAC_IRQS;
+
+/*! brief Pointers to transfer handle for each DMAC channel. */
+static dmac_handle_t *s_DMACHandle[FSL_FEATURE_MW_DMAC_MODULE_CHANNEL * FSL_FEATURE_SOC_MW_DMAC_COUNT];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * brief Get the DMAC instance from peripheral base address.
+ *
+ * param base DMAC peripheral base address.
+ * return DMAC instance.
+ */
+static uint32_t DMAC_GetInstance(DMAC_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_dmacBases); instance++)
+ {
+ if (s_dmacBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_dmacBases));
+
+ return instance;
+}
+
+/*!
+ * brief Get default dmac configuration.
+ *
+ * note This function will reset all of the configuration structure members to zero firstly,
+ * then apply default configurations to the structure.
+ *
+ * param config pointer to user's DMAC configure structure, see dmac_config_t for detail.
+ */
+void DMAC_GetDefaultConfig(dmac_config_t *config)
+{
+ assert(config != NULL);
+
+ (void)memset(config, 0, sizeof(dmac_config_t));
+
+ /*The value should be less than 1023, default value 12.*/
+ config->m2pAckDelayCycle = 12U;
+ for (uint32_t i = 0U; i < (uint32_t)FSL_FEATURE_MW_DMAC_MODULE_CHANNEL; i++)
+ {
+ /*The default value is kDMAC_PeriphNum_None.*/
+ config->peripheralNumber[i] = kDMAC_PeriphNum_None;
+ }
+}
+
+/*!
+ * brief DMAC initialization
+ *
+ * param base DMAC peripheral base address.
+ * param Config pointer to user's DMAC configure structure, see dmac_transfer_config_t for detail.
+ */
+void DMAC_Init(DMAC_Type *base, dmac_config_t *config)
+{
+ assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate DMAC peripheral clock */
+ CLOCK_EnableClock(s_dmacClockName[DMAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ /* clear all the enabled request, status to make sure DMAC status is in normal condition */
+ base->STATUS_TFRINT = 0xFFFFFFFFU;
+ base->STATUS_BLOCKINT = 0xFFFFFFFFU;
+ base->STATUS_BUSERRINT = 0xFFFFFFFFU;
+ base->STATUS_ADDRERRINT = 0xFFFFFFFFU;
+
+ /* Configure DMAC peripheral according to the configuration structure. */
+ DMAC_SetAckDelayCycle(base, config->m2pAckDelayCycle);
+
+ /* channel transfer configuration */
+ for (uint32_t i = 0U; i < (uint32_t)FSL_FEATURE_MW_DMAC_MODULE_CHANNEL; i++)
+ {
+ if (config->channelTransferConfig[i] != NULL)
+ {
+ DMAC_SetChannelTransferConfig(base, (dmac_channel_t)i, config->channelTransferConfig[i]);
+ }
+ if (config->peripheralNumber[i] != kDMAC_PeriphNum_None)
+ {
+ DMAC_SetPeripheralNumber(base, (dmac_channel_t)i, config->peripheralNumber[i]);
+ }
+ }
+}
+
+/*!
+ * brief DMAC De-initialization
+ *
+ * param base DMAC peripheral base address.
+ */
+void DMAC_Deinit(DMAC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate DMAC peripheral clock */
+ CLOCK_DisableClock(s_dmacClockName[DMAC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Get channel default transfer configuration.
+ *
+ * param transfer pointer to user's DMAC channel configure structure, see dmac_channel_transfer_config_t for detail.
+ * param srcAddr source address, must be byte address.
+ * param destAddr destination address, must be byte address.
+ * param transferWidth the number of bits are transferred in each read/write.
+ * param burstLength burst transaction length.
+ * param transferTotalBytes transfer totalbytes 0~8191bytes maximum transfer length (8k-1) bytes.
+ * param transferType DMAC channel transfer type.
+ */
+void DMAC_GetChannelDefaultTransferConfig(dmac_channel_transfer_config_t *transfer,
+ void *srcAddr,
+ void *destAddr,
+ dmac_channel_transfer_width_t transferWidth,
+ dmac_channel_burst_length_t burstLength,
+ uint32_t transferTotalBytes,
+ dmac_channel_transfer_type_t transferType)
+{
+ assert(transfer != NULL);
+ assert(((transferTotalBytes % (uint32_t)transferWidth) == 0U));
+ assert(((uint32_t)(uint32_t *)srcAddr & ((uint32_t)transferWidth - 1U)) == 0U);
+ assert(((uint32_t)(uint32_t *)destAddr & ((uint32_t)transferWidth - 1U)) == 0U);
+
+ (void)memset(transfer, 0, sizeof(dmac_channel_transfer_config_t));
+
+ transfer->srcAddr = srcAddr;
+ transfer->destAddr = destAddr;
+ transfer->transferWidth = transferWidth;
+ transfer->burstLength = burstLength;
+ transfer->transferTotalBytes = transferTotalBytes;
+ transfer->transferType = transferType;
+
+ /* default advance channel transfer configurations */
+ if (transferType == kDMAC_ChannelTransferMemoryToMemory)
+ {
+ transfer->srcAddrIncrementType = kDMAC_ChannelAddressIncrement;
+ transfer->destAddrIncrementType = kDMAC_ChannelAddressIncrement;
+ }
+ else if (transferType == kDMAC_ChannelTransferPeripheralToMemory)
+ {
+ transfer->srcAddrIncrementType = kDMAC_ChannelAddressFix;
+ transfer->destAddrIncrementType = kDMAC_ChannelAddressIncrement;
+ }
+ else
+ {
+ transfer->srcAddrIncrementType = kDMAC_ChannelAddressIncrement;
+ transfer->destAddrIncrementType = kDMAC_ChannelAddressFix;
+ }
+}
+
+/*!
+ * brief DMAC set channel transfer configurations
+ *
+ * param base DMAC peripheral base address.
+ * param channel DMAC channel number.
+ * param transfer pointer to user's DMAC channel configure structure, see dmac_channel_transfer_config_t for detail.
+ */
+void DMAC_SetChannelTransferConfig(DMAC_Type *base, dmac_channel_t channel, dmac_channel_transfer_config_t *transfer)
+{
+ assert(transfer != NULL);
+ assert(((transfer->transferTotalBytes % (uint32_t)transfer->transferWidth) == 0U));
+ assert(((uint32_t)(uint32_t *)transfer->srcAddr & ((uint32_t)transfer->transferWidth - 1U)) == 0U);
+ assert(((uint32_t)(uint32_t *)transfer->destAddr & ((uint32_t)transfer->transferWidth - 1U)) == 0U);
+
+ uint32_t ctrlA = base->CHANNEL[channel].CTRLA;
+
+ base->CHANNEL[channel].SADR = (uint32_t)(uint32_t *)transfer->srcAddr;
+
+ base->CHANNEL[channel].TADR = (uint32_t)(uint32_t *)transfer->destAddr;
+
+ ctrlA &= ~DMAC_CTRLA_WIDTH_MASK;
+ ctrlA |= DMAC_CTRLA_WIDTH((transfer->transferWidth == kDMAC_ChannelTransferWidth32Bits) ?
+ ((uint32_t)transfer->transferWidth - 1U) :
+ (uint32_t)transfer->transferWidth);
+
+ ctrlA &= ~DMAC_CTRLA_TRAN_SIZE_MASK;
+ ctrlA |= DMAC_CTRLA_TRAN_SIZE(transfer->burstLength);
+
+ ctrlA &= ~DMAC_CTRLA_LEN_MASK;
+ ctrlA |= DMAC_CTRLA_LEN(transfer->transferTotalBytes);
+
+ ctrlA &= ~DMAC_CTRLA_TRAN_TYPE_MASK;
+ ctrlA |= DMAC_CTRLA_TRAN_TYPE(transfer->transferType);
+
+ ctrlA &= ~DMAC_CTRLA_INCSRCADDR_MASK;
+ ctrlA |= DMAC_CTRLA_INCSRCADDR(transfer->srcAddrIncrementType);
+
+ ctrlA &= ~DMAC_CTRLA_INCTRGADDR_MASK;
+ ctrlA |= DMAC_CTRLA_INCTRGADDR(transfer->destAddrIncrementType);
+
+ base->CHANNEL[channel].CTRLA = ctrlA;
+
+ DMAC_EnableChannelInterrupts(base, channel, transfer->interruptMask);
+}
+
+/*!
+ * brief DMAC ack delay cycle for single transfer in M2P transfer type.Only called when the transfer type is M2P.
+ *
+ * param base DMAC peripheral base address.
+ * param m2pAckDelayCycle for single write transaction to peripheral. The value should be less than 1023, default
+ * value 12.
+ */
+void DMAC_SetAckDelayCycle(DMAC_Type *base, uint32_t m2pAckDelayCycle)
+{
+ /* Config DMAC ACK Delay Cycle for single transfer */
+ base->ACK_DELAY = DMAC_ACK_DELAY_ACK_DELAY_NUM(m2pAckDelayCycle);
+}
+
+/*!
+ * brief DMAC set peripheral number.
+ *
+ * param base DMAC peripheral base address.
+ * param channel DMAC channel number.
+ * param peripheralNumber Indicates the valid peripheral request number, default value kDMAC_PeriphNum_None,
+ * see @ref dmac_peripheral_number_t for detail.
+ */
+void DMAC_SetPeripheralNumber(DMAC_Type *base, dmac_channel_t channel, dmac_peripheral_number_t peripheralNumber)
+{
+ base->CHANNEL[channel].CTRLB =
+ (base->CHANNEL[channel].CTRLB & (~DMAC_CTRLB_PERNUM_MASK)) | DMAC_CTRLB_PERNUM(peripheralNumber);
+}
+
+/*!
+ * brief enables the dmac channel interrupts
+ *
+ * param base DMAC peripheral base address.
+ * param channel DMAC channel number.
+ * param interruptsMask the mask is a logical OR of enumerator members see _dmac_channel_interrupt_flag.
+ */
+void DMAC_EnableChannelInterrupts(DMAC_Type *base, dmac_channel_t channel, uint32_t interruptsMask)
+{
+ if (0U != (interruptsMask & (uint32_t)kDMAC_ChannelInterruptFlagBusError))
+ {
+ base->MASK_BUSERRINT |= (1UL << channel);
+ }
+ else
+ {
+ base->MASK_BUSERRINT &= ~(1UL << channel);
+ }
+
+ if (0U != (interruptsMask & (uint32_t)kDMAC_ChannelInterruptFlagAdressError))
+ {
+ base->MASK_ADDRERRINT |= (1UL << channel);
+ }
+ else
+ {
+ base->MASK_ADDRERRINT &= ~(1UL << channel);
+ }
+
+ if (0U != (interruptsMask & (uint32_t)kDMAC_ChannelInterruptFlagTransferComplete))
+ {
+ base->MASK_TFRINT |= (1UL << channel);
+ }
+ else
+ {
+ base->MASK_TFRINT &= ~(1UL << channel);
+ }
+
+ if (0U != (interruptsMask & (uint32_t)kDMAC_ChannelInterruptBlockTransferComplete))
+ {
+ base->MASK_BLOCKINT |= (1UL << channel);
+ }
+ else
+ {
+ base->MASK_BLOCKINT &= ~(1UL << channel);
+ }
+}
+
+/*!
+ * brief disables the dmac channel interrupts
+ *
+ * param base DMAC peripheral base address.
+ * param channel DMAC channel number.
+ * param interruptsMask the mask is a logical OR of enumerator members see _dmac_channel_interrupt_flag.
+ */
+void DMAC_DisableChannelInterrupts(DMAC_Type *base, dmac_channel_t channel, uint32_t interruptsMask)
+{
+ if (interruptsMask == (uint32_t)kDMAC_ChannelInterruptFlagBusError)
+ {
+ base->MASK_BUSERRINT |= (1UL << channel);
+ }
+
+ if (interruptsMask == (uint32_t)kDMAC_ChannelInterruptFlagAdressError)
+ {
+ base->MASK_ADDRERRINT |= (1UL << channel);
+ }
+
+ if (interruptsMask == (uint32_t)kDMAC_ChannelInterruptFlagTransferComplete)
+ {
+ base->MASK_TFRINT |= (1UL << channel);
+ }
+
+ if (interruptsMask == (uint32_t)kDMAC_ChannelInterruptBlockTransferComplete)
+ {
+ base->MASK_BLOCKINT |= (1UL << channel);
+ }
+}
+
+/*!
+ * brief Gets the DMAC channel status.
+ *
+ * param base DMAC peripheral base address.
+ * param channel DMAC channel number.
+ * retval The mask of channel status. Users need to use the
+ * _dmac_channel_interrupt_flag type to decode the return variables.
+ */
+uint32_t DMAC_GetChannelInterruptStatus(DMAC_Type *base, dmac_channel_t channel)
+{
+ uint32_t retval = 0U;
+
+ /* Get ChannelTransferComplete bit flag */
+ if (((base->STATUS_TFRINT >> channel) & 0x1U) != 0U)
+ {
+ retval |= (uint32_t)kDMAC_ChannelInterruptFlagTransferComplete;
+ }
+
+ /* Get ChannelBlockTransferComplete bit flag */
+ if (((base->STATUS_BLOCKINT >> channel) & 0x1U) != 0U)
+ {
+ retval |= (uint32_t)kDMAC_ChannelInterruptBlockTransferComplete;
+ }
+
+ /* Get ChannelBusError bit flag */
+ if (((base->STATUS_BUSERRINT >> channel) & 0x1U) != 0U)
+ {
+ retval |= (uint32_t)kDMAC_ChannelInterruptFlagBusError;
+ }
+
+ /* Get ChannelAddressError bit flag */
+ if (((base->STATUS_ADDRERRINT >> channel) & 0x1U) != 0U)
+ {
+ retval |= (uint32_t)kDMAC_ChannelInterruptFlagAdressError;
+ }
+
+ return retval;
+}
+
+/*!
+ * brief Clears the DMAC channel status
+ *
+ * param base DMAC peripheral base address.
+ * param channel DMAC channel number.
+ * param status The mask of channel status to be cleared. Users need to use
+ * the defined _dmac_channel_interrupt_flag type.
+ */
+void DMAC_ClearChannelInterruptStatus(DMAC_Type *base, dmac_channel_t channel, uint32_t status)
+{
+ /* Clear ChannelTransferComplete bit flag */
+ if (0U != (status & (uint32_t)kDMAC_ChannelInterruptFlagTransferComplete))
+ {
+ base->STATUS_TFRINT = (1UL << channel);
+ }
+ /* Clear ChannelBlockTransferComplete bit flag */
+ if (0U != (status & (uint32_t)kDMAC_ChannelInterruptBlockTransferComplete))
+ {
+ base->STATUS_BLOCKINT = (1UL << channel);
+ }
+ /* Clear ChannelBusError bit flag */
+ if (0U != (status & (uint32_t)kDMAC_ChannelInterruptFlagBusError))
+ {
+ base->STATUS_BUSERRINT = (1UL << channel);
+ }
+ /* Clear ChannelAddressError bit flag */
+ if (0U != (status & (uint32_t)kDMAC_ChannelInterruptFlagAdressError))
+ {
+ base->STATUS_ADDRERRINT = (1UL << channel);
+ }
+}
+
+/*!
+ * brief Creates the DMAC channel handle.
+ *
+ * This function is called if using the transactional API for DMAC. This function
+ * initializes the internal state of the DMAC handle.
+ *
+ * param base DMAC peripheral base address.
+ * param handle DMAC handle pointer. The DMAC handle stores Callback function and
+ * parameters.
+ * param channel DMAC channel number.
+ *
+ */
+void DMAC_TransferCreateHandle(DMAC_Type *base, dmac_handle_t *handle, dmac_channel_t channel)
+{
+ assert(handle != NULL);
+
+ uint32_t dmacInstance = 0U;
+
+ /* Zero the handle */
+ (void)memset(handle, 0, sizeof(dmac_handle_t));
+
+ handle->base = base;
+ handle->channel = channel;
+
+ /* Get the DMAC instance number */
+ handle->state = (uint32_t)kDMAC_TransferStatusIdle;
+ dmacInstance = DMAC_GetInstance(base);
+ s_DMACHandle[channel] = handle;
+
+ /* Enable interrupt */
+ (void)EnableIRQ(s_dmacIRQNumber[dmacInstance]);
+}
+
+/*!
+ * brief Sets the DMAC Callback function.
+ *
+ * This callback is called in the DMAC IRQ handler. Use the callback to do something
+ * after the current transfer complete.
+ *
+ * param handle DMAC handle pointer.
+ * param callback DMAC callback function pointer.
+ * param userData Parameter for callback function. If it is not needed, just set to NULL.
+ */
+void DMAC_TransferSetCallback(dmac_handle_t *handle, dmac_transfer_callback_t callback, void *userData)
+{
+ assert(handle != NULL);
+
+ handle->callback = callback;
+ handle->userData = userData;
+}
+
+/*!
+ * @brief Submits the DMAC transfer configurations.
+ *
+ * @param handle DMAC handle pointer
+ * @param transfer pointer to user's DMAC channel configure structure, see _dmac_channel_interrupt_flag for detail
+ *
+ * @retval #kStatus_Success It means submit transfer request succeed
+ * @retval #kStatus_Fail It means submit transfer request failed
+ */
+status_t DMAC_TransferSubmit(dmac_handle_t *handle, dmac_channel_transfer_config_t *transfer)
+{
+ assert(handle != NULL);
+ assert(transfer != NULL);
+
+ if (handle->state == (uint32_t)kDMAC_TransferStatusBusy)
+ {
+ return kStatus_Fail;
+ }
+ DMAC_SetChannelTransferConfig(handle->base, handle->channel, transfer);
+ handle->state = kDMAC_TransferStatusBusy;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief DMAC starts transfer.
+ *
+ * This function enables the channel request. Users can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * param handle DMAC handle pointer.
+ */
+void DMAC_TransferStart(dmac_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ DMAC_StartChannel(handle->base, handle->channel);
+}
+
+/*!
+ * brief DMAC stops transfer.
+ *
+ * This function disables the channel request to pause the transfer. Users can call DMAC_StartTransfer()
+ * again to resume the transfer.
+ *
+ * param handle DMAC handle pointer.
+ */
+void DMAC_TransferStop(dmac_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ DMAC_StopChannel(handle->base, handle->channel);
+ handle->state = (uint32_t)kDMAC_TransferStatusIdle;
+}
+
+/*!
+ * brief DMAC IRQ handler for the transfer completion.
+ *
+ * param base DMAC peripheral base address.
+ */
+void DMAC_TransferHandleIRQ(DMAC_Type *base)
+{
+ dmac_handle_t *handle;
+ uint32_t startChannel = 0U;
+ uint32_t intStatusTfr, intStatusBlock, intStatusBusErr, intStatusAddrErr;
+
+ /* Get current unmasked interrupt status */
+ intStatusTfr = base->STATUS_TFRINT;
+ intStatusBlock = base->STATUS_BLOCKINT;
+ intStatusBusErr = base->STATUS_BUSERRINT;
+ intStatusAddrErr = base->STATUS_ADDRERRINT;
+
+ /* Clear the unmasked generated interrupts */
+ base->STATUS_TFRINT |= intStatusTfr;
+ base->STATUS_BLOCKINT |= intStatusBlock;
+ base->STATUS_BUSERRINT |= intStatusBusErr;
+ base->STATUS_ADDRERRINT |= intStatusAddrErr;
+
+ /* Find channels that have completed transfer */
+ for (uint32_t i = 0U; i < (uint32_t)FSL_FEATURE_MW_DMAC_MODULE_CHANNEL; i++)
+ {
+ handle = s_DMACHandle[i + startChannel];
+ /* Handle is not present */
+ if (NULL == handle)
+ {
+ continue;
+ }
+
+ if (((intStatusTfr & (0x01UL << i)) != 0U) && ((base->MASK_TFRINT & (0x01UL << i)) != 0U))
+ {
+ if (NULL != handle->callback)
+ {
+ handle->state = (uint32_t)kDMAC_TransferStatusIdle;
+ (handle->callback)(handle, handle->userData, kDMAC_ChannelInterruptFlagTransferComplete);
+ }
+ }
+
+ if (((intStatusBlock & (0x01UL << i)) != 0U) && ((base->MASK_BLOCKINT & (0x01UL << i)) != 0U))
+ {
+ if (NULL != handle->callback)
+ {
+ (handle->callback)(handle, handle->userData, kDMAC_ChannelInterruptBlockTransferComplete);
+ }
+ }
+
+ if ((intStatusBusErr & (0x01UL << i)) != 0U)
+ {
+ if (NULL != handle->callback)
+ {
+ (handle->callback)(handle, handle->userData, kDMAC_ChannelInterruptFlagBusError);
+ }
+ }
+
+ if ((intStatusAddrErr & (0x01UL << i)) != 0U)
+ {
+ if (NULL != handle->callback)
+ {
+ (handle->callback)(handle, handle->userData, kDMAC_ChannelInterruptFlagAdressError);
+ }
+ }
+ }
+}
+#if defined DMAC
+void DMAC_DriverIRQHandler(void);
+void DMAC_DriverIRQHandler(void)
+{
+ DMAC_TransferHandleIRQ(DMAC);
+
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/drivers/mw320/dmac/fsl_dmac.h b/drivers/mw320/dmac/fsl_dmac.h
new file mode 100644
index 000000000..3a14334e9
--- /dev/null
+++ b/drivers/mw320/dmac/fsl_dmac.h
@@ -0,0 +1,428 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_DMAC_H_
+#define _FSL_DMAC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup dmac
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief DMAC transfer type */
+typedef enum _dmac_channel_transfer_type
+{
+ kDMAC_ChannelTransferMemoryToMemory = 0x0U, /*!< Transfer type from memory to memory assume that the both source and
+ destination address are incremental */
+ kDMAC_ChannelTransferPeripheralToMemory, /*!< Transfer type peripher to memory assume that the source address is
+ fixed */
+ kDMAC_ChannelTransferMemoryToPeripheral, /*!< Transfer type from memory to peripheral assume that the destination
+ address is fixed */
+} dmac_channel_transfer_type_t;
+
+/*! @brief DMAC interrupt source
+ * @anchor _dmac_channel_interrupt_flag
+ */
+enum _dmac_channel_interrupt_flag
+{
+ kDMAC_ChannelInterruptFlagTransferComplete = 1U, /*!< Dmac transfer complete interrupt */
+ kDMAC_ChannelInterruptBlockTransferComplete = 2U, /*!< Block transfer complete interrupt */
+ kDMAC_ChannelInterruptFlagBusError = 4U, /*!< Bus Error interrupt */
+ kDMAC_ChannelInterruptFlagAdressError = 8U, /*!< Address Error interrupt */
+};
+
+/*!@brief dmac channel index */
+typedef enum _dmac_channel
+{
+ kDMAC_Channel0 = 0U, /*!< channel 0 define, priority level 0, the highest priority */
+ kDMAC_Channel1 = 1U, /*!< channel 1 define, priority level 0, the highest priority */
+ kDMAC_Channel2 = 2U, /*!< channel 2 define, priority level 0, the highest priority */
+ kDMAC_Channel3 = 3U, /*!< channel 3 define, priority level 0, the highest priority */
+ kDMAC_Channel4 = 4U, /*!< channel 4 define, priority level 1 */
+ kDMAC_Channel5 = 5U, /*!< channel 5 define, priority level 1 */
+ kDMAC_Channel6 = 6U, /*!< channel 6 define, priority level 1 */
+ kDMAC_Channel7 = 7U, /*!< channel 7 define, priority level 1 */
+ kDMAC_Channel8 = 8U, /*!< channel 8 define, priority level 2 */
+ kDMAC_Channel9 = 9U, /*!< channel 9 define, priority level 2 */
+ kDMAC_Channel10 = 10U, /*!< channel 10 define, priority level 2 */
+ kDMAC_Channel11 = 11U, /*!< channel 11 define, priority level 2 */
+ kDMAC_Channel12 = 12U, /*!< channel 12 define, priority level 3, the lowest priority */
+ kDMAC_Channel13 = 13U, /*!< channel 13 define, priority level 3, the lowest priority */
+ kDMAC_Channel14 = 14U, /*!< channel 14 define, priority level 3, the lowest priority */
+ kDMAC_Channel15 = 15U, /*!< channel 15 define, priority level 3, the lowest priority */
+ kDMAC_Channel16 = 16U, /*!< channel 16 define, priority level 0, the highest priority */
+ kDMAC_Channel17 = 17U, /*!< channel 17 define, priority level 0, the highest priority */
+ kDMAC_Channel18 = 18U, /*!< channel 18 define, priority level 0, the highest priority */
+ kDMAC_Channel19 = 19U, /*!< channel 19 define, priority level 0, the highest priority */
+ kDMAC_Channel20 = 20U, /*!< channel 20 define, priority level 1 */
+ kDMAC_Channel21 = 21U, /*!< channel 21 define, priority level 1 */
+ kDMAC_Channel22 = 22U, /*!< channel 22 define, priority level 1 */
+ kDMAC_Channel23 = 23U, /*!< channel 23 define, priority level 1 */
+ kDMAC_Channel24 = 24U, /*!< channel 24 define, priority level 2 */
+ kDMAC_Channel25 = 25U, /*!< channel 25 define, priority level 2 */
+ kDMAC_Channel26 = 26U, /*!< channel 26 define, priority level 2 */
+ kDMAC_Channel27 = 27U, /*!< channel 27 define, priority level 2 */
+ kDMAC_Channel28 = 28U, /*!< channel 28 define, priority level 3, the lowest priority */
+ kDMAC_Channel29 = 29U, /*!< channel 29 define, priority level 3, the lowest priority */
+ kDMAC_Channel30 = 30U, /*!< channel 30 define, priority level 3, the lowest priority */
+ kDMAC_Channel31 = 31U, /*!< channel 31 define, priority level 3, the lowest priority */
+} dmac_channel_t;
+
+/*! @brief DMAC transfer address increment definition */
+typedef enum _dmac_channel_address_increment_type
+{
+ kDMAC_ChannelAddressFix = 0U, /*!< Address Fix */
+ kDMAC_ChannelAddressIncrement, /*!< Address increment */
+} dmac_channel_address_increment_type_t;
+
+/*! @brief DMAC transfer width configuration */
+typedef enum _dmac_channel_transfer_width
+{
+ kDMAC_ChannelTransferWidth8Bits = 1U, /*!< Source/Destination data transfer width is 1 byte every time */
+ kDMAC_ChannelTransferWidth16Bits = 2U, /*!< Source/Destination data transfer width is 2 bytes every time */
+ kDMAC_ChannelTransferWidth32Bits = 4U, /*!< Source/Destination data transfer width is 4 bytes every time */
+} dmac_channel_transfer_width_t;
+
+/*! @brief DMAC transfer burst length definition */
+typedef enum _dmac_channel_burst_length
+{
+ kDMAC_ChannelBurstLength1DataWidth = 0U, /*!< Maximum burst transaction length 1 data width */
+ kDMAC_ChannelBurstLength4DataWidth, /*!< Maximum burst transaction length 4 data width */
+ kDMAC_ChannelBurstLength8DataWidth, /*!< Maximum burst transaction length 8 data width */
+ kDMAC_ChannelBurstLength16DataWidth, /*!< Maximum burst transaction length 16 data width */
+} dmac_channel_burst_length_t;
+
+/*! @brief dmac channel transfer configuration
+ *
+ * The transfer configuration structure support full feature configuration of the transfer control descriptor.
+ *
+ */
+typedef struct _dmac_channel_transfer_config
+{
+ void *srcAddr; /*!< source address */
+ void *destAddr; /*!< destination address */
+
+ dmac_channel_address_increment_type_t srcAddrIncrementType; /*!< Source address increment
+ kDMAC_ChannelAddressFix: No change
+ kDMAC_ChannelAddressIncrement: Increment */
+ dmac_channel_address_increment_type_t destAddrIncrementType; /*!< Destination address increment
+ kDMAC_ChannelAddressFix: No change
+ kDMAC_ChannelAddressIncrement: Increment */
+
+ dmac_channel_transfer_type_t transferType; /*!< Transfer type and flow control
+ kDMAC_ChannelTransferMemoryToMemory: Memory to Memory
+ kDMAC_ChannelTransferPeripheralToMemory: Memory to peripheral
+ kDMAC_ChannelTransferMemoryToPeripheral: Peripheral to memory */
+
+ dmac_channel_burst_length_t burstLength; /*!< Burst transaction length
+ kDMAC_ChannelBurstLength1DataWidth: 1 Data Width
+ kDMAC_ChannelBurstLength4DataWidth: 4 Data Width
+ kDMAC_ChannelBurstLength8DataWidth: 8 Data Width
+ kDMAC_ChannelBurstLength16DataWidth: 16 Data Width */
+
+ dmac_channel_transfer_width_t transferWidth; /*!< Transfer width
+ kDMAC_ChannelTransferWidth8Bits: 8 bits
+ kDMAC_ChannelTransferWidth16Bits: 16 bits
+ kDMAC_ChannelTransferWidth32Bits: 32 bits*/
+
+ uint32_t transferTotalBytes; /*!< Transfer totalbytes
+ 0~8191bytes
+ maximum transfer length (8k-1) bytes*/
+
+ uint32_t interruptMask; /*!< Interrupt Mask */
+} dmac_channel_transfer_config_t;
+
+/*! @brief dmac configuration structure */
+typedef struct _dmac_config
+{
+ uint32_t m2pAckDelayCycle; /*!< m2pAckDelayCycle for single write transaction to peripheral. The value should be
+ less than 1023, default value 12. */
+
+ dmac_channel_transfer_config_t
+ *channelTransferConfig[FSL_FEATURE_MW_DMAC_MODULE_CHANNEL]; /*!< channel transfer configuration pointer */
+
+ dmac_peripheral_number_t peripheralNumber[FSL_FEATURE_MW_DMAC_MODULE_CHANNEL]; /*!< Peripheral Number
+ Indicates the valid peripheral request number.The default value kDMAC_PeriphNum_None. */
+} dmac_config_t;
+
+/*! @brief handler for DMAC */
+typedef struct _dmac_handle dmac_handle_t;
+
+/*! @brief Define Callback function for DMAC
+ *
+ * @param handle DMAC handle pointer, users shall not touch the values inside.
+ * @param userData The callback user parameter pointer. Users can use this parameter to involve things users need to
+ * change in DMAC Callback function.
+ * @param status The mask of channel status . Users need to use the _dmac_channel_interrupt_status type.
+ * If the current loaded transfer done. In normal mode it means if all transfer done. In
+ * scatter gather mode, this parameter shows is the current transfer block in DMAC register is done.
+ */
+typedef void (*dmac_transfer_callback_t)(dmac_handle_t *handle, void *userData, uint32_t status);
+
+/*! @brief DMAC transfer handle structure */
+struct _dmac_handle
+{
+ volatile uint32_t state; /*!< channel transfer state */
+ dmac_transfer_callback_t callback; /*!< callback function */
+ void *userData; /*!< Callback function parameter. */
+ DMAC_Type *base; /*!< DMAC peripheral base address. */
+ dmac_channel_t channel; /*!< DMAC channel number. */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name DMAC Initialization and De-initialization interfaces
+ * @{
+ */
+
+/*!
+ * @brief Get default dmac configuration.
+ *
+ * @note This function will reset all of the configuration structure members to zero firstly,
+ * then apply default configurations to the structure.
+ *
+ * @param config pointer to user's DMAC configure structure, see @ref dmac_config_t for detail.
+ */
+void DMAC_GetDefaultConfig(dmac_config_t *config);
+
+/*!
+ * @brief DMAC initialization
+ *
+ * @param base DMAC peripheral base address.
+ * @param config pointer to user's DMAC config structure, see @ref dmac_config_t for detail.
+ */
+void DMAC_Init(DMAC_Type *base, dmac_config_t *config);
+
+/*!
+ * @brief DMAC De-initialization
+ *
+ * @param base DMAC peripheral base address.
+ */
+void DMAC_Deinit(DMAC_Type *base);
+
+/*! @} */
+
+/*!
+ * @name DMAC channel functional interfaces
+ * @{
+ */
+
+/*!
+ * @brief Get channel default transfer configuration.
+ *
+ * @param transfer pointer to user's DMAC channel configure structure, see @ref dmac_channel_transfer_config_t for
+ * detail.
+ * @param srcAddr source address, must be byte address.
+ * @param destAddr destination address, must be byte address.
+ * @param transferWidth the number of bits are transferred in each read/write.
+ * @param burstLength burst transaction length.
+ * @param transferTotalBytes transfer totalbytes 0~8191bytes maximum transfer length (8k-1) bytes.
+ * @param transferType DMAC channel transfer type.
+ */
+void DMAC_GetChannelDefaultTransferConfig(dmac_channel_transfer_config_t *transfer,
+ void *srcAddr,
+ void *destAddr,
+ dmac_channel_transfer_width_t transferWidth,
+ dmac_channel_burst_length_t burstLength,
+ uint32_t transferTotalBytes,
+ dmac_channel_transfer_type_t transferType);
+
+/*!
+ * @brief DMAC set channel transfer configurations
+ *
+ * @param base DMAC peripheral base address.
+ * @param channel DMAC channel number.
+ * @param transfer pointer to user's DMAC channel configure structure,see @ref dmac_channel_transfer_config_t for
+ * detail.
+ */
+void DMAC_SetChannelTransferConfig(DMAC_Type *base, dmac_channel_t channel, dmac_channel_transfer_config_t *transfer);
+
+/*!
+ * @brief start the dmac channel
+ *
+ * @param base DMAC peripheral base address.
+ * @param channel DMAC channel number.
+ */
+static inline void DMAC_StartChannel(DMAC_Type *base, dmac_channel_t channel)
+{
+ base->CHANNEL[channel].CHL_EN |= DMAC_CHL_EN_CHL_EN(1U);
+}
+
+/*!
+ * @brief stop the dmac channel
+ *
+ * @param base DMAC peripheral base address.
+ * @param channel DMAC channel number.
+ */
+static inline void DMAC_StopChannel(DMAC_Type *base, dmac_channel_t channel)
+{
+ base->CHANNEL[channel].CHL_STOP |= DMAC_CHL_STOP_CHL_STOP(1U);
+}
+
+/*!
+ * @brief DMAC ack delay cycle for single transfer in M2P transfer type.Only called when the transfer type is M2P.
+ *
+ * @param base DMAC peripheral base address.
+ * @param m2pAckDelayCycle for single write transaction to peripheral. The value should be less than 1023, default
+ * value 12.
+ */
+void DMAC_SetAckDelayCycle(DMAC_Type *base, uint32_t m2pAckDelayCycle);
+
+/*!
+ * @brief DMAC set peripheral number.
+ *
+ * @param base DMAC peripheral base address.
+ * @param channel DMAC channel number.
+ * @param peripheralNumber Indicates the valid peripheral request number, default value kDMAC_PeriphNum_None,
+ * see dmac_peripheral_number_t for detail.
+ */
+void DMAC_SetPeripheralNumber(DMAC_Type *base, dmac_channel_t channel, dmac_peripheral_number_t peripheralNumber);
+
+/*! @} */
+
+/*!
+ * @name DMAC channel interrupt Interfaces
+ * @{
+ */
+/*!
+ * @brief enables the dmac channel interrupts
+ *
+ * @param base DMAC peripheral base address.
+ * @param channel DMAC channel number.
+ * @param interruptsMask the mask is a logical OR of enumerator members see @ref _dmac_channel_interrupt_flag.
+ */
+void DMAC_EnableChannelInterrupts(DMAC_Type *base, dmac_channel_t channel, uint32_t interruptsMask);
+
+/*!
+ * @brief disables the dmac channel interrupts
+ *
+ * @param base DMAC peripheral base address.
+ * @param channel DMAC channel number.
+ * @param interruptsMask the mask is a logical OR of enumerator members see @ref _dmac_channel_interrupt_flag.
+ */
+void DMAC_DisableChannelInterrupts(DMAC_Type *base, dmac_channel_t channel, uint32_t interruptsMask);
+
+/*! @} */
+
+/*!
+ * @name DMAC channel Status Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Gets the DMAC channel status.
+ *
+ * @param base DMAC peripheral base address.
+ * @param channel DMAC channel number.
+ * @retval The mask of channel status. Users need to use the @ref
+ * _dmac_channel_interrupt_flag type to decode the return variables.
+ */
+uint32_t DMAC_GetChannelInterruptStatus(DMAC_Type *base, dmac_channel_t channel);
+
+/*!
+ * @brief Clears the DMAC channel status.
+ *
+ * @param base DMAC peripheral base address.
+ * @param channel DMAC channel number.
+ * @param status The mask of channel status to be cleared. Users need to use
+ * the defined @ref _dmac_channel_interrupt_flag type.
+ */
+void DMAC_ClearChannelInterruptStatus(DMAC_Type *base, dmac_channel_t channel, uint32_t status);
+
+/*! @} */
+
+/*!
+ * @name DMAC Transactional Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Creates the DMAC channel handle.
+ *
+ * This function is called if using the transactional API for DMAC. This function
+ * initializes the internal state of the DMAC handle.
+ *
+ * @param base DMAC peripheral base address.
+ * @param handle DMAC handle pointer. The DMAC handle stores Callback function and
+ * parameters.
+ * @param channel DMAC channel number.
+ *
+ */
+void DMAC_TransferCreateHandle(DMAC_Type *base, dmac_handle_t *handle, dmac_channel_t channel);
+
+/*!
+ * @brief Sets the DMAC Callback function.
+ *
+ * This callback is called in the DMAC IRQ handler. Use the callback to do something
+ * after the current transfer complete.
+ *
+ * @param handle DMAC handle pointer.
+ * @param callback DMAC callback function pointer.
+ * @param userData Parameter for callback function. If it is not needed, just set to NULL.
+ */
+void DMAC_TransferSetCallback(dmac_handle_t *handle, dmac_transfer_callback_t callback, void *userData);
+
+/*!
+ * @brief Submits the DMAC transfer configurations.
+ *
+ * @param handle DMAC handle pointer
+ * @param transfer pointer to user's DMAC channel configure structure,see @ref dmac_channel_transfer_config_t for
+ * detail.
+ *
+ * @retval #kStatus_Success It means submit transfer request succeed
+ * @retval #kStatus_Fail It means submit transfer request failed
+ */
+status_t DMAC_TransferSubmit(dmac_handle_t *handle, dmac_channel_transfer_config_t *transfer);
+
+/*!
+ * @brief DMAC starts transfer.
+ *
+ * This function enables the channel request. Users can call this function after submitting the transfer request
+ * or before submitting the transfer request.
+ *
+ * @param handle DMAC handle pointer.
+ */
+void DMAC_TransferStart(dmac_handle_t *handle);
+
+/*!
+ * @brief DMAC stops transfer.
+ *
+ * This function disables the channel request to pause the transfer. Users can call DMAC_StartTransfer()
+ * again to resume the transfer.
+ *
+ * @param handle DMAC handle pointer.
+ */
+void DMAC_TransferStop(dmac_handle_t *handle);
+
+/*!
+ * @brief DMAC IRQ handler for the transfer completion.
+ *
+ * @param base DMAC peripheral base address.
+ */
+void DMAC_TransferHandleIRQ(DMAC_Type *base);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /*_FSL_DMAC_H_*/
diff --git a/drivers/mw320/flashc/driver_mw_flashc.cmake b/drivers/mw320/flashc/driver_mw_flashc.cmake
new file mode 100644
index 000000000..8248e69b1
--- /dev/null
+++ b/drivers/mw320/flashc/driver_mw_flashc.cmake
@@ -0,0 +1,14 @@
+#Description: MW_FLASHC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_flashc component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_flashc.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/flashc/fsl_flashc.c b/drivers/mw320/flashc/fsl_flashc.c
new file mode 100644
index 000000000..ce2902db8
--- /dev/null
+++ b/drivers/mw320/flashc/fsl_flashc.c
@@ -0,0 +1,561 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flashc.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flashc"
+#endif
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Base pointer array */
+static FLASHC_Type *const s_flashcBases[] = FLASHC_BASE_PTRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Get the instance number for FLASHC.
+ *
+ * param base FLASHC base pointer.
+ */
+uint32_t FLASHC_GetInstance(FLASHC_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_flashcBases); instance++)
+ {
+ if (s_flashcBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_flashcBases));
+
+ return instance;
+}
+
+/*!
+ * brief Initializes FLASHC, it override the HW configuration (FCCR.CMD_TYPE) if it is enabled.
+ *
+ * param base FLASHC base pointer.
+ * param config FLASHC configure.
+ */
+void FLASHC_Init(FLASHC_Type *base, flashc_config_t *config)
+{
+ uint32_t temp = 0x00U;
+
+ /* Set instruction count*/
+ temp |= FLASHC_FCCR2_INSTR_CNT(config->instrCnt);
+ /* Set address count*/
+ temp |= FLASHC_FCCR2_ADDR_CNT(config->addrCnt);
+ /* Set read mode count */
+ temp |= FLASHC_FCCR2_RM_CNT(config->readModeCnt);
+ /* Set dummy count */
+ temp |= FLASHC_FCCR2_DUMMY_CNT(config->dummyCnt);
+ /* Set data length mode */
+ temp |= FLASHC_FCCR2_BYTE_LEN(config->byteLen);
+ /* Set address pin number */
+ temp |= FLASHC_FCCR2_ADDR_PIN(config->addrPinMode);
+ /* Set data pin number */
+ temp |= FLASHC_FCCR2_DATA_PIN(config->dataPinMode);
+ base->FCCR2 = temp;
+
+ /* Set read mode */
+ base->FRMR = FLASHC_FRMR_RDMODE(config->readMode);
+
+ /* Set instruction */
+ base->FINSTR = FLASHC_FINSTR_INSTR(config->instrucion);
+
+ /* Set timing configuration. */
+ FLASHC_SetTimingConfig(base, &config->timingConfig);
+}
+
+/*!
+ * @brief De-initializes FLASHC.
+ *
+ * @param base FLASHC base pointer.
+ */
+void FLASHC_Deinit(FLASHC_Type *base)
+{
+}
+
+/*!
+ * brief Gets default settings for FLASHC.
+ *
+ * param config FLASHC configuration structure.
+ */
+void FLASHC_GetDefaultConfig(flashc_config_t *config)
+{
+ /* Initializes the configure structure to zero. */
+ (void)memset(config, 0x00U, sizeof(*config));
+
+ config->timingConfig.clockPhase = kFLASHC_ClockPhaseRising;
+ config->timingConfig.clockPolarity = kFLASHC_ClockPolarityLow;
+ config->timingConfig.preScaler = kFLASHC_ClockDiv1;
+ config->timingConfig.captEdge = kFLASHC_CaptureEdgeFirst;
+ config->timingConfig.clkOutDly = 0x00U;
+ config->timingConfig.clkInDly = 0x00U;
+ config->timingConfig.dinDly = 0x00U;
+
+ config->dataPinMode = kFLASHC_DataPinSingle;
+ config->addrPinMode = kFLASHC_AddrPinSingle;
+ config->byteLen = kFLASHC_TransferLength1Byte;
+ config->dummyCnt = kFLASHC_DummyCnt0Byte;
+ config->readModeCnt = kFLASHC_ReadModeCnt0Byte;
+ config->readMode = 0x00U;
+ config->addrCnt = kFLASHC_AddressCnt0Byte;
+ config->instrCnt = kFLASHC_InstructionCnt0Byte;
+ config->instrucion = 0x00U;
+}
+
+/*!
+ * brief Configure the timing of the FLASHC.
+ *
+ * param base FLASHC base pointer.
+ * param config FLASHC timing configure.
+ */
+void FLASHC_SetTimingConfig(FLASHC_Type *base, flashc_timing_config_t *config)
+{
+ uint32_t temp = 0x00U;
+
+ temp = FLASHC->FCCR;
+ /* Set FLASHC clock phase and polarity. */
+ temp = ((temp & ~FLASHC_FCCR_CLK_PHA_MASK) | FLASHC_FCCR_CLK_PHA(config->clockPhase)) |
+ ((temp & ~FLASHC_FCCR_CLK_POL_MASK) | FLASHC_FCCR_CLK_POL(config->clockPolarity));
+
+ /* Set FLASHC clock prescaler */
+ temp = ((temp & ~FLASHC_FCCR_CLK_PRESCALE_MASK) | FLASHC_FCCR_CLK_PRESCALE(config->preScaler));
+
+ FLASHC->FCCR = temp;
+
+ temp = FLASHC->FCTR;
+
+ /* Set FLASHC capture clock edge */
+ temp = ((temp & ~FLASHC_FCTR_CLK_CAPT_EDGE_MASK) | FLASHC_FCTR_CLK_CAPT_EDGE(config->captEdge));
+
+ /* set clock out delay */
+ temp = ((temp & ~FLASHC_FCTR_CLK_OUT_DLY_MASK) | FLASHC_FCTR_CLK_OUT_DLY(config->clkOutDly));
+
+ /* set clock in delay */
+ temp = ((temp & ~FLASHC_FCTR_CLK_IN_DLY_MASK) | FLASHC_FCTR_CLK_IN_DLY(config->clkInDly));
+
+ /* set data in delay */
+ temp = ((temp & ~FLASHC_FCTR_DIN_DLY_MASK) | FLASHC_FCTR_DIN_DLY(config->dinDly));
+
+ FLASHC->FCTR = temp;
+}
+
+/*!
+ * brief Flush the Cache.
+ *
+ * param base FLASHC base pointer.
+ * return return status.
+ */
+status_t FLASHC_FlushCache(FLASHC_Type *base)
+{
+ status_t status = kStatus_Fail;
+ volatile uint32_t cnt = 0U;
+
+ /* Cache Line Flush. */
+ FLASHC->FCCR |= FLASHC_FCCR_CACHE_LINE_FLUSH_MASK;
+
+ while (cnt < 0x200000U)
+ {
+ if ((FLASHC->FCCR & FLASHC_FCCR_CACHE_LINE_FLUSH_MASK) == 0U)
+ {
+ status = kStatus_Success;
+ break;
+ }
+
+ cnt++;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Enable Flash Cache Hit Counters.
+ *
+ * param base FLASHC base pointer.
+ * param enable true/false.
+ */
+void FLASHC_EnableCacheHitCounter(FLASHC_Type *base, bool enable)
+{
+ if (enable == true)
+ {
+ FLASHC->FCACR |= FLASHC_FCACR_HIT_CNT_EN_MASK;
+ }
+ else
+ {
+ FLASHC->FCACR &= ~FLASHC_FCACR_HIT_CNT_EN_MASK;
+ }
+}
+
+/*!
+ * brief Enable Flash Cache Miss Counters.
+ *
+ * param base FLASHC base pointer.
+ * param enable true/false.
+ */
+void FLASHC_EnableCacheMissCounter(FLASHC_Type *base, bool enable)
+{
+ if (enable == true)
+ {
+ FLASHC->FCACR |= FLASHC_FCACR_MISS_CNT_EN_MASK;
+ }
+ else
+ {
+ FLASHC->FCACR &= ~FLASHC_FCACR_MISS_CNT_EN_MASK;
+ }
+}
+
+/*!
+ * brief Enable Flash Cache Miss Counters.
+ *
+ * param base FLASHC base pointer.
+ * param hitCnt cache hit counter.
+ * param missCnt cache miss counter.
+ */
+void FLASHC_GetCacheCounter(FLASHC_Type *base, uint32_t *hitCnt, uint32_t *missCnt)
+{
+ assert(hitCnt != NULL);
+ assert(missCnt != NULL);
+
+ /* Get cache hit counter. */
+ *hitCnt = FLASHC->FCHCR;
+ /* Get cache miss counter. */
+ *missCnt = FLASHC->FCMCR;
+}
+
+/*!
+ * brief Reset Flash Controller Cache Counters.
+ *
+ * param base FLASHC base pointer.
+ */
+void FLASHC_ResetCacheCounter(FLASHC_Type *base)
+{
+ /* Clear cache hit counter. */
+ FLASHC->FCHCR = 0x00U;
+ /* Clear cache miss counter. */
+ FLASHC->FCMCR = 0x00U;
+}
+
+/*!
+ * brief Use offset address for flash memory access and set the offset address.
+ *
+ * param base FLASHC base pointer.
+ * param address offset address.
+ */
+void FLASHC_EnableOffsetAddr(FLASHC_Type *base, uint32_t address)
+{
+ base->FCACR |= FLASHC_FCACR_OFFSET_EN_MASK;
+
+ base->FAOFFR = address;
+}
+
+/*!
+ * brief Exit dual continuous read mode.
+ *
+ * param base FLASHC base pointer.
+ * return return status.
+ */
+status_t FLASHC_ExitDualContReadMode(FLASHC_Type *base)
+{
+ volatile uint32_t cnt = 0x00U;
+ uint32_t temp = 0x00U;
+ uint32_t cacheMode;
+
+ /*Backup cache mode. */
+ cacheMode = (base->FCCR & FLASHC_FCCR_CACHE_EN_MASK) >> FLASHC_FCCR_CACHE_EN_SHIFT;
+ /* Disable cache mode. */
+ base->FCCR &= ~FLASHC_FCCR_CACHE_EN_MASK;
+
+ /* clear the continuous read mode exit status bit. */
+ base->FCSR = FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK;
+
+ temp = base->FCCR;
+ /* Set hardware command for exit from dual read mode. */
+ base->FCCR = (temp & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(kFLASHC_HardwareCmdExitFromDual);
+
+ while (cnt < 0x200000U)
+ {
+ if ((base->FCSR & FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK) == FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK)
+ {
+ /* clear the continuous read mode exit status bit. */
+ base->FCSR = FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK;
+ base->FCCR |= FLASHC_FCCR_CACHE_EN(cacheMode);
+ return kStatus_Success;
+ }
+
+ cnt++;
+ }
+
+ /* Restore cache mode. */
+ base->FCCR |= FLASHC_FCCR_CACHE_EN(cacheMode);
+
+ return kStatus_Fail;
+}
+
+/*!
+ * brief Exit quad continuous read mode.
+ *
+ * param base FLASHC base pointer.
+ * return return status.
+ */
+status_t FLASHC_ExitQuadContReadMode(FLASHC_Type *base)
+{
+ volatile uint32_t cnt = 0x00U;
+ uint32_t temp = 0x00U;
+ uint32_t cacheMode;
+
+ /*Backup cache mode. */
+ cacheMode = (base->FCCR & FLASHC_FCCR_CACHE_EN_MASK) >> FLASHC_FCCR_CACHE_EN_SHIFT;
+ /* Disable cache mode. */
+ base->FCCR &= ~FLASHC_FCCR_CACHE_EN_MASK;
+
+ /* clear the continuous read mode exit status bit. */
+ base->FCSR = FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK;
+
+ temp = base->FCCR;
+ /* Set hardware command for exit from quad read mode. */
+ base->FCCR = (temp & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(kFLASHC_HardwareCmdExitFromQuad);
+
+ while (cnt < 0x200000U)
+ {
+ if ((base->FCSR & FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK) == FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK)
+ {
+ /* clear the continuous read mode exit status bit. */
+ base->FCSR = FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK;
+ base->FCCR |= FLASHC_FCCR_CACHE_EN(cacheMode);
+ return kStatus_Success;
+ }
+
+ cnt++;
+ }
+
+ /* Restore cache mode. */
+ base->FCCR |= FLASHC_FCCR_CACHE_EN(cacheMode);
+
+ return kStatus_Fail;
+}
+
+/*!
+ * brief Enable QSPI pad.
+ *
+ * param base FLASHC base pointer.
+ * return return status.
+ */
+status_t FLASHC_EnableQSPIPad(FLASHC_Type *base)
+{
+ status_t status = kStatus_Fail;
+ uint32_t currentMode = 0x00U;
+ uint32_t exitMethod = 0x00U;
+
+ status = FLASHC_FlushCache(base);
+ if (status != kStatus_Success)
+ {
+ return kStatus_Fail;
+ }
+
+ currentMode = (base->FCCR & FLASHC_FCCR_CMD_TYPE_MASK) >> FLASHC_FCCR_CMD_TYPE_SHIFT;
+
+ switch (currentMode)
+ {
+ case kFLASHC_HardwareCmdFastReadDualOutput:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kFLASHC_HardwareCmdFastReadDualIO:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kFLASHC_HardwareCmdFastReadDualIOContinuous:
+ exitMethod = kFLASHC_HardwareCmdExitFromDual;
+ break;
+ case kFLASHC_HardwareCmdFastReadQuadOutput:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kFLASHC_HardwareCmdFastReadQuadIO:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kFLASHC_HardwareCmdFastReadQuadIOContinuous:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kFLASHC_HardwareCmdWordReadQuadIO:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kFLASHC_HardwareCmdWordReadQuadIOContinuous:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kFLASHC_HardwareCmdOctalWordReadQuadIO:
+ SUPPRESS_FALL_THROUGH_WARNING();
+ case kFLASHC_HardwareCmdOctalWordReadQuadIOContinuous:
+ exitMethod = kFLASHC_HardwareCmdExitFromQuad;
+ break;
+ default:
+ assert(NULL);
+ break;
+ }
+
+ if (exitMethod == (uint8_t)kFLASHC_HardwareCmdExitFromQuad)
+ {
+ status = FLASHC_ExitQuadContReadMode(base);
+ }
+ else if (exitMethod == (uint8_t)kFLASHC_HardwareCmdExitFromDual)
+ {
+ status = FLASHC_ExitDualContReadMode(base);
+ }
+ else
+ {
+ ; /* Intentional empty for MISRA C-2012 rule 15.7. */
+ }
+
+ if (status == kStatus_Success)
+ {
+ /* Select PAD to QSPI/ */
+ base->FCCR &= ~FLASHC_FCCR_FLASHC_PAD_EN_MASK;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Enable FLASHC pad.
+ *
+ * param base FLASHC base pointer.
+ * param mode FLASHC read mode.
+ * param jedecID JEDEC ID.
+ */
+void FLASHC_EnableFLASHCPad(FLASHC_Type *base, flashc_hw_cmd_t mode, uint32_t jedecID)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->FCCR;
+ /* Select PAD to FLASHC */
+ temp |= FLASHC_FCCR_FLASHC_PAD_EN_MASK;
+
+ /* Check continuous read mode requirement is supported or not. */
+ if (kFLASHC_HardwareCmdFastReadDualIOContinuous == mode)
+ {
+ switch (jedecID)
+ {
+ case 0xef4014:
+ case 0xef4015:
+ case 0xef4016:
+ case 0xef4017:
+ case 0xef4018:
+ case 0xc84016:
+ case 0xc86016:
+ case 0xc84018:
+ /*
+ * For continuous quad read mode, flash chip read mode bits
+ * [M7-0] needs to have 0x20h value (bit 4/5 set). This is
+ * limitation of flash controller in 88MW300. In addition to
+ * exit from continuous read mode, command 0xFFh is required.
+ * Please check flash part datasheet before updating this.
+ */
+ break;
+ default:
+ mode = kFLASHC_HardwareCmdFastReadDualIO;
+ break;
+ }
+ }
+
+ /* Check continuous read mode requirement is supported or not. */
+ if (kFLASHC_HardwareCmdFastReadQuadIOContinuous == mode)
+ {
+ switch (jedecID)
+ {
+ case 0xef4014:
+ case 0xef4015:
+ case 0xef4016:
+ case 0xef4017:
+ case 0xef4018:
+ case 0xc84016:
+ case 0xc86016:
+ case 0xc84018:
+ /*
+ * For continuous quad read mode, flash chip read mode bits
+ * [M7-0] needs to have 0x20h value (bit 4/5 set). This is
+ * limitation of flash controller in 88MW300. In addition to
+ * exit from continuous read mode, command 0xFFh is required.
+ * Please check flash part datasheet before updating this.
+ */
+ break;
+ default:
+ mode = kFLASHC_HardwareCmdFastReadQuadIO;
+ break;
+ }
+ }
+
+ /* Set hardware command for FLASHC read mode. */
+ base->FCCR = (temp & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(mode);
+}
+
+/*!
+ * brief Set quad mode read command.
+ *
+ * param base FLASHC base pointer.
+ * param jedecID JEDEC ID.
+ */
+void FLASH_SetQuadModeReadCmd(FLASHC_Type *base, uint32_t jedecID)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->FCCR;
+
+ switch (jedecID)
+ {
+ case 0xef4014:
+ case 0xef4015:
+ case 0xef4016:
+ case 0xef4017:
+ case 0xef4018:
+ case 0xc84016:
+ case 0xc86016:
+ case 0xc84018:
+ /*
+ * For continuous quad read mode, flash chip read mode bits
+ * [M7-0] needs to have 0x20h value (bit 4/5 set). This is
+ * limitation of flash controller in 88MW300. In addition to
+ * exit from continuous read mode, command 0xFFh is required.
+ * Please check flash part datasheet before updating this.
+ */
+ base->FCCR =
+ (temp & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(kFLASHC_HardwareCmdFastReadQuadIOContinuous);
+ break;
+ case 0xc84015:
+ case 0xc22014:
+ case 0xc22016:
+ case 0xc22017:
+ case 0xc22018:
+ case 0xc22810:
+ case 0xc22811:
+ case 0xc22812:
+ case 0xc22813:
+ case 0xc22814:
+ case 0xc22815:
+ case 0xc22816:
+ case 0xc22817:
+ case 0xc22310:
+ case 0xc22311:
+ case 0xc22312:
+ case 0xc22313:
+ case 0xc22314:
+ case 0xc22315:
+ base->FCCR = (temp & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(kFLASHC_HardwareCmdFastReadQuadIO);
+ break;
+ default:
+ assert(NULL);
+ break;
+ }
+}
diff --git a/drivers/mw320/flashc/fsl_flashc.h b/drivers/mw320/flashc/fsl_flashc.h
new file mode 100644
index 000000000..f83150975
--- /dev/null
+++ b/drivers/mw320/flashc/fsl_flashc.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_FLASHC_H_
+#define _FSL_FLASHC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flashc_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief FLASHC configuration way selection */
+typedef enum
+{
+ kFLASHC_HardwareConfig, /*!< Use hardware configuration */
+ kFLASHC_SoftwareConfig, /*!< Use software configuration */
+} flashc_config_selection_t;
+
+/*! @brief FLASHC hardware configuration */
+typedef enum
+{
+ kFLASHC_HardwareCmdNormalRead, /*!< read data(0x03) */
+ kFLASHC_HardwareCmdFastRead, /*!< fast read data(0x0B) */
+ kFLASHC_HardwareCmdFastReadDualOutput, /*!< fast read dual output (0x3B) */
+ kFLASHC_HardwareCmdFastReadQuadOutput, /*!< fast read quad output (0x6B) */
+ kFLASHC_HardwareCmdFastReadDualIO, /*!< fast read dual I/O (0xBB) */
+ kFLASHC_HardwareCmdFastReadDualIOContinuous, /*!< fast read dual I/O with continuous read (0xBB) */
+ kFLASHC_HardwareCmdFastReadQuadIO, /*!< fast read quad I/O (0xEB) */
+ kFLASHC_HardwareCmdFastReadQuadIOContinuous, /*!< fast read quad I/O with continuous read (0xEB) */
+ kFLASHC_HardwareCmdWordReadQuadIO, /*!< word read quad I/O (0xE7) */
+ kFLASHC_HardwareCmdWordReadQuadIOContinuous, /*!< word read quad I/O with continuous read(0xE7) */
+ kFLASHC_HardwareCmdOctalWordReadQuadIO, /*!< Octal word read quad I/O (0xE3) */
+ kFLASHC_HardwareCmdOctalWordReadQuadIOContinuous, /*!< Octal word read quad I/O with continuous read(0xE3) */
+ kFLASHC_HardwareCmdExitFromDual, /*!< exit from continuous read mode (dual) */
+ kFLASHC_HardwareCmdExitFromQuad, /*!< exit from continuous read mode (quad) */
+} flashc_hw_cmd_t;
+
+/*! @brief FLASHC data pin */
+typedef enum _flashc_data_pin
+{
+ kFLASHC_DataPinSingle, /*!< Use 1 serial interface pin. */
+ kFLASHC_DataPinDual, /*!< Use 2 serial interface pins. */
+ kFLASHC_DataPinQuad, /*!< Use 4 serial interface pins. */
+} flashc_data_pin_t;
+
+/*! @brief FLASHC address pin */
+typedef enum _flashc_addr_pin
+{
+ kFLASHC_AddrPinSingle, /*!< Use 1 serial interface pin */
+ kFLASHC_AddrPinAsData, /*!< Use the number of pins as indicated in DATA_PIN */
+} flashc_addr_pin_t;
+
+/*! @brief FLASHC clock phase */
+typedef enum _flashc_clock_phase
+{
+ kFLASHC_ClockPhaseRising, /*!< Data is latched on the rising edge of the serial clock. */
+ kFLASHC_ClockPhaseFalling, /*!< Data is latched on the falling edge of the serial clock. */
+} flashc_clock_phase_t;
+
+/*! @brief FLASHC clock polarity */
+typedef enum _flashc_clock_polarity
+{
+ kFLASHC_ClockPolarityLow, /*!< Inactive state of serial clock is low. */
+ kFLASHC_ClockPolarityHigh, /*!< Inactive state of serial clock is high. */
+} flashc_clock_polarity_t;
+
+/*! @brief FLASHC capture clock edge */
+typedef enum _flashc_capture_edge
+{
+ kFLASHC_CaptureEdgeFirst, /*!< Input data is captured on the first edge of the serial clock */
+ kFLASHC_CaptureEdgeSecond, /*!< Input data is captured on the second edge of the serial clock */
+} flashc_capture_edge_t;
+
+/*! @brief FLASHC transfer length */
+typedef enum _flashc_transfer_length
+{
+ kFLASHC_TransferLength1Byte, /*!< 1 byte in each serial interface I/O transfer */
+ kFLASHC_TransferLength4Bytes, /*!< 4 bytes in each serial interface I/O transfer */
+} flashc_transfer_length_t;
+
+/*! @brief FLASHC clock prescaler */
+typedef enum _flashc_clock_prescaler
+{
+ kFLASHC_ClockDiv1 = 0x1, /*!< Serial interface clock prescaler is SPI clock / 1 */
+ kFLASHC_ClockDiv2 = 0x2, /*!< Serial interface clock prescaler is SPI clock / 2 */
+ kFLASHC_ClockDiv3 = 0x3, /*!< Serial interface clock prescaler is SPI clock / 3 */
+ kFLASHC_ClockDiv4 = 0x4, /*!< Serial interface clock prescaler is SPI clock / 4 */
+ kFLASHC_ClockDiv5 = 0x5, /*!< Serial interface clock prescaler is SPI clock / 5 */
+ kFLASHC_ClockDiv6 = 0x6, /*!< Serial interface clock prescaler is SPI clock / 6 */
+ kFLASHC_ClockDiv7 = 0x7, /*!< Serial interface clock prescaler is SPI clock / 7 */
+ kFLASHC_ClockDiv8 = 0x8, /*!< Serial interface clock prescaler is SPI clock / 8 */
+ kFLASHC_ClockDiv9 = 0x9, /*!< Serial interface clock prescaler is SPI clock / 9 */
+ kFLASHC_ClockDiv10 = 0xA, /*!< Serial interface clock prescaler is SPI clock / 10 */
+ kFLASHC_ClockDiv11 = 0xB, /*!< Serial interface clock prescaler is SPI clock / 11 */
+ kFLASHC_ClockDiv12 = 0xC, /*!< Serial interface clock prescaler is SPI clock / 12 */
+ kFLASHC_ClockDiv13 = 0xD, /*!< Serial interface clock prescaler is SPI clock / 13 */
+ kFLASHC_ClockDiv14 = 0xE, /*!< Serial interface clock prescaler is SPI clock / 14 */
+ kFLASHC_ClockDiv15 = 0xF, /*!< Serial interface clock prescaler is SPI clock / 15 */
+ kFLASHC_ClockDiv16 = 0x18, /*!< Serial interface clock prescaler is SPI clock / 16 */
+ kFLASHC_ClockDiv18 = 0x19, /*!< Serial interface clock prescaler is SPI clock / 18 */
+ kFLASHC_ClockDiv20 = 0x1A, /*!< Serial interface clock prescaler is SPI clock / 20 */
+ kFLASHC_ClockDiv22 = 0x1B, /*!< Serial interface clock prescaler is SPI clock / 22 */
+ kFLASHC_ClockDiv24 = 0x1C, /*!< Serial interface clock prescaler is SPI clock / 24 */
+ kFLASHC_ClockDiv26 = 0x1D, /*!< Serial interface clock prescaler is SPI clock / 26 */
+ kFLASHC_ClockDiv28 = 0x1E, /*!< Serial interface clock prescaler is SPI clock / 28 */
+ kFLASHC_ClockDiv30 = 0x1F, /*!< Serial interface clock prescaler is SPI clock / 30 */
+} flashc_clock_prescaler_t;
+
+/*! @brief FLASHC Instruction Count */
+typedef enum _flashc_instruction_count
+{
+ kFLASHC_InstructionCnt0Byte, /*!< Instrution count: 0 byte */
+ kFLASHC_InstructionCnt1Byte, /*!< Instrution count: 1 byte */
+ kFLASHC_InstructionCnt2Byte, /*!< Instrution count: 2 bytes */
+} flashc_instruction_count_t;
+
+/*! @brief FLASHC Address Count */
+typedef enum _flashc_address_count
+{
+ kFLASHC_AddressCnt0Byte, /*!< Address count: 0 byte */
+ kFLASHC_AddressCnt1Byte, /*!< Address count: 1 byte */
+ kFLASHC_AddressCnt2Byte, /*!< Address count: 2 bytes */
+ kFLASHC_AddressCnt3Byte, /*!< Address count: 3 bytes */
+ kFLASHC_AddressCnt4Byte, /*!< Address count: 4 bytes */
+} flashc_address_count_t;
+
+/*! @brief FLASHC Read Mode Count */
+typedef enum _flashc_read_mode_count
+{
+ kFLASHC_ReadModeCnt0Byte, /*!< Read mode count: 0 byte */
+ kFLASHC_ReadModeCnt1Byte, /*!< Read mode count: 1 byte */
+ kFLASHC_ReadModeCnt2Byte, /*!< Read mode count: 2 bytes */
+} flashc_read_mode_count_t;
+
+/*! @brief FLASHC Dummy Count */
+typedef enum _flashc_dummy_count
+{
+ kFLASHC_DummyCnt0Byte, /*!< Dummy count: 0 byte */
+ kFLASHC_DummyCnt1Byte, /*!< Dummy count: 1 byte */
+ kFLASHC_DummyCnt2Byte, /*!< Dummy count: 2 bytes */
+} flashc_dummy_count_t;
+
+/*! @brief FLASHC timing configure structure*/
+typedef struct _flashc_timing_config
+{
+ flashc_clock_phase_t clockPhase; /*!< Serial Interface Clock Phase. */
+ flashc_clock_polarity_t clockPolarity; /*!< Serial Interface Clock Polarity. */
+ flashc_clock_prescaler_t preScaler; /*!< Configure FLASHC prescaler for serial interface */
+ flashc_capture_edge_t captEdge; /*!< Configure FLASHC capture clock edge */
+ uint8_t clkOutDly; /*!< Delay on the outgoing clock to flash */
+ uint8_t clkInDly; /*!< Delay on the clock that capture read data from flash */
+ uint8_t dinDly; /*!< Delay on the incoming data from flash */
+} flashc_timing_config_t;
+
+/*! @brief FLASHC configure structure*/
+typedef struct _flashc_config
+{
+ flashc_timing_config_t timingConfig; /*!< Timing configuration */
+ flashc_data_pin_t dataPinMode; /*!< Configure FLASHC data pin */
+ flashc_addr_pin_t addrPinMode; /*!< Configure FLASHC addr pin */
+ flashc_transfer_length_t byteLen; /*!< Configure FLASHC length each serial transfer */
+ flashc_dummy_count_t dummyCnt; /*!< Dummy count */
+ flashc_read_mode_count_t readModeCnt; /*!< read mode count */
+ uint16_t readMode; /*!< read mode */
+ flashc_address_count_t addrCnt; /*!< address count */
+ flashc_instruction_count_t instrCnt; /*!< instruction count */
+ uint16_t instrucion; /*!< instruction */
+} flashc_config_t;
+
+/******************************************************************************
+ * API
+ *****************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Get the instance number for FLASHC.
+ *
+ * @param base FLASHC base pointer.
+ */
+uint32_t FLASHC_GetInstance(FLASHC_Type *base);
+
+/*!
+ * @brief Initializes FLASHC, it override the HW configuration (FCCR.CMD_TYPE) if it is enabled.
+ *
+ * @param base FLASHC base pointer.
+ * @param config FLASHC configure.
+ */
+void FLASHC_Init(FLASHC_Type *base, flashc_config_t *config);
+
+/*!
+ * @brief De-initializes FLASHC.
+ *
+ * @param base FLASHC base pointer.
+ */
+void FLASHC_Deinit(FLASHC_Type *base);
+
+/*!
+ * @brief Gets default settings for FLASHC.
+ *
+ * @param config FLASHC configuration structure.
+ */
+void FLASHC_GetDefaultConfig(flashc_config_t *config);
+
+/*!
+ * @brief Configure the timing of the FLASHC.
+ *
+ * @param base FLASHC base pointer.
+ * @param config FLASHC timing configure.
+ */
+void FLASHC_SetTimingConfig(FLASHC_Type *base, flashc_timing_config_t *config);
+
+/*!
+ * @brief Flush the Cache.
+ *
+ * @param base FLASHC base pointer.
+ * @return return status.
+ */
+status_t FLASHC_FlushCache(FLASHC_Type *base);
+
+/*!
+ * @brief Enable Flash Cache Hit Counters.
+ *
+ * @param base FLASHC base pointer.
+ * @param enable true/false.
+ */
+void FLASHC_EnableCacheHitCounter(FLASHC_Type *base, bool enable);
+
+/*!
+ * @brief Enable Flash Cache Miss Counters.
+ *
+ * @param base FLASHC base pointer.
+ * @param enable true/false.
+ */
+void FLASHC_EnableCacheMissCounter(FLASHC_Type *base, bool enable);
+
+/*!
+ * @brief Enable Flash Cache Miss Counters.
+ *
+ * @param base FLASHC base pointer.
+ * @param hitCnt cache hit counter.
+ * @param missCnt cache miss counter.
+ */
+void FLASHC_GetCacheCounter(FLASHC_Type *base, uint32_t *hitCnt, uint32_t *missCnt);
+
+/*!
+ * @brief Reset Flash Controller Cache Counters.
+ *
+ * @param base FLASHC base pointer.
+ */
+void FLASHC_ResetCacheCounter(FLASHC_Type *base);
+
+/*!
+ * @brief Enable the cache mode.
+ */
+static inline void FLASHC_EnableCacheMode(FLASHC_Type *base)
+{
+ FLASHC->FCCR |= FLASHC_FCCR_CACHE_EN_MASK;
+}
+
+/*!
+ * @brief Disable the cache mode.
+ */
+static inline void FLASHC_DisableCacheMode(FLASHC_Type *base)
+{
+ FLASHC->FCCR &= ~FLASHC_FCCR_CACHE_EN_MASK;
+}
+
+/*!
+ * @brief Enable the sram mode.
+ */
+static inline void FLASHC_EnableSramMode(FLASHC_Type *base)
+{
+ FLASHC->FCCR |= FLASHC_FCCR_SRAM_MODE_EN_MASK;
+}
+
+/*!
+ * @brief Disable the sram mode.
+ */
+static inline void FLASHC_DisableSramMode(FLASHC_Type *base)
+{
+ FLASHC->FCCR &= ~FLASHC_FCCR_SRAM_MODE_EN_MASK;
+}
+
+/*!
+ * @brief Hardware command configuration for FLASHC.
+ *
+ * @param base FLASHC base pointer.
+ * @param command FLASHC hardware command for read.
+ */
+static inline void FLASHC_SetHardwareCommand(FLASHC_Type *base, flashc_hw_cmd_t command)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->FCCR;
+
+ base->FCCR = (temp & ~FLASHC_FCCR_CMD_TYPE_MASK) | FLASHC_FCCR_CMD_TYPE(command);
+}
+
+/*!
+ * @brief Set selection hardware or software configuration for FLASHC.
+ *
+ * @param base FLASHC base pointer.
+ * @param cfgSel FLASHC Configuration Override.
+ */
+static inline void FLASHC_SetConfigSelection(FLASHC_Type *base, flashc_config_selection_t cfgSel)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->FCCR2;
+
+ base->FCCR2 = (temp & ~FLASHC_FCCR2_USE_CFG_OVRD_MASK) | FLASHC_FCCR2_USE_CFG_OVRD(cfgSel);
+}
+
+/*!
+ * @brief do not use offset address for flash memory access.
+ *
+ * @param base FLASHC base pointer.
+ */
+static inline void FLASHC_DisableOffsetAddr(FLASHC_Type *base)
+{
+ base->FCACR &= ~FLASHC_FCACR_OFFSET_EN_MASK;
+}
+
+/*!
+ * @brief Use offset address for flash memory access and set the offset address.
+ *
+ * @param base FLASHC base pointer.
+ * @param address offset address.
+ */
+void FLASHC_EnableOffsetAddr(FLASHC_Type *base, uint32_t address);
+
+/*!
+ * @brief Get exit continuous read mode status.
+ *
+ * @param base FLASHC base pointer.
+ */
+static inline bool FLASHC_GetExitContReadStatus(FLASHC_Type *base)
+{
+ return ((base->FCSR & FLASHC_FCSR_CONT_RD_MD_EXIT_DONE_MASK) ? true : false);
+}
+
+/*!
+ * @brief Exit dual continuous read mode.
+ *
+ * @param base FLASHC base pointer.
+ * @return return status.
+ */
+status_t FLASHC_ExitDualContReadMode(FLASHC_Type *base);
+
+/*!
+ * @brief Exit quad continuous read mode.
+ *
+ * @param base FLASHC base pointer.
+ * @return return status.
+ */
+status_t FLASHC_ExitQuadContReadMode(FLASHC_Type *base);
+
+/*!
+ * @brief Switch into QSPI from FLASHC.
+ *
+ * @param base FLASHC base pointer.
+ * @return return status.
+ */
+status_t FLASHC_EnableQSPIPad(FLASHC_Type *base);
+
+/*!
+ * @brief Switch back FLASHC from QSPI.
+ *
+ * @param base FLASHC base pointer.
+ * @param mode FLASHC read mode.
+ * @param jedecID JEDEC ID.
+ */
+void FLASHC_EnableFLASHCPad(FLASHC_Type *base, flashc_hw_cmd_t mode, uint32_t jedecID);
+
+/*!
+ * @brief Set quad mode read command.
+ *
+ * @param base FLASHC base pointer.
+ * @param jedecID JEDEC ID.
+ */
+void FLASH_SetQuadModeReadCmd(FLASHC_Type *base, uint32_t jedecID);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @}*/
+
+#endif /* _FSL_QSPI_H_*/
diff --git a/drivers/mw320/gpio/driver_mw_gpio.cmake b/drivers/mw320/gpio/driver_mw_gpio.cmake
new file mode 100644
index 000000000..c41387b28
--- /dev/null
+++ b/drivers/mw320/gpio/driver_mw_gpio.cmake
@@ -0,0 +1,14 @@
+#Description: MW_GPIO Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_gpio component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_gpio.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/gpio/fsl_gpio.c b/drivers/mw320/gpio/fsl_gpio.c
new file mode 100644
index 000000000..2b949c202
--- /dev/null
+++ b/drivers/mw320/gpio/fsl_gpio.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.gpio"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalInput,
+ * 0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalOutput,
+ * 0,
+ * }
+ * endcode
+ *
+ * param base GPIO peripheral base pointer
+ * param pin GPIO port pin number
+ * param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
+{
+ assert(NULL != config);
+ assert(pin < (uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER);
+
+ if (config->pinDirection == kGPIO_DigitalInput)
+ {
+ base->GCDR_REG[GPIO_PORT(pin)] = 1UL << GPIO_PORT_PIN(pin);
+ }
+ else
+ {
+ GPIO_PinWrite(base, pin, config->outputLogic);
+ base->GSDR_REG[GPIO_PORT(pin)] = 1UL << GPIO_PORT_PIN(pin);
+ }
+}
+
+/*!
+ * @brief Sets the output level of single GPIO pin to the logic 1 or 0.
+ *
+ * @param base GPIO peripheral base pointer
+ * @param pin GPIO pin number
+ * @param output GPIO pin output logic level.
+ * - 0: corresponding pin output low-logic level.
+ * - 1: corresponding pin output high-logic level.
+ */
+void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
+{
+ assert(pin < (uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER);
+
+ if (output != 0U)
+ {
+ base->GPSR_REG[GPIO_PORT(pin)] = 1UL << GPIO_PORT_PIN(pin);
+ }
+ else
+ {
+ base->GPCR_REG[GPIO_PORT(pin)] = 1UL << GPIO_PORT_PIN(pin);
+ }
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer
+ * @param port GPIO port number. Each port contains 32 GPIOs.
+ * @param mask GPIO pin bit mask. Bit position stands for the pin number in the port.
+ */
+void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ uint32_t level;
+
+ assert(port <= GPIO_PORT((uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER - 1U));
+
+ level = base->GPLR_REG[port];
+
+ GPIO_PortClear(base, port, level & mask);
+ GPIO_PortSet(base, port, (~level) & mask);
+}
+
+/*!
+ * @brief Configures the gpio pin interrupt.
+ *
+ * @param base GPIO peripheral base pointer.
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration.
+ */
+void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config)
+{
+ uint32_t regVal;
+
+ assert(pin < (uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER);
+
+ regVal = 1UL << GPIO_PORT_PIN(pin);
+
+ switch (config)
+ {
+ case kGPIO_InterruptStatusFlagDisabled:
+ base->GCRER_REG[GPIO_PORT(pin)] = regVal;
+ base->GCFER_REG[GPIO_PORT(pin)] = regVal;
+ break;
+ case kGPIO_InterruptRisingEdge:
+ base->GSRER_REG[GPIO_PORT(pin)] = regVal;
+ base->GCFER_REG[GPIO_PORT(pin)] = regVal;
+ break;
+ case kGPIO_InterruptFallingEdge:
+ base->GCRER_REG[GPIO_PORT(pin)] = regVal;
+ base->GSFER_REG[GPIO_PORT(pin)] = regVal;
+ break;
+ case kGPIO_InterruptEitherEdge:
+ base->GSRER_REG[GPIO_PORT(pin)] = regVal;
+ base->GSFER_REG[GPIO_PORT(pin)] = regVal;
+ break;
+ default:
+ assert(false);
+ break;
+ }
+}
diff --git a/drivers/mw320/gpio/fsl_gpio.h b/drivers/mw320/gpio/fsl_gpio.h
new file mode 100644
index 000000000..d6210dda2
--- /dev/null
+++ b/drivers/mw320/gpio/fsl_gpio.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_GPIO_H_
+#define _FSL_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gpio
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief GPIO driver version 2.0.0. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief Get GPIO port from pin number */
+#define GPIO_PORT(pin) (((uint32_t)(pin)) >> 5U)
+/*! @brief Get GPIO pin inside the port from pin number */
+#define GPIO_PORT_PIN(pin) (((uint32_t)(pin)) & 0x1FU)
+
+/*! @brief GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+ kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
+ kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Each pin can only be configured as either an output pin or an input pin at a time.
+ * If configured as an input pin, leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+ gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+ /* Output configurations; ignore if configured as an input pin */
+ uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
+} gpio_pin_config_t;
+
+/*! @brief Configures the interrupt generation condition. */
+typedef enum _gpio_interrupt_config
+{
+ kGPIO_InterruptStatusFlagDisabled = 0x00U, /*!< Interrupt status flag is disabled. */
+ kGPIO_InterruptRisingEdge = 0x01U, /*!< Interrupt on rising edge. */
+ kGPIO_InterruptFallingEdge = 0x02U, /*!< Interrupt on falling edge. */
+ kGPIO_InterruptEitherEdge = 0x03U, /*!< Interrupt on either edge. */
+} gpio_interrupt_config_t;
+
+/*! @} */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup gpio_driver
+ * @{
+ */
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * @code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalInput,
+ * 0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ * kGPIO_DigitalOutput,
+ * 0,
+ * }
+ * @endcode
+ *
+ * @param base GPIO peripheral base pointer
+ * @param pin GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of single GPIO pin to the logic 1 or 0.
+ *
+ * @param base GPIO peripheral base pointer
+ * @param pin GPIO pin number
+ * @param output GPIO pin output logic level.
+ * - 0: corresponding pin output low-logic level.
+ * - 1: corresponding pin output high-logic level.
+ */
+void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output);
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
+ * @param port GPIO port number. Each port contains 32 GPIOs.
+ * @param mask GPIO pin bit mask. Bit position stands for the pin number in the port.
+ */
+__STATIC_INLINE void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ assert(port <= GPIO_PORT((uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER - 1U));
+
+ base->GPSR_REG[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer
+ * @param port GPIO port number. Each port contains 32 GPIOs.
+ * @param mask GPIO pin bit mask. Bit position stands for the pin number in the port.
+ */
+__STATIC_INLINE void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ assert(port <= GPIO_PORT((uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER - 1U));
+
+ base->GPCR_REG[port] = mask;
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer
+ * @param port GPIO port number. Each port contains 32 GPIOs.
+ * @param mask GPIO pin bit mask. Bit position stands for the pin number in the port.
+ */
+void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask);
+
+/*@}*/
+
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO port.
+ *
+ * @param base GPIO peripheral base pointer
+ * @param pin GPIO pin number
+ * @retval GPIO port input value
+ * - 0: corresponding pin input low-logic level.
+ * - 1: corresponding pin input high-logic level.
+ */
+__STATIC_INLINE uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
+{
+ assert(pin < (uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER);
+
+ return (base->GPLR_REG[GPIO_PORT(pin)] >> GPIO_PORT_PIN(pin)) & 0x01U;
+}
+
+/*@}*/
+
+/*! @name GPIO Interrupt */
+/*@{*/
+
+/*!
+ * @brief Configures the gpio pin interrupt.
+ *
+ * @param base GPIO peripheral base pointer.
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration.
+ */
+void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_config_t config);
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number. Each port contains 32 GPIOs.
+ * @param mask GPIO pin bit mask. Bit position stands for the pin number in the port.
+ */
+__STATIC_INLINE void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ assert(port <= GPIO_PORT((uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER - 1U));
+
+ base->APMASK_REG[port] |= mask;
+}
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number. Each port contains 32 GPIOs.
+ * @param mask GPIO pin bit mask. Bit position stands for the pin number in the port.
+ */
+__STATIC_INLINE void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ assert(port <= GPIO_PORT((uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER - 1U));
+
+ base->APMASK_REG[port] &= ~mask;
+}
+
+/*!
+ * @brief Reads the GPIO port interrupt status flag.
+ *
+ * The flag remains set until a logic one is written to that flag.
+ *
+ * @param base GPIO peripheral base pointer
+ * @param port GPIO port number. Each port contains 32 GPIOs.
+ * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
+ * pin 0 and 16 have the interrupt.
+ */
+__STATIC_INLINE uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base, uint32_t port)
+{
+ assert(port <= GPIO_PORT((uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER - 1U));
+
+ return base->GEDR_REG[port];
+}
+
+/*!
+ * @brief Clears multiple GPIO pin interrupt status flags.
+ *
+ * @param base GPIO peripheral base pointer
+ * @param port GPIO port number. Each port contains 32 GPIOs.
+ * @param mask GPIO pin bit mask. Bit position stands for the pin number in the port.
+ */
+__STATIC_INLINE void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ assert(port <= GPIO_PORT((uint32_t)FSL_FEATURE_MW_GPIO_IO_NUMBER - 1U));
+
+ base->GEDR_REG[port] = mask;
+}
+
+/*@}*/
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_GPIO_H_*/
diff --git a/drivers/mw320/gpt/driver_mw_gpt.cmake b/drivers/mw320/gpt/driver_mw_gpt.cmake
new file mode 100644
index 000000000..ceeea948f
--- /dev/null
+++ b/drivers/mw320/gpt/driver_mw_gpt.cmake
@@ -0,0 +1,14 @@
+#Description: MW_GPT Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_gpt component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_gpt.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/gpt/fsl_gpt.c b/drivers/mw320/gpt/fsl_gpt.c
new file mode 100644
index 000000000..815ac485f
--- /dev/null
+++ b/drivers/mw320/gpt/fsl_gpt.c
@@ -0,0 +1,569 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpt.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.gpt"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Gets the instance from the base address
+ *
+ * @param base GPT peripheral base address
+ *
+ * @return The GPT instance
+ */
+static uint32_t GPT_GetInstance(GPT_Type *base);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to GPT bases for each instance. */
+static GPT_Type *const s_gptBases[] = GPT_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to GPT clocks for each instance. */
+static const clock_ip_name_t s_gptClocks[] = GPT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t GPT_GetInstance(GPT_Type *base)
+{
+ uint32_t instance;
+ uint32_t gptArrayCount = (sizeof(s_gptBases) / sizeof(s_gptBases[0]));
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < gptArrayCount; instance++)
+ {
+ if (s_gptBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < gptArrayCount);
+
+ return instance;
+}
+
+/*!
+ * @brief Ungates the GPT clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application which is using the GPT driver.
+ * If the GPT instance has only TPM features, please use the TPM driver.
+ *
+ * @param base GPT peripheral base address
+ * @param config Pointer to the user configuration structure.
+ *
+ * @return kStatus_Success indicates success; Else indicates failure.
+ */
+status_t GPT_Init(GPT_Type *base, const gpt_config_t *config)
+{
+ uint32_t i;
+
+ assert(config);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate the GPT clock*/
+ (void)CLOCK_EnableClock(s_gptClocks[GPT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ /* Ensure GPT is stopped. */
+ GPT_StopTimer(base);
+
+ /* Set all channels to no function mode. */
+ for (i = 0U; i < 6U; i++)
+ {
+ base->CH[i].CH_CNTL_REG = 0U;
+ }
+
+ /* Clear all status */
+ GPT_ClearStatusFlags(base, (uint32_t)kGPT_AllFlags);
+
+ /* Configure counter clock. */
+ base->CLK_CNTL_REG = GPT_CLK_CNTL_REG_CLK_SRC(config->src) | GPT_CLK_CNTL_REG_CLK_DIV(config->div) |
+ GPT_CLK_CNTL_REG_CLK_PRE(config->prescale);
+ /* Configure counter update mode and debug behaivor. */
+ base->CNT_CNTL_REG =
+ (config->stopCntInDebug ? GPT_CNT_CNTL_REG_CNT_DBG_ACT(0U) : GPT_CNT_CNTL_REG_CNT_DBG_ACT(1U)) |
+ GPT_CNT_CNTL_REG_CNT_UPDT_MOD(config->cntUpdateMode);
+ /* Configure input capture clock and filter. */
+ base->IC_CNTL_REG = GPT_IC_CNTL_REG_CHX_IC_DIV(config->icDiv) | GPT_IC_CNTL_REG_CHX_IC_WIDTH(config->icFilter);
+ /* Set up counter overflow threshold. */
+ GPT_SetTimerPeriod(base, config->cntUppVal);
+ /* Reset the counter to make the timer period valid immediately. */
+ GPT_ResetTimer(base);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Gates the GPT clock.
+ *
+ * param base GPT peripheral base address
+ */
+void GPT_Deinit(GPT_Type *base)
+{
+ /* Ensure GPT is stopped. */
+ GPT_StopTimer(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Gate the GPT clock */
+ (void)CLOCK_DisableClock(s_gptClocks[GPT_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief Fills in the GPT configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ * config->src = kGPT_SystemClock;
+ * config->div = kGPT_ClkDiv_Divide_1;
+ * config->prescale = 0U;
+ * config->cntUpdateMode = kGPT_CntUpdateMode_Normal;
+ * config->stopCntInDebug = true;
+ * config->cntUppVal = 0xFFFFFFFFU;
+ * config->icDiv = kGPT_SampClkDiv_Divide_1;
+ * config->icFilter = kGPT_InputCapFilter_None;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void GPT_GetDefaultConfig(gpt_config_t *config)
+{
+ assert(config != NULL);
+
+ /* Initializes the configure structure to zero. */
+ (void)memset(config, 0, sizeof(*config));
+
+ /* Set clock source to system clock (not from pad). */
+ config->src = kGPT_SystemClock;
+ /* Set clock source divider to 1 for counter. */
+ config->div = kGPT_ClkDiv_Divide_1;
+ /* Set clock prescalar divider to 1 for counter. */
+ config->prescale = 0U;
+ /* Set counter update mode to normal. */
+ config->cntUpdateMode = kGPT_CntUpdateMode_Normal;
+ /* Stop counter in debug mode. */
+ config->stopCntInDebug = true;
+ /* Set counter overflow threshold to maximum. */
+ config->cntUppVal = 0xFFFFFFFFU;
+ /* Set input capture sample clock divider to 1. */
+ config->icDiv = kGPT_SampClkDiv_Divide_1;
+ /* Set input capture filter cycles to 1 (no filter). */
+ config->icFilter = kGPT_InputCapFilter_None;
+}
+
+/*!
+ * @brief Enables capturing an input signal on the channel using the function parameters.
+ *
+ * When the edge specified in the captureMode argument occurs on the channel, the GPT counter is
+ * captured into the CMR0 register. The user has to read the CMR0 register separately to get this
+ * value.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ * @param captureMode Specifies which edge to capture
+ */
+void GPT_SetupInputCapture(GPT_Type *base, gpt_chnl_t chnlNumber, gpt_input_capture_edge_t captureMode)
+{
+ base->CH[chnlNumber].CH_CNTL_REG = GPT_CH_CNTL_REG_IC_EDGE(captureMode) | GPT_CH_CNTL_REG_CHX_IO(1U);
+}
+
+/*!
+ * @brief Trigger input capturing by software. Edge and filter is ignored.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ */
+void GPT_TriggerInputCapture(GPT_Type *base, gpt_chnl_t chnlNumber)
+{
+ base->USER_REQ_REG = ((uint32_t)GPT_USER_REQ_REG_CH0_USER_ITRIG_MASK) << ((uint8_t)chnlNumber);
+}
+
+/*!
+ * @brief Get captured value.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ */
+uint32_t GPT_GetCapturedValue(GPT_Type *base, gpt_chnl_t chnlNumber)
+{
+ return base->CH[chnlNumber].CH_CMR0_REG;
+}
+
+/*!
+ * @brief Configures one-shot pulse on the channel.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ * @param pol Channel output polarity reset value.
+ * @param delayTicks Delay width before triggering the pulse, the uint of this value is timer ticks.
+ * @param dutyTicks Pulse width, the uint of this value is timer ticks.
+ */
+void GPT_SetupOneshotPulse(
+ GPT_Type *base, gpt_chnl_t chnlNumber, gpt_chnl_pol_t pol, uint32_t delayTicks, uint32_t dutyTicks)
+{
+ /* counter must be started */
+ assert((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) != 0U);
+
+ base->CH[chnlNumber].CH_CNTL_REG = GPT_CH_CNTL_REG_POL(pol) | GPT_CH_CNTL_REG_CHX_IO(4U);
+ base->CH[chnlNumber].CH_CMR0_REG = dutyTicks;
+ base->CH[chnlNumber].CH_CMR1_REG = delayTicks;
+
+ /* Update CMRs */
+ base->USER_REQ_REG = GPT_USER_REQ_REG_CH0_CMR_UPDT_MASK << ((uint8_t)chnlNumber);
+ /* Shouldn't cause channel error. */
+ assert((base->STS_REG & (((uint32_t)GPT_STS_REG_CH0_ERR_STS_MASK) << ((uint8_t)chnlNumber))) == 0U);
+
+ /* Now trigger the channel reset for one shot pulse */
+ base->USER_REQ_REG = ((uint32_t)GPT_USER_REQ_REG_CH0_RST_MASK) << ((uint8_t)chnlNumber);
+}
+
+/*!
+ * @brief Configures one-shot edge on the channel.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ * @param pol Channel output polarity reset value.
+ * @param delayTicks Delay width before changing the edge, the uint of this value is timer ticks.
+ */
+void GPT_SetupOneshotEdge(GPT_Type *base, gpt_chnl_t chnlNumber, gpt_chnl_pol_t pol, uint32_t delayTicks)
+{
+ /* counter must be started */
+ assert((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) != 0U);
+
+ base->CH[chnlNumber].CH_CNTL_REG = GPT_CH_CNTL_REG_POL(pol) | GPT_CH_CNTL_REG_CHX_IO(5U);
+ base->CH[chnlNumber].CH_CMR1_REG = delayTicks;
+
+ /* Update CMRs */
+ base->USER_REQ_REG = GPT_USER_REQ_REG_CH0_CMR_UPDT_MASK << ((uint8_t)chnlNumber);
+ /* Shouldn't cause channel error. */
+ assert((base->STS_REG & (((uint32_t)GPT_STS_REG_CH0_ERR_STS_MASK) << ((uint8_t)chnlNumber))) == 0U);
+
+ /* Now trigger the channel reset for one shot pulse */
+ base->USER_REQ_REG = ((uint32_t)GPT_USER_REQ_REG_CH0_RST_MASK) << ((uint8_t)chnlNumber);
+}
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this
+ * function to configure all GPT channels that are used to output a PWM signal.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number.
+ * @param pol PWM output polarity reset value.
+ * @param dutyPercent PWM pulse width, value should be between 0 to 100
+ * @param mode PWM operation mode, options available in enumeration ::gpt_pwm_mode_t
+ * @param pwmFreq_Hz PWM signal frequency in Hz
+ * @param srcClock_Hz GPT counter clock in Hz
+ *
+ * @return kStatus_Success if the PWM setup was successful
+ * kStatus_Fail on failure
+ */
+status_t GPT_SetupPwm(GPT_Type *base,
+ gpt_chnl_t chnlNumber,
+ gpt_chnl_pol_t pol,
+ uint32_t dutyPercent,
+ gpt_pwm_mode_t mode,
+ uint32_t pwmFreq_Hz,
+ uint32_t srcClock_Hz)
+{
+ uint32_t reg, periodTicks;
+ uint32_t gptClock;
+
+ assert(0U != srcClock_Hz);
+ assert(0U != pwmFreq_Hz);
+ assert(dutyPercent <= 100U);
+
+ reg = base->CLK_CNTL_REG;
+ gptClock = srcClock_Hz / (1UL << ((reg & GPT_CLK_CNTL_REG_CLK_DIV_MASK) >> GPT_CLK_CNTL_REG_CLK_DIV_SHIFT)) /
+ (((reg & GPT_CLK_CNTL_REG_CLK_PRE_MASK) >> GPT_CLK_CNTL_REG_CLK_PRE_SHIFT) + 1U);
+ periodTicks = (gptClock + pwmFreq_Hz - 1U) / pwmFreq_Hz;
+
+ return GPT_SetupPwmMode(base, chnlNumber, pol, periodTicks, periodTicks * dutyPercent / 100U, mode);
+}
+
+/*!
+ * @brief Configures the PWM mode parameters.
+ *
+ * Call this function to configure the PWM signal mode, duty cycle in ticks, and edge. Use this
+ * function to configure all GPT channels that are used to output a PWM signal.
+ * Please note that: This API is similar with GPT_SetupPwm() API, but will not set the timer period,
+ * and this API will set channel match value in timer ticks, not period percent.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number.
+ * @param pol PWM output polarity reset value.
+ * @param periodTicks PWM period width, the uint of this value is timer ticks.
+ * @param dutyTicks PWM pulse width, the uint of this value is timer ticks.
+ * @param mode PWM operation mode, options available in enumeration ::gpt_pwm_mode_t
+ *
+ * @return kStatus_Success if the PWM setup was successful
+ * kStatus_Fail on failure
+ */
+status_t GPT_SetupPwmMode(GPT_Type *base,
+ gpt_chnl_t chnlNumber,
+ gpt_chnl_pol_t pol,
+ uint32_t periodTicks,
+ uint32_t dutyTicks,
+ gpt_pwm_mode_t mode)
+{
+ /* counter must be started */
+ assert((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) != 0U);
+ assert(periodTicks > 0U);
+ assert(periodTicks >= dutyTicks);
+
+ if (mode == kGPT_CenterAlignedPwm)
+ {
+ base->CH[chnlNumber].CH_CNTL_REG = GPT_CH_CNTL_REG_POL(pol) | GPT_CH_CNTL_REG_CHX_IO(7U);
+ base->CH[chnlNumber].CH_CMR0_REG = (dutyTicks + 1U) / 2U;
+ base->CH[chnlNumber].CH_CMR1_REG = (periodTicks - dutyTicks + 1U) / 2U;
+ }
+ else /* Edge aligned */
+ {
+ base->CH[chnlNumber].CH_CNTL_REG = GPT_CH_CNTL_REG_POL(pol) | GPT_CH_CNTL_REG_CHX_IO(6U);
+ base->CH[chnlNumber].CH_CMR0_REG = dutyTicks;
+ base->CH[chnlNumber].CH_CMR1_REG = periodTicks - dutyTicks;
+ }
+
+ /* Update CMRs */
+ base->USER_REQ_REG = GPT_USER_REQ_REG_CH0_CMR_UPDT_MASK << ((uint8_t)chnlNumber);
+ /* Shouldn't cause channel error. */
+ assert((base->STS_REG & (((uint32_t)GPT_STS_REG_CH0_ERR_STS_MASK) << ((uint8_t)chnlNumber))) == 0U);
+
+ /* Now trigger the channel reset for one shot pulse */
+ base->USER_REQ_REG = ((uint32_t)GPT_USER_REQ_REG_CH0_RST_MASK) << ((uint8_t)chnlNumber);
+
+ return kStatus_Success;
+}
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number.
+ * @param dutyPercent New PWM pulse width; The value should be between 0 to 100
+ * 0=inactive signal(0% duty cycle)...
+ * 100=active signal (100% duty cycle)
+ *
+ * @return kStatus_Success if the PWM update was successful
+ * kStatus_Fail on failure
+ */
+status_t GPT_UpdatePwmDutycycle(GPT_Type *base, gpt_chnl_t chnlNumber, uint8_t dutyPercent)
+{
+ uint32_t periodTicks, dutyTicks;
+ status_t status = kStatus_Success;
+
+ /* counter must be started */
+ assert((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) != 0U);
+ assert(dutyPercent <= 100U);
+
+ periodTicks = base->CH[chnlNumber].CH_CMR0_REG + base->CH[chnlNumber].CH_CMR1_REG;
+ dutyTicks = periodTicks * dutyPercent / 100U;
+
+ base->CH[chnlNumber].CH_CMR0_REG = dutyTicks;
+ base->CH[chnlNumber].CH_CMR1_REG = periodTicks - dutyTicks;
+
+ /* Update CMRs */
+ base->USER_REQ_REG = GPT_USER_REQ_REG_CH0_CMR_UPDT_MASK << ((uint8_t)chnlNumber);
+
+ if ((base->STS_REG & (((uint32_t)GPT_STS_REG_CH0_ERR_STS_MASK) << ((uint8_t)chnlNumber))) != 0U)
+ {
+ /* Clear error and return */
+ base->STS_REG = (((uint32_t)GPT_STS_REG_CH0_ERR_STS_MASK) << ((uint8_t)chnlNumber));
+ status = kStatus_Fail;
+ }
+
+ return status;
+}
+
+/*!
+ * @brief Pause the PWM signal.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number.
+ *
+ * @return kStatus_Success if the PWM update was successful
+ * kStatus_Fail on failure
+ */
+status_t GPT_PausePwm(GPT_Type *base, gpt_chnl_t chnlNumber)
+{
+ status_t status = kStatus_Success;
+
+ /* counter must be started */
+ assert((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) != 0U);
+
+ base->CH[chnlNumber].CH_CMR0_REG = 0U;
+ base->CH[chnlNumber].CH_CMR1_REG = 0U;
+
+ /* Update CMRs */
+ base->USER_REQ_REG = GPT_USER_REQ_REG_CH0_CMR_UPDT_MASK << ((uint8_t)chnlNumber);
+
+ if ((base->STS_REG & (((uint32_t)GPT_STS_REG_CH0_ERR_STS_MASK) << ((uint8_t)chnlNumber))) != 0U)
+ {
+ /* Clear error and return */
+ base->STS_REG = (((uint32_t)GPT_STS_REG_CH0_ERR_STS_MASK) << ((uint8_t)chnlNumber));
+ status = kStatus_Fail;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Enables the selected GPT interrupts.
+ *
+ * param base GPT peripheral base address
+ * param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::gpt_interrupt_enable_t
+ */
+void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask)
+{
+ base->INT_MSK_REG &= ~(mask & (uint32_t)kGPT_AllInterruptsEnable);
+}
+
+/*!
+ * brief Disables the selected GPT interrupts.
+ *
+ * param base GPT peripheral base address
+ * param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::gpt_interrupt_enable_t
+ */
+void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask)
+{
+ base->INT_MSK_REG |= (mask & (uint32_t)kGPT_AllInterruptsEnable);
+}
+
+/*!
+ * brief Gets the enabled GPT interrupts.
+ *
+ * param base GPT peripheral base address
+ *
+ * return The enabled interrupts. This is the logical OR of members of the
+ * enumeration ::gpt_interrupt_enable_t
+ */
+uint32_t GPT_GetEnabledInterrupts(GPT_Type *base)
+{
+ return (~base->INT_MSK_REG) & (uint32_t)kGPT_AllInterruptsEnable;
+}
+
+/*!
+ * brief Gets the GPT status flags.
+ *
+ * param base GPT peripheral base address
+ *
+ * return The status flags. This is the logical OR of members of the
+ * enumeration ::gpt_status_flags_t
+ */
+uint32_t GPT_GetStatusFlags(GPT_Type *base)
+{
+ return base->STS_REG & (uint32_t)kGPT_AllFlags;
+}
+
+/*!
+ * brief Clears the GPT status flags.
+ *
+ * param base GPT peripheral base address
+ * param mask The status flags to clear. This is a logical OR of members of the
+ * enumeration ::gpt_status_flags_t
+ */
+void GPT_ClearStatusFlags(GPT_Type *base, uint32_t mask)
+{
+ base->STS_REG = mask & (uint32_t)kGPT_AllFlags;
+}
+
+/*!
+ * @brief Sets the timer period in units of ticks for the GPT instance.
+ *
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
+ * the CNT_UPP_VAL register.
+ *
+ * @note
+ * Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
+ *
+ * @param base GPT peripheral base address
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
+ */
+void GPT_SetTimerPeriod(GPT_Type *base, uint32_t ticks)
+{
+ assert(ticks > 0U);
+
+ base->CNT_UPP_VAL_REG = ticks;
+}
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value in a range from 0 to a
+ * timer period.
+ *
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base GPT peripheral base address
+ *
+ * @return The current counter value in ticks
+ */
+uint32_t GPT_GetCurrentTimerCount(GPT_Type *base)
+{
+ /* To get counter, autoUpdateCntVal must be configured to auto-update. */
+ assert((base->CNT_CNTL_REG & GPT_CNT_CNTL_REG_CNT_UPDT_MOD_MASK) != GPT_CNT_CNTL_REG_CNT_UPDT_MOD(3U));
+ return base->CNT_VAL_REG;
+}
+
+/*!
+ * @brief Starts the GPT counter.
+ *
+ * @param base GPT peripheral base address
+ */
+void GPT_StartTimer(GPT_Type *base)
+{
+ if ((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) == 0U)
+ {
+ base->CNT_EN_REG = GPT_CNT_EN_REG_CNT_START_MASK;
+ while ((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) == 0U)
+ {
+ }
+ }
+}
+
+/*!
+ * @brief Stops the GPT counter.
+ *
+ * @param base GPT peripheral base address
+ */
+void GPT_StopTimer(GPT_Type *base)
+{
+ if ((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) != 0U)
+ {
+ base->CNT_EN_REG = GPT_CNT_EN_REG_CNT_STOP_MASK;
+ while ((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RUN_MASK) != 0U)
+ {
+ }
+ }
+}
+
+/*!
+ * @brief Performs a GPT counter reset.
+ *
+ * @param base GPT peripheral base address
+ */
+void GPT_ResetTimer(GPT_Type *base)
+{
+ /* Reset counter */
+ base->CNT_EN_REG = GPT_CNT_EN_REG_CNT_RESET_MASK;
+ while ((base->CNT_EN_REG & GPT_CNT_EN_REG_CNT_RST_DONE_MASK) == 0U)
+ {
+ }
+}
diff --git a/drivers/mw320/gpt/fsl_gpt.h b/drivers/mw320/gpt/fsl_gpt.h
new file mode 100644
index 000000000..2798b83a9
--- /dev/null
+++ b/drivers/mw320/gpt/fsl_gpt.h
@@ -0,0 +1,520 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_GPT_H_
+#define _FSL_GPT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup gpt
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief GPT driver version 2.0.0. */
+#define FSL_GPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+ * @brief List of GPT channels
+ * @note Actual number of available channels is SoC dependent
+ */
+typedef enum _gpt_chnl
+{
+ kGPT_Chnl_0 = 0U, /*!< GPT channel number 0*/
+ kGPT_Chnl_1, /*!< GPT channel number 1 */
+ kGPT_Chnl_2, /*!< GPT channel number 2 */
+ kGPT_Chnl_3, /*!< GPT channel number 3 */
+ kGPT_Chnl_4, /*!< GPT channel number 4 */
+ kGPT_Chnl_5, /*!< GPT channel number 5 */
+} gpt_chnl_t;
+
+/*! @brief GPT channel polarity */
+typedef enum _gpt_chnl_pol
+{
+ kGPT_ChnlPol_Low = 0U, /*!< Output state reset to 0 */
+ kGPT_ChnlPol_High, /*!< Output state reset to 1 */
+} gpt_chnl_pol_t;
+
+/*! @brief GPT PWM operation modes */
+typedef enum _gpt_pwm_mode
+{
+ kGPT_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
+ kGPT_CenterAlignedPwm, /*!< Center-aligned PWM */
+} gpt_pwm_mode_t;
+
+/*! @brief GPT input capture edge */
+typedef enum _gpt_input_capture_edge
+{
+ kGPT_RisingEdge = 0U, /*!< Capture on rising edge only */
+ kGPT_FallingEdge, /*!< Capture on falling edge only */
+} gpt_input_capture_edge_t;
+
+/*! @brief GPT input capture edge */
+typedef enum _gpt_input_capture_filter
+{
+ kGPT_InputCapFilter_None = 0U, /*!< No filter */
+ kGPT_InputCapFilter_2Cycles, /*!< Filter 2 consecutive cycles */
+ kGPT_InputCapFilter_3Cycles, /*!< Filter 3 consecutive cycles */
+ kGPT_InputCapFilter_4Cycles, /*!< Filter 4 consecutive cycles */
+ kGPT_InputCapFilter_5Cycles, /*!< Filter 5 consecutive cycles */
+ kGPT_InputCapFilter_6Cycles, /*!< Filter 6 consecutive cycles */
+ kGPT_InputCapFilter_7Cycles, /*!< Filter 7 consecutive cycles */
+} gpt_input_capture_filter_t;
+
+/*! @brief GPT clock source selection*/
+typedef enum _gpt_clock_source
+{
+ kGPT_SystemClock = 0U, /*!< System clock from PMU selected */
+ kGPT_ExternalClock /*!< External clock from pad */
+} gpt_clock_source_t;
+
+/*! @brief GPT clock divider factor selection for the clock source. */
+typedef enum _gpt_clock_div
+{
+ kGPT_ClkDiv_Divide_1 = 0U, /*!< Divide by 1 */
+ kGPT_ClkDiv_Divide_2, /*!< Divide by 2 */
+ kGPT_ClkDiv_Divide_4, /*!< Divide by 4 */
+ kGPT_ClkDiv_Divide_8, /*!< Divide by 8 */
+ kGPT_ClkDiv_Divide_16, /*!< Divide by 16 */
+ kGPT_ClkDiv_Divide_32, /*!< Divide by 32 */
+ kGPT_ClkDiv_Divide_64, /*!< Divide by 64 */
+ kGPT_ClkDiv_Divide_128, /*!< Divide by 128 */
+ kGPT_ClkDiv_Divide_256, /*!< Divide by 256 */
+ kGPT_ClkDiv_Divide_512, /*!< Divide by 512 */
+ kGPT_ClkDiv_Divide_1024, /*!< Divide by 1024 */
+ kGPT_ClkDiv_Divide_2048, /*!< Divide by 2048 */
+ kGPT_ClkDiv_Divide_4096, /*!< Divide by 4096 */
+ kGPT_ClkDiv_Divide_8192, /*!< Divide by 8192 */
+ kGPT_ClkDiv_Divide_16384, /*!< Divide by 16384 */
+ kGPT_ClkDiv_Divide_32768, /*!< Divide by 32768 */
+} gpt_clock_div_t;
+
+/*!
+ * @brief List of GPT interrupts
+ */
+typedef enum _gpt_interrupt_enable
+{
+ kGPT_Chnl0InterruptEnable = (1U << 0), /*!< Channel 0 interrupt */
+ kGPT_Chnl1InterruptEnable = (1U << 1), /*!< Channel 1 interrupt */
+ kGPT_Chnl2InterruptEnable = (1U << 2), /*!< Channel 2 interrupt */
+ kGPT_Chnl3InterruptEnable = (1U << 3), /*!< Channel 3 interrupt */
+ kGPT_Chnl4InterruptEnable = (1U << 4), /*!< Channel 4 interrupt */
+ kGPT_Chnl5InterruptEnable = (1U << 5), /*!< Channel 5 interrupt */
+
+ kGPT_Chnl0ErrInterruptEnable = (1U << 8), /*!< Channel 0 error interrupt */
+ kGPT_Chnl1ErrInterruptEnable = (1U << 9), /*!< Channel 1 error interrupt */
+ kGPT_Chnl2ErrInterruptEnable = (1U << 10), /*!< Channel 2 error interrupt */
+ kGPT_Chnl3ErrInterruptEnable = (1U << 11), /*!< Channel 3 error interrupt */
+ kGPT_Chnl4ErrInterruptEnable = (1U << 12), /*!< Channel 4 error interrupt */
+ kGPT_Chnl5ErrInterruptEnable = (1U << 13), /*!< Channel 5 error interrupt */
+
+ kGPT_TimeOverflowInterruptEnable = (1U << 16), /*!< Time overflow interrupt */
+
+ kGPT_Dma0OverflowInterruptEnable = (1U << 24), /*!< DMA0 overflow interrupt */
+ kGPT_Dma1OverflowInterruptEnable = (1U << 25), /*!< DMA1 overflow interrupt */
+
+ kGPT_AllInterruptsEnable = 0x3013F3FUL, /*!< All interrupts */
+} gpt_interrupt_enable_t;
+
+/*!
+ * @brief List of GPT flags
+ */
+typedef enum _gpt_status_flags
+{
+ kGPT_Chnl0Flag = (1U << 0), /*!< Channel 0 flag */
+ kGPT_Chnl1Flag = (1U << 1), /*!< Channel 1 flag */
+ kGPT_Chnl2Flag = (1U << 2), /*!< Channel 2 flag */
+ kGPT_Chnl3Flag = (1U << 3), /*!< Channel 3 flag */
+ kGPT_Chnl4Flag = (1U << 4), /*!< Channel 4 flag */
+ kGPT_Chnl5Flag = (1U << 5), /*!< Channel 5 flag */
+
+ kGPT_Chnl0ErrFlag = (1U << 8), /*!< Channel 0 error flag */
+ kGPT_Chnl1ErrFlag = (1U << 9), /*!< Channel 1 error flag */
+ kGPT_Chnl2ErrFlag = (1U << 10), /*!< Channel 2 error flag */
+ kGPT_Chnl3ErrFlag = (1U << 11), /*!< Channel 3 error flag */
+ kGPT_Chnl4ErrFlag = (1U << 12), /*!< Channel 4 error flag */
+ kGPT_Chnl5ErrFlag = (1U << 13), /*!< Channel 5 error flag */
+
+ kGPT_TimeOverflowFlag = (1U << 16), /*!< Time overflow flag */
+
+ kGPT_Dma0OverflowFlag = (1U << 24), /*!< DMA0 overflow flag */
+ kGPT_Dma1OverflowFlag = (1U << 25), /*!< DMA1 overflow flag */
+
+ kGPT_AllFlags = 0x3013F3FUL, /*!< All flags */
+} gpt_status_flags_t;
+
+/*! @brief GPT counter update mode */
+typedef enum _gpt_cnt_update_mode
+{
+ kGPT_CntUpdateMode_Normal = 0U, /*!< Used in any ratio between counter clock and APB clock. Every 3-4 counter ticks
+ are updated to CNT_VAL */
+ kGPT_CntUpdateMode_Fast = 1U, /*!< Used when counter clock is at least 5 times slower than APB clock. Every counter
+ tick is updated to CNT_VAL */
+ kGPT_CntUpdateMode_Off = 3U, /*!< Do not update to CNT_VAL */
+} gpt_cnt_update_mode_t;
+
+/*! @brief GPT sample clock divider factor selection. */
+typedef enum _gpt_input_capture_div
+{
+ kGPT_SampClkDiv_Divide_1 = 0U, /*!< Divide by 1 */
+ kGPT_SampClkDiv_Divide_2, /*!< Divide by 2 */
+ kGPT_SampClkDiv_Divide_4, /*!< Divide by 4 */
+ kGPT_SampClkDiv_Divide_8, /*!< Divide by 8 */
+ kGPT_SampClkDiv_Divide_16, /*!< Divide by 16 */
+ kGPT_SampClkDiv_Divide_32, /*!< Divide by 32 */
+ kGPT_SampClkDiv_Divide_64, /*!< Divide by 64 */
+ kGPT_SampClkDiv_Divide_128, /*!< Divide by 128 */
+} gpt_input_capture_div_t;
+
+/*!
+ * @brief GPT configuration structure
+ *
+ * This structure holds the configuration settings for the GPT peripheral. To initialize this
+ * structure to reasonable defaults, call the GPT_GetDefaultConfig() function and pass a
+ * pointer to the configuration structure instance.
+ *
+ * The configuration structure can be made constant so as to reside in flash.
+ */
+typedef struct _gpt_config
+{
+ gpt_clock_source_t src; /*!< GPT clock source selection. */
+ gpt_clock_div_t div; /*!< GPT clock divider value for counter. */
+ uint8_t prescale; /*!< GPT clock prescale value for counter, divided by (prescale + 1) */
+ gpt_cnt_update_mode_t cntUpdateMode; /*!< Counter value update mode. */
+ bool stopCntInDebug; /*!< true: In debug mode, stop the counters.
+ false: In debug mode, counters are not affected. */
+ uint32_t cntUppVal; /*!< If counter reaches this value, the counter will overflow to 0. */
+ gpt_input_capture_div_t icDiv; /*!< Input capture sample clock divider. */
+ gpt_input_capture_filter_t icFilter; /*!< Input capture filter cycles in sampling ticks. */
+} gpt_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the GPT clock and configures the peripheral for basic operation.
+ *
+ * @note This API should be called at the beginning of the application which is using the GPT driver.
+ * If the GPT instance has only TPM features, please use the TPM driver.
+ *
+ * @param base GPT peripheral base address
+ * @param config Pointer to the user configuration structure.
+ *
+ * @return kStatus_Success indicates success; Else indicates failure.
+ */
+status_t GPT_Init(GPT_Type *base, const gpt_config_t *config);
+
+/*!
+ * @brief Gates the GPT clock.
+ *
+ * @param base GPT peripheral base address
+ */
+void GPT_Deinit(GPT_Type *base);
+
+/*!
+ * @brief Fills in the GPT configuration structure with the default settings.
+ *
+ * The default values are:
+ * @code
+ * config->src = kGPT_SystemClock;
+ * config->div = kGPT_ClkDiv_Divide_1;
+ * config->prescale = 0U;
+ * config->cntUpdateMode = kGPT_CntUpdateMode_Normal;
+ * config->stopCntInDebug = true;
+ * config->cntUppVal = 0xFFFFFFFFU;
+ * config->icDiv = kGPT_SampClkDiv_Divide_1;
+ * config->icFilter = kGPT_InputCapFilter_None;
+ * @endcode
+ * @param config Pointer to the user configuration structure.
+ */
+void GPT_GetDefaultConfig(gpt_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Channel mode operations
+ * @{
+ */
+
+/*!
+ * @brief Enables capturing an input signal on the channel using the function parameters.
+ *
+ * When the edge specified in the captureMode argument occurs on the channel, the GPT counter is
+ * captured into the CMR0 register. The user has to read the CMR0 register separately to get this
+ * value.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ * @param captureMode Specifies which edge to capture
+ */
+void GPT_SetupInputCapture(GPT_Type *base, gpt_chnl_t chnlNumber, gpt_input_capture_edge_t captureMode);
+
+/*!
+ * @brief Trigger input capturing by software. Edge and filter is ignored.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ */
+void GPT_TriggerInputCapture(GPT_Type *base, gpt_chnl_t chnlNumber);
+
+/*!
+ * @brief Get captured value.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ * @return The captured counter value.
+ */
+uint32_t GPT_GetCapturedValue(GPT_Type *base, gpt_chnl_t chnlNumber);
+
+/*!
+ * @brief Configures one-shot pulse on the channel.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ * @param pol Channel output polarity reset value.
+ * @param delayTicks Delay width before triggering the pulse, the uint of this value is timer ticks.
+ * @param dutyTicks Pulse width, the uint of this value is timer ticks.
+ */
+void GPT_SetupOneshotPulse(
+ GPT_Type *base, gpt_chnl_t chnlNumber, gpt_chnl_pol_t pol, uint32_t delayTicks, uint32_t dutyTicks);
+
+/*!
+ * @brief Configures one-shot edge on the channel.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number
+ * @param pol Channel output polarity reset value.
+ * @param delayTicks Delay width before changing the edge, the uint of this value is timer ticks.
+ */
+void GPT_SetupOneshotEdge(GPT_Type *base, gpt_chnl_t chnlNumber, gpt_chnl_pol_t pol, uint32_t delayTicks);
+
+/*!
+ * @brief Configures the PWM signal parameters.
+ *
+ * Call this function to configure the PWM signal period, mode, duty cycle, and edge. Use this
+ * function to configure all GPT channels that are used to output a PWM signal.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number.
+ * @param pol PWM output polarity reset value.
+ * @param dutyPercent PWM pulse width, value should be between 0 to 100
+ * @param mode PWM operation mode, options available in enumeration ::gpt_pwm_mode_t
+ * @param pwmFreq_Hz PWM signal frequency in Hz
+ * @param srcClock_Hz GPT counter clock in Hz
+ *
+ * @return kStatus_Success if the PWM setup was successful
+ * kStatus_Error on failure
+ */
+status_t GPT_SetupPwm(GPT_Type *base,
+ gpt_chnl_t chnlNumber,
+ gpt_chnl_pol_t pol,
+ uint32_t dutyPercent,
+ gpt_pwm_mode_t mode,
+ uint32_t pwmFreq_Hz,
+ uint32_t srcClock_Hz);
+
+/*!
+ * @brief Configures the PWM mode parameters.
+ *
+ * Call this function to configure the PWM signal mode, duty cycle in ticks, and edge. Use this
+ * function to configure all GPT channels that are used to output a PWM signal.
+ * Please note that: This API is similar with GPT_SetupPwm() API, but will not set the timer period,
+ * and this API will set channel match value in timer ticks, not period percent.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number.
+ * @param pol PWM output polarity reset value.
+ * @param periodTicks PWM period width, the uint of this value is timer ticks.
+ * @param dutyTicks PWM pulse width, the uint of this value is timer ticks.
+ * @param mode PWM operation mode, options available in enumeration ::gpt_pwm_mode_t
+ *
+ * @return kStatus_Success if the PWM setup was successful
+ * kStatus_Error on failure
+ */
+status_t GPT_SetupPwmMode(GPT_Type *base,
+ gpt_chnl_t chnlNumber,
+ gpt_chnl_pol_t pol,
+ uint32_t periodTicks,
+ uint32_t dutyTicks,
+ gpt_pwm_mode_t mode);
+
+/*!
+ * @brief Updates the duty cycle of an active PWM signal.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number.
+ * @param dutyPercent New PWM pulse width; The value should be between 0 to 100
+ * 0=inactive signal(0% duty cycle)...
+ * 100=active signal (100% duty cycle)
+ *
+ * @return kStatus_Success if the PWM update was successful
+ * kStatus_Error on failure
+ */
+status_t GPT_UpdatePwmDutycycle(GPT_Type *base, gpt_chnl_t chnlNumber, uint8_t dutyPercent);
+
+/*!
+ * @brief Pause the PWM signal.
+ *
+ * @param base GPT peripheral base address
+ * @param chnlNumber The channel number.
+ *
+ * @return kStatus_Success if the PWM update was successful
+ * kStatus_Error on failure
+ */
+status_t GPT_PausePwm(GPT_Type *base, gpt_chnl_t chnlNumber);
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected GPT interrupts.
+ *
+ * @param base GPT peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::gpt_interrupt_enable_t
+ */
+void GPT_EnableInterrupts(GPT_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the selected GPT interrupts.
+ *
+ * @param base GPT peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::gpt_interrupt_enable_t
+ */
+void GPT_DisableInterrupts(GPT_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the enabled GPT interrupts.
+ *
+ * @param base GPT peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ * enumeration ::gpt_interrupt_enable_t
+ */
+uint32_t GPT_GetEnabledInterrupts(GPT_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the GPT status flags.
+ *
+ * @param base GPT peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ * enumeration ::gpt_status_flags_t
+ */
+uint32_t GPT_GetStatusFlags(GPT_Type *base);
+
+/*!
+ * @brief Clears the GPT status flags.
+ *
+ * @param base GPT peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ * enumeration ::gpt_status_flags_t
+ */
+void GPT_ClearStatusFlags(GPT_Type *base, uint32_t mask);
+
+/*! @}*/
+
+/*!
+ * @name Read and write the timer period
+ * @{
+ */
+
+/*!
+ * @brief Sets the timer period in units of ticks for the GPT instance.
+ *
+ * Timers counts from 0 until it equals the count value set here. The count value is written to
+ * the CNT_UPP_VAL register.
+ * The period update take effects during the next counter-reach-upper event. To guarantee an
+ * immediate update, use GPT_ResetTimer() after setting the period.
+ *
+ * @note
+ * Call the utility macros provided in the fsl_common.h to convert usec or msec to ticks.
+ *
+ * @param base GPT peripheral base address
+ * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
+ */
+void GPT_SetTimerPeriod(GPT_Type *base, uint32_t ticks);
+
+/*!
+ * @brief Reads the current timer counting value.
+ *
+ * This function returns the real-time timer counting value in a range from 0 to a
+ * timer period.
+ *
+ * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
+ *
+ * @param base GPT peripheral base address
+ *
+ * @return The current counter value in ticks
+ */
+uint32_t GPT_GetCurrentTimerCount(GPT_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the GPT counter.
+ *
+ * @param base GPT peripheral base address
+ */
+void GPT_StartTimer(GPT_Type *base);
+
+/*!
+ * @brief Stops the GPT counter.
+ *
+ * @param base GPT peripheral base address
+ */
+void GPT_StopTimer(GPT_Type *base);
+
+/*!
+ * @brief Performs a GPT counter reset.
+ *
+ * @param base GPT peripheral base address
+ */
+void GPT_ResetTimer(GPT_Type *base);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_GPT_H_*/
diff --git a/drivers/mw320/i2c/driver_mw_i2c.cmake b/drivers/mw320/i2c/driver_mw_i2c.cmake
new file mode 100644
index 000000000..a740f0275
--- /dev/null
+++ b/drivers/mw320/i2c/driver_mw_i2c.cmake
@@ -0,0 +1,14 @@
+#Description: MW_I2C Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_i2c component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_i2c.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/i2c/driver_mw_i2c_dmac.cmake b/drivers/mw320/i2c/driver_mw_i2c_dmac.cmake
new file mode 100644
index 000000000..a2284474a
--- /dev/null
+++ b/drivers/mw320/i2c/driver_mw_i2c_dmac.cmake
@@ -0,0 +1,15 @@
+#Description: MW_I2C DMAC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_i2c_dmac component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_i2c_dmac.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_mw_dmac)
+include(driver_mw_i2c)
diff --git a/drivers/mw320/i2c/fsl_i2c.c b/drivers/mw320/i2c/fsl_i2c.c
new file mode 100644
index 000000000..19a2ae906
--- /dev/null
+++ b/drivers/mw320/i2c/fsl_i2c.c
@@ -0,0 +1,1709 @@
+/*
+ * Copyright 2020,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_i2c.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.i2c"
+#endif
+
+/*! brief i2c master transfer state, used in I2C driver internal master transfer state machine. */
+enum _i2c_master_transfer_states
+{
+ kMasterIdleState = 0x0U, /*!< I2C bus idle. */
+ kMasterSendCommandState = 0x1U, /*!< Send command byte phase. */
+ kMasterSendDataState = 0x2U, /*!< Send data transfer phase. */
+ kMasterReceiveDataState = 0x3U, /*!< Receive data transfer phase. */
+ kMasterWaitForCompletionState = 0x4U, /*!< Wait for stop signal detected to complete the transfer phase. */
+};
+
+/*******************************************************************************
+ * Driver Internal Functions Declaration
+ ******************************************************************************/
+/*!
+ * @brief Wait until there is room in tx FIFO and checks bus errors in master mode.
+ *
+ * @note: The API only checks the error status that occured on bus, error caused by user misuse such as
+ * kI2C_RxUnderflowInterruptFlag, kI2C_TxOverflowInterruptFlag or kI2C_MasterOperateWhenDisabledFlag will not be checked
+ *
+ * @param base The I2C peripheral base address.
+ * @retval #kStatus_I2C_RxHardwareOverrun Master rx FIFO overflow
+ * @retval #kStatus_I2C_GeneralCall_Nak Master nacked after issueing general call
+ * @retval #kStatus_I2C_ArbitrationLost Master lost arbitration when addressing
+ * @retval #kStatus_I2C_Nak Master nacked during data transmitting
+ * @retval #kStatus_I2C_Addr_Nak Master nacked during slave probing
+ */
+static status_t I2C_MasterWaitForTxReady(I2C_Type *base);
+
+/*!
+ * @brief Wait until there is room in tx FIFO and checks bus errors in slave mode.
+ *
+ * @note: The API only checks the error status that occured on bus, error caused by user misuse such as
+ * kI2C_RxUnderflowInterruptFlag, kI2C_TxOverflowInterruptFlag, kI2C_SlaveReadWhenRequestedDataFlag or
+ * kI2C_SlaveDisabledWhileBusy will not be checked
+ *
+ * @param base The I2C peripheral base address.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_RxHardwareOverrun Slave rx FIFO overflow
+ * @retval #kStatus_I2C_TxFifoFlushed Slave is addressed and is requested data but there are still old data remaining in
+ * tx FIFO
+ * @retval #kStatus_I2C_ArbitrationLost Data on SDA is not the same as slave transmitted
+ * @retval #kStatus_I2C_Nak Slave nacked by master
+ */
+static status_t I2C_SlaveWaitForTxReady(I2C_Type *base);
+
+/*!
+ * @brief Prepares the master transfer software state machine.
+ * @param base I2C base pointer
+ * @param handle pointer to i2c_master_transfer_handle_t structure which stores the transfer state.
+ */
+static void I2C_MasterInitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle);
+
+/*!
+ * @brief Runs master transfer softerware state machine to perform transfer.
+ *
+ * Master software state machine controls transfer state, perfroms master data transfer according to user's transfer
+ * configuration. For example, if user sets the transfer configuration @ref i2c_master_transfer_t to perform master read
+ * with command, this function will execute state in such order: kMasterSendCommandState(Send subaddress),
+ * kMasterReceiveDataState(Recieve data).
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_transfer_handle_t structure which stores the transfer state
+ * @param isDone input param to get whether transfer is done, true is done
+ * @retval kStatus_Success No error found.
+ * @retval #kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval #kStatus_I2C_Nak Received Nak error.
+ * @retval #kStatus_I2C_Addr_Nak Received Nak during addressing error.
+ * @retval #kStatus_I2C_GeneralCall_Nak Master Nacked after issueing general call
+ * @retval #kStatus_I2C_Timeout Transfer error, timeout happens when waiting for status flags to change.
+ */
+static status_t I2C_MasterRunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone);
+
+/*!
+ * @brief Master interrupt handler.
+ *
+ * @param base I2C base pointer.
+ * @param i2cHandle pointer to i2c_master_handle_t structure.
+ */
+static void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
+
+/*!
+ * @brief Slave interrupt handler.
+ *
+ * @param base I2C base pointer.
+ * @param i2cHandle pointer to i2c_slave_handle_t structure which stores the transfer state
+ */
+static void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
+
+/*!
+ * @brief Shared IRQ handler that can call both master and slave ISRs.
+ *
+ * The master and slave ISRs are called through function pointers in order to decouple
+ * this code from the ISR functions. Without this, the linker would always pull in both
+ * ISRs and every function they call, even if only the functional API was used.
+ *
+ * @param base I2C base pointer.
+ * @param instance The I2C peripheral instance number.
+ */
+static void I2C_CommonIRQHandler(I2C_Type *base, uint32_t instance);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! brief Pointers to i2c bases for each instance. */
+static I2C_Type *const s_I2cBases[] = I2C_BASE_PTRS;
+
+/*! brief Pointers to i2c IRQ number for each instance. */
+const IRQn_Type s_I2cIrqs[] = I2C_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! brief Pointers to i2c clocks for each instance. */
+static const clock_ip_name_t i2cClocks[] = I2C_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! brief Pointers to i2c handles for each instance. */
+void *s_i2cHandles[ARRAY_SIZE(s_I2cBases)];
+
+/*! brief Pointer to master IRQ handler for each instance. */
+i2c_isr_t s_i2cMasterIsr;
+
+/*! brief Pointer to slave IRQ handler for each instance. */
+static i2c_isr_t s_i2cSlaveIsr;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static status_t I2C_MasterWaitForTxReady(I2C_Type *base)
+{
+ status_t result = kStatus_Success;
+ uint32_t status;
+
+#if I2C_RETRY_TIMES
+ uint32_t waitTimes = I2C_RETRY_TIMES;
+#endif
+ do
+ {
+ /* Check for error flags. */
+ status = I2C_MasterGetStatusFlags(base);
+ result = I2C_MasterCheckAndClearError(base, status);
+ if (kStatus_Success != result)
+ {
+ break;
+ }
+#if I2C_RETRY_TIMES
+ /* Wait until tx FIFO is not full */
+ } while (((base->IC_STATUS & I2C_IC_STATUS_TFNF) == 0U) && (0U != --waitTimes));
+
+ if (0U == waitTimes)
+ {
+ result = kStatus_I2C_Timeout;
+ }
+#else
+ /* Wait until tx FIFO is not full */
+ } while ((base->IC_STATUS & I2C_IC_STATUS_TFNF_MASK) == 0U);
+#endif
+
+ return result;
+}
+
+static status_t I2C_SlaveWaitForTxReady(I2C_Type *base)
+{
+ status_t result = kStatus_Success;
+ uint32_t status;
+
+#if I2C_RETRY_TIMES
+ uint32_t waitTimes = I2C_RETRY_TIMES;
+#endif
+ do
+ {
+ /* Check for error flags. */
+ status = I2C_SlaveGetStatusFlags(base);
+ result = I2C_SlaveCheckAndClearError(base, status);
+ if (kStatus_Success != result)
+ {
+ break;
+ }
+ /* Wait until master is requesting data */
+#if I2C_RETRY_TIMES
+ } while (((base->IC_RAW_INTR_STAT & I2C_IC_RAW_INTR_STAT_RD_REQ_MASK) == 0U) && (0U != --waitTimes));
+
+ if (0U == waitTimes)
+ {
+ result = kStatus_I2C_Timeout;
+ }
+#else
+ } while ((base->IC_RAW_INTR_STAT & I2C_IC_RAW_INTR_STAT_RD_REQ_MASK) == 0U);
+#endif
+ /* Clear read request flag */
+ (void)base->IC_CLR_RD_REQ;
+
+ return result;
+}
+
+/*!
+ * brief Gets instance number for I2C module.
+ *
+ * param base I2C base pointer.
+ * retval The number of the instance.
+ */
+uint32_t I2C_GetInstance(I2C_Type *base)
+{
+ uint32_t instance;
+ for (instance = 0U; instance < ARRAY_SIZE(s_I2cBases); ++instance)
+ {
+ if (s_I2cBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_I2cBases));
+ return instance;
+}
+
+/*!
+ * brief Clears the I2C master status flags.
+ *
+ * param base I2C base pointer
+ * param statusFlags The status flag mask, can be a single flag or several flags in #_i2c_status_flags ORed
+ * together.
+ */
+void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusFlags)
+{
+ /* These 13 flags from kI2C_Master7bitAddressNackFlag to kI2C_MasterArbitrationLostFlag are cleared when
+ kI2C_TxAbortInterruptFlag is cleared, so add the kI2C_TxAbortInterruptFlag if not included in the mask. */
+ if ((statusFlags & 0x3FFE0000UL) != 0U)
+ {
+ statusFlags |= (uint32_t)kI2C_TxAbortInterruptFlag;
+ }
+ if ((statusFlags & (uint32_t)kI2C_MasterAllClearFlags) != 0U)
+ {
+ /* Ignore other auto cleared flags. */
+ statusFlags &= (uint32_t)kI2C_MasterAllClearFlags;
+ /* The software clearable bits are cleared individually by reading their corresponding whole register */
+ /* Store the first register base's address */
+ uint32_t const volatile *readReg = &base->IC_CLR_RX_UNDER;
+ uint8_t regNum;
+ /* Bit 0,1,2,3,4,6,8 except 2 and 4 are clearable */
+ for (uint8_t i = 0U; i <= 10U; ++i)
+ {
+ /* If bit i is set, then read the corresponding whole register to clear it */
+ if ((statusFlags & (0x1U << i)) != 0U)
+ {
+ regNum = i;
+ if (i == 3U)
+ {
+ regNum -= 1U;
+ }
+ else if (i > 5U)
+ {
+ regNum -= 2U;
+ }
+ /* Read the register */
+ *(readReg + regNum);
+ }
+ }
+ }
+}
+
+/*!
+ * brief Clears the I2C slave status flags.
+ *
+ * param base I2C base pointer
+ * param statusFlags The status flag mask, can be a single flag or several flags in #_i2c_slave_status_flags ORed
+ * together
+ */
+void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusFlags)
+{
+ /* These 3 flags are cleared when kI2C_TxAbortInterruptFlag is cleared, so add the kI2C_TxAbortInterruptFlag if not
+ * included in the mask. */
+ if ((statusFlags & (uint32_t)(kI2C_SlaveFlushTxFifoFlag | kI2C_SlaveArbitrationLostFlag |
+ kI2C_SlaveReadWhenRequestedDataFlag)) != 0U)
+ {
+ statusFlags |= (uint32_t)kI2C_TxAbortInterruptFlag;
+ }
+ if ((statusFlags & (uint32_t)kI2C_SlaveAllClearFlags) != 0U)
+ {
+ /* Ignore other auto cleared flags. */
+ statusFlags &= (uint32_t)kI2C_SlaveAllClearFlags;
+ /* The software clearable bits are cleared individually by reading their corresponding whole register */
+ /* Store the first register base's address */
+ uint32_t const volatile *readReg = &base->IC_CLR_RX_UNDER;
+ uint8_t regNum;
+ /* Bit 0-11 except 2 and 4 are clearable */
+ for (uint8_t i = 0U; i <= 11U; ++i)
+ {
+ /* If bit i is set, then read the corresponding whole register to clear it */
+ if ((statusFlags & (0x1U << i)) != 0U)
+ {
+ regNum = i;
+ if (i == 3U)
+ {
+ regNum -= 1U;
+ }
+ else if (i >= 5U)
+ {
+ regNum -= 2U;
+ }
+ /* Read the register */
+ *(readReg + regNum);
+ }
+ }
+ }
+}
+
+/*!
+ * brief Sets the I2C master configuration structure to default values.
+ *
+ * The purpose of this API is to initialize the configuration structure to default value for @ref I2C_MasterInit to use.
+ * Use the unchanged structure in @ref I2C_MasterInit or modify the structure before calling @ref I2C_MasterInit.
+ * This is an example:
+ * code
+ * i2c_master_config_t config;
+ * I2C_MasterGetDefaultConfig(&config);
+ * I2C_MasterInit(I2C0, &config, 12000000U);
+ * endcode
+ *
+ * param masterConfig Pointer to the master configuration structure
+ */
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig)
+{
+ /* Initializes the configure structure to zero. */
+ (void)memset(masterConfig, 0, sizeof(*masterConfig));
+
+ masterConfig->speed = kI2C_MasterSpeedStandard;
+ masterConfig->addressingMode = kI2C_AddressMatch7bit;
+ masterConfig->highSpeedMasterCodeAddress = 0x1U;
+ masterConfig->rxFifoWaterMark = 0U;
+ masterConfig->txFifoWaterMark = 8U;
+ masterConfig->dataHoldTime = 0x1U;
+ masterConfig->dataSetupTime = 0x64U;
+ masterConfig->glitchFilter = 0x6U;
+ masterConfig->glitchFilterHighSpeed = 0x2U;
+ masterConfig->enable = false;
+}
+
+/*!
+ * brief Initializes the I2C peripheral to operate as master.
+ *
+ * This API initialize the I2C module for master operation.
+ *
+ * note If FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL is enbaled by user, the init function will not ungate I2C clock source
+ * before initialization, to avoid hardfault, user has to manually enable ungate the clock source before calling the API
+ *
+ * The configuration structure can be filled manully or be set with default values by calling
+ * ref I2C_MasterGetDefaultConfig. This is an example.
+ * code
+ * I2C_MasterGetDefaultConfig(&config);
+ * I2C_MasterInit(I2C0, &config, 12000000U);
+ * endcode
+ *
+ * param base I2C base pointer
+ * param masterConfig Pointer to the master configuration structure
+ * param sourceClock_Hz Frequency in Hertz of the I2C functional clock source
+ */
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t sourceClock_Hz)
+{
+ assert((base != NULL) && (masterConfig != NULL) && (sourceClock_Hz != 0U));
+ assert(masterConfig->txFifoWaterMark < I2C_GetTxFifoDepth(base));
+ assert(masterConfig->rxFifoWaterMark < I2C_GetRxFifoDepth(base));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate the clock. */
+ CLOCK_EnableClock(i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+ I2C_MasterSetSpeedMode(base, masterConfig->speed, sourceClock_Hz);
+ I2C_MasterSetAddressingMode(base, masterConfig->addressingMode);
+ I2C_MasterSetHighSpeedAddress(base, masterConfig->highSpeedMasterCodeAddress);
+ I2C_SetRxWaterMark(base, masterConfig->rxFifoWaterMark);
+ I2C_SetTxWaterMark(base, masterConfig->txFifoWaterMark);
+ I2C_SetSdaHoldTime(base, masterConfig->dataHoldTime);
+ I2C_SetSdaSetupTime(base, masterConfig->dataSetupTime);
+ I2C_SetGlitchFilter(base, masterConfig->glitchFilter);
+ I2C_SetGlitchFilterHighSpeed(base, masterConfig->glitchFilterHighSpeed);
+ I2C_EnableMaster(base, true);
+ I2C_Enable(base, masterConfig->enable);
+}
+
+/*!
+ * brief De-initializes the I2C peripheral. Call this API to disable the I2C module.
+ *
+ * param base I2C base pointer
+ */
+void I2C_MasterDeinit(I2C_Type *base)
+{
+ /* Wait until master is not active */
+ while ((base->IC_STATUS & I2C_IC_STATUS_MST_ACTIVITY_MASK) != 0U)
+ {
+ }
+ /* Disable I2C module. */
+ I2C_Enable(base, false);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Disable I2C clock. */
+ CLOCK_DisableClock(i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Sets the I2C slave configuration structure to default values.
+ *
+ * The purpose of this API is to initialize the configuration structure for @ref I2C_SlaveInit to use. Use the unchanged
+ * initialized structure in @ref I2C_SlaveInit or modify the structure before calling @ref I2C_SlaveInit.
+ * This is an example.
+ * code
+ * i2c_slave_config_t config;
+ * config.slaveAdress = 0x7FU;
+ * I2C_SlaveGetDefaultConfig(&config);
+ * endcode
+ *
+ * param slaveConfig Pointer to the slave configuration structure
+ */
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig)
+{
+ assert(slaveConfig != NULL);
+
+ slaveConfig->addressingMode = kI2C_AddressMatch7bit;
+ slaveConfig->rxFifoWaterMark = 0U;
+ slaveConfig->txFifoWaterMark = 255U;
+ slaveConfig->dataHoldTime = 0x1U;
+ slaveConfig->dataSetupTime = 0x64U;
+ slaveConfig->ackGeneralCall = true;
+ slaveConfig->glitchFilter = 0x6U;
+ slaveConfig->glitchFilterHighSpeed = 0x2U;
+ slaveConfig->enable = false;
+}
+
+/*!
+ * brief Initializes the I2C peripheral to operate as slave.
+ *
+ * This API initialize the I2C module for slave operation. User can also configure whether to enable the module in the
+ * function.
+ *
+ * note If FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL is enbaled by user, the init function will not ungate I2C clock source
+ * before initialization, to avoid hardfault, user has to manually ungate the clock source before calling the API
+ *
+ * The configuration structure can be filled manully or be set with default values by calling
+ * ref I2C_SlaveGetDefaultConfig. This is an example.
+ * code
+ * i2c_slave_config_t sConfig;
+ * I2C_SlaveGetDefaultConfig(&sConfig);
+ * sConfig.address = 0x2AU;
+ * I2C_SlaveInit(I2C0, &sConfig);
+ * endcode
+ *
+ * param base I2C base pointer
+ * param slaveConfig Pointer to the slave configuration structure
+ */
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig)
+{
+ assert((base != NULL) && (slaveConfig != NULL));
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Ungate the clock. */
+ CLOCK_EnableClock(i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ I2C_SlaveSetAddressingMode(base, slaveConfig->addressingMode, slaveConfig->slaveAddress);
+ I2C_SetRxWaterMark(base, slaveConfig->rxFifoWaterMark);
+ I2C_SetTxWaterMark(base, slaveConfig->txFifoWaterMark);
+ I2C_SetSdaHoldTime(base, slaveConfig->dataHoldTime);
+ I2C_SetSdaSetupTime(base, slaveConfig->dataSetupTime);
+ I2C_EnableAckGeneralCall(base, slaveConfig->ackGeneralCall);
+ I2C_SetGlitchFilter(base, slaveConfig->glitchFilter);
+ I2C_SetGlitchFilterHighSpeed(base, slaveConfig->glitchFilterHighSpeed);
+ I2C_EnableMaster(base, false);
+ I2C_Enable(base, slaveConfig->enable);
+}
+
+/*!
+ * brief De-initializes the I2C peripheral. Call this API to disable the I2C module.
+ *
+ * param base I2C base pointer
+ */
+void I2C_SlaveDeinit(I2C_Type *base)
+{
+ /* Wait until slave is not active */
+ while ((base->IC_STATUS & I2C_IC_STATUS_SLV_ACTIVITY_MASK) != 0U)
+ {
+ }
+ /* Disable I2C module. */
+ I2C_Enable(base, false);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Disable I2C clock. */
+ CLOCK_DisableClock(i2cClocks[I2C_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief Sets the I2C transaction speed mode.
+ *
+ * After the I2C module is initialized as master, user can call this function to change the transfer baud rate. There
+ * are 3 speed modes to choos from, kI2C_MasterSpeedStandard for 100kbps, kI2C_MasterSpeedFast for 400kbps and
+ * kI2C_MasterSpeedHigh for 3.4Mbps.
+ *
+ * param base I2C base pointer.
+ * param speed Master transfer speed mode to be configured
+ * param sourceClock_Hz I2C peripheral clock frequency in Hz
+ */
+void I2C_MasterSetSpeedMode(I2C_Type *base, i2c_master_speed_mode_t speed, uint32_t sourceClock_Hz)
+{
+ assert((base != NULL) && ((uint8_t)speed != 0U) && (sourceClock_Hz != 0U));
+
+ /* Set speed mode */
+ base->IC_CON = (base->IC_CON & ~I2C_IC_CON_SPEED_MASK) | I2C_IC_CON_SPEED((uint8_t)speed);
+
+ uint16_t highCount;
+ uint16_t lowCount;
+ /* Configure clock count register */
+ if (speed == kI2C_MasterSpeedStandard)
+ {
+ highCount = (5U * sourceClock_Hz / 100000U + 5U) / 10U;
+ lowCount = (5U * sourceClock_Hz / 100000U + 5U) / 10U;
+ base->IC_SS_SCL_HCNT = (uint32_t)highCount;
+ base->IC_SS_SCL_LCNT = (uint32_t)lowCount;
+ }
+ else if (speed == kI2C_MasterSpeedFast)
+ {
+ highCount = (sourceClock_Hz / 100000U + 5U) / 10U;
+ lowCount = (15U * sourceClock_Hz / 1000000U + 5U) / 10U;
+ base->IC_FS_SCL_HCNT = (uint32_t)highCount;
+ base->IC_FS_SCL_LCNT = (uint32_t)lowCount;
+ }
+ else
+ {
+ highCount = (4U * sourceClock_Hz / 1000000U + 5U) / 10U;
+ lowCount = (6U * sourceClock_Hz / 1000000U + 5U) / 10U;
+ base->IC_HS_SCL_HCNT = (uint32_t)highCount;
+ base->IC_HS_SCL_LCNT = (uint32_t)lowCount;
+ }
+}
+
+/*!
+ * brief Convert provided status flags to status code, and clear any errors if present.
+ *
+ * note: The API only checks the error status that occured on bus, error caused by user misuse such as
+ * kI2C_RxUnderflowInterruptFlag, kI2C_TxOverflowInterruptFlag or kI2C_MasterOperateWhenDisabledFlag will not be checked
+ *
+ * param base The I2C peripheral base address.
+ * param status Status flags to check.
+ * retval #kStatus_Success
+ * retval #kStatus_I2C_RxHardwareOverrun Master rx FIFO overflow
+ * retval #kStatus_I2C_GeneralCall_Nak Master nacked after issueing general call
+ * retval #kStatus_I2C_ArbitrationLost Master lost arbitration when addressing
+ * retval #kStatus_I2C_Nak Master nacked during data transmitting
+ * retval #kStatus_I2C_Addr_Nak Master nacked during slave probing
+ */
+status_t I2C_MasterCheckAndClearError(I2C_Type *base, uint32_t status)
+{
+ status_t result = kStatus_Success;
+ status &= (uint32_t)kI2C_MasterErrorFlags;
+ if (0U != status)
+ {
+ /* Select the correct error code. Ordered by severity, with bus issues first. */
+ if (0U != (status & (uint32_t)kI2C_RxOverflowInterruptFlag))
+ {
+ /* Empty rx FIFO */
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) != 0U)
+ {
+ (void)I2C_ReadByte(base);
+ }
+ result = kStatus_I2C_RxHardwareOverrun;
+ }
+ if (0U != (status & (uint32_t)kI2C_MasterGeneralCallNackFlag))
+ {
+ result = kStatus_I2C_GeneralCall_Nak;
+ }
+ else if (0U != (status & (uint32_t)kI2C_MasterArbitrationLostFlag))
+ {
+ result = kStatus_I2C_ArbitrationLost;
+ }
+ else if (0U != (status & (uint32_t)kI2C_MasterDataNackFlag))
+ {
+ result = kStatus_I2C_Nak;
+ }
+ else if (0U != (status & (uint32_t)(kI2C_Master7bitAddressNackFlag | kI2C_Master10bitAddressNack1Flag |
+ kI2C_Master10bitAddressNack2Flag)))
+ {
+ result = kStatus_I2C_Addr_Nak;
+ }
+ else
+ {
+ /* Avoid MISRA 15.7 violation */
+ }
+
+ /* Clear the flags. */
+ I2C_MasterClearStatusFlags(base, status);
+ }
+ else
+ {
+ /* Avoid MISRA 15.7 violation */
+ }
+
+ return result;
+}
+
+/*!
+ * brief Sends a piece of data to I2C bus in master mode in blocking way.
+ *
+ * Call this function when using I2C as master to send certain bytes of data to bus. This function uses the blocking
+ * way, which means it does not return until all the data is sent to bus.
+ *
+ * note The I2C module generates START/STOP/RESTART automatically. When tx FIFO state changes from empty to not empty,
+ * start signal is generated; when tx FIFO is empty again, stop signal is generated; when read command follows a write
+ * command, restart signal is generated in between. So stop signal will be generated after this API returns, and before
+ * calling this API if tx FIFO is empty, start signal will be generated first automatically, if tx FIFO is not empty and
+ * the last command in tx FIFO is write, restart signal will be generated first automatically.
+ *
+ * param base I2C base pointer.
+ * param data The pointer to the data to be transmitted.
+ * param txSize The length in bytes of the data to be transmitted.
+ * retval kStatus_Success Successfully complete the data transmission.
+ * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * retval kStatus_I2C_Nak Transfer error, receive NAK during transfer.
+ * retval kStatus_I2C_Addr_Nak Transfer error, receive NAK during addressing, only applies when tx FIFO is empty before
+ * calling this API.
+ * retval #kStatus_I2C_Timeout Transfer error, timeout happens when waiting for status flags to change.
+ */
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *data, size_t txSize)
+{
+ assert(NULL != data);
+
+ status_t result = kStatus_Success;
+ uint32_t statusFlags;
+ uint8_t *buf = (uint8_t *)data;
+
+ /* Send data buffer */
+ while (0U != (txSize--))
+ {
+ /* Wait until there is room in the fifo. This also checks for errors. */
+ result = I2C_MasterWaitForTxReady(base);
+ if (kStatus_Success != result)
+ {
+ break;
+ }
+
+ I2C_WriteByte(base, *buf++);
+ }
+
+ if (result == kStatus_Success)
+ {
+ statusFlags = I2C_MasterGetStatusFlags(base);
+ while ((statusFlags & (uint32_t)kI2C_TxFifoEmptyFlag) != 0U)
+ {
+ result = I2C_MasterCheckAndClearError(base, statusFlags);
+ if (result != kStatus_Success)
+ {
+ break;
+ }
+ else
+ {
+ statusFlags = I2C_MasterGetStatusFlags(base);
+ }
+ }
+ }
+ return result;
+}
+
+/*!
+ * brief Receives a piece of data from I2C bus in master mode in blocking way.
+ *
+ * Call this function when using I2C as master to receive certain bytes of data from bus. This function uses the
+ * blocking way, which means it does not return until all the data is received or is nacked by slave.
+ *
+ * note When doing read operation, software needs to push dummy data to tx FIFO with read command to generate clock,
+ * plus I2C module generates START/STOP/RESTART automatically, meaning when tx FIFO state changes from empty to not
+ * empty, start signal is generated, when tx FIFO is empty again, stop signal is generated, when read command follows
+ * a write command, restart signal is generated in between. So stop signal will be generated after this API returns,
+ * and before calling this API if tx FIFO is empty, start signal will be generated first automatically, if tx FIFO is
+ * not empty and the last command in tx FIFO is write, restart signal will be generated first automatically.
+ *
+ * param base I2C base pointer.
+ * param data The pointer to the data to store the received data.
+ * param rxSize The length in bytes of the data to be received.
+ * retval kStatus_Success Successfully complete the data transmission.
+ * retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *data, size_t rxSize)
+{
+ status_t result = kStatus_Success;
+ uint8_t txCountEach = 0U;
+ uint8_t rxCountEach = 0U;
+ uint32_t txSize = rxSize;
+
+ /* Empty rx FIFO first */
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) != 0U)
+ {
+ (void)I2C_ReadByte(base);
+ }
+
+ while (txSize != 0U)
+ {
+ /* Calculate how many data can be pushed to tx FIFO */
+ txCountEach = MIN((I2C_GetTxFifoDepth(base) - I2C_GetTxFifoDataCount(base)), txSize);
+ txSize -= txCountEach;
+ /* Push dummy to tx FIFO */
+ while (txCountEach-- != 0U)
+ {
+ I2C_MasterWriteDummy(base);
+ }
+ /* Calculate how many data can be read from rx FIFO */
+ rxCountEach = MIN(I2C_GetRxFifoDataCount(base), rxSize);
+ rxSize -= rxCountEach;
+ while (rxCountEach-- != 0U)
+ {
+ *data++ = I2C_ReadByte(base);
+ }
+ }
+
+ while (rxSize-- != 0U)
+ {
+#if I2C_RETRY_TIMES
+ uint32_t waitTimes = I2C_RETRY_TIMES;
+ while (((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) == 0U) && (waitTimes-- != 0U))
+#else
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) == 0U)
+#endif
+ {
+ }
+ *data++ = I2C_ReadByte(base);
+ }
+
+ return result;
+}
+
+/*!
+ * brief Convert provided status flags to status code, and clear any errors if present.
+ *
+ * note: The API only checks the error status that occured on bus, error caused by user misuse such as
+ * kI2C_RxUnderflowInterruptFlag, kI2C_TxOverflowInterruptFlag, kI2C_SlaveReadWhenRequestedDataFlag or
+ * kI2C_SlaveDisabledWhileBusy will not be checked
+ *
+ * param base The I2C peripheral base address.
+ * param status Status flags to check.
+ * retval #kStatus_Success
+ * retval #kStatus_I2C_RxHardwareOverrun Slave rx FIFO overflow
+ * retval #kStatus_I2C_TxFifoFlushed Slave is addressed and is requested data but there are still old data remaining in
+ * tx FIFO retval #kStatus_I2C_ArbitrationLost Data on SDA is not the same as slave transmitted retval #kStatus_I2C_Nak
+ * Slave nacked by master
+ */
+status_t I2C_SlaveCheckAndClearError(I2C_Type *base, uint32_t status)
+{
+ status_t result = kStatus_Success;
+ status &= (uint32_t)kI2C_SlaveErrorFlags;
+ if (0U != status)
+ {
+ /* Select the correct error code. Ordered by severity, with bus issues first. */
+ if (0U != (status & (uint32_t)kI2C_RxOverflowInterruptFlag))
+ {
+ /* Empty rx FIFO */
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) != 0U)
+ {
+ (void)I2C_ReadByte(base);
+ }
+ result = kStatus_I2C_RxHardwareOverrun;
+ }
+ if (0U != (status & (uint32_t)kI2C_SlaveFlushTxFifoFlag))
+ {
+ result = kStatus_I2C_TxFifoFlushed;
+ }
+ else if (0U != (status & (uint32_t)kI2C_SlaveArbitrationLostFlag))
+ {
+ result = kStatus_I2C_ArbitrationLost;
+ }
+ else if (0U != (status & (uint32_t)kI2C_SlaveNackInterruptFlag))
+ {
+ result = kStatus_I2C_Nak;
+ }
+ else
+ {
+ /* Avoid MISRA 15.7 violation */
+ }
+
+ /* Clear the flags. */
+ I2C_SlaveClearStatusFlags(base, status);
+ }
+ else
+ {
+ /* Avoid MISRA 15.7 violation */
+ }
+
+ return result;
+}
+
+/*!
+ * brief Sends a piece of data to I2C bus in slave mode in blocking way.
+ *
+ * Call this funtion to let I2C slave poll register status until it is addressed, then slave sends txSize of data to bus
+ * until all the data has been sent to bus or untill it is nacked.
+ *
+ * param base I2C base pointer.
+ * param data The pointer to the data to be transferred.
+ * param txSize The length in bytes of the data to be transferred.
+ * retval #kStatus_Success
+ * retval #kStatus_I2C_TxFifoFlushed Slave is addressed and is requested data but there are still old data remaining in
+ * tx FIFO retval #kStatus_I2C_ArbitrationLost Data on SDA is not the same as slave transmitted retval #kStatus_I2C_Nak
+ * Slave nacked by master
+ */
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *data, size_t txSize)
+{
+ assert(NULL != data);
+
+ status_t result = kStatus_Success;
+ uint8_t *buf = (uint8_t *)data;
+
+ I2C_SlaveNackNextByte(base, false);
+ /* Send data buffer */
+ while (0U != (txSize--))
+ {
+ /* Wait until there is room in the fifo. This also checks for errors. */
+ result = I2C_SlaveWaitForTxReady(base);
+ if (kStatus_Success != result)
+ {
+ break;
+ }
+
+ I2C_WriteByte(base, *buf++);
+ }
+ /* For slave data is transmitted one by one after master read request is received, so after the last data is pushed
+ * to FIFO, there is no need to check whether it is nacked by master */
+ return result;
+}
+
+/*!
+ * brief Receives a piece of data from I2C bus in slave mode in blocking way.
+ *
+ * Call this funtion to let I2C slave poll register status until it is addressed, then slave receives rxSize of data
+ * until all the data has been received.
+ *
+ * param base I2C base pointer.
+ * param data The pointer to the data to store the received data.
+ * param rxSize The length in bytes of the data to be received.
+ * retval kStatus_Success Successfully complete data receive.
+ * retval kStatus_I2C_Timeout Wait status flag timeout.
+ */
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *data, size_t rxSize)
+{
+ status_t result = kStatus_Success;
+ uint8_t rxCountEach = 0U;
+
+ /* Empty rx FIFO first */
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) != 0U)
+ {
+ (void)I2C_ReadByte(base);
+ }
+
+#if I2C_RETRY_TIMES
+ uint32_t waitTimes = I2C_RETRY_TIMES;
+ while ((rxSize != 0U) && (waitTimes-- != 0U))
+#else
+ while (rxSize != 0U)
+#endif
+ {
+ /* Calculate how many data can be read from rx FIFO */
+ rxCountEach = MIN(I2C_GetRxFifoDataCount(base), rxSize);
+ rxSize -= rxCountEach;
+ while (rxCountEach-- != 0U)
+ {
+ *data++ = I2C_ReadByte(base);
+ }
+ }
+
+ return result;
+}
+
+/*!
+ * brief Performs a master polling transfer on the I2C bus.
+ *
+ * note The API does not return until the transfer succeeds or fails due to arbitration lost or receiving a NAK.
+ *
+ * param base I2C base pointer.
+ * param transferConfig Pointer to the transfer configuration structure.
+ * retval kStatus_Success Successfully complete the data transmission.
+ * retval #kStatus_I2C_Busy Previous transmission still not finished.
+ * retval #kStatus_I2C_Timeout Transfer error, timeout happens when waiting for status flags to change.
+ * retval #kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * retval #kStatus_I2C_Nak Transfer error, receive NAK during transfer.
+ * retval #kStatus_I2C_Addr_Nak Transfer error, receive NAK during slave probing.
+ * retval #kStatus_I2C_GeneralCall_Nak Transfer error, receive NAK after issueing general call.
+ */
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *transferConfig)
+{
+ assert(NULL != transferConfig);
+ assert(I2C_IsMaster(base));
+
+ if ((I2C_MasterGetStatusFlags(base) & (uint32_t)kI2C_BusBusyInterruptFlag) != 0U)
+ {
+ return kStatus_I2C_Busy;
+ }
+
+ status_t result = kStatus_Success;
+ uint8_t commandBuffer[4U];
+
+ /* Enable module */
+ I2C_Enable(base, true);
+
+ if (transferConfig->slaveAddress == 0U)
+ {
+ I2C_MasterEnableGeneralCall(base, true);
+ }
+ else
+ {
+ I2C_MasterEnableGeneralCall(base, false);
+ I2C_MasterSetTargetAddress(base, transferConfig->slaveAddress);
+ }
+
+ /* Empty rx FIFO first */
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) != 0U)
+ {
+ (void)I2C_ReadByte(base);
+ }
+
+ /* Send subaddress first, start will be issued automatically when tx FIFO is not empty */
+ if (transferConfig->subaddressSize != 0U)
+ {
+ uint8_t cmdCount;
+ for (cmdCount = 1U; cmdCount <= transferConfig->subaddressSize; cmdCount++)
+ {
+ commandBuffer[cmdCount - 1U] =
+ (uint8_t)((transferConfig->subaddress >> (8U * (transferConfig->subaddressSize - cmdCount))) & 0xffU);
+ }
+ result = I2C_MasterWriteBlocking(base, &commandBuffer[0U], transferConfig->subaddressSize);
+ }
+
+ /* Return if error. */
+ if (kStatus_Success != result)
+ {
+ if (result == kStatus_I2C_Nak)
+ {
+ result = kStatus_I2C_Addr_Nak;
+ }
+ return result;
+ }
+
+ if (transferConfig->direction == kI2C_Write)
+ {
+ result = I2C_MasterWriteBlocking(base, transferConfig->data, transferConfig->dataSize);
+ }
+ else
+ {
+ result = I2C_MasterReadBlocking(base, transferConfig->data, transferConfig->dataSize);
+ }
+
+ /* Wait until stop signal is issued automatically. */
+ while ((base->IC_RAW_INTR_STAT & I2C_IC_RAW_INTR_STAT_STOP_DET_MASK) == 0U)
+ {
+ }
+
+ /* Clear all status */
+ I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_MasterAllClearFlags);
+
+ return result;
+}
+
+/*!
+ * brief Initializes the I2C master transfer in interrupt way.
+ *
+ * This function is responsible for initializig master transfer handle, installing user callback, registering master
+ * IRQ handling function and opening global interrupt.
+ *
+ * param base I2C base pointer
+ * param handle pointer to i2c_master_transfer_handle_t structure to store the transfer state
+ * param callback pointer to user callback function
+ * param userData User configurable pointer to any data, function, structure etc that user wish to use in the callback
+ */
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+ i2c_master_handle_t *handle,
+ i2c_master_transfer_callback_t callback,
+ void *userData)
+{
+ assert(NULL != handle);
+ /* Clear out the handle. */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ uint32_t instance;
+ /* Look up instance number */
+ instance = I2C_GetInstance(base);
+
+ /* Save callback and userData. */
+ handle->completionCallback = callback;
+ handle->userData = userData;
+
+ /* Save the handle into static handle array */
+ s_i2cHandles[instance] = handle;
+ /* Save IRQ handler into static ISR function pointer. */
+ s_i2cMasterIsr = I2C_MasterTransferHandleIRQ;
+
+ /* Disable internal IRQs and enable global IRQ. */
+ I2C_DisableInterrupts(base, (uint16_t)kI2C_AllInterruptEnable);
+ (void)EnableIRQ(s_I2cIrqs[instance]);
+}
+
+/*!
+ * brief Initiates a master transfer on the I2C bus in interrupt way.
+ *
+ * note Transfer in interrupt way is non-blocking which means this API returns immediately after transfer initiates.
+ * User can call @ref I2C_MasterTransferGetCount to get the count of data that master has transmitted/received and check
+ * transfer status. If the return status is kStatus_NoTransferInProgress, the transfer is finished. Also if user
+ * installs a user callback when calling @ref I2C_MasterTransferCreateHandle before, the callback will be invoked when
+ * transfer finishes.
+ *
+ * param base I2C base pointer
+ * param handle pointer to i2c_master_transfer_handle_t structure which stores the transfer state.
+ * param transfer Pointer to the transfer configuration structure.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval #kStatus_I2C_Busy Previous transmission still not finished.
+ */
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *transfer)
+{
+ assert((NULL != handle) && (NULL != transfer));
+
+ /* Return busy if another transaction is in progress. */
+ if ((handle->state != (uint8_t)kMasterIdleState) ||
+ ((I2C_MasterGetStatusFlags(base) & (uint32_t)kI2C_BusBusyInterruptFlag) != 0U))
+ {
+ return kStatus_I2C_Busy;
+ }
+
+ /* Disable I2C IRQ sources while we configure stuff. */
+ I2C_DisableInterrupts(base, (uint16_t)kI2C_AllInterruptEnable);
+
+ /* Save transfer into handle. */
+ handle->transfer = *transfer;
+
+ /* Generate commands to send. */
+ I2C_MasterInitTransferStateMachine(base, handle);
+ /* Clear all flags. */
+ I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_MasterAllClearFlags);
+ /* Enable I2C internal IRQ sources */
+ I2C_EnableInterrupts(base, (uint16_t)(kI2C_TxRequestInterruptEnable | kI2C_TxAbortInterruptEnable));
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Gets the master transfer count and status during a interrupt transfer.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_master_handle_t structure which stores the transfer state.
+ * param count Pointer to number of bytes transferred so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_NoTransferInProgress Curent no transfer is in progress.
+ * retval kStatus_Success Successfully obtained the count.
+ */
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count)
+{
+ assert(NULL != handle);
+ status_t result = kStatus_Success;
+ if (NULL == count)
+ {
+ result = kStatus_InvalidArgument;
+ }
+ /* Catch when there is not an active transfer. */
+ else if (handle->state == (uint8_t)kMasterIdleState)
+ {
+ *count = 0U;
+ result = kStatus_NoTransferInProgress;
+ }
+ else
+ {
+ /* Cache some fields with IRQs disabled. This ensures all field values */
+ /* are synchronized with each other during an ongoing transfer. */
+ uint16_t irqs = I2C_GetEnabledInterrupts(base);
+ I2C_DisableInterrupts(base, irqs);
+
+ /* Get transfer count based on current transfer state. */
+ switch (handle->state)
+ {
+ case (uint8_t)kMasterIdleState:
+ case (uint8_t)kMasterSendCommandState:
+ *count = 0;
+ break;
+
+ case (uint8_t)kMasterSendDataState:
+ *count = handle->transfer.dataSize - handle->transmitSize - I2C_GetTxFifoDataCount(base);
+ break;
+
+ case (uint8_t)kMasterReceiveDataState:
+ *count = handle->transfer.dataSize - handle->receiveSize;
+ break;
+
+ case (uint8_t)kMasterWaitForCompletionState:
+ if (handle->transfer.direction == kI2C_Write)
+ {
+ *count = handle->transfer.dataSize - I2C_GetTxFifoDataCount(base);
+ }
+ else
+ {
+ *count = handle->transfer.dataSize;
+ }
+ break;
+
+ default:
+ assert(false);
+ break;
+ }
+ I2C_EnableInterrupts(base, irqs);
+ }
+ return result;
+}
+
+/*!
+ * brief Aborts an in-process transfer in interrupt way.
+ *
+ * note This API can be called at any time after a transfer of interrupt way initiates and before it finishes to abort
+ * the transfer early.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ */
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
+{
+ if (handle->state != (uint8_t)kMasterIdleState)
+ {
+ /* Disable internal IRQ enables. */
+ I2C_DisableInterrupts(base, (uint16_t)kI2C_AllInterruptEnable);
+
+ /* Disable the module to reset FIFO. */
+ I2C_Enable(base, false);
+
+ /* Reset handle. */
+ handle->state = (uint8_t)kMasterIdleState;
+ }
+}
+
+static void I2C_MasterInitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle)
+{
+ /* Enable module */
+ I2C_Enable(base, true);
+
+ if (handle->transfer.slaveAddress == 0U)
+ {
+ I2C_MasterEnableGeneralCall(base, true);
+ }
+ else
+ {
+ I2C_MasterEnableGeneralCall(base, false);
+ I2C_MasterSetTargetAddress(base, handle->transfer.slaveAddress);
+ }
+
+ /* Empty rx FIFO first */
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) != 0U)
+ {
+ (void)I2C_ReadByte(base);
+ }
+
+ handle->transmitSize = handle->transfer.dataSize;
+ handle->receiveSize = handle->transfer.dataSize;
+
+ if (handle->transfer.subaddressSize != 0U)
+ {
+ handle->state = kMasterSendCommandState;
+ }
+ else if (handle->transfer.direction == kI2C_Write)
+ {
+ handle->state = kMasterSendDataState;
+ }
+ else
+ {
+ handle->state = kMasterReceiveDataState;
+ }
+}
+
+static void I2C_MasterTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
+{
+ assert(i2cHandle != NULL);
+ i2c_master_handle_t *handle = (i2c_master_handle_t *)i2cHandle;
+ bool isDone = false;
+ status_t result;
+
+ if (handle->state != (uint8_t)kMasterIdleState)
+ {
+ result = I2C_MasterRunTransferStateMachine(base, handle, &isDone);
+
+ if ((result != kStatus_Success) || isDone)
+ {
+ /* Disable internal IRQ enables. */
+ I2C_DisableInterrupts(base, (uint16_t)kI2C_AllInterruptEnable);
+ /* Clear all status */
+ I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_MasterAllClearFlags);
+ /* Set handle to idle state. */
+ handle->state = (uint8_t)kMasterIdleState;
+ /* Handle error */
+ if (result != kStatus_Success)
+ {
+ /* Disable and re-enable the module to reset FIFO. */
+ I2C_Enable(base, false);
+ I2C_Enable(base, true);
+ }
+
+ /* Invoke callback. */
+ if (NULL != handle->completionCallback)
+ {
+ handle->completionCallback(base, handle, result, handle->userData);
+ }
+ }
+ }
+}
+
+static status_t I2C_MasterRunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone)
+{
+ status_t result = kStatus_Success;
+ uint32_t status;
+ uint8_t txFifoCount = I2C_GetTxFifoDataCount(base);
+ uint8_t txCount;
+ uint8_t rxCount = MIN(I2C_GetRxFifoDataCount(base), handle->receiveSize);
+ i2c_master_transfer_t *xfer = &handle->transfer;
+
+ /* Set default isDone return value. */
+ *isDone = false;
+
+ /* Check for errors. */
+ status = I2C_MasterGetStatusFlags(base);
+ /* For the last byte, nack flag is expected. Do not check and clear kI2C_MasterDataNackFlag for the last byte */
+ if ((handle->transmitSize == 0U) && (txFifoCount == 0U))
+ {
+ status &= ~(uint32_t)kI2C_MasterDataNackFlag;
+ }
+ result = I2C_MasterCheckAndClearError(base, status);
+ if (kStatus_Success != result)
+ {
+ return result;
+ }
+
+ /* Execute the state. */
+ switch (handle->state)
+ {
+ case (uint8_t)kMasterSendCommandState:
+ txCount = MIN((I2C_GetTxFifoDepth(base) - txFifoCount), xfer->subaddressSize);
+ while (txCount-- != 0U)
+ {
+ xfer->subaddressSize--;
+ I2C_WriteByte(base, (uint8_t)((xfer->subaddress >> (8U * xfer->subaddressSize)) & 0xffU));
+ }
+ if (xfer->subaddressSize == 0U)
+ {
+ if (0U != xfer->dataSize)
+ {
+ if (xfer->direction == kI2C_Read)
+ {
+ handle->state = (uint8_t)kMasterReceiveDataState;
+ /* Enable rx interrupt */
+ I2C_EnableInterrupts(base,
+ (uint16_t)(kI2C_RxOverflowInterruptFlag | kI2C_RxDataReadyInterruptFlag));
+ }
+ else
+ {
+ handle->state = (uint8_t)kMasterSendDataState;
+ }
+ }
+ else
+ {
+ /* No transfer, so move to stop state. */
+ handle->state = (uint8_t)kMasterWaitForCompletionState;
+ }
+ }
+ break;
+
+ case (uint8_t)kMasterSendDataState:
+ txCount = MIN((I2C_GetTxFifoDepth(base) - txFifoCount), handle->transmitSize);
+ while (txCount-- != 0U)
+ {
+ handle->transmitSize--;
+ I2C_WriteByte(base, *xfer->data++);
+ }
+ if (0U == handle->transmitSize)
+ {
+ handle->state = (uint8_t)kMasterWaitForCompletionState;
+ }
+ break;
+
+ case (uint8_t)kMasterReceiveDataState:
+ txCount = MIN((I2C_GetTxFifoDepth(base) - txFifoCount), handle->transmitSize);
+ while (rxCount-- != 0U)
+ {
+ handle->receiveSize--;
+ *(xfer->data)++ = I2C_ReadByte(base);
+ }
+ if (handle->receiveSize == 0U)
+ {
+ handle->state = (uint8_t)kMasterWaitForCompletionState;
+ }
+ while (txCount-- != 0U)
+ {
+ handle->transmitSize--;
+ I2C_MasterWriteDummy(base);
+ }
+ break;
+
+ case (uint8_t)kMasterWaitForCompletionState:
+ /* We stay in this state until the stop is detected. */
+ if (0U != (status & (uint32_t)kI2C_StopDetectInterruptFlag))
+ {
+ *isDone = true;
+ }
+ break;
+
+ default:
+ assert(false);
+ break;
+ }
+ return result;
+}
+
+/*!
+ * brief Initializes the I2C slave transfer in interrupt way.
+ *
+ * This function is responsible for initializig slave transfer handle, installing user callback, registering master
+ * IRQ handling function and opening global interrupt.
+ *
+ * param base I2C base pointer
+ * param handle pointer to i2c_slave_handle_t structure to store the transfer state
+ * param callback pointer to user callback function
+ * param userData User configurable pointer to any data, function, structure etc that user wish to use in the callback
+ */
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+ i2c_slave_handle_t *handle,
+ i2c_slave_transfer_callback_t callback,
+ void *userData)
+{
+ assert(NULL != handle);
+ /* Clear out the handle. */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ uint32_t instance;
+ /* Look up instance number */
+ instance = I2C_GetInstance(base);
+
+ /* Save callback and userData. */
+ handle->callback = callback;
+ handle->userData = userData;
+
+ /* Save the handle into static handle array */
+ s_i2cHandles[instance] = handle;
+ /* Save IRQ handler into static ISR function pointer. */
+ s_i2cSlaveIsr = I2C_SlaveTransferHandleIRQ;
+
+ /* Disable internal IRQs and enable global IRQ. */
+ I2C_DisableInterrupts(base, (uint16_t)kI2C_AllInterruptEnable);
+ (void)EnableIRQ(s_I2cIrqs[instance]);
+}
+
+/*!
+ * brief Sets I2C slave ready to process bus events.
+ *
+ * Call this API to let I2C start monitoring bus events driven by I2C master on bus. When user specified event occurs,
+ * callback will be invoked passes event information to the callback.
+ *
+ * note When #kI2C_SlaveOutofTransmitDataEvent and #kI2C_SlaveReceiveEvent occured, slave callback will
+ * always be revoked regardless which events user choose to enable. This means user need not configure them in the
+ * eventMask. If user wants to enable all the events, use #kI2C_SlaveAllEvents for convenience.
+ *
+ * param base The I2C peripheral base address.
+ * param handle Pointer to #i2c_slave_transfer_handle_t structure which stores the transfer state.
+ * param eventMask Bit mask formed by OR operation of event(s) in #i2c_slave_transfer_event_t enumerators. When these
+ * events occur the callback will be invoked.
+ * retval kStatus_I2C_Busy I2C slave has already been started on this handle.
+ */
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint8_t eventMask)
+{
+ assert(NULL != handle);
+
+ status_t result = kStatus_Success;
+ /* Return busy if slave is already in transaction, or the bus is occupied with other transfer. */
+ if ((handle->isBusy) || ((I2C_SlaveGetStatusFlags(base) & (uint32_t)kI2C_BusBusyInterruptFlag) != 0U))
+ {
+ return kStatus_I2C_Busy;
+ }
+
+ /* Enable module */
+ I2C_Enable(base, true);
+ /* Empty rx FIFO first */
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) != 0U)
+ {
+ (void)I2C_ReadByte(base);
+ }
+
+ /* Disable I2C IRQ sources while we configure stuff. */
+ I2C_DisableInterrupts(base, (uint16_t)kI2C_AllInterruptEnable);
+ /* Clear transfer in handle. */
+ (void)memset(&handle->transfer, 0, sizeof(handle->transfer));
+ /* Record that we're busy. */
+ handle->isBusy = true;
+ /* Set up event mask. tx and rx are always enabled. */
+ handle->eventMask = eventMask | (uint8_t)kI2C_SlaveTransmitEvent | (uint8_t)kI2C_SlaveReceiveEvent;
+ /* Disable slave nack the next byte */
+ I2C_SlaveNackNextByte(base, false);
+ /* Clear all flags. */
+ I2C_SlaveClearStatusFlags(base, (uint16_t)kI2C_SlaveAllClearFlags);
+ /* Enable I2C internal IRQ sources used in slave transfer. Global IRQ was enabled in I2C_SlaveTransferCreateHandle
+ */
+ I2C_EnableInterrupts(base, (uint16_t)kI2C_SlaveInterruptEnable);
+
+ return result;
+}
+
+/*!
+ * brief Gets how many bytes slave have transferred in curent data buffer.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_slave_transfer_handle_t structure.
+ * param count Number of bytes slave have transferred after the last start/repeated start.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_NoTransferInProgress Curent no transfer is in progress.
+ * retval kStatus_Success Successfully obtained the count.
+ */
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count)
+{
+ assert(NULL != handle);
+
+ if (NULL == count)
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* Catch when there is not an active transfer. */
+ if (false == handle->isBusy)
+ {
+ *count = 0U;
+ return kStatus_NoTransferInProgress;
+ }
+
+ /* For an active transfer, just return the count from the handle. */
+ *count = handle->transferredCount;
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the slave transfer.
+ *
+ * note This API can be called at any time to stop slave for handling further bus events.
+ *
+ * param base I2C base pointer.
+ * param handle pointer to i2c_slave_transfer_handle_t structure which stores the transfer state.
+ */
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ if (handle->isBusy)
+ {
+ /* Disable I2C IRQ sources. */
+ I2C_DisableInterrupts(base, (uint16_t)kI2C_AllInterruptEnable);
+ /* Set slave to nack data automatically */
+ I2C_SlaveNackNextByte(base, true);
+
+ /* Reset transfer info. */
+ (void)memset(&handle->transfer, 0, sizeof(handle->transfer));
+
+ /* We're no longer busy. */
+ handle->isBusy = false;
+ }
+}
+
+static void I2C_SlaveTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
+{
+ assert(NULL != i2cHandle);
+
+ i2c_slave_handle_t *handle = (i2c_slave_handle_t *)i2cHandle;
+ uint32_t statusFlags = I2C_SlaveGetStatusFlags(base);
+ i2c_slave_transfer_t *xfer = &(handle->transfer);
+ size_t tmpDataSize;
+ uint8_t rxFullSlots;
+
+ /* Check stop flag. */
+ if (0U != (statusFlags & (uint32_t)kI2C_StopDetectInterruptFlag))
+ {
+ /* Read IC_CLR_STOP_DET register to clear the stop detect interrupt flag */
+ (void)base->IC_CLR_STOP_DET;
+
+ /* Call slave callback if this is the STOP of the transfer. */
+ if (true == handle->isBusy)
+ {
+ xfer->event = kI2C_SlaveCompletionEvent;
+ xfer->completionStatus = kStatus_Success;
+ handle->isBusy = false;
+
+ if ((0U != (handle->eventMask & (uint8_t)xfer->event)) && (NULL != handle->callback))
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ }
+ }
+
+ /* Check start flag. */
+ if (0U != (statusFlags & (uint32_t)kI2C_StartDetectInterruptFlag))
+ {
+ /* Read IC_CLR_START_DET register to clear the start detect interrupt flag */
+ (void)base->IC_CLR_START_DET;
+ /* Disable slave nack the next byte */
+ I2C_SlaveNackNextByte(base, false);
+
+ handle->isBusy = true;
+ xfer->event = kI2C_SlaveStartDetectEvent;
+
+ if ((0U != (handle->eventMask & (uint8_t)xfer->event)) && (NULL != handle->callback))
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ }
+
+ /* Check general call ACK flag. */
+ if (0U != (statusFlags & (uint32_t)kI2C_SlaveGeneralCallAckInterruptFlag))
+ {
+ /* Read IC_CLR_GEN_CALL register to clear the general call ack interrupt flag */
+ (void)base->IC_CLR_GEN_CALL;
+ /* Disable slave nack the next byte */
+ I2C_SlaveNackNextByte(base, false);
+
+ handle->isBusy = true;
+ xfer->event = kI2C_SlaveGenaralcallEvent;
+
+ if ((0U != (handle->eventMask & (uint8_t)xfer->event)) && (NULL != handle->callback))
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ }
+
+ /* Check rx overflow flag. */
+ if (0U != (statusFlags & (uint32_t)kI2C_RxOverflowInterruptFlag))
+ {
+ /* Read IC_CLR_RX_OVER register to clear the rx FIFO overflow interrupt flag */
+ (void)base->IC_CLR_RX_OVER;
+ /* Set slave to nack the next byte to terminate the transfer */
+ I2C_SlaveNackNextByte(base, true);
+
+ xfer->event = kI2C_SlaveCompletionEvent;
+ xfer->completionStatus = kStatus_I2C_RxHardwareOverrun;
+ handle->isBusy = false;
+
+ if ((0U != (handle->eventMask & (uint8_t)xfer->event)) && (NULL != handle->callback))
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ }
+
+ /* Check NAK */
+ if (0U != (statusFlags & (uint32_t)kI2C_SlaveNackInterruptFlag))
+ {
+ /* Read IC_CLR_RX_DONE register to clear the slave nack interrupt flag */
+ (void)base->IC_CLR_RX_DONE;
+
+ if (handle->transfer.dataSize != 0U)
+ {
+ xfer->completionStatus = kStatus_I2C_Nak;
+ }
+ else
+ {
+ xfer->completionStatus = kStatus_Success;
+ }
+ xfer->event = kI2C_SlaveCompletionEvent;
+ handle->isBusy = false;
+ if ((0U != (handle->eventMask & (uint8_t)xfer->event)) && (NULL != handle->callback))
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ }
+
+ /* Check arbitration, though slave does not really own the bus, there is still such incident as the data on SDA line
+ is not the same as slave sends, in such case we call slave loses arbitration */
+ if (0U != (statusFlags & (uint32_t)kI2C_SlaveArbitrationLostFlag))
+ {
+ /* Read IC_CLR_TX_ABRT register to clear the tx abort interrupt flag */
+ (void)base->IC_CLR_TX_ABRT;
+
+ xfer->event = kI2C_SlaveCompletionEvent;
+ xfer->completionStatus = kStatus_I2C_ArbitrationLost;
+ handle->isBusy = false;
+ if ((0U != (handle->eventMask & (uint8_t)xfer->event)) && (NULL != handle->callback))
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ }
+
+ /* Receive data */
+ if (0U != (statusFlags & (uint32_t)kI2C_RxDataReadyInterruptFlag))
+ {
+ tmpDataSize = xfer->dataSize;
+ /* If we're out of data, invoke callback to get more. */
+ if ((NULL == xfer->data) || (0U == tmpDataSize))
+ {
+ xfer->event = kI2C_SlaveReceiveEvent;
+ if (NULL != handle->callback)
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ /* Clear the transferred count now that we have a new buffer. */
+ handle->transferredCount = 0U;
+ }
+
+ rxFullSlots = I2C_GetRxFifoDataCount(base);
+ while ((rxFullSlots != 0U) && (0U != xfer->dataSize))
+ {
+ /* Receive data. */
+ *handle->transfer.data++ = I2C_ReadByte(base);
+ handle->transferredCount++;
+ xfer->dataSize--;
+ rxFullSlots--;
+ if (0U == xfer->dataSize)
+ {
+ xfer->event = kI2C_SlaveCompletionEvent;
+ xfer->completionStatus = kStatus_Success;
+ handle->isBusy = false;
+
+ /* Proceed receive complete event. */
+ if (((handle->eventMask & (uint8_t)xfer->event) != 0U) && (handle->callback != NULL))
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ }
+ }
+ }
+
+ /* Master request data */
+ if (0U != (statusFlags & (uint32_t)kI2C_SlaveReadRequestInterruptFlag))
+ {
+ /* Read IC_CLR_RD_REQ register to clear the read request interrupt flag */
+ (void)base->IC_CLR_RD_REQ;
+
+ tmpDataSize = xfer->dataSize;
+ /* If we're out of data, invoke callback to get more. */
+ if ((NULL == xfer->data) || (0U == tmpDataSize))
+ {
+ xfer->event = kI2C_SlaveTransmitEvent;
+ if (NULL != handle->callback)
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ /* Clear the transferred count now that we have a new buffer. */
+ handle->transferredCount = 0U;
+ }
+
+ if (0U != (handle->transfer.dataSize))
+ {
+ /* Send data. */
+ I2C_WriteByte(base, *handle->transfer.data++);
+ handle->transfer.dataSize--;
+ handle->transferredCount++;
+ }
+ else
+ {
+ xfer->event = kI2C_SlaveCompletionEvent;
+ xfer->completionStatus = kStatus_Success;
+ handle->isBusy = false;
+
+ /* Proceed txdone event. */
+ if (((handle->eventMask & (uint8_t)xfer->event) != 0U) && (handle->callback != NULL))
+ {
+ handle->callback(base, xfer, handle->userData);
+ }
+ }
+ }
+}
+
+static void I2C_CommonIRQHandler(I2C_Type *base, uint32_t instance)
+{
+ /* Check for master function. */
+ if (I2C_IsMaster(base))
+ {
+ /* Master mode. */
+ s_i2cMasterIsr(base, s_i2cHandles[instance]);
+ }
+
+ /* Check for slave function. */
+ if (I2C_IsSlave(base))
+ {
+ /* Slave mode. */
+ s_i2cSlaveIsr(base, s_i2cHandles[instance]);
+ }
+ SDK_ISR_EXIT_BARRIER;
+}
+
+#if defined(I2C0)
+void I2C0_DriverIRQHandler(void);
+/* Implementation of I2C0 handler named in startup code. */
+void I2C0_DriverIRQHandler(void)
+{
+ I2C_CommonIRQHandler(I2C0, 0U);
+}
+#endif
+
+#if defined(I2C1)
+void I2C1_DriverIRQHandler(void);
+/* Implementation of I2C1 handler named in startup code. */
+void I2C1_DriverIRQHandler(void)
+{
+ I2C_CommonIRQHandler(I2C1, 1U);
+}
+#endif
diff --git a/drivers/mw320/i2c/fsl_i2c.h b/drivers/mw320/i2c/fsl_i2c.h
new file mode 100644
index 000000000..3beecd8cd
--- /dev/null
+++ b/drivers/mw320/i2c/fsl_i2c.h
@@ -0,0 +1,1396 @@
+/*
+ * Copyright 2020,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_I2C_H_
+#define _FSL_I2C_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup i2c_driver
+ * @ingroup i2c
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief Retry times when checking status flags. */
+#ifndef I2C_RETRY_TIMES
+#define I2C_RETRY_TIMES 0U /* Default defines to zero, driver keeps checking status flag untill it changes. */
+#endif
+
+/*!
+ * @brief I2C API status codes, used by bus operation APIs and transactional APIs as return value to indicate the bus's
+ * current status as the API's execution result, or used in the callback to indicate transfer results.
+ */
+enum
+{
+ kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_I2C, 0), /*!< I2C bus is busy. */
+ kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_I2C, 1), /*!< I2C Bus is idle. */
+ kStatus_I2C_Nak = MAKE_STATUS(kStatusGroup_I2C, 2), /*!< I2C detected NACK on bus. When in SMBus mode, this means
+ the receiver nacks transmitter before PEC byte. */
+ kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_I2C, 3), /*!< I2C lost arbitration during addressing. */
+ kStatus_I2C_Timeout =
+ MAKE_STATUS(kStatusGroup_I2C, 4), /*!< Timeout happens when waiting for status flags to change. */
+ kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_I2C, 5), /*!< NACK was detected during the address probe. */
+ kStatus_I2C_GeneralCall_Nak =
+ MAKE_STATUS(kStatusGroup_I2C, 6), /*!< NACK was detected after issuing general call. */
+ kStatus_I2C_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_I2C, 7), /*!< I2C rx receiver overrun. */
+ kStatus_I2C_TxFifoFlushed = MAKE_STATUS(kStatusGroup_I2C, 8), /*!< I2C tx FIFO is flushed by hardware. */
+};
+
+/*!
+ * @brief I2C common hardware status flags
+ *
+ * These enumerations can be ORed together to form bit masks. The masks can be used together with masks in
+ * #_i2c_master_status_flags as parameter by @ref I2C_MasterClearStatusFlags or as return value by
+ * @ref I2C_MasterGetStatusFlags. Or together with masks in #_i2c_slave_status_flags as parameter by
+ * @ref I2C_SlaveClearStatusFlags or as return value by @ref I2C_SlaveGetStatusFlags
+ */
+enum _i2c_status_flags
+{
+ kI2C_RxUnderflowInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_RX_UNDER_MASK, /*!< Sets when software tries to read from empty rx FIFO. bit 0 */
+ kI2C_RxOverflowInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_RX_OVER_MASK, /*!< Sets when new data received and the rx FIFO is already full. bit 1 */
+ kI2C_RxDataReadyInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_RX_FULL_MASK, /*!< Sets when data in rx FIFO reaches or is above rx watermark. bit 2 */
+ kI2C_TxOverflowInterruptFlag = I2C_IC_RAW_INTR_STAT_TX_OVER_MASK, /*!< Sets when software tries to push data to tx
+ FIFO and it's already full. bit 3 */
+ kI2C_TxRequestInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_TX_EMPTY_MASK, /*!< Sets when data in tx FIFO is at or below tx FIFO watermark. bit 4 */
+ kI2C_TxAbortInterruptFlag = I2C_IC_RAW_INTR_STAT_TX_ABRT_MASK, /*!< Sets when any of the below status from
+ kI2C_Master7bitAddressNackFlag to kI2C_MasterArbitrationLostFlag is set, results in the tx FIFO being flushed.
+ Clear this flag will also clear these status flags automatically. bit 6 */
+ kI2C_BusBusyInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_ACTIVITY_MASK, /*!< Sets when there is I2C activity on bus. bit 8 */
+ kI2C_StopDetectInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_STOP_DET_MASK, /*!< Sets when stop condition is detected. bit 9 */
+ kI2C_StartDetectInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_START_DET_MASK, /*!< Sets when start condition is detected. bit 10 */
+ kI2C_ActiveFlag = I2C_IC_STATUS_ACTIVITY_MASK
+ << 25U, /*!< Sets when I2C module is in active transfer state. bit 25 */
+ kI2C_TxFifoNotFullFlag = I2C_IC_STATUS_TFNF_MASK << 25U, /*!< Sets when I2C tx FIFO is not full. bit 26 */
+ kI2C_TxFifoEmptyFlag = I2C_IC_STATUS_TFE_MASK << 25U, /*!< Sets when I2C txFIFO is completely empty. bit 27 */
+ kI2C_RxFifoNotEmptyFlag = I2C_IC_STATUS_RFNE_MASK << 25U, /*!< Sets when I2C rx FIFO is not empty. bit 28 */
+ kI2C_RxFifoFullFlag = I2C_IC_STATUS_RFF_MASK << 25U, /*!< Sets when I2C rx FIFO is completely full. bit 29 */
+};
+
+/*!
+ * @brief I2C master hardware status flags
+ *
+ * These enumerations can be ORed together to form bit masks. The masks can be used as parameter by
+ * @ref I2C_MasterClearStatusFlags or as return value by @ref I2C_MasterGetStatusFlags.
+ */
+enum _i2c_master_status_flags
+{
+ /* These flags are cleared when kI2C_TxAbortInterruptFlag is cleared */
+ kI2C_Master7bitAddressNackFlag = I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MASK
+ << 12U, /*!< Sets when I2C master is nacked in 7-bit addressing. bit 12 */
+ kI2C_Master10bitAddressNack1Flag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MASK
+ << 12U, /*!< Sets when I2C master is nacked of first byte of address in 10-bit addressing. bit 13 */
+ kI2C_Master10bitAddressNack2Flag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MASK
+ << 12U, /*!< Sets when I2C master is nacked of second byte of address in 10-bit addressing. bit 14 */
+ kI2C_MasterDataNackFlag = I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MASK
+ << 12U, /*!< Sets when I2C master is nacked in data sending. bit 15 */
+ kI2C_MasterGeneralCallNackFlag = I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MASK
+ << 12U, /*!< Sets when I2C master is nacked after issueing general call. bit 16 */
+ kI2C_MasterGeneralCallReadFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MASK
+ << 12U, /*!< Sets when I2C master uses read command after issueing general call. bit 17 */
+ kI2C_MasterHighSpeedCodeAckFlag = I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MASK
+ << 12U, /*!< Sets when I2C master is in high speed mode and the high speed master
+ code was acknowledged. bit 18 */
+ kI2C_MasterStartByteAckFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MASK
+ << 12U, /*!< Sets when I2C master has sent a START byte and the START byte was acknowledged. bit 19 */
+ kI2C_MasterHighSpeedRestartDisabledFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MASK
+ << 12U, /*!< Sets when I2C master tries to transfer data in high speed mode with restart disabled. bit 20 */
+ kI2C_MasterStartWithRestartDisabledFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MASK
+ << 12U, /*!< Sets when master tries to send a start with restart disabled. bit 21 */
+ kI2C_Master10bitAddressReadRestartDisabledFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MASK
+ << 12U, /*!< Sets when I2C master issues read command in 10-bit addessing with restart disabled. bit 22 */
+ kI2C_MasterOperateWhenDisabledFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MASK
+ << 12U, /*!< Sets when software wants to initiate a master operation with master mode disabled. bit 23 */
+ kI2C_MasterArbitrationLostFlag =
+ I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MASK
+ << 12U, /*!< Sets when master loses arbitration or kI2C_SlaveArbitrationLostFlag is set. bit 24 */
+
+ kI2C_MasterActiveFlag = I2C_IC_STATUS_MST_ACTIVITY_MASK
+ << 25U, /*!< Sets when I2C master operation is active. bit 30 */
+
+ /*! These flags are cleared automatically according to module status, or when other status bit is cleared.
+ eg. once tx FIFO is not empty kI2C_TxFifoEmptyFlag is cleared automatically.
+ eg. status bits from kI2C_Master7bitAddressNackFlag to kI2C_MasterArbitrationLostFlag are cleared when
+ kI2C_TxAbortInterruptFlag is cleared. */
+ kI2C_MasterAutoClearFlags =
+ kI2C_RxDataReadyInterruptFlag | kI2C_TxRequestInterruptFlag | kI2C_ActiveFlag | kI2C_TxFifoNotFullFlag |
+ kI2C_TxFifoEmptyFlag | kI2C_RxFifoNotEmptyFlag | kI2C_RxFifoFullFlag | kI2C_MasterActiveFlag |
+ kI2C_Master7bitAddressNackFlag | kI2C_Master10bitAddressNack1Flag | kI2C_Master10bitAddressNack2Flag |
+ kI2C_MasterDataNackFlag | kI2C_MasterGeneralCallNackFlag | kI2C_MasterGeneralCallReadFlag |
+ kI2C_MasterHighSpeedCodeAckFlag | kI2C_MasterStartByteAckFlag | kI2C_MasterHighSpeedRestartDisabledFlag |
+ kI2C_MasterStartWithRestartDisabledFlag | kI2C_Master10bitAddressReadRestartDisabledFlag |
+ kI2C_MasterOperateWhenDisabledFlag | kI2C_MasterArbitrationLostFlag,
+
+ /*! All flags which are clearable. */
+ kI2C_MasterAllClearFlags = kI2C_RxUnderflowInterruptFlag | kI2C_RxOverflowInterruptFlag |
+ kI2C_TxOverflowInterruptFlag | kI2C_TxAbortInterruptFlag | kI2C_BusBusyInterruptFlag |
+ kI2C_StopDetectInterruptFlag | kI2C_StartDetectInterruptFlag,
+
+ /* All error flags */
+ kI2C_MasterErrorFlags = kI2C_RxUnderflowInterruptFlag | kI2C_RxOverflowInterruptFlag |
+ kI2C_TxOverflowInterruptFlag | kI2C_TxAbortInterruptFlag | kI2C_Master7bitAddressNackFlag |
+ kI2C_Master10bitAddressNack1Flag | kI2C_Master10bitAddressNack2Flag |
+ kI2C_MasterDataNackFlag | kI2C_MasterGeneralCallNackFlag | kI2C_MasterGeneralCallReadFlag |
+ kI2C_MasterHighSpeedRestartDisabledFlag | kI2C_MasterStartWithRestartDisabledFlag |
+ kI2C_Master10bitAddressReadRestartDisabledFlag | kI2C_MasterOperateWhenDisabledFlag |
+ kI2C_MasterArbitrationLostFlag,
+};
+
+/*!
+ * @brief I2C slave hardware status flags
+ *
+ * These enumerations can be ORed together to form bit masks. The masks can be used as parameter by
+ * @ref I2C_SlaveClearStatusFlags, or as return value by @ref I2C_SlaveGetStatusFlags.
+ */
+enum _i2c_slave_status_flags
+{
+ kI2C_SlaveReadRequestInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_RD_REQ_MASK, /*!< Sets when I2C as slave and master tries to read data from it. bit 5 */
+ kI2C_SlaveNackInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_RX_DONE_MASK, /*!< Sets when I2C as slave transmiter and was nacked by master, indicating
+ tx complete. bit 7 */
+ kI2C_SlaveGeneralCallAckInterruptFlag =
+ I2C_IC_RAW_INTR_STAT_GEN_CALL_MASK, /*!< Sets when general call address is received and acknowledged. bit 11 */
+
+ kI2C_SlaveFlushTxFifoFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MASK, /*!< Sets when I2C slave receives a read command but there are
+ still old data remaining in tx FIFO. Cleared when
+ kI2C_TxAbortInterruptFlag is cleared. bit 13 */
+ kI2C_SlaveArbitrationLostFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MASK, /*!< Sets when data on bus is not the same as slave sends. Cleared
+ when kI2C_TxAbortInterruptFlag is cleared. bit 14 */
+ kI2C_SlaveReadWhenRequestedDataFlag =
+ I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MASK, /*!< Sets when I2C slave is request data from master but use read
+ command. Cleared when kI2C_TxAbortInterruptFlag is cleared. bit
+ 15 */
+ kI2C_SlaveDisabledWhileBusy = I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MASK << 16U, /*!< Sets when I2C slave is
+ busy while disabled. If slave is addressed when disabled, slave will nack the master even address matched, if slave
+ is receiveing slave will nack the transfer immediately. Cleared when module is re-eanbled. bit 16 */
+ kI2C_SlaveRxDataLost = I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MASK
+ << 16U, /*!< Sets when I2C slave is actively
+receiving data when disabled, and at least one byte have been received. Cleared when module is re-eanbled. bit 17 */
+
+ kI2C_SlaveActiveFlag = I2C_IC_STATUS_SLV_ACTIVITY_MASK
+ << 25U, /*!< Sets when I2C slave operation is active. bit 31 */
+
+ /*! These flags are cleared automatically according to module status, or when other status bit is cleared.
+ eg. once tx FIFO is not empty kI2C_TxFifoEmptyFlag is cleared automatically.
+ eg. kI2C_SlaveFlushTxFifoFlag, kI2C_SlaveArbitrationLostFlag and kI2C_SlaveReadWhenRequestedDataFlag are cleared
+ when kI2C_TxAbortInterruptFlag is cleared. */
+ kI2C_SlaveAutoClearFlags = kI2C_RxDataReadyInterruptFlag | kI2C_TxRequestInterruptFlag | kI2C_SlaveFlushTxFifoFlag |
+ kI2C_SlaveArbitrationLostFlag | kI2C_SlaveReadWhenRequestedDataFlag | kI2C_ActiveFlag |
+ kI2C_TxFifoNotFullFlag | kI2C_TxFifoEmptyFlag | kI2C_RxFifoNotEmptyFlag |
+ kI2C_RxFifoFullFlag | kI2C_SlaveActiveFlag | kI2C_SlaveDisabledWhileBusy |
+ kI2C_SlaveRxDataLost,
+
+ /*! All flags which are clearable. */
+ kI2C_SlaveAllClearFlags = kI2C_RxUnderflowInterruptFlag | kI2C_RxOverflowInterruptFlag |
+ kI2C_TxOverflowInterruptFlag | kI2C_SlaveReadRequestInterruptFlag |
+ kI2C_TxAbortInterruptFlag | kI2C_SlaveNackInterruptFlag | kI2C_BusBusyInterruptFlag |
+ kI2C_StopDetectInterruptFlag | kI2C_StartDetectInterruptFlag |
+ kI2C_SlaveGeneralCallAckInterruptFlag,
+
+ /* All error flags */
+ kI2C_SlaveErrorFlags = kI2C_RxUnderflowInterruptFlag | kI2C_RxOverflowInterruptFlag | kI2C_TxOverflowInterruptFlag |
+ kI2C_TxAbortInterruptFlag | kI2C_SlaveNackInterruptFlag | kI2C_SlaveFlushTxFifoFlag |
+ kI2C_SlaveArbitrationLostFlag | kI2C_SlaveReadWhenRequestedDataFlag |
+ kI2C_SlaveDisabledWhileBusy | kI2C_SlaveRxDataLost,
+};
+
+/*!
+ * @brief I2C interrupt enable/disable source.
+ *
+ * These enumerations can be ORed together to form bit masks. The masks can be used as parameter by
+ * @ref I2C_EnableInterrupts, @ref I2C_DisableInterrupts, or as return value by @ref I2C_GetEnabledInterrupts.
+ */
+enum _i2c_interrupt_enable
+{
+ /* Common */
+ kI2C_RxUnderflowInterruptEnable = I2C_IC_INTR_MASK_M_RX_UNDER_MASK, /*!< Rx FIFO underflow interrupt. bit 0 */
+ kI2C_RxOverflowInterruptEnable = I2C_IC_INTR_MASK_M_RX_OVER_MASK, /*!< Rx FIFO overflow interrupt. bit 1 */
+ kI2C_RxDataReadyInterruptEnable = I2C_IC_INTR_MASK_M_RX_FULL_MASK, /*!< Rx data ready interrupt. bit 2 */
+ kI2C_TxOverflowInterruptEnable = I2C_IC_INTR_MASK_M_TX_OVER_MASK, /*!< Tx FIFO overflow interrupt. bit 3 */
+ kI2C_TxRequestInterruptEnable = I2C_IC_INTR_MASK_M_TX_EMPTY_MASK, /*!< Tx data request interrupt. bit 4 */
+ kI2C_SlaveReadRequestInterruptEnable =
+ I2C_IC_INTR_MASK_M_RD_REQ_MASK, /*!< I2C slave requested data by master interrupt. bit 5 */
+ kI2C_TxAbortInterruptEnable = I2C_IC_INTR_MASK_M_TX_ABRT_MASK, /*!< Tx abort interrupt. bit 6 */
+ kI2C_SlaveNackInterruptEnable = I2C_IC_INTR_MASK_M_RX_DONE_MASK, /*!< I2C slave nack interrupt. bit 7 */
+ kI2C_BusBusyInterruptEnable = I2C_IC_INTR_MASK_M_ACTIVITY_MASK, /*!< I2C bus busy interrupt. bit 8 */
+ kI2C_StopDetectInterruptEnable =
+ I2C_IC_INTR_MASK_M_STOP_DET_MASK, /*!< I2C stop condition detect interrupt. bit 9 */
+ kI2C_StartDetectInterruptEnable =
+ I2C_IC_INTR_MASK_M_START_DET_MASK, /*!< I2C start condition detect interrupt. bit 10 */
+ kI2C_SlaveGeneralCallAckInterruptEnable =
+ I2C_IC_INTR_MASK_M_GEN_CALL_MASK, /*!< I2C ganaral call detect and acknowledge interrupt. bit 11 */
+
+ kI2C_SlaveInterruptEnable = kI2C_RxOverflowInterruptEnable | kI2C_RxDataReadyInterruptEnable |
+ kI2C_SlaveReadRequestInterruptEnable | kI2C_TxAbortInterruptEnable |
+ kI2C_SlaveNackInterruptEnable | kI2C_StopDetectInterruptEnable |
+ kI2C_StartDetectInterruptEnable | kI2C_SlaveGeneralCallAckInterruptEnable,
+
+ kI2C_AllInterruptEnable =
+ kI2C_RxUnderflowInterruptEnable | kI2C_RxOverflowInterruptEnable | kI2C_RxDataReadyInterruptEnable |
+ kI2C_TxOverflowInterruptEnable | kI2C_TxRequestInterruptEnable | kI2C_TxAbortInterruptEnable |
+ kI2C_BusBusyInterruptEnable | kI2C_StopDetectInterruptEnable | kI2C_StartDetectInterruptEnable |
+ kI2C_SlaveReadRequestInterruptEnable | kI2C_SlaveNackInterruptEnable | kI2C_SlaveGeneralCallAckInterruptEnable,
+};
+
+/*! @brief Master speed mode. */
+typedef enum _i2c_master_speed_mode
+{
+ kI2C_MasterSpeedStandard = 0x1U, /*!< Standard mode, 100kbps. */
+ kI2C_MasterSpeedFast = 0X2U, /*!< Fast mode, 400kbps. */
+ kI2C_MasterSpeedHigh = 0X3U, /*!< High speed mode, 3.4Mbps. */
+} i2c_master_speed_mode_t;
+
+/*! @brief Addressing mode, normal 7-bit address or 10-bit address. */
+typedef enum _i2c_address_mode
+{
+ kI2C_AddressMatch7bit = 0x0U, /*!< 7-bit addressing mode. */
+ kI2C_AddressMatch10bit = 0X1U, /*!< 10-bit addressing mode. */
+} i2c_address_mode_t;
+
+/*! @brief I2C DMA configuration for Transmit and Receive.*/
+enum _i2c_dma_enable_flags
+{
+ kQSPI_DmaRx = 0x1U, /*!< Receive DMA Enable Flag. */
+ kQSPI_DmaTx = 0x2U, /*!< Transmit DMA Enable Flag. */
+};
+
+/*!
+ * @brief I2C master configuration structure.
+ *
+ * This structure includes all the master operation needed features, user can configure these features one by one
+ * manually, or call @ref I2C_MasterGetDefaultConfig to set the structure to default value. Then, call
+ * @ref I2C_MasterInit to initialize I2C module. After initialization, the I2C module can only operate as master. To
+ * deinitialize I2C, call @ref I2C_MasterDeinit.
+ */
+typedef struct _i2c_master_config
+{
+ bool enable; /*!< Enable the I2C peripheral as master during initialization. I2C_IC_CON[IC_SLAVE_DISABLE],
+ I2C_IC_CON[master_mode], I2C_IC_ENABLE[ENABLE] */
+ i2c_master_speed_mode_t speed; /*!< The speed I2C master operates. I2C_IC_CON[SPEED] */
+ i2c_address_mode_t addressingMode; /*!< Addressing mode. I2C_IC_TAR[IC_10BITADDR_MASTER] */
+ uint8_t highSpeedMasterCodeAddress; /*!< Master code address in high speed mode, only 0-7 is avaliable.
+ I2C_IC_HS_MADDR[IC_HS_MAR] */
+ uint8_t rxFifoWaterMark; /*!< Rx FIFO watermark that controls the rx interrupt trigger level. I2C_IC_RX_TL[RX_TL] */
+ uint8_t txFifoWaterMark; /*!< Tx FIFO watermark that controls the tx interrupt trigger level. I2C_IC_TX_TL[TX_TL] */
+ uint16_t dataHoldTime; /*!< The number of clock source cycles of the data hold time tHD:DAT.
+ I2C_IC_SDA_HOLD[IC_SDA_HOLD] */
+ uint16_t dataSetupTime; /*!< The number of clock source cycles of the data setup time tSU:DAT.
+ I2C_IC_SDA_SETUP[SDA_SETUP] */
+ uint8_t glitchFilter; /*!< The number of clock source cycles of the longest glitch to be filtered in standard and
+ fast mode. I2C_IC_FS_SPKLEN[IC_FS_SPKLEN] */
+ uint8_t glitchFilterHighSpeed; /*!< The number of clock source cycles of the longest glitch to be filtered in high
+ speed mode. I2C_IC_HS_SPKLEN[IC_HS_SPKLEN] */
+} i2c_master_config_t;
+
+/*!
+ * @brief I2C slave configuration structure.
+ *
+ * This structure includes all the slave operation needed features, user can configure these features one by one
+ * manually, or call @ref I2C_SlaveGetDefaultConfig to set the structure to default value. Then, call
+ * @ref I2C_SlaveInit to initialize I2C module. After initialization, the I2C module can only operate as slave. To
+ * deinitialize I2C, call @ref I2C_SlaveDeinit.
+ */
+typedef struct _i2c_slave_config
+{
+ bool enable; /*!< Enable the I2C peripheral as slave during initialization. I2C_IC_CON[IC_SLAVE_DISABLE],
+ I2C_IC_CON[master_mode], I2C_IC_ENABLE[ENABLE] */
+ i2c_address_mode_t addressingMode; /*!< Addressing mode. I2C_IC_CON[IC_10BITADDR_SLAVE] */
+ uint16_t slaveAddress; /*!< Slave address. I2C_IC_SAR[IC_SAR] */
+ uint8_t rxFifoWaterMark; /*!< Rx FIFO watermark that controls the rx interrupt trigger level. I2C_IC_RX_TL[RX_TL] */
+ uint8_t txFifoWaterMark; /*!< Tx FIFO watermark that controls the tx interrupt trigger level. I2C_IC_TX_TL[TX_TL] */
+ uint16_t dataHoldTime; /*!< The number of clock source cycles of the data hold time tHD:DAT.
+ I2C_IC_SDA_HOLD[IC_SDA_HOLD] */
+ uint16_t dataSetupTime; /*!< The number of clock source cycles of the data setup time tSU:DAT.
+ I2C_IC_SDA_SETUP[SDA_SETUP] */
+ bool ackGeneralCall; /*!< True to let slave response general call with Ack. I2C_IC_ACK_GENERAL_CALL[ACK_GEN_CALL] */
+ uint8_t glitchFilter; /*!< The number of clock source cycles of the longest glitch to be filtered in standard and
+ fast mode. I2C_IC_FS_SPKLEN[IC_FS_SPKLEN] */
+ uint8_t glitchFilterHighSpeed; /*!< The number of clock source cycles of the longest glitch to be filtered in high
+ speed mode. I2C_IC_HS_SPKLEN[IC_HS_SPKLEN] */
+} i2c_slave_config_t;
+
+/*! @brief Master transfer direction. */
+typedef enum _i2c_direction
+{
+ kI2C_Write = 0U, /*!< Master transmit. */
+ kI2C_Read = 1U /*!< Master receive. */
+} i2c_direction_t;
+
+/*!
+ * @brief I2C master transfer configuration structure.
+ *
+ * This structure definition includes all the user configurable features, that are used to control single I2C transfer
+ * of master mode, in polling way or in interrupt way.
+ */
+typedef struct _i2c_master_transfer
+{
+ uint16_t slaveAddress; /*!< 7-bit slave address, set to 0 to issue general call. */
+ i2c_direction_t direction; /*!< Transfer direction, #kI2C_Write or #kI2C_Read. */
+ uint32_t subaddress; /*!< Pointer to command code. */
+ size_t subaddressSize; /*!< Size of the command code, max value 4. */
+ uint8_t *volatile data; /*!< Pointer to the send/receive data buffer. */
+ volatile size_t dataSize; /*!< Transfer size. */
+} i2c_master_transfer_t;
+
+/*! @brief Forward declaration of the I2C master transfer handle structure. */
+typedef struct _i2c_master_handle i2c_master_handle_t;
+
+/*!
+ * @brief I2C master transfer callback function definition
+ *
+ * Defines the interface of user callback function used in master interrupt transfer. The callback function shall be
+ * defined and declared in application level by user. Before starting master transfer by calling
+ * @ref I2C_MasterTransferNonBlocking, call @ref I2C_MasterTransferCreateHandle to install the user callback. When
+ * master transfer ends successfully or failed due to any event like arbitration lost or nacked by slave, user callback
+ * will be invoked by driver. And then user can decide what to do next in the callback according to its third parameter
+ * completionStatus that indicates how the transfer ends.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle I2C transfer handle, which contains the information of base pointer, completionStatus and user data.
+ * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed.
+ * @param userData Pointer to user configurable structure.
+ */
+typedef void (*i2c_master_transfer_callback_t)(I2C_Type *base,
+ i2c_master_handle_t *handle,
+ status_t completionStatus,
+ void *userData);
+/*!
+ * @brief I2C master transfer handle
+ *
+ * @note If user wants to use the transactional API to transfer data in interrupt way in master mode, one I2C instance
+ * should and can only be allocated one master handle.
+ * @note The handle is maintained by I2C driver internally, which means the transfer state is retained and user shall
+ * not modify its state #state in application level. If user only wish to use transactional APIs without understanding
+ * its machanism, it is not necessary to understand these members.
+ */
+struct _i2c_master_handle
+{
+ uint8_t state; /*!< A transfer state maintained during transfer. */
+ i2c_master_transfer_t transfer; /*!< I2C master transfer structure. */
+ size_t transmitSize; /*!< Total bytes to be transferred. */
+ size_t receiveSize; /*!< Total bytes to be received. */
+ i2c_master_transfer_callback_t completionCallback; /*!< Callback function invoked when the transfer is finished. */
+ void *userData; /*!< User configurable pointer to any data, function, structure etc that user wish to use in the
+ callback */
+};
+
+/*!
+ * @brief Set of slave transfer events.
+ *
+ * This enumeration lists all the protocol level events that may happen during slave transfer. They can be used for two
+ * related purposes:
+ * 1. User can select certain events and combined them by OR operation to form a mask, and use the mask to configure
+ * slave transfer configuration stucture i2c_slave_transfer_t::u8EventMask. If any of these selected events happens,
+ * driver will alert user by invoking callback.
+ * 2. When slave callback is invoked, user has to know which specific event occured. Callback uses slave transfer
+ * configuration structure i2c_slave_transfer_t as 2nd parameter, its member i2c_slave_transfer_t::eEvent shows which
+ * event just happened.
+ */
+typedef enum _i2c_slave_transfer_event
+{
+ kI2C_SlaveStartDetectEvent = 0x01U, /*!< A start/repeated start was detected. */
+ kI2C_SlaveGenaralcallEvent = 0x02U, /*!< Received the general call address after a start or repeated start. */
+ kI2C_SlaveTransmitEvent = 0x04U, /*!< Slave runs out of data to transmit, request a new data buffer. */
+ kI2C_SlaveReceiveEvent = 0x08U, /*!< Slave runs out of space to store received data, request a new data buffer. */
+ kI2C_SlaveCompletionEvent =
+ 0x10U, /*!< Slave detects a stop signal, or slave is nacked by master during master-receive,
+ or slave has finished transmit/receive previously configured amount of data. */
+ /*! A bit mask of all available events. */
+ kI2C_SlaveAllEvents = kI2C_SlaveStartDetectEvent | kI2C_SlaveGenaralcallEvent | kI2C_SlaveTransmitEvent |
+ kI2C_SlaveReceiveEvent | kI2C_SlaveCompletionEvent,
+} i2c_slave_transfer_event_t;
+
+/*!
+ * @brief I2C slave transfer configuration structure.
+ *
+ * Covers slave transfer data buffer pointer, data size and the events user want driver to alert.
+ * @note Unlike master who controls the transfer flow, slave has to monitor any bus event and change its configuration
+ * accordingly. So this slave transfer configuration structure is also used as second parameter of callback, for user
+ * to change the transfer configuration in the callback. The read-only member eEvent shows which event occured that
+ * causes the callback being invoked.
+ */
+typedef struct _i2c_slave_transfer
+{
+ uint8_t *volatile data; /*!< Pointer to the buffer of data to send, or to store received data. */
+ volatile uint16_t dataSize; /*!< Transfer size. */
+ i2c_slave_transfer_event_t event; /*!< The event that caused the callback being invoked. Read-only. */
+ status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for
+ #kI2C_SlaveCompletionEvent. */
+} i2c_slave_transfer_t;
+/*!
+ * @brief I2C slave transfer callback function definition
+ *
+ * Defines the interface of slave user callback function. The callback function shall be defined and declared in
+ * application level by user. Before calling @ref I2C_SlaveTransferNonBlocking to let I2C slave ready to process bus
+ * events, call @ref I2C_SlaveTransferCreateHandle first to install the user callback to slave handle. When I2C slave
+ * meets user selected events, callback will be invoked and user can decide the following steps in the callback.
+ * All the events that can trigger callback are listed in #i2c_slave_transfer_event_t.
+ *
+ * @param base Base address for the I2C instance on which the event occurred.
+ * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback.
+ * @param userData Pointer to user configurable structure.
+ */
+typedef void (*i2c_slave_transfer_callback_t)(I2C_Type *base, i2c_slave_transfer_t *transfer, void *userData);
+
+/*!
+ * @brief I2C slave transfer handle
+ *
+ * @note If user wants to use the transactional API to transfer data in slave mode, one I2C instance should and can only
+ * be allocated one handle.
+ * @note The handle is maintained by I2C driver internally, which means the transfer state is retained and user shall
+ * not modify its state #isBusy in application level. If user only wish to use transactional APIs without understanding
+ * its machanism, it is not necessary to understand these members.
+ */
+typedef struct _i2c_slave_handle
+{
+ i2c_slave_transfer_t transfer; /*!< I2C slave transfer structure. */
+ size_t transferredCount; /*!< The number of bytes actually transferred for curent data buffer. */
+ bool isBusy; /*!< Whether transfer is busy. */
+ uint8_t eventMask; /*!< Mask of the events. When these enents occur during transfer driver will alert user using
+ callback. */
+ i2c_slave_transfer_callback_t callback; /*!< Callback function invoked at the transfer event. */
+ status_t completionStatus; /*!< I2C slave transfer complete status, indicating how the transfer ends, such as
+ #kStatus_I2C_Nak indicates the slave was nacked by master before all the data was sent. This parameter is only
+ useful when eEvent is #kI2C_SlaveCompletionEvent. */
+ void *userData; /*!< User configurable pointer to any data, function, structure etc that user wish to use in the
+ callback. */
+} i2c_slave_handle_t;
+/* --------------------------------------------- Slave Transfer Sub-group ------------------------------------------- */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! brief Typedef for interrupt handler. */
+typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle);
+
+/*! @brief Pointers to i2c IRQ number for each instance. */
+extern const IRQn_Type s_I2cIrqs[];
+
+/*! @brief Pointers to i2c handles for each instance. */
+extern void *s_i2cHandles[];
+
+/*! @brief Pointer to master IRQ handler for each instance. */
+extern i2c_isr_t s_i2cMasterIsr;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name Hardware Status Flags Sub-group
+ * @{
+ */
+/*!
+ * @brief Gets the I2C master hardware status flags.
+ *
+ * @param base I2C base pointer
+ * @return the mask of status flags, can be a single flag or several flags in #_i2c_master_status_flags ORed together
+ */
+static inline uint32_t I2C_MasterGetStatusFlags(I2C_Type *base)
+{
+ return ((base->IC_RAW_INTR_STAT & 0x75FUL) | ((base->IC_TX_ABRT_SOURCE & 0x1FFFUL) << 12U) |
+ ((base->IC_STATUS & 0x3FUL) << 25U));
+}
+
+/*!
+ * @brief Clears the I2C master status flags.
+ *
+ * @param base I2C base pointer
+ * @param statusFlags The status flag mask, can be a single flag or several flags in #_i2c_status_flags ORed
+ * together.
+ */
+void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusFlags);
+
+/*!
+ * @brief Gets the I2C slave hardware status flags.
+ *
+ * @param base I2C base pointer
+ * @return the mask of status flags, can be a single flag or several flags in #_i2c_status_flags ORed together
+ */
+static inline uint32_t I2C_SlaveGetStatusFlags(I2C_Type *base)
+{
+ return ((base->IC_RAW_INTR_STAT & 0xFFFUL) | (base->IC_TX_ABRT_SOURCE & 0xE000UL) |
+ ((base->IC_ENABLE_STATUS & 0x6UL) << 16U) | ((base->IC_STATUS & 0x5FUL) << 25U));
+}
+
+/*!
+ * @brief Clears the I2C slave status flags.
+ *
+ * @param base I2C base pointer
+ * @param statusFlags The status flag mask, can be a single flag or several flags in #_i2c_slave_status_flags ORed
+ * together
+ */
+void I2C_SlaveClearStatusFlags(I2C_Type *base, uint32_t statusFlags);
+/* @} */
+
+/*!
+ * @name Interrupt Sub-group
+ * @{
+ */
+/*!
+ * @brief Enables I2C interrupt source.
+ *
+ * @param base I2C base pointer
+ * @param interrupts The interrupt source mask, can be a single source or several sources in #_i2c_interrupt_enable
+ * ORed together
+ */
+static inline void I2C_EnableInterrupts(I2C_Type *base, uint16_t interrupts)
+{
+ base->IC_INTR_MASK |= (uint32_t)interrupts;
+}
+
+/*!
+ * @brief Disables I2C interrupt source.
+ *
+ * @param base I2C base pointer
+ * @param interrupts The interrupt source mask, can be a single source or several sources in #_i2c_interrupt_enable
+ * ORed together
+ */
+static inline void I2C_DisableInterrupts(I2C_Type *base, uint16_t interrupts)
+{
+ base->IC_INTR_MASK &= ~(uint32_t)interrupts;
+}
+/*!
+ * @brief Get all the enabled interrupt sources.
+ *
+ * @param base I2C base pointer
+ * @return The interrupt source mask, can be a single source or several sources in #_i2c_interrupt_enable ORed
+ * together
+ */
+static inline uint16_t I2C_GetEnabledInterrupts(I2C_Type *base)
+{
+ return (uint16_t)(base->IC_INTR_MASK & 0xFFFUL);
+}
+/* @} */
+
+/*!
+ * @name Module Init/Deinit Sub-group
+ * @{
+ */
+/*!
+ * @brief Sets the I2C master configuration structure to default values.
+ *
+ * The purpose of this API is to initialize the configuration structure to default value for @ref I2C_MasterInit to use.
+ * Use the unchanged structure in @ref I2C_MasterInit or modify the structure before calling @ref I2C_MasterInit.
+ * This is an example:
+ * @code
+ * i2c_master_config_t config;
+ * I2C_MasterGetDefaultConfig(&config);
+ * I2C_MasterInit(I2C0, &config, 12000000U);
+ * @endcode
+ *
+ * @param masterConfig Pointer to the master configuration structure
+ */
+void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig);
+
+/*!
+ * @brief Initializes the I2C peripheral to operate as master.
+ *
+ * This API initialize the I2C module for master operation.
+ *
+ * @note If FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL is enbaled by user, the init function will not ungate I2C clock source
+ * before initialization, to avoid hardfault, user has to manually enable ungate the clock source before calling the API
+ *
+ * The configuration structure can be filled manully or be set with default values by calling
+ * @ref I2C_MasterGetDefaultConfig. This is an example.
+ * @code
+ * I2C_MasterGetDefaultConfig(&config);
+ * I2C_MasterInit(I2C0, &config, 12000000U);
+ * @endcode
+ *
+ * @param base I2C base pointer
+ * @param masterConfig Pointer to the master configuration structure
+ * @param sourceClock_Hz Frequency in Hertz of the I2C functional clock source
+ */
+void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t sourceClock_Hz);
+
+/*!
+ * @brief De-initializes the I2C peripheral. Call this API to disable the I2C module.
+ *
+ * @param base I2C base pointer
+ */
+void I2C_MasterDeinit(I2C_Type *base);
+
+/*!
+ * @brief Sets the I2C slave configuration structure to default values.
+ *
+ * The purpose of this API is to initialize the configuration structure for @ref I2C_SlaveInit to use. Use the unchanged
+ * initialized structure in @ref I2C_SlaveInit or modify the structure before calling @ref I2C_SlaveInit.
+ * This is an example.
+ * @code
+ * i2c_slave_config_t config;
+ * config.slaveAdress = 0x7FU;
+ * I2C_SlaveGetDefaultConfig(&config);
+ * @endcode
+ *
+ * @param slaveConfig Pointer to the slave configuration structure
+ */
+void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig);
+
+/*!
+ * @brief Initializes the I2C peripheral to operate as slave.
+ *
+ * This API initialize the I2C module for slave operation. User can also configure whether to enable the module in the
+ * function.
+ *
+ * @note If FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL is enbaled by user, the init function will not ungate I2C clock source
+ * before initialization, to avoid hardfault, user has to manually ungate the clock source before calling the API
+ *
+ * The configuration structure can be filled manully or be set with default values by calling
+ * @ref I2C_SlaveGetDefaultConfig. This is an example.
+ * @code
+ * i2c_slave_config_t sConfig;
+ * I2C_SlaveGetDefaultConfig(&sConfig);
+ * sConfig.address = 0x2AU;
+ * I2C_SlaveInit(I2C0, &sConfig);
+ * @endcode
+ *
+ * @param base I2C base pointer
+ * @param slaveConfig Pointer to the slave configuration structure
+ */
+void I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig);
+
+/*!
+ * @brief De-initializes the I2C peripheral. Call this API to disable the I2C module.
+ *
+ * @param base I2C base pointer
+ */
+void I2C_SlaveDeinit(I2C_Type *base);
+/* @} */
+
+/*!
+ * @name Common Peripheral Configuration Sub-group
+ * @{
+ */
+/*!
+ * @brief Sets I2C rx FIFO watermark.
+ *
+ * @param base I2C base pointer
+ * @param rxWaterMark rx watermark level
+ */
+static inline void I2C_SetRxWaterMark(I2C_Type *base, uint8_t rxWaterMark)
+{
+ base->IC_RX_TL = (uint32_t)rxWaterMark;
+}
+
+/*!
+ * @brief Sets I2C tx FIFO watermark.
+ *
+ * @param base I2C base pointer
+ * @param txWaterMark tx watermark level
+ */
+static inline void I2C_SetTxWaterMark(I2C_Type *base, uint8_t txWaterMark)
+{
+ base->IC_TX_TL = (uint32_t)txWaterMark;
+}
+
+/*!
+ * @brief Enables or disables the I2C module.
+ *
+ * @param base I2C base pointer
+ * @param enable Pass true to enable and false to disable the module
+ */
+static inline void I2C_Enable(I2C_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IC_ENABLE |= (uint32_t)I2C_IC_ENABLE_ENABLE_MASK;
+ }
+ else
+ {
+ base->IC_ENABLE &= ~(uint32_t)I2C_IC_ENABLE_ENABLE_MASK;
+ }
+}
+
+/*!
+ * @brief Enables the I2C module as master or slave.
+ *
+ * @param base I2C base pointer
+ * @param enable Pass true to enable as master and false to enable as slave
+ */
+static inline void I2C_EnableMaster(I2C_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IC_CON |= ((uint32_t)I2C_IC_CON_MASTER_MODE_MASK | (uint32_t)I2C_IC_CON_IC_SLAVE_DISABLE_MASK);
+ }
+ else
+ {
+ base->IC_CON &= ~((uint32_t)I2C_IC_CON_MASTER_MODE_MASK | (uint32_t)I2C_IC_CON_IC_SLAVE_DISABLE_MASK);
+ }
+}
+
+/*!
+ * @brief Gets the data count in tx FIFO.
+ *
+ * @param base I2C base pointer
+ * @return The data count in tx FIFO
+ */
+static inline uint8_t I2C_GetTxFifoDataCount(I2C_Type *base)
+{
+ return (uint8_t)base->IC_TXFLR;
+}
+
+/*!
+ * @brief Gets the data count in rx FIFO.
+ *
+ * @param base I2C base pointer
+ * @return The data count in rx FIFO
+ */
+static inline uint8_t I2C_GetRxFifoDataCount(I2C_Type *base)
+{
+ return (uint8_t)base->IC_RXFLR;
+}
+
+/*!
+ * @brief Gets tx FIFO depth.
+ *
+ * @param base I2C base pointer
+ * @return The tx FIFO depth
+ */
+static inline uint8_t I2C_GetTxFifoDepth(I2C_Type *base)
+{
+ return (uint8_t)((base->IC_COMP_PARAM_1 & I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MASK) >>
+ I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_SHIFT);
+}
+
+/*!
+ * @brief Gets rx FIFO depth.
+ *
+ * @param base I2C base pointer
+ * @return The rx FIFO depth
+ */
+static inline uint8_t I2C_GetRxFifoDepth(I2C_Type *base)
+{
+ return (uint8_t)((base->IC_COMP_PARAM_1 & I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MASK) >>
+ I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_SHIFT);
+}
+
+/*!
+ * @brief Sets I2C SDA hold time.
+ *
+ * @param base I2C base pointer
+ * @param sdaHoldTime Number of clock source cycles of SDA hold time
+ */
+static inline void I2C_SetSdaHoldTime(I2C_Type *base, uint16_t sdaHoldTime)
+{
+ base->IC_SDA_HOLD = (uint32_t)sdaHoldTime;
+}
+
+/*!
+ * @brief Sets I2C SDA setup time.
+ *
+ * @param base I2C base pointer
+ * @param sdaSetupTime Number of clock source cycles of SDA setup time
+ */
+static inline void I2C_SetSdaSetupTime(I2C_Type *base, uint16_t sdaSetupTime)
+{
+ base->IC_SDA_SETUP = (uint32_t)sdaSetupTime;
+}
+
+/*!
+ * @brief Enables I2C module to response ack to general call.
+ *
+ * @param base I2C base pointer
+ * @param enable Pass true to enable and false to disable
+ */
+static inline void I2C_EnableAckGeneralCall(I2C_Type *base, bool enable)
+{
+ base->IC_ACK_GENERAL_CALL = (uint32_t)enable;
+}
+
+/*!
+ * @brief Returns whether the I2C module is enabled.
+ *
+ * @param base I2C base pointer
+ * @return True for enabled, false for disabled.
+ */
+static inline bool I2C_IsEnabled(I2C_Type *base)
+{
+ return (0U != (base->IC_ENABLE_STATUS & (uint32_t)I2C_IC_ENABLE_STATUS_IC_EN_MASK));
+}
+
+/*!
+ * @brief Sets I2C glitch filter width of normal and fast mode.
+ *
+ * @param base I2C base pointer
+ * @param glitchFilter Number of clock source cycles of max glitch time
+ */
+static inline void I2C_SetGlitchFilter(I2C_Type *base, uint8_t glitchFilter)
+{
+ base->IC_FS_SPKLEN = (uint32_t)glitchFilter;
+}
+
+/*!
+ * @brief Sets I2C glitch filter width of high speed mode.
+ *
+ * @param base I2C base pointer
+ * @param glitchFilter Number of clock source cycles of max glitch time
+ */
+static inline void I2C_SetGlitchFilterHighSpeed(I2C_Type *base, uint8_t glitchFilter)
+{
+ base->IC_HS_SPKLEN = (uint32_t)glitchFilter;
+}
+/* @} */
+
+/*!
+ * @name Master Peripheral Configuration Sub-group
+ * @{
+ */
+/*!
+ * @brief Sets I2C master high speed mode address.
+ *
+ * @param base I2C base pointer
+ * @param address High speed address, only low 3 bits are avaliable
+ */
+static inline void I2C_MasterSetHighSpeedAddress(I2C_Type *base, uint8_t address)
+{
+ base->IC_HS_MADDR = (uint32_t)(address & 0x7UL);
+}
+
+/*!
+ * @brief Returns whether the I2C module is in master mode.
+ *
+ * @note Although I2C can not be master and slave at the same time, when I2C is not in master mode does not mean it's in
+ * slave mode, the master and slave function may both be disabled.
+ *
+ * @param base I2C base pointer
+ * @return True for master mode enabled, false for disabled.
+ */
+static inline bool I2C_IsMaster(I2C_Type *base)
+{
+ return ((base->IC_CON & (uint32_t)(I2C_IC_CON_MASTER_MODE_MASK | I2C_IC_CON_IC_SLAVE_DISABLE_MASK)) ==
+ (uint32_t)(I2C_IC_CON_MASTER_MODE_MASK | I2C_IC_CON_IC_SLAVE_DISABLE_MASK));
+}
+
+/*!
+ * @brief Sets I2C master addressing mode.
+ *
+ * @param base I2C base pointer
+ * @param addressingMode The I2C addressing mode master operates
+ */
+static inline void I2C_MasterSetAddressingMode(I2C_Type *base, i2c_address_mode_t addressingMode)
+{
+ if (addressingMode == kI2C_AddressMatch7bit)
+ {
+ base->IC_TAR &= ~(uint32_t)I2C_IC_TAR_IC_10BITADDR_MASTER_MASK;
+ }
+ else
+ {
+ base->IC_TAR |= (uint32_t)I2C_IC_TAR_IC_10BITADDR_MASTER_MASK;
+ }
+}
+
+/*!
+ * @brief Sets target address for I2C master transaction.
+ *
+ * @param base I2C base pointer
+ * @param address The I2C addressing mode master operates
+ */
+static inline void I2C_MasterSetTargetAddress(I2C_Type *base, uint16_t address)
+{
+ base->IC_TAR = (base->IC_TAR & ~(uint32_t)I2C_IC_TAR_IC_TAR_MASK) | I2C_IC_TAR_IC_TAR(address);
+}
+
+/*!
+ * @brief Choose whether to perform general call command.
+ *
+ * @param base I2C base pointer
+ * @param enable True to issue general call, false to issue common start byte according to target address
+ */
+static inline void I2C_MasterEnableGeneralCall(I2C_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IC_TAR = (base->IC_TAR & ~(uint32_t)(I2C_IC_TAR_GC_OR_START_MASK)) | I2C_IC_TAR_SPECIAL_MASK;
+ }
+ else
+ {
+ base->IC_TAR &= ~(uint32_t)(I2C_IC_TAR_SPECIAL_MASK | I2C_IC_TAR_GC_OR_START_MASK);
+ }
+}
+
+/*!
+ * @brief Sets the I2C transaction speed mode.
+ *
+ * After the I2C module is initialized as master, user can call this function to change the transfer baud rate. There
+ * are 3 speed modes to choos from, kI2C_MasterSpeedStandard for 100kbps, kI2C_MasterSpeedFast for 400kbps and
+ * kI2C_MasterSpeedHigh for 3.4Mbps.
+ *
+ * @param base I2C base pointer.
+ * @param speed Master transfer speed mode to be configured
+ * @param sourceClock_Hz I2C peripheral clock frequency in Hz
+ */
+void I2C_MasterSetSpeedMode(I2C_Type *base, i2c_master_speed_mode_t speed, uint32_t sourceClock_Hz);
+/* @} */
+
+/*!
+ * @name Slave Peripheral Configuration Sub-group
+ * @{
+ */
+/*!
+ * @brief Returns whether the I2C module is in slave mode.
+ *
+ * @note Although I2C can not be master and slave at the same time, when I2C is not in slave mode does not mean it's in
+ * master mode, the master and slave function may both be disabled.
+ *
+ * @param base I2C base pointer
+ * @return True for slave mode enabled, false for disabled.
+ */
+static inline bool I2C_IsSlave(I2C_Type *base)
+{
+ return ((base->IC_CON & (uint32_t)(I2C_IC_CON_MASTER_MODE_MASK | I2C_IC_CON_IC_SLAVE_DISABLE_MASK)) == 0U);
+}
+
+/*!
+ * @brief Sets I2C slave addressing mode and address.
+ *
+ * @param base I2C base pointer
+ * @param addressingMode The I2C addressing mode slave resonses to
+ * @param address The I2C address, for 7-bit only low 7 bits are valid and for 10-bit only low 10 bits are valid
+ */
+static inline void I2C_SlaveSetAddressingMode(I2C_Type *base, i2c_address_mode_t addressingMode, uint16_t address)
+{
+ if (addressingMode == kI2C_AddressMatch7bit)
+ {
+ base->IC_CON &= ~(uint32_t)I2C_IC_CON_IC_10BITADDR_SLAVE_MASK;
+ }
+ else
+ {
+ base->IC_CON |= (uint32_t)I2C_IC_CON_IC_10BITADDR_SLAVE_MASK;
+ }
+ base->IC_SAR = (uint32_t)address;
+}
+/* @} */
+
+/*!
+ * @name Common Bus Operation Sub-Group
+ * @{
+ */
+/*!
+ * @brief Reads one byte from data register directly.
+ *
+ * @param base I2C base pointer
+ * @return The data read from data register.
+ */
+static inline uint8_t I2C_ReadByte(I2C_Type *base)
+{
+ return (uint8_t)(base->IC_DATA_CMD & 0xFFUL);
+}
+
+/*!
+ * @brief Writes one byte to the data register directly.
+ *
+ * @note If using I2C as master to perform read operation, user needs to write dummy to data register to generate clock,
+ * do not use this API to write dummy since this API will issue write command simultaneously, use @ref
+ * I2C_MasterWriteDummy.
+ *
+ * @param base I2C base pointer
+ * @param data The byte to write.
+ */
+static inline void I2C_WriteByte(I2C_Type *base, uint8_t data)
+{
+ base->IC_DATA_CMD = (((uint32_t)data) & 0xFFUL);
+}
+/* @} */
+
+/*!
+ * @name DMA Configuration Sub-Group
+ * @{
+ */
+/*!
+ * @brief Disables the I2C DMA requests.
+ *
+ * @param base I2C base pointer
+ * @param mask Enable mask formed by enums in #_i2c_dma_enable_flags
+ */
+static inline void I2C_EnableDMA(I2C_Type *base, uint8_t mask)
+{
+ base->IC_DMA_CR |= (uint32_t)mask;
+}
+
+/*!
+ * @brief Enables the I2C DMA requests.
+ *
+ * @param base I2C base pointer
+ * @param mask Disable mask formed by enums in #_i2c_dma_enable_flags
+ */
+static inline void I2C_DisableDMA(I2C_Type *base, uint8_t mask)
+{
+ base->IC_DMA_CR &= ~(uint32_t)mask;
+}
+
+/*!
+ * @brief Sets I2C tx DMA trigger level.
+ *
+ * @param base I2C base pointer
+ * @param txLevel tx DMA trigger level
+ */
+static inline void I2C_SetDmaTxWaterMark(I2C_Type *base, uint8_t txLevel)
+{
+ base->IC_DMA_TDLR = (uint32_t)txLevel;
+}
+
+/*!
+ * @brief Sets I2C rx DMA trigger level.
+ *
+ * @param base I2C base pointer
+ * @param rxLevel rx DMA trigger level
+ */
+static inline void I2C_SetDmaRxWaterMark(I2C_Type *base, uint8_t rxLevel)
+{
+ base->IC_DMA_RDLR = (uint32_t)rxLevel;
+}
+
+/*!
+ * @brief Gets I2C read/write register address.
+ *
+ * @param base I2C base pointer
+ * @return The I2C Data Register address.
+ */
+static inline uint32_t I2C_GetDataRegAddr(I2C_Type *base)
+{
+ return (uint32_t)((void *)(&(base->IC_DATA_CMD)));
+}
+/* @} */
+
+/*!
+ * @name Master Bus Operation Sub-Group
+ * @{
+ */
+/*!
+ * @brief Writes dummy data data register and issue read command to generate clock.
+ *
+ * @note If using I2C as master to perform read operation, user needs to write dummy to data register to generate clock,
+ * use this API not @ref I2C_WriteByte to write dummy, since I2C_WriteByte issue write command simultaneously.
+ *
+ * @param base I2C base pointer
+ */
+static inline void I2C_MasterWriteDummy(I2C_Type *base)
+{
+ base->IC_DATA_CMD = 0x100UL;
+}
+
+/*!
+ * @brief Convert provided status flags to status code, and clear any errors if present.
+ *
+ * @note: The API only checks the error status that occured on bus, error caused by user misuse such as
+ * kI2C_RxUnderflowInterruptFlag, kI2C_TxOverflowInterruptFlag or kI2C_MasterOperateWhenDisabledFlag will not be checked
+ *
+ * @param base The I2C peripheral base address.
+ * @param status Status flags to check.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_RxHardwareOverrun Master rx FIFO overflow
+ * @retval #kStatus_I2C_GeneralCall_Nak Master nacked after issueing general call
+ * @retval #kStatus_I2C_ArbitrationLost Master lost arbitration when addressing
+ * @retval #kStatus_I2C_Nak Master nacked during data transmitting
+ * @retval #kStatus_I2C_Addr_Nak Master nacked during slave probing
+ */
+status_t I2C_MasterCheckAndClearError(I2C_Type *base, uint32_t status);
+
+/*!
+ * @brief Sends a piece of data to I2C bus in master mode in blocking way.
+ *
+ * Call this function when using I2C as master to send certain bytes of data to bus. This function uses the blocking
+ * way, which means it does not return until all the data is sent to bus.
+ *
+ * @note The I2C module generates START/STOP/RESTART automatically. When tx FIFO state changes from empty to not empty,
+ * start signal is generated; when tx FIFO is empty again, stop signal is generated; when read command follows a write
+ * command, restart signal is generated in between. So stop signal will be generated after this API returns, and before
+ * calling this API if tx FIFO is empty, start signal will be generated first automatically, if tx FIFO is not empty and
+ * the last command in tx FIFO is write, restart signal will be generated first automatically.
+ *
+ * @param base I2C base pointer.
+ * @param data The pointer to the data to be transmitted.
+ * @param txSize The length in bytes of the data to be transmitted.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval kStatus_I2C_Nak Transfer error, receive NAK during transfer.
+ * @retval kStatus_I2C_Addr_Nak Transfer error, receive NAK during addressing, only applies when tx FIFO is empty before
+ * calling this API.
+ * @retval #kStatus_I2C_Timeout Transfer error, timeout happens when waiting for status flags to change.
+ */
+status_t I2C_MasterWriteBlocking(I2C_Type *base, const uint8_t *data, size_t txSize);
+
+/*!
+ * @brief Receives a piece of data from I2C bus in master mode in blocking way.
+ *
+ * Call this function when using I2C as master to receive certain bytes of data from bus. This function uses the
+ * blocking way, which means it does not return until all the data is received or is nacked by slave.
+ *
+ * @note When doing read operation, software needs to push dummy data to tx FIFO with read command to generate clock,
+ * plus I2C module generates START/STOP/RESTART automatically, meaning when tx FIFO state changes from empty to not
+ * empty, start signal is generated, when tx FIFO is empty again, stop signal is generated, when read command follows
+ * a write command, restart signal is generated in between. So stop signal will be generated after this API returns,
+ * and before calling this API if tx FIFO is empty, start signal will be generated first automatically, if tx FIFO is
+ * not empty and the last command in tx FIFO is write, restart signal will be generated first automatically.
+ *
+ * @param base I2C base pointer.
+ * @param data The pointer to the data to store the received data.
+ * @param rxSize The length in bytes of the data to be received.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval kStatus_I2C_Timeout Send stop signal failed, timeout.
+ */
+status_t I2C_MasterReadBlocking(I2C_Type *base, uint8_t *data, size_t rxSize);
+/* @} */
+
+/*!
+ * @name Slave Bus Operation Sub-Group
+ * @{
+ */
+/*!
+ * @brief Enables slave to send nack after receiving next byte of data
+ *
+ * @param base I2C base pointer
+ * @param enable Pass true to enable nack and false to disable
+ */
+static inline void I2C_SlaveNackNextByte(I2C_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IC_SLV_DATA_NACK_ONLY |= I2C_IC_SLV_DATA_NACK_ONLY_NACK_MASK;
+ }
+ else
+ {
+ base->IC_SLV_DATA_NACK_ONLY &= ~I2C_IC_SLV_DATA_NACK_ONLY_NACK_MASK;
+ }
+}
+
+/*!
+ * @brief Convert provided status flags to status code, and clear any errors if present.
+ *
+ * @note: The API only checks the error status that occured on bus, error caused by user misuse such as
+ * kI2C_RxUnderflowInterruptFlag, kI2C_TxOverflowInterruptFlag, kI2C_SlaveReadWhenRequestedDataFlag or
+ * kI2C_SlaveDisabledWhileBusy will not be checked
+ *
+ * @param base The I2C peripheral base address.
+ * @param status Status flags to check.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_RxHardwareOverrun Slave rx FIFO overflow
+ * @retval #kStatus_I2C_TxFifoFlushed Slave is addressed and is requested data but there are still old data remaining in
+ * tx FIFO
+ * @retval #kStatus_I2C_ArbitrationLost Data on SDA is not the same as slave transmitted
+ * @retval #kStatus_I2C_Nak Slave nacked by master
+ */
+status_t I2C_SlaveCheckAndClearError(I2C_Type *base, uint32_t status);
+
+/*!
+ * @brief Sends a piece of data to I2C bus in slave mode in blocking way.
+ *
+ * Call this funtion to let I2C slave poll register status until it is addressed, then slave sends txSize of data to bus
+ * until all the data has been sent to bus or untill it is nacked.
+ *
+ * @param base I2C base pointer.
+ * @param data The pointer to the data to be transferred.
+ * @param txSize The length in bytes of the data to be transferred.
+ * @retval #kStatus_Success
+ * @retval #kStatus_I2C_TxFifoFlushed Slave is addressed and is requested data but there are still old data remaining in
+ * tx FIFO
+ * @retval #kStatus_I2C_ArbitrationLost Data on SDA is not the same as slave transmitted
+ * @retval #kStatus_I2C_Nak Slave nacked by master
+ */
+status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *data, size_t txSize);
+
+/*!
+ * @brief Receives a piece of data from I2C bus in slave mode in blocking way.
+ *
+ * Call this funtion to let I2C slave poll register status until it is addressed, then slave receives rxSize of data
+ * until all the data has been received.
+ *
+ * @param base I2C base pointer.
+ * @param data The pointer to the data to store the received data.
+ * @param rxSize The length in bytes of the data to be received.
+ * @retval kStatus_Success Successfully complete data receive.
+ * @retval kStatus_I2C_Timeout Wait status flag timeout.
+ */
+status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *data, size_t rxSize);
+/* @} */
+
+/*!
+ * @name Master Transfer Sub-group
+ * @{
+ */
+/*!
+ * @brief Performs a master polling transfer on the I2C bus.
+ *
+ * @note The API does not return until the transfer succeeds or fails due to arbitration lost or receiving a NAK.
+ *
+ * @param base I2C base pointer.
+ * @param transferConfig Pointer to the transfer configuration structure.
+ * @retval kStatus_Success Successfully complete the data transmission.
+ * @retval #kStatus_I2C_Busy Previous transmission still not finished.
+ * @retval #kStatus_I2C_Timeout Transfer error, timeout happens when waiting for status flags to change.
+ * @retval #kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
+ * @retval #kStatus_I2C_Nak Transfer error, receive NAK during transfer.
+ * @retval #kStatus_I2C_Addr_Nak Transfer error, receive NAK during slave probing.
+ * @retval #kStatus_I2C_GeneralCall_Nak Transfer error, receive NAK after issueing general call.
+ */
+status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *transferConfig);
+
+/*!
+ * @brief Initializes the I2C master transfer in interrupt way.
+ *
+ * This function is responsible for initializig master transfer handle, installing user callback, registering master
+ * IRQ handling function and opening global interrupt.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_transfer_handle_t structure to store the transfer state.
+ * @param callback pointer to user callback function.
+ * @param userData User configurable pointer to any data, function, structure etc that user wish to use in the callback
+ */
+void I2C_MasterTransferCreateHandle(I2C_Type *base,
+ i2c_master_handle_t *handle,
+ i2c_master_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Initiates a master transfer on the I2C bus in interrupt way.
+ *
+ * @note Transfer in interrupt way is non-blocking which means this API returns immediately after transfer initiates.
+ * User can call @ref I2C_MasterTransferGetCount to get the count of data that master has transmitted/received and check
+ * transfer status. If the return status is kStatus_NoTransferInProgress, the transfer is finished. Also if user
+ * installs a user callback when calling @ref I2C_MasterTransferCreateHandle before, the callback will be invoked when
+ * transfer finishes.
+ *
+ * @param base I2C base pointer
+ * @param handle pointer to i2c_master_transfer_handle_t structure which stores the transfer state.
+ * @param transfer Pointer to the transfer configuration structure.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval #kStatus_I2C_Busy Previous transmission still not finished.
+ */
+status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *transfer);
+
+/*!
+ * @brief Gets the master transfer count and status during a interrupt transfer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_transfer_handle_t structure which stores the transfer state.
+ * @param count Pointer to number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_NoTransferInProgress Curent no transfer is in progress.
+ * @retval kStatus_Success Successfully obtained the count.
+ */
+status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts an in-process transfer in interrupt way.
+ *
+ * @note This API can be called at any time after a transfer of interrupt way initiates and before it finishes to abort
+ * the transfer early.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_master_handle_t structure which stores the transfer state
+ */
+void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
+/* @} */
+
+/*!
+ * @name Slave Transfer Sub-group
+ * @{
+ */
+/*!
+ * @brief Initializes the I2C slave transfer in interrupt way.
+ *
+ * This function is responsible for initializig slave transfer handle, installing user callback, registering master
+ * IRQ handling function and opening global interrupt.
+ *
+ * @param base I2C base pointer
+ * @param handle pointer to i2c_slave_handle_t structure to store the transfer state
+ * @param callback pointer to user callback function
+ * @param userData User configurable pointer to any data, function, structure etc that user wish to use in the callback
+ */
+void I2C_SlaveTransferCreateHandle(I2C_Type *base,
+ i2c_slave_handle_t *handle,
+ i2c_slave_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Sets I2C slave ready to process bus events.
+ *
+ * Call this API to let I2C start monitoring bus events driven by I2C master on bus. When user specified event occurs,
+ * callback will be invoked passes event information to the callback.
+ *
+ * @note When #kI2C_SlaveTransmitEvent and #kI2C_SlaveReceiveEvent occured, slave callback will
+ * always be revoked regardless which events user choose to enable. This means user need not configure them in the
+ * eventMask. If user wants to enable all the events, use #kI2C_SlaveAllEvents for convenience.
+ *
+ * @param base The I2C peripheral base address.
+ * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state.
+ * @param eventMask Bit mask formed by OR operation of event(s) in #i2c_slave_transfer_event_t enumerators. When these
+ * events occur the callback will be invoked.
+ * @retval kStatus_I2C_Busy I2C slave has already been started on this handle.
+ */
+status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle, uint8_t eventMask);
+
+/*!
+ * @brief Gets how many bytes slave have transferred in curent data buffer.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure.
+ * @param count Number of bytes slave have transferred after the last start/repeated start.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_NoTransferInProgress Curent no transfer is in progress.
+ * @retval kStatus_Success Successfully obtained the count.
+ */
+status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Aborts the slave transfer.
+ *
+ * @note This API can be called at any time to stop slave for handling further bus events.
+ *
+ * @param base I2C base pointer.
+ * @param handle pointer to i2c_slave_handle_t structure which stores the transfer state.
+ */
+void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle);
+/* @} */
+
+/*!
+ * @brief Gets instance number for I2C module.
+ *
+ * @param base I2C base pointer.
+ * @retval The number of the instance.
+ */
+uint32_t I2C_GetInstance(I2C_Type *base);
+
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+
+#endif /* _FSL_I2C_H_*/
diff --git a/drivers/mw320/i2c/fsl_i2c_dmac.c b/drivers/mw320/i2c/fsl_i2c_dmac.c
new file mode 100644
index 000000000..959fe64f8
--- /dev/null
+++ b/drivers/mw320/i2c/fsl_i2c_dmac.c
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2020,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_i2c_dmac.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.i2c_dmac"
+#endif
+
+/*! brief i2c master dmac transfer state, used in I2C dmac driver internal transfer state. */
+enum _i2c_master_dmac_transfer_states
+{
+ kMasterIdleState = 0x0U, /*!< I2C bus idle. */
+ kMasterBusy = 0x1U, /*!< i2C bus busy. */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief DMAC callback for I2C master DMAC transfer.
+ *
+ * @param handle DMAC handle
+ * @param userData user param passed to the callback function
+ * @param status Transfer completion status
+ */
+static void I2C_MasterTransferCallbackDMA(dmac_handle_t *handle, void *userData, uint32_t status);
+
+/*!
+ * @brief Master interrupt handler.
+ *
+ * @param base I2C base pointer.
+ * @param i2cHandle pointer to i2c_master_handle_t structure.
+ */
+static void I2C_MasterDmacTransferHandleIRQ(I2C_Type *base, void *i2cHandle);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! brief The dummy data used to send to generate clock when performing read operatipn. */
+static uint32_t g_TxDummy = 0x100UL;
+
+/*******************************************************************************
+ * Codes
+ ******************************************************************************/
+static void I2C_MasterTransferCallbackDMA(dmac_handle_t *handle, void *userData, uint32_t status)
+{
+ i2c_master_dmac_handle_t *i2cDmacHandle = (i2c_master_dmac_handle_t *)userData;
+ I2C_DisableDMA(i2cDmacHandle->base, (uint8_t)kQSPI_DmaTx | (uint8_t)kQSPI_DmaRx);
+ I2C_DisableInterrupts(i2cDmacHandle->base, (uint16_t)kI2C_AllInterruptEnable);
+
+ /* Wait for transfer to finish then clear all alearable status flags. */
+ while ((I2C_MasterGetStatusFlags(i2cDmacHandle->base) & kI2C_StopDetectInterruptFlag) == 0U)
+ {
+ }
+
+ I2C_MasterClearStatusFlags(i2cDmacHandle->base, (uint32_t)kI2C_MasterAllClearFlags);
+
+ if (i2cDmacHandle->completionCallback != NULL)
+ {
+ i2cDmacHandle->completionCallback(i2cDmacHandle->base, i2cDmacHandle, kStatus_Success, i2cDmacHandle->userData);
+ }
+}
+
+/*!
+ * brief Initializes the I2C master transfer in DMAC way.
+ *
+ * param base I2C peripheral base address
+ * param handle Pointer to i2c_master_dmac_handle_t structure to store the transfer state.
+ * param callback Pointer to the user callback function
+ * param userData User configurable pointer to any data, function, structure etc that user wish to use in the callback
+ * param dmacTxHandle DMAC handle pointer for tx
+ * param dmacRxHandle DMAC handle pointer for rx
+ */
+void I2C_MasterTransferCreateHandleDMAC(I2C_Type *base,
+ i2c_master_dmac_handle_t *handle,
+ i2c_master_dmac_transfer_callback_t callback,
+ void *userData,
+ dmac_handle_t *dmacTxHandle,
+ dmac_handle_t *dmacRxHandle)
+{
+ assert(handle != NULL);
+ assert(dmacTxHandle != NULL);
+ assert(dmacRxHandle != NULL);
+
+ uint32_t instance = I2C_GetInstance(base);
+
+ /* Zero handle. */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ /* Set the user callback and userData. */
+ handle->completionCallback = callback;
+ handle->userData = userData;
+
+ /* Set the DMAC handle and I2C base. */
+ handle->dmacTxHandle = dmacTxHandle;
+ handle->dmacRxHandle = dmacRxHandle;
+ handle->base = base;
+
+ /* Why using IRQ handler in DMAC transfer is that once master is nacked by slave or loses arbitration the transfer
+ should abort, however DMAC still keeps writing/reading which will push new data to tx FIFO and initiate new
+ transfer automatically, so we need to open interrupt to monitor event that can causes transfer abort. */
+
+ /* Save the handle into static handle array */
+ s_i2cHandles[instance] = handle;
+ /* Save IRQ handler into static ISR function pointer. */
+ s_i2cMasterIsr = I2C_MasterDmacTransferHandleIRQ;
+ /* Disable internal IRQs and enable global IRQ. */
+ I2C_DisableInterrupts(base, (uint16_t)kI2C_AllInterruptEnable);
+ (void)EnableIRQ(s_I2cIrqs[instance]);
+}
+
+/*!
+ * brief Initiates a master transfer on the I2C bus in DMAC way.
+ *
+ * note Transfer in DMAC way is non-blocking which means this API returns immediately after transfer initiates.
+ * If user installs a user callback when calling @ref I2C_MasterTransferCreateHandleDMAC before, the callback will be
+ * invoked when transfer finishes.
+ *
+ * param base I2C base pointer
+ * param handle pointer to i2c_master_transfer_handle_t structure which stores the transfer state.
+ * param xfer Pointer to the transfer configuration structure.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval #kStatus_I2C_Busy Previous transmission still not finished.
+ */
+status_t I2C_MasterTransferDMAC(I2C_Type *base, i2c_master_dmac_handle_t *handle, i2c_master_transfer_t *xfer)
+{
+ assert(handle != NULL);
+ assert(xfer != NULL);
+
+ /* Return busy if another transaction is in progress. */
+ if ((handle->state != (uint8_t)kMasterIdleState) ||
+ ((I2C_MasterGetStatusFlags(base) & (uint32_t)kI2C_BusBusyInterruptFlag) != 0U))
+ {
+ return kStatus_I2C_Busy;
+ }
+
+ dmac_channel_transfer_config_t dmacConfig;
+
+ /* Enable module */
+ I2C_Enable(base, true);
+
+ /* Set target slave address */
+ if (xfer->slaveAddress == 0U)
+ {
+ I2C_MasterEnableGeneralCall(base, true);
+ }
+ else
+ {
+ I2C_MasterEnableGeneralCall(base, false);
+ I2C_MasterSetTargetAddress(base, xfer->slaveAddress);
+ }
+
+ /* Empty rx FIFO first */
+ while ((base->IC_STATUS & I2C_IC_STATUS_RFNE_MASK) != 0U)
+ {
+ (void)I2C_ReadByte(base);
+ }
+
+ /* Clear all flags. */
+ I2C_MasterClearStatusFlags(base, (uint32_t)kI2C_MasterAllClearFlags);
+ /* Enable I2C internal IRQ sources */
+ I2C_EnableInterrupts(base, (uint16_t)kI2C_TxAbortInterruptEnable);
+
+ if (xfer->direction == kI2C_Write)
+ {
+ DMAC_GetChannelDefaultTransferConfig(&dmacConfig, (void *)xfer->data, (uint32_t *)I2C_GetDataRegAddr(base),
+ kDMAC_ChannelTransferWidth8Bits, kDMAC_ChannelBurstLength1DataWidth,
+ xfer->dataSize, kDMAC_ChannelTransferMemoryToPeripheral);
+ dmacConfig.interruptMask = kDMAC_ChannelInterruptFlagTransferComplete;
+ DMAC_TransferSetCallback(handle->dmacTxHandle, I2C_MasterTransferCallbackDMA, handle);
+ DMAC_TransferSubmit(handle->dmacTxHandle, &dmacConfig);
+ }
+ else
+ {
+ DMAC_GetChannelDefaultTransferConfig(&dmacConfig, (uint32_t *)I2C_GetDataRegAddr(base), (void *)xfer->data,
+ kDMAC_ChannelTransferWidth8Bits, kDMAC_ChannelBurstLength1DataWidth,
+ xfer->dataSize, kDMAC_ChannelTransferPeripheralToMemory);
+ dmacConfig.interruptMask = kDMAC_ChannelInterruptFlagTransferComplete;
+ DMAC_TransferSetCallback(handle->dmacRxHandle, I2C_MasterTransferCallbackDMA, handle);
+ DMAC_TransferSubmit(handle->dmacRxHandle, &dmacConfig);
+
+ DMAC_GetChannelDefaultTransferConfig(&dmacConfig, &g_TxDummy, (uint32_t *)I2C_GetDataRegAddr(base),
+ kDMAC_ChannelTransferWidth32Bits, kDMAC_ChannelBurstLength1DataWidth,
+ xfer->dataSize * sizeof(g_TxDummy),
+ kDMAC_ChannelTransferMemoryToPeripheral);
+ dmacConfig.srcAddrIncrementType = kDMAC_ChannelAddressFix;
+ DMAC_TransferSubmit(handle->dmacTxHandle, &dmacConfig);
+ }
+
+ while (xfer->subaddressSize != 0U)
+ {
+ xfer->subaddressSize--;
+ I2C_WriteByte(base, (uint8_t)((xfer->subaddress >> (8U * xfer->subaddressSize)) & 0xffU));
+ }
+
+ if (xfer->direction == kI2C_Write)
+ {
+ DMAC_TransferStart(handle->dmacTxHandle);
+ I2C_EnableDMA(base, (uint8_t)kQSPI_DmaTx);
+ }
+ else
+ {
+ DMAC_TransferStart(handle->dmacRxHandle);
+ DMAC_TransferStart(handle->dmacTxHandle);
+ I2C_EnableDMA(base, (uint8_t)kQSPI_DmaTx | (uint8_t)kQSPI_DmaRx);
+ }
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Aborts a master DMAC non-blocking transfer early.
+ *
+ * param base I2C peripheral base address
+ * param handle A pointer to the i2c_master_dmac_handle_t structure.
+ */
+void I2C_MasterTransferAbortDMAC(I2C_Type *base, i2c_master_dmac_handle_t *handle)
+{
+ DMAC_TransferStop(handle->dmacTxHandle);
+ DMAC_TransferStop(handle->dmacRxHandle);
+
+ /* Disable dmac transfer. */
+ I2C_DisableDMA(base, (uint8_t)kQSPI_DmaTx | (uint8_t)kQSPI_DmaRx);
+ /* Reset the state to idle. */
+ handle->state = (uint8_t)kMasterIdleState;
+}
+
+static void I2C_MasterDmacTransferHandleIRQ(I2C_Type *base, void *i2cHandle)
+{
+ assert(i2cHandle != NULL);
+ status_t result = kStatus_Success;
+ i2c_master_dmac_handle_t *handle = (i2c_master_dmac_handle_t *)i2cHandle;
+ uint32_t status = I2C_MasterGetStatusFlags(base);
+
+ I2C_MasterTransferAbortDMAC(base, handle);
+
+ if ((status & (uint32_t)kI2C_Master7bitAddressNackFlag) != 0U)
+ {
+ result = kStatus_I2C_Addr_Nak;
+ }
+
+ if ((status & (uint32_t)kI2C_MasterDataNackFlag) != 0U)
+ {
+ result = kStatus_I2C_Nak;
+ }
+
+ if ((status & (uint32_t)kI2C_MasterGeneralCallNackFlag) != 0U)
+ {
+ result = kStatus_I2C_GeneralCall_Nak;
+ }
+
+ if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U)
+ {
+ result = kStatus_I2C_ArbitrationLost;
+ }
+
+ if (handle->completionCallback != NULL)
+ {
+ handle->completionCallback(base, handle, result, handle->userData);
+ }
+}
diff --git a/drivers/mw320/i2c/fsl_i2c_dmac.h b/drivers/mw320/i2c/fsl_i2c_dmac.h
new file mode 100644
index 000000000..cd79b649f
--- /dev/null
+++ b/drivers/mw320/i2c/fsl_i2c_dmac.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2020,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_I2C_DMAC_H_
+#define _FSL_I2C_DMAC_H_
+
+#include "fsl_i2c.h"
+#include "fsl_dmac.h"
+
+/*!
+ * @addtogroup i2c_dmac_driver
+ * @ingroup i2c
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C DMAC driver version. */
+#define FSL_I2C_DMAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief Retry times for waiting flag. */
+#ifndef I2C_RETRY_TIMES
+#define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+#endif
+
+/*! @brief I2C master DMAC handle typedef. */
+typedef struct _i2c_master_dmac_handle i2c_master_dmac_handle_t;
+
+/*! @brief I2C master DMAC transfer callback typedef. */
+typedef void (*i2c_master_dmac_transfer_callback_t)(I2C_Type *base,
+ i2c_master_dmac_handle_t *handle,
+ status_t status,
+ void *userData);
+
+/*! @brief Typedef for master dmac handler. */
+typedef void (*i2c_dmac_master_irq_handler_t)(I2C_Type *base, i2c_master_dmac_handle_t *handle);
+
+/*! @brief I2C master DMAC transfer structure. */
+struct _i2c_master_dmac_handle
+{
+ I2C_Type *base; /*!< I2C instance base pointer. */
+ i2c_master_transfer_t transfer; /*!< I2C master transfer struct. */
+ size_t transferSize; /*!< Total bytes to be transferred. */
+ uint8_t state; /*!< I2C master transfer status. */
+ dmac_handle_t *dmacTxHandle; /*!< The DMAC handler used for tx. */
+ dmac_handle_t *dmacRxHandle; /*!< The DMAC handler used for rx. */
+ i2c_master_dmac_transfer_callback_t
+ completionCallback; /*!< A callback function called after the DMAC transfer finished. */
+ void *userData; /*!< A callback parameter passed to the callback function. */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /*_cplusplus. */
+
+/*!
+ * @name I2C Master DMAC Transfer Sub-group
+ * @{
+ */
+
+/*!
+ * @brief Initializes the I2C master transfer in DMAC way.
+ *
+ * @param base I2C peripheral base address
+ * @param handle Pointer to i2c_master_dmac_handle_t structure to store the transfer state.
+ * @param callback Pointer to the user callback function
+ * @param userData User configurable pointer to any data, function, structure etc that user wish to use in the callback
+ * @param dmacTxHandle DMAC handle pointer for tx
+ * @param dmacRxHandle DMAC handle pointer for rx
+ */
+void I2C_MasterTransferCreateHandleDMAC(I2C_Type *base,
+ i2c_master_dmac_handle_t *handle,
+ i2c_master_dmac_transfer_callback_t callback,
+ void *userData,
+ dmac_handle_t *dmacTxHandle,
+ dmac_handle_t *dmacRxHandle);
+
+/*!
+ * @brief Initiates a master transfer on the I2C bus in DMAC way.
+ *
+ * @note Transfer in DMAC way is non-blocking which means this API returns immediately after transfer initiates.
+ * If user installs a user callback when calling @ref I2C_MasterTransferCreateHandleDMAC before, the callback will be
+ * invoked when transfer finishes.
+ *
+ * @param base I2C base pointer
+ * @param handle pointer to i2c_master_transfer_handle_t structure which stores the transfer state.
+ * @param xfer Pointer to the transfer configuration structure.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval #kStatus_I2C_Busy Previous transmission still not finished.
+ */
+status_t I2C_MasterTransferDMAC(I2C_Type *base, i2c_master_dmac_handle_t *handle, i2c_master_transfer_t *xfer);
+
+/*!
+ * @brief Aborts an in-process transfer in DMAC way.
+ *
+ * @note This API can be called at any time after a transfer of DMAC way initiates and before it finishes to abort
+ * the transfer early.
+ *
+ * @param base I2C base pointer.
+ * @param handle Pointer to i2c_master_handle_t structure which stores the transfer state
+ */
+void I2C_MasterTransferAbortDMAC(I2C_Type *base, i2c_master_dmac_handle_t *handle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif /*_cplusplus. */
+/*@}*/
+#endif /*_FSL_I2C_DMAC_H_*/
diff --git a/drivers/mw320/qspi/driver_mw_qspi.cmake b/drivers/mw320/qspi/driver_mw_qspi.cmake
new file mode 100644
index 000000000..434c1a498
--- /dev/null
+++ b/drivers/mw320/qspi/driver_mw_qspi.cmake
@@ -0,0 +1,14 @@
+#Description: MW_QSPI Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_qspi component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_qspi.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/qspi/fsl_qspi.c b/drivers/mw320/qspi/fsl_qspi.c
new file mode 100644
index 000000000..32d7563af
--- /dev/null
+++ b/drivers/mw320/qspi/fsl_qspi.c
@@ -0,0 +1,426 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_qspi.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.qspi"
+#endif
+
+/*******************************************************************************
+ * Definitations
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void QSPI_MemSet(void *src, uint8_t value, size_t length);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Base pointer array */
+static QSPI_Type *const s_qspiBases[] = QSPI_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of QSPI clock name. */
+static const clock_ip_name_t s_qspiClock[] = QSPI_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void QSPI_MemSet(void *src, uint8_t value, size_t length)
+{
+ assert(src != NULL);
+ uint8_t *p = src;
+
+ for (volatile uint32_t i = 0U; i < length; i++)
+ {
+ *p = value;
+ p++;
+ }
+}
+
+/*!
+ * brief Get the instance number for QSPI.
+ *
+ * param base QSPI base pointer.
+ */
+uint32_t QSPI_GetInstance(QSPI_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_qspiBases); instance++)
+ {
+ if (s_qspiBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_qspiBases));
+
+ return instance;
+}
+
+/*!
+ * brief Initializes QSPI.
+ *
+ * param config QSPI configuration structure.
+ */
+void QSPI_Init(QSPI_Type *base, qspi_config_t *config)
+{
+ uint32_t val = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable qspi clock */
+ CLOCK_EnableClock(s_qspiClock[QSPI_GetInstance(base)]);
+#endif
+
+ /* Set QSPI clock prescaler */
+ val |= QSPI_CONF_CLK_PRESCALE(config->preScale);
+ /* Set data length mode */
+ val |= QSPI_CONF_BYTE_LEN(config->byteLen);
+ /* Set QSPI clock phase */
+ val |= QSPI_CONF_CLK_PHA(config->clockPhase);
+ /* Set QSPI clock polarity */
+ val |= QSPI_CONF_CLK_POL(config->clockPolarity);
+ /* Set data pin number */
+ val |= QSPI_CONF_DATA_PIN(config->dataPinMode);
+ /* Set address pin number */
+ val |= QSPI_CONF_ADDR_PIN(config->addrPinMode);
+
+ base->CONF = val;
+
+ val = base->TIMING;
+ /* Set QSPI capture clock edge */
+ val |= QSPI_TIMING_CLK_CAPT_EDGE(config->captureEdge);
+ base->TIMING = val;
+
+ /* Set header count. */
+ QSPI_SetHeaderCount(base, &config->headerCnt);
+
+ /* Unmask all interrupts */
+ QSPI_MaskInterrupts(base, 0x00U);
+}
+
+/*!
+ * brief Gets default settings for QSPI.
+ *
+ * param config QSPI configuration structure.
+ */
+void QSPI_GetDefaultConfig(qspi_config_t *config)
+{
+ /* Initializes the configure structure to zero. */
+ QSPI_MemSet(config, 0x00U, sizeof(*config));
+
+ config->preScale = kQSPI_ClockDiv1;
+ config->byteLen = kQSPI_TransferLength1Byte;
+ config->clockPhase = kQSPI_ClockPhaseRising;
+ config->clockPolarity = kQSPI_ClockPolarityLow;
+ config->dataPinMode = kQSPI_DataPinSingle;
+ config->addrPinMode = kQSPI_AddrPinSingle;
+ config->captureEdge = kQSPI_CaptureEdgeFirst;
+
+ /* Configure header count. */
+ config->headerCnt.instructionCnt = kQSPI_InstructionCnt0Byte;
+ config->headerCnt.addressCnt = kQSPI_AddressCnt0Byte;
+ config->headerCnt.readModeCnt = kQSPI_ReadModeCnt0Byte;
+ config->headerCnt.dummyCnt = kQSPI_DummyCnt0Byte;
+}
+
+/*!
+ * brief Deinitializes the QSPI module.
+ *
+ * param base Pointer to QSPI Type.
+ */
+void QSPI_Deinit(QSPI_Type *base)
+{
+}
+
+/*!
+ * brief Do software reset QSPI.
+ *
+ * param base Pointer to QSPI Type.
+ */
+void QSPI_SoftwareReset(QSPI_Type *base)
+{
+ base->CONF2 |= QSPI_CONF2_SRST_MASK;
+
+ /* Delay */
+ for (uint32_t i = 0x00U; i < 10U; i++)
+ {
+ __asm("nop");
+ }
+
+ base->CONF2 &= ~QSPI_CONF2_SRST_MASK;
+}
+
+/*!
+ * brief Flush Write and Read FIFOs.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return return status.
+ */
+status_t QSPI_FlushFIFO(QSPI_Type *base)
+{
+ status_t status = kStatus_InvalidArgument;
+ volatile uint32_t localCnt = 0U;
+
+ /* Flush write and read FIFO. */
+ base->CONF |= QSPI_CONF_FIFO_FLUSH_MASK;
+
+ /* Wait until Write and Read FIFOs are flushed. */
+ while (localCnt++ < 0xFFFFFFFU)
+ {
+ if ((base->CONF & QSPI_CONF_FIFO_FLUSH_MASK) == 0x00U)
+ {
+ status = kStatus_Success;
+ break;
+ }
+ }
+
+ return status;
+}
+
+/*!
+ * brief Set QSPI serial interface header count.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param config Pointer to header count configuration structure.
+ */
+void QSPI_SetHeaderCount(QSPI_Type *base, qspi_header_count_config_t *config)
+{
+ assert(config != NULL);
+
+ uint32_t tempVal = 0x00U;
+
+ tempVal = QSPI_HDRCNT_INSTR_CNT(config->instructionCnt) | QSPI_HDRCNT_ADDR_CNT(config->addressCnt) |
+ QSPI_HDRCNT_RM_CNT(config->readModeCnt) | QSPI_HDRCNT_DUMMY_CNT(config->dummyCnt);
+
+ base->HDRCNT = tempVal;
+}
+
+/*!
+ * @brief Activate or de-activate serial select output.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param enable enable or disable.
+ */
+void QSPI_SetSSEnable(QSPI_Type *base, bool enable)
+{
+ if (enable == true)
+ {
+ base->CNTL |= QSPI_CNTL_SS_EN_MASK;
+ }
+ else
+ {
+ base->CNTL &= ~QSPI_CNTL_SS_EN_MASK;
+ }
+
+ while (0x00U == (QSPI_GetStatusFlags(base) & (uint32_t)kQSPI_TransferReady))
+ {
+ }
+}
+
+/*!
+ * @brief Start the specified QSPI transfer.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param direction QSPI tansfer direction.
+ */
+void QSPI_StartTransfer(QSPI_Type *base, qspi_transfer_direction_t direction)
+{
+ uint32_t tempVal = 0x00U;
+
+ /* Assert QSPI SS */
+ base->CNTL |= QSPI_CNTL_SS_EN_MASK;
+ /* Wait until QSPI ready */
+ while ((base->CNTL & QSPI_CNTL_XFER_RDY_MASK) == 0x00U)
+ {
+ }
+
+ tempVal = base->CONF;
+ /* Set read/write mode */
+ base->CONF = (tempVal & ~QSPI_CONF_RW_EN_MASK) | QSPI_CONF_RW_EN(direction);
+
+ /* Start QSPI */
+ base->CONF |= QSPI_CONF_XFER_START_MASK;
+}
+
+/*!
+ * @brief Stop QSPI transfer.
+ *
+ * @param base Pointer to QSPI Type.
+ */
+void QSPI_StopTransfer(QSPI_Type *base)
+{
+ /* Wait until QSPI ready */
+ while ((base->CNTL & QSPI_CNTL_XFER_RDY_MASK) == 0x00U)
+ {
+ }
+
+ /* Wait until wfifo empty */
+ while ((base->CNTL & QSPI_CNTL_WFIFO_EMPTY_MASK) == 0x00U)
+ {
+ }
+
+ /* Stop QSPI */
+ base->CONF |= QSPI_CONF_XFER_STOP_MASK;
+
+ /* Wait until QSPI release start signal */
+ while ((base->CONF & QSPI_CONF_XFER_START_MASK) == QSPI_CONF_XFER_START_MASK)
+ {
+ }
+
+ /* De-assert QSPI SS */
+ base->CNTL &= ~QSPI_CNTL_SS_EN_MASK;
+ /* Wait until QSPI ready */
+ while ((base->CNTL & QSPI_CNTL_XFER_RDY_MASK) == 0x00U)
+ {
+ }
+}
+
+/*!
+ * @brief Write a byte to QSPI serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param data data to be written.
+ */
+void QSPI_WriteByte(QSPI_Type *base, uint8_t data)
+{
+ /* Wait unitl WFIFO is not full*/
+ while ((base->CNTL & QSPI_CNTL_WFIFO_FULL_MASK) == QSPI_CNTL_WFIFO_FULL_MASK)
+ {
+ }
+
+ base->DOUT = (data & 0xFFU);
+}
+
+/*!
+ * @brief Read a byte from QSPI serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return byte from QSPI serial interface.
+ */
+uint8_t QSPI_ReadByte(QSPI_Type *base)
+{
+ uint8_t data;
+
+ /* Wait if RFIFO is empty*/
+ while ((base->CNTL & QSPI_CNTL_RFIFO_EMPTY_MASK) == QSPI_CNTL_RFIFO_EMPTY_MASK)
+ {
+ }
+
+ data = (base->DIN & 0xFFU);
+
+ return data;
+}
+
+/*!
+ * @brief Write a word to QSPI serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param word data to be written.
+ */
+void QSPI_WriteWord(QSPI_Type *base, uint32_t data)
+{
+ /* Wait unitl WFIFO is not full*/
+ while ((base->CNTL & QSPI_CNTL_RFIFO_FULL_MASK) == QSPI_CNTL_RFIFO_FULL_MASK)
+ {
+ }
+
+ base->DOUT = data;
+}
+
+/*!
+ * @brief Read a word from QSPI serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return word from QSPI serial interface.
+ */
+uint32_t QSPI_ReadWord(QSPI_Type *base)
+{
+ /* Wait if RFIFO is empty*/
+ while ((base->CNTL & QSPI_CNTL_RFIFO_EMPTY_MASK) == QSPI_CNTL_RFIFO_EMPTY_MASK)
+ {
+ }
+
+ return base->DIN;
+}
+
+/*!
+ * @brief Set DMA tansfer related configuration.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param direction DMA transfer direction, read or write.
+ * @param length DMA burst length, 1/4/8 bytes.
+ */
+void QSPI_SetDmaTransferConfig(QSPI_Type *base, qspi_dma_transfer_direction_t direction, qspi_dma_burst_len_t length)
+{
+ if (direction == kQSPI_DmaRead)
+ {
+ base->CONF2 |= QSPI_CONF2_DMA_RD_EN_MASK;
+ base->CONF2 |= QSPI_CONF2_DMA_RD_BURST(length);
+ }
+ else
+ {
+ base->CONF2 |= QSPI_CONF2_DMA_WR_EN_MASK;
+ base->CONF2 |= QSPI_CONF2_DMA_WR_BURST(length);
+ }
+}
+
+/*!
+ * brief Sends a buffer of data bytes using a blocking method.
+ * note This function blocks via polling until all bytes have been sent.
+ * param base QSPI base pointer
+ * param buffer The data bytes to send
+ * param size The number of data bytes to send
+ */
+void QSPI_WriteBlocking(QSPI_Type *base, uint32_t *buffer, size_t size)
+{
+ assert(size >= 4U);
+
+ uint32_t i = 0;
+
+ for (i = 0; i < size / 4U; i++)
+ {
+ /* Wait unitl WFIFO is not full*/
+ while (0U != (QSPI_GetStatusFlags(base) & (uint32_t)kQSPI_WriteFifoFull))
+ {
+ }
+
+ base->DOUT = *buffer++;
+ }
+}
+
+/*!
+ * brief Receives a buffer of data bytes using a blocking method.
+ *
+ * param base QSPI base pointer
+ * param buffer The data bytes to send
+ * param size The number of data bytes to receive
+ */
+void QSPI_ReadBlocking(QSPI_Type *base, uint32_t *buffer, size_t size)
+{
+ assert(size >= 4U);
+
+ uint32_t i = 0;
+
+ for (i = 0; i < size / 4U; i++)
+ {
+ /* Wait if RFIFO is empty*/
+ while (0U != (QSPI_GetStatusFlags(base) & (uint32_t)kQSPI_ReadFifoEmpty))
+ {
+ }
+
+ buffer[i] = base->DIN;
+ }
+}
diff --git a/drivers/mw320/qspi/fsl_qspi.h b/drivers/mw320/qspi/fsl_qspi.h
new file mode 100644
index 000000000..a923ac2be
--- /dev/null
+++ b/drivers/mw320/qspi/fsl_qspi.h
@@ -0,0 +1,613 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_QSPI_H_
+#define _FSL_QSPI_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup qspi_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief QSPI driver version 2.0.0. */
+#define FSL_QSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @brief QSPI transfer mode */
+typedef enum _qspi_transfer_mode
+{
+ kQSPI_TransferModeSingle, /*!< Use 1 serial interface pin. */
+ kQSPI_TransferModeDual, /*!< Use 2 serial interface pins. */
+ kQSPI_TransferModeQuad, /*!< Use 4 serial interface pins. */
+} qspi_transfer_mode_t;
+
+/*! @brief QSPI data pin */
+typedef enum _qspi_data_pin
+{
+ kQSPI_DataPinSingle, /*!< Use 1 serial interface pin. */
+ kQSPI_DataPinDual, /*!< Use 2 serial interface pins. */
+ kQSPI_DataPinQuad, /*!< Use 4 serial interface pins. */
+} qspi_data_pin_t;
+
+/*! @brief QSPI address pin */
+typedef enum _qspi_addr_pin
+{
+ kQSPI_AddrPinSingle, /*!< Use 1 serial interface pin */
+ kQSPI_AddrPinAsData, /*!< Use the number of pins as indicated in DATA_PIN */
+} qspi_addr_pin_t;
+
+/*! @brief QSPI clock phase */
+typedef enum _qspi_clock_phase
+{
+ kQSPI_ClockPhaseRising, /*!< Data is latched on the rising edge of the serial clock. */
+ kQSPI_ClockPhaseFalling, /*!< Data is latched on the falling edge of the serial clock. */
+} qspi_clock_phase_t;
+
+/*! @brief QSPI clock polarity */
+typedef enum _qspi_clock_polarity
+{
+ kQSPI_ClockPolarityLow, /*!< Inactive state of serial clock is low. */
+ kQSPI_ClockPolarityHigh, /*!< Inactive state of serial clock is high. */
+} qspi_clock_polarity_t;
+
+/*! @brief QSPI capture clock edge */
+typedef enum _qspi_capture_edge
+{
+ kQSPI_CaptureEdgeFirst, /*!< Input data is captured on the first edge of the serial clock */
+ kQSPI_CaptureEdgeSecond, /*!< Input data is captured on the second edge of the serial clock */
+} qspi_capture_edge_t;
+
+/*! @brief QSPI transfer length */
+typedef enum _qspi_transfer_length
+{
+ kQSPI_TransferLength1Byte, /*!< 1 byte in each serial interface I/O transfer */
+ kQSPI_TransferLength4Bytes, /*!< 4 bytes in each serial interface I/O transfer */
+} qspi_transfer_length_t;
+
+/*! @brief QSPI clock prescaler */
+typedef enum _qspi_clock_prescaler
+{
+ kQSPI_ClockDiv1 = 0x1, /*!< Serial interface clock prescaler is SPI clock / 1 */
+ kQSPI_ClockDiv2 = 0x2, /*!< Serial interface clock prescaler is SPI clock / 2 */
+ kQSPI_ClockDiv3 = 0x3, /*!< Serial interface clock prescaler is SPI clock / 3 */
+ kQSPI_ClockDiv4 = 0x4, /*!< Serial interface clock prescaler is SPI clock / 4 */
+ kQSPI_ClockDiv5 = 0x5, /*!< Serial interface clock prescaler is SPI clock / 5 */
+ kQSPI_ClockDiv6 = 0x6, /*!< Serial interface clock prescaler is SPI clock / 6 */
+ kQSPI_ClockDiv7 = 0x7, /*!< Serial interface clock prescaler is SPI clock / 7 */
+ kQSPI_ClockDiv8 = 0x8, /*!< Serial interface clock prescaler is SPI clock / 8 */
+ kQSPI_ClockDiv9 = 0x9, /*!< Serial interface clock prescaler is SPI clock / 9 */
+ kQSPI_ClockDiv10 = 0xA, /*!< Serial interface clock prescaler is SPI clock / 10 */
+ kQSPI_ClockDiv11 = 0xB, /*!< Serial interface clock prescaler is SPI clock / 11 */
+ kQSPI_ClockDiv12 = 0xC, /*!< Serial interface clock prescaler is SPI clock / 12 */
+ kQSPI_ClockDiv13 = 0xD, /*!< Serial interface clock prescaler is SPI clock / 13 */
+ kQSPI_ClockDiv14 = 0xE, /*!< Serial interface clock prescaler is SPI clock / 14 */
+ kQSPI_ClockDiv15 = 0xF, /*!< Serial interface clock prescaler is SPI clock / 15 */
+ kQSPI_ClockDiv16 = 0x18, /*!< Serial interface clock prescaler is SPI clock / 16 */
+ kQSPI_ClockDiv18 = 0x19, /*!< Serial interface clock prescaler is SPI clock / 18 */
+ kQSPI_ClockDiv20 = 0x1A, /*!< Serial interface clock prescaler is SPI clock / 20 */
+ kQSPI_ClockDiv22 = 0x1B, /*!< Serial interface clock prescaler is SPI clock / 22 */
+ kQSPI_ClockDiv24 = 0x1C, /*!< Serial interface clock prescaler is SPI clock / 24 */
+ kQSPI_ClockDiv26 = 0x1D, /*!< Serial interface clock prescaler is SPI clock / 26 */
+ kQSPI_ClockDiv28 = 0x1E, /*!< Serial interface clock prescaler is SPI clock / 28 */
+ kQSPI_ClockDiv30 = 0x1F, /*!< Serial interface clock prescaler is SPI clock / 30 */
+} qspi_clock_prescaler_t;
+
+/*! @brief QSPI read or write type */
+typedef enum _qspi_transfer_direction
+{
+ kQSPI_Read, /*!< Read data from the serial interface */
+ kQSPI_Write, /*!< Write data to the serial interface */
+} qspi_transfer_direction_t;
+
+/*! @brief QSPI status bit, @anchor _qspi_status_flags*/
+enum
+{
+ kQSPI_TransferReady = QSPI_CNTL_XFER_RDY_MASK, /*!< Serial interface transfer ready */
+ kQSPI_ReadFifoEmpty = QSPI_CNTL_RFIFO_EMPTY_MASK, /*!< QSPI read FIFO empty flag */
+ kQSPI_ReadFifoFull = QSPI_CNTL_RFIFO_FULL_MASK, /*!< QSPI read FIFO full flag */
+ kQSPI_WriteFifoEmpty = QSPI_CNTL_WFIFO_EMPTY_MASK, /*!< QSPI write FIFO empty flag */
+ kQSPI_WriteFifoFull = QSPI_CNTL_WFIFO_FULL_MASK, /*!< QSPI write FIFO full flag */
+ kQSPI_ReadFifoUnderflow = QSPI_CNTL_RFIFO_UNDRFLW_MASK, /*!< QSPI read FIFO underflow flag */
+ kQSPI_ReadFifoOverflow = QSPI_CNTL_RFIFO_OVRFLW_MASK, /*!< QSPI read FIFO overflow flag */
+ kQSPI_WriteFifoUnderflow = QSPI_CNTL_WFIFO_UNDRFLW_MASK, /*!< QSPI write FIFO underflow flag */
+ kQSPI_WriteFifoOverflow = QSPI_CNTL_WFIFO_OVERFLW_MASK, /*!< QSPI write FIFO overflow flag */
+};
+
+/*! @brief QSPI interrupt status bit, @anchor _qspi_interrupt_status_flags*/
+enum
+{
+ kQSPI_InterruptTransferDone = QSPI_ISR_XFER_DONE_IS_MASK, /*!< QSPI interrupt transfer done flag */
+ kQSPI_InterruptTransferReady = QSPI_ISR_XFER_RDY_IS_MASK, /*!< QSPI interrupt transfer ready flag */
+ kQSPI_InterruptReadFifoDmaBurst = QSPI_ISR_XFER_RDY_IS_MASK, /*!< QSPI interrupt read FIFO DMA burst flag */
+ kQSPI_InterruptWriteFifoDmaBurst =
+ QSPI_ISR_WFIFO_DMA_BURST_IS_MASK, /*!< QSPI interrupt write FIFO DMA burst flag */
+ kQSPI_InterruptReadFifoEmpty = QSPI_ISR_RFIFO_EMPTY_IS_MASK, /*!< QSPI interrupt read FIFO empty flag */
+ kQSPI_InterruptReadFifoFull = QSPI_ISR_RFIFO_FULL_IS_MASK, /*!< QSPI interrupt read FIFO full flag */
+ kQSPI_InterruptWriteFifoEmpty = QSPI_ISR_WFIFO_EMPTY_IS_MASK, /*!< QSPI interrupt write FIFO empty flag */
+ kQSPI_InterruptWriteFifoFull = QSPI_ISR_WFIFO_FULL_IS_MASK, /*!< QSPI interrupt write FIFO full flag */
+ kQSPI_InterruptReadFifoUnderflow = QSPI_ISR_RFIFO_UNDRFLW_IS_MASK, /*!< QSPI interrupt read FIFO underflow flag */
+ kQSPI_InterruptReadFifoOverflow = QSPI_ISR_RFIFO_OVRFLW_IS_MASK, /*!< QSPI interrupt read FIFO overflow flag */
+ kQSPI_InterruptWriteFifoUnderflow = QSPI_ISR_WFIFO_UNDRFLW_IS_MASK, /*!< QSPI interrupt write FIFO underflow flag */
+ kQSPI_InterruptWriteFifoOverflow = QSPI_ISR_WFIFO_OVRFLW_IS_MASK, /*!< QSPI interrupt write FIFO overflow flag */
+};
+
+/*! @brief QSPI interrupt mask status bit, @anchor _qspi_interrupt_mask_status_flags*/
+enum
+{
+ kQSPI_InterruptTransferDoneMask = QSPI_IMR_XFER_DONE_IM_MASK, /*!< QSPI interrupt transfer done mask flag */
+ kQSPI_InterruptTransferReadyMask = QSPI_IMR_XFER_RDY_IM_MASK, /*!< QSPI interrupt transfer ready mask flag*/
+ kQSPI_InterruptReadFifoDmaBurstMask =
+ QSPI_IMR_XFER_RDY_IM_MASK, /*!< QSPI interrupt read FIFO DMA burst mask flag */
+ kQSPI_InterruptWriteFifoDmaBurstMask =
+ QSPI_IMR_WFIFO_DMA_BURST_IM_MASK, /*!< QSPI interrupt write FIFO DMA burst mask flag */
+ kQSPI_InterruptReadFifoEmptyMask = QSPI_IMR_RFIFO_EMPTY_IM_MASK, /*!< QSPI interrupt read FIFO empty mask flag */
+ kQSPI_InterruptReadFifoFullMask = QSPI_IMR_RFIFO_FULL_IM_MASK, /*!< QSPI interrupt read FIFO full mask flag */
+ kQSPI_InterruptWriteFifoEmptyMask = QSPI_IMR_WFIFO_EMPTY_IM_MASK, /*!< QSPI interrupt write FIFO empty mask flag */
+ kQSPI_InterruptWriteFifoFullMask = QSPI_IMR_WFIFO_FULL_IM_MASK, /*!< QSPI interrupt write FIFO full mask flag */
+ kQSPI_InterruptReadFifoUnderflowMask =
+ QSPI_IMR_RFIFO_UNDRFLW_IM_MASK, /*!< QSPI interrupt read FIFO underflow mask flag */
+ kQSPI_InterruptReadFifoOverflowMask =
+ QSPI_IMR_RFIFO_OVRFLW_IM_MASK, /*!< QSPI interrupt read FIFO overflow mask flag */
+ kQSPI_InterruptWriteFifoUnderflowMask =
+ QSPI_IMR_WFIFO_UNDRFLW_IM_MASK, /*!< QSPI interrupt write FIFO underflow mask flag */
+ kQSPI_InterruptWriteFifoOverflowMask =
+ QSPI_IMR_WFIFO_OVRFLW_IM_MASK, /*!< QSPI interrupt write FIFO overflow mask flag */
+};
+
+/*! @brief QSPI dma read/write type */
+typedef enum _qspi_dma_transfer_direction
+{
+ kQSPI_DmaRead, /*!< QSPI DMA read */
+ kQSPI_DmaWrite, /*!< QSPI DMA write */
+} qspi_dma_transfer_direction_t;
+
+/*! @brief QSPI dma read/write burst type */
+typedef enum _qspi_dma_burst_len
+{
+ kQSPI_BurstLen1, /*!< One data(each of width BYTE_LEN) is available in the Read/Write FIFO before a receive/transmit
+ burst request is made to the DMA */
+ kQSPI_BurstLen4, /*!< Four data(each of width BYTE_LEN) is available in the Read/Write FIFO before a
+ receive/transmit burst request is made to the DMA */
+ kQSPI_BurstLen8, /*!< Eight data(each of width BYTE_LEN) is available in the Read/Write FIFO before a
+ receive/transmit burst request is made to the DMA */
+ kQSPI_BurstLen0, /*!< Disable DMA read/write */
+} qspi_dma_burst_len_t;
+
+/*! @brief QSPI Instruction Count */
+typedef enum _qspi_instruction_count
+{
+ kQSPI_InstructionCnt0Byte, /*!< Instrution count: 0 byte */
+ kQSPI_InstructionCnt1Byte, /*!< Instrution count: 1 byte */
+ kQSPI_InstructionCnt2Byte, /*!< Instrution count: 2 bytes */
+} qspi_instruction_count_t;
+
+/*! @brief QSPI Address Count */
+typedef enum _qspi_address_count
+{
+ kQSPI_AddressCnt0Byte, /*!< Address count: 0 byte */
+ kQSPI_AddressCnt1Byte, /*!< Address count: 1 byte */
+ kQSPI_AddressCnt2Byte, /*!< Address count: 2 bytes */
+ kQSPI_AddressCnt3Byte, /*!< Address count: 3 bytes */
+ kQSPI_AddressCnt4Byte, /*!< Address count: 4 bytes */
+} qspi_address_count_t;
+
+/*! @brief QSPI Read Mode Count */
+typedef enum _qspi_read_mode_count
+{
+ kQSPI_ReadModeCnt0Byte, /*!< Read mode count: 0 byte */
+ kQSPI_ReadModeCnt1Byte, /*!< Read mode count: 1 byte */
+ kQSPI_ReadModeCnt2Byte, /*!< Read mode count: 2 bytes */
+} qspi_read_mode_count_t;
+
+/*! @brief QSPI Dummy Count */
+typedef enum _qspi_dummy_count
+{
+ kQSPI_DummyCnt0Byte, /*!< Dummy count: 0 byte */
+ kQSPI_DummyCnt1Byte, /*!< Dummy count: 1 byte */
+ kQSPI_DummyCnt2Byte, /*!< Dummy count: 2 bytes */
+ kQSPI_DummyCnt3Byte, /*!< Dummy count: 3 bytes */
+} qspi_dummy_count_t;
+
+/*! @brief QSPI header count configuration structure*/
+typedef struct _qspi_header_count_config
+{
+ qspi_instruction_count_t instructionCnt; /*!< Instruction Count, number of bytes in INSTR register to shift out. */
+ qspi_address_count_t addressCnt; /*!< Address Count, number of bytes in ADDR register to shift out. */
+ qspi_read_mode_count_t readModeCnt; /*!< Read Mode Count, number of bytes in RMODE register to shift out. */
+ qspi_dummy_count_t dummyCnt; /*!< Dummy Count, number of bytes as dummy to shift out. */
+} qspi_header_count_config_t;
+
+/*! @brief QSPI configuration structure*/
+typedef struct _qspi_config
+{
+ qspi_clock_prescaler_t preScale; /*!< Serial Interface Clock Prescaler. */
+ qspi_transfer_length_t byteLen; /*!< Byte Length, the number of bytes in each serial interface I/O transfer. */
+ qspi_clock_phase_t clockPhase; /*!< Serial Interface Clock Phase. */
+ qspi_clock_polarity_t clockPolarity; /*!< Serial Interface Clock Polarity. */
+ qspi_data_pin_t dataPinMode; /*!< Data Transfer Pin. */
+ qspi_addr_pin_t addrPinMode; /*!< Address Transfer Pin. */
+ qspi_capture_edge_t captureEdge; /*!< Serial Interface Capture Clock Edge. */
+
+ qspi_header_count_config_t headerCnt; /*!< Serial Interface header count. */
+} qspi_config_t;
+
+/******************************************************************************
+ * API
+ *****************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Get the instance number for QSPI.
+ *
+ * @param base QSPI base pointer.
+ */
+uint32_t QSPI_GetInstance(QSPI_Type *base);
+
+/*!
+ * @brief Initializes the QSPI module and internal state.
+ *
+ * This function enables the clock for QSPI and also configures the QSPI with the
+ * input configure parameters. Users should call this function before any QSPI operations.
+ *
+ * @param base Pointer to QuadSPI Type.
+ * @param config QSPI configure structure.
+ */
+void QSPI_Init(QSPI_Type *base, qspi_config_t *config);
+
+/*!
+ * @brief Gets default settings for QSPI.
+ *
+ * @param config QSPI configuration structure.
+ */
+void QSPI_GetDefaultConfig(qspi_config_t *config);
+
+/*!
+ * @brief Deinitializes the QSPI module.
+ *
+ * @param base Pointer to QuadSPI Type.
+ */
+void QSPI_Deinit(QSPI_Type *base);
+
+/*!
+ * @brief Do software reset QSPI.
+ *
+ * @param base Pointer to QSPI Type.
+ */
+void QSPI_SoftwareReset(QSPI_Type *base);
+
+/*! @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Gets the state value of QSPI.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return status flag, use status flag to AND @ref _qspi_interrupt_mask_status_flags could get the related status.
+ */
+static inline uint32_t QSPI_GetInterruptMaskStatusFlags(QSPI_Type *base)
+{
+ return base->IMR;
+}
+
+/*!
+ * @brief Mask/Unmask specified interrupts.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param mask interrupt mask.
+ */
+static inline void QSPI_MaskInterrupts(QSPI_Type *base, uint32_t mask)
+{
+ base->IMR = mask;
+}
+
+/*!
+ * @brief Get QSPI status flag.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return status flag, use status flag to AND @ref _qspi_status_flags could get the related status.
+ */
+static inline uint32_t QSPI_GetStatusFlags(QSPI_Type *base)
+{
+ return base->CNTL;
+}
+
+/*!
+ * @brief Get interrupt status.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return status flag, use status flag to AND @ref _qspi_interrupt_status_flags could get the related status.
+ */
+static inline uint32_t QSPI_GetInterruptStatus(QSPI_Type *base)
+{
+ return base->ISR;
+}
+
+/*!
+ * @brief Clear transfer done interrupt.
+ *
+ * @param base Pointer to QSPI Type.
+ */
+static inline void QSPI_ClearTransferDoneStatus(QSPI_Type *base)
+{
+ base->ISC = QSPI_ISC_XFER_DONE_IC_MASK;
+}
+
+/*! @} */
+
+/*!
+ * @name QSPI functional interface
+ * @{
+ */
+
+/*!
+ * @brief Flush Write and Read FIFOs.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return return status.
+ */
+status_t QSPI_FlushFIFO(QSPI_Type *base);
+
+/*!
+ * @brief Set QSPI serial interface transfer mode.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param dataPin QSPI tansfer data pin.
+ */
+static inline void QSPI_SetDatePin(QSPI_Type *base, qspi_data_pin_t dataPin)
+{
+ uint32_t tempVal = 0x00U;
+
+ tempVal = base->CONF;
+ base->CONF = (tempVal & ~QSPI_CONF_DATA_PIN_MASK) | QSPI_CONF_DATA_PIN(dataPin);
+}
+
+/*!
+ * @brief Set QSPI serial interface transfer mode.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param addrPin QSPI tansfer address pin.
+ */
+static inline void QSPI_SetAddressPin(QSPI_Type *base, qspi_addr_pin_t addrPin)
+{
+ uint32_t tempVal = 0x00U;
+
+ tempVal = base->CONF;
+ base->CONF = (tempVal & ~QSPI_CONF_ADDR_PIN_MASK) | QSPI_CONF_ADDR_PIN(addrPin);
+}
+
+/*!
+ * @brief Set QSPI serial interface header count .
+ *
+ * @param base Pointer to QSPI Type.
+ * @param config Pointer to header count configuration structure.
+ */
+void QSPI_SetHeaderCount(QSPI_Type *base, qspi_header_count_config_t *config);
+
+/*!
+ * @brief Set number of bytes in INSTR register to shift out to the serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param count number of bytes in INSTR register to shift out.
+ */
+static inline void QSPI_SetInstructionCnt(QSPI_Type *base, qspi_instruction_count_t count)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->HDRCNT;
+ base->HDRCNT = (temp & ~QSPI_HDRCNT_INSTR_CNT_MASK) | QSPI_HDRCNT_INSTR_CNT(count);
+}
+
+/*!
+ * @brief Set number of bytes in ADDR register to shift out to the serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param count number of bytes in ADDR register to shift out.
+ */
+static inline void QSPI_SetAddressCnt(QSPI_Type *base, qspi_address_count_t count)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->HDRCNT;
+ base->HDRCNT = (temp & ~QSPI_HDRCNT_ADDR_CNT_MASK) | QSPI_HDRCNT_ADDR_CNT(count);
+}
+
+/*!
+ * @brief Set number of bytes in RM register to shift out to the serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param count number of bytes in RM register to shift out.
+ */
+static inline void QSPI_SetReadModeCnt(QSPI_Type *base, qspi_read_mode_count_t count)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->HDRCNT;
+ base->HDRCNT = (temp & ~QSPI_HDRCNT_RM_CNT_MASK) | QSPI_HDRCNT_RM_CNT(count);
+}
+
+/*!
+ * @brief Set number of bytes as dummy to shift out to the serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param count number of bytes as dummy to shift out.
+ */
+static inline void QSPI_SetDummyCnt(QSPI_Type *base, qspi_dummy_count_t count)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->HDRCNT;
+ base->HDRCNT = (temp & ~QSPI_HDRCNT_DUMMY_CNT_MASK) | QSPI_HDRCNT_DUMMY_CNT(count);
+}
+
+/*!
+ * @brief Set QSPI serial interface instruction.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param instruction QSPI serial interface instruction.
+ */
+static inline void QSPI_SetInstruction(QSPI_Type *base, uint32_t instruction)
+{
+ base->INSTR = QSPI_INSTR_INSTR(instruction);
+}
+
+/*!
+ * @brief Set QSPI serial interface address.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param address QSPI serial interface address.
+ */
+static inline void QSPI_SetAddress(QSPI_Type *base, uint32_t address)
+{
+ base->ADDR = address;
+}
+
+/*!
+ * @brief Set QSPI serial interface read mode.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param mode QSPI serial interface read mode.
+ */
+static inline void QSPI_SetReadMode(QSPI_Type *base, uint32_t mode)
+{
+ base->RDMODE = QSPI_RDMODE_RMODE(mode);
+}
+
+/*!
+ * @brief Set number of bytes of data to shift in from the serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param count number of bytes of data to shift in.
+ */
+static inline void QSPI_SetDataInCnt(QSPI_Type *base, uint32_t count)
+{
+ base->DINCNT = QSPI_DINCNT_DATA_IN_CNT(count);
+}
+
+/*!
+ * @brief Update the number of bytes in each serial interface I/O transfer.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param length the number of bytes in each serial interface I/O transfer.
+ */
+static inline void QSPI_UpdateTansferLength(QSPI_Type *base, qspi_transfer_length_t length)
+{
+ uint32_t temp = 0x00U;
+
+ temp = base->CONF;
+ base->CONF = (temp & ~QSPI_CONF_BYTE_LEN_MASK) | QSPI_CONF_BYTE_LEN(length);
+}
+
+/*!
+ * @brief Activate or de-activate serial select output.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param enable enable or disable.
+ */
+void QSPI_SetSSEnable(QSPI_Type *base, bool enable);
+
+/*!
+ * @brief Start the specified QSPI transfer.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param direction QSPI tansfer direction.
+ */
+void QSPI_StartTransfer(QSPI_Type *base, qspi_transfer_direction_t direction);
+
+/*!
+ * @brief Stop QSPI transfer.
+ *
+ * @param base Pointer to QSPI Type.
+ */
+void QSPI_StopTransfer(QSPI_Type *base);
+
+/*!
+ * @brief Write a byte to QSPI serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param data data to be written.
+ */
+void QSPI_WriteByte(QSPI_Type *base, uint8_t data);
+
+/*!
+ * @brief Read a byte from QSPI serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return byte from QSPI serial interface.
+ */
+uint8_t QSPI_ReadByte(QSPI_Type *base);
+
+/*!
+ * @brief Write a word to QSPI serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param word data to be written.
+ */
+void QSPI_WriteWord(QSPI_Type *base, uint32_t word);
+
+/*!
+ * @brief Read a word from QSPI serial interface.
+ *
+ * @param base Pointer to QSPI Type.
+ * @return word from QSPI serial interface.
+ */
+uint32_t QSPI_ReadWord(QSPI_Type *base);
+
+/*!
+ * @brief Set DMA tansfer related configuration.
+ *
+ * @param base Pointer to QSPI Type.
+ * @param direction DMA transfer direction, read or write.
+ * @param length DMA burst length, 1/4/8 bytes.
+ */
+void QSPI_SetDmaTransferConfig(QSPI_Type *base, qspi_dma_transfer_direction_t direction, qspi_dma_burst_len_t length);
+
+/*!
+ * @brief Sends a buffer of data bytes using a blocking method.
+ * @note This function blocks via polling until all bytes have been sent.
+ * @param base QSPI base pointer
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to send
+ */
+void QSPI_WriteBlocking(QSPI_Type *base, uint32_t *buffer, size_t size);
+
+/*!
+ * @brief Receives a buffer of data bytes using a blocking method.
+ *
+ * @param base QSPI base pointer
+ * @param buffer The data bytes to send
+ * @param size The number of data bytes to receive
+ */
+void QSPI_ReadBlocking(QSPI_Type *base, uint32_t *buffer, size_t size);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/* @}*/
+
+#endif /* _FSL_QSPI_H_*/
diff --git a/drivers/mw320/rtc/driver_mw_rtc.cmake b/drivers/mw320/rtc/driver_mw_rtc.cmake
new file mode 100644
index 000000000..e02a77b9e
--- /dev/null
+++ b/drivers/mw320/rtc/driver_mw_rtc.cmake
@@ -0,0 +1,14 @@
+#Description: MW_RTC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_rtc component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_rtc.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/rtc/fsl_rtc.c b/drivers/mw320/rtc/fsl_rtc.c
new file mode 100644
index 000000000..cc799f2e0
--- /dev/null
+++ b/drivers/mw320/rtc/fsl_rtc.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_rtc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.rtc"
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * @brief Ungates the RTC clock and configures the peripheral for basic operation.
+ *
+ * This function configures the RTC only if the counter is not running.
+ *
+ * @note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * @param base RTC peripheral base address
+ * @param config Pointer to the user's RTC configuration structure.
+ */
+void RTC_Init(RTC_Type *base, const rtc_config_t *config)
+{
+ bool running;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ CLOCK_EnableClock(kCLOCK_Rtc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+ running = ((base->CNT_EN_REG & RTC_CNT_EN_REG_CNT_RUN_MASK) != 0U);
+ if (running && (!config->ignoreInRunning))
+ {
+ RTC_StopTimer(base);
+ }
+
+ /* Reconfigure the RTC if it's not running. */
+ if ((base->CNT_EN_REG & RTC_CNT_EN_REG_CNT_RUN_MASK) == 0U)
+ {
+ /* Ensure RTC reset is deasserted */
+ while ((base->CNT_EN_REG & RTC_CNT_EN_REG_STS_RESETN_MASK) == 0U)
+ {
+ }
+ base->CNT_CNTL_REG =
+ (config->stopCntInDebug ? RTC_CNT_CNTL_REG_CNT_DBG_ACT(0U) : RTC_CNT_CNTL_REG_CNT_DBG_ACT(1U)) |
+ (config->autoUpdateCntVal ? RTC_CNT_CNTL_REG_CNT_UPDT_MOD(2U) : RTC_CNT_CNTL_REG_CNT_UPDT_MOD(0U));
+ base->CLK_CNTL_REG = RTC_CLK_CNTL_REG_CLK_DIV(config->clkDiv);
+ base->CNT_UPP_VAL_REG = config->cntUppVal;
+ /* Reset counter */
+ RTC_ResetTimer(base);
+ }
+}
+
+/*!
+ * @brief Stops the timer and gate the RTC clock.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_Deinit(RTC_Type *base)
+{
+ RTC_StopTimer(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ CLOCK_DisableClock(kCLOCK_Rtc);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * @brief Fills in the RTC config struct with the default settings.
+ *
+ * The default values are as follows.
+ * @code
+ * config->ignoreInRunning = false;
+ * config->autoUpdateCntVal = true;
+ * config->stopCntInDebug = true;
+ * config->clkDiv = kRTC_ClockDiv32;
+ * config->cntUppVal = 0xFFFFFFFFU;
+ * @endcode
+ * @param config Pointer to the user's RTC configuration structure.
+ */
+void RTC_GetDefaultConfig(rtc_config_t *config)
+{
+ assert(NULL != config);
+
+ /* Initializes the configure structure to zero. */
+ (void)memset(config, 0, sizeof(*config));
+
+ /* Force update of the configuration even if the counter is running. */
+ config->ignoreInRunning = false;
+ /* Enable CNT_VAL_REG update for counter read. */
+ config->autoUpdateCntVal = true;
+ /* Stop the counter in debug mode. */
+ config->stopCntInDebug = true;
+ /* Use 1.024KHz clock for counter. */
+ config->clkDiv = kRTC_ClockDiv32;
+ /* Use 32bit full range for counter. */
+ config->cntUppVal = 0xFFFFFFFFU;
+}
+
+/*!
+ * @brief Gets current RTC counter value.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return counter value in RTC.
+ */
+uint32_t RTC_GetCounter(RTC_Type *base)
+{
+ /* To get counter, autoUpdateCntVal must be configured to true. */
+ assert((base->CNT_CNTL_REG & RTC_CNT_CNTL_REG_CNT_UPDT_MOD_MASK) == RTC_CNT_CNTL_REG_CNT_UPDT_MOD(2U));
+ return base->CNT_VAL_REG;
+}
+
+/*!
+ * @brief Sets the RTC alarm time.
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param base RTC peripheral base address
+ * @param alarmCnt Counter value to trigger the alarm.
+ *
+ * @return kStatus_Success: success in setting the RTC alarm
+ * kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, uint32_t alarmCnt)
+{
+ status_t status;
+
+ /* If we can get the counter value, validate the alarm value. */
+ if (((base->CNT_CNTL_REG & RTC_CNT_CNTL_REG_CNT_UPDT_MOD_MASK) == RTC_CNT_CNTL_REG_CNT_UPDT_MOD(2U)) &&
+ alarmCnt <= base->CNT_VAL_REG)
+ {
+ status = kStatus_Fail;
+ }
+ else
+ {
+ base->CNT_ALARM_VAL_REG = alarmCnt;
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * @brief Returns the RTC alarm counter value.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return Alarm counter value in RTC.
+ */
+uint32_t RTC_GetAlarm(RTC_Type *base)
+{
+ return base->CNT_ALARM_VAL_REG;
+}
+
+/*!
+ * brief Enables the selected RTC interrupts.
+ *
+ * param base RTC peripheral base address
+ * param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
+{
+ base->INT_MSK_REG &= ~(mask & ((uint32_t)kRTC_AllInterruptsEnable));
+}
+
+/*!
+ * brief Disables the selected RTC interrupts.
+ *
+ * param base RTC peripheral base address
+ * param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
+{
+ base->INT_MSK_REG |= (mask & ((uint32_t)kRTC_AllInterruptsEnable));
+}
+
+/*!
+ * brief Gets the enabled RTC interrupts.
+ *
+ * param base RTC peripheral base address
+ *
+ * return The enabled interrupts. This is the logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
+{
+ return (~base->INT_MSK_REG) & ((uint32_t)kRTC_AllInterruptsEnable);
+}
+
+/*!
+ * brief Gets the RTC status flags.
+ *
+ * param base RTC peripheral base address
+ *
+ * return The status flags. This is the logical OR of members of the
+ * enumeration ::rtc_status_flags_t
+ */
+uint32_t RTC_GetStatusFlags(RTC_Type *base)
+{
+ uint32_t tmp32 = (base->CNT_EN_REG >> RTC_CNT_EN_REG_CNT_RUN_SHIFT) & ((uint32_t)kRTC_AllNonClearableFlags);
+
+ tmp32 |= (base->INT_RAW_REG & ((uint32_t)kRTC_AllClearableFlags));
+
+ return tmp32;
+}
+
+/*!
+ * brief Clears the RTC status flags.
+ *
+ * param base RTC peripheral base address
+ * param mask The status flags to clear. This is a logical OR of members of the
+ * enumeration ::rtc_status_flags_t
+ */
+void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
+{
+ base->INT_RAW_REG = mask & ((uint32_t)kRTC_AllClearableFlags);
+}
+
+/*!
+ * @brief Starts the RTC time counter.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_StartTimer(RTC_Type *base)
+{
+ if ((base->CNT_EN_REG & RTC_CNT_EN_REG_CNT_RUN_MASK) == 0U)
+ {
+ base->CNT_EN_REG = RTC_CNT_EN_REG_CNT_START_MASK;
+ while ((base->CNT_EN_REG & RTC_CNT_EN_REG_CNT_RUN_MASK) == 0U)
+ {
+ }
+ }
+}
+
+/*!
+ * @brief Stops the RTC time counter.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_StopTimer(RTC_Type *base)
+{
+ if ((base->CNT_EN_REG & RTC_CNT_EN_REG_CNT_RUN_MASK) != 0U)
+ {
+ base->CNT_EN_REG = RTC_CNT_EN_REG_CNT_STOP_MASK;
+ while ((base->CNT_EN_REG & RTC_CNT_EN_REG_CNT_RUN_MASK) != 0U)
+ {
+ }
+ }
+}
+
+/*!
+ * @brief Performs a counter reset on the RTC module.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_ResetTimer(RTC_Type *base)
+{
+ uint32_t i;
+
+ /* If user calls RTC_ResetTimer() continously in short time, write reset bit cannot work well.
+ * Need a loop to redo the reset operation until it takes effect. */
+ do
+ {
+ /* Reset counter */
+ base->CNT_EN_REG = RTC_CNT_EN_REG_CNT_RESET_MASK;
+
+ for (i = 0U; (i < 10000U) && ((base->CNT_EN_REG & RTC_CNT_EN_REG_CNT_RST_DONE_MASK) == 0U); i++)
+ {
+ }
+ } while ((base->CNT_EN_REG & RTC_CNT_EN_REG_CNT_RST_DONE_MASK) == 0U);
+}
diff --git a/drivers/mw320/rtc/fsl_rtc.h b/drivers/mw320/rtc/fsl_rtc.h
new file mode 100644
index 000000000..5f4bcd0f7
--- /dev/null
+++ b/drivers/mw320/rtc/fsl_rtc.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_RTC_H_
+#define _FSL_RTC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rtc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of RTC interrupts */
+typedef enum _rtc_interrupt_enable
+{
+ kRTC_AlarmInterruptEnable = (1U << 15U), /*!< Alarm interrupt. */
+ kRTC_TimeOverflowInterruptEnable = (1U << 16U), /*!< Time overflow interrupt. */
+ kRTC_AllInterruptsEnable = (3U << 15U), /*!< All interrupts to enable. */
+} rtc_interrupt_enable_t;
+
+/*! @brief List of RTC flags */
+typedef enum _rtc_status_flags
+{
+ kRTC_CntRunFlag = (1U << 0U), /*!< Counter reset done flag */
+ kRTC_CntRstDoneFlag = (1U << 1U), /*!< Counter reset done flag */
+ kRTC_ResetFlag = (1U << 2U), /*!< Module reset flag */
+ kRTC_AlarmFlag = (1U << 15U), /*!< Alarm flag */
+ kRTC_TimeOverflowFlag = (1U << 16U), /*!< Time overflow flag */
+ kRTC_AllNonClearableFlags = (7U << 0U), /*!< All non-clearable flags */
+ kRTC_AllClearableFlags = (3U << 15U), /*!< All clearable flags */
+} rtc_status_flags_t;
+
+/*! @brief List of clock divider */
+typedef enum _rtc_clock_div
+{
+ kRTC_ClockDiv1 = 0U, /*!< Clock divider 1 */
+ kRTC_ClockDiv2 = 1U, /*!< Clock divider 2 */
+ kRTC_ClockDiv4 = 2U, /*!< Clock divider 4 */
+ kRTC_ClockDiv8 = 3U, /*!< Clock divider 8 */
+ kRTC_ClockDiv16 = 4U, /*!< Clock divider 16 */
+ kRTC_ClockDiv32 = 5U, /*!< Clock divider 32 */
+ kRTC_ClockDiv64 = 6U, /*!< Clock divider 64 */
+ kRTC_ClockDiv128 = 7U, /*!< Clock divider 128 */
+ kRTC_ClockDiv256 = 8U, /*!< Clock divider 256 */
+ kRTC_ClockDiv512 = 9U, /*!< Clock divider 512 */
+ kRTC_ClockDiv1024 = 10U, /*!< Clock divider 1024 */
+ kRTC_ClockDiv2048 = 11U, /*!< Clock divider 2048 */
+ kRTC_ClockDiv4096 = 12U, /*!< Clock divider 4096 */
+ kRTC_ClockDiv8192 = 13U, /*!< Clock divider 8192 */
+ kRTC_ClockDiv16384 = 14U, /*!< Clock divider 16384 */
+ kRTC_ClockDiv32768 = 15U, /*!< Clock divider 32768 */
+} rtc_clock_div_t;
+
+/*!
+ * @brief RTC config structure
+ *
+ * This structure holds the configuration settings for the RTC peripheral. To initialize this
+ * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _rtc_config
+{
+ bool ignoreInRunning; /*!< true: If the counter is already running, the configuration will be ignored.
+ false: Counter will always be reset and the the configurations will always be set. */
+ bool autoUpdateCntVal; /*!< true: CNT_VAL is updated on every counter clock tick.
+ false: CNT_VAL is not updated. */
+ bool stopCntInDebug; /*!< true: In debug mode, stop the counters.
+ false: In debug mode, counters are not affected. */
+ rtc_clock_div_t clkDiv; /*!< Counter clock divider. */
+ uint32_t cntUppVal; /*!< If counter reaches this value, the counter will overflow to 0. */
+} rtc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RTC clock and configures the peripheral for basic operation.
+ *
+ * This function configures the RTC only if the counter is not running.
+ *
+ * @note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * @param base RTC peripheral base address
+ * @param config Pointer to the user's RTC configuration structure.
+ */
+void RTC_Init(RTC_Type *base, const rtc_config_t *config);
+
+/*!
+ * @brief Stops the timer and gate the RTC clock.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_Deinit(RTC_Type *base);
+
+/*!
+ * @brief Fills in the RTC config struct with the default settings.
+ *
+ * The default values are as follows.
+ * @code
+ * config->ignoreInRunning = true;
+ * config->autoUpdateCntVal = true;
+ * config->stopCntInDebug = true;
+ * config->clkDiv = kRTC_ClockDiv32;
+ * config->cntUppVal = 0xFFFFFFFFU;
+ * @endcode
+ * @param config Pointer to the user's RTC configuration structure.
+ */
+void RTC_GetDefaultConfig(rtc_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Current Time & Alarm
+ * @{
+ */
+
+/*!
+ * @brief Gets current RTC counter value.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return counter value in RTC.
+ */
+uint32_t RTC_GetCounter(RTC_Type *base);
+
+/*!
+ * @brief Sets the RTC alarm time.
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param base RTC peripheral base address
+ * @param alarmCnt Counter value to trigger the alarm.
+ *
+ * @return kStatus_Success: success in setting the RTC alarm
+ * kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, uint32_t alarmCnt);
+
+/*!
+ * @brief Returns the RTC alarm counter value.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return Alarm counter value in RTC.
+ */
+uint32_t RTC_GetAlarm(RTC_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Disables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask);
+
+/*!
+ * @brief Gets the enabled RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+uint32_t RTC_GetEnabledInterrupts(RTC_Type *base);
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ * enumeration ::rtc_status_flags_t
+ */
+uint32_t RTC_GetStatusFlags(RTC_Type *base);
+
+/*!
+ * @brief Clears the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ * enumeration ::rtc_status_flags_t
+ */
+void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask);
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the RTC time counter.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_StartTimer(RTC_Type *base);
+
+/*!
+ * @brief Stops the RTC time counter.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_StopTimer(RTC_Type *base);
+
+/*!
+ * @brief Performs a counter reset on the RTC module.
+ *
+ * @param base RTC peripheral base address
+ */
+void RTC_ResetTimer(RTC_Type *base);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_RTC_H_ */
diff --git a/drivers/mw320/sdioc/driver_mw_sdioc.cmake b/drivers/mw320/sdioc/driver_mw_sdioc.cmake
new file mode 100644
index 000000000..a13739bf3
--- /dev/null
+++ b/drivers/mw320/sdioc/driver_mw_sdioc.cmake
@@ -0,0 +1,14 @@
+#Description: MW_SDIOC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_sdioc component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_sdioc.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/sdioc/fsl_sdioc.c b/drivers/mw320/sdioc/fsl_sdioc.c
new file mode 100644
index 000000000..5304bbc25
--- /dev/null
+++ b/drivers/mw320/sdioc/fsl_sdioc.c
@@ -0,0 +1,419 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_sdioc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Typedef for interrupt handler. */
+typedef void (*sdioc_isr_t)(sdioc_handle_t *handle);
+/*! @brief check flag avalibility */
+#define IS_SDIOC_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL)
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief SDIOC base pointer array */
+static SDIOC_Type *const s_sdiocBase[] = SDIOC_BASE_PTRS;
+
+/*! @brief SDIOC internal handle pointer array */
+static sdioc_handle_t *s_sdiocHandle[ARRAY_SIZE(s_sdiocBase)] = {NULL};
+
+/*! @brief SDIOC IRQ name array */
+static const IRQn_Type s_sdiocIRQ[] = SDIOC_IRQS;
+
+/* SDIOC ISR for transactional APIs. */
+static sdioc_isr_t s_sdiocIsr;
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t SDIOC_GetInstance(SDIOC_Type *base)
+{
+ uint8_t instance = 0;
+
+ while ((instance < ARRAY_SIZE(s_sdiocBase)) && (s_sdiocBase[instance] != base))
+ {
+ instance++;
+ }
+
+ assert(instance < ARRAY_SIZE(s_sdiocBase));
+
+ return instance;
+}
+
+/*!
+ * brief Transfer parameters command/data/dma configurations.
+ *
+ * param base SDIOC base address.
+ * param command Transfer command pointer, application should not pass NULL pointer to this parameter.
+ * param data Transfer data pointer, application can pass NULL when send command only.
+ * param dmaConfig Internal dma configurations, application can pass NULL when dma is not used.
+ *
+ * retval #kStatus_InvalidArgument Argument is invalid.
+ * retval #kStatus_Success Operate successfully.
+ */
+
+status_t SDIOC_SetTransferConfig(SDIOC_Type *base,
+ sdioc_command_t *command,
+ sdioc_data_t *data,
+ sdioc_dma_config_t *dmaConfig)
+{
+ uint32_t xferReg = 0U;
+ uint32_t blockCountReg = 0U;
+ status_t error = kStatus_Success;
+
+ if (command == NULL)
+ {
+ error = kStatus_InvalidArgument;
+ }
+ else
+ {
+ /* command index/type/response type configuration */
+ xferReg |= command->commandResponseType | SDIOC_MM4_CMD_XFRMD_CMD_TYPE(command->commandType) |
+ SDIOC_MM4_CMD_XFRMD_CMD_IDX(command->commandIndex);
+
+ /* data configuration */
+ if (data != NULL)
+ {
+ blockCountReg = base->MM4_BLK_CNTL & ~(SDIOC_MM4_BLK_CNTL_XFR_BLKSZ_MASK |
+ SDIOC_MM4_BLK_CNTL_DMA_BUFSZ_MASK | SDIOC_MM4_BLK_CNTL_BLK_CNT_MASK);
+ xferReg |= SDIOC_MM4_CMD_XFRMD_DXFRDIR(data->dataTxAddr != NULL ? 0U : 1U);
+
+ xferReg |= SDIOC_MM4_CMD_XFRMD_DPSEL_MASK;
+
+ if (data->dataEnableAutoCommand12)
+ {
+ xferReg |= SDIOC_MM4_CMD_XFRMD_AUTOCMD12_MASK;
+ }
+
+ if (dmaConfig != NULL)
+ {
+ xferReg |= SDIOC_MM4_CMD_XFRMD_DMA_EN_MASK;
+ blockCountReg |= SDIOC_MM4_BLK_CNTL_DMA_BUFSZ(dmaConfig->dmaBufferBoundary);
+ }
+
+ if (data->dataBlockCount > 1U)
+ {
+ xferReg |= SDIOC_MM4_CMD_XFRMD_MS_BLKSEL_MASK | SDIOC_MM4_CMD_XFRMD_BLKCNTEN_MASK;
+ }
+
+ blockCountReg |=
+ SDIOC_MM4_BLK_CNTL_BLK_CNT(data->dataBlockCount) | SDIOC_MM4_BLK_CNTL_XFR_BLKSZ(data->dataBlockSize);
+
+ base->MM4_SYSADDR = data->dataTxAddr != NULL ? (uint32_t)data->dataTxAddr : (uint32_t)data->dataRxAddr;
+ }
+
+ base->MM4_BLK_CNTL = blockCountReg;
+ base->MM4_ARG = command->commandArgument;
+ base->MM4_CMD_XFRMD = xferReg;
+ }
+
+ return error;
+}
+
+/*!
+ * brief SDIOC module initialization function.
+ *
+ * Configures the SDIOC according to the user configuration.
+ *
+ * Example:
+ code
+ sdioc_config_t config;
+ config.busVoltage = kSDIOC_BusVoltage_3V3;
+ config.dataTimeout = kSDIOC_DataTimeoutValue14;
+ SDIOC_Init(SDIOC, &config);
+ endcode
+ *
+ * param base SDIOC peripheral base address.
+ * param config SDIOC configuration information.
+ * retval #kStatus_Success Operate successfully.
+ */
+void SDIOC_Init(SDIOC_Type *base, const sdioc_config_t *config)
+{
+ assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable SDIOC clock. */
+ CLOCK_EnableClock(kCLOCK_Sdio);
+ CLOCK_EnableClock(kCLOCK_SdioAhb);
+#endif
+ /* reset command and data line */
+ SDIOC_ResetCommandLine(base);
+ SDIOC_ResetDataLine(base);
+
+ /* enable internal/card clock */
+ SDIOC_EnableCardClock(base, true);
+ SDIOC_EnableInternalClock(base, true);
+
+ /* set sdio bus voltage */
+ SDIOC_SetBusVoltage(base, config->busVoltage);
+ /* set data timeout value */
+ SDIOC_SetDataTimeout(base, config->dataTimeout);
+}
+
+/*!
+ * brief Deinitializes the SDIOC.
+ *
+ * param base SDIOC peripheral base address.
+ */
+void SDIOC_Deinit(SDIOC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Disable clock. */
+ CLOCK_DisableClock(kCLOCK_Sdio);
+ CLOCK_DisableClock(kCLOCK_SdioAhb);
+#endif
+}
+
+static status_t SDIOC_ReceiveCommandResponse(SDIOC_Type *base, sdioc_command_t *command)
+{
+ assert(command != NULL);
+
+ uint32_t response0 = SDIOC_ReadCommandResponse(base, kSDIOC_ResponseIndex0);
+ uint32_t response1 = SDIOC_ReadCommandResponse(base, kSDIOC_ResponseIndex1);
+ uint32_t response2 = SDIOC_ReadCommandResponse(base, kSDIOC_ResponseIndex2);
+
+ if (command->commandResponseType != kSDIOC_CommandNoResponse)
+ {
+ command->commandResponse[0U] = response0;
+ if (command->commandResponseType == kSDIOC_CommandResponseLen136BitsCheckCrc)
+ {
+ /* R3-R2-R1-R0(lowest 8 bit is invalid bit) has the same format as R2 format in SD specification document
+ after removed internal CRC7 and end bit. */
+ command->commandResponse[0U] <<= 8U;
+ command->commandResponse[1U] = (response1 << 8U) | ((response0 & 0xFF000000U) >> 24U);
+ command->commandResponse[2U] = (response2 << 8U) | ((response1 & 0xFF000000U) >> 24U);
+ command->commandResponse[3U] =
+ (SDIOC_ReadCommandResponse(base, kSDIOC_ResponseIndex3) << 8U) | ((response2 & 0xFF000000U) >> 24U);
+ }
+ }
+
+ /* check response error flag */
+ if ((command->commandResponseErrorFlags != 0U) &&
+ ((command->commandResponseType == kSDIOC_CommandResponseLen48Bits) ||
+ (command->commandResponseType == kSDIOC_CommandResponseLen48BitsCheckCrcIndex) ||
+ (command->commandResponseType == kSDIOC_CommandResponseLen48BitsWithCheckBusyCrcIndex)))
+ {
+ if ((command->commandResponseErrorFlags & command->commandResponse[0U]) != 0U)
+ {
+ return kStatus_SDIOC_TransferCommandResponseError;
+ }
+ }
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Creates the SDIOC handle.
+ *
+ * param base SDIOC peripheral base address.
+ * param handle SDIOC handle pointer.
+ * param callback Structure pointer to contain all callback functions.
+ * param userData Callback function parameter.
+ */
+void SDIOC_TransferCreateHandle(SDIOC_Type *base, sdioc_handle_t *handle, sdioc_callback_t *callback, void *userData)
+{
+ assert(handle != NULL);
+ assert(callback != NULL);
+
+ /* Zero the handle. */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ handle->base = base;
+
+ /* Set the callback. */
+ handle->callback.transferCallback = callback->transferCallback;
+ handle->callback.cardIntCallback = callback->cardIntCallback;
+ handle->callback.cardDetectCallback = callback->cardDetectCallback;
+ handle->userData = userData;
+
+ /* Save the handle in global variables to support the double weak mechanism. */
+ s_sdiocHandle[SDIOC_GetInstance(base)] = handle;
+
+ /* save IRQ handler */
+ s_sdiocIsr = SDIOC_TransferHandleIRQ;
+
+ (void)EnableIRQ(s_sdiocIRQ[SDIOC_GetInstance(base)]);
+}
+
+/*!
+ * brief Transfers the command/data using an interrupt and an asynchronous method.
+ *
+ * This function sends a command and data and returns immediately. It doesn't wait for the transfer to complete or
+ * to encounter an error. The application must not call this API in multiple threads at the same time. Because of that
+ * this API doesn't support the re-entry mechanism.
+ *
+ * This function transfer data through SDIOC internal DMA.
+ *
+ * note Call API @ref SDIOC_TransferCreateHandle when calling this API.
+ *
+ * param handle SDIOC handle.
+ * param command Transfer command.
+ * param data Transfer data.
+ * param dmaConfig Internal dma configurations.
+ * retval #kStatus_InvalidArgument Argument is invalid.
+ * retval #kStatus_SDIOC_BusyTransferring Busy transferring.
+ * retval #kStatus_Success Operate successfully.
+ */
+status_t SDIOC_TransferDMANonBlocking(sdioc_handle_t *handle,
+ sdioc_command_t *command,
+ sdioc_data_t *data,
+ sdioc_dma_config_t *dmaConfig)
+{
+ status_t error = kStatus_Success;
+
+ if ((handle == NULL) || (command == NULL) || (dmaConfig == NULL))
+ {
+ error = kStatus_InvalidArgument;
+ }
+ else
+ {
+ if ((SDIOC_GetPresentStatus(handle->base) & (uint32_t)kSDIOC_PresentStatusCommandInhibit) != 0U)
+ {
+ return kStatus_SDIOC_BusyTransferring;
+ }
+
+ handle->command = command;
+
+ if (data == NULL)
+ {
+ SDIOC_ClearInterruptStatus(handle->base, kSDIOC_InterruptCommandFlag);
+ SDIOC_EnableInterruptStatus(handle->base, kSDIOC_InterruptCommandFlag, true);
+ SDIOC_EnableInterruptSignal(handle->base, kSDIOC_InterruptCommandFlag, true);
+ }
+ else
+ {
+ if ((SDIOC_GetPresentStatus(handle->base) & (uint32_t)kSDIOC_PresentStatusDataInhibit) != 0U)
+ {
+ return kStatus_SDIOC_BusyTransferring;
+ }
+
+ SDIOC_ClearInterruptStatus(handle->base, kSDIOC_InterruptCommandAndDataFlag);
+ SDIOC_EnableInterruptStatus(handle->base, kSDIOC_InterruptCommandAndDataFlag, true);
+ SDIOC_EnableInterruptSignal(handle->base, kSDIOC_InterruptCommandAndDataFlag, true);
+
+ handle->data = data;
+ }
+ }
+
+ /* transfer configurations */
+ if (error == kStatus_Success)
+ {
+ error = SDIOC_SetTransferConfig(handle->base, command, data, dmaConfig);
+ }
+
+ return error;
+}
+
+static void SDIOC_TransferHandleCardDetect(sdioc_handle_t *handle, uint32_t interruptFlags)
+{
+ if (handle->callback.cardDetectCallback != NULL)
+ {
+ handle->callback.cardDetectCallback(
+ handle, (interruptFlags & (uint32_t)kSDIOC_InterruptCardInsertedFlag) != 0U ? true : false,
+ handle->userData);
+ }
+}
+
+static void SDIOC_TransferHandleCommand(sdioc_handle_t *handle, uint32_t interruptFlags)
+{
+ status_t transferStatus = kStatus_SDIOC_TransferCommandSuccess;
+
+ if (handle->command != NULL)
+ {
+ if ((interruptFlags & kSDIOC_InterruptCommandErrorFlag) != 0U)
+ {
+ transferStatus = kStatus_SDIOC_TransferCommandFail;
+ }
+ else
+ {
+ if (kStatus_Success != SDIOC_ReceiveCommandResponse(handle->base, handle->command))
+ {
+ transferStatus = kStatus_SDIOC_TransferCommandResponseError;
+ }
+ }
+ if (handle->callback.transferCallback != NULL)
+ {
+ handle->callback.transferCallback(handle, transferStatus, handle->userData);
+ }
+
+ handle->command = NULL;
+ }
+ /* disable command interrupt signal */
+ SDIOC_EnableInterruptSignal(handle->base, kSDIOC_InterruptCommandFlag, false);
+}
+
+static void SDIOC_TransferHandleData(sdioc_handle_t *handle, uint32_t interruptFlags)
+{
+ if (handle->data != NULL)
+ {
+ if (handle->callback.transferCallback != NULL)
+ {
+ handle->callback.transferCallback(handle,
+ (interruptFlags & (uint32_t)kSDIOC_InterruptDataErrorFlag) != 0U ?
+ kStatus_SDIOC_TransferDataFail :
+ kStatus_SDIOC_TransferDataSuccess,
+ handle->userData);
+ }
+
+ handle->data = NULL;
+ }
+
+ /* disable data interrupt signal */
+ SDIOC_EnableInterruptSignal(handle->base, kSDIOC_InterruptDataFlag, false);
+}
+
+static void SDIOC_TransferHandleCardInterrupt(sdioc_handle_t *handle)
+{
+ if (handle->callback.cardIntCallback != NULL)
+ {
+ handle->callback.cardIntCallback(handle, handle->userData);
+ }
+}
+
+/*!
+ * brief IRQ handler for the SDIOC.
+ *
+ * This function deals with the IRQs on the given host controller.
+ *
+ * param handle SDIOC handle.
+ */
+void SDIOC_TransferHandleIRQ(sdioc_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ uint32_t interruptFlags = SDIOC_GetEnabledInterruptStatus(handle->base);
+ SDIOC_ClearInterruptStatus(handle->base, interruptFlags);
+
+ if (IS_SDIOC_FLAG_SET(interruptFlags, kSDIOC_InterruptCardDetectFlag))
+ {
+ SDIOC_TransferHandleCardDetect(handle, interruptFlags);
+ }
+ if (IS_SDIOC_FLAG_SET(interruptFlags, kSDIOC_InterruptCommandFlag))
+ {
+ SDIOC_TransferHandleCommand(handle, interruptFlags);
+ }
+ if (IS_SDIOC_FLAG_SET(interruptFlags, kSDIOC_InterruptDataFlag))
+ {
+ SDIOC_TransferHandleData(handle, interruptFlags);
+ }
+ if (IS_SDIOC_FLAG_SET(interruptFlags, kSDIOC_InterruptCardInterruptFlag))
+ {
+ SDIOC_TransferHandleCardInterrupt(handle);
+ }
+}
+
+#ifdef SDIOC
+void SDIO_DriverIRQHandler(void)
+{
+ s_sdiocIsr(s_sdiocHandle[0U]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/drivers/mw320/sdioc/fsl_sdioc.h b/drivers/mw320/sdioc/fsl_sdioc.h
new file mode 100644
index 000000000..8d9ae8d1f
--- /dev/null
+++ b/drivers/mw320/sdioc/fsl_sdioc.h
@@ -0,0 +1,767 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_SDIOC_H_
+#define _FSL_SDIOC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sdioc
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.1. */
+#define FSL_SDIOC_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+
+/*! @brief SDIOC transfer status. */
+enum
+{
+ kStatus_SDIOC_BusyTransferring = MAKE_STATUS(kStatusGroup_SDIOC, 0U), /*!< Transfer is on-going. */
+ kStatus_SDIOC_TransferCommandSuccess = MAKE_STATUS(kStatusGroup_SDIOC, 1U), /*!< Transfer command success. */
+ kStatus_SDIOC_TransferCommandFail = MAKE_STATUS(kStatusGroup_SDIOC, 2U), /*!< Transfer command fail. */
+ kStatus_SDIOC_TransferCommandResponseError =
+ MAKE_STATUS(kStatusGroup_SDIOC, 3U), /*!< Transfer command response error . */
+ kStatus_SDIOC_TransferDataFail = MAKE_STATUS(kStatusGroup_SDIOC, 4U), /*!< Transfer data fail. */
+ kStatus_SDIOC_TransferDataSuccess = MAKE_STATUS(kStatusGroup_SDIOC, 5U), /*!< Transfer data success. */
+};
+
+/*! @brief SDIOC bus voltage level type definition */
+typedef enum _sdioc_bus_voltage
+{
+ kSDIOC_BusVoltage_3V3 = 0x07, /*!< SDIO bus voltage select 3.3V */
+ kSDIOC_BusVoltage_3V0 = 0x06, /*!< SDIO bus voltage select 3.0V */
+ kSDIOC_BusVoltage_1V8 = 0x05, /*!< SDIO bus voltage select 1.8V */
+
+ /* 0 -4 are reserved */
+
+} sdioc_bus_voltage_t;
+
+/*! @brief SDIOC speed mode type definition */
+typedef enum _sdioc_bus_speed
+{
+ kSDIOC_BusSpeedNormal = 0x00, /*!< SDIO normal speed mode */
+ kSDIOC_BusSpeedHigh, /*!< SDIO high speed mode */
+} sdioc_bus_speed_t;
+
+/*! @brief SDIOC data width type definition */
+typedef enum _sdioc_bus_width
+{
+ kSDIOC_BusWidth1Bit = 0x00, /*!< SDIO data width 1 bit mode */
+ kSDIOC_BusWidth4Bit, /*!< SDIO data width 4 bits mode */
+} sdioc_bus_width_t;
+
+/*! @brief SDIOC command type definition
+ * @anchor _sdioc_command_type
+ */
+enum
+{
+ kSDIOC_CommandTypeNormal = 0x00, /*!< Normal command */
+ kSDIOC_CommandTypeSuspend, /*!< Suspend command */
+ kSDIOC_CommandTypeResume, /*!< Resume command */
+ kSDIOC_CommandTypeAbort, /*!< Abort command */
+};
+
+/*! @brief SDIOC response type definition
+ * @anchor _sdioc_command_response_type
+ */
+enum
+{
+ kSDIOC_CommandNoResponse = SDIOC_MM4_CMD_XFRMD_RES_TYPE(0x00), /*!< No response */
+ kSDIOC_CommandResponseLen136BitsCheckCrc =
+ SDIOC_MM4_CMD_XFRMD_RES_TYPE(1U) | SDIOC_MM4_CMD_XFRMD_CRCCHKEN_MASK, /*!< Response length 136 bits */
+ kSDIOC_CommandResponseLen48Bits = SDIOC_MM4_CMD_XFRMD_RES_TYPE(2U), /*!< Response length 48 bits*/
+ kSDIOC_CommandResponseLen48BitsCheckCrcIndex = SDIOC_MM4_CMD_XFRMD_RES_TYPE(2U) |
+ SDIOC_MM4_CMD_XFRMD_CRCCHKEN_MASK |
+ SDIOC_MM4_CMD_XFRMD_IDXCHKEN_MASK, /*!< Response length 48 bits*/
+ kSDIOC_CommandResponseLen48BitsWithCheckBusyCrcIndex =
+ SDIOC_MM4_CMD_XFRMD_RES_TYPE(3U) | SDIOC_MM4_CMD_XFRMD_CRCCHKEN_MASK |
+ SDIOC_MM4_CMD_XFRMD_IDXCHKEN_MASK, /*!< Response length 48 bits, check busy after response */
+};
+
+/*! @brief SDIOC response number definition */
+typedef enum _sdioc_response_index
+{
+ kSDIOC_ResponseIndex0 = 0x00, /*!< Command response 0 */
+ kSDIOC_ResponseIndex1, /*!< Command response 1 */
+ kSDIOC_ResponseIndex2, /*!< Command response 2 */
+ kSDIOC_ResponseIndex3, /*!< Command response 3 */
+} sdioc_response_index_t;
+
+/*! @brief SDIOC dma buffer boundary */
+typedef enum _sdioc_dma_buffer_boundary
+{
+ kSDIOC_DMABufferBoundary4K = 0U, /*!< DMA buffer boundary 4K*/
+ kSDIOC_DMABufferBoundary8K = 1U, /*!< DMA buffer boundary 8K */
+ kSDIOC_DMABufferBoundary16K = 2U, /*!< DMA buffer boundary 16K */
+ kSDIOC_DMABufferBoundary32K = 3U, /*!< DMA buffer boundary 32K */
+ kSDIOC_DMABufferBoundary64K = 4U, /*!< DMA buffer boundary 64K */
+ kSDIOC_DMABufferBoundary128K = 5U, /*!< DMA buffer boundary 128K */
+ kSDIOC_DMABufferBoundary256K = 6U, /*!< DMA buffer boundary 256K */
+ kSDIOC_DMABufferBoundary512K = 7U, /*!< DMA buffer boundary 512K */
+} sdioc_dma_buffer_boundary_t;
+
+/*! @brief sdioc data timeout value definition */
+typedef enum _sdioc_data_timeout_value
+{
+ kSDIOC_DataTimeoutValue0 = 0U, /*!< timeout out value is (timeout clock)*2^13 */
+ kSDIOC_DataTimeoutValue1 = 1U, /*!< timeout out value is (timeout clock)*2^14 */
+ kSDIOC_DataTimeoutValue2 = 2U, /*!< timeout out value is (timeout clock)*2^15 */
+ kSDIOC_DataTimeoutValue3 = 3U, /*!< timeout out value is (timeout clock)*2^16 */
+ kSDIOC_DataTimeoutValue4 = 4U, /*!< timeout out value is (timeout clock)*2^17 */
+ kSDIOC_DataTimeoutValue5 = 5U, /*!< timeout out value is (timeout clock)*2^18 */
+ kSDIOC_DataTimeoutValue6 = 6U, /*!< timeout out value is (timeout clock)*2^19 */
+ kSDIOC_DataTimeoutValue7 = 7U, /*!< timeout out value is (timeout clock)*2^20 */
+ kSDIOC_DataTimeoutValue8 = 8U, /*!< timeout out value is (timeout clock)*2^21 */
+ kSDIOC_DataTimeoutValue9 = 9U, /*!< timeout out value is (timeout clock)*2^22 */
+ kSDIOC_DataTimeoutValue10 = 10U, /*!< timeout out value is (timeout clock)*2^23 */
+ kSDIOC_DataTimeoutValue11 = 11U, /*!< timeout out value is (timeout clock)*2^24 */
+ kSDIOC_DataTimeoutValue12 = 12U, /*!< timeout out value is (timeout clock)*2^25 */
+ kSDIOC_DataTimeoutValue13 = 13U, /*!< timeout out value is (timeout clock)*2^26 */
+ kSDIOC_DataTimeoutValue14 = 14U, /*!< timeout out value is (timeout clock)*2^27 */
+} sdioc_data_timeout_value_t;
+
+/*! @brief SDIOC interrupt flag definition
+ * @anchor _sdioc_interrupt_flag
+ */
+enum
+{
+ kSDIOC_InterruptCommandCompleteFlag = SDIOC_MM4_I_STAT_CMDCOMP_MASK, /*!< Command complete interrupt flag */
+ kSDIOC_InterruptXferCompleteFlag = SDIOC_MM4_I_STAT_XFRCOMP_MASK, /*!< Transfer complete interrupt flag */
+ kSDIOC_InterruptBlockGapEventFlag = SDIOC_MM4_I_STAT_BGEVNT_MASK, /*!< Block gap event flag */
+ kSDIOC_InterruptDMAInterruptFlag = SDIOC_MM4_I_STAT_DMAINT_MASK, /*!< DMA interrupt flag */
+ kSDIOC_InterruptBufferWriteReadyFlag = SDIOC_MM4_I_STAT_BUFWRRDY_MASK, /*!< Buffer write ready interrupt flag*/
+ kSDIOC_InterruptBufferReadReadyFlag = SDIOC_MM4_I_STAT_BUFRDRDY_MASK, /*!< Buffer read ready interrupt flag */
+ kSDIOC_InterruptCardInsertedFlag = SDIOC_MM4_I_STAT_CDINS_MASK, /*!< Card insertion interrupt flag */
+ kSDIOC_InterruptCardRemovedFlag = SDIOC_MM4_I_STAT_CDREM_MASK, /*!< Card remove interrupt flag */
+ kSDIOC_InterruptCardInterruptFlag =
+ SDIOC_MM4_I_STAT_CDINT_MASK, /*!< Card interrupt flag, interrupt detected by DAT[1] */
+ kSDIOC_InterruptERRInterrupt = SDIOC_MM4_I_STAT_ERRINT_MASK, /*!< Error interrupt flag */
+ kSDIOC_InterruptCommandTimeoutFlag = SDIOC_MM4_I_STAT_CTOERR_MASK, /*!< Command timeout error interrupt flag */
+ kSDIOC_InterruptCommandCrcErrorFlag = SDIOC_MM4_I_STAT_CCRCERR_MASK, /*!< Command crc error interrupt flag */
+ kSDIOC_InterruptCommandEntBitErrorFlag = SDIOC_MM4_I_STAT_CENDERR_MASK, /*!< Command end bit error interrupt flag */
+ kSDIOC_InterruptCommandIndexErrorFlag = SDIOC_MM4_I_STAT_CIDXERR_MASK, /*!< Command index error interrupt flag */
+ kSDIOC_InterruptDataTimeoutErrorFlag = SDIOC_MM4_I_STAT_DTOERR_MASK, /*!< Data timeout error interrupt flag */
+ kSDIOC_InterruptDataCrcErrorFlag = SDIOC_MM4_I_STAT_DCRCERR_MASK, /*!< Data crc error interrupt flag */
+ kSDIOC_InterruptDataEndBitErrorFlag = SDIOC_MM4_I_STAT_DENDERR_MASK, /*!< Data end bit error interrupt flag */
+ kSDIOC_InterruptCurrentLimitErrorFlag = SDIOC_MM4_I_STAT_ILMTERR_MASK, /*!< Current limit error interrupt flag */
+ kSDIOC_InterruptAutoCommand12ErrorFlag = SDIOC_MM4_I_STAT_AC12ERR_MASK, /*!< Current limit error interrupt flag */
+ kSDIOC_InterruptAhbTargetErrorFlag = SDIOC_MM4_I_STAT_AHBTERR_MASK, /*!< AHB Target error interrupt flag */
+
+ kSDIOC_InterruptCardDetectFlag =
+ kSDIOC_InterruptCardInsertedFlag | kSDIOC_InterruptCardRemovedFlag, /*!< card insert flag summary */
+ kSDIOC_InterruptCommandErrorFlag = kSDIOC_InterruptCommandTimeoutFlag | kSDIOC_InterruptCommandCrcErrorFlag |
+ kSDIOC_InterruptCommandEntBitErrorFlag |
+ kSDIOC_InterruptCommandIndexErrorFlag, /*!< command error flag summary */
+ kSDIOC_InterruptCommandFlag =
+ kSDIOC_InterruptCommandCompleteFlag | kSDIOC_InterruptCommandErrorFlag, /*!< command flag summary */
+
+ kSDIOC_InterruptDataErrorFlag = kSDIOC_InterruptDataTimeoutErrorFlag | kSDIOC_InterruptDataCrcErrorFlag |
+ kSDIOC_InterruptDataEndBitErrorFlag | kSDIOC_InterruptAutoCommand12ErrorFlag |
+ kSDIOC_InterruptDMAInterruptFlag |
+ kSDIOC_InterruptAhbTargetErrorFlag, /*!< data error flag */
+
+ kSDIOC_InterruptDataFlag =
+ kSDIOC_InterruptXferCompleteFlag | kSDIOC_InterruptDataErrorFlag, /*!< data flag summary */
+
+ kSDIOC_InterruptCommandAndDataFlag =
+ kSDIOC_InterruptCommandFlag | kSDIOC_InterruptDataFlag, /*!< command and data flag summary */
+};
+
+/*! @brief SDIOC present status definition */
+enum
+{
+ kSDIOC_PresentStatusCommandInhibit = SDIOC_MM4_STATE_CCMDINHBT_MASK, /*!< Command inhibit(CMD) status */
+ kSDIOC_PresentStatusDataInhibit = SDIOC_MM4_STATE_DCMDINHBT_MASK, /*!< Command inhibit(DAT) status */
+ kSDIOC_PresentStatusDataLineActive = SDIOC_MM4_STATE_DATACTV_MASK, /*!< DAT line active */
+ kSDIOC_PresentStatusWriteTransferActive = SDIOC_MM4_STATE_WRACTV_MASK, /*!< Write transfer active */
+ kSDIOC_PresentStatusReadTransferActive = SDIOC_MM4_STATE_RDACTV_MASK, /*!< Read transfer active */
+ kSDIOC_PresentStatusBufferWriteReady = SDIOC_MM4_STATE_BUFWREN_MASK, /*!< Buffer write enable */
+ kSDIOC_PresentStatusBufferReadReady = SDIOC_MM4_STATE_BUFRDEN_MASK, /*!< Buffer read enable */
+ kSDIOC_PresentStatusCardInserted = SDIOC_MM4_STATE_CDINSTD_MASK, /*!< Card inserted */
+ kSDIOC_PresentStatusData0Level = 1U << SDIOC_MM4_STATE_LWRDATLVL_SHIFT, /*!< Data[0] line signal level */
+ kSDIOC_PresentStatusData1Level = 1U << (SDIOC_MM4_STATE_LWRDATLVL_SHIFT + 1U), /*!< Data[1] line signal level */
+ kSDIOC_PresentStatusData2Level = 1U << (SDIOC_MM4_STATE_LWRDATLVL_SHIFT + 2U), /*!< Data[2] line signal level */
+ kSDIOC_PresentStatusData3Level = 1U << (SDIOC_MM4_STATE_LWRDATLVL_SHIFT + 3U), /*!< Data[3] line signal level */
+ kSDIOC_PresentStatusCommandLevel = SDIOC_MM4_STATE_CMDLVL_MASK, /*!< CMD line signal level */
+ kSDIOC_PresentStatusData4Level = 1U << SDIOC_MM4_STATE_UPRDATLVL_SHIFT, /*!< DAT[4] line signal level */
+ kSDIOC_PresentStatusData5Level = 1U << (SDIOC_MM4_STATE_UPRDATLVL_SHIFT + 1U), /*!< DAT[5] line signal level */
+ kSDIOC_PresentStatusData6Level = 1U << (SDIOC_MM4_STATE_UPRDATLVL_SHIFT + 2U), /*!< DAT[6] line signal level */
+ kSDIOC_PresentStatusData7Level = 1U << (SDIOC_MM4_STATE_UPRDATLVL_SHIFT + 3U), /*!< DAT[7] line signal level */
+};
+
+/*! @brief SDIOC Configuration Structure definition */
+typedef struct _sdioc_config
+{
+ sdioc_bus_voltage_t busVoltage; /*!< bus voltage */
+ sdioc_data_timeout_value_t dataTimeout; /*!< data timeout value */
+} sdioc_config_t;
+
+/*! @brief SDIOC command configuration structure definition */
+typedef struct _sdioc_command
+{
+ uint32_t commandIndex; /*!< Command index*/
+ uint32_t commandArgument; /*!< command argument which specified as bit 39-8 of command-format */
+ uint8_t commandType; /*!< Command type, @ref _sdioc_command_type */
+ uint32_t commandResponseType; /*!< Command response type, @ref _sdioc_command_response_type */
+ uint32_t commandResponseErrorFlags; /*!< Command response error flags */
+ uint32_t commandResponse[4]; /*!< Command response */
+} sdioc_command_t;
+
+/*! @brief SDIOC data configuration structure definition*/
+typedef struct _sdioc_data
+{
+ bool dataEnableAutoCommand12; /*!< enable auto command 12 after data transfer complete */
+ uint32_t dataBlockCount; /*!< Block count for current transfer.
+ - 0x0000: stop count
+ - 0x0001: 1 block
+ - 0x0002: 2 blocks
+ ..................
+ ..................
+ - 0xFFFF: 65535 blocks */
+
+ uint32_t dataBlockSize; /*!< Transfer block size.
+ - 0x000: no data transfer
+ - 0x001: 1 byte
+ - 0x002: 2 bytes
+ - 0x003: 3 bytes
+ - 0x004: 4 bytes
+ ..................
+ - 0x1FF: 511 bytes
+ - 0x200: 512 bytes
+ ..................
+ - 0x800: 2048 bytes
+ - 0x801 - 0xFFF: reserved */
+ uint8_t *dataTxAddr; /*!< tx data buffer address */
+ uint8_t *dataRxAddr; /*!< rx data buffer address */
+
+} sdioc_data_t;
+
+/*! @brief SDIOC dma configuration structure definition */
+typedef struct _sdioc_dma_config
+{
+ sdioc_dma_buffer_boundary_t dmaBufferBoundary; /*!< dma buffer boundary */
+} sdioc_dma_config_t;
+
+/*! @brief SDIOC handle typedef. */
+typedef struct _sdioc_handle sdioc_handle_t;
+
+/*! @brief SDIOC callback pointer*/
+typedef void (*sdioc_transfer_callback_t)(sdioc_handle_t *handle, status_t transferStatus, void *userData);
+typedef void (*sdioc_card_int_callback_t)(sdioc_handle_t *handle, void *userData);
+typedef void (*sdioc_card_detect_callback_t)(sdioc_handle_t *handle, bool isCardInserted, void *userData);
+
+/*!< @brief SDIOC callback structure definition */
+typedef struct _sdioc_callback
+{
+ sdioc_transfer_callback_t transferCallback; /*!< transfer callback pointer */
+ sdioc_card_int_callback_t cardIntCallback; /*!< card interrupt callback pointer */
+ sdioc_card_detect_callback_t cardDetectCallback; /*!< card detect callback pointer */
+} sdioc_callback_t;
+
+/*!
+ * @brief SDIOC handle.
+ *
+ * Defines the structure to save the SDIOC state information and callback function.
+ *
+ */
+struct _sdioc_handle
+{
+ SDIOC_Type *base; /*!< host controller base address */
+ sdioc_data_t *data; /*!< transfer data pointer */
+ sdioc_command_t *command; /*!< transfer command pointer */
+ sdioc_callback_t callback; /*!< Callback function. */
+ void *userData; /*!< Parameter for transfer complete callback. */
+};
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name SDIOC Initialization and deinitialization
+ * @{
+ */
+/*!
+ * @brief SDIOC module initialization function.
+ *
+ * Configures the SDIOC according to the user configuration.
+ *
+ * Example:
+ @code
+ sdioc_config_t config;
+ config.busVoltage = kSDIOC_BusVoltage_3V3;
+ config.dataTimeout = kSDIOC_DataTimeoutValue14;
+ SDIOC_Init(SDIOC, &config);
+ @endcode
+ *
+ * @param base SDIOC peripheral base address.
+ * @param config SDIOC configuration information.
+ * @retval #kStatus_Success Operate successfully.
+ */
+void SDIOC_Init(SDIOC_Type *base, const sdioc_config_t *config);
+
+/*!
+ * @brief Deinitializes the SDIOC.
+ *
+ * @param base SDIOC peripheral base address.
+ */
+void SDIOC_Deinit(SDIOC_Type *base);
+/* @} */
+
+/*!
+ * @name SDIOC bus functional interface
+ * @{
+ */
+/*!
+ * @brief SDIOC set bus voltage.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param busVoltage SDIO bus voltage.
+ */
+static inline void SDIOC_SetBusVoltage(SDIOC_Type *base, sdioc_bus_voltage_t busVoltage)
+{
+ base->MM4_CNTL1 = (base->MM4_CNTL1 & ~SDIOC_MM4_CNTL1_VLTGSEL_MASK) | SDIOC_MM4_CNTL1_VLTGSEL(busVoltage);
+}
+
+/*!
+ * @brief SDIOC set data bus width.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param busWidth SDIO bus width.
+ */
+static inline void SDIOC_SetDataBusWidth(SDIOC_Type *base, sdioc_bus_width_t busWidth)
+{
+ base->MM4_CNTL1 = (base->MM4_CNTL1 & ~SDIOC_MM4_CNTL1__4BITMD_MASK) | SDIOC_MM4_CNTL1__4BITMD(busWidth);
+}
+
+/*!
+ * @brief SDIOC set bus speed.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param busSpeed SDIO bus speed.
+ */
+static inline void SDIOC_SetBusSpeed(SDIOC_Type *base, sdioc_bus_speed_t busSpeed)
+{
+ base->MM4_CNTL1 = (base->MM4_CNTL1 & ~SDIOC_MM4_CNTL1_HISPEED_MASK) | SDIOC_MM4_CNTL1_HISPEED(busSpeed);
+}
+
+/*!
+ * @brief SDIOC enable/disable bus power.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param enable true is enable power, false is disable power.
+ */
+static inline void SDIOC_EnableBusPower(SDIOC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_CNTL1 |= SDIOC_MM4_CNTL1_BUSPWR_MASK;
+ }
+ else
+ {
+ base->MM4_CNTL1 &= ~SDIOC_MM4_CNTL1_BUSPWR_MASK;
+ }
+}
+
+/*!
+ * @brief SDIOC enable/disable internal clock.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param enable true is enable internal clock, false is disable internal clock.
+ */
+static inline void SDIOC_EnableInternalClock(SDIOC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_CNTL2 |= SDIOC_MM4_CNTL2_INTCLKEN_MASK;
+ }
+ else
+ {
+ base->MM4_CNTL2 &= ~SDIOC_MM4_CNTL2_INTCLKEN_MASK;
+ }
+}
+
+/*!
+ * @brief SDIOC enable/disable card clock.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param enable true is enable card clock, false is disable card clock.
+ */
+static inline void SDIOC_EnableCardClock(SDIOC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_CNTL2 |= SDIOC_MM4_CNTL2_MM4CLKEN_MASK;
+ }
+ else
+ {
+ base->MM4_CNTL2 &= ~SDIOC_MM4_CNTL2_MM4CLKEN_MASK;
+ }
+}
+
+/*!
+ * @brief SDIOC software reset entire host controller except for the card detection circuit register.
+ *
+ * @param base SDIOC peripheral base address.
+ */
+static inline void SDIOC_ResetAll(SDIOC_Type *base)
+{
+ base->MM4_CNTL2 |= SDIOC_MM4_CNTL2_MSWRST_MASK;
+}
+
+/*!
+ * @brief SDIOC software reset command line.
+ *
+ * @param base SDIOC peripheral base address.
+ */
+static inline void SDIOC_ResetCommandLine(SDIOC_Type *base)
+{
+ base->MM4_CNTL2 |= SDIOC_MM4_CNTL2_CMDSWRST_MASK;
+}
+
+/*!
+ * @brief SDIOC software reset data line.
+ *
+ * @param base SDIOC peripheral base address.
+ */
+static inline void SDIOC_ResetDataLine(SDIOC_Type *base)
+{
+ base->MM4_CNTL2 |= SDIOC_MM4_CNTL2_DATSWRST_MASK;
+}
+
+/*!
+ * @brief SDIOC set data timeout value.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param timeout timeout value.
+ */
+static inline void SDIOC_SetDataTimeout(SDIOC_Type *base, sdioc_data_timeout_value_t timeout)
+{
+ base->MM4_CNTL2 = (base->MM4_CNTL2 & (~SDIOC_MM4_CNTL2_DTOCNTR_MASK)) | SDIOC_MM4_CNTL2_DTOCNTR(timeout);
+}
+
+/* @} */
+
+/*!
+ * @name SDIOC block gap functional interface
+ * @{
+ */
+/*!
+ * @brief SDIOC enable stop at block gap request.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param enable true is enable stop executing read and write transaction at next block gap, false is disable.
+ */
+static inline void SDIOC_EnableStopAtBlockGap(SDIOC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_CNTL1 |= SDIOC_MM4_CNTL1_BGREQSTP_MASK;
+ }
+ else
+ {
+ base->MM4_CNTL1 &= ~SDIOC_MM4_CNTL1_BGREQSTP_MASK;
+ }
+}
+
+/*!
+ * @brief SDIOC enable continue request.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param enable true is restart a transaction which was stopped using stop at block gap request, false not affect.
+ */
+static inline void SDIOC_EnableContinueRequest(SDIOC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_CNTL1 |= SDIOC_MM4_CNTL1_CONTREQ_MASK;
+ }
+ else
+ {
+ base->MM4_CNTL1 &= ~SDIOC_MM4_CNTL1_CONTREQ_MASK;
+ }
+}
+
+/*!
+ * @brief SDIOC enable/disable read wait control.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param enable true is enable read wait function, false is disable.
+ */
+static inline void SDIOC_EnableReadWaitControl(SDIOC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_CNTL1 |= SDIOC_MM4_CNTL1_RDWTCNTL_MASK;
+ }
+ else
+ {
+ base->MM4_CNTL1 &= ~SDIOC_MM4_CNTL1_RDWTCNTL_MASK;
+ }
+}
+
+/*!
+ * @brief SDIOC enable/disable stop at block gap interrupt.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param enable true is enable interrupt at block gap, false is disable.
+ */
+static inline void SDIOC_EnableStopAtBlockGapInterrupt(SDIOC_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_CNTL1 |= SDIOC_MM4_CNTL1_BGIRQEN_MASK;
+ }
+ else
+ {
+ base->MM4_CNTL1 &= ~SDIOC_MM4_CNTL1_BGIRQEN_MASK;
+ }
+}
+
+/*!
+ * @brief SDIOC read command response.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param responseIndex response index.
+ * @retval response read from sdioc.
+ */
+static inline uint32_t SDIOC_ReadCommandResponse(SDIOC_Type *base, sdioc_response_index_t responseIndex)
+{
+ return ((uint32_t *)&(base->MM4_RESP0))[responseIndex];
+}
+
+/*!
+ * @brief SDIOC read data port.
+ *
+ * @param base SDIOC peripheral base address.
+ * @retval data read from SDIOC fifo.
+ */
+static inline uint32_t SDIOC_ReadData(SDIOC_Type *base)
+{
+ return base->MM4_DP;
+}
+
+/*!
+ * @brief SDIOC write data port.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param data data to be written to SDIOC fifo.
+ */
+static inline void SDIOC_WriteData(SDIOC_Type *base, uint32_t data)
+{
+ base->MM4_DP = data;
+}
+
+/* @} */
+
+/*!
+ * @name SDIOC dma functional interface
+ * @{
+ */
+
+/*!
+ * @brief SDIOC set dma buffer boundary.
+ *
+ * The large contiguous memory space may not be available in the virtual memory
+ * system. To perform long DMA transfer, DMA System Address register shall be
+ * updated at every system memory boundary during DMA transfer.
+ * These bits specify the size of contiguous buffer in the system memory. The
+ * SDMA transfer shall wait at the every boundary specified by these fields and the
+ * Host Controller generates the DMA Interrupt to request the Host Driver to
+ * update the SDMA System Address register.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param bufferBoundary dma buffer boundary.
+ */
+static inline void SDIOC_SetDmaBufferBoundary(SDIOC_Type *base, sdioc_dma_buffer_boundary_t bufferBoundary)
+{
+ base->MM4_BLK_CNTL =
+ (base->MM4_BLK_CNTL & ~SDIOC_MM4_BLK_CNTL_DMA_BUFSZ_MASK) | SDIOC_MM4_BLK_CNTL_DMA_BUFSZ(bufferBoundary);
+}
+
+/*!
+ * @brief SDIOC set dma buffer address.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param bufferAddress dma buffer address.
+ */
+static inline void SDIOC_SetDmaBufferAddress(SDIOC_Type *base, void *bufferAddress)
+{
+ base->MM4_SYSADDR = (uint32_t)bufferAddress;
+}
+
+/* @} */
+
+/*!
+ * @name SDIOC interrupt and status interface
+ * @{
+ */
+
+/*!
+ * @brief SDIOC enable/disable interrupt status.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param interruptFlags status flag to enable/disable, @ref _sdioc_interrupt_flag.
+ * @param enable true is enable the corresponding interrupt status, false is disable.
+ */
+static inline void SDIOC_EnableInterruptStatus(SDIOC_Type *base, uint32_t interruptFlags, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_I_STAT_EN |= interruptFlags;
+ }
+ else
+ {
+ base->MM4_I_STAT_EN &= ~interruptFlags;
+ }
+}
+
+/*!
+ * @brief SDIOC enable/disable interrupt signal.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param interruptFlags status flag to enable/disable, @ref _sdioc_interrupt_flag.
+ * @param enable true is enable the corresponding interrupt status, false is disable.
+ */
+static inline void SDIOC_EnableInterruptSignal(SDIOC_Type *base, uint32_t interruptFlags, bool enable)
+{
+ if (enable)
+ {
+ base->MM4_I_SIG_EN |= interruptFlags;
+ }
+ else
+ {
+ base->MM4_I_SIG_EN &= ~interruptFlags;
+ }
+}
+
+/*!
+ * @brief SDIOC get interrupt status.
+ *
+ * @param base SDIOC peripheral base address.
+ * @retval interrupt status flag.
+ */
+static inline uint32_t SDIOC_GetInterruptStatus(SDIOC_Type *base)
+{
+ return base->MM4_I_STAT;
+}
+
+/*!
+ * @brief Gets the enabled interrupt status.
+ *
+ * @param base USDHC peripheral base address.
+ * @retval Current interrupt status flags mask @ref _sdioc_interrupt_flag.
+ */
+static inline uint32_t SDIOC_GetEnabledInterruptStatus(SDIOC_Type *base)
+{
+ uint32_t intStatus = base->MM4_I_STAT;
+
+ return intStatus & base->MM4_I_SIG_EN;
+}
+
+/*!
+ * @brief SDIOC clear interrupt status.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param interruptFlags interrupt status flag to clear, @ref _sdioc_interrupt_flag..
+ */
+static inline void SDIOC_ClearInterruptStatus(SDIOC_Type *base, uint32_t interruptFlags)
+{
+ base->MM4_I_STAT = interruptFlags;
+}
+
+/*!
+ * @brief SDIOC get host controller present status.
+ *
+ * @param base SDIOC peripheral base address.
+ * @retval present status flag.
+ */
+static inline uint32_t SDIOC_GetPresentStatus(SDIOC_Type *base)
+{
+ return base->MM4_STATE;
+}
+
+/*!
+ * @brief Transfer parameters command/data/dma configurations.
+ *
+ * @param base SDIOC base address.
+ * @param command Transfer command pointer, application should not pass NULL pointer to this parameter.
+ * @param data Transfer data pointer, application can pass NULL when send command only.
+ * @param dmaConfig Internal dma configurations, application can pass NULL when dma is not used.
+ *
+ * @retval #kStatus_InvalidArgument Argument is invalid.
+ * @retval #kStatus_Success Operate successfully.
+ */
+status_t SDIOC_SetTransferConfig(SDIOC_Type *base,
+ sdioc_command_t *command,
+ sdioc_data_t *data,
+ sdioc_dma_config_t *dmaConfig);
+/* @} */
+
+/*!
+ * @name SDIOC transactional interface
+ * @{
+ */
+/*!
+ * @brief Creates the SDIOC handle.
+ *
+ * @param base SDIOC peripheral base address.
+ * @param handle SDIOC handle pointer.
+ * @param callback Structure pointer to contain all callback functions.
+ * @param userData Callback function parameter.
+ */
+void SDIOC_TransferCreateHandle(SDIOC_Type *base, sdioc_handle_t *handle, sdioc_callback_t *callback, void *userData);
+
+/*!
+ * @brief Transfers the command/data using an interrupt and an asynchronous method.
+ *
+ * This function sends a command and data and returns immediately. It doesn't wait for the transfer to complete or
+ * to encounter an error. The application must not call this API in multiple threads at the same time. Because of that
+ * this API doesn't support the re-entry mechanism.
+ *
+ * This function transfer data through SDIOC internal DMA.
+ *
+ * @note Call API @ref SDIOC_TransferCreateHandle when calling this API.
+ *
+ * @param handle SDIOC handle.
+ * @param command Transfer command pointer should not be NULL.
+ * @param data Transfer data pointer can be NULL if send command only.
+ * @param dmaConfig Internal dma configurations, NULL pointer is not allowed.
+ *
+ * @retval #kStatus_InvalidArgument Argument is invalid.
+ * @retval #kStatus_SDIOC_BusyTransferring Busy transferring.
+ * @retval #kStatus_Success Operate successfully.
+ */
+status_t SDIOC_TransferDMANonBlocking(sdioc_handle_t *handle,
+ sdioc_command_t *command,
+ sdioc_data_t *data,
+ sdioc_dma_config_t *dmaConfig);
+
+/*!
+ * @brief IRQ handler for the SDIOC.
+ *
+ * This function deals with the IRQs on the given host controller.
+ *
+ * @param handle SDIOC handle.
+ */
+void SDIOC_TransferHandleIRQ(sdioc_handle_t *handle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+
+#endif /* _FSL_SDIOC_H_ */
diff --git a/drivers/mw320/ssp/driver_mw_ssp.cmake b/drivers/mw320/ssp/driver_mw_ssp.cmake
new file mode 100644
index 000000000..b9ab8043b
--- /dev/null
+++ b/drivers/mw320/ssp/driver_mw_ssp.cmake
@@ -0,0 +1,14 @@
+#Description: MW_SSP Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_ssp component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_ssp.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/ssp/driver_mw_ssp_dmac.cmake b/drivers/mw320/ssp/driver_mw_ssp_dmac.cmake
new file mode 100644
index 000000000..bd419f818
--- /dev/null
+++ b/drivers/mw320/ssp/driver_mw_ssp_dmac.cmake
@@ -0,0 +1,15 @@
+#Description: MW_SSP_DMA Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_ssp_dmac component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_ssp_dmac.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_mw_dmac)
+include(driver_mw_ssp)
diff --git a/drivers/mw320/ssp/fsl_ssp.c b/drivers/mw320/ssp/fsl_ssp.c
new file mode 100644
index 000000000..ba5a18779
--- /dev/null
+++ b/drivers/mw320/ssp/fsl_ssp.c
@@ -0,0 +1,891 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_ssp.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Typedef for interrupt handler. */
+typedef void (*ssp_isr_t)(ssp_handle_t *handle);
+/*! @brief check flag avalibility */
+#define IS_SSP_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL)
+/*! @brief SSAP fifo depth */
+#define SSP_FIFO_COUNT(bitWidth) ((bitWidth) == 16U ? 32U : 16U)
+/*! @brief SSP transfer state */
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief SSP base pointer array */
+static SSP_Type *const s_sspBase[] = SSP_BASE_PTRS;
+
+/*! @brief SSP internal handle pointer array */
+static ssp_handle_t *s_sspHandle[ARRAY_SIZE(s_sspBase)][2];
+
+/*! @brief SSP IRQ name array */
+static const IRQn_Type s_sspIRQ[] = SSP_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Clock name array */
+static const clock_ip_name_t s_sspClock[] = SSP_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* SSP send ISR for transactional APIs. */
+static ssp_isr_t s_sspSendIsr;
+static ssp_isr_t s_sspReceiveIsr;
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief SSP write data fifo.
+ *
+ *
+ * @param base SSP peripheral base address.
+ * @param buffer write buffer pointer.
+ * @param bitWidth data bitwidth.
+ * @param size data size to write.
+ */
+static void SSP_WriteNonBlocking(SSP_Type *base, uint8_t *buffer, uint32_t bitWidth, uint32_t size);
+
+/*!
+ * @brief SSP read data fifo.
+ *
+ *
+ * @param base SSP peripheral base address.
+ * @param buffer read buffer pointer.
+ * @param bitWidth data bitwidth.
+ * @param size data size to read.
+ */
+static void SSP_ReadNonBlocking(SSP_Type *base, uint8_t *buffer, uint32_t bitWidth, uint32_t size);
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+uint32_t SSP_GetInstance(SSP_Type *base)
+{
+ uint8_t instance = 0;
+
+ while ((instance < ARRAY_SIZE(s_sspBase)) && (s_sspBase[instance] != base))
+ {
+ instance++;
+ }
+
+ assert(instance < ARRAY_SIZE(s_sspBase));
+
+ return instance;
+}
+
+static void SSP_WriteNonBlocking(SSP_Type *base, uint8_t *buffer, uint32_t bitWidth, uint32_t size)
+{
+ uint32_t i = 0, j = 0U;
+ uint32_t bytesPerWord = bitWidth;
+ uint32_t data = 0;
+ uint32_t temp = 0;
+
+ for (i = 0; i < size / bytesPerWord; i++)
+ {
+ for (j = 0; j < bytesPerWord; j++)
+ {
+ temp = (uint32_t)(*buffer);
+ data |= (temp << (8U * j));
+ buffer++;
+ }
+ SSP_WriteData(base, data);
+ data = 0;
+ }
+}
+
+static void SSP_ReadNonBlocking(SSP_Type *base, uint8_t *buffer, uint32_t bitWidth, uint32_t size)
+{
+ uint32_t i = 0, j = 0;
+ uint32_t bytesPerWord = bitWidth;
+ uint32_t data = 0;
+
+ for (i = 0; i < size / bytesPerWord; i++)
+ {
+ data = SSP_ReadData(base);
+ for (j = 0; j < bytesPerWord; j++)
+ {
+ *buffer = (uint8_t)(data >> (8U * j)) & 0xFFU;
+ buffer++;
+ }
+ }
+}
+
+/*!
+ * brief SSP get default configuration.
+ *
+ * code
+ * config->enableRXHalfCycleDelay = false;
+ * config->enableMasterClockReturn = false;
+ * config->enableFifoPackingMode = false;
+ * config->enableSlaveClockFreeRuning = false;
+ * config->txFifoWaterMark = SSP_FIFO_COUNT(32) / 2U;
+ * config->rxFifoWaterMark = SSP_FIFO_COUNT(32) / 2U;
+ * config->mode = kSSP_TransmitReceiveMode;
+ * config->format = kSSP_TransceiverFormatPSP;
+ * endcode
+ *
+ * param config the pointer of ssp configuration structure.
+ */
+void SSP_GetDefaultConfig(ssp_config_t *config)
+{
+ assert(config != NULL);
+
+ (void)memset(config, 0, sizeof(ssp_config_t));
+
+ config->enableRXHalfCycleDelay = false;
+ config->enableMasterClockReturn = false;
+ config->enableFifoPackingMode = false;
+ config->enableSlaveClockFreeRuning = false;
+ config->txFifoWaterMark = SSP_FIFO_COUNT(32) / 2U;
+ config->rxFifoWaterMark = SSP_FIFO_COUNT(32) / 2U;
+ config->mode = kSSP_TransmitReceiveMode;
+ config->format = kSSP_TransceiverFormatPSP;
+}
+
+/*!
+ * brief SSP module initialization function.
+ *
+ * Configures the SSP according to the user configuration.
+ *
+ * param base SSP peripheral base address.
+ * param config SSP configuration information.
+ */
+void SSP_Init(SSP_Type *base, const ssp_config_t *config)
+{
+ assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable SSP clock. */
+ CLOCK_EnableClock(s_sspClock[SSP_GetInstance(base)]);
+#endif
+
+ /* clear bit error/tx underrun/rx overrun status */
+ base->SSP_SSSR |= SSP_SSP_SSSR_TUR_MASK | SSP_SSP_SSITR_TROR_MASK | SSP_SSP_SSSR_BCE_MASK;
+ /* SSP configuration */
+ base->SSP_SSCR0 = SSP_SSP_SSCR0_FRF(config->format) | SSP_SSP_SSCR0_MCRT(config->enableMasterClockReturn) |
+ SSP_SSP_SSCR0_RHCD(config->enableRXHalfCycleDelay) |
+ SSP_SSP_SSCR0_FPCKE(config->enableFifoPackingMode);
+
+ base->SSP_SSCR1 = SSP_SSP_SSCR1_RFT(config->rxFifoWaterMark - 1UL) |
+ SSP_SSP_SSCR1_TFT(config->txFifoWaterMark - 1UL) | SSP_SSP_SSCR1_RWOT(config->mode) |
+ SSP_SSP_SSCR1_SCFR(config->enableSlaveClockFreeRuning);
+
+ if (config->transceiverConfig != NULL)
+ {
+ if (config->format == kSSP_TransceiverFormatSPI)
+ {
+ SSP_SetSPIModeConfig(base, (ssp_spi_mode_config_t *)config->transceiverConfig);
+ }
+ else
+ {
+ SSP_SetPSPModeConfig(base, (ssp_psp_mode_config_t *)config->transceiverConfig);
+ }
+ }
+}
+
+/*!
+ * brief Deinitializes the SSP.
+ *
+ * param base SSP peripheral base address.
+ */
+void SSP_Deinit(SSP_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Disable clock. */
+ CLOCK_DisableClock(s_sspClock[SSP_GetInstance(base)]);
+#endif
+}
+
+/*!
+ * brief SSP get default SPI mode configuration.
+ *
+ * The default SSP SPI mode configurations:
+ * code
+ * config->spiClockPolarity = kSSP_ClockPolarityLow;
+ * config->spiClockPhase = kSSP_SpiClkPhase0;
+ * config->spiClockDirection = kSSP_ClockDirectionMaster;
+ * config->dataWidth = kSSP_DataSize8Bit;
+ * config->txdIdleState = kSSP_TxdIdleStateIsNot3Stated;
+ * config->txdLastPhaseState = kSSP_TxdLastPhase3StatedHalfOfLSBClockCycle;
+ * endcode
+ *
+ * param config the pointer of ssp configuration structure.
+ */
+void SSP_GetDefaultSPIModeConfig(ssp_spi_mode_config_t *config)
+{
+ assert(config != NULL);
+
+ config->spiClockPolarity = kSSP_ClockPolarityLow;
+ config->spiClockPhase = kSSP_SpiClkPhase0;
+ config->spiClockDirection = kSSP_ClockDirectionMaster;
+ config->dataWidth = kSSP_DataSize8Bit;
+ config->txdIdleState = kSSP_TxdIdleStateIsNot3Stated;
+ config->txdLastPhaseState = kSSP_TxdLastPhase3StatedHalfOfLSBClockCycle;
+}
+
+/*!
+ * brief SSP set SPI mode configuration.
+ *
+ * param base SSP peripheral base address.
+ * param config the pointer of ssp spi mode configuration structure.
+ */
+void SSP_SetSPIModeConfig(SSP_Type *base, const ssp_spi_mode_config_t *config)
+{
+ assert(config != NULL);
+
+ uint32_t sscr = base->SSP_SSCR1;
+
+ sscr &= ~(SSP_SSP_SSCR1_SCLKDIR_MASK | SSP_SSP_SSCR1_SFRMDIR_MASK | SSP_SSP_SSCR1_SPH_MASK |
+ SSP_SSP_SSCR1_SPO_MASK | SSP_SSP_SSCR1_TTELP_MASK | SSP_SSP_SSCR1_TTE_MASK);
+
+ sscr |= SSP_SSP_SSCR1_SCLKDIR(config->spiClockDirection) | SSP_SSP_SSCR1_SFRMDIR(config->spiClockDirection) |
+ SSP_SSP_SSCR1_SPH(config->spiClockPhase) | SSP_SSP_SSCR1_SPO(config->spiClockPolarity) |
+ SSP_SSP_SSCR1_TTELP(config->txdLastPhaseState) | SSP_SSP_SSCR1_TTE(config->txdIdleState);
+
+ base->SSP_SSCR1 = sscr;
+
+ sscr = base->SSP_SSCR0;
+ sscr &= ~(SSP_SSP_SSCR0_DSS_MASK | SSP_SSP_SSCR0_EDSS_MASK);
+ sscr |= (uint32_t)config->dataWidth;
+ base->SSP_SSCR0 = sscr;
+}
+
+/*!
+ * brief SSP get default PSP mode configuration.
+ *
+ * The default SSP PSP mode configurations are 16bit, 2 slots, i2s protocol.
+ * code
+ * config->bitClockDirection = kSSP_ClockDirectionMaster;
+ * config->bitClockMode = kSPP_BitClockIdleLowDrivenFallingSampleRising;
+ * config->frameClockDirection = kSSP_ClockDirectionMaster;
+ * config->frameClockPolarity = kSSP_ClockPolarityLow;
+ * config->frameRelativeTiming = kSSP_FrameSyncAssertWithTheLsbOfThePreviousFrame;
+ * config->txdIdleState = kSSP_TxdIdleStateIsNot3Stated;
+ * config->txdLastPhaseState = kSSP_TxdLastPhase3StatedOnLSBEndClockEdge;
+ * config->txdEndTransferState = kSSP_TxdEndTransferState0;
+ * config->dataWidth = kSSP_DataSize16Bit;
+ * config->frameLength = 16U;
+ * config->enableNetWorkMode = true;
+ * config->frameSlotsNumber = 2U;
+ * config->txActiveSlotMask = 3U;
+ * config->rxActiveSlotMask = 3U;
+ * config->dummyStartDelay = 0U;
+ * config->dummyStopDelay = 0U;
+ * config->startDelay = 0U;
+ * config->frameDelay = 0U;
+ * endcode
+ *
+ * param config the pointer of PSP configuration structure.
+ */
+void SSP_GetDefaultPSPModeConfig(ssp_psp_mode_config_t *config)
+{
+ assert(config != NULL);
+
+ config->bitClockDirection = kSSP_ClockDirectionMaster;
+ config->bitClockMode = kSPP_BitClockIdleLowDrivenFallingSampleRising;
+
+ config->frameClockDirection = kSSP_ClockDirectionMaster;
+ config->frameClockPolarity = kSSP_ClockPolarityLow;
+ config->frameRelativeTiming = kSSP_FrameSyncAssertWithTheLsbOfThePreviousFrame;
+
+ config->txdIdleState = kSSP_TxdIdleStateIsNot3Stated;
+ config->txdLastPhaseState = kSSP_TxdLastPhase3StatedOnLSBEndClockEdge;
+ config->txdEndTransferState = kSSP_TxdEndTransferState0;
+
+ config->dataWidth = kSSP_DataSize16Bit;
+ config->frameLength = 16U;
+
+ config->enableNetWorkMode = true;
+ config->frameSlotsNumber = 2U;
+ config->txActiveSlotMask = 3U;
+ config->rxActiveSlotMask = 3U;
+ /* below configuration should be ignored when network mode enabled */
+ config->dummyStartDelay = 0U;
+ config->dummyStopDelay = 0U;
+ config->startDelay = 0U;
+ config->frameDelay = 0U;
+}
+
+/*!
+ * brief SSP set PSP mode configuration.
+ *
+ * param base SSP peripheral base address.
+ * param config the pointer of ssp psp mode configuration structure.
+ */
+void SSP_SetPSPModeConfig(SSP_Type *base, const ssp_psp_mode_config_t *config)
+{
+ assert(config != NULL);
+ assert(config->frameSlotsNumber != 0U);
+
+ uint32_t sscr = base->SSP_SSCR1, sspsp = base->SSP_SSPSP;
+
+ sscr &=
+ ~(SSP_SSP_SSCR1_SCLKDIR_MASK | SSP_SSP_SSCR1_SFRMDIR_MASK | SSP_SSP_SSCR1_TTELP_MASK | SSP_SSP_SSCR1_TTE_MASK);
+
+ sscr |= SSP_SSP_SSCR1_SCLKDIR(config->bitClockDirection) | SSP_SSP_SSCR1_SFRMDIR(config->frameClockDirection) |
+ SSP_SSP_SSCR1_TTELP(config->txdLastPhaseState) | SSP_SSP_SSCR1_TTE(config->txdIdleState);
+
+ base->SSP_SSCR1 = sscr;
+
+ sscr = base->SSP_SSCR0;
+ sscr &= ~(SSP_SSP_SSCR0_DSS_MASK | SSP_SSP_SSCR0_EDSS_MASK | SSP_SSP_SSCR0_FRDC_MASK | SSP_SSP_SSCR0_MOD_MASK);
+ sscr |= (uint32_t)config->dataWidth | SSP_SSP_SSCR0_FRDC(config->frameSlotsNumber - 1UL) |
+ SSP_SSP_SSCR0_MOD(config->enableNetWorkMode);
+ base->SSP_SSCR0 = sscr;
+
+ sspsp = SSP_SSP_SSPSP_FSRT(config->frameRelativeTiming) | SSP_SSP_SSPSP_SFRMWDTH(config->frameLength) |
+ SSP_SSP_SSPSP_ETDS(config->txdEndTransferState) | SSP_SSP_SSPSP_SFRMP(config->frameClockPolarity) |
+ SSP_SSP_SSPSP_SCMODE(config->bitClockMode);
+
+ if (config->enableNetWorkMode == false)
+ {
+ sspsp |= SSP_SSP_SSPSP_EDMYSTOP(config->dummyStopDelay) | SSP_SSP_SSPSP_EDMYSTRT(config->dummyStartDelay) |
+ SSP_SSP_SSPSP_DMYSTOP(config->dummyStopDelay) | SSP_SSP_SSPSP_DMYSTRT(config->dummyStartDelay) |
+ SSP_SSP_SSPSP_SFRMDLY(config->frameDelay) | SSP_SSP_SSPSP_STRTDLY(config->startDelay);
+ }
+ else
+ {
+ base->SSP_SSTSA = config->txActiveSlotMask;
+ base->SSP_SSRSA = config->rxActiveSlotMask;
+ }
+
+ base->SSP_SSPSP = sspsp;
+}
+
+/*! brief SSP enable interrupt.
+ *
+ * param base SSP peripheral base address
+ * param interruptMask the Interrupt to be enabled, can a value or OR value of @ref _ssp_interrupt_mask.
+ */
+void SSP_EnableInterrupt(SSP_Type *base, uint32_t interruptMask)
+{
+ if ((interruptMask & (uint32_t)kSSP_InterruptTransmitFifoUnderrun) != 0U)
+ {
+ base->SSP_SSCR0 &= ~SSP_SSP_SSCR0_TIM_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptReceiveFifoOverrun) != 0U)
+ {
+ base->SSP_SSCR0 &= ~SSP_SSP_SSCR0_RIM_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptBitCountError) != 0U)
+ {
+ base->SSP_SSCR1 |= SSP_SSP_SSCR1_EBCEI_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptTransmitFifoReady) != 0U)
+ {
+ base->SSP_SSCR1 |= SSP_SSP_SSCR1_TIE_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptReceiveFifoReady) != 0U)
+ {
+ base->SSP_SSCR1 |= SSP_SSP_SSCR1_RIE_MASK;
+ }
+}
+
+/*! brief SSP disable interrupt.
+ *
+ * param base SSP peripheral base address
+ * param interruptMask the Interrupt to be disabled, can a value or OR value of @ref _ssp_interrupt_mask.
+ */
+void SSP_DisableInterrupt(SSP_Type *base, uint32_t interruptMask)
+{
+ if ((interruptMask & (uint32_t)kSSP_InterruptTransmitFifoUnderrun) != 0U)
+ {
+ base->SSP_SSCR0 |= SSP_SSP_SSCR0_TIM_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptReceiveFifoOverrun) != 0U)
+ {
+ base->SSP_SSCR0 |= SSP_SSP_SSCR0_RIM_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptBitCountError) != 0U)
+ {
+ base->SSP_SSCR1 &= ~SSP_SSP_SSCR1_EBCEI_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptTransmitFifoReady) != 0U)
+ {
+ base->SSP_SSCR1 &= ~SSP_SSP_SSCR1_TIE_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptReceiveFifoReady) != 0U)
+ {
+ base->SSP_SSCR1 &= ~SSP_SSP_SSCR1_RIE_MASK;
+ }
+}
+
+/*! brief SSP clear interrupt status.
+ *
+ * Note: Transmit fifo ready flag and receive fifo flag do not support clear by software.
+ *
+ * param base SSP peripheral base address
+ * param interruptMask the Interrupt to be cleared, can a value or OR'ed value of @ref _ssp_interrupt_mask.
+ */
+void SSP_ClearInterruptStatus(SSP_Type *base, uint32_t interruptMask)
+{
+ if ((interruptMask & (uint32_t)kSSP_InterruptTransmitFifoUnderrun) != 0U)
+ {
+ base->SSP_SSSR = SSP_SSP_SSSR_TUR_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptReceiveFifoOverrun) != 0U)
+ {
+ base->SSP_SSSR = SSP_SSP_SSSR_ROR_MASK;
+ }
+
+ if ((interruptMask & (uint32_t)kSSP_InterruptBitCountError) != 0U)
+ {
+ base->SSP_SSSR = SSP_SSP_SSSR_BCE_MASK;
+ }
+}
+
+/*! brief SSP get interrupt status.
+ *
+ * param base SSP peripheral base address
+ * param interruptMask the Interrupt to be cleared, can a value or OR'ed value of @ref _ssp_interrupt_mask.
+ */
+uint32_t SSP_GetInterruptStatus(SSP_Type *base)
+{
+ uint32_t retval = 0U;
+
+ if ((base->SSP_SSSR & SSP_SSP_SSSR_TUR_MASK) != 0U)
+ {
+ retval |= (uint32_t)kSSP_InterruptTransmitFifoUnderrun;
+ }
+
+ if ((base->SSP_SSSR & SSP_SSP_SSSR_ROR_MASK) != 0U)
+ {
+ retval |= (uint32_t)kSSP_InterruptReceiveFifoOverrun;
+ }
+
+ if ((base->SSP_SSSR & SSP_SSP_SSSR_BCE_MASK) != 0U)
+ {
+ retval |= (uint32_t)kSSP_InterruptBitCountError;
+ }
+
+ if ((base->SSP_SSSR & SSP_SSP_SSSR_TFS_MASK) != 0U)
+ {
+ retval |= (uint32_t)kSSP_InterruptTransmitFifoReady;
+ }
+
+ if ((base->SSP_SSSR & SSP_SSP_SSSR_RFS_MASK) != 0U)
+ {
+ retval |= (uint32_t)kSSP_InterruptReceiveFifoReady;
+ }
+
+ return retval;
+}
+
+/*!
+ * brief Creates the SSP send handle.
+ *
+ * param base SSP peripheral base address.
+ * param handle SSP handle pointer.
+ * param callback Structure pointer to contain all callback functions.
+ * param userData Callback function parameter.
+ */
+void SSP_TransferSendCreateHandle(SSP_Type *base,
+ ssp_handle_t *handle,
+ ssp_transfer_callback_t callback,
+ void *userData)
+{
+ assert(handle != NULL);
+ assert(callback != NULL);
+
+ uint32_t regBitWidth = base->SSP_SSCR0 & (SSP_SSP_SSCR0_DSS_MASK | SSP_SSP_SSCR0_EDSS_MASK);
+ /* Zero the handle. */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ handle->base = base;
+
+ /* Set the callback. */
+ handle->callback = callback;
+ handle->userData = userData;
+ handle->sspFifoWatermark = ((base->SSP_SSCR1 & SSP_SSP_SSCR1_TFT_MASK) >> SSP_SSP_SSCR1_TFT_SHIFT) + 1U;
+ handle->bitWidth =
+ regBitWidth == (uint32_t)kSSP_DataSize8Bit ? 1U : regBitWidth == (uint32_t)kSSP_DataSize16Bit ? 2U : 4U;
+
+ /* Save the handle in global variables to support the double weak mechanism. */
+ s_sspHandle[SSP_GetInstance(base)][0] = handle;
+
+ /* save IRQ handler */
+ s_sspSendIsr = SSP_TransferSendHandleIRQ;
+
+ (void)EnableIRQ(s_sspIRQ[SSP_GetInstance(base)]);
+}
+
+/*!
+ * brief Creates the SSP receive handle.
+ *
+ * param base SSP peripheral base address.
+ * param handle SSP handle pointer.
+ * param callback Structure pointer to contain all callback functions.
+ * param userData Callback function parameter.
+ */
+void SSP_TransferReceiveCreateHandle(SSP_Type *base,
+ ssp_handle_t *handle,
+ ssp_transfer_callback_t callback,
+ void *userData)
+{
+ assert(handle != NULL);
+ assert(callback != NULL);
+
+ uint32_t regBitWidth = base->SSP_SSCR0 & (SSP_SSP_SSCR0_DSS_MASK | SSP_SSP_SSCR0_EDSS_MASK);
+ /* Zero the handle. */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ handle->base = base;
+
+ /* Set the callback. */
+ handle->callback = callback;
+ handle->userData = userData;
+ handle->sspFifoWatermark = ((base->SSP_SSCR1 & SSP_SSP_SSCR1_RFT_MASK) >> SSP_SSP_SSCR1_RFT_SHIFT) + 1U;
+ handle->bitWidth =
+ regBitWidth == (uint32_t)kSSP_DataSize8Bit ? 1U : regBitWidth == (uint32_t)kSSP_DataSize16Bit ? 2U : 4U;
+
+ /* Save the handle in global variables to support the double weak mechanism. */
+ s_sspHandle[SSP_GetInstance(base)][1] = handle;
+
+ /* save IRQ handler */
+ s_sspReceiveIsr = SSP_TransferReceiveHandleIRQ;
+
+ (void)EnableIRQ(s_sspIRQ[SSP_GetInstance(base)]);
+}
+
+/*!
+ * brief Send the data using an interrupt and an asynchronous method.
+ *
+ * This function sends data and returns immediately. It doesn't wait for the transfer to complete or
+ * to encounter an error. The application can submit multiple transfer requests without waiting previous
+ * transfer request complete, since the SSP driver maintained a software transfer queue, the sizeof the queue
+ * is configurable by macro SSP_XFER_QUEUE_SIZE which indicates how many request can be submitted at the same time.
+ *
+ * note Call API @ref SSP_TransferCreateHandle when calling this API.
+ *
+ * param handle SSP handle.
+ * param transfer transfer pointer.
+ * retval #kStatus_InvalidArgument Argument is invalid.
+ * retval #kSSP_TransferStatusBusy Busy transferring.
+ * retval #kStatus_Success Operate successfully.
+ */
+status_t SSP_TransferSendNonBlocking(ssp_handle_t *handle, ssp_transfer_t *transfer)
+{
+ status_t error = kStatus_Success;
+
+ if ((handle == NULL) || (transfer == NULL))
+ {
+ error = kStatus_InvalidArgument;
+ }
+ /* Check if the queue is full */
+ else
+ {
+ if (handle->sspQueue[handle->sspQueueUser].dataBuffer != NULL)
+ {
+ error = kSSP_TransferStatusBusy;
+ }
+ else
+ {
+ /* Add into queue */
+ handle->sspQueue[handle->sspQueueUser].dataBuffer = transfer->dataBuffer;
+ handle->sspQueue[handle->sspQueueUser].dataSize = transfer->dataSize;
+ handle->sspQueueUser = (handle->sspQueueUser + 1U) % SSP_XFER_QUEUE_SIZE;
+
+ /* Enable interrupt */
+ SSP_EnableInterrupt(handle->base, (uint32_t)kSSP_InterruptTransmitFifoUnderrun |
+ (uint32_t)kSSP_InterruptTransmitFifoReady |
+ (uint32_t)kSSP_InterruptBitCountError);
+ /* Enable ssp port */
+ SSP_Enable(handle->base, true);
+ }
+ }
+
+ return error;
+}
+
+/*!
+ * brief Receive the data using an interrupt and an asynchronous method.
+ *
+ * This function sends data and returns immediately. It doesn't wait for the transfer to complete or
+ * to encounter an error. The application can submit multiple transfer requests without waiting previous
+ * transfer request complete, since the SSP driver maintained a software transfer queue, the sizeof the queue
+ * is configurable by macro SSP_XFER_QUEUE_SIZE which indicates how many request can be submitted at the same time.
+ *
+ * note Call API @ref SSP_TransferCreateHandle when calling this API.
+ *
+ * param handle SSP handle.
+ * param transfer transfer pointer.
+ * retval #kStatus_InvalidArgument Argument is invalid.
+ * retval #kSSP_TransferStatusBusy Busy transferring.
+ * retval #kStatus_Success Operate successfully.
+ */
+status_t SSP_TransferReceiveNonBlocking(ssp_handle_t *handle, ssp_transfer_t *transfer)
+{
+ status_t error = kStatus_Success;
+
+ if ((handle == NULL) || (transfer == NULL))
+ {
+ error = kStatus_InvalidArgument;
+ }
+ else
+ {
+ /* Check if the queue is full */
+ if (handle->sspQueue[handle->sspQueueUser].dataBuffer != NULL)
+ {
+ error = kSSP_TransferStatusBusy;
+ }
+ else
+ {
+ /* Add into queue */
+ handle->sspQueue[handle->sspQueueUser].dataBuffer = transfer->dataBuffer;
+ handle->sspQueue[handle->sspQueueUser].dataSize = transfer->dataSize;
+ handle->sspQueueUser = (handle->sspQueueUser + 1U) % SSP_XFER_QUEUE_SIZE;
+
+ /* Enable interrupt */
+ SSP_EnableInterrupt(handle->base, (uint32_t)kSSP_InterruptBitCountError |
+ (uint32_t)kSSP_InterruptReceiveFifoOverrun |
+ (uint32_t)kSSP_InterruptReceiveFifoReady);
+ /* Enable ssp port */
+ SSP_Enable(handle->base, true);
+ }
+ }
+
+ return error;
+}
+
+/*!
+ * brief Aborts the current send.
+ *
+ * note This API can be called any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param handle Pointer to the ssp_handle_t structure which stores the transfer state.
+ */
+void SSP_TransferAbortSend(ssp_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ SSP_DisableInterrupt(handle->base, (uint32_t)kSSP_InterruptTransmitFifoUnderrun |
+ (uint32_t)kSSP_InterruptBitCountError |
+ (uint32_t)kSSP_InterruptTransmitFifoReady);
+
+ /* Clear the queue */
+ (void)memset(handle->sspQueue, 0, sizeof(ssp_transfer_t) * SSP_XFER_QUEUE_SIZE);
+ handle->sspQueueDriver = 0;
+ handle->sspQueueUser = 0;
+}
+
+/*!
+ * brief Aborts the current IRQ receive.
+ *
+ * note This API can be called when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * param handle Pointer to the ssp_handle_t structure which stores the transfer state.
+ */
+void SSP_TransferAbortReceive(ssp_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ SSP_DisableInterrupt(handle->base, (uint32_t)kSSP_InterruptReceiveFifoOverrun |
+ (uint32_t)kSSP_InterruptBitCountError |
+ (uint32_t)kSSP_InterruptReceiveFifoReady);
+
+ /* Clear the queue */
+ (void)memset(handle->sspQueue, 0, sizeof(ssp_transfer_t) * SSP_XFER_QUEUE_SIZE);
+ handle->sspQueueDriver = 0;
+ handle->sspQueueUser = 0;
+}
+
+/*!
+ * brief IRQ handler for the SSP transmitter.
+ *
+ * This function deals with the IRQs on the given host controller.
+ *
+ * param handle SSP handle.
+ */
+void SSP_TransferSendHandleIRQ(ssp_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ SSP_Type *base = handle->base;
+ uint32_t status = base->SSP_SSSR;
+
+ /* clear the interrupt status */
+ base->SSP_SSSR |= status;
+
+ /* Handle Error */
+ if (IS_SSP_FLAG_SET(status, SSP_SSP_SSSR_BCE_MASK))
+ {
+ /* Call the callback */
+ if (handle->callback != NULL)
+ {
+ (handle->callback)(handle, kSSP_TransferStatusBitCountError, handle->userData);
+ }
+ }
+
+ if (IS_SSP_FLAG_SET(status, SSP_SSP_SSSR_TUR_MASK))
+ {
+ /* Call the callback */
+ if (handle->callback != NULL)
+ {
+ (handle->callback)(handle, kSSP_TransferStatusTxFifoError, handle->userData);
+ }
+ }
+
+ if (IS_SSP_FLAG_SET(status, SSP_SSP_SSSR_TFS_MASK) && IS_SSP_FLAG_SET(base->SSP_SSCR1, SSP_SSP_SSCR1_TIE_MASK))
+ {
+ size_t sendSize =
+ MIN((handle->sspQueue[handle->sspQueueDriver].dataSize), handle->sspFifoWatermark * handle->bitWidth);
+ uint8_t *sendBuffer = handle->sspQueue[handle->sspQueueDriver].dataBuffer;
+
+ SSP_WriteNonBlocking(base, sendBuffer, handle->bitWidth, sendSize);
+
+ /* Update internal counter */
+ handle->sspQueue[handle->sspQueueDriver].dataSize -= sendSize;
+ handle->sspQueue[handle->sspQueueDriver].dataBuffer = (uint8_t *)((uint32_t)sendBuffer + sendSize);
+
+ /* If finished a block, call the callback function */
+ if (handle->sspQueue[handle->sspQueueDriver].dataSize == 0U)
+ {
+ (void)memset(&handle->sspQueue[handle->sspQueueDriver], 0, sizeof(ssp_transfer_t));
+ handle->sspQueueDriver = (handle->sspQueueDriver + 1U) % SSP_XFER_QUEUE_SIZE;
+ if (handle->callback != NULL)
+ {
+ (handle->callback)(handle, kSSP_TransferStatusTxIdle, handle->userData);
+ }
+ }
+
+ /* If all data finished, just stop the transfer */
+ if (handle->sspQueue[handle->sspQueueDriver].dataBuffer == NULL)
+ {
+ SSP_TransferAbortSend(handle);
+ }
+ }
+}
+
+/*!
+ * brief IRQ handler for the SSP receiver.
+ *
+ * This function deals with the IRQs on the given host controller.
+ *
+ * param handle SSP handle.
+ */
+void SSP_TransferReceiveHandleIRQ(ssp_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ SSP_Type *base = handle->base;
+ uint32_t status = base->SSP_SSSR;
+
+ /* clear the interrupt status */
+ base->SSP_SSSR |= status;
+
+ /* Handle Error */
+ if (IS_SSP_FLAG_SET(status, SSP_SSP_SSSR_BCE_MASK))
+ {
+ /* Call the callback */
+ if (handle->callback != NULL)
+ {
+ (handle->callback)(handle, kSSP_TransferStatusBitCountError, handle->userData);
+ }
+ }
+
+ if (IS_SSP_FLAG_SET(status, SSP_SSP_SSSR_ROR_MASK))
+ {
+ /* Call the callback */
+ if (handle->callback != NULL)
+ {
+ (handle->callback)(handle, kSSP_TransferStatusRxFifoError, handle->userData);
+ }
+ }
+
+ if (IS_SSP_FLAG_SET(status, SSP_SSP_SSSR_RFS_MASK) && IS_SSP_FLAG_SET(base->SSP_SSCR1, SSP_SSP_SSCR1_RIE_MASK))
+ {
+ size_t receiveSize =
+ MIN((handle->sspQueue[handle->sspQueueDriver].dataSize), handle->sspFifoWatermark * handle->bitWidth);
+ uint8_t *receiveBuffer = handle->sspQueue[handle->sspQueueDriver].dataBuffer;
+
+ SSP_ReadNonBlocking(base, receiveBuffer, handle->bitWidth, receiveSize);
+
+ /* Update internal counter */
+ handle->sspQueue[handle->sspQueueDriver].dataSize -= receiveSize;
+ handle->sspQueue[handle->sspQueueDriver].dataBuffer = (uint8_t *)((uint32_t)receiveBuffer + receiveSize);
+
+ /* If finished a block, call the callback function */
+ if (handle->sspQueue[handle->sspQueueDriver].dataSize == 0U)
+ {
+ (void)memset(&handle->sspQueue[handle->sspQueueDriver], 0, sizeof(ssp_transfer_t));
+ handle->sspQueueDriver = (handle->sspQueueDriver + 1U) % SSP_XFER_QUEUE_SIZE;
+ if (handle->callback != NULL)
+ {
+ (handle->callback)(handle, kSSP_TransferStatusRxIdle, handle->userData);
+ }
+ }
+
+ /* If all data finished, just stop the transfer */
+ if (handle->sspQueue[handle->sspQueueDriver].dataBuffer == NULL)
+ {
+ SSP_TransferAbortReceive(handle);
+ }
+ }
+}
+
+#ifdef SSP0
+void SSP0_DriverIRQHandler(void);
+void SSP0_DriverIRQHandler(void)
+{
+ if (IS_SSP_FLAG_SET(SSP0->SSP_SSSR, SSP_SSP_SSSR_TUR_MASK | SSP_SSP_SSSR_TFS_MASK))
+ {
+ s_sspSendIsr(s_sspHandle[0U][0U]);
+ }
+
+ if (IS_SSP_FLAG_SET(SSP0->SSP_SSSR, SSP_SSP_SSSR_ROR_MASK | SSP_SSP_SSSR_RFS_MASK))
+ {
+ s_sspReceiveIsr(s_sspHandle[0U][1U]);
+ }
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#ifdef SSP1
+void SSP1_DriverIRQHandler(void);
+void SSP1_DriverIRQHandler(void)
+{
+ if (IS_SSP_FLAG_SET(SSP1->SSP_SSSR, SSP_SSP_SSSR_TUR_MASK | SSP_SSP_SSSR_TFS_MASK))
+ {
+ s_sspSendIsr(s_sspHandle[1U][0U]);
+ }
+
+ if (IS_SSP_FLAG_SET(SSP1->SSP_SSSR, SSP_SSP_SSSR_ROR_MASK | SSP_SSP_SSSR_RFS_MASK))
+ {
+ s_sspReceiveIsr(s_sspHandle[1U][1U]);
+ }
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#ifdef SSP2
+void SSP2_DriverIRQHandler(void);
+void SSP2_DriverIRQHandler(void)
+{
+ if (IS_SSP_FLAG_SET(SSP2->SSP_SSSR, SSP_SSP_SSSR_TUR_MASK | SSP_SSP_SSSR_TFS_MASK))
+ {
+ s_sspSendIsr(s_sspHandle[2U][0U]);
+ }
+
+ if (IS_SSP_FLAG_SET(SSP2->SSP_SSSR, SSP_SSP_SSSR_ROR_MASK | SSP_SSP_SSSR_RFS_MASK))
+ {
+ s_sspReceiveIsr(s_sspHandle[2U][1U]);
+ }
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/drivers/mw320/ssp/fsl_ssp.h b/drivers/mw320/ssp/fsl_ssp.h
new file mode 100644
index 000000000..adfc01670
--- /dev/null
+++ b/drivers/mw320/ssp/fsl_ssp.h
@@ -0,0 +1,638 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_SSP_H_
+#define _FSL_SSP_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup ssp_driver
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions.
+ *****************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.0. */
+#define FSL_SSP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
+#ifndef SSP_XFER_QUEUE_SIZE
+/*! @brief SSP xfer queue size definition */
+#define SSP_XFER_QUEUE_SIZE 4U
+#endif
+
+/*! @brief transfer status */
+enum
+{
+ kSSP_TransferStatusTxIdle = MAKE_STATUS(kStatusGroup_SSP, 0), /*!< ssp status idle */
+ kSSP_TransferStatusRxIdle = MAKE_STATUS(kStatusGroup_SSP, 1), /*!< ssp status idle */
+ kSSP_TransferStatusBusy = MAKE_STATUS(kStatusGroup_SSP, 2), /*!< ssp status busy */
+ kSSP_TransferStatusBitCountError = MAKE_STATUS(kStatusGroup_SSP, 3), /*!< ssp status bit count error */
+ kSSP_TransferStatusTxFifoError = MAKE_STATUS(kStatusGroup_SSP, 4), /*!< ssp status tx fifo error */
+ kSSP_TransferStatusRxFifoError = MAKE_STATUS(kStatusGroup_SSP, 5), /*!< ssp status rx fifo error */
+};
+
+/*! @brief ssp mode */
+typedef enum _ssp_transcevier_mode
+{
+ kSSP_TransmitReceiveMode, /*!< ssp tansmit and receive mode */
+ kSSP_ReceiveMode, /*!< ssp receive without transmit mode */
+} ssp_transcevier_mode_t;
+
+/*! @brief ssp interrupt mask
+ * @anchor _ssp_interrupt_mask
+ */
+enum
+{
+ kSSP_InterruptTransmitFifoUnderrun = 1U, /*!< transmit fifo underrun */
+ kSSP_InterruptReceiveFifoOverrun = 2U, /*!< receive fifo underrun */
+ kSSP_InterruptBitCountError = 4U, /*!< bit count error */
+ kSSP_InterruptTransmitFifoReady = 8U, /*!< transmit fifo ready for write */
+ kSSP_InterruptReceiveFifoReady = 16U, /*!< receive fifo ready for read */
+};
+
+/*! @brief ssp frame format */
+typedef enum _ssp_transceiver_format
+{
+ kSSP_TransceiverFormatSPI = 0U, /*!< frame format serial Peripheral Interface */
+ kSSP_TransceiverFormatPSP = 3U, /*!< frame format programmable serial protocol */
+} ssp_transceiver_format_t;
+
+/*! @brief ssp clock direction */
+typedef enum _ssp_clock_direction
+{
+ kSSP_ClockDirectionMaster = 0U, /*!< SSP clock direction master */
+ kSSP_ClockDirectionSlave, /*!< SSP clock direction slave */
+} ssp_clock_direction_t;
+
+/*! @brief ssp data size */
+typedef enum _ssp_data_width
+{
+ kSSP_DataSize8Bit = 0x7U, /*!< SSP data size 8 bit */
+ kSSP_DataSize16Bit = 0xFU, /*!< SSP data size 16 bit */
+ kSSP_DataSize18Bit = 1U | (1U << 20U), /*!< SSP data size 18 bit */
+ kSSP_DataSize32Bit = 0xFU | (1U << 20U), /*!< SSP data size 32 bit */
+} ssp_data_width_t;
+
+/*! @brief ssp txd last phase state */
+typedef enum _ssp_txd_last_phase_state
+{
+ kSSP_TxdLastPhase3StatedHalfOfLSBClockCycle =
+ 0U, /*!< txdx is 3-stated 1/2 clock cycle after the beginning of the LSB */
+ kSSP_TxdLastPhase3StatedOnLSBEndClockEdge = 1U, /*!< txdx is 3-stated on the clock edge that ends the LSB */
+} ssp_txd_last_phase_state_t;
+
+/*! @brief ssp txd last phase state */
+typedef enum _ssp_txd_idle_state
+{
+ kSSP_TxdIdleStateIsNot3Stated = 0U, /*!< txdx is not 3-stated when not transmitting data */
+ kSSP_TxdIdleState3Stated = 1U, /*!< txdx is 3-stated when not transmitting data */
+} ssp_txd_idle_state_t;
+
+/*! @brief ssp txd end transfer state */
+typedef enum _ssp_txd_end_transfer_state
+{
+ kSSP_TxdEndTransferState0 = 0U, /*!< txd end transfer state 0 */
+ kSSP_TxdEndTransferState1 = 1U, /*!< txd end transfer state 1 */
+} ssp_txd_end_transfer_state_t;
+
+/*! @brief ssp clk polarity */
+typedef enum _ssp_clock_polarity
+{
+ kSSP_ClockPolarityLow = 0U, /*!< clock polarity low */
+ kSSP_ClockPolarityHigh = 1U, /*!< clock polarity high */
+} ssp_clock_polarity_t;
+
+/*! @brief ssp bit clock mode */
+typedef enum _ssp_bit_clock_mode
+{
+ kSPP_BitClockIdleLowDrivenFallingSampleRising =
+ 0U, /*!< data driven on falling edge, sample on rising edge, ide state low */
+ kSPP_BitClockIdleLowDrivenRisingSampleFalling =
+ 1U, /*!< data driven on rising edge, sample on falling edge, ide state low */
+ kSPP_BitClockIdleHighDrivenRasingSampleFalling =
+ 2U, /*!< data driven on rising edge, sample on falling edge, ide state high */
+ kSPP_BitClockIdleHighDrivenFallingSampleRising =
+ 3U, /*!< data driven on falling edge, sample on rising edge, ide state high */
+} ssp_bit_clock_mode_t;
+
+/*! @brief ssp frame sync relative timing bit */
+typedef enum _ssp_frame_sync_relative_timing
+{
+ kSSP_FrameSyncAssertAfterEndOfDMTStop = 0U, /*!< next frame assert after the end of the DMTSTOP timing */
+ kSSP_FrameSyncAssertWithTheLsbOfThePreviousFrame = 1U, /*!< next frame assert with the LSB of previous frame */
+} ssp_frame_sync_relative_timing_t;
+
+/*! @brief ssp spi clk phase */
+typedef enum _ssp_spi_clock_phase
+{
+ kSSP_SpiClkPhase0 = 0U, /*!< motorola clk inactive until one cycle after the
+ start of frame and active until 1/2 cycle before the end of a frame */
+
+ kSSP_SpiClkPhase1 = 1U, /*!< motorola clk inactive until 1/2 cycle after the
+ start of frame and active until 1 cycle before the end of a frame */
+} ssp_spi_clock_phase_t;
+
+/*! @brief ssp motorola spi mode configuration */
+typedef struct _ssp_spi_mode_config
+{
+ ssp_clock_polarity_t spiClockPolarity; /*!< SPI clock polarity */
+ ssp_spi_clock_phase_t spiClockPhase; /*!< SPI clock pahse */
+ ssp_clock_direction_t
+ spiClockDirection; /*!< SPI clock direction for serial bit clock direction and frame clock direction */
+
+ ssp_data_width_t dataWidth; /*!< data width 8/16/18/32 bits */
+
+ ssp_txd_idle_state_t txdIdleState; /*!< txd state when idle */
+ ssp_txd_last_phase_state_t txdLastPhaseState; /*!< txd last phase state */
+} ssp_spi_mode_config_t;
+
+/*! @brief ssp psp mode configuration */
+typedef struct _ssp_mode_psp_config
+{
+ ssp_clock_direction_t bitClockDirection; /*!< bit clock generate internally or input externally */
+ ssp_bit_clock_mode_t bitClockMode; /*!< bit clock mode */
+
+ ssp_clock_direction_t frameClockDirection; /*!< frame clock generate internally or input externally */
+ ssp_clock_polarity_t frameClockPolarity; /*!< frame clock polarity */
+ ssp_frame_sync_relative_timing_t frameRelativeTiming; /*!< frame sync relative timing */
+
+ ssp_txd_idle_state_t txdIdleState; /*!< txd state when idle */
+ ssp_txd_last_phase_state_t txdLastPhaseState; /*!< txd last phase state */
+ ssp_txd_end_transfer_state_t txdEndTransferState; /*!< txd end transfer state */
+
+ ssp_data_width_t dataWidth; /*!< data width 8/16/18/32 bits */
+ uint8_t frameLength; /*!< frame length, valid range 1-0x3F SSPSCLKx cycles */
+
+ uint8_t dummyStartDelay; /*!< The MSB of the dummy start delay */
+ uint8_t dummyStopDelay; /*!< The MSB of the dummy stop delay */
+ uint8_t startDelay; /*!< number of 0-7 non-active clocks that defines the duration of idle time */
+ uint8_t frameDelay; /*!< Programmed value specifies the number (0 -127) of active one-half
+ clocks (SSPSCLKx) asserted from the most-significant bit of TXDx
+ (output) or RXD (input) being driven to SSPSFRMx. */
+
+ bool enableNetWorkMode; /*!< network should be enabled when emulating I2S protocol*/
+ uint8_t frameSlotsNumber; /*!< the tims slots number per frame, 1-8 can be specified */
+ uint8_t
+ txActiveSlotMask; /*!< the each bit in the txActiveSlotMask represent a time slot
+ 0 is the SSP does not transmit data in this time slot, 1 is the SSP does transmit data in this
+ time slot, so txActiveSlotMask = 3 means slot 0 and 1 is enabled, other slots are disabled */
+ uint8_t
+ rxActiveSlotMask; /*!< the each bit in the txActiveSlotMask represent a time slot
+ 0 is the SSP does not transmit data in this time slot, 1 is the SSP does transmit data in this
+ time slot, so txActiveSlotMask = 3 means slot 0 and 1 is enabled, other slots are disabled */
+} ssp_psp_mode_config_t;
+
+/*! @brief ssp configuration */
+typedef struct _ssp_config
+{
+ bool enableRXHalfCycleDelay; /*!< true is enable rx half cycle delay, false is disable */
+ bool enableMasterClockReturn; /*!< true is enable master clock delay, false is disable */
+ bool enableSlaveClockFreeRuning; /*!< true is clock input to SSPSCLKx is only active during data transfer
+ * false is clock input to SSPSCLKx is continuously runing*/
+
+ bool enableFifoPackingMode; /*!< fifo packing mode */
+ uint8_t txFifoWaterMark; /*!< tx fifo watermark value */
+ uint8_t rxFifoWaterMark; /*!< rx fifo watermark value */
+
+ ssp_transcevier_mode_t mode; /*!< transceiver work mode */
+ ssp_transceiver_format_t format; /*!< transceiver work format */
+ void *transceiverConfig; /*!< transceiver configuration pointer, should be a pointer of
+ - ssp_psp_mode_config_t, can be used to simulate i2s
+ - ssp_spi_mode_config_t, can be used to simulate spi */
+} ssp_config_t;
+
+/*! @brief ssp transfer content */
+typedef struct _ssp_transfer
+{
+ void *dataBuffer; /*!< the pointer of data buffer */
+ uint32_t dataSize; /*!< the size of data to be transferred */
+} ssp_transfer_t;
+
+/*! @brief SSP handle typedef. */
+typedef struct _ssp_handle ssp_handle_t;
+
+/*! @brief SSP callback pointer*/
+typedef void (*ssp_transfer_callback_t)(ssp_handle_t *handle, status_t transferStatus, void *userData);
+
+/*!
+ * @brief SSP handle.
+ *
+ * Defines the structure to save the SSP state information and callback function.
+ * A ssp_handle variable can be used to represent either SSP TX or SSP RX.
+ *
+ */
+struct _ssp_handle
+{
+ SSP_Type *base; /*!< ssp base address */
+
+ uint32_t bitWidth; /*!< bit width */
+ uint32_t sspFifoWatermark; /*!< ssp fifo WaterMark */
+
+ ssp_transfer_t sspQueue[SSP_XFER_QUEUE_SIZE]; /*!< ssp queue storing queued transfer */
+ volatile uint8_t sspQueueUser; /*!< Index for user to queue transfer */
+ volatile uint8_t sspQueueDriver; /*!< Index for driver to get the transfer data and size */
+
+ ssp_transfer_callback_t callback; /*!< Callback function. */
+ void *userData; /*!< Parameter for transfer complete callback. */
+};
+
+/*************************************************************************************************
+ * API
+ ************************************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name SSP Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief SSP get default configuration.
+ *
+ * @code
+ * config->enableRXHalfCycleDelay = false;
+ * config->enableMasterClockReturn = false;
+ * config->enableFifoPackingMode = false;
+ * config->enableSlaveClockFreeRuning = false;
+ * config->txFifoWaterMark = SSP_FIFO_COUNT(32) / 2U;
+ * config->rxFifoWaterMark = SSP_FIFO_COUNT(32) / 2U;
+ * config->mode = kSSP_TransmitReceiveMode;
+ * config->format = kSSP_TransceiverFormatPSP;
+ * @endcode
+ *
+ * @param config the pointer of ssp configuration structure.
+ */
+void SSP_GetDefaultConfig(ssp_config_t *config);
+
+/*!
+ * @brief SSP module initialization function.
+ *
+ * Configures the SSP according to the user configuration.
+ *
+ * @param base SSP peripheral base address.
+ * @param config SSP configuration information.
+ */
+void SSP_Init(SSP_Type *base, const ssp_config_t *config);
+
+/*!
+ * @brief Deinitializes the SSP.
+ *
+ * @param base SSP peripheral base address.
+ */
+void SSP_Deinit(SSP_Type *base);
+
+/*!
+ * @brief Get SSP instance index.
+ *
+ * Used for SSP DMA driver only.
+ *
+ * @param base SSP peripheral base address.
+ */
+uint32_t SSP_GetInstance(SSP_Type *base);
+
+/* @} */
+
+/*!
+ * @name SSP bus functional interface
+ * @{
+ */
+
+/*!
+ * @brief SSP get default SPI mode configuration.
+ *
+ * The default SSP SPI mode configurations:
+ * @code
+ * config->spiClockPolarity = kSSP_ClockPolarityLow;
+ * config->spiClockPhase = kSSP_SpiClkPhase0;
+ * config->spiClockDirection = kSSP_ClockDirectionMaster;
+ * config->dataWidth = kSSP_DataSize8Bit;
+ * config->txdIdleState = kSSP_TxdIdleStateIsNot3Stated;
+ * config->txdLastPhaseState = kSSP_TxdLastPhase3StatedHalfOfLSBClockCycle;
+ * @endcode
+ *
+ * @param config the pointer of ssp configuration structure.
+ */
+void SSP_GetDefaultSPIModeConfig(ssp_spi_mode_config_t *config);
+
+/*!
+ * @brief SSP set SPI mode configuration.
+ *
+ * @param base SSP peripheral base address.
+ * @param config the pointer of ssp spi mode configuration structure.
+ */
+void SSP_SetSPIModeConfig(SSP_Type *base, const ssp_spi_mode_config_t *config);
+
+/*!
+ * @brief SSP get default PSP mode configuration.
+ *
+ * The default SSP PSP mode configurations are 16bit, 2 slots, i2s protocol.
+ * @code
+ * config->bitClockDirection = kSSP_ClockDirectionMaster;
+ * config->bitClockMode = kSPP_BitClockIdleLowDrivenFallingSampleRising;
+ * config->frameClockDirection = kSSP_ClockDirectionMaster;
+ * config->frameClockPolarity = kSSP_ClockPolarityLow;
+ * config->frameRelativeTiming = kSSP_FrameSyncAssertWithTheLsbOfThePreviousFrame;
+ * config->txdIdleState = kSSP_TxdIdleStateIsNot3Stated;
+ * config->txdLastPhaseState = kSSP_TxdLastPhase3StatedOnLSBEndClockEdge;
+ * config->txdEndTransferState = kSSP_TxdEndTransferState0;
+ * config->dataWidth = kSSP_DataSize16Bit;
+ * config->frameLength = 16U;
+ * config->enableNetWorkMode = true;
+ * config->frameSlotsNumber = 2U;
+ * config->txActiveSlotMask = 3U;
+ * config->rxActiveSlotMask = 3U;
+ * config->dummyStartDelay = 0U;
+ * config->dummyStopDelay = 0U;
+ * config->startDelay = 0U;
+ * config->frameDelay = 0U;
+ * @endcode
+ *
+ * @param config the pointer of PSP configuration structure.
+ */
+void SSP_GetDefaultPSPModeConfig(ssp_psp_mode_config_t *config);
+
+/*!
+ * @brief SSP set PSP mode configuration.
+ *
+ * @param base SSP peripheral base address.
+ * @param config the pointer of ssp psp mode configuration structure.
+ */
+void SSP_SetPSPModeConfig(SSP_Type *base, const ssp_psp_mode_config_t *config);
+/*!
+ * @brief SSP enable/disable loop back mode.
+ *
+ * The tx serial shifter is internally connected to input of RX serial shifter, the loopback mode used for test purpose
+ * only.
+ *
+ * @param base SSP peripheral base address.
+ * @param enable true is enable the loop back mode, false is disable the loop back mode.
+ */
+static inline void SSP_EnableLoopBackMode(SSP_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->SSP_SSCR1 |= SSP_SSP_SSCR1_LBM_MASK;
+ }
+ else
+ {
+ base->SSP_SSCR1 &= ~SSP_SSP_SSCR1_LBM_MASK;
+ }
+}
+
+/*!
+ * @brief SSP write data fifo.
+ *
+ * When a data sample size of less than 32-bits is selected, or 16 bits for packed mode, software
+ * should right-justify the data that is written to the SSP Data Register for automatic insertion into the
+ * TXFIFO. The transmit logic left-justifies the data and ignores any unused bits, cannot perform a write in
+ * packed mode of less than 32 bits wide.
+ *
+ * @param base SSP peripheral base address.
+ * @param data data to write.
+ */
+static inline void SSP_WriteData(SSP_Type *base, uint32_t data)
+{
+ base->SSP_SSDR = data;
+}
+
+/*!
+ * @brief SSP read data fifo.
+ *
+ * Received data of less than 32 bits is right-justified automatically in the RXFIFO
+ *
+ * @param base SSP peripheral base address.
+ * @return data value read from fifo.
+ */
+static inline uint32_t SSP_ReadData(SSP_Type *base)
+{
+ return base->SSP_SSDR;
+}
+
+/*!
+ * @brief SSP enable/disable.
+ *
+ * @param base SSP peripheral base address.
+ * @param enable true is enable, false is disable.
+ */
+static inline void SSP_Enable(SSP_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->SSP_SSCR0 |= SSP_SSP_SSCR0_SSE_MASK;
+ }
+ else
+ {
+ base->SSP_SSCR0 &= ~SSP_SSP_SSCR0_SSE_MASK;
+ }
+}
+
+/* @} */
+
+/*!
+ * @name SSP interrupt functional interface
+ * @{
+ */
+/*! @brief SSP enable interrupt.
+ *
+ * @param base SSP peripheral base address
+ * @param interruptMask the Interrupt to be enabled, can a value or OR value of @ref _ssp_interrupt_mask.
+ */
+void SSP_EnableInterrupt(SSP_Type *base, uint32_t interruptMask);
+
+/*! @brief SSP disable interrupt.
+ *
+ * @param base SSP peripheral base address
+ * @param interruptMask the Interrupt to be disable, can a value or OR value of @ref _ssp_interrupt_mask.
+ */
+void SSP_DisableInterrupt(SSP_Type *base, uint32_t interruptMask);
+
+/*! @brief SSP clear interrupt status.
+ *
+ * Note: Transmit fifo ready flag and receive fifo flag do not support clear by software.
+ *
+ * @param base SSP peripheral base address
+ * @param interruptMask the Interrupt to be cleared, can a value or OR'ed value of @ref _ssp_interrupt_mask.
+ */
+void SSP_ClearInterruptStatus(SSP_Type *base, uint32_t interruptMask);
+
+/*! brief SSP get interrupt status.
+ *
+ * @param base SSP peripheral base address
+ * @return interrupt status flag, a value or OR'ed value of @ref _ssp_interrupt_mask.
+ */
+uint32_t SSP_GetInterruptStatus(SSP_Type *base);
+
+/* @} */
+
+/*!
+ * @name SSP dma functional interface
+ * @{
+ */
+/*!
+ * @brief SSP enable/disable tx DMA requst.
+ *
+ * @param base SSP peripheral base address.
+ * @param enable true is enable TX dma request, false is disable
+ */
+static inline void SSP_EnableSendDMARequest(SSP_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->SSP_SSCR1 |= SSP_SSP_SSCR1_TSRE_MASK;
+ }
+ else
+ {
+ base->SSP_SSCR1 &= ~SSP_SSP_SSCR1_TSRE_MASK;
+ }
+}
+
+/*!
+ * @brief SSP enable/disable rx DMA requst.
+ *
+ * @param base SSP peripheral base address.
+ * @param enable true is enable RX dma request, false is disable
+ */
+static inline void SSP_EnableReceiveDMARequest(SSP_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->SSP_SSCR1 |= SSP_SSP_SSCR1_RSRE_MASK;
+ }
+ else
+ {
+ base->SSP_SSCR1 &= ~SSP_SSP_SSCR1_RSRE_MASK;
+ }
+}
+
+/*!
+ * @brief SSP get data fifo address.
+ *
+ * @param base SSP peripheral base address.
+ * @return the ssp data fifo register address.
+ */
+static inline uint32_t SSP_GetFifoAddress(SSP_Type *base)
+{
+ return (uint32_t)&base->SSP_SSDR;
+}
+/* @} */
+
+/*!
+ * @name SSP transactional interface
+ * @{
+ */
+/*!
+ * @brief Creates the SSP send handle.
+ *
+ * @param base SSP peripheral base address.
+ * @param handle SSP handle pointer.
+ * @param callback Structure pointer to contain all callback functions.
+ * @param userData Callback function parameter.
+ */
+void SSP_TransferSendCreateHandle(SSP_Type *base,
+ ssp_handle_t *handle,
+ ssp_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Creates the SSP receive handle.
+ *
+ * @param base SSP peripheral base address.
+ * @param handle SSP handle pointer.
+ * @param callback Structure pointer to contain all callback functions.
+ * @param userData Callback function parameter.
+ */
+void SSP_TransferReceiveCreateHandle(SSP_Type *base,
+ ssp_handle_t *handle,
+ ssp_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Send the data using an interrupt and an asynchronous method.
+ *
+ * This function sends data and returns immediately. It doesn't wait for the transfer to complete or
+ * to encounter an error. The application can submit multiple transfer requests without waiting previous
+ * transfer request complete, since the SSP driver maintained a software transfer queue, the sizeof the queue
+ * is configurable by macro SSP_XFER_QUEUE_SIZE which indicates how many request can be submitted at the same time.
+ *
+ * @note Call API @ref SSP_TransferSendCreateHandle when calling this API.
+ *
+ * @param handle SSP handle.
+ * @param transfer transfer pointer.
+ * @retval #kStatus_InvalidArgument Argument is invalid.
+ * @retval #kSSP_TransferStatusBusy Busy transferring.
+ * @retval #kStatus_Success Operate successfully.
+ */
+status_t SSP_TransferSendNonBlocking(ssp_handle_t *handle, ssp_transfer_t *transfer);
+
+/*!
+ * @brief Receive the data using an interrupt and an asynchronous method.
+ *
+ * This function sends data and returns immediately. It doesn't wait for the transfer to complete or
+ * to encounter an error. The application can submit multiple transfer requests without waiting previous
+ * transfer request complete, since the SSP driver maintained a software transfer queue, the sizeof the queue
+ * is configurable by macro SSP_XFER_QUEUE_SIZE which indicates how many request can be submitted at the same time.
+ *
+ * @note Call API @ref SSP_TransferReceiveCreateHandle when calling this API.
+ *
+ * @param handle SSP handle.
+ * @param transfer transfer pointer.
+ * @retval #kStatus_InvalidArgument Argument is invalid.
+ * @retval #kSSP_TransferStatusBusy Busy transferring.
+ * @retval #kStatus_Success Operate successfully.
+ */
+status_t SSP_TransferReceiveNonBlocking(ssp_handle_t *handle, ssp_transfer_t *transfer);
+
+/*!
+ * @brief Aborts the current send.
+ *
+ * @note This API can be called any time when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param handle Pointer to the ssp_handle_t structure which stores the transfer state.
+ */
+void SSP_TransferAbortSend(ssp_handle_t *handle);
+
+/*!
+ * @brief Aborts the current IRQ receive.
+ *
+ * @note This API can be called when an interrupt non-blocking transfer initiates
+ * to abort the transfer early.
+ *
+ * @param handle Pointer to the ssp_handle_t structure which stores the transfer state.
+ */
+void SSP_TransferAbortReceive(ssp_handle_t *handle);
+
+/*!
+ * @brief IRQ handler for the SSP transmitter.
+ *
+ * This function deals with the IRQs on the given host controller.
+ *
+ * @param handle SSP handle.
+ */
+void SSP_TransferSendHandleIRQ(ssp_handle_t *handle);
+
+/*!
+ * @brief IRQ handler for the SSP receiver.
+ *
+ * This function deals with the IRQs on the given host controller.
+ *
+ * @param handle SSP handle.
+ */
+void SSP_TransferReceiveHandleIRQ(ssp_handle_t *handle);
+
+/* @} */
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+
+#endif /* _FSL_SSP_H_ */
diff --git a/drivers/mw320/ssp/fsl_ssp_dmac.c b/drivers/mw320/ssp/fsl_ssp_dmac.c
new file mode 100644
index 000000000..8f2610c82
--- /dev/null
+++ b/drivers/mw320/ssp/fsl_ssp_dmac.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_ssp_dmac.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.ssp_dmac"
+#endif
+
+/*! @brief Mapping of dmac burst length */
+#define DMAC_BURST_LENGTH_MAPPING(fifoWatermark) \
+ ((fifoWatermark) < 4U ? kDMAC_ChannelBurstLength1DataWidth : \
+ (fifoWatermark) < 8U ? kDMAC_ChannelBurstLength4DataWidth : \
+ (fifoWatermark) < 16U ? kDMAC_ChannelBurstLength8DataWidth : \
+ kDMAC_ChannelBurstLength16DataWidth)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief SSP EDMAC callback for send.
+ *
+ * @param handle pointer to ssp_dmac_handle_t structure which stores the transfer state.
+ * @param userData Parameter for user callback.
+ * @param transferStatus dmac transfer status
+ */
+static void SSP_TxDMACallback(dmac_handle_t *handle, void *userData, uint32_t transferStatus);
+
+/*!
+ * @brief SSP EDMAC callback for receive.
+ *
+ * @param handle pointer to ssp_dmac_handle_t structure which stores the transfer state.
+ * @param userData Parameter for user callback.
+ * @param transferStatus dmac transfer status
+ */
+static void SSP_RxDMACallback(dmac_handle_t *handle, void *userData, uint32_t transferStatus);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void SSP_TxDMACallback(dmac_handle_t *handle, void *userData, uint32_t transferStatus)
+{
+ ssp_dmac_handle_t *sspHandle = (ssp_dmac_handle_t *)userData;
+
+ if (transferStatus == (uint32_t)kDMAC_ChannelInterruptFlagTransferComplete)
+ {
+ /* Call callback function */
+ if (sspHandle->callback != NULL)
+ {
+ (sspHandle->callback)(sspHandle, kSSP_TransferStatusTxIdle, sspHandle->userData);
+ }
+
+ SSP_TransferAbortSendDMAC(sspHandle);
+ }
+}
+
+static void SSP_RxDMACallback(dmac_handle_t *handle, void *userData, uint32_t transferStatus)
+{
+ ssp_dmac_handle_t *sspHandle = (ssp_dmac_handle_t *)userData;
+
+ if (transferStatus == (uint32_t)kDMAC_ChannelInterruptFlagTransferComplete)
+ {
+ /* Call callback function */
+ if (sspHandle->callback != NULL)
+ {
+ (sspHandle->callback)(sspHandle, kSSP_TransferStatusRxIdle, sspHandle->userData);
+ }
+
+ SSP_TransferAbortReceiveDMAC(sspHandle);
+ }
+}
+
+/*!
+ * brief Initializes the SSP send DMAC handle.
+ *
+ * This function initializes the SSP send DMAC handle, must be called after the SSP mode configuration done.
+ *
+ * param base SSP base pointer.
+ * param handle SSP DMAC handle pointer.
+ * param base SSP peripheral base address.
+ * param callback Pointer to user callback function.
+ * param userData User parameter passed to the callback function.
+ * param dmacHandle DMAC handle pointer, this handle shall be static allocated by users.
+ */
+void SSP_TransferSendCreateHandleDMAC(
+ SSP_Type *base, ssp_dmac_handle_t *handle, ssp_dmac_callback_t callback, void *userData, dmac_handle_t *dmacHandle)
+{
+ assert((handle != NULL) && (dmacHandle != NULL));
+
+ uint32_t fifoWatermark = ((base->SSP_SSCR1 & SSP_SSP_SSCR1_TFT_MASK) >> SSP_SSP_SSCR1_TFT_SHIFT) + 1U;
+ uint32_t regBitWidth = base->SSP_SSCR0 & (SSP_SSP_SSCR0_DSS_MASK | SSP_SSP_SSCR0_EDSS_MASK);
+
+ /* Zero the handle */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ /* Set ssp base to handle */
+ handle->dmacHandle = dmacHandle;
+ handle->callback = callback;
+ handle->userData = userData;
+ handle->base = base;
+ handle->burstLength = DMAC_BURST_LENGTH_MAPPING(fifoWatermark);
+ handle->bitWidth =
+ regBitWidth == (uint32_t)kSSP_DataSize8Bit ? 1U : regBitWidth == (uint32_t)kSSP_DataSize16Bit ? 2U : 4U;
+
+ /* Set SSP state to idle */
+ handle->state = (uint32_t)kSSP_TransferStatusTxIdle;
+
+ /* Install callback for Tx dmac channel */
+ DMAC_TransferSetCallback(dmacHandle, SSP_TxDMACallback, handle);
+}
+
+/*!
+ * brief Initializes the SSP receive DMAC handle.
+ *
+ * This function initializes the SSP receive DMAC handle, must be called after the SSP mode configuration done.
+ *
+ * param base SSP base pointer.
+ * param handle SSP DMAC handle pointer.
+ * param base SSP peripheral base address.
+ * param callback Pointer to user callback function.
+ * param userData User parameter passed to the callback function.
+ * param dmacHandle DMAC handle pointer, this handle shall be static allocated by users.
+ */
+void SSP_TransferReceiveCreateHandleDMAC(
+ SSP_Type *base, ssp_dmac_handle_t *handle, ssp_dmac_callback_t callback, void *userData, dmac_handle_t *dmacHandle)
+{
+ assert((handle != NULL) && (dmacHandle != NULL));
+
+ uint32_t fifoWatermark = ((base->SSP_SSCR1 & SSP_SSP_SSCR1_RFT_MASK) >> SSP_SSP_SSCR1_RFT_SHIFT) + 1U;
+ uint32_t regBitWidth = base->SSP_SSCR0 & (SSP_SSP_SSCR0_DSS_MASK | SSP_SSP_SSCR0_EDSS_MASK);
+
+ /* Zero the handle */
+ (void)memset(handle, 0, sizeof(*handle));
+
+ /* Set ssp base to handle */
+ handle->dmacHandle = dmacHandle;
+ handle->callback = callback;
+ handle->userData = userData;
+ handle->base = base;
+ handle->burstLength = DMAC_BURST_LENGTH_MAPPING(fifoWatermark);
+ handle->bitWidth =
+ regBitWidth == (uint32_t)kSSP_DataSize8Bit ? 1U : regBitWidth == (uint32_t)kSSP_DataSize16Bit ? 2U : 4U;
+
+ /* Set SSP state to idle */
+ handle->state = (uint32_t)kSSP_TransferStatusTxIdle;
+
+ /* Install callback for Tx dmac channel */
+ DMAC_TransferSetCallback(dmacHandle, SSP_RxDMACallback, handle);
+}
+
+/*!
+ * brief Performs a non-blocking SSP transfer using DMAC.
+ *
+ * note This interface returns immediately after the transfer initiates.
+ *
+ * param base SSP base pointer.
+ * param handle SSP DMAC handle pointer.
+ * param xfer Pointer to DMAC transfer structure.
+ * retval kStatus_Success Successfully start the data receive.
+ * retval kStatus_SSP_TxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SSP_TransferSendDMAC(ssp_dmac_handle_t *handle, ssp_transfer_t *xfer)
+{
+ status_t error = kStatus_Success;
+ dmac_channel_transfer_config_t transferConfig;
+
+ /* Check if input parameter invalid */
+ if ((handle == NULL) || (xfer->dataBuffer == NULL) || (xfer->dataSize == 0U))
+ {
+ error = kStatus_InvalidArgument;
+ }
+ else
+ {
+ if (handle->state == (uint32_t)kSSP_TransferStatusBusy)
+ {
+ error = kSSP_TransferStatusBusy;
+ }
+ else
+ {
+ DMAC_GetChannelDefaultTransferConfig(&transferConfig, xfer->dataBuffer,
+ (uint32_t *)SSP_GetFifoAddress(handle->base),
+ (dmac_channel_transfer_width_t)handle->bitWidth, handle->burstLength,
+ xfer->dataSize, kDMAC_ChannelTransferMemoryToPeripheral);
+ transferConfig.interruptMask = (uint32_t)kDMAC_ChannelInterruptFlagTransferComplete;
+ if (DMAC_TransferSubmit(handle->dmacHandle, &transferConfig) != kStatus_Success)
+ {
+ error = kSSP_TransferStatusBusy;
+ }
+ else
+ {
+ /* Change the state of handle */
+ handle->state = (uint32_t)kSSP_TransferStatusBusy;
+
+ /* Start DMAC transfer */
+ DMAC_TransferStart(handle->dmacHandle);
+
+ /* Enable DMAC request and start SSP */
+ SSP_EnableSendDMARequest(handle->base, true);
+ /* Enable ssp port */
+ SSP_Enable(handle->base, true);
+ }
+ }
+ }
+
+ return error;
+}
+
+/*!
+ * brief Performs a non-blocking SSP transfer using DMAC.
+ *
+ * note This interface returns immediately after transfer initiates.
+ *
+ * param base SSP base pointer
+ * param handle SSP DMAC handle pointer.
+ * param xfer Pointer to DMAC transfer structure.
+ * retval kStatus_Success Successfully start the data receive.
+ * retval kStatus_SSP_RxBusy Previous receive still not finished.
+ * retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SSP_TransferReceiveDMAC(ssp_dmac_handle_t *handle, ssp_transfer_t *xfer)
+{
+ status_t error = kStatus_Success;
+ dmac_channel_transfer_config_t transferConfig;
+
+ /* Check if input parameter invalid */
+ if ((handle == NULL) || (xfer->dataBuffer == NULL) || (xfer->dataSize == 0U))
+ {
+ error = kStatus_InvalidArgument;
+ }
+ else
+ {
+ if (handle->state == (uint32_t)kSSP_TransferStatusBusy)
+ {
+ error = kSSP_TransferStatusBusy;
+ }
+ else
+ {
+ DMAC_GetChannelDefaultTransferConfig(&transferConfig, (uint32_t *)SSP_GetFifoAddress(handle->base),
+ xfer->dataBuffer, (dmac_channel_transfer_width_t)handle->bitWidth,
+ handle->burstLength, xfer->dataSize,
+ kDMAC_ChannelTransferPeripheralToMemory);
+ transferConfig.interruptMask = (uint32_t)kDMAC_ChannelInterruptFlagTransferComplete;
+ if (DMAC_TransferSubmit(handle->dmacHandle, &transferConfig) != kStatus_Success)
+ {
+ error = kSSP_TransferStatusBusy;
+ }
+ else
+ {
+ /* Change the state of handle */
+ handle->state = (uint32_t)kSSP_TransferStatusBusy;
+ /* Start DMAC transfer */
+ DMAC_TransferStart(handle->dmacHandle);
+ /* Enable DMAC request and start SSP */
+ SSP_EnableReceiveDMARequest(handle->base, true);
+ /* Enable ssp port */
+ SSP_Enable(handle->base, true);
+ }
+ }
+ }
+
+ return error;
+}
+
+/*!
+ * brief Aborts a SSP transfer using DMAC.
+ *
+ * param base SSP base pointer.
+ * param handle SSP DMAC handle pointer.
+ */
+void SSP_TransferAbortSendDMAC(ssp_dmac_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ /* Disable dmac */
+ DMAC_TransferStop(handle->dmacHandle);
+
+ /* Disable DMAC enable bit */
+ SSP_EnableSendDMARequest(handle->base, false);
+
+ /* Set the handle state */
+ handle->state = (uint32_t)kSSP_TransferStatusTxIdle;
+}
+
+/*!
+ * brief Aborts a SSP transfer using DMAC.
+ *
+ * param base SSP base pointer.
+ * param handle SSP DMAC handle pointer.
+ */
+void SSP_TransferAbortReceiveDMAC(ssp_dmac_handle_t *handle)
+{
+ assert(handle != NULL);
+
+ /* Disable dmac */
+ DMAC_TransferStop(handle->dmacHandle);
+
+ /* Disable DMAC enable bit */
+ SSP_EnableReceiveDMARequest(handle->base, false);
+
+ /* Set the handle state */
+ handle->state = (uint32_t)kSSP_TransferStatusRxIdle;
+}
diff --git a/drivers/mw320/ssp/fsl_ssp_dmac.h b/drivers/mw320/ssp/fsl_ssp_dmac.h
new file mode 100644
index 000000000..5bb4c7e87
--- /dev/null
+++ b/drivers/mw320/ssp/fsl_ssp_dmac.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_SSP_DMAC_H_
+#define _FSL_SSP_DMAC_H_
+
+#include "fsl_dmac.h"
+#include "fsl_ssp.h"
+
+/*!
+ * @addtogroup ssp_dma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_SSP_DMAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+typedef struct _ssp_dmac_handle ssp_dmac_handle_t;
+
+/*! @brief Define SSP DMAC callback */
+typedef void (*ssp_dmac_callback_t)(ssp_dmac_handle_t *handle, status_t transferStatus, void *userData);
+
+/*! @brief SSP DMAC transfer handle, users should not touch the content of the handle.
+ * A ssp_dmac_handle object can used to represent SSP TX or RX.
+ */
+struct _ssp_dmac_handle
+{
+ SSP_Type *base; /*!< SSP base address */
+ dmac_handle_t *dmacHandle; /*!< DMAC handler for SSP send */
+
+ uint32_t bitWidth; /*!< bit width */
+ dmac_channel_burst_length_t burstLength; /*!< dmac channel burst length */
+
+ uint32_t state; /*!< SSP DMAC transfer internal state */
+ ssp_dmac_callback_t callback; /*!< Callback for users while transfer finish or error occurred */
+ void *userData; /*!< User callback parameter */
+};
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+/*!
+ * @name DMAC Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the SSP master DMAC handle.
+ *
+ * This function initializes the SSP master DMAC handle, which can be used for other SSP master transactional APIs.
+ * Usually, for a specified SSP instance, call this API once to get the initialized handle.
+ *
+ * @param base SSP base pointer.
+ * @param handle SSP DMAC handle pointer.
+ * @param base SSP peripheral base address.
+ * @param callback Pointer to user callback function.
+ * @param userData User parameter passed to the callback function.
+ * @param dmacHandle DMAC handle pointer, this handle shall be static allocated by users.
+ */
+void SSP_TransferSendCreateHandleDMAC(
+ SSP_Type *base, ssp_dmac_handle_t *handle, ssp_dmac_callback_t callback, void *userData, dmac_handle_t *dmacHandle);
+
+/*!
+ * @brief Initializes the SSP receive DMAC handle.
+ *
+ * This function initializes the SSP receive DMAC handle, which can be used for other SSP master transactional APIs.
+ * Usually, for a specified SSP instance, call this API once to get the initialized handle.
+ *
+ * @param base SSP base pointer.
+ * @param handle SSP DMAC handle pointer.
+ * @param base SSP peripheral base address.
+ * @param callback Pointer to user callback function.
+ * @param userData User parameter passed to the callback function.
+ * @param dmacHandle DMAC handle pointer, this handle shall be static allocated by users.
+ */
+void SSP_TransferReceiveCreateHandleDMAC(
+ SSP_Type *base, ssp_dmac_handle_t *handle, ssp_dmac_callback_t callback, void *userData, dmac_handle_t *dmacHandle);
+
+/*!
+ * @brief Performs a non-blocking SSP transfer using DMAC.
+ *
+ * @note This interface returns immediately after the transfer initiates.
+ *
+ * @param handle SSP DMAC handle pointer.
+ * @param xfer Pointer to DMAC transfer structure.
+ * @retval kStatus_Success Successfully start the data receive.
+ * @retval kStatus_SSP_TxBusy Previous receive still not finished.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SSP_TransferSendDMAC(ssp_dmac_handle_t *handle, ssp_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking SSP transfer using DMAC.
+ *
+ * @note This interface returns immediately after transfer initiates.
+ *
+ * @param handle SSP DMAC handle pointer.
+ * @param xfer Pointer to DMAC transfer structure.
+ * @retval kStatus_Success Successfully start the data receive.
+ * @retval kStatus_SSP_RxBusy Previous receive still not finished.
+ * @retval kStatus_InvalidArgument The input parameter is invalid.
+ */
+status_t SSP_TransferReceiveDMAC(ssp_dmac_handle_t *handle, ssp_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a SSP transfer using DMAC.
+ *
+ * @param handle SSP DMAC handle pointer.
+ */
+void SSP_TransferAbortSendDMAC(ssp_dmac_handle_t *handle);
+
+/*!
+ * @brief Aborts a SSP transfer using DMAC.
+ *
+ * @param handle SSP DMAC handle pointer.
+ */
+void SSP_TransferAbortReceiveDMAC(ssp_dmac_handle_t *handle);
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif
diff --git a/drivers/mw320/uart/driver_mw_uart.cmake b/drivers/mw320/uart/driver_mw_uart.cmake
new file mode 100644
index 000000000..f5f2fc63c
--- /dev/null
+++ b/drivers/mw320/uart/driver_mw_uart.cmake
@@ -0,0 +1,14 @@
+#Description: MW_UART Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_uart component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_uart.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/uart/driver_mw_uart_dmac.cmake b/drivers/mw320/uart/driver_mw_uart_dmac.cmake
new file mode 100644
index 000000000..b20786fb6
--- /dev/null
+++ b/drivers/mw320/uart/driver_mw_uart_dmac.cmake
@@ -0,0 +1,15 @@
+#Description: MW_UART DMAC Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_uart_dmac component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_uart_dmac.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_mw_uart)
+include(driver_mw_dmac)
diff --git a/drivers/mw320/uart/fsl_uart.c b/drivers/mw320/uart/fsl_uart.c
new file mode 100644
index 000000000..4e5ee919a
--- /dev/null
+++ b/drivers/mw320/uart/fsl_uart.c
@@ -0,0 +1,1306 @@
+/*
+ * Copyright 2020,2021 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mw_uart"
+#endif
+
+/* UART transfer state. */
+enum
+{
+ kUART_TxIdle, /*!< TX idle. */
+ kUART_TxBusy, /*!< TX busy. */
+ kUART_RxIdle, /*!< RX idle. */
+ kUART_RxBusy, /*!< RX busy. */
+ kUART_RxFramingError, /* Rx framing error */
+ kUART_RxParityError /* Rx parity error */
+};
+
+/* Typedef for interrupt handler. */
+typedef void (*uart_isr_t)(UART_Type *base, uart_handle_t *handle);
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Check whether the RX ring buffer is full.
+ *
+ * @userData handle UART handle pointer.
+ * @retval true RX ring buffer is full.
+ * @retval false RX ring buffer is not full.
+ */
+static bool UART_TransferIsRxRingBufferFull(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Write to TX register using non-blocking method.
+ *
+ * This function writes data to the TX register directly, upper layer must make
+ * sure the TX register is empty or TX FIFO has empty room before calling this function.
+ *
+ * @note This function does not check whether all the data has been sent out to bus,
+ * so before disable TX, check kUART_TransmissionCompleteFlag to ensure the TX is
+ * finished.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX register using non-blocking method.
+ *
+ * This function reads data from the TX register directly, upper layer must make
+ * sure the RX register is full or TX FIFO has data before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of UART peripheral base address. */
+static UART_Type *const s_uartBases[] = UART_BASE_PTRS;
+/* Array of UART handle. */
+static uart_handle_t *s_uartHandle[ARRAY_SIZE(s_uartBases)];
+/* Array of UART IRQ number. */
+static const IRQn_Type s_uartIRQ[] = UART_IRQS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of UART clock name. */
+static const clock_ip_name_t s_uartClock[] = UART_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/* UART ISR for transactional APIs. */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+static uart_isr_t s_uartIsr = (uart_isr_t)DefaultISR;
+#else
+static uart_isr_t s_uartIsr;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static bool UART_TransferIsRxRingBufferFull(UART_Type *base, uart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ bool full;
+
+ if (UART_TransferGetRxRingBufferLength(base, handle) == (handle->rxRingBufferSize - 1U))
+ {
+ full = true;
+ }
+ else
+ {
+ full = false;
+ }
+ return full;
+}
+
+static void UART_WriteNonBlocking(UART_Type *base, const uint8_t *data, size_t length)
+{
+ assert(NULL != data);
+
+ size_t i;
+
+ /* The Non Blocking write data API assume user have ensured there is enough space in
+ peripheral to write. */
+ for (i = 0U; i < length; i++)
+ {
+ base->THR = data[i];
+ }
+}
+
+static void UART_ReadNonBlocking(UART_Type *base, uint8_t *data, size_t length)
+{
+ assert(NULL != data);
+
+ size_t i;
+ uint8_t dataMask = 0xFFU >> (base->LCR ^ 0x3U);
+
+ /* The Non Blocking read data API assume user have ensured there is enough space in
+ peripheral to write. */
+ for (i = 0; i < length; i++)
+ {
+ data[i] = (uint8_t)(base->RBR & dataMask);
+ }
+}
+
+/*!
+ * brief Get the UART instance from peripheral base address.
+ *
+ * param base UART peripheral base address.
+ * return UART instance.
+ */
+uint32_t UART_GetInstance(UART_Type *base)
+{
+ uint32_t instance;
+ /* Find the instance index from base address mappings. */
+ for (instance = 0U; instance < ARRAY_SIZE(s_uartBases); instance++)
+ {
+ if (s_uartBases[instance] == base)
+ {
+ break;
+ }
+ }
+ assert(instance < ARRAY_SIZE(s_uartBases));
+ return instance;
+}
+
+/*!
+ * brief Initializes an UART instance with the user configuration structure and the peripheral clock frequency.
+ *
+ * This function configures the UART module with user-defined settings. Call the UART_GetDefaultConfig function
+ * to get the configuration structure configured with default settings.
+ * The example below shows how to use this API to configure the UART.
+ * code
+ * uart_config_t uartConfig;
+ * UART_GetDefaultConfig(&uartConfig);
+ * UART_Init(UART1, &uartConfig, 20000000U);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param config Pointer to a user-defined configuration structure.
+ * param srcClock_Hz UART clock source frequency in Hz.
+ * retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success UART initialize succeed
+ */
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz)
+{
+ assert(NULL != config);
+ assert(0U != config->baudRate_Bps);
+
+ /* Reset UART registers */
+ base->DLL = 0x2U;
+ base->DLH = 0x0U;
+ base->IER = 0U;
+ base->FCR = 0U;
+ base->LCR = 0U;
+ base->MCR = 0U;
+ base->SCR = 0U;
+ base->ISR = 0U;
+ base->ABR = 0U;
+
+ if (UART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz) == kStatus_UART_BaudrateNotSupport)
+ {
+ return kStatus_UART_BaudrateNotSupport;
+ }
+ else
+ {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable uart clock */
+ CLOCK_EnableClock(s_uartClock[UART_GetInstance(base)]);
+#endif
+ }
+ UART_SetParity(base, config->parityMode);
+ UART_EnableStickyParity(base, config->enableStickyParity);
+ UART_SetDataBits(base, config->dataBitCount);
+ UART_SetStopBits(base, config->stopBitCount);
+ UART_SetFifoConfig(base, (uart_fifo_config_t *)&config->fifoConfig);
+ UART_SetAutoBaudConfig(base, (uart_autobaud_config_t *)&config->autoBaudConfig);
+ UART_SetInfraredConfig(base, (uart_infrared_config_t *)&config->infraredConfig);
+ UART_EnableHighSpeed(base, config->enableHighSpeed);
+ UART_EnableLoop(base, config->enableLoop);
+ UART_EnablCts(base, config->enableTxCTS);
+ UART_EnableRts(base, config->enableRxRTS);
+ UART_Enable(base, config->enable);
+
+ return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a UART instance.
+ *
+ * This function waits for transmit to complete, disables TX and RX, and disables the UART clock.
+ *
+ * param base UART peripheral base address.
+ */
+void UART_Deinit(UART_Type *base)
+{
+ /* Wait all data shift out */
+ while ((UART_GetStatusFlags(base) & (uint16_t)kUART_TxEmptyInterruptFlag) == 0U)
+ {
+ }
+ /* Disable module. */
+ UART_Enable(base, false);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Enable uart clock */
+ CLOCK_DisableClock(s_uartClock[UART_GetInstance(base)]);
+#endif
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the UART configuration structure to a default value.
+ * The example below shows how to use this API to configure the UART.
+ * code
+ * uart_config_t uartConfig;
+ * UART_GetDefaultConfig(&uartConfig);
+ * UART_Init(UART1, &uartConfig, 20000000U);
+ * endcode
+ *
+ * param config Pointer to a configuration structure.
+ */
+void UART_GetDefaultConfig(uart_config_t *config)
+{
+ assert(NULL != config);
+ /* Initializes the configure structure to zero. */
+ (void)memset(config, 0, sizeof(*config));
+
+ config->baudRate_Bps = 115200U;
+ config->parityMode = kUART_ParityDisabled;
+ config->enableStickyParity = false;
+ config->dataBitCount = kUART_Databits8;
+ config->stopBitCount = kUART_Stopbits1;
+ config->fifoConfig.txFifoWatermark = kUART_TxfifoEmpty;
+ config->fifoConfig.rxFifoWatermark = kUART_RxfifoByte1;
+ config->fifoConfig.resetTxFifo = false;
+ config->fifoConfig.resetRxFifo = false;
+ config->fifoConfig.fifoEnable = true;
+ config->autoBaudConfig.autoBaudEnable = false;
+ config->autoBaudConfig.baudProgramType = kUART_BaudrateProgramAuto;
+ config->autoBaudConfig.baudCalType = kUART_BaudrateCalFormula;
+ config->infraredConfig.txIrEnable = false;
+ config->infraredConfig.rxIrEnable = false;
+ config->infraredConfig.txIrPolarity = kUART_IrPositivePulse;
+ config->infraredConfig.rxIrPolarity = kUART_IrPositivePulse;
+ config->infraredConfig.irPulseWidth = kUART_IrPulsewidth3div16;
+ config->enableHighSpeed = true;
+ config->enableLoop = false;
+ config->enableTxCTS = false;
+ config->enableRxRTS = false;
+ config->enable = false;
+}
+
+/*!
+ * brief Gets UART hardware status flags.
+ *
+ * param base UART peripheral base address.
+ * return UART status flags, can be a single flag or several flags in #_uart_status_flags combined by OR.
+ */
+uint16_t UART_GetStatusFlags(UART_Type *base)
+{
+ uint16_t status = (uint16_t)base->LSR;
+ status |= (uint16_t)(base->IIR & 0x18UL) << 8U;
+ return status;
+}
+
+/*!
+ * brief Enables UART interrupts according to the provided mask.
+ *
+ * This function enables the UART interrupts according to the provided mask. The mask is a logical OR of enumeration
+ * members in #_uart_interrupt_enable.
+ *
+ * param base UART peripheral base address.
+ * param u16Interrupts The interrupt source mask, can be a single source or several sources in #_uart_interrupt_enable
+ * combined by OR.
+ */
+void UART_EnableInterrupts(UART_Type *base, uint8_t interrupts)
+{
+ base->MCR |= UART_MCR_OUT2_MASK;
+ if ((interrupts & (uint8_t)kUART_AutoBaudCompleteInterruptEnable) != 0U)
+ {
+ base->ABR |= UART_ABR_ABLIE_MASK;
+ }
+ base->IER |= (interrupts & 0x1FU);
+}
+
+/*!
+ * brief Disables UART interrupts according to the provided mask.
+ *
+ * This function disables the UART interrupts according to the provided mask. The mask is a logical OR of enumeration
+ * members in #_uart_interrupt_enable.
+ *
+ * param base UART peripheral base address.
+ * param interrupts The interrupt source mask, can be a single source or several sources in #_uart_interrupt_enable
+ * combined by OR.
+ */
+void UART_DisableInterrupts(UART_Type *base, uint8_t interrupts)
+{
+ if ((interrupts & (uint8_t)kUART_AutoBaudCompleteInterruptEnable) != 0U)
+ {
+ base->ABR &= ~UART_ABR_ABLIE_MASK;
+ }
+ base->IER &= ~(interrupts & 0x1FU);
+}
+
+/*!
+ * brief Gets the enabled UART interrupts.
+ *
+ * This function gets the enabled UART interrupts. The enabled interrupts are returned as the logical OR value of the
+ * enumerators #_uart_interrupt_enable.
+ *
+ * param base UART peripheral base address.
+ * return The interrupt source mask, can be a single source or several sources in #_uart_interrupt_enable combined
+ * by OR.
+ */
+uint8_t UART_GetEnabledInterrupts(UART_Type *base)
+{
+ uint8_t interrupts = (uint8_t)base->IER & 0x1FU;
+ if ((base->ABR & UART_ABR_ABLIE_MASK) != 0U)
+ {
+ interrupts |= (uint8_t)kUART_AutoBaudCompleteInterruptEnable;
+ }
+ return interrupts;
+}
+
+/*!
+ * brief Sets the UART instance baudrate.
+ *
+ * This API configures the UART module baudrate. This API can be used to update
+ * the UART module baudrate after the UART module is initialized by the UART_Init.
+ * code
+ * UART_SetBaudRate(UART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base UART peripheral base address.
+ * param baudRate_Bps UART baudrate to be set.
+ * param srcClock_Hz UART clock source frequency in HZ.
+ * retval kStatus_UART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * retval kStatus_Success Set baudrate succeeded.
+ */
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
+{
+ assert((baudRate_Bps != 0U) && (srcClock_Hz != 0U));
+
+ uint16_t div = (uint16_t)(srcClock_Hz * 10U / baudRate_Bps / 16U + 5U) / 10U;
+ uint32_t actualBaud = srcClock_Hz / (uint32_t)div / 16U;
+ uint32_t diff = actualBaud > baudRate_Bps ? actualBaud - baudRate_Bps : baudRate_Bps - actualBaud;
+ if (diff > (baudRate_Bps / 100U * 3U))
+ {
+ return kStatus_UART_BaudrateNotSupport;
+ }
+ else
+ {
+ /* Configure the Baud Rate */
+ base->LCR |= UART_LCR_DLAB_MASK;
+ base->DLH = (div >> 8U) & 0xFFU;
+ base->DLL = div & 0xFFU;
+ base->LCR &= ~UART_LCR_DLAB_MASK;
+ return kStatus_Success;
+ }
+}
+
+/*!
+ * brief Sets the UART auto baud configuration.
+ *
+ * This API configures the UART auto baud function, including enable/disable, calculation type, program type.
+ *
+ * param base UART peripheral base address.
+ * param autoBaudConfig pointer to UART auto baud configuration.
+ */
+void UART_SetAutoBaudConfig(UART_Type *base, uart_autobaud_config_t *autoBaudConfig)
+{
+ assert(autoBaudConfig != NULL);
+
+ base->ABR = (base->ABR & ~(UART_ABR_ABT_MASK | UART_ABR_ABUP_MASK | UART_ABR_ABE_MASK)) |
+ UART_ABR_ABT(autoBaudConfig->baudCalType) | UART_ABR_ABUP(autoBaudConfig->baudProgramType) |
+ UART_ABR_ABE(autoBaudConfig->autoBaudEnable);
+}
+
+/*!
+ * brief Set DL register according to Auto Baud Detect Count value.
+ *
+ * param base UART peripheral base address.
+ */
+void UART_SetAutoBaud(UART_Type *base)
+{
+ uint16_t autoBaudCount = UART_GetAutoBaudCount(base);
+ /* Configure the Baud Rate */
+ base->LCR |= UART_LCR_DLAB_MASK;
+ base->DLH = (autoBaudCount >> 12U) & 0xFF;
+ base->DLL = (autoBaudCount >> 4U) & 0xFF;
+ base->LCR &= ~UART_LCR_DLAB_MASK;
+}
+
+/*!
+ * brief Sets the UART auto baud configuration.
+ *
+ * This API configures the UART auto baud function, including enable/disable, calculation type, program type.
+ *
+ * param base UART peripheral base address.
+ * param infraredConfig pointer to UART infrared configuration.
+ */
+void UART_SetInfraredConfig(UART_Type *base, uart_infrared_config_t *infraredConfig)
+{
+ assert(infraredConfig != NULL);
+
+ base->ISR = UART_ISR_RXPL(infraredConfig->rxIrPolarity) | UART_ISR_TXPL(infraredConfig->txIrPolarity) |
+ UART_ISR_XMODE(infraredConfig->irPulseWidth) | UART_ISR_RCVEIR(infraredConfig->rxIrEnable) |
+ UART_ISR_XMITIR(infraredConfig->txIrEnable);
+}
+
+/*!
+ * brief Read 9 bit data from the UART peripheral.
+ *
+ * Before calling this API, make sure parity is enabled, and rx register full or data available in rx FIFO.
+ *
+ * param base UART peripheral base address.
+ * return The received data
+ */
+uint16_t UART_Read9bits(UART_Type *base)
+{
+ uint16_t data;
+ uint8_t i;
+ uint8_t parity = 0U;
+
+ /* Receive data */
+ data = (uint16_t)UART_ReadByte(base);
+
+ for (i = 0U; i < 8U; i++)
+ {
+ parity ^= ((data >> i) & 0x1U);
+ }
+
+ /* Check the parity error status bit */
+ parity ^= (base->LSR & UART_LSR_PE_MASK) >> UART_LSR_PE_SHIFT;
+ /* Check current parity setting */
+ if ((base->LCR & UART_LCR_EPS_MASK) != 0U)
+ {
+ parity ^= 0x1U;
+ }
+ /* get bit9 according parity error status */
+ data |= parity << 8U;
+
+ return (data & 0x1FF);
+}
+
+/*!
+ * brief Writes TX register using a blocking method.
+ *
+ * This function polls the TX register, waits TX register to be empty or TX FIFO
+ * have room then writes data to the TX buffer.
+ *
+ * param base UART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ */
+status_t UART_WriteBlocking(UART_Type *base, const uint8_t *data, uint32_t length)
+{
+ assert(NULL != data);
+
+ const uint8_t *dataAddress = data;
+
+#if UART_RETRY_TIMES
+ uint32_t waitTimes;
+#endif
+
+ while (0U != length)
+ {
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while ((0U == (base->LSR & UART_LSR_TDRQ_MASK)) && (0U != --waitTimes))
+#else
+ while (0U == (base->LSR & UART_LSR_TDRQ_MASK))
+#endif
+ {
+ }
+#if UART_RETRY_TIMES
+ if (0U == waitTimes)
+ {
+ return kStatus_UART_Timeout;
+ }
+#endif
+ base->THR = *(dataAddress);
+ dataAddress++;
+ length--;
+ }
+ /* Ensure all the data in the transmit buffer are sent out to bus. */
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while ((0U == (base->LSR & UART_LSR_TEMT_MASK)) && (0U != --waitTimes))
+#else
+ while (0U == (base->LSR & UART_LSR_TEMT_MASK))
+#endif
+ {
+ }
+#if UART_RETRY_TIMES
+ if (0U == waitTimes)
+ {
+ return kStatus_UART_Timeout;
+ }
+#endif
+ return kStatus_Success;
+}
+
+/*!
+ * brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits RX register to be full or RX FIFO
+ * have data, then reads data from the RX register.
+ *
+ * param base UART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_Fail Receiver error occurred while receiving data.
+ * retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data
+ * retval kStatus_UART_NoiseError Noise error occurred while receiving data
+ * retval kStatus_UART_FramingErrorFraming error occurred while receiving data
+ * retval kStatus_UART_ParityError Parity error occurred while receiving data
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, uint32_t length)
+{
+ assert(NULL != data);
+
+ status_t status = kStatus_Success;
+ uint16_t statusFlag;
+ uint8_t dataMask = 0xFFU >> (base->LCR ^ 0x3U);
+
+#if UART_RETRY_TIMES
+ uint32_t waitTimes;
+#endif
+
+ while (0U != (length--))
+ {
+ statusFlag = UART_GetStatusFlags(base);
+#if UART_RETRY_TIMES
+ waitTimes = UART_RETRY_TIMES;
+ while (((statusFlag & (uint16_t)kUART_RxDataReadyInterruptFlag) == 0U) && (0U != --waitTimes))
+ {
+ if (0U == waitTimes)
+ {
+ status = kStatus_UART_Timeout;
+ break;
+ }
+#else
+ while ((statusFlag & (uint16_t)kUART_RxDataReadyInterruptFlag) == 0U)
+ {
+#endif
+ if (0U != (statusFlag & (uint16_t)kUART_RxOverrunInterruptFlag))
+ {
+ status = kStatus_UART_RxHardwareOverrun;
+ /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other
+ * error flags*/
+ break;
+ }
+
+ if (0U != (statusFlag & (uint16_t)kUART_ParityErrorInterruptFlag))
+ {
+ status = kStatus_UART_ParityError;
+ }
+
+ if (0U != (statusFlag & (uint16_t)kUART_FramingErrorInterruptFLag))
+ {
+ status = kStatus_UART_FramingError;
+ }
+
+ if (0U != (statusFlag & (uint16_t)kUART_FifoErrorInterruptFlag))
+ {
+ status = kStatus_UART_FifoError;
+ }
+ if (kStatus_Success != status)
+ {
+ break;
+ }
+ statusFlag = UART_GetStatusFlags(base);
+ }
+
+ if (kStatus_Success == status)
+ {
+ *(data++) = (uint8_t)(base->RBR & dataMask);
+ }
+ else
+ {
+ break;
+ }
+ }
+ return status;
+}
+
+/*!
+ * brief Initializes the UART handle.
+ *
+ * This function initializes the UART handle, which can be used for other UART
+ * transactional APIs. Usually, for a specified UART instance,
+ * call this API once to get the initialized handle.
+ *
+ * The UART driver supports the "background" receiving, which means that user can set up
+ * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
+ * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ * The ring buffer is disabled if passing NULL as @p ringBuffer.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param callback Callback function.
+ * param userData User data.
+ */
+void UART_TransferCreateHandle(UART_Type *base,
+ uart_handle_t *handle,
+ uart_transfer_callback_t callback,
+ void *userData)
+{
+ assert(NULL != handle);
+
+ uint32_t instance;
+
+ /* Zero the handle. */
+ (void)memset(handle, 0, sizeof(uart_handle_t));
+
+ /* Set data mask */
+ handle->dataMask = 0xFFU >> (base->LCR ^ 0x3U);
+
+ /* Set the TX/RX state. */
+ handle->rxState = (uint8_t)kUART_RxIdle;
+ handle->txState = (uint8_t)kUART_TxIdle;
+
+ /* Set the callback and user data. */
+ handle->callback = callback;
+ handle->userData = userData;
+
+ /* Get instance from peripheral base address. */
+ instance = UART_GetInstance(base);
+
+ /* Save the handle in global variables to support the double weak mechanism. */
+ s_uartHandle[instance] = handle;
+ s_uartIsr = UART_TransferHandleIRQ;
+
+ /* Enable interrupt in NVIC. */
+ (void)EnableIRQ(s_uartIRQ[instance]);
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
+void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+ assert(NULL != handle);
+ assert(NULL != ringBuffer);
+
+ /* Setup the ring buffer address */
+ handle->rxRingBuffer = ringBuffer;
+ handle->rxRingBufferSize = ringBufferSize;
+ handle->rxRingBufferHead = 0U;
+ handle->rxRingBufferTail = 0U;
+
+ /* Enable the interrupt to accept the data when user need the ring buffer. */
+ UART_EnableInterrupts(base, (uint16_t)kUART_RxDataReadyInterruptEnable | (uint16_t)kUART_RxStatusInterruptEnable);
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ if (handle->rxState == (uint8_t)kUART_RxIdle)
+ {
+ UART_DisableInterrupts(base,
+ (uint16_t)kUART_RxDataReadyInterruptEnable | (uint16_t)kUART_RxStatusInterruptEnable);
+ }
+
+ handle->rxRingBuffer = NULL;
+ handle->rxRingBufferSize = 0U;
+ handle->rxRingBufferHead = 0U;
+ handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t UART_TransferGetRxRingBufferLength(UART_Type *base, uart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ size_t size;
+ size_t tmpRxRingBufferSize = handle->rxRingBufferSize;
+ uint16_t tmpRxRingBufferTail = handle->rxRingBufferTail;
+ uint16_t tmpRxRingBufferHead = handle->rxRingBufferHead;
+
+ if (tmpRxRingBufferTail > tmpRxRingBufferHead)
+ {
+ size = ((size_t)tmpRxRingBufferHead + tmpRxRingBufferSize - (size_t)tmpRxRingBufferTail);
+ }
+ else
+ {
+ size = ((size_t)tmpRxRingBufferHead - (size_t)tmpRxRingBufferTail);
+ }
+
+ return size;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function send data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data written to the transmitter register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * note The kStatus_UART_TxIdle is passed to the upper layer when all data are written
+ * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
+ * check the kUART_TransmissionCompleteFlag to ensure that the transmit is finished.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART transfer structure, see #uart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to the TX register.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer)
+{
+ assert(NULL != handle);
+ assert(NULL != xfer);
+ assert(NULL != xfer->data);
+ assert(0U != xfer->dataSize);
+
+ status_t status;
+
+ /* Return error if current TX busy. */
+ if ((uint8_t)kUART_TxBusy == handle->txState)
+ {
+ status = kStatus_UART_TxBusy;
+ }
+ else
+ {
+ handle->txData = xfer->data;
+ handle->txDataSize = xfer->dataSize;
+ handle->txDataSizeAll = xfer->dataSize;
+ handle->txState = (uint8_t)kUART_TxBusy;
+
+ /* Enable transmitter interrupt. */
+ UART_EnableInterrupts(base, (uint16_t)kUART_TxDataRequestInterruptEnable);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Gets the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by an interrupt method.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
+{
+ assert(NULL != handle);
+ assert(NULL != count);
+
+ status_t status = kStatus_Success;
+ size_t tmptxDataSize = handle->txDataSize;
+
+ if ((uint8_t)kUART_TxIdle == handle->txState)
+ {
+ status = kStatus_NoTransferInProgress;
+ }
+ else
+ {
+ *count = handle->txDataSizeAll - tmptxDataSize;
+ }
+ return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are not sent out.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ UART_DisableInterrupts(base, (uint16_t)kUART_TxDataRequestInterruptEnable);
+
+ handle->txDataSize = 0;
+ handle->txState = (uint8_t)kUART_TxIdle;
+}
+
+/*!
+ * brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function
+ * which returns without waiting to ensure that all data are received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough for read, the receive
+ * request is saved by the UART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes a status parameter kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
+ * The 5 bytes are copied to xfer->data, which returns with the
+ * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
+ * saved from xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART transfer structure, see uart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * @retval kStatus_UART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveNonBlocking(UART_Type *base,
+ uart_handle_t *handle,
+ uart_transfer_t *xfer,
+ size_t *receivedBytes)
+{
+ assert(NULL != handle);
+ assert(NULL != xfer);
+ assert(NULL != xfer->data);
+ assert(0U != xfer->dataSize);
+
+ uint32_t i;
+ status_t status;
+ /* How many bytes to copy from ring buffer to user memory. */
+ size_t bytesToCopy = 0U;
+ /* How many bytes to receive. */
+ size_t bytesToReceive;
+ /* How many bytes currently have received. */
+ size_t bytesCurrentReceived;
+
+ /* How to get data:
+ 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+ to uart handle, enable interrupt to store received data to xfer->data. When
+ all data received, trigger callback.
+ 2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+ If there are enough data in ring buffer, copy them to xfer->data and return.
+ If there are not enough data in ring buffer, copy all of them to xfer->data,
+ save the xfer->data remained empty space to uart handle, receive data
+ to this empty space and trigger callback when finished. */
+
+ if ((uint8_t)kUART_RxBusy == handle->rxState)
+ {
+ status = kStatus_UART_RxBusy;
+ }
+ else
+ {
+ bytesToReceive = xfer->dataSize;
+ bytesCurrentReceived = 0;
+
+ /* If RX ring buffer is used. */
+ if (NULL != handle->rxRingBuffer)
+ {
+ /* Disable UART RX IRQ, protect ring buffer. */
+ UART_DisableInterrupts(base, (uint16_t)kUART_RxDataReadyInterruptEnable);
+
+ /* How many bytes in RX ring buffer currently. */
+ bytesToCopy = UART_TransferGetRxRingBufferLength(base, handle);
+
+ if (0U != bytesToCopy)
+ {
+ bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+
+ bytesToReceive -= bytesToCopy;
+
+ /* Copy data from ring buffer to user memory. */
+ for (i = 0U; i < bytesToCopy; i++)
+ {
+ xfer->data[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail];
+ bytesCurrentReceived++;
+
+ /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+ if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferTail = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferTail++;
+ }
+ }
+ }
+
+ /* If ring buffer does not have enough data, still need to read more data. */
+ if (0U != bytesToReceive)
+ {
+ /* No data in ring buffer, save the request to UART handle. */
+ handle->rxData = &xfer->data[bytesCurrentReceived];
+ handle->rxDataSize = bytesToReceive;
+ handle->rxDataSizeAll = bytesToReceive;
+ handle->rxState = (uint8_t)kUART_RxBusy;
+ }
+ /* Enable UART RX IRQ if previously enabled. */
+ UART_EnableInterrupts(base, (uint16_t)kUART_RxDataReadyInterruptEnable);
+
+ /* Call user callback since all data are received. */
+ if (0U == bytesToReceive)
+ {
+ if (NULL != handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
+ }
+ }
+ }
+ /* Ring buffer not used. */
+ else
+ {
+ handle->rxData = xfer->data;
+ handle->rxDataSize = bytesToReceive;
+ handle->rxDataSizeAll = bytesToReceive;
+ handle->rxState = (uint8_t)kUART_RxBusy;
+
+ /* Enable RX interrupt. */
+ UART_EnableInterrupts(base,
+ (uint16_t)kUART_RxDataReadyInterruptEnable | (uint16_t)kUART_RxStatusInterruptEnable);
+ }
+
+ /* Return the how many bytes have read. */
+ if (NULL != receivedBytes)
+ {
+ *receivedBytes = bytesCurrentReceived;
+ }
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count)
+{
+ assert(NULL != handle);
+ assert(NULL != count);
+
+ status_t status = kStatus_Success;
+ size_t tmprxDataSize = handle->rxDataSize;
+
+ if ((uint8_t)kUART_RxIdle == handle->rxState)
+ {
+ status = kStatus_NoTransferInProgress;
+ }
+ else
+ {
+ *count = handle->rxDataSizeAll - tmprxDataSize;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+ if (NULL == handle->rxRingBuffer)
+ {
+ /* Disable RX interrupt. */
+ UART_DisableInterrupts(base,
+ (uint16_t)kUART_RxDataReadyInterruptEnable | (uint16_t)kUART_RxStatusInterruptEnable);
+ }
+
+ handle->rxDataSize = 0U;
+ handle->rxState = (uint8_t)kUART_RxIdle;
+}
+
+/*!
+ * brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle)
+{
+ assert(NULL != handle);
+
+ uint8_t count;
+ uint8_t tempCount;
+ uint16_t status = UART_GetStatusFlags(base);
+ uint8_t enabledInterrupts = UART_GetEnabledInterrupts(base);
+ uint16_t tpmRxRingBufferHead;
+ uint32_t tpmData;
+
+ /* If RX framing error */
+ if (((uint16_t)kUART_FramingErrorInterruptFLag & status) != 0U)
+ {
+ handle->rxState = (uint8_t)kUART_RxFramingError;
+ handle->rxDataSize = 0U;
+ /* Trigger callback. */
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_UART_FramingError, handle->userData);
+ }
+ }
+
+ /* If RX parity error */
+ if (((uint16_t)kUART_ParityErrorInterruptFlag & status) != 0U)
+ {
+ handle->rxState = (uint8_t)kUART_RxParityError;
+ handle->rxDataSize = 0U;
+ /* Trigger callback. */
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_UART_ParityError, handle->userData);
+ }
+ }
+
+ /* If RX overrun. */
+ if (((uint16_t)kUART_RxOverrunInterruptFlag & status) != 0U)
+ {
+ /* Trigger callback. */
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData);
+ }
+ }
+
+ /* If RX FIFO error. */
+ if (((uint16_t)kUART_FifoErrorInterruptFlag & status) != 0U)
+ {
+ /* Trigger callback. */
+ if (handle->callback != NULL)
+ {
+ handle->callback(base, handle, kStatus_UART_RxHardwareOverrun, handle->userData);
+ }
+ }
+
+ /* Receive data register full */
+ if ((0U != ((uint16_t)kUART_RxDataReadyInterruptFlag & status)) &&
+ (0U != ((uint8_t)kUART_RxDataReadyInterruptEnable & enabledInterrupts)))
+ {
+ /* Get the size that can be stored into buffer for this interrupt. */
+ if (UART_IsFifoEnabled(base))
+ {
+ count = UART_GetRxFifoLevel(base);
+ }
+ else
+ {
+ count = 1;
+ }
+
+ /* If handle->rxDataSize is not 0, save data to handle->rxData first. */
+ while ((0U != handle->rxDataSize) && (0U != count))
+ {
+ tempCount = (uint8_t)MIN(handle->rxDataSize, count);
+
+ /* Using non block API to read the data from the registers. */
+ UART_ReadNonBlocking(base, handle->rxData, tempCount);
+ handle->rxData = &handle->rxData[tempCount];
+ handle->rxDataSize -= tempCount;
+ count -= tempCount;
+
+ /* If all the data required for upper layer is ready, trigger callback. */
+ if (0U == handle->rxDataSize)
+ {
+ handle->rxState = (uint8_t)kUART_RxIdle;
+
+ if (NULL != handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_RxIdle, handle->userData);
+ }
+ }
+ }
+
+ /* If use RX ring buffer, receive data to ring buffer. */
+ if (NULL != handle->rxRingBuffer)
+ {
+ while (0U != count--)
+ {
+ /* If RX ring buffer is full, trigger callback to notify ring buffer overrun. */
+ if (UART_TransferIsRxRingBufferFull(base, handle))
+ {
+ if (NULL != handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_RxRingBufferOverrun, handle->userData);
+ }
+ }
+
+ /* If ring buffer is still full after callback function, the oldest data is over write. */
+ if (UART_TransferIsRxRingBufferFull(base, handle))
+ {
+ /* Increase handle->rxRingBufferTail to make room for new data. */
+ if (((uint32_t)handle->rxRingBufferTail + 1U) == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferTail = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferTail++;
+ }
+ }
+
+ /* Read data. */
+ tpmRxRingBufferHead = handle->rxRingBufferHead;
+ tpmData = UART_ReadByte(base);
+ handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)(tpmData & handle->dataMask);
+
+ /* Increase handle->rxRingBufferHead. */
+ if (((uint32_t)handle->rxRingBufferHead + 1U) == handle->rxRingBufferSize)
+ {
+ handle->rxRingBufferHead = 0U;
+ }
+ else
+ {
+ handle->rxRingBufferHead++;
+ }
+ }
+ }
+ /* If no receive requst pending, stop RX interrupt. */
+ else if (0U == handle->rxDataSize)
+ {
+ UART_DisableInterrupts(
+ base, (uint16_t)kUART_RxDataReadyInterruptEnable | (uint16_t)kUART_RxStatusInterruptEnable);
+ }
+ else
+ {
+ /* Avoid MISRA 15.7 */
+ }
+ }
+
+ /* Send data register request and the interrupt is enabled. */
+ if ((0U != ((uint16_t)kUART_TxDataRequestInterruptFlag & status)) &&
+ (0U != ((uint8_t)kUART_TxDataRequestInterruptEnable & enabledInterrupts)))
+ {
+ /* Get the bytes that available at this moment. */
+ if (UART_IsFifoEnabled(base))
+ {
+ /* Since we do not have access to the tx data count on FIFO, and FCR is write only so
+ we do not have the access to the tx FIFO water mark setting either, so safely assume
+ half of the FIFO is available */
+ count = 32U;
+ }
+ else
+ {
+ count = 1U;
+ }
+
+ while ((0U != handle->txDataSize) && (0U != count))
+ {
+ tempCount = (uint8_t)MIN(handle->txDataSize, count);
+
+ /* Using non block API to write the data to the registers. */
+ UART_WriteNonBlocking(base, handle->txData, tempCount);
+ handle->txData = &handle->txData[tempCount];
+ handle->txDataSize -= tempCount;
+ count -= tempCount;
+ }
+ }
+
+ /* Send data register empty and the interrupt is enabled. */
+ if ((0U != ((uint16_t)kUART_TxEmptyInterruptFlag & status)) &&
+ (0U != ((uint8_t)kUART_TxDataRequestInterruptEnable & enabledInterrupts)))
+ {
+ /* If all the data are written to data register, notify user with the callback, then TX finished. */
+ if (0U == handle->txDataSize)
+ {
+ /* Set txState to idle only when all data has been sent out to bus. */
+ handle->txState = (uint8_t)kUART_TxIdle;
+ /* Disable transmission complete interrupt. */
+ UART_DisableInterrupts(base, (uint8_t)kUART_TxDataRequestInterruptEnable);
+
+ /* Trigger callback. */
+ if (NULL != handle->callback)
+ {
+ handle->callback(base, handle, kStatus_UART_TxIdle, handle->userData);
+ }
+ }
+ }
+}
+
+/*!
+ * brief UART Error IRQ handle function.
+ *
+ * This function handles the UART error IRQ request.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ */
+void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle)
+{
+ /* To be implemented by User. */
+}
+
+#if defined(UART0)
+void UART0_DriverIRQHandler(void);
+void UART0_DriverIRQHandler(void)
+{
+ s_uartIsr(UART0, s_uartHandle[0]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(UART1)
+void UART1_DriverIRQHandler(void);
+void UART1_DriverIRQHandler(void)
+{
+ s_uartIsr(UART1, s_uartHandle[1]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(UART2)
+void UART2_DriverIRQHandler(void);
+void UART2_DriverIRQHandler(void)
+{
+ s_uartIsr(UART2, s_uartHandle[2]);
+ SDK_ISR_EXIT_BARRIER;
+}
+#endif
diff --git a/drivers/mw320/uart/fsl_uart.h b/drivers/mw320/uart/fsl_uart.h
new file mode 100644
index 000000000..067989583
--- /dev/null
+++ b/drivers/mw320/uart/fsl_uart.h
@@ -0,0 +1,1055 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_UART_H_
+#define _FSL_UART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup uart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief UART driver version. */
+#define FSL_UART_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* ============================================= General Control Macro ============================================== */
+/*! @brief Retry times for waiting flag. */
+#ifndef UART_RETRY_TIMES
+#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is asserts/deasserts. */
+#endif
+
+/*! @brief Error codes for the UART driver. */
+enum
+{
+ kStatus_UART_TxBusy = MAKE_STATUS(kStatusGroup_UART, 0), /*!< TX busy */
+ kStatus_UART_RxBusy = MAKE_STATUS(kStatusGroup_UART, 1), /*!< RX busy */
+ kStatus_UART_TxIdle = MAKE_STATUS(kStatusGroup_UART, 2), /*!< UART transmitter is idle. */
+ kStatus_UART_RxIdle = MAKE_STATUS(kStatusGroup_UART, 3), /*!< UART receiver is idle. */
+ kStatus_UART_FlagCannotClearManually = MAKE_STATUS(kStatusGroup_UART, 4), /*!< Some flag can't manually clear */
+ kStatus_UART_Error = MAKE_STATUS(kStatusGroup_UART, 5), /*!< Error happens on UART. */
+ kStatus_UART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_UART, 6), /*!< UART RX software ring buffer overrun. */
+ kStatus_UART_RxHardwareOverrun = MAKE_STATUS(kStatusGroup_UART, 7), /*!< UART RX receiver overrun. */
+ kStatus_UART_FifoError = MAKE_STATUS(kStatusGroup_UART, 8), /*!< UART noise error. */
+ kStatus_UART_FramingError = MAKE_STATUS(kStatusGroup_UART, 9), /*!< UART framing error. */
+ kStatus_UART_ParityError = MAKE_STATUS(kStatusGroup_UART, 10), /*!< UART parity error. */
+ kStatus_UART_BaudrateNotSupport =
+ MAKE_STATUS(kStatusGroup_UART, 11), /*!< Baudrate is not support in current clock source */
+ kStatus_UART_IdleLineDetected = MAKE_STATUS(kStatusGroup_UART, 12), /*!< IDLE flag. */
+ kStatus_UART_Timeout = MAKE_STATUS(kStatusGroup_UART, 13), /*!< UART times out. */
+ kStatus_UART_RxFifoError = MAKE_STATUS(kStatusGroup_UART, 14), /*!< UART Rx FIFO error. */
+};
+
+/* ================================== Functional Group Structure/Enumeration List =================================== */
+/* ----------------------------------------------- Interrupt Sub-group ---------------------------------------------- */
+/*!
+ * @brief UART interrupt configuration structure, default settings all disabled.
+ *
+ * This structure contains the settings for all of the UART interrupt configurations.
+ */
+enum _uart_interrupt_enable
+{
+ kUART_RxDataReadyInterruptEnable =
+ (UART_IER_RAVIE_MASK), /*!< Receiver data ready interrupt, caused by rx register full when FIFO disabled or rx
+ data count above water mark when FIFO enabled. bit 0 */
+ kUART_TxDataRequestInterruptEnable =
+ (UART_IER_TIE_MASK), /*!< Transmitter data request interrupt, caused by tx register empty when FIFO disabled or
+ tx data count below water mark when FIFO enabled. bit 1 */
+ kUART_RxStatusInterruptEnable =
+ (UART_IER_RLSE_MASK), /*!< Receiver line status interrupt, caused by such status as rx over run, framing/parity
+ error and break detect. bit 2 */
+ kUART_ModemStatusChangeInterruptEnable =
+ (UART_IER_MIE_MASK), /*!< Modem status change interrupt, caused by RTS/CTS pin status change. bit 3 */
+ kUART_RxTimeoutInterruptEnable = (UART_IER_RTOIE_MASK), /*!< Receiver timeout interrupt. bit 4 */
+ kUART_AutoBaudCompleteInterruptEnable =
+ (UART_ABR_ABLIE_MASK << 4), /*!< Auto baud completes programing baud rate divisor interrupt. bit 5 */
+};
+
+/* ---------------------------------------- Hardware Status Flags Sub-group ----------------------------------------- */
+/*!
+ * @brief UART status flags.
+ *
+ * This provides constants for the UART status flags for use in the UART functions.
+ */
+enum _uart_status_flags
+{
+ kUART_RxDataReadyInterruptFlag =
+ (UART_LSR_DR_MASK), /*!< Receiver data ready flag, self cleared by reading data out. bit 0 */
+ kUART_RxOverrunInterruptFlag = (UART_LSR_OE_MASK), /*!< Receiver overrun flag, can cause rx status interrupt, slef
+ cleared when reading the LSR(line status register). bit 1 */
+ kUART_ParityErrorInterruptFlag = (UART_LSR_PE_MASK), /*!< Parity error flag, can cause rx status interrupt, self
+ cleared when reading the LSR(line status register). bit 2 */
+ kUART_FramingErrorInterruptFLag =
+ (UART_LSR_FE_MASK), /*!< Framing error flag, can cause rx status interrupt, self cleared when reading the
+ LSR(line status register). bit 3 */
+ kUART_BreakDetectInterruptFlag = (UART_LSR_BI_MASK), /*!< Break detect flag, can cause rx status interrupt, self
+ cleared when reading the LSR(line status register). bit 4 */
+ kUART_TxDataRequestInterruptFlag =
+ (UART_LSR_TDRQ_MASK), /*!< Transmitter data request flag, self cleared by pushing data to tx FIFO until data
+ count exceed water mark. bit 5 */
+ kUART_TxEmptyInterruptFlag =
+ (UART_LSR_TEMT_MASK), /*!< Transmitter empty flag, self cleared by pushing data to tx FIFO. bit 6 */
+ kUART_FifoErrorInterruptFlag =
+ (UART_LSR_FIFOE_MASK), /*!< FIFO error flag, self cleared by empting the rx FIFO. bit 7 */
+ kUART_RxTimeoutInterruptFlag = (UART_IIR_TOD_MASK << 8), /*!< Receiver timeout interrupt flag. bit 11 */
+ kUART_AutoBaudCompleteInterruptFlag =
+ (UART_IIR_ABL_MASK << 8), /*!< Auto baud completes programing baud rate divisor flag. bit 12 */
+};
+
+/* --------------------------------------- Peripheral Configuration Sub-group --------------------------------------- */
+/*! @brief UART parity mode. */
+typedef enum _uart_parity_mode
+{
+ kUART_ParityDisabled = 0x0U, /*!< Parity disabled, bit setting: LCR[PEN] = 0 */
+ kUART_ParityOdd = 0x1U, /*!< Parity enabled, type odd, bit setting: LCR[EPS]|[PEN] = 01 */
+ kUART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: LCR[EPS]|[PEN] = 11 */
+} uart_parity_mode_t;
+
+/*! @brief UART data bits count. */
+typedef enum _uart_data_bits
+{
+ kUART_Databits5 = 0x0U, /*!< UART data bits length: 5 bits */
+ kUART_Databits6, /*!< UART data bits length: 6 bits */
+ kUART_Databits7, /*!< UART data bits length: 7 bits */
+ kUART_Databits8, /*!< UART data bits length: 8 bits */
+} uart_data_bits_t;
+
+/*! @brief UART stop bit count. */
+typedef enum _uart_stop_bit_count
+{
+ kUART_Stopbits1, /*!< UART stop bits length: 1 bits */
+ kUART_Stopbits2, /*!< UART stop bits length: 2 bits */
+} uart_stop_bit_count_t;
+
+/*!
+ * @brief UART TX FIFO watermark level definition
+ */
+typedef enum _uart_txfifo_watermark
+{
+ kUART_TxfifoHalfEmpty = 0U, /*!< UART Transmit Interrupt Level: half empty */
+ kUART_TxfifoEmpty, /*!< UART Transmit Interrupt Level: full empty */
+} uart_txfifo_watermark_t;
+
+/*!
+ * @brief UART RX FIFO watermark level definition
+ */
+typedef enum _uart_rxfifo_watermark
+{
+ kUART_RxfifoByte1 = 0U, /*!< 1 byte or more in rx fifo causes interrupt(Not valid in dma mode) */
+ kUART_RxfifoBytes8, /*!< 8 byte or more in rx fifo causes interrupt */
+ kUART_RxfifoBytes16, /*!< 16 byte or more in rx fifo causes interrupt */
+ kUART_RxfifoBytes32, /*!< 32 byte or more in rx fifo causes interrupt */
+} uart_rxfifo_watermark_t;
+
+/*!
+ * @brief UART FIFO Configuration Structure definition
+ */
+typedef struct _uart_fifo_config
+{
+ uart_txfifo_watermark_t txFifoWatermark; /*!< TX FIFO watermark. FCR[TIL] */
+ uart_rxfifo_watermark_t rxFifoWatermark; /*!< RX FIFO watermark. FCR[ITL] */
+ bool resetTxFifo; /*!< Tx FIFO reset. FCR[RESETTF] */
+ bool resetRxFifo; /*!< Rx FIFO reset. FCR[RESETRF] */
+ bool fifoEnable; /*!< FIFO enable. FCR[TRFIFOE] */
+} uart_fifo_config_t;
+
+/*!
+ * @brief UART Auto Baud Calculation type definition
+ */
+typedef enum _uart_autobaud_program
+{
+ kUART_BaudrateProgramManual = 0, /*!< User calculates and programs UART divisor latch register using the value UART
+ stored in Auto-Baud Count Register. */
+ kUART_BaudrateProgramAuto, /*!< UART programs UART Divisor Latch Register automatically. */
+} uart_autobaud_program_t;
+
+/*!
+ * @brief UART Auto Baud Calculation type definition
+ *
+ * When choosing kUART_BaudrateProgramAuto for baud rate program method, this is used to configure the baudrate
+ * calculation method of UART.
+ */
+typedef enum _uart_autobaud_calculation
+{
+ kUART_BaudrateCalFormula = 0, /*!< Formula is used to calculate baud rate, any baud rate can be programmed by the
+ UART but could fail below 28.8 Kbps. */
+ kUART_BaudrateCalTable, /*!< Table is used to calculate baud rate, allows any baud rate above 28.8 Kbps. Below 28.8
+ Kbps the only baud rates that can be programmed by the UART are 19200, 14400, 9600, 4800,
+ 1200, and 300. */
+} uart_autobaud_calculation_t;
+
+/*!
+ * @brief UART Auto baud detect and set Configuration Structure definition
+ */
+typedef struct _uart_autobaud_config
+{
+ bool autoBaudEnable; /*!< Enable or Disable Auto Baud Function. ABR[ABE] */
+ uart_autobaud_program_t baudProgramType; /*!< Uart Auto Baud Program type. ABR[ABUP] */
+ uart_autobaud_calculation_t baudCalType; /*!< Uart Auto Baud calculation type. ABR[ABT] */
+} uart_autobaud_config_t;
+
+/*!
+ * @brief UART Infrared mode ncoder/Decoder Polarity type definition
+ */
+typedef enum _uart_infrared_polarity
+{
+ kUART_IrPositivePulse = 0, /*!< UART IR Encoder/Decoder takes positive pulse as zero */
+ kUART_IrNegativePulse, /*!< UART IR Encoder/Decoder takes negative pulse as zero */
+} uart_infrared_polarity_t;
+
+/*!
+ * @brief UART Infrared Transmit Pulse Width type definition
+ */
+typedef enum _uart_infrared_pulsewidth
+{
+ kUART_IrPulsewidth3div16 = 0, /*!< UART IR Transmit pulse width is 3/16 of a bit time width */
+ kUART_IrPulsewidth1p6us, /*!< UART IR Transmit pulse width is 1.6us width */
+} uart_infrared_pulsewidth_t;
+
+/*!
+ * @brief UART Infrared Configuration Structure type definition
+ */
+typedef struct _uart_infrared_config
+{
+ bool txIrEnable; /*!< Enable or Disable Uart Transmit IR Function. ISR[XMITIR] */
+ bool rxIrEnable; /*!< Enable or Disable Uart Receive IR Function. ISR[RCVEIR] */
+ uart_infrared_polarity_t txIrPolarity; /*!< Transmit IR Polarity type. ISR[TXPL] */
+ uart_infrared_polarity_t rxIrPolarity; /*!< Receive IR Polarity type. ISR[RXPL] */
+ uart_infrared_pulsewidth_t irPulseWidth; /*!< IR Pulse Width type. ISR[XMODE] */
+} uart_infrared_config_t;
+
+/* ----------------------------------- Module Initialize/De-initialize Sub-group ------------------------------------ */
+/*! @brief UART configuration structure. */
+typedef struct _uart_config
+{
+ uint32_t baudRate_Bps; /*!< UART baud rate. DLL, DLH */
+ uart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd. LCR[EPS][PEN] */
+ bool enableStickyParity; /*!< Sticky parity, when enabled the parity bit remains unchanged and is opposite to PEN
+ bit. LCR[STKYP] */
+ uart_data_bits_t dataBitCount; /*!< Data bits count, eight (default), seven. LCR[WLS10] */
+ uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits. LCR[STB] */
+ uart_fifo_config_t fifoConfig; /*!< FIFO configuration. */
+ uart_autobaud_config_t autoBaudConfig; /*!< Auto baud detect and set configuration. */
+ uart_infrared_config_t infraredConfig; /*!< Infrared function configuration. */
+ bool enableHighSpeed; /*!< High speed enable. IER[HSE] = 1 */
+ bool enableLoop; /*!< Loop mode MCR[LOOP] */
+ bool enableTxCTS; /*!< TX CTS enable. MCR[AFE] = 1 */
+ bool enableRxRTS; /*!< RX RTS enable. To enable RTS, CTS must be enabled. MCR[AFE][RTS] = 11 */
+ bool enable; /*!< Enable UART. IER[UUE] */
+} uart_config_t;
+
+/* ================================= Transactional Group Structure/Enumeration List ================================ */
+/* Forward declaration of the handle typedef. */
+typedef struct _uart_handle_t uart_handle_t;
+
+/*!
+ * @brief UART interrupt transfer callback function definition
+ *
+ * Defines the interface of user callback function used in UART interrupt transfer using transactional APIs. The
+ * callback function shall be defined and declared in application level by user. Before starting UART transmiting or
+ * receiving by calling @ref UART_TransferSendNonBlocking or @ref UART_TransferReceiveNonBlocking, call
+ * @ref UART_TransferCreateHandle to install the user callback. When the transmiting or receiving ends or any bus error
+ * like hardware overrun occurs, user callback will be invoked by driver.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Transfer handle.
+ * @param status Transfer status
+ * @param userData Pointer to user specified data or structure etc.
+ */
+typedef void (*uart_transfer_callback_t)(UART_Type *base, uart_handle_t *handle, status_t status, void *userData);
+
+/*!
+ * @brief UART transfer handle
+ *
+ * @note If user wants to use the transactional API to transfer data in interrupt way, one UART instance should and can
+ * only be allocated one handle.
+ * @note The handle is maintained by UART driver internally, which means the transfer state is retained and user shall
+ * not modify its state #txState or #rxState in application level. If user only wish to use transactional APIs
+ * without understanding its machanism, it is not necessary to understand these members.
+ */
+struct _uart_handle_t
+{
+ uint8_t dataMask;
+ uint8_t *volatile txData; /*!< Address of remaining data to send. */
+ volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+ size_t txDataSizeAll; /*!< Size of the data to send out. */
+ uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
+ volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+ size_t rxDataSizeAll; /*!< Size of the data to receive. */
+
+ uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
+ size_t rxRingBufferSize; /*!< Size of the ring buffer. */
+ volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+ volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+ uart_transfer_callback_t callback; /*!< Callback function. */
+ void *userData; /*!< uart callback function parameter.*/
+
+ volatile uint8_t txState; /*!< TX transfer state. */
+ volatile uint8_t rxState; /*!< RX transfer state. */
+};
+
+/*! @brief UART transfer structure. */
+typedef struct _uart_transfer
+{
+ uint8_t *data; /*!< The buffer pointer of data to be transferred.*/
+ uint32_t dataSize; /*!< The byte count to be transferred. */
+} uart_transfer_t;
+/* ============================== End of Transactional Group Structure/Enumeration List ============================ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Get the UART instance from peripheral base address.
+ *
+ * @param base UART peripheral base address.
+ * @return UART instance.
+ */
+uint32_t UART_GetInstance(UART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes an UART instance with the user configuration structure and the peripheral clock frequency.
+ *
+ * This function configures the UART module with user-defined settings. Call the UART_GetDefaultConfig function
+ * to get the configuration structure configured with default settings.
+ * The example below shows how to use this API to configure the UART.
+ * @code
+ * uart_config_t uartConfig;
+ * UART_GetDefaultConfig(&uartConfig);
+ * UART_Init(UART1, &uartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param config Pointer to a user-defined configuration structure.
+ * @param srcClock_Hz UART clock source frequency in Hz.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success UART initialize succeed
+ */
+status_t UART_Init(UART_Type *base, const uart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for transmit to complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param base UART peripheral base address.
+ */
+void UART_Deinit(UART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the UART configuration structure to a default value.
+ * The example below shows how to use this API to configure the UART.
+ * @code
+ * uart_config_t uartConfig;
+ * UART_GetDefaultConfig(&uartConfig);
+ * UART_Init(UART1, &uartConfig, 20000000U);
+ * @endcode
+ *
+ * @param config Pointer to a configuration structure.
+ */
+void UART_GetDefaultConfig(uart_config_t *config);
+/* @} */
+
+/*!
+ * @name Hardware Status Flags
+ * @{
+ */
+/*!
+ * @brief Gets UART hardware status flags.
+ *
+ * @param base UART peripheral base address.
+ * @return UART status flags, can be a single flag or several flags in #_uart_status_flags combined by OR.
+ */
+uint16_t UART_GetStatusFlags(UART_Type *base);
+/* @} */
+
+/*!
+ * @name Interrupt
+ * @{
+ */
+/*!
+ * @brief Enables UART interrupts according to the provided mask.
+ *
+ * This function enables the UART interrupts according to the provided mask. The mask is a logical OR of enumeration
+ * members in #_uart_interrupt_enable.
+ *
+ * @param base UART peripheral base address.
+ * @param interrupts The interrupt source mask, can be a single source or several sources in #_uart_interrupt_enable
+ * combined by OR.
+ */
+void UART_EnableInterrupts(UART_Type *base, uint8_t interrupts);
+
+/*!
+ * @brief Disables UART interrupts according to the provided mask.
+ *
+ * This function disables the UART interrupts according to the provided mask. The mask is a logical OR of enumeration
+ * members in #_uart_interrupt_enable.
+ *
+ * @param base UART peripheral base address.
+ * @param interrupts The interrupt source mask, can be a single source or several sources in #_uart_interrupt_enable
+ * combined by OR.
+ */
+void UART_DisableInterrupts(UART_Type *base, uint8_t interrupts);
+
+/*!
+ * @brief Gets the enabled UART interrupts.
+ *
+ * This function gets the enabled UART interrupts. The enabled interrupts are returned as the logical OR value of the
+ * enumerators #_uart_interrupt_enable.
+ *
+ * @param base UART peripheral base address.
+ * @return The interrupt source mask, can be a single source or several sources in #_uart_interrupt_enable combined
+ * by OR.
+ */
+uint8_t UART_GetEnabledInterrupts(UART_Type *base);
+/* @} */
+
+/*!
+ * @name General Peripheral Configuration
+ * @{
+ */
+/*!
+ * @brief Enables or disables the UART module.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_Enable(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IER |= UART_IER_UUE_MASK;
+ }
+ else
+ {
+ base->IER &= ~UART_IER_UUE_MASK;
+ }
+}
+
+/*!
+ * @brief Enables or disables the UART high speed mode.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableHighSpeed(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IER |= UART_IER_HSE_MASK;
+ }
+ else
+ {
+ base->IER &= ~UART_IER_HSE_MASK;
+ }
+}
+
+/*!
+ * @brief Enables or disables the UART dma request.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableDMA(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->IER |= UART_IER_DMAE_MASK;
+ }
+ else
+ {
+ base->IER &= ~UART_IER_DMAE_MASK;
+ }
+}
+
+/*!
+ * @brief Set the UART FIFO configuration
+ *
+ * @note The FIFO configuration register FCR is write only, so we have no way of getting current FIFO configuration.
+ * In this case any modification of FCR must contain the full FIFO configuration, including tx/rx watermark, whether to
+ * reset tx/rx FIFO, and tx/rx FIFO enable.
+ *
+ * @param base UART peripheral base address
+ * @param fifoConfig Pointer to FIFO configuration structure
+ */
+static inline void UART_SetFifoConfig(UART_Type *base, uart_fifo_config_t *fifoConfig)
+{
+ base->FCR = UART_FCR_ITL(fifoConfig->rxFifoWatermark) | UART_FCR_TIL(fifoConfig->txFifoWatermark) |
+ UART_FCR_RESETRF(fifoConfig->resetRxFifo) | UART_FCR_RESETTF(fifoConfig->resetTxFifo) |
+ UART_FCR_TRFIFOE(fifoConfig->fifoEnable);
+}
+
+/*!
+ * @brief Checks the UART FIFO enable status.
+ *
+ * @param base UART peripheral base address.
+ * @return true is FIFO is enabled.
+ */
+static inline bool UART_IsFifoEnabled(UART_Type *base)
+{
+ return ((base->IIR & UART_IIR_FIFOES10_MASK) != 0U);
+}
+
+/*!
+ * @brief Enables or disables the UART CTS input.
+ *
+ * @note The RTS output can not be enabled without enabling the CTS input, which means disabling CTS will
+ * disables RTS as well.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnablCts(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MCR |= UART_MCR_AFE_MASK;
+ }
+ else
+ {
+ base->MCR &= ~UART_MCR_AFE_MASK;
+ }
+}
+
+/*!
+ * @brief Enables or disables the UART RTS output.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableRts(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MCR |= UART_MCR_RTS_MASK;
+ }
+ else
+ {
+ base->MCR &= ~UART_MCR_RTS_MASK;
+ }
+}
+
+/*!
+ * @brief Checks the CTS pin status.
+ *
+ * @param base UART peripheral base address.
+ * @return true is CTS pin is asserted meaning free to send data.
+ */
+static inline bool UART_IsCtsAsserted(UART_Type *base)
+{
+ return ((base->MSR & UART_MSR_CTS_MASK) == 0U);
+}
+
+/*!
+ * @brief Enables or disables the UART loop mode.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableLoop(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->MCR |= UART_MCR_LOOP_MASK;
+ }
+ else
+ {
+ base->MCR &= ~UART_MCR_LOOP_MASK;
+ }
+}
+
+/*!
+ * @brief Set the UART parity type
+ *
+ * @param base UART peripheral base address.
+ * @param parity parity type
+ */
+static inline void UART_SetParity(UART_Type *base, uart_parity_mode_t parity)
+{
+ if (parity == kUART_ParityDisabled)
+ {
+ base->LCR &= ~UART_LCR_PEN_MASK;
+ }
+ else
+ {
+ base->LCR |= UART_LCR_PEN_MASK;
+ if (parity == kUART_ParityOdd)
+ {
+ base->LCR &= ~UART_LCR_EPS_MASK;
+ }
+ else
+ {
+ base->LCR |= UART_LCR_EPS_MASK;
+ }
+ }
+}
+
+/*!
+ * @brief Enables or disables sticky parity
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableStickyParity(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->LCR |= UART_LCR_STKYP_MASK;
+ }
+ else
+ {
+ base->LCR &= ~UART_LCR_STKYP_MASK;
+ }
+}
+
+/*!
+ * @brief Set the UART data bits
+ *
+ * @param base UART peripheral base address.
+ * @param dataBits bits to set
+ */
+static inline void UART_SetDataBits(UART_Type *base, uart_data_bits_t dataBits)
+{
+ base->LCR |= (base->LCR & (~UART_LCR_WLS10_MASK)) | UART_LCR_WLS10((uint8_t)dataBits);
+}
+
+/*!
+ * @brief Set the UART stop bits
+ *
+ * @param base UART peripheral base address.
+ * @param stopBits stop bits to set
+ */
+static inline void UART_SetStopBits(UART_Type *base, uart_stop_bit_count_t stopBits)
+{
+ base->LCR |= (base->LCR & (~UART_LCR_STB_MASK)) | UART_LCR_STB((uint8_t)stopBits);
+}
+
+/*!
+ * @brief Get current UART receive FIFO level.
+ *
+ * @param base Select the UART port, should be kUART1_Id, kUART2_Id.
+ * @return The number of data entries in the receive FIFO
+ */
+static inline uint8_t UART_GetRxFifoLevel(UART_Type *base)
+{
+ return (uint8_t)base->RFOR;
+}
+
+/*!
+ * @brief Sets the UART instance baudrate.
+ *
+ * This API configures the UART module baudrate. This API can be used to update
+ * the UART module baudrate after the UART module is initialized by the UART_Init.
+ * @code
+ * UART_SetBaudRate(UART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base UART peripheral base address.
+ * @param baudRate_Bps UART baudrate to be set.
+ * @param srcClock_Hz UART clock source frequency in HZ.
+ * @retval kStatus_UART_BaudrateNotSupport Baudrate is not supported in the current clock source.
+ * @retval kStatus_Success Set baudrate succeeded.
+ */
+status_t UART_SetBaudRate(UART_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Sets the UART auto baud configuration.
+ *
+ * This API configures the UART auto baud function, including enable/disable, calculation type, program type.
+ *
+ * @param base UART peripheral base address.
+ * @param autoBaudConfig pointer to UART auto baud configuration.
+ */
+void UART_SetAutoBaudConfig(UART_Type *base, uart_autobaud_config_t *autoBaudConfig);
+
+/*!
+ * @brief Get UART auto baud count number.
+ *
+ * @param base UART peripheral base address
+ * @return none
+ */
+static inline uint16_t UART_GetAutoBaudCount(UART_Type *base)
+{
+ return (uint16_t)base->ACR;
+}
+
+/*!
+ * @brief Set DL register according to Auto Baud Detect Count value.
+ *
+ * @param base UART peripheral base address.
+ */
+void UART_SetAutoBaud(UART_Type *base);
+
+/*!
+ * @brief Sets the UART auto baud configuration.
+ *
+ * This API configures the UART auto baud function, including enable/disable, calculation type, program type.
+ *
+ * @param base UART peripheral base address.
+ * @param infraredConfig pointer to UART infrared configuration.
+ */
+void UART_SetInfraredConfig(UART_Type *base, uart_infrared_config_t *infraredConfig);
+/* @} */
+
+/*!
+ * @name Bus Operation
+ * @{
+ */
+/*!
+ * @brief Gets the UART receive data register byte address.
+ *
+ * This function returns the UART receive data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base UART peripheral base address.
+ * @return UART data register byte addresses which are used both by the transmitter and the receiver.
+ */
+static inline uint32_t UART_GetRxDataRegisterAddress(UART_Type *base)
+{
+ return (uint32_t)((uint8_t *)&(base->RBR));
+}
+
+/*!
+ * @brief Gets the UART transmit data register byte address.
+ *
+ * This function returns the UART transmit data register address, which is mainly used by DMA/eDMA.
+ *
+ * @param base UART peripheral base address.
+ * @return UART data register byte addresses which are used both by the transmitter and the receiver.
+ */
+static inline uint32_t UART_GetTxDataRegisterAddress(UART_Type *base)
+{
+ return (uint32_t)((uint8_t *)&(base->THR));
+}
+
+/*!
+ * @brief Writes to the TX register.
+ *
+ * This function writes data to the TX register directly. The upper layer must ensure
+ * that the TX register is empty or TX FIFO has room before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void UART_WriteByte(UART_Type *base, uint8_t data)
+{
+ base->THR = data;
+}
+
+/*!
+ * @brief Reads the RX register directly.
+ *
+ * This function reads data from the RX register directly. The upper layer must
+ * ensure that the RX register is full or that the TX FIFO has data before calling this function.
+ *
+ * @param base UART peripheral base address.
+ * @return The byte read from UART data register.
+ */
+static inline uint8_t UART_ReadByte(UART_Type *base)
+{
+ return (uint8_t)(base->RBR);
+}
+
+/*!
+ * @brief Send 9 bit data to the UART peripheral.
+ *
+ * Before calling this API, make sure parity and sticky parity are enabled, and tx register empty or room in tx FIFO.
+ *
+ * @param base UART peripheral base address.
+ * @param data The data to be sent
+ */
+static inline void UART_Write9bits(UART_Type *base, uint16_t data)
+{
+ if (((data >> 8U) & 0x1U) != 0U)
+ {
+ base->LCR &= ~UART_LCR_EPS_MASK;
+ }
+ else
+ {
+ base->LCR |= UART_LCR_EPS_MASK;
+ }
+
+ /* Send data */
+ UART_WriteByte(base, (uint8_t)data);
+}
+
+/*!
+ * @brief Read 9 bit data from the UART peripheral.
+ *
+ * Before calling this API, make sure parity is enabled, and rx register full or data available in rx FIFO.
+ *
+ * @param base UART peripheral base address.
+ * @return The received data
+ */
+uint16_t UART_Read9bits(UART_Type *base);
+
+/*!
+ * @brief Writes TX register using a blocking method.
+ *
+ * This function polls the TX register, waits TX register to be empty or TX FIFO
+ * have room then writes data to the TX buffer.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+status_t UART_WriteBlocking(UART_Type *base, const uint8_t *data, uint32_t length);
+
+/*!
+ * @brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits RX register to be full or RX FIFO
+ * have data, then reads data from the RX register.
+ *
+ * @param base UART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_Fail Receiver error occurred while receiving data.
+ * @retval kStatus_UART_RxHardwareOverrun Receiver overrun occurred while receiving data
+ * @retval kStatus_UART_NoiseError Noise error occurred while receiving data
+ * @retval kStatus_UART_FramingErrorFraming error occurred while receiving data
+ * @retval kStatus_UART_ParityError Parity error occurred while receiving data
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t UART_ReadBlocking(UART_Type *base, uint8_t *data, uint32_t length);
+
+/*!
+ * @brief Enables or disables break condition.
+ *
+ * When break condition is enabled tx pin is pulled low by UART, when disabled the pin is high.
+ *
+ * @param base UART peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void UART_EnableBreakCondition(UART_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->LCR |= UART_LCR_SB_MASK;
+ }
+ else
+ {
+ base->LCR &= ~UART_LCR_SB_MASK;
+ }
+}
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+/*!
+ * @brief Initializes the UART handle.
+ *
+ * This function initializes the UART handle, which can be used for other UART
+ * transactional APIs. Usually, for a specified UART instance,
+ * call this API once to get the initialized handle.
+ *
+ * The UART driver supports the "background" receiving, which means that user can set up
+ * an RX ring buffer optionally. Data received is stored into the ring buffer even when the
+ * user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ * The ring buffer is disabled if passing NULL as @p ringBuffer.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param callback Callback function.
+ * @param userData User data.
+ */
+void UART_TransferCreateHandle(UART_Type *base,
+ uart_handle_t *handle,
+ uart_transfer_callback_t callback,
+ void *userData);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific UART handle.
+ *
+ * When the RX ring buffer is used, data received is stored into the ring buffer even when
+ * the user doesn't call the UART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param ringBuffer Start address of ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void UART_TransferStartRingBuffer(UART_Type *base, uart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferStopRingBuffer(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t UART_TransferGetRxRingBufferLength(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function send data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data written to the transmitter register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The kStatus_UART_TxIdle is passed to the upper layer when all data are written
+ * to the TX register. However, there is no check to ensure that all the data sent out. Before disabling the TX,
+ * check the kUART_TransmissionCompleteFlag to ensure that the transmit is finished.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART transfer structure, see #uart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_UART_TxBusy Previous transmission still not finished, data not all written to the TX register.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendNonBlocking(UART_Type *base, uart_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Gets the number of bytes that have been sent out to bus.
+ *
+ * This function gets the number of bytes that have been sent out to bus by an interrupt method.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetSendCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are not sent out.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferAbortSend(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief Receives a buffer of data using the interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function
+ * which returns without waiting to ensure that all data are received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough for read, the receive
+ * request is saved by the UART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes a status parameter kStatus_UART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in ring buffer.
+ * The 5 bytes are copied to xfer->data, which returns with the
+ * parameter @p receivedBytes set to 5. For the remaining 5 bytes, the newly arrived data is
+ * saved from xfer->data[5]. When 5 bytes are received, the UART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART transfer structure, see uart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into the transmit queue.
+ * @retval kStatus_UART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveNonBlocking(UART_Type *base,
+ uart_handle_t *handle,
+ uart_transfer_t *xfer,
+ size_t *receivedBytes);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t UART_TransferGetReceiveCount(UART_Type *base, uart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferAbortReceive(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferHandleIRQ(UART_Type *base, uart_handle_t *handle);
+
+/*!
+ * @brief UART Error IRQ handle function.
+ *
+ * This function handles the UART error IRQ request.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ */
+void UART_TransferHandleErrorIRQ(UART_Type *base, uart_handle_t *handle);
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} End of group uart_driver*/
+
+#endif /* _FSL_UART_H_ */
diff --git a/drivers/mw320/uart/fsl_uart_dmac.c b/drivers/mw320/uart/fsl_uart_dmac.c
new file mode 100644
index 000000000..70be3d2b3
--- /dev/null
+++ b/drivers/mw320/uart/fsl_uart_dmac.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_uart_dmac.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.uart_dmac"
+#endif
+
+/* UART DMAC transfer state. */
+enum
+{
+ kUART_TxIdle, /* TX idle. */
+ kUART_TxBusy, /* TX busy. */
+ kUART_RxIdle, /* RX idle. */
+ kUART_RxBusy /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief UART DMAC send finished callback function.
+ *
+ * This function is called when UART DMAC send finished. It disables the UART
+ * TX DMAC request and sends @ref kStatus_UART_TxIdle to UART callback.
+ *
+ * @param handle The DMAC handle.
+ * @param param Callback function parameter.
+ * @param status The mask of channel status.
+ */
+static void UART_TransferSendDMACCallback(dmac_handle_t *handle, void *param, uint32_t status);
+
+/*!
+ * @brief UART DMAC receive finished callback function.
+ *
+ * This function is called when UART DMAC receive finished. It disables the UART
+ * RX DMAC request and sends @ref kStatus_UART_RxIdle to UART callback.
+ *
+ * @param handle The DMAC handle.
+ * @param param Callback function parameter.
+ * @param status The mask of channel status.
+ */
+static void UART_TransferReceiveDMACCallback(dmac_handle_t *handle, void *param, uint32_t status);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void UART_TransferSendDMACCallback(dmac_handle_t *handle, void *param, uint32_t status)
+{
+ assert((handle != NULL) && (param != NULL));
+
+ uart_dmac_handle_t *uartHandle = (uart_dmac_handle_t *)param;
+
+ /* Disable interrupt. */
+ DMAC_DisableChannelInterrupts(handle->base, handle->channel, kDMAC_ChannelInterruptFlagTransferComplete);
+
+ uartHandle->txState = (uint8_t)kUART_TxIdle;
+
+ /* Ensure all the data in the transmit buffer are sent out to bus. */
+ while (0U == (uartHandle->base->LSR & UART_LSR_TEMT_MASK))
+ {
+ }
+
+ if (uartHandle->callback != NULL)
+ {
+ uartHandle->callback(uartHandle->base, uartHandle, kStatus_UART_TxIdle, uartHandle->userData);
+ }
+}
+
+static void UART_TransferReceiveDMACCallback(dmac_handle_t *handle, void *param, uint32_t status)
+{
+ assert((handle != NULL) && (param != NULL));
+
+ uart_dmac_handle_t *uartHandle = (uart_dmac_handle_t *)param;
+
+ /* Disable interrupt. */
+ DMAC_DisableChannelInterrupts(handle->base, handle->channel, kDMAC_ChannelInterruptFlagTransferComplete);
+
+ uartHandle->rxState = (uint8_t)kUART_RxIdle;
+
+ if (uartHandle->callback != NULL)
+ {
+ uartHandle->callback(uartHandle->base, uartHandle, kStatus_UART_RxIdle, uartHandle->userData);
+ }
+}
+
+/*!
+ * brief Initializes the UART handle which is used in transactional functions and sets the callback.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to the uart_dmac_handle_t structure.
+ * param callback UART callback, NULL means no callback.
+ * param userData User callback function data.
+ * param rxDmaHandle User requested DMAC handle for the RX DMAC transfer.
+ * param txDmaHandle User requested DMAC handle for the TX DMAC transfer.
+ */
+void UART_TransferCreateHandleDMAC(UART_Type *base,
+ uart_dmac_handle_t *handle,
+ uart_dmac_transfer_callback_t callback,
+ void *userData,
+ dmac_handle_t *txDmaHandle,
+ dmac_handle_t *rxDmaHandle)
+{
+ assert((handle != NULL) && (txDmaHandle != NULL) && (rxDmaHandle != NULL));
+
+ (void)memset(handle, 0, sizeof(*handle));
+
+ handle->rxState = (uint8_t)kUART_RxIdle;
+ handle->txState = (uint8_t)kUART_TxIdle;
+
+ handle->callback = callback;
+ handle->userData = userData;
+
+ handle->rxDmaHandle = rxDmaHandle;
+ handle->txDmaHandle = txDmaHandle;
+
+ /* Configure TX DMAC callback. */
+ if (txDmaHandle != NULL)
+ {
+ DMAC_TransferSetCallback(handle->txDmaHandle, UART_TransferSendDMACCallback, handle);
+ }
+
+ /* Configure RX DMAC callback. */
+ if (rxDmaHandle != NULL)
+ {
+ DMAC_TransferSetCallback(handle->rxDmaHandle, UART_TransferReceiveDMACCallback, handle);
+ }
+}
+
+/*!
+ * brief Sends data using DMAC.
+ *
+ * This function sends data using DMAC. This is non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * param base UART peripheral base address.
+ * param handle UART handle pointer.
+ * param xfer UART DMAC transfer structure. See #uart_transfer_t.
+ * retval kStatus_Success if succeeded; otherwise failed.
+ * retval kStatus_UART_TxBusy Previous transfer ongoing.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendDMAC(UART_Type *base, uart_dmac_handle_t *handle, uart_transfer_t *xfer)
+{
+ assert((handle != NULL) && (handle->txDmaHandle != NULL));
+ assert((xfer != NULL) && (xfer->data != NULL) && (xfer->dataSize != 0U));
+
+ status_t status;
+
+ /* If previous TX not finished. */
+ if ((uint8_t)kUART_TxBusy == handle->txState)
+ {
+ status = kStatus_UART_TxBusy;
+ }
+ else
+ {
+ dmac_channel_transfer_config_t dmacConfig;
+
+ handle->txState = (uint8_t)kUART_TxBusy;
+
+ /* Prepare transfer. */
+ DMAC_GetChannelDefaultTransferConfig(&dmacConfig, (void *)xfer->data,
+ (uint32_t *)UART_GetTxDataRegisterAddress(base),
+ kDMAC_ChannelTransferWidth8Bits, kDMAC_ChannelBurstLength1DataWidth,
+ xfer->dataSize, kDMAC_ChannelTransferMemoryToPeripheral);
+ dmacConfig.interruptMask = kDMAC_ChannelInterruptFlagTransferComplete;
+ DMAC_TransferSubmit(handle->txDmaHandle, &dmacConfig);
+ DMAC_TransferStart(handle->txDmaHandle);
+ UART_Enable(base, true);
+ UART_EnableDMA(base, true);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Receives data using DMAC.
+ *
+ * This function receives data using DMAC. This is non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to the uart_dmac_handle_t structure.
+ * param xfer UART DMAC transfer structure. See #uart_transfer_t.
+ * retval kStatus_Success if succeeded; otherwise failed.
+ * retval kStatus_UART_RxBusy Previous transfer on going.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveDMAC(UART_Type *base, uart_dmac_handle_t *handle, uart_transfer_t *xfer)
+{
+ assert((handle != NULL) && (handle->rxDmaHandle != NULL));
+ assert((xfer != NULL) && (xfer->data != NULL) && (xfer->dataSize != 0U));
+
+ status_t status;
+
+ /* If previous RX not finished. */
+ if ((uint8_t)kUART_RxBusy == handle->rxState)
+ {
+ status = kStatus_UART_RxBusy;
+ }
+ else
+ {
+ dmac_channel_transfer_config_t dmacConfig;
+
+ handle->rxState = (uint8_t)kUART_RxBusy;
+
+ /* Prepare transfer. */
+ DMAC_GetChannelDefaultTransferConfig(&dmacConfig, (uint32_t *)UART_GetRxDataRegisterAddress(base),
+ (void *)xfer->data, kDMAC_ChannelTransferWidth8Bits,
+ kDMAC_ChannelBurstLength1DataWidth, xfer->dataSize,
+ kDMAC_ChannelTransferPeripheralToMemory);
+ dmacConfig.interruptMask = kDMAC_ChannelInterruptFlagTransferComplete;
+ DMAC_TransferSubmit(handle->rxDmaHandle, &dmacConfig);
+ DMAC_TransferStart(handle->rxDmaHandle);
+ UART_Enable(base, true);
+ UART_EnableDMA(base, true);
+
+ status = kStatus_Success;
+ }
+
+ return status;
+}
+
+/*!
+ * brief Aborts the send data using DMAC.
+ *
+ * This function aborts the sent data using DMAC.
+ *
+ * note This function only aborts the tx DMAC transfer not disable the DMA function, since disable DMA function will
+ * disable tx and rx together. If user wants to abort both tx/rx DMAC transfer, use UART_EnableDMA(base, false).
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to uart_dmac_handle_t structure.
+ */
+void UART_TransferAbortSendDMAC(UART_Type *base, uart_dmac_handle_t *handle)
+{
+ assert((handle != NULL) && (handle->txDmaHandle != NULL));
+
+ /* Stop transfer. */
+ DMAC_TransferStop(handle->txDmaHandle);
+
+ handle->txState = (uint8_t)kUART_TxIdle;
+}
+
+/*!
+ * brief Aborts the received data using DMAC.
+ *
+ * This function abort receive data which using DMAC.
+ *
+ * note This function only aborts the rx DMAC transfer not disable the DMA function, since disable DMA function will
+ * disable tx and rx together. If user wants to abort both tx/rx DMAC transfer, use UART_EnableDMA(base, false).
+ *
+ * param base UART peripheral base address.
+ * param handle Pointer to uart_dmac_handle_t structure.
+ */
+void UART_TransferAbortReceiveDMAC(UART_Type *base, uart_dmac_handle_t *handle)
+{
+ assert((handle != NULL) && (handle->rxDmaHandle != NULL));
+
+ /* Stop transfer. */
+ DMAC_TransferStop(handle->rxDmaHandle);
+
+ handle->rxState = (uint8_t)kUART_RxIdle;
+}
diff --git a/drivers/mw320/uart/fsl_uart_dmac.h b/drivers/mw320/uart/fsl_uart_dmac.h
new file mode 100644
index 000000000..5b9aa715d
--- /dev/null
+++ b/drivers/mw320/uart/fsl_uart_dmac.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_UART_DMAC_H_
+#define _FSL_UART_DMAC_H_
+
+#include "fsl_uart.h"
+#include "fsl_dmac.h"
+
+/*!
+ * @addtogroup uart_dmac_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief UART DMAC driver version. */
+#define FSL_UART_DMAC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/* Forward declaration of the handle typedef. */
+typedef struct _uart_dmac_handle uart_dmac_handle_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*uart_dmac_transfer_callback_t)(UART_Type *base,
+ uart_dmac_handle_t *handle,
+ status_t status,
+ void *userData);
+
+/*!
+ * @brief UART DMAC handle
+ */
+struct _uart_dmac_handle
+{
+ UART_Type *base; /*!< UART peripheral base address. */
+
+ uart_dmac_transfer_callback_t callback; /*!< Callback function. */
+ void *userData; /*!< UART callback function parameter.*/
+
+ dmac_handle_t *txDmaHandle; /*!< The DMAC TX channel used. */
+ dmac_handle_t *rxDmaHandle; /*!< The DMAC RX channel used. */
+
+ volatile uint8_t txState; /*!< TX transfer state. */
+ volatile uint8_t rxState; /*!< RX transfer state */
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name DMAC transactional APIs
+ * @{
+ */
+
+/*!
+ * @brief Initializes the UART handle which is used in transactional functions and sets the callback.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to the uart_dmac_handle_t structure.
+ * @param callback UART callback, NULL means no callback.
+ * @param userData User callback function data.
+ * @param rxDmaHandle User requested DMAC handle for the RX DMAC transfer.
+ * @param txDmaHandle User requested DMAC handle for the TX DMAC transfer.
+ */
+void UART_TransferCreateHandleDMAC(UART_Type *base,
+ uart_dmac_handle_t *handle,
+ uart_dmac_transfer_callback_t callback,
+ void *userData,
+ dmac_handle_t *txDmaHandle,
+ dmac_handle_t *rxDmaHandle);
+
+/*!
+ * @brief Sends data using DMAC.
+ *
+ * This function sends data using DMAC. This is non-blocking function, which returns
+ * right away. When all data is sent, the send callback function is called.
+ *
+ * @param base UART peripheral base address.
+ * @param handle UART handle pointer.
+ * @param xfer UART DMAC transfer structure. See #uart_transfer_t.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_TxBusy Previous transfer ongoing.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferSendDMAC(UART_Type *base, uart_dmac_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Receives data using DMAC.
+ *
+ * This function receives data using DMAC. This is non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to the uart_dmac_handle_t structure.
+ * @param xfer UART DMAC transfer structure. See #uart_transfer_t.
+ * @retval kStatus_Success if succeeded; otherwise failed.
+ * @retval kStatus_UART_RxBusy Previous transfer on going.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t UART_TransferReceiveDMAC(UART_Type *base, uart_dmac_handle_t *handle, uart_transfer_t *xfer);
+
+/*!
+ * @brief Aborts the send data using DMAC.
+ *
+ * This function aborts the sent data using DMAC.
+ *
+ * @note This function only aborts the tx DMAC transfer not disable the DMA function, since disable DMA function will
+ * disable tx and rx together. If user wants to abort both tx/rx DMAC transfer, use UART_EnableDMA(base, false).
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to uart_dmac_handle_t structure.
+ */
+void UART_TransferAbortSendDMAC(UART_Type *base, uart_dmac_handle_t *handle);
+
+/*!
+ * @brief Aborts the received data using DMAC.
+ *
+ * This function abort receive data which using DMAC.
+ *
+ * @note This function only aborts the rx DMAC transfer not disable the DMA function, since disable DMA function will
+ * disable tx and rx together. If user wants to abort both tx/rx DMAC transfer, use UART_EnableDMA(base, false).
+ *
+ * @param base UART peripheral base address.
+ * @param handle Pointer to uart_dmac_handle_t structure.
+ */
+void UART_TransferAbortReceiveDMAC(UART_Type *base, uart_dmac_handle_t *handle);
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_UART_DMAC_H_ */
diff --git a/drivers/mw320/wdt/driver_mw_wdt.cmake b/drivers/mw320/wdt/driver_mw_wdt.cmake
new file mode 100644
index 000000000..165216dd2
--- /dev/null
+++ b/drivers/mw320/wdt/driver_mw_wdt.cmake
@@ -0,0 +1,14 @@
+#Description: MW_WDT Driver; user_visible: True
+include_guard(GLOBAL)
+message("driver_mw_wdt component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+ ${CMAKE_CURRENT_LIST_DIR}/fsl_wdt.c
+)
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
+ ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_common)
diff --git a/drivers/mw320/wdt/fsl_wdt.c b/drivers/mw320/wdt/fsl_wdt.c
new file mode 100644
index 000000000..4428a5c8f
--- /dev/null
+++ b/drivers/mw320/wdt/fsl_wdt.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_wdt.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.mw_wdt"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static WDT_Type *const s_wdtBases[] = WDT_BASE_PTRS;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/* Array of WDT clock name. */
+static const clock_ip_name_t s_wdtClock[] = WDT_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t WDT_GetInstance(WDT_Type *base)
+{
+ uint32_t instance;
+
+ /* Find the instance index from base address mappings. */
+ for (instance = 0; instance < ARRAY_SIZE(s_wdtBases); instance++)
+ {
+ if (s_wdtBases[instance] == base)
+ {
+ break;
+ }
+ }
+
+ assert(instance < ARRAY_SIZE(s_wdtBases));
+
+ return instance;
+}
+
+/*!
+ * brief Prepares an available pre-defined setting for module's configuration.
+ * This function initializes the WDT configuration structure to default values.
+ * config->timeoutValue = kWDT_TimeoutVal2ToThePowerOf16;
+ * config->timeoutMode =kWDT_TimeoutModeReset;
+ * config->resetWidth = kWDT_ResetWidthLen2;
+ * config->enableWDT = false;
+ * @param config Pointer to the WDT configuration structure, @ref wdt_config_t.
+ */
+void WDT_GetDefaultConfig(wdt_config_t *config)
+{
+ config->timeoutValue = kWDT_TimeoutVal2ToThePowerOf16;
+ config->timeoutMode = kWDT_ModeTimeoutReset;
+ config->resetWidth = kWDT_ResetPulseLen8;
+ config->enableWDT = false;
+}
+
+/*!
+ * brief Initializes the WDT module with input configuration
+ * Call this function to do initialization configuration for WDT module.
+ * The configurations are:
+ * - WDT counter timeout value
+ * - Timeout response mode select
+ * - Reset assert pulse width configuration
+ * - WDT enable/disable
+ * param base WDT peripheral base address.
+ * param config The pointer to WDT configuration structure, @ref wdt_config_t.
+ */
+void WDT_Init(WDT_Type *base, const wdt_config_t *config)
+{
+ assert(config != NULL);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ /* Set configuration */
+ CLOCK_EnableClock(s_wdtClock[WDT_GetInstance(base)]);
+#endif
+
+ uint32_t u32ConfigVal = base->WDT_TORR;
+ u32ConfigVal &= ~(WDT_WDT_TORR_TOP_INIT_MASK | WDT_WDT_TORR_TOP_MASK);
+ u32ConfigVal |=
+ WDT_WDT_TORR_TOP_INIT((uint32_t)config->timeoutValue) | WDT_WDT_TORR_TOP((uint32_t)config->timeoutValue);
+
+ base->WDT_TORR = u32ConfigVal;
+
+ u32ConfigVal = base->WDT_CR;
+ u32ConfigVal &= ~(WDT_WDT_CR_RMOD_MASK | WDT_WDT_CR_RPL_MASK | WDT_WDT_CR_WDT_EN_MASK);
+ u32ConfigVal |= (WDT_WDT_CR_RMOD((uint32_t)config->timeoutMode) | WDT_WDT_CR_RPL((uint32_t)config->resetWidth) |
+ WDT_WDT_CR_WDT_EN(config->enableWDT));
+
+ base->WDT_CR = u32ConfigVal;
+}
+
+void WDT_Refresh(WDT_Type *base)
+{
+ base->WDT_CRR = WDT_REFRESH_PATTERN;
+}
diff --git a/drivers/mw320/wdt/fsl_wdt.h b/drivers/mw320/wdt/fsl_wdt.h
new file mode 100644
index 000000000..1b555513a
--- /dev/null
+++ b/drivers/mw320/wdt/fsl_wdt.h
@@ -0,0 +1,249 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_WDT_H
+#define _FSL_WDT_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup wdt
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief WDT driver version 2.0.0. */
+#define FSL_WDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! @name WDT refresh pattern. */
+/*@{*/
+#define WDT_REFRESH_PATTERN (0x76U) /*!< Refresh pattern to restart WDT */
+/*@}*/
+
+/*! @brief enumeration for wdt timeout response mode select. */
+typedef enum _wdt_timeout_response_mode
+{
+ kWDT_ModeTimeoutReset = 0, /*!< WDT will generate system reset for timeout */
+ kWDT_ModeTimeoutInterrupt = 1, /*!< WDT will generate interrupt for timeout */
+} wdt_timeout_response_mode_t;
+
+/*! @brief enumeration for wdt reset assert width select. */
+typedef enum _wdt_reset_width
+{
+ kWDT_ResetPulseLen2 = 0, /*!< WDT reset pulse length: 2 pclk cycles */
+ kWDT_ResetPulseLen4 = 1, /*!< WDT reset pulse length: 4 pclk cycles */
+ kWDT_ResetPulseLen8 = 2, /*!< WDT reset pulse length: 8 pclk cycles */
+ kWDT_ResetPulseLen16 = 3, /*!< WDT reset pulse length: 16 pclk cycles */
+ kWDT_ResetPulseLen32 = 4, /*!< WDT reset pulse length: 32 pclk cycles */
+ kWDT_ResetPulseLen64 = 5, /*!< WDT reset pulse length: 64 pclk cycles */
+ kWDT_ResetPulseLen128 = 6, /*!< WDT reset pulse length: 128 pclk cycles */
+ kWDT_ResetPulseLen256 = 7, /*!< WDT reset pulse length: 256 pclk cycles */
+} wdt_reset_width_t;
+
+/*! @brief enumeration for wdt timeout value config. */
+typedef enum _wdt_timeout_value
+{
+ kWDT_TimeoutVal2ToThePowerOf16 = 0, /*!< WDT timeout value : 2^16 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf17 = 1, /*!< WDT timeout value : 2^17 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf18 = 2, /*!< WDT timeout value : 2^18 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf19 = 3, /*!< WDT timeout value : 2^19 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf20 = 4, /*!< WDT timeout value : 2^20 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf21 = 5, /*!< WDT timeout value : 2^21 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf22 = 6, /*!< WDT timeout value : 2^22 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf23 = 7, /*!< WDT timeout value : 2^23 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf24 = 8, /*!< WDT timeout value : 2^24 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf25 = 9, /*!< WDT timeout value : 2^25 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf26 = 10, /*!< WDT timeout value : 2^26 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf27 = 11, /*!< WDT timeout value : 2^27 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf28 = 12, /*!< WDT timeout value : 2^28 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf29 = 13, /*!< WDT timeout value : 2^29 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf30 = 14, /*!< WDT timeout value : 2^30 pclk cycles */
+ kWDT_TimeoutVal2ToThePowerOf31 = 15, /*!< WDT timeout value : 2^31 pclk cycles */
+} wdt_timeout_value_t;
+
+/*! @brief structure for WDT module initialization configuration. */
+typedef struct _wdt_config
+{
+ wdt_timeout_value_t timeoutValue;
+ wdt_timeout_response_mode_t timeoutMode : 1;
+ wdt_reset_width_t resetWidth : 4;
+ bool enableWDT : 1;
+} wdt_config_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @name Initialization Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Initializes the WDT module with input configuration
+ * Call this function to do initialization configuration for WDT module.
+ * The configurations are:
+ * - WDT counter timeout value
+ * - Timeout response mode select
+ * - Reset assert pulse width configuration
+ * - WDT enable/disable
+ * @param base WDT peripheral base address.
+ * @param config The pointer to WDT configuration structure, @ref wdt_config_t.
+ */
+void WDT_Init(WDT_Type *base, const wdt_config_t *config);
+
+/*!
+ * @brief Prepares an available pre-defined setting for module's configuration.
+ * This function initializes the WDT configuration structure to default values.
+ * config->timeoutValue = kWDT_TimeoutVal2ToThePowerOf16;
+ * config->timeoutMode =kWDT_TimeoutModeReset;
+ * config->resetWidth = kWDT_ResetWidthLen2;
+ * config->enableWDT = false;
+ * @param config Pointer to the WDT configuration structure, @ref wdt_config_t.
+ */
+void WDT_GetDefaultConfig(wdt_config_t *config);
+/* @} */
+
+/*!
+ * @name WDT Operation Interfaces
+ * @{
+ */
+
+/*!
+ * @brief Enable/Disable the WDT module.
+ *
+ * This function enable/disables the WDT.
+ * To disable the WDT Watchdog, call WDT_Enable(base, false).
+ *
+ * @param base WDT peripheral base address.
+ * @param enable Enable the feature or not.
+ */
+static inline void WDT_Enable(WDT_Type *base, bool enable)
+{
+ if (enable)
+ {
+ base->WDT_CR |= WDT_WDT_CR_WDT_EN_MASK;
+ }
+ else
+ {
+ base->WDT_CR &= ~WDT_WDT_CR_WDT_EN_MASK;
+ }
+}
+
+/*!
+ * @brief Sets the WDT timeout value.
+ *
+ */
+static inline void WDT_SetTimeoutValue(WDT_Type *base, wdt_timeout_value_t timeoutValue)
+{
+ base->WDT_TORR = (base->WDT_TORR & ~WDT_WDT_TORR_TOP_MASK) | WDT_WDT_TORR_TOP((uint32_t)timeoutValue);
+}
+
+/*!
+ * @brief Gets the WDT timeout value.
+ *
+ */
+static inline uint32_t WDT_GetCounterValue(WDT_Type *base)
+{
+ return base->WDT_CCVR;
+}
+
+/*!
+ * @brief Refreshes the WDT timer
+ *
+ * This function feeds/services the WDT.
+ *
+ * @param base WDT peripheral base address.
+ */
+void WDT_Refresh(WDT_Type *base);
+
+/* @} */
+
+/*!
+ * @name Interrupt Control Interfaces
+ * @{
+ */
+/*!
+ * @brief Enables the WDT interrupt, if config->timeoutMode = kWDT_TimeoutModeInterrupt
+ * for calling WDT_Init, the WDT interrupt is by default enabled, this function does not
+ * take effect.
+ *
+ * This function set WDT timeout response mode to generate interrupt.
+ *
+ * @param base WDT peripheral base address
+ */
+static inline void WDT_EnableInterrupt(WDT_Type *base)
+{
+ base->WDT_CR |= WDT_WDT_CR_RMOD_MASK;
+}
+
+/*!
+ * @brief Enables the WDT interrupt, if config->timeoutMode = kWDT_TimeoutModeReset
+ * for calling WDT_Init, the WDT interrupt is by default disabled, this function does not
+ * take effect.
+ *
+ * This function set WDT timeout response mode to generate reset.
+ *
+ * @param base WDT peripheral base address
+ */
+static inline void WDT_DisableInterrupt(WDT_Type *base)
+{
+ base->WDT_CR &= ~WDT_WDT_CR_RMOD_MASK;
+}
+/* @} */
+
+/*!
+ * @name Status get/clear interface.
+ * @{
+ */
+
+/*!
+ * @brief Gets WDT interrupt status.
+ *
+ * @param base WDT peripheral base address
+ *
+ * @return true if interrupt flag is asserted, else false
+ *
+ */
+
+static inline bool WDT_GetInterruptStatus(WDT_Type *base)
+{
+ return ((base->WDT_STAT & WDT_WDT_STAT_WDT_STAT_MASK) != 0U) ? true : false;
+}
+
+/*!
+ * @brief Clear WDT interrupt status
+ *
+ * @param base WDT peripheral base address
+ */
+static inline void WDT_ClearInterruptStatus(WDT_Type *base)
+{
+ volatile uint32_t tmpData;
+ /* Clear interrupt flag for read */
+ tmpData = base->WDT_EOI;
+ tmpData = tmpData;
+}
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+
+#endif /* _FSL_WDT_H_ */
diff --git a/drivers/sai/driver_sai_edma.cmake b/drivers/sai/driver_sai_edma.cmake
index 1529f92df..852813583 100644
--- a/drivers/sai/driver_sai_edma.cmake
+++ b/drivers/sai/driver_sai_edma.cmake
@@ -11,13 +11,7 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
- include(driver_edma)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
- include(driver_edma)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
include(driver_edma)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
@@ -29,22 +23,28 @@ endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
include(driver_dma3)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(driver_edma)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
include(driver_edma)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
+ include(driver_edma)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(driver_edma)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MK66F18")
include(driver_edma)
endif()
diff --git a/drivers/spi/driver_spi_freertos.cmake b/drivers/spi/driver_spi_freertos.cmake
index 899b91e76..5004b56fe 100644
--- a/drivers/spi/driver_spi_freertos.cmake
+++ b/drivers/spi/driver_spi_freertos.cmake
@@ -14,11 +14,11 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
include(middleware_freertos-kernel_K32L2B31A)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
- include(middleware_freertos-kernel_MKM35Z7)
-endif()
if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
include(middleware_freertos-kernel_MKL27Z644)
endif()
+if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+ include(middleware_freertos-kernel_MKM35Z7)
+endif()
include(driver_spi)
diff --git a/drivers/uart/driver_uart_freertos.cmake b/drivers/uart/driver_uart_freertos.cmake
index 19bacbae9..a40d9a64d 100644
--- a/drivers/uart/driver_uart_freertos.cmake
+++ b/drivers/uart/driver_uart_freertos.cmake
@@ -14,26 +14,26 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
include(middleware_freertos-kernel_K32L2B31A)
endif()
+if(${MCUX_DEVICE} STREQUAL "MK22F51212")
+ include(middleware_freertos-kernel_MK22F51212)
+endif()
if(${MCUX_DEVICE} STREQUAL "MK64F12")
include(middleware_freertos-kernel_MK64F12)
endif()
if(${MCUX_DEVICE} STREQUAL "MK66F18")
include(middleware_freertos-kernel_MK66F18)
endif()
+if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
+ include(middleware_freertos-kernel_MKL27Z644)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+ include(middleware_freertos-kernel_MKM35Z7)
+endif()
if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
include(middleware_freertos-kernel_MKV11Z7)
endif()
if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
include(middleware_freertos-kernel_MKV31F51212)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
- include(middleware_freertos-kernel_MK22F51212)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
- include(middleware_freertos-kernel_MKM35Z7)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
- include(middleware_freertos-kernel_MKL27Z644)
-endif()
include(driver_uart)
diff --git a/drivers/utick/driver_utick.cmake b/drivers/utick/driver_utick.cmake
index 3a013885c..220074ac2 100644
--- a/drivers/utick/driver_utick.cmake
+++ b/drivers/utick/driver_utick.cmake
@@ -11,6 +11,9 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
+if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+ include(driver_common)
+endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm0plus")
include(driver_common)
endif()
@@ -20,22 +23,19 @@ endif()
if(${MCUX_DEVICE} STREQUAL "LPC54628")
include(driver_common)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
- include(driver_common)
-endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018")
include(driver_common)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
include(driver_common)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+if(${MCUX_DEVICE} STREQUAL "LPC55S16")
include(driver_common)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
+if(${MCUX_DEVICE} STREQUAL "LPC55S28")
include(driver_common)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S28")
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
include(driver_common)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
diff --git a/tools/boot2/boot2.bin b/tools/boot2/boot2.bin
new file mode 100644
index 000000000..61ea1a932
Binary files /dev/null and b/tools/boot2/boot2.bin differ
diff --git a/tools/boot2/layout.bin b/tools/boot2/layout.bin
new file mode 100644
index 000000000..4f98599af
Binary files /dev/null and b/tools/boot2/layout.bin differ
diff --git a/tools/boot2/layout.txt b/tools/boot2/layout.txt
new file mode 100644
index 000000000..ee52b0f1a
--- /dev/null
+++ b/tools/boot2/layout.txt
@@ -0,0 +1,9 @@
+# Component Address Size device Name[8]
+FC_COMP_BOOT2 0x0 0x6000 0 boot2
+FC_COMP_FW 0x10000 0x90000 0 mcufw
+FC_COMP_FW 0xa0000 0x90000 0 mcufw
+FC_COMP_FTFS 0x130000 0x10000 0 ftfs
+FC_COMP_FTFS 0x140000 0x10000 0 ftfs
+FC_COMP_WLAN_FW 0x150000 0x50000 0 wififw
+FC_COMP_WLAN_FW 0x1a0000 0x50000 0 wififw
+FC_COMP_PSM 0x1f0000 0x4000 0 psm
diff --git a/tools/mw_img_conv/bin/mw_img_conv.exe b/tools/mw_img_conv/bin/mw_img_conv.exe
new file mode 100644
index 000000000..630bf2e00
Binary files /dev/null and b/tools/mw_img_conv/bin/mw_img_conv.exe differ
diff --git a/tools/mw_img_conv/mw320/mkimg.sh b/tools/mw_img_conv/mw320/mkimg.sh
new file mode 100644
index 000000000..6fe8f48cb
--- /dev/null
+++ b/tools/mw_img_conv/mw320/mkimg.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+
+if [[ "$OSTYPE" == "linux-gnu" ]]; then
+ ARCH=`uname -m`
+ if [[ "$ARCH" == "i686" ]]; then
+ IMG_CONV=../bin/mw_img_conv
+ else
+ IMG_CONV=../bin/mw_img_conv64
+ fi
+else
+ IMG_CONV=../bin/mw_img_conv.exe
+fi
+
+if [ "$#" -ne 1 ] ; then
+ echo "Usage: $0 "
+ exit 1
+fi
+
+path=`dirname $1`
+name=`basename $1 .bin`
+addr=`head -c8 $1 | od -An -t x1 -j7`
+
+if [[ "$addr" == *"1f"* ]]; then
+ echo "$IMG_CONV mcufw $1 $path/$name.fw.bin 0x1F000100"
+ $IMG_CONV mcufw $1 $path/$name.fw.bin 0x1F000100
+else
+ echo "$IMG_CONV mcufw $1 $path/$name.fw.bin 0x00100000"
+ $IMG_CONV mcufw $1 $path/$name.fw.bin 0x00100000
+fi
diff --git a/tools/mw_img_conv/src/mw_img_conv.c b/tools/mw_img_conv/src/mw_img_conv.c
new file mode 100644
index 000000000..2181d9a52
--- /dev/null
+++ b/tools/mw_img_conv/src/mw_img_conv.c
@@ -0,0 +1,431 @@
+/*
+ * Copyright 2008-2020 NXP
+ *
+ * NXP CONFIDENTIAL
+ * The source code contained or described herein and all documents related to
+ * the source code ("Materials") are owned by NXP, its
+ * suppliers and/or its licensors. Title to the Materials remains with NXP,
+ * its suppliers and/or its licensors. The Materials contain
+ * trade secrets and proprietary and confidential information of NXP, its
+ * suppliers and/or its licensors. The Materials are protected by worldwide copyright
+ * and trade secret laws and treaty provisions. No part of the Materials may be
+ * used, copied, reproduced, modified, published, uploaded, posted,
+ * transmitted, distributed, or disclosed in any way without NXP's prior
+ * express written permission.
+ *
+ * No license under any patent, copyright, trade secret or other intellectual
+ * property right is granted to or conferred upon you by disclosure or delivery
+ * of the Materials, either expressly, by implication, inducement, estoppel or
+ * otherwise. Any license under such intellectual property rights must be
+ * express and approved by NXP in writing.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MAX_NAME 8
+#define MAX_FL_COMP 16
+#define CRC_TABLE_SIZE 256
+#define MAX_BUFFER_SIZE 512
+#define MAX_FILE_PATH 256
+#define MAX_COMP_SIZE 32
+#define MAX_SECT_SIZE 1024
+
+#define STRINGIFY_1(x) #x
+#define S(x) STRINGIFY_1(x)
+
+#define WLAN_FW_MAGIC (('W' << 0)|('L' << 8)|('F' << 16)|('W' << 24))
+#define FW_MAGIC_STR (('M' << 0)|('R' << 8)|('V' << 16)|('L' << 24))
+#define FW_MAGIC_SIG ((0x7BUL << 0) | (0xF1UL << 8) | (0x9CUL << 16) | (0x2EUL << 24))
+#define FW_BLK_LOADABLE_SEGMENT (2) /* loads data to follow */
+#define MCU_FW_OFFSET (0x100U) /* MCU firmware application offset from image header */
+
+/** Partition Table */
+struct partition_table {
+#define PARTITION_TABLE_MAGIC (('W' << 0)|('M' << 8)|('P' << 16)|('T' << 24))
+ /** The magic identifying the start of the partition table */
+ uint32_t magic;
+#define PARTITION_TABLE_VERSION 1
+ /** The version number of this partition table */
+ uint16_t version;
+ /** The number of partition entries that follow this */
+ uint16_t partition_entries_no;
+ /** Generation level */
+ uint32_t gen_level;
+ /** The CRC of all the above components */
+ uint32_t crc;
+};
+
+/** Partition Entry */
+struct partition_entry {
+ /** The type of the flash component */
+ uint8_t type;
+ /** The device id, internal flash is always id 0 */
+ uint8_t device;
+ /** A descriptive component name */
+ char name[MAX_NAME];
+ /** Start address on the given device */
+ uint32_t start;
+ /** Size on the given device */
+ uint32_t size;
+ /** Generation level */
+ uint32_t gen_level;
+};
+
+/** The various components in a flash layout */
+enum flash_comp {
+ /** The secondary stage boot loader to assist firmware bootup */
+ FC_COMP_BOOT2 = 0,
+ /** The firmware image. There can be a maximum of two firmware
+ * components available in a flash layout. These will be used in an
+ * active-passive mode if rfget module is enabled.
+ */
+ FC_COMP_FW,
+ /** The wlan firmware image. There can be one wlan firmware image in the
+ * system. The contents of this location would be downloaded to the WLAN
+ * chip.
+ */
+ FC_COMP_WLAN_FW,
+ /** The FTFS image. */
+ FC_COMP_FTFS,
+ /** The PSM data */
+ FC_COMP_PSM,
+ /** Application Specific component */
+ FC_COMP_USER_APP,
+ /** The BT firmware image if external BT/BLE chip is used */
+ FC_COMP_BT_FW,
+};
+
+/*
+ * Firmware magic signature
+ *
+ * First word is the string "MRVL" and is endian invariant.
+ * Second word = magic value 0x2e9cf17.
+ * Third word = time stamp (seconds since 00:00:00 UTC, January 1, 1970).
+ */
+struct img_hdr {
+ uint32_t magic_str;
+ uint32_t magic_sig;
+ uint32_t time;
+ uint32_t seg_cnt;
+ uint32_t entry;
+};
+
+/* Maximum number of segments */
+#define SEG_CNT 9
+
+struct seg_hdr {
+ uint32_t type;
+ uint32_t offset;
+ uint32_t len;
+ uint32_t laddr;
+ uint32_t crc;
+};
+
+struct wlan_fw_header {
+ uint32_t magic;
+ uint32_t length;
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static uint32_t crc_table[CRC_TABLE_SIZE];
+static const int rcrc32 = 0xEDB88320;
+static char gbuffer[MAX_BUFFER_SIZE];
+static struct partition_table g_flash_table;
+static struct partition_entry g_flash_parts[MAX_FL_COMP];
+static uint8_t gsection[MAX_SECT_SIZE];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void die_usage(const char *argv0)
+{
+ fprintf(stderr, "Usage: %s []\n", argv0);
+ fprintf(stderr, " option:\n");
+ fprintf(stderr, " layout: Convert layout config file to layout flash image.\n");
+ fprintf(stderr, " mcufw: Convert MCU image to MCU flash image. needed.\n");
+ fprintf(stderr, " wififw: Convert WiFi image to WiFi flash image\n");
+ exit(1);
+}
+
+static void die_perror(const char *msg)
+{
+ perror(msg);
+ exit(1);
+}
+
+static int flash_get_comp(const char *comp)
+{
+ if (!strcmp(comp, "FC_COMP_FW"))
+ return FC_COMP_FW;
+ else if (!strcmp(comp, "FC_COMP_WLAN_FW"))
+ return FC_COMP_WLAN_FW;
+ else if (!strcmp(comp, "FC_COMP_BT_FW"))
+ return FC_COMP_BT_FW;
+ else if (!strcmp(comp, "FC_COMP_FTFS"))
+ return FC_COMP_FTFS;
+ else if (!strcmp(comp, "FC_COMP_BOOT2"))
+ return FC_COMP_BOOT2;
+ else if (!strcmp(comp, "FC_COMP_PSM"))
+ return FC_COMP_PSM;
+ else if (!strcmp(comp, "FC_COMP_USER_APP"))
+ return FC_COMP_USER_APP;
+ else {
+ printf("Error: Invalid flash component %s\n", comp);
+ return -1;
+ }
+}
+
+static void soft_crc32_init(void)
+{
+ unsigned int crc = 0;
+ unsigned char i;
+ unsigned int j;
+
+ for (j = 0; j < CRC_TABLE_SIZE; j++) {
+ crc = 0;
+ for (i = 0x01; i != 0x00; i <<= 1) {
+ if ((crc & 0x00000001) != 0) {
+ crc >>= 1;
+ crc ^= rcrc32;
+ } else {
+ crc >>= 1;
+ }
+ if ((j & i) != 0)
+ crc ^= rcrc32;
+ }
+ crc_table[j] = crc;
+ }
+}
+
+static uint32_t soft_crc32(const void *__data, int data_size, uint32_t crc)
+{
+ const uint8_t *data = __data;
+ unsigned int result = crc;
+ unsigned char crc_H8;
+
+ while (data_size--) {
+ crc_H8 = (unsigned char)(result & 0x000000FF);
+ result >>= 8;
+ result ^= crc_table[crc_H8 ^ (*data)];
+ data++;
+ }
+
+ return result;
+}
+
+static void h_to_le32(uint32_t v, uint32_t *x)
+{
+ uint8_t *b = (uint8_t *)x;
+ b[0] = v;
+ b[1] = (v >> 8);
+ b[2] = (v >> 16);
+ b[3] = (v >> 24);
+}
+
+static void convert_layout(FILE *in, FILE *out)
+{
+ int i = 0, parts_no = 0, ret;
+ char comp[MAX_COMP_SIZE];
+ struct partition_entry *fl = &g_flash_parts[0];
+ uint32_t crc;
+
+ memset(gbuffer, 0, sizeof(gbuffer));
+ memset(&g_flash_table, 0, sizeof(g_flash_table));
+ memset(&g_flash_parts[0], 0, sizeof(g_flash_parts));
+
+ while (fgets(gbuffer, sizeof(gbuffer), in) != NULL) {
+ if (i >= MAX_FL_COMP) {
+ printf("Only %d partition entries are supported, "
+ "Truncating...\n", MAX_FL_COMP);
+ break;
+ }
+ /* Skip and continue if the line begins with # or is empty */
+ if (gbuffer[0] == '#' || gbuffer[0] == '\n')
+ /*
+ * There is autogeneration header in layout file and
+ * hence printing here some log message will increase
+ * overall time.
+ */
+ continue;
+ sscanf(gbuffer,
+ "%"S(MAX_COMP_SIZE)"s""\t%x\t%x\t%d\t""%"S(MAX_NAME)"s"
+ , comp,
+ (unsigned int *)&fl[i].start,
+ (unsigned int *)&fl[i].size,
+ (unsigned int *)&fl[i].device,
+ fl[i].name);
+ if ((ret = flash_get_comp(comp)) != -1)
+ fl[i].type = ret;
+ else {
+ die_perror("get component type failed");
+ }
+
+ /* Default generation level for all partitions */
+ fl[i].gen_level = 1;
+
+ parts_no++;
+ i++;
+ memset(gbuffer, 0, sizeof(gbuffer));
+ }
+
+ g_flash_table.magic = PARTITION_TABLE_MAGIC;
+ g_flash_table.version = PARTITION_TABLE_VERSION;
+ g_flash_table.partition_entries_no = parts_no;
+ g_flash_table.gen_level = 0;
+ g_flash_table.crc = soft_crc32(&g_flash_table, sizeof(g_flash_table) - 4, 0);
+ if (fwrite(&g_flash_table, sizeof(g_flash_table), 1, out) != 1)
+ die_perror("write output file error");
+
+ crc = soft_crc32(&g_flash_parts[0], sizeof(g_flash_parts[0]) * parts_no, 0);
+ if (fwrite(&g_flash_parts[0], sizeof(g_flash_parts[0]) * parts_no, 1, out) != 1)
+ die_perror("write output file error");
+
+ if (fwrite(&crc, sizeof(crc), 1, out) != 1)
+ die_perror("write output file error");
+}
+
+static void convert_mcufw(FILE *in, FILE *out, uint32_t laddr)
+{
+ struct img_hdr ih;
+ struct seg_hdr *sh;
+ uint32_t len, entry, pad, crc;
+ uint8_t *data;
+
+ fseek(in, 0, SEEK_END);
+ len = ftell(in);
+ fseek(in, 4, SEEK_SET);
+ if (fread(&entry, 4, 1, in) != 1)
+ {
+ die_perror("read fw entry error");
+ }
+ fseek(in, 0, SEEK_SET);
+
+ h_to_le32(FW_MAGIC_STR, &ih.magic_str);
+ h_to_le32(FW_MAGIC_SIG, &ih.magic_sig);
+ h_to_le32(time(NULL), &ih.time);
+ h_to_le32(1U, &ih.seg_cnt);
+ h_to_le32(entry, &ih.entry);
+
+ if (MCU_FW_OFFSET - sizeof(struct img_hdr) < SEG_CNT * sizeof(struct seg_hdr))
+ {
+ die_perror("MCU_FW_OFFSET too small");
+ }
+
+ sh = malloc(MCU_FW_OFFSET - sizeof(struct img_hdr));
+ if (!sh)
+ die_perror("out of memory");
+ memset(sh, 0xff, MCU_FW_OFFSET - sizeof(struct img_hdr));
+
+ /* padding firmware to 4 bytes aligned */
+ pad = ((len + 3U) & ~3UL) - len;
+ data = malloc(len + pad);
+ if (!data)
+ die_perror("out of memory");
+ if (fread(data, len, 1, in) != 1)
+ die_perror("cannot read MCU firmware");
+ memset(data + len, 0xff, pad);
+ len += pad;
+
+ crc = soft_crc32(data, len, 0);
+
+ h_to_le32(FW_BLK_LOADABLE_SEGMENT, &sh[0].type);
+ h_to_le32(MCU_FW_OFFSET, &sh[0].offset);
+ h_to_le32(len, &sh[0].len);
+ h_to_le32(laddr, &sh[0].laddr);
+ h_to_le32(crc, &sh[0].crc);
+
+ if (fwrite(&ih, sizeof(ih), 1, out) != 1)
+ die_perror("write image header error");
+ if (fwrite(sh, MCU_FW_OFFSET - sizeof(struct img_hdr), 1, out) != 1)
+ die_perror("write segment header error");
+ if (fwrite(data, len, 1, out) != 1)
+ die_perror("write MCU firmware error");
+}
+
+static void convert_wififw(FILE *in, FILE *out)
+{
+ struct wlan_fw_header wf_header;
+ uint32_t len;
+ uint32_t sz;
+
+ fseek(in, 0, SEEK_END);
+ len = ftell(in);
+ fseek(in, 0, SEEK_SET);
+
+ wf_header.magic = WLAN_FW_MAGIC;
+ wf_header.length = len;
+
+ if (fwrite(&wf_header, sizeof(wf_header), 1, out) != 1)
+ die_perror("write wifi header error");
+
+ while (len > 0)
+ {
+ sz = sizeof(gsection) > len ? len : sizeof(gsection);
+ if (fread(gsection, sz, 1, in) != 1)
+ die_perror("read input file error");
+ if (fwrite(gsection, sz, 1, out) != 1)
+ die_perror("write output file error");
+ len -= sz;
+ }
+}
+
+/*!
+ * @brief Main function
+ */
+int main(int argc, char *argv[])
+{
+ FILE *in, *out;
+ uint32_t laddr;
+
+ if (argc != 4 && argc != 5)
+ die_usage(argv[0]);
+
+ in = fopen(argv[2], "rb");
+ if (!in)
+ die_perror(argv[1]);
+ out = fopen(argv[3], "wb");
+ if (!out)
+ die_perror(argv[2]);
+
+ soft_crc32_init();
+
+ if (!strncmp(argv[1], "layout", 6))
+ {
+ convert_layout(in, out);
+ }
+ else if (!strncmp(argv[1], "mcufw", 5))
+ {
+ if (argc != 5)
+ {
+ die_usage(argv[0]);
+ }
+ laddr = strtoul(argv[4], NULL, 0);
+ printf("Convert MCU firmware with load address 0x%x\n", laddr);
+ convert_mcufw(in, out, laddr);
+ }
+ else if (!strncmp(argv[1], "wififw", 6))
+ {
+ convert_wififw(in, out);
+ }
+
+ fclose(in);
+ if (fclose(out) != 0)
+ die_perror(argv[3]);
+
+ return 0;
+}
+
diff --git a/utilities/debug_console/debug_console/fsl_debug_console.c b/utilities/debug_console/debug_console/fsl_debug_console.c
index 4e15006c3..cbcee44c4 100644
--- a/utilities/debug_console/debug_console/fsl_debug_console.c
+++ b/utilities/debug_console/debug_console/fsl_debug_console.c
@@ -86,20 +86,14 @@
#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
static SemaphoreHandle_t s_debugConsoleReadSemaphore;
-#if configSUPPORT_STATIC_ALLOCATION
-static StaticSemaphore_t s_debugConsoleReadSemaphoreStatic;
-#endif
#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore;
-#if configSUPPORT_STATIC_ALLOCATION
-static StaticSemaphore_t s_debugConsoleReadWaitSemaphoreStatic;
-#endif
#endif
#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM)
#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
-static volatile bool s_debugConsoleReadWaitSemaphore;
+static volatile uint8_t s_debugConsoleReadWaitSemaphore;
#endif
#else
@@ -118,20 +112,16 @@ static volatile bool s_debugConsoleReadWaitSemaphore;
/* mutex semaphore */
/* clang-format off */
-#if configSUPPORT_STATIC_ALLOCATION
-#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex, stack) ((mutex) = xSemaphoreCreateMutexStatic(stack))
-#else
#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex())
-#endif
#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) \
do \
{ \
- if(NULL != (mutex)) \
+ if(NULL != mutex) \
{ \
vSemaphoreDelete(mutex); \
- (mutex) = NULL; \
+ mutex = NULL; \
} \
- } while(false)
+ } while(0)
#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \
{ \
@@ -162,49 +152,41 @@ static volatile bool s_debugConsoleReadWaitSemaphore;
}
/* Binary semaphore */
-#if configSUPPORT_STATIC_ALLOCATION
-#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary,stack) ((binary) = xSemaphoreCreateBinaryStatic(stack))
-#else
#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary())
-#endif
#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \
do \
{ \
- if(NULL != (binary)) \
+ if(NULL != binary) \
{ \
- vSemaphoreDelete((binary)); \
- (binary) = NULL; \
+ vSemaphoreDelete(binary); \
+ binary = NULL; \
} \
- } while(false)
-#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake((binary), portMAX_DELAY))
-#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR((binary), NULL))
+ } while(0)
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake(binary, portMAX_DELAY))
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR(binary, NULL))
#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE)
-#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) (void)(mutex)
-#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) (void)(mutex)
-#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) (void)(mutex)
-#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) (void)(mutex)
+#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex)
+#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex)
+#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex)
#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U)
-#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) (void)(binary)
-#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) (void)(binary)
+#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary)
+#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary)
#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \
{ \
- while (!(binary)) \
+ while (!binary) \
{ \
} \
- (binary) = false; \
+ binary = false; \
}
-#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) \
- do \
- { \
- (binary) = true; \
- } while(false)
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (binary = true)
#else
-#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (void)(binary)
-#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (void)(binary)
+#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary)
+#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary)
#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
/* clang-format on */
@@ -594,9 +576,7 @@ int DbgConsole_ReadLine(uint8_t *buf, size_t size)
}
/* take mutex lock function */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
-#endif
do
{
@@ -604,9 +584,7 @@ int DbgConsole_ReadLine(uint8_t *buf, size_t size)
if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i]))
{
/* release mutex lock function */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-#endif
i = -1;
break;
}
@@ -641,9 +619,7 @@ int DbgConsole_ReadLine(uint8_t *buf, size_t size)
}
/* release mutex lock function */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-#endif
return i;
}
@@ -660,9 +636,7 @@ int DbgConsole_ReadCharacter(uint8_t *ch)
}
/* take mutex lock function */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
-#endif
/* read one character */
if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch))
{
@@ -677,9 +651,7 @@ int DbgConsole_ReadCharacter(uint8_t *ch)
}
/* release mutex lock function */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-#endif
return ret;
}
@@ -691,7 +663,7 @@ static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal,
for (i = 0; i < len; i++)
{
- if (((uint32_t)*indicator + 1UL) >= (uint32_t)DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
+ if (((uint32_t)*indicator + 1UL) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
{
(void)DbgConsole_SendDataReliable((uint8_t *)buf, (uint32_t)(*indicator));
*indicator = 0;
@@ -708,24 +680,21 @@ static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal,
#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U))
#include "board.h"
#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
-static const serial_port_uart_config_t uartConfig = {.instance = BOARD_DEBUG_UART_INSTANCE,
- .clockRate = BOARD_DEBUG_UART_CLK_FREQ,
- .baudRate = BOARD_DEBUG_UART_BAUDRATE,
- .parityMode = kSerialManager_UartParityDisabled,
- .stopBitCount = kSerialManager_UartOneStopBit,
+static const serial_port_uart_config_t uartConfig = {
+ .instance = BOARD_DEBUG_UART_INSTANCE,
+ .clockRate = BOARD_DEBUG_UART_CLK_FREQ,
+ .baudRate = BOARD_DEBUG_UART_BAUDRATE,
+ .parityMode = kSerialManager_UartParityDisabled,
+ .stopBitCount = kSerialManager_UartOneStopBit,
#if !defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)
#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
- .mode = kSerialManager_UartBlockMode,
-#endif
+ .mode = kSerialManager_UartBlockMode,
#endif
- .enableRx = 1U,
- .enableTx = 1U,
- .enableRxRTS = 0U,
- .enableTxCTS = 0U,
-#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
- .txFifoWatermark = 0U,
- .rxFifoWatermark = 0U
#endif
+ .enableRx = 1U,
+ .enableTx = 1U,
+ .enableRxRTS = 0U,
+ .enableTxCTS = 0U,
};
#endif
#endif
@@ -752,10 +721,6 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t
.enableTx = 1,
.enableRxRTS = 0U,
.enableTxCTS = 0U,
-#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u))
- .txFifoWatermark = 0U,
- .rxFifoWatermark = 0U
-#endif
};
#endif
#endif
@@ -843,19 +808,9 @@ status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t
assert(kStatus_SerialManager_Success == status);
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
-#if configSUPPORT_STATIC_ALLOCATION
- DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore, &s_debugConsoleReadSemaphoreStatic);
-#else
DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-#endif
-#endif
#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) && configSUPPORT_STATIC_ALLOCATION
- DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore, &s_debugConsoleReadWaitSemaphoreStatic);
-#else
DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
-#endif
#endif
{
@@ -940,9 +895,7 @@ status_t DbgConsole_Deinit(void)
#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))
DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore);
#endif
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-#endif
return (status_t)kStatus_Success;
}
@@ -990,7 +943,7 @@ DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void)
#if SDK_DEBUGCONSOLE
/* See fsl_debug_console.h for documentation of this function. */
-int DbgConsole_Printf(const char *fmt_s, ...)
+int DbgConsole_Printf(const char *formatString, ...)
{
va_list ap;
int logLength = 0, dbgResult = 0;
@@ -998,9 +951,9 @@ int DbgConsole_Printf(const char *fmt_s, ...)
if (NULL != g_serialHandle)
{
- va_start(ap, fmt_s);
+ va_start(ap, formatString);
/* format print log first */
- logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_PrintCallback);
+ logLength = StrFormatPrintf(formatString, ap, printBuf, DbgConsole_PrintCallback);
/* print log */
dbgResult = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength);
@@ -1079,9 +1032,7 @@ status_t DbgConsole_TryGetchar(char *ch)
}
/* take mutex lock function */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore);
-#endif
if (kStatus_SerialManager_Success ==
SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1,
@@ -1096,9 +1047,7 @@ status_t DbgConsole_TryGetchar(char *ch)
}
}
/* release mutex lock function */
-#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS)
DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore);
-#endif
return status;
#else
return (status_t)kStatus_Fail;
diff --git a/utilities/debug_console/debug_console/fsl_debug_console.h b/utilities/debug_console/debug_console/fsl_debug_console.h
index a42f6d7d4..03cc1f8fb 100644
--- a/utilities/debug_console/debug_console/fsl_debug_console.h
+++ b/utilities/debug_console/debug_console/fsl_debug_console.h
@@ -200,10 +200,10 @@ static inline status_t DbgConsole_ExitLowpower(void)
*
* Call this function to write a formatted output to the standard output stream.
*
- * @param fmt_s Format control string.
+ * @param formatString Format control string.
* @return Returns the number of characters printed or a negative value if an error occurs.
*/
-int DbgConsole_Printf(const char *fmt_s, ...);
+int DbgConsole_Printf(const char *formatString, ...);
/*!
* @brief Writes a character to stdout.
diff --git a/utilities/debug_console_lite/utility_debug_console_lite.cmake b/utilities/debug_console_lite/utility_debug_console_lite.cmake
index a34b19cfc..b68505eac 100644
--- a/utilities/debug_console_lite/utility_debug_console_lite.cmake
+++ b/utilities/debug_console_lite/utility_debug_console_lite.cmake
@@ -11,23 +11,20 @@ target_include_directories(${MCUX_SDK_PROJECT_NAME} PUBLIC
)
#OR Logic component
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC845")
- include(component_miniusart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "LPC812")
- include(component_miniusart_adapter)
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
+ include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK28FA15")
+if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC802")
- include(component_miniusart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC51U68")
+ include(component_usart_adapter)
endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm0plus")
include(component_usart_adapter)
@@ -35,121 +32,124 @@ endif()
if(${MCUX_DEVICE} STREQUAL "LPC54114_cm4")
include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
- include(component_iuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC54628")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
- include(component_iuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC54S018")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2B31A")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC55S16")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK64F12")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC55S28")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK66F18")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1")
+ include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "LPC802")
+ include(component_miniusart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
+if(${MCUX_DEVICE} STREQUAL "LPC804")
+ include(component_miniusart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "LPC812")
+ include(component_miniusart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "LPC824")
+ include(component_miniusart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "LPC845")
+ include(component_miniusart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMX8MM6")
+ include(component_iuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
+ include(component_iuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54628")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMX8MQ6")
+ include(component_iuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MK22F51212")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core0")
+ include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE06Z4")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMX8QM6_cm4_core1")
+ include(component_lpuart_adapter)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMX8QX6")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC824")
- include(component_miniusart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+ include(component_lpuart_adapter)
+endif()
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
+ include(component_lpuart_adapter)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1021")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE02Z4")
- include(component_uart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+ include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S16")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1052")
+ include(component_lpuart_adapter)
endif()
if(${MCUX_DEVICE} STREQUAL "MIMXRT1062")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMX8MN6")
- include(component_iuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MIMXRT1064")
+ include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54S018")
+if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
include(component_usart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKE04Z4")
+if(${MCUX_DEVICE} STREQUAL "MK22F51212")
include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC804")
- include(component_miniusart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm0plus")
- include(component_lpuart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L3A60_cm4")
+if(${MCUX_DEVICE} STREQUAL "MK28FA15")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC54S018M")
- include(component_usart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+if(${MCUX_DEVICE} STREQUAL "MK64F12")
include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC51U68")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MK66F18")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKE02Z4")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core0")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKE04Z4")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S69_cm33_core1")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKE06Z4")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MCIMX7U5")
+if(${MCUX_DEVICE} STREQUAL "MKE15Z7")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1024")
+if(${MCUX_DEVICE} STREQUAL "MKE16Z4")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1011")
+if(${MCUX_DEVICE} STREQUAL "MKL27Z644")
include(component_lpuart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "LPC55S28")
- include(component_usart_adapter)
-endif()
-if(${MCUX_DEVICE} STREQUAL "K32L2A41A")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKM35Z7")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT685S_cm33")
- include(component_usart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKV11Z7")
+ include(component_uart_adapter)
endif()
-if(${MCUX_DEVICE} STREQUAL "MIMXRT1015")
- include(component_lpuart_adapter)
+if(${MCUX_DEVICE} STREQUAL "MKV31F51212")
+ include(component_uart_adapter)
endif()
diff --git a/west.yml b/west.yml
index 5a80705f3..7ffeb1644 100644
--- a/west.yml
+++ b/west.yml
@@ -10,25 +10,23 @@
# See the west documentation for more information:
#
# https://docs.zephyrproject.org/latest/guides/west/index.html
-
manifest:
-
remotes:
- name: nxpmicro
url-base: https://github.com/NXPmicro
-
+ - name: nxp
+ url-base: https://github.com/NXP
defaults:
remote: nxpmicro
-
projects:
- name: mcux-sdk-examples
- revision: 62f5041d6d7da742ffd7ea0f8f017a670af450e8
+ revision: MCUX_2.9.4_MW320
path: examples
- name: FreeRTOS-Kernel
- revision: 030849f81f057eea51527f63cb5ecc28283d2275
+ revision: MCUX_2.9.4_MW320
path: rtos/freertos/freertos_kernel
- name: mcux-sdk-middleware-sdmmc
- revision: MCUX_2.9.0
+ revision: 3789034d53336cf6ca73d7777aa05fd7d2d81ad3
path: middleware/sdmmc
- name: mcux-sdk-middleware-multicore
path: middleware/multicore
@@ -41,6 +39,15 @@ manifest:
path: middleware/multicore/erpc
url: https://github.com/EmbeddedRPC/erpc
revision: 1.8.0
-
+ - name: lwip
+ path: middleware/lwip
+ revision: 4ef9433dee75f3597f782d817a432b0cf950750d
+ - name: mbedtls
+ path: middleware/mbedtls
+ revision: 75010b7b49c72067f4c3e57361975069075bca74
+ - name: wifi_nxp
+ path: middleware/wifi
+ revision: 8fbb64dd7a0384efdd46dd5fe8ea8172b70e7adb
+ remote: nxp
self:
path: core