From cdea0b54142dcb1c7cbd04c637fed38d234aa4ef Mon Sep 17 00:00:00 2001 From: Susan Su Date: Tue, 31 Aug 2021 21:01:51 +0800 Subject: [PATCH 1/4] zephyr: Enable NXP HAL support in mcux-sdk - For device, board support and mcux drivers, change to use that in mcux-sdk offerring. - For middleware, imx drivers and the component drivers, keep using existing enablement in hal-nxp. Signed-off-by: Susan Su --- CMakeLists.txt | 78 + zephyr/components/mcr20a/MCR20Overwrites.h | 309 + zephyr/components/phyksz8081/fsl_phy.c | 301 + zephyr/components/phyksz8081/fsl_phy.h | 206 + zephyr/hal_nxp.cmake | 231 + zephyr/imx/CMakeLists.txt | 8 + zephyr/imx/README | 52 + zephyr/imx/devices/CMakeLists.txt | 1 + zephyr/imx/devices/MCIMX6X/CMakeLists.txt | 2 + zephyr/imx/devices/MCIMX6X/MCIMX6X_M4.h | 41139 ++++++++++++++ zephyr/imx/devices/MCIMX6X/clock_freq.c | 265 + zephyr/imx/devices/MCIMX6X/clock_freq.h | 90 + zephyr/imx/devices/MCIMX7D/CMakeLists.txt | 2 + zephyr/imx/devices/MCIMX7D/MCIMX7D_M4.h | 44765 ++++++++++++++++ zephyr/imx/devices/MCIMX7D/clock_freq.c | 267 + zephyr/imx/devices/MCIMX7D/clock_freq.h | 99 + zephyr/imx/devices/device_imx.h | 74 + zephyr/imx/drivers/CMakeLists.txt | 21 + zephyr/imx/drivers/adc_imx6sx.c | 519 + zephyr/imx/drivers/adc_imx6sx.h | 513 + zephyr/imx/drivers/adc_imx7d.c | 803 + zephyr/imx/drivers/adc_imx7d.h | 555 + zephyr/imx/drivers/ccm_analog_imx6sx.c | 192 + zephyr/imx/drivers/ccm_analog_imx6sx.h | 340 + zephyr/imx/drivers/ccm_analog_imx7d.c | 270 + zephyr/imx/drivers/ccm_analog_imx7d.h | 398 + zephyr/imx/drivers/ccm_imx6sx.c | 67 + zephyr/imx/drivers/ccm_imx6sx.h | 785 + zephyr/imx/drivers/ccm_imx7d.c | 85 + zephyr/imx/drivers/ccm_imx7d.h | 470 + zephyr/imx/drivers/ecspi.c | 205 + zephyr/imx/drivers/ecspi.h | 493 + zephyr/imx/drivers/epit.c | 89 + zephyr/imx/drivers/epit.h | 326 + zephyr/imx/drivers/flexcan.c | 1073 + zephyr/imx/drivers/flexcan.h | 712 + zephyr/imx/drivers/gpio_imx.c | 162 + zephyr/imx/drivers/gpio_imx.h | 272 + zephyr/imx/drivers/gpt.c | 91 + zephyr/imx/drivers/gpt.h | 414 + zephyr/imx/drivers/i2c_imx.c | 167 + zephyr/imx/drivers/i2c_imx.h | 284 + zephyr/imx/drivers/lmem.c | 348 + zephyr/imx/drivers/lmem.h | 174 + zephyr/imx/drivers/mu_imx.c | 155 + zephyr/imx/drivers/mu_imx.h | 569 + zephyr/imx/drivers/rdc.c | 89 + zephyr/imx/drivers/rdc.h | 270 + zephyr/imx/drivers/rdc_defs_imx6sx.h | 210 + zephyr/imx/drivers/rdc_defs_imx7d.h | 222 + zephyr/imx/drivers/rdc_semaphore.c | 187 + zephyr/imx/drivers/rdc_semaphore.h | 140 + zephyr/imx/drivers/sema4.c | 199 + zephyr/imx/drivers/sema4.h | 278 + zephyr/imx/drivers/uart_imx.c | 612 + zephyr/imx/drivers/uart_imx.h | 779 + zephyr/imx/drivers/wdog_imx.c | 81 + zephyr/imx/drivers/wdog_imx.h | 193 + zephyr/middleware/usb/CMakeLists.txt | 15 + zephyr/middleware/usb/device/CMakeLists.txt | 9 + zephyr/middleware/usb/device/usb_device.h | 660 + zephyr/middleware/usb/device/usb_device_dci.h | 140 + .../middleware/usb/device/usb_device_ehci.c | 1974 + .../middleware/usb/device/usb_device_ehci.h | 296 + .../usb/device/usb_device_lpcip3511.c | 2335 + .../usb/device/usb_device_lpcip3511.h | 274 + zephyr/middleware/usb/include/usb.h | 132 + zephyr/middleware/usb/include/usb_spec.h | 299 + zephyr/middleware/usb/phy/CMakeLists.txt | 8 + zephyr/middleware/usb/phy/usb_phy.c | 278 + zephyr/middleware/usb/phy/usb_phy.h | 105 + .../wireless/framework_5.3.3/CMakeLists.txt | 7 + .../framework_5.3.3/Common/EmbeddedTypes.h | 215 + .../Interface/fsl_os_abstraction.h | 608 + .../Interface/fsl_os_abstraction_config.h | 63 + .../Source/fsl_os_abstraction_zephyr.c | 29 + .../XCVR/MKW40Z4/BLEDefaults.h | 433 + .../XCVR/MKW40Z4/CMakeLists.txt | 5 + .../XCVR/MKW40Z4/KW4xXcvrDrv.c | 2332 + .../XCVR/MKW40Z4/KW4xXcvrDrv.h | 165 + .../XCVR/MKW40Z4/ZigbeeDefaults.h | 105 + .../framework_5.3.3/XCVR/MKW40Z4/fsl_xcvr.h | 36 + .../XCVR/MKW40Z4/ifr_mkw40z4_radio.c | 392 + .../XCVR/MKW40Z4/ifr_mkw40z4_radio.h | 180 + .../XCVR/MKW40Z4/ifr_tbl_mkw40z4_radio.h | 172 + .../framework_5.3.3/XCVR/MKW40Z4/overwrites.h | 323 + .../XCVR/MKW40Z4/tsm_ll_timing.c | 218 + .../XCVR/MKW40Z4/tsm_ll_timing.h | 113 + .../XCVR/MKW40Z4/tsm_timing_ble.h | 368 + .../XCVR/MKW40Z4/tsm_timing_zigbee.h | 66 + .../XCVR/MKW41Z4/CMakeLists.txt | 18 + .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c | 212 + .../XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h | 157 + .../cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c | 207 + .../cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c | 201 + .../cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c | 623 + .../fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c | 353 + .../fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c | 341 + .../fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c | 356 + .../fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c | 341 + .../fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c | 340 + .../fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c | 353 + .../fsl_xcvr_mode_datarate_config.c | 212 + .../cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c | 343 + .../cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c | 244 + .../XCVR/MKW41Z4/dbg_ram_capture.c | 160 + .../XCVR/MKW41Z4/dbg_ram_capture.h | 206 + .../framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.c | 2123 + .../framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.h | 1236 + .../XCVR/MKW41Z4/fsl_xcvr_trim.c | 995 + .../XCVR/MKW41Z4/fsl_xcvr_trim.h | 132 + .../framework_5.3.3/XCVR/MKW41Z4/ifr_radio.c | 530 + .../framework_5.3.3/XCVR/MKW41Z4/ifr_radio.h | 199 + zephyr/module.yml | 4 + 114 files changed, 123942 insertions(+) create mode 100644 CMakeLists.txt create mode 100644 zephyr/components/mcr20a/MCR20Overwrites.h create mode 100644 zephyr/components/phyksz8081/fsl_phy.c create mode 100644 zephyr/components/phyksz8081/fsl_phy.h create mode 100644 zephyr/hal_nxp.cmake create mode 100644 zephyr/imx/CMakeLists.txt create mode 100644 zephyr/imx/README create mode 100644 zephyr/imx/devices/CMakeLists.txt create mode 100644 zephyr/imx/devices/MCIMX6X/CMakeLists.txt create mode 100644 zephyr/imx/devices/MCIMX6X/MCIMX6X_M4.h create mode 100644 zephyr/imx/devices/MCIMX6X/clock_freq.c create mode 100644 zephyr/imx/devices/MCIMX6X/clock_freq.h create mode 100644 zephyr/imx/devices/MCIMX7D/CMakeLists.txt create mode 100644 zephyr/imx/devices/MCIMX7D/MCIMX7D_M4.h create mode 100644 zephyr/imx/devices/MCIMX7D/clock_freq.c create mode 100644 zephyr/imx/devices/MCIMX7D/clock_freq.h create mode 100644 zephyr/imx/devices/device_imx.h create mode 100644 zephyr/imx/drivers/CMakeLists.txt create mode 100644 zephyr/imx/drivers/adc_imx6sx.c create mode 100644 zephyr/imx/drivers/adc_imx6sx.h create mode 100644 zephyr/imx/drivers/adc_imx7d.c create mode 100644 zephyr/imx/drivers/adc_imx7d.h create mode 100644 zephyr/imx/drivers/ccm_analog_imx6sx.c create mode 100644 zephyr/imx/drivers/ccm_analog_imx6sx.h create mode 100644 zephyr/imx/drivers/ccm_analog_imx7d.c create mode 100644 zephyr/imx/drivers/ccm_analog_imx7d.h create mode 100644 zephyr/imx/drivers/ccm_imx6sx.c create mode 100644 zephyr/imx/drivers/ccm_imx6sx.h create mode 100644 zephyr/imx/drivers/ccm_imx7d.c create mode 100644 zephyr/imx/drivers/ccm_imx7d.h create mode 100644 zephyr/imx/drivers/ecspi.c create mode 100644 zephyr/imx/drivers/ecspi.h create mode 100644 zephyr/imx/drivers/epit.c create mode 100644 zephyr/imx/drivers/epit.h create mode 100644 zephyr/imx/drivers/flexcan.c create mode 100644 zephyr/imx/drivers/flexcan.h create mode 100644 zephyr/imx/drivers/gpio_imx.c create mode 100644 zephyr/imx/drivers/gpio_imx.h create mode 100644 zephyr/imx/drivers/gpt.c create mode 100644 zephyr/imx/drivers/gpt.h create mode 100644 zephyr/imx/drivers/i2c_imx.c create mode 100644 zephyr/imx/drivers/i2c_imx.h create mode 100644 zephyr/imx/drivers/lmem.c create mode 100644 zephyr/imx/drivers/lmem.h create mode 100644 zephyr/imx/drivers/mu_imx.c create mode 100644 zephyr/imx/drivers/mu_imx.h create mode 100644 zephyr/imx/drivers/rdc.c create mode 100644 zephyr/imx/drivers/rdc.h create mode 100644 zephyr/imx/drivers/rdc_defs_imx6sx.h create mode 100644 zephyr/imx/drivers/rdc_defs_imx7d.h create mode 100644 zephyr/imx/drivers/rdc_semaphore.c create mode 100644 zephyr/imx/drivers/rdc_semaphore.h create mode 100644 zephyr/imx/drivers/sema4.c create mode 100644 zephyr/imx/drivers/sema4.h create mode 100644 zephyr/imx/drivers/uart_imx.c create mode 100644 zephyr/imx/drivers/uart_imx.h create mode 100644 zephyr/imx/drivers/wdog_imx.c create mode 100644 zephyr/imx/drivers/wdog_imx.h create mode 100644 zephyr/middleware/usb/CMakeLists.txt create mode 100644 zephyr/middleware/usb/device/CMakeLists.txt create mode 100644 zephyr/middleware/usb/device/usb_device.h create mode 100644 zephyr/middleware/usb/device/usb_device_dci.h create mode 100644 zephyr/middleware/usb/device/usb_device_ehci.c create mode 100644 zephyr/middleware/usb/device/usb_device_ehci.h create mode 100644 zephyr/middleware/usb/device/usb_device_lpcip3511.c create mode 100644 zephyr/middleware/usb/device/usb_device_lpcip3511.h create mode 100644 zephyr/middleware/usb/include/usb.h create mode 100644 zephyr/middleware/usb/include/usb_spec.h create mode 100644 zephyr/middleware/usb/phy/CMakeLists.txt create mode 100644 zephyr/middleware/usb/phy/usb_phy.c create mode 100644 zephyr/middleware/usb/phy/usb_phy.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/CMakeLists.txt create mode 100644 zephyr/middleware/wireless/framework_5.3.3/Common/EmbeddedTypes.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Interface/fsl_os_abstraction.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Interface/fsl_os_abstraction_config.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Source/fsl_os_abstraction_zephyr.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/BLEDefaults.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/CMakeLists.txt create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/KW4xXcvrDrv.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/KW4xXcvrDrv.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ZigbeeDefaults.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/fsl_xcvr.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ifr_mkw40z4_radio.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ifr_mkw40z4_radio.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ifr_tbl_mkw40z4_radio.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/overwrites.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/tsm_ll_timing.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/tsm_ll_timing.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/tsm_timing_ble.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/tsm_timing_zigbee.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/CMakeLists.txt create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/dbg_ram_capture.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/dbg_ram_capture.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr_trim.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr_trim.h create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ifr_radio.c create mode 100644 zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ifr_radio.h create mode 100644 zephyr/module.yml diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 000000000..df55d77c1 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,78 @@ +if(CONFIG_HAS_MCUX OR CONFIG_HAS_IMX_HAL) + zephyr_library() +endif() + +set(MCUX_SDK_PROJECT_NAME ${ZEPHYR_CURRENT_LIBRARY}) +# Translate the SoC name and part number into the mcux device and cpu +# name respectively. +string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE) + +if("${MCUX_DEVICE}" STREQUAL "LPC54114") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm4) +elseif("${MCUX_DEVICE}" STREQUAL "LPC54114_M0") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm0plus) + set(MCUX_DEVICE LPC54114) +elseif("${MCUX_DEVICE}" STREQUAL "LPC55S16") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}) +elseif("${MCUX_DEVICE}" STREQUAL "LPC55S28") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}) +elseif("${MCUX_DEVICE}" STREQUAL "LPC55S69_CPU0") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33_core0) + set(MCUX_DEVICE LPC55S69) +elseif("${MCUX_DEVICE}" STREQUAL "LPC55S69_CPU1") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33_core1) + set(MCUX_DEVICE LPC55S69) +elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1052") + string(REGEX REPLACE "(.*)[AB]$" "CPU_\\1B" MCUX_CPU ${CONFIG_SOC_PART_NUMBER}) +elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT685S_CM33") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33) + set(MCUX_DEVICE MIMXRT685S) +elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1176_CM4") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm4) + set(MCUX_DEVICE MIMXRT1176) +elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1176_CM7") + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm7) + set(MCUX_DEVICE MIMXRT1176) +else() + set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}) +endif() + +zephyr_include_directories(devices/${MCUX_DEVICE}) +zephyr_include_directories(devices/${MCUX_DEVICE}/drivers) +# The mcux uses the cpu name to expose SoC-specific features of a +# given peripheral. For example, the UART peripheral may be +# instantiated with/without a hardware FIFO, and the size of that FIFO +# may be different for each instance in a given SoC. See +# fsl_device_registers.h and ${MCUX_DEVICE}_features.h +zephyr_compile_definitions(${MCUX_CPU}) + +# Build mcux device-specific objects. Although it is not normal +# practice, drilling down like this avoids the need for repetitive +# build scripts for every mcux device. +zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_clock.c) +if (${MCUX_DEVICE} MATCHES "LPC|MIMXRT6") + zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_power.c) + zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_reset.c) + + if ((${MCUX_DEVICE} MATCHES "MIMXRT6") AND (CONFIG_PM)) + zephyr_code_relocate(devices/${MCUX_DEVICE}/drivers/fsl_power.c SRAM) + endif() +endif() + +if (${MCUX_DEVICE} MATCHES "MIMXRT117") + zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_romapi.c) + zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_pmu.c) + zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_dcdc.c) + zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_anatop_ai.c) + if ("${MCUX_DEVICE}" STREQUAL "MIMXRT1176_CM4") + zephyr_include_directories(devices/${MCUX_DEVICE}/cm4/) + zephyr_library_sources_ifdef( + CONFIG_HAS_MCUX_CACHE + devices/${MCUX_DEVICE}/cm4/fsl_cache.c + ) + endif() +endif() + +#Include Entry cmake component +include(${CMAKE_CURRENT_LIST_DIR}/zephyr/hal_nxp.cmake) +enable_language(C ASM) diff --git a/zephyr/components/mcr20a/MCR20Overwrites.h b/zephyr/components/mcr20a/MCR20Overwrites.h new file mode 100644 index 000000000..4b0221132 --- /dev/null +++ b/zephyr/components/mcr20a/MCR20Overwrites.h @@ -0,0 +1,309 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* \file MCR20Overwrites.h +* Description: Overwrites header file for MCR20 Register values +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef OVERWRITES_H_ +#define OVERWRITES_H_ + +typedef struct overwrites_tag { + char address; + char data; +}overwrites_t; + + +/*****************************************************************************************************************/ +// This file is created exclusively for use with the transceiver 2.0 silicon +// and is provided for the world to use. It contains a list of all +// known overwrite values. Overwrite values are non-default register +// values that configure the transceiver device to a more optimally performing +// posture. It is expected that low level software (i.e. PHY) will +// consume this file as a #include, and transfer the contents to the +// the indicated addresses in the transceiver's memory space. This file has +// at least one required entry, that being its own version current version +// number, to be stored at transceiver's location 0x3B the +// OVERWRITES_VERSION_NUMBER register. The RAM register is provided in +// the transceiver address space to assist in future debug efforts. The +// analyst may read this location (once device has been booted with +// mysterious software) and have a good indication of what register +// overwrites were performed (with all versions of the overwrites.h file +// being archived forever at the Compass location shown above. +// +// The transceiver has an indirect register (IAR) space. Write access to this space +// requires 3 or more writes: +// 1st) the first write is an index value to the indirect (write Bit7=0, register access Bit 6=0) + 0x3E +// 2nd) IAR Register #0x00 - 0xFF. +// 3rd) The data to write +// nth) Burst mode additional data if required. +// +// Write access to direct space requires only a single address, data pair. + +overwrites_t const overwrites_direct[] ={ +{0x3B, 0x0C}, //version 0C: new value for ACKDELAY targeting 198us (23 May, 2013, Larry Roshak) +{0x23, 0x17} //PA_PWR new default Power Step is "23" +}; + +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) +{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x55}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x68, 0x61}, //RSSI_OFFSET +{0x78, 0x03}, //CHF_PMAGAIN +{0x22, 0x50}, //CCA1_THRESH +{0x4D, 0x13}, //CORR_NVAL moved from 0x14 to 0x13 for 0.5 dB improved Rx Sensitivity +{0x39, 0x3D} //ACKDELAY new value targeting a delay of 198us (23 May, 2013, Larry Roshak) +}; + + +/* begin of deprecated versions + +==VERSION 1== +(version 1 is empty) + +==VERSION 2== +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02} //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +}; + +==VERSION 3== +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3 +{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +}; + +==VERSION 4== +overwrites_t const overwrites_direct[] ={ +{0x3B, 0x04} //version 04 is the current version: update PA_COILTUNING default +}; + +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1: override VCOALC_REF_TX to 3 +{0x92, 0x07} //VCO_CTRL2: override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x8A, 0x71} //PA_TUNING: override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) +}; + +==VERSION 5== +overwrites_t const overwrites_direct[] ={ +{0x3B, 0x05} //version 05: updates Channel Filter Register set (21 Dec 2012, on behalf of S. Soca) +}; + +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) +{0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +}; + +==VERSION 6== +overwrites_t const overwrites_direct[] ={ +{0x3B, 0x06} //version 06: disable PA calibration +}; + +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07} //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x8A, 0x71} //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) +{0x79, 0x2F} //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7A, 0x2F} //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7B, 0x24} //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7C, 0x24} //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7D, 0x24} //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7E, 0x24} //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x82, 0x24} //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x83, 0x24} //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7F, 0x32} //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x80, 0x1D} //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x81, 0x2D} //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x64, 0x28} //PA_CAL_DIS=1 Disabled PA calibration +}; + +==VERSION 7== +overwrites_t const overwrites_direct[] ={ +{0x3B, 0x07} //version 07: updated registers for ED/RSSI +}; + +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) +{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x73}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x68, 0x60}, //RSSI_OFFSET +{0x69, 0x65} //RSSI_SLOPE +}; + + +==VERSION 8== +overwrites_t const overwrites_direct[] ={ +{0x3B, 0x08} //version 08: updated registers for ED/RSSI +}; + +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) +{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x73}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x69, 0x65} //RSSI_SLOPE +{0x68, 0x61}, //RSSI_OFFSET +{0x78, 0x03} //CHF_PMAGAIN +}; + + +==VERSION 9== +overwrites_t const overwrites_direct[] ={ +{0x3B, 0x09} //version 09: updated registers for ED/RSSI and PowerStep +{0x23, 0x17} //PA_PWR new default value +}; + +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) +{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x55}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x68, 0x61}, //RSSI_OFFSET +{0x78, 0x03} //CHF_PMAGAIN +}; + +==VERSION A== +overwrites_t const overwrites_direct[] ={ +{0x3B, 0x0A} //version 0A: updated registers for CCA +{0x23, 0x17} //PA_PWR new default Power Step is "23" +}; + +overwrites_t const overwrites_indirect[] ={ +{0x31, 0x02}, //clear MISO_HIZ_EN (for single SPI master/slave pair) and SPI_PUL_EN (minimize HIB currents) +{0x91, 0xB3}, //VCO_CTRL1 override VCOALC_REF_TX to 3 +{0x92, 0x07}, //VCO_CTRL2 override VCOALC_REF_RX to 3, keep VCO_BUF_BOOST = 1 +{0x8A, 0x71}, //PA_TUNING override PA_COILTUNING to 001 (27 Nov 2012, D. Brown, on behalf of S. Eid) +{0x79, 0x2F}, //CHF_IBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7A, 0x2F}, //CHF_QBUF Adjust the gm-C filter gain (+/- 6dB) (21 Dec, 2012, on behalf of S. Soca) +{0x7B, 0x24}, //CHF_IRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7C, 0x24}, //CHF_QRIN Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7D, 0x24}, //CHF_IL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7E, 0x24}, //CHF_QL Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x7F, 0x32}, //CHF_CC1 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x80, 0x1D}, //CHF_CCL Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x81, 0x2D}, //CHF_CC2 Adjust the filter center frequency (+/- 1MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x82, 0x24}, //CHF_IROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x83, 0x24}, //CHF_QROUT Adjust the filter bandwidth (+/- 0.5MHz) (21 Dec, 2012, on behalf of S. Soca) +{0x64, 0x28}, //PA_CAL_DIS=1 Disabled PA calibration +{0x52, 0x55}, //AGC_THR1 RSSI tune up +{0x53, 0x2D}, //AGC_THR2 RSSI tune up +{0x66, 0x5F}, //ATT_RSSI1 tune up +{0x67, 0x8F}, //ATT_RSSI2 tune up +{0x68, 0x61}, //RSSI_OFFSET +{0x78, 0x03} //CHF_PMAGAIN +{0x22, 0x50} //CCA1_THRESH +}; + +end of deprecated versions */ + + +#endif //OVERWRITES_H_ + diff --git a/zephyr/components/phyksz8081/fsl_phy.c b/zephyr/components/phyksz8081/fsl_phy.c new file mode 100644 index 000000000..627c71273 --- /dev/null +++ b/zephyr/components/phyksz8081/fsl_phy.c @@ -0,0 +1,301 @@ +/* +* Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP +* All rights reserved. +* + * SPDX-License-Identifier: BSD-3-Clause +*/ + +#include "fsl_phy.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines the timeout macro. */ +#define PHY_TIMEOUT_COUNT 100000U + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz) +{ + uint32_t bssReg; + uint32_t counter = PHY_TIMEOUT_COUNT; + uint32_t idReg = 0; + status_t result = kStatus_Success; + uint32_t instance = ENET_GetInstance(base); + uint32_t timeDelay; + uint32_t ctlReg = 0; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Set SMI first. */ + CLOCK_EnableClock(s_enetClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + ENET_SetSMI(base, srcClock_Hz, false); + + /* Initialization after PHY stars to work. */ + while ((idReg != PHY_CONTROL_ID1) && (counter != 0U)) + { + (void)PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg); + counter--; + } + + if (counter == 0U) + { + return kStatus_Fail; + } + + /* Reset PHY. */ + counter = PHY_TIMEOUT_COUNT; + result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK); + if (result == kStatus_Success) + { +#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE) + uint32_t data = 0; + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result != kStatus_Success) + { + return result; + } + result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK)); + if (result != kStatus_Success) + { + return result; + } +#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */ + + /* Set the negotiation. */ + result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, + (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | + PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U)); + if (result == kStatus_Success) + { + result = + PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK)); + if (result == kStatus_Success) + { + /* Check auto negotiation complete. */ + while (counter-- != 0U) + { + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg); + if ( result == kStatus_Success) + { + (void)PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); + if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U) && ((ctlReg & PHY_LINK_READY_MASK) != 0U)) + { + /* Wait a moment for Phy status stable. */ + for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay++) + { + __ASM("nop"); + } + break; + } + } + + if (counter == 0U) + { + return kStatus_PHY_AutoNegotiateFail; + } + } + } + } + } + + return result; +} + +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data) +{ + uint32_t counter; + + /* Clear the SMI interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI write command. */ + ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data); + + /* Wait for SMI complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0U; counter--) + { + if ((ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) != 0U) + { + break; + } + } + + /* Check for timeout. */ + if (counter == 0U) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr) +{ + assert(dataPtr); + + uint32_t counter; + + /* Clear the MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + /* Starts a SMI read command operation. */ + ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame); + + /* Wait for MII complete. */ + for (counter = PHY_TIMEOUT_COUNT; counter > 0U; counter--) + { + if ((ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) != 0U) + { + break; + } + } + + /* Check for timeout. */ + if (counter == 0U) + { + return kStatus_PHY_SMIVisitTimeout; + } + + /* Get data from MII register. */ + *dataPtr = ENET_ReadSMIData(base); + + /* Clear MII interrupt event. */ + ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK); + + return kStatus_Success; +} + +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable) +{ + status_t result; + uint32_t data = 0; + + /* Set the loop mode. */ + if (enable) + { + if (mode == kPHY_LocalLoop) + { + if (speed == kPHY_Speed100M) + { + data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + else + { + data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK; + } + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data); + } + else + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + else + { + /* Disable the loop mode. */ + if (mode == kPHY_LocalLoop) + { + /* First read the current status in control register. */ + result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data); + if (result == kStatus_Success) + { + data &= ~PHY_BCTL_LOOP_MASK; + return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK)); + } + } + else + { + /* First read the current status in control one register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data); + if (result == kStatus_Success) + { + return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK)); + } + } + } + return result; +} + +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status) +{ + assert(status); + + status_t result = kStatus_Success; + uint32_t data; + + /* Read the basic status register. */ + result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data); + if (result == kStatus_Success) + { + if ((PHY_BSTATUS_LINKSTATUS_MASK & data) == 0U) + { + /* link down. */ + *status = false; + } + else + { + /* link up. */ + *status = true; + } + } + return result; +} + +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex) +{ + assert(duplex); + + status_t result = kStatus_Success; + uint32_t data, ctlReg; + + /* Read the control two register. */ + result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg); + if (result == kStatus_Success) + { + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* Full duplex. */ + *duplex = kPHY_FullDuplex; + } + else + { + /* Half duplex. */ + *duplex = kPHY_HalfDuplex; + } + + data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK; + if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data)) + { + /* 100M speed. */ + *speed = kPHY_Speed100M; + } + else + { /* 10M speed. */ + *speed = kPHY_Speed10M; + } + } + + return result; +} diff --git a/zephyr/components/phyksz8081/fsl_phy.h b/zephyr/components/phyksz8081/fsl_phy.h new file mode 100644 index 000000000..104d0cdfd --- /dev/null +++ b/zephyr/components/phyksz8081/fsl_phy.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_PHY_H_ +#define _FSL_PHY_H_ + +#include "fsl_enet.h" + +/*! + * @addtogroup phy_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief PHY driver version */ +#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ + +/*! @brief Defines the PHY registers. */ +#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */ +#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */ +#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */ +#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */ +#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */ +#define PHY_OMS_OVERRIDE_REG 0x16U /*!< The PHY Operation Mode Strap Override register. */ +#define PHY_OMS_STATUS_REG 0x17U /*!< The PHY Operation Mode Strap Status register. */ +#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */ +#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */ + +#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/ + +/*! @brief Defines the mask flag in basic control register. */ +#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */ +#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */ +#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */ +#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */ +#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */ +#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */ +#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */ + +/*!@brief Defines the mask flag of operation mode in control two register*/ +#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */ +#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ +#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */ +#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */ +#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */ +#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */ +#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */ +#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */ +#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */ +#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK) + +/*! @brief Defines the mask flag in basic status register. */ +#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */ +#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */ +#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */ + +/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */ +#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */ +#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/ +#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/ +#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/ + +/*! @brief Defines the mask flag in PHY Operation Mode Strap Override/Status register. */ +#define PHY_OMS_NANDTREE_MASK 0x0020U /*!< The PHY NAND Tree Strap-In Override/Status mask. */ +#define PHY_OMS_FACTORY_MODE_MASK 0x8000U /*!< The factory mode Override/Status mask. */ + +/*! @brief Defines the PHY status. */ +enum +{ + kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */ + kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */ +}; + +/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */ +typedef enum _phy_speed +{ + kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */ + kPHY_Speed100M /*!< ENET PHY 100M speed. */ +} phy_speed_t; + +/*! @brief Defines the PHY link duplex. */ +typedef enum _phy_duplex +{ + kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */ + kPHY_FullDuplex /*!< ENET PHY full duplex. */ +} phy_duplex_t; + +/*! @brief Defines the PHY loopback mode. */ +typedef enum _phy_loop +{ + kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */ + kPHY_RemoteLoop /*!< ENET PHY remote loopback. */ +} phy_loop_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name PHY Driver + * @{ + */ + +/*! + * @brief Initializes PHY. + * + * This function initialize the SMI interface and initialize PHY. + * The SMI is the MII management interface between PHY and MAC, which should be + * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI. + * @retval kStatus_Success PHY initialize success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + * @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail + */ +status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz); + +/*! + * @brief PHY Write function. This function write data over the SMI to + * the specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param data The data written to the PHY register. + * @retval kStatus_Success PHY write success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data); + +/*! + * @brief PHY Read function. This interface read data over the SMI from the + * specified PHY register. This function is called by all PHY interfaces. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param phyReg The PHY register. + * @param dataPtr The address to store the data read from the PHY register. + * @retval kStatus_Success PHY read success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr); + +/*! + * @brief Enables/disables PHY loopback. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param mode The loopback mode to be enabled, please see "phy_loop_t". + * the two loopback mode should not be both set. when one loopback mode is set + * the other one should be disabled. + * @param speed PHY speed for loopback mode. + * @param enable True to enable, false to disable. + * @retval kStatus_Success PHY loopback success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable); + +/*! + * @brief Gets the PHY link status. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param status The link up or down status of the PHY. + * - true the link is up. + * - false the link is down. + * @retval kStatus_Success PHY get link status success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status); + +/*! + * @brief Gets the PHY link speed and duplex. + * + * @param base ENET peripheral base address. + * @param phyAddr The PHY address. + * @param speed The address of PHY link speed. + * @param duplex The link duplex of PHY. + * @retval kStatus_Success PHY get link speed and duplex success + * @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out + */ +status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_PHY_H_ */ diff --git a/zephyr/hal_nxp.cmake b/zephyr/hal_nxp.cmake new file mode 100644 index 000000000..c2079435a --- /dev/null +++ b/zephyr/hal_nxp.cmake @@ -0,0 +1,231 @@ +CMAKE_MINIMUM_REQUIRED (VERSION 3.10.0) + +list(APPEND CMAKE_MODULE_PATH + ${CMAKE_CURRENT_LIST_DIR}/../devices/${MCUX_DEVICE} + ${CMAKE_CURRENT_LIST_DIR}/../devices/${MCUX_DEVICE}/drivers + ${CMAKE_CURRENT_LIST_DIR}/../drivers/common + ${CMAKE_CURRENT_LIST_DIR}/../CMSIS/Core/Include +) + +function(include_ifdef feature_toggle module) + if(${${feature_toggle}}) + include(${module}) + endif() +endfunction() + +function(include_driver_ifdef feature_toggle directory module) + if(${${feature_toggle}}) + list(APPEND CMAKE_MODULE_PATH + ${CMAKE_CURRENT_LIST_DIR}/../drivers/${directory} + ) + zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/${directory}) + include(${module}) + endif() +endfunction() + +message("Load components for ${MCUX_DEVICE}:") + +include(driver_common) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/common) + +#specific operation to shared drivers +if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(fsl_flexspi.c ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT) +endif() + +if(NOT CONFIG_ASSERT OR CONFIG_FORCE_NO_ASSERT) + zephyr_compile_definitions(NDEBUG) # squelch fsl_flexcan.c warning +endif() + +zephyr_library_compile_definitions_ifdef( + CONFIG_HAS_MCUX_CACHE FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL +) + +if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(fsl_flexspi.c ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT) +endif() + +#include shared drivers +include_driver_ifdef(CONFIG_ADC_MCUX_LPADC lpadc driver_lpadc) +include_driver_ifdef(CONFIG_COUNTER_MCUX_CTIMER ctimer driver_ctimer) +include_driver_ifdef(CONFIG_COUNTER_MCUX_LPC_RTC lpc_rtc driver_lpc_rtc) +include_driver_ifdef(CONFIG_DMA_MCUX_LPC lpc_dma driver_lpc_dma) +include_driver_ifdef(CONFIG_GPIO_MCUX_LPC lpc_gpio driver_lpc_gpio) +include_driver_ifdef(CONFIG_GPIO_MCUX_LPC pint driver_pint) +include_driver_ifdef(CONFIG_GPIO_MCUX_LPC inputmux driver_inputmux) +include_driver_ifdef(CONFIG_I2C_MCUX_FLEXCOMM flexcomm driver_flexcomm_i2c) +include_driver_ifdef(CONFIG_I2C_MCUX_FLEXCOMM flexcomm driver_flexcomm) +include_driver_ifdef(CONFIG_I2S_MCUX_FLEXCOMM flexcomm driver_flexcomm_i2s) +include_driver_ifdef(CONFIG_I2S_MCUX_FLEXCOMM flexcomm driver_flexcomm) +include_driver_ifdef(CONFIG_MCUX_OS_TIMER ostimer driver_ostimer) +include_driver_ifdef(CONFIG_SOC_FLASH_LPC flashiap driver_flashiap) +include_driver_ifdef(CONFIG_SPI_MCUX_FLEXCOMM flexcomm driver_flexcomm_spi) +include_driver_ifdef(CONFIG_SPI_MCUX_FLEXCOMM flexcomm driver_flexcomm) +include_driver_ifdef(CONFIG_UART_MCUX_FLEXCOMM flexcomm driver_flexcomm_usart) +include_driver_ifdef(CONFIG_UART_MCUX_FLEXCOMM flexcomm driver_flexcomm) +include_driver_ifdef(CONFIG_WDT_MCUX_WWDT wwdt driver_wwdt) +include_driver_ifdef(CONFIG_ADC_MCUX_ADC12 adc12 driver_adc12) +include_driver_ifdef(CONFIG_ADC_MCUX_ADC16 adc16 driver_adc16) +include_driver_ifdef(CONFIG_CAN_MCUX_FLEXCAN flexcan driver_flexcan) +include_driver_ifdef(CONFIG_COUNTER_MCUX_PIT pit driver_pit) +include_driver_ifdef(CONFIG_COUNTER_MCUX_RTC rtc driver_rtc) +include_driver_ifdef(CONFIG_DAC_MCUX_DAC dac driver_dac) +include_driver_ifdef(CONFIG_DAC_MCUX_DAC32 dac32 driver_dac32) +include_driver_ifdef(CONFIG_DMA_MCUX_EDMA edma driver_edma) +include_driver_ifdef(CONFIG_DMA_MCUX_EDMA dmamux driver_dmamux) +include_driver_ifdef(CONFIG_ENTROPY_MCUX_RNGA rnga driver_rnga) +include_driver_ifdef(CONFIG_ENTROPY_MCUX_TRNG trng driver_trng) +include_driver_ifdef(CONFIG_ETH_MCUX enet driver_enet) +include_driver_ifdef(CONFIG_HAS_MCUX_SMC smc driver_smc) +include_driver_ifdef(CONFIG_I2C_MCUX i2c driver_i2c) +include_driver_ifdef(CONFIG_I2C_MCUX_LPI2C lpi2c driver_lpi2c) +include_driver_ifdef(CONFIG_MCUX_ACMP acmp driver_acmp) +include_driver_ifdef(CONFIG_PWM_MCUX_FTM ftm driver_ftm) +include_driver_ifdef(CONFIG_PWM_MCUX_TPM tpm driver_tpm) +include_driver_ifdef(CONFIG_PWM_MCUX_PWT pwt driver_pwt) +include_driver_ifdef(CONFIG_RTC_MCUX rtc driver_rtc) +include_driver_ifdef(CONFIG_SOC_FLASH_MCUX flash driver_flash) +include_driver_ifdef(CONFIG_SPI_MCUX_DSPI dspi driver_dspi) +include_driver_ifdef(CONFIG_SPI_MCUX_LPSPI lpspi driver_lpspi) +include_driver_ifdef(CONFIG_UART_MCUX uart driver_uart) +include_driver_ifdef(CONFIG_UART_MCUX_LPSCI lpsci driver_lpsci) +include_driver_ifdef(CONFIG_UART_MCUX_LPUART lpuart driver_lpuart) +include_driver_ifdef(CONFIG_WDT_MCUX_WDOG wdog driver_wdog) +include_driver_ifdef(CONFIG_WDT_MCUX_WDOG32 wdog32 driver_wdog32) +include_driver_ifdef(CONFIG_COUNTER_MCUX_GPT gpt driver_gpt) +include_driver_ifdef(CONFIG_COUNTER_MCUX_PIT pit driver_pit) +include_driver_ifdef(CONFIG_DISPLAY_MCUX_ELCDIF elcdif driver_elcdif) +include_driver_ifdef(CONFIG_ETH_MCUX enet driver_enet) +include_driver_ifdef(CONFIG_GPIO_MCUX_IGPIO igpio driver_igpio) +include_driver_ifdef(CONFIG_I2C_MCUX_LPI2C lpi2c driver_lpi2c) +include_driver_ifdef(CONFIG_I2S_MCUX_SAI sai driver_sai) +include_driver_ifdef(CONFIG_I2S_MCUX_SAI sai_edma driver_sai_edma) +include_driver_ifdef(CONFIG_MEMC_MCUX_FLEXSPI flexspi driver_flexspi) +include_driver_ifdef(CONFIG_PWM_MCUX pwm driver_pwm) +include_driver_ifdef(CONFIG_SPI_MCUX_LPSPI lpspi driver_lpspi) +include_driver_ifdef(CONFIG_UART_MCUX_LPUART lpuart driver_lpuart) +include_driver_ifdef(CONFIG_VIDEO_MCUX_CSI csi driver_csi) +include_driver_ifdef(CONFIG_WDT_MCUX_IMX_WDOG wdog driver_wdog) +include_driver_ifdef(CONFIG_DMA_MCUX_LPC lpc_dma driver_lpc_dma) +include_driver_ifdef(CONFIG_MEMC_MCUX_FLEXSPI flexspi driver_flexspi) +include_driver_ifdef(CONFIG_PWM_MCUX_SCTIMER sctimer driver_sctimer) +include_driver_ifdef(CONFIG_HAS_MCUX_RDC rdc driver_rdc) +include_driver_ifdef(CONFIG_UART_MCUX_IUART iuart driver_iuart) + +#include device specific drivers +if (${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") +zephyr_include_directories(devices/${MCUX_DEVICE}/xip) +endif() + +if ((${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") AND (NOT CONFIG_SOC_MIMXRT1176_CM4)) +include_driver_ifdef(CONFIG_HAS_MCUX_CACHE cache/armv7-m7 driver_cache_armv7_m7) +elseif(${MCUX_DEVICE} MATCHES "MIMXRT(5|6)") +include_driver_ifdef(CONFIG_HAS_MCUX_CACHE cache/cache64 driver_cache_cache64) +elseif((${MCUX_DEVICE} MATCHES "MK(28|66)") OR (CONFIG_SOC_MIMXRT1176_CM4)) +include_driver_ifdef(CONFIG_HAS_MCUX_CACHE cache/lmem driver_cache_lmem) +endif() + +if(${MCUX_DEVICE} MATCHES "K[0-9EVLMW]") +include(${CMAKE_CURRENT_LIST_DIR}/../drivers/port/driver_port.cmake) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/port) +include(${CMAKE_CURRENT_LIST_DIR}/../drivers/sim/driver_sim.cmake) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/sim) +include(${CMAKE_CURRENT_LIST_DIR}/../drivers/rcm/driver_rcm.cmake) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/rcm) +endif() + +if ((${MCUX_DEVICE} MATCHES "LPC8[0-9][0-9]") OR (${MCUX_DEVICE} MATCHES "LPC5(1|4)")) +include_driver_ifdef(CONFIG_SOC_FLASH_MCUX iap driver_iap) +include_driver_ifdef(CONFIG_ENTROPY_MCUX_RNG iap driver_rng) +elseif (${MCUX_DEVICE} MATCHES "LPC55") +include_driver_ifdef(CONFIG_SOC_FLASH_MCUX iap1 driver_iap1) +include_driver_ifdef(CONFIG_ENTROPY_MCUX_RNG rng_1 driver_rng_1) +endif() + +if (${MCUX_DEVICE} MATCHES "LPC5") +include(${CMAKE_CURRENT_LIST_DIR}/../drivers/lpc_iocon/driver_lpc_iocon.cmake) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/lpc_iocon) +elseif (${MCUX_DEVICE} MATCHES "LPC8") +include(${CMAKE_CURRENT_LIST_DIR}/../drivers/lpc_iocon_lite/driver_lpc_iocon_lite.cmake) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/lpc_iocon_lite) +endif() + +if(${MCUX_DEVICE} MATCHES "MIMXRT(5|6)") +include(${CMAKE_CURRENT_LIST_DIR}/../drivers/lpc_iopctl/driver_lpc_iopctl.cmake) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/lpc_iopctl) +endif() + +if(${MCUX_DEVICE} MATCHES "MK(80|82|64|66|M34|M35)") +include(${CMAKE_CURRENT_LIST_DIR}/../drivers/sysmpu/driver_sysmpu.cmake) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../drivers/sysmpu) +endif() + +#include macro definition +zephyr_compile_definitions_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER XIP_BOOT_HEADER_ENABLE=1) +zephyr_compile_definitions_ifdef(CONFIG_NXP_IMX_RT6XX_BOOT_HEADER BOOT_HEADER_ENABLE=1) +zephyr_compile_definitions_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA XIP_BOOT_HEADER_DCD_ENABLE=1) +zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + +#include board specific configuration files +if(CONFIG_BOARD_MIMXRT1010_EVK) + set(MCUX_BOARD evkmimxrt1010) +elseif(CONFIG_BOARD_MIMXRT1015_EVK) + set(MCUX_BOARD evkmimxrt1015) +elseif(CONFIG_BOARD_MIMXRT1020_EVK) + set(MCUX_BOARD evkmimxrt1020) +elseif(CONFIG_BOARD_MIMXRT1024_EVK) + set(MCUX_BOARD evkmimxrt1024) +elseif(CONFIG_BOARD_MIMXRT1050_EVK OR CONFIG_BOARD_MIMXRT1050_EVK_QSPI) + set(MCUX_BOARD evkbimxrt1050) +elseif(CONFIG_BOARD_MIMXRT1060_EVK OR CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH) + set(MCUX_BOARD evkmimxrt1060) +elseif(CONFIG_BOARD_MIMXRT1064_EVK) + set(MCUX_BOARD evkmimxrt1064) +elseif(CONFIG_BOARD_MIMXRT685_EVK) + set(MCUX_BOARD evkmimxrt685) +elseif(CONFIG_BOARD_MIMXRT1170_EVK_CM7 OR CONFIG_BOARD_MIMXRT1170_EVK_CM4) + set(MCUX_BOARD evkmimxrt1170) +endif() + +if (${MCUX_BOARD} MATCHES "evk[bm]imxrt1[0-9][0-9][0-9]") +list(APPEND CMAKE_MODULE_PATH + ${CMAKE_CURRENT_LIST_DIR}/../boards/${MCUX_BOARD}/xip +) +include_ifdef(CONFIG_BOOT_FLEXSPI_NOR driver_xip_board_${MCUX_BOARD}) +zephyr_library_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA ${CMAKE_CURRENT_LIST_DIR}/../boards/${MCUX_BOARD}/dcd.c) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../boards/${MCUX_BOARD}) +elseif (${MCUX_BOARD} MATCHES "evkmimxrt6[0-9][0-9]") +list(APPEND CMAKE_MODULE_PATH + ${CMAKE_CURRENT_LIST_DIR}/../boards/${MCUX_BOARD}/flash_config +) +include_ifdef(CONFIG_NXP_IMX_RT6XX_BOOT_HEADER driver_flash_config) +zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/../boards/${MCUX_BOARD}) +endif() + +# add imx drivers which are not included in mcux-sdk delivery +add_subdirectory_ifdef( + CONFIG_HAS_IMX_HAL + ${CMAKE_CURRENT_LIST_DIR}/imx + ) + +# add component drivers which are not included in mcux-sdk delivery +if(CONFIG_IEEE802154_MCR20A) + zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/components/mcr20a) +endif() + +if(CONFIG_ETH_MCUX) + zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/components/phyksz8081) +endif() + +zephyr_library_sources_ifdef(CONFIG_ETH_MCUX ${CMAKE_CURRENT_LIST_DIR}/phyksz8081/fsl_phy.c) + +# add middleware which are not included in mcux-sdk delivery +add_subdirectory_ifdef( + CONFIG_USB_DEVICE_DRIVER + ${CMAKE_CURRENT_LIST_DIR}/middleware/usb + ) + +add_subdirectory_ifdef( + CONFIG_IEEE802154_KW41Z + ${CMAKE_CURRENT_LIST_DIR}/middleware/wireless/framework_5.3.3 + ) diff --git a/zephyr/imx/CMakeLists.txt b/zephyr/imx/CMakeLists.txt new file mode 100644 index 000000000..35e66de4c --- /dev/null +++ b/zephyr/imx/CMakeLists.txt @@ -0,0 +1,8 @@ +# Translate the SoC name and part number into the imx device and cpu +# name respectively. +string(TOUPPER ${CONFIG_SOC} IMX_DEVICE) + +# Build imx drivers and utilities that can be used for multiple SoC's. +add_subdirectory(drivers) +add_subdirectory(devices) +add_subdirectory(devices/${IMX_DEVICE}) diff --git a/zephyr/imx/README b/zephyr/imx/README new file mode 100644 index 000000000..ccb778f5c --- /dev/null +++ b/zephyr/imx/README @@ -0,0 +1,52 @@ +iMX7D and MX6SX Port +##################### + +Origin: + i.MX 7Dual/Solo FreeRTOS BSP for Cortex-M4 Peripheral Driver + https://www.nxp.com/webapp/Download?colCode=FreeRTOS_iMX7D_1.0.1_LINUX&appType=license + i.MX 6SoloX FreeRTOS BSP 1.0.1 for Cortex-M4 Peripheral Driver + https://www.nxp.com/webapp/Download?colCode=FreeRTOS_MX6SX_1.0.1_LINUX&appType=license + + +Status: + FreeRTOS_iMX7D_1.0.1 + FreeRTOS_MX6SX_1.0.1 + +Purpose: + The peripheral driver wrap the H/W + +Description: + This code component is used to add Zephyr support on iMX7 and iMX6SX + processors, exclusively on Cortex M4 core, and to speed up the development + process it was decided to have it based on NXP FreeRTOS BSP implementation. + + The i.MX FreeRTOS BSP is split into separate downloadable packages, + based on SoC. The packages share most of the peripheral driver files + and here they are combined together. + + The source code was imported from the following folders: + FreeRTOS_BSP_1.0.1_iMX7D/platform/drivers + FreeRTOS_BSP_1.0.1_iMX6SX/platform/drivers + FreeRTOS_BSP_1.0.1_iMX7D/platform/devices + FreeRTOS_BSP_1.0.1_iMX6SX/platform/devices + +Dependencies: + This source code depends on headers and sources from zephyr: + ext/hal/cmsis + +URL: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors/i.mx-7dual-processors-heterogeneous-processing-with-dual-arm-cortex-a7-cores-and-cortex-m4-core:i.MX7D?tab=Design_Tools_Tab + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX?tab=Design_Tools_Tab + +commit: + No commit hash + +Maintained-by: + External + +License: + BSD-3-Clause + +License Link: + https://www.nxp.com/webapp/sps/download/license.jsp?colCode=FreeRTOS_iMX7D_1.0.1_LINUX&appType=file1&DOWNLOAD_ID=null + https://www.nxp.com/webapp/sps/download/license.jsp?colCode=FreeRTOS_MX6SX_1.0.1_LINUX&appType=file1&DOWNLOAD_ID=null diff --git a/zephyr/imx/devices/CMakeLists.txt b/zephyr/imx/devices/CMakeLists.txt new file mode 100644 index 000000000..4e449f8cc --- /dev/null +++ b/zephyr/imx/devices/CMakeLists.txt @@ -0,0 +1 @@ +zephyr_include_directories(.) diff --git a/zephyr/imx/devices/MCIMX6X/CMakeLists.txt b/zephyr/imx/devices/MCIMX6X/CMakeLists.txt new file mode 100644 index 000000000..a2e8d1caa --- /dev/null +++ b/zephyr/imx/devices/MCIMX6X/CMakeLists.txt @@ -0,0 +1,2 @@ +zephyr_include_directories(.) +zephyr_library_sources(clock_freq.c) diff --git a/zephyr/imx/devices/MCIMX6X/MCIMX6X_M4.h b/zephyr/imx/devices/MCIMX6X/MCIMX6X_M4.h new file mode 100644 index 000000000..09d5b8b92 --- /dev/null +++ b/zephyr/imx/devices/MCIMX6X/MCIMX6X_M4.h @@ -0,0 +1,41139 @@ +/* +** ################################################################### +** Processors: MCIMX6X_M4 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** GNU C Compiler - CodeSourcery Sourcery G++ +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: +** Version: rev. 1.0, 2015-07-17 +** Build: b150707 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCIMX6X_M4 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2015-07-17) +** Initial version . +** +** ################################################################### +*/ + +/*! + * @file MCIMX6X_M4.h + * @version 1.0 + * @date 2015-07-17 + * @brief CMSIS Peripheral Access Layer for MCIMX6X_M4 + * + * CMSIS Peripheral Access Layer for MCIMX6X_M4 + */ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(MCIMX6X_M4_H_) /* Check if memory map has not been already included */ +#define MCIMX6X_M4_H_ +#define MCU_MCIMX6X_M4 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error MCIMX6X_M4 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000u + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + Cortex_M4_IRQn = 0, /**< Cache Controller interrupt */ + DAP_IRQn = 1, /**< Debug Access Port interrupt request. */ + SDMA_IRQn = 2, /**< SDMA interrupt request from all channels. */ + Reserved0_IRQn = 3, /**< Reserved */ + SNVS_IRQn = 4, /**< PMIC power off request. */ + LCDIF1_IRQn = 5, /**< LCDIF1 Sync Interrupt */ + LCDIF2_IRQn = 6, /**< LCDIF2 Sync Interrupt */ + CSI1_IRQn = 7, /**< CMOS Sensor Interface interrupt request */ + PXP_IRQn = 8, /**< PXP interrupt */ + Reserved1_IRQn = 9, /**< Reserved */ + GPU_IRQn = 10, /**< GPU general interrupt request */ + WDOG3_IRQn = 11, /**< WDOG3 interrupt request */ + SEMA4_CP1_IRQn = 12, /**< SEMA4 CP1 interrupt request. */ + APBHDMA_IRQn = 13, /**< Logical OR of APBH DMA channels 0-3 completion and error interrupts. */ + EIM_IRQn = 14, /**< EIM interrupt request. */ + BCH_IRQn = 15, /**< BCH operation complete interrupt. */ + GPMI_IRQn = 16, /**< GPMI operation timeout error interrupt. */ + UART6_IRQn = 17, /**< UART6 interrupt request. */ + eCSPI5_IRQn = 18, /**< eCSPI5 interrupt request. */ + SNVS_CONSOLIDATED_IRQn = 19, /**< SNVS consolidated interrupt. */ + SNVS_SECURITY_IRQn = 20, /**< SNVS security interrupt. */ + CSU_IRQn = 21, /**< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */ + USDHC1_IRQn = 22, /**< uSDHC1 (Enhanced SDHC) interrupt request */ + USDHC2_IRQn = 23, /**< uSDHC2 (Enhanced SDHC) interrupt request. */ + USDHC3_IRQn = 24, /**< uSDHC3 (Enhanced SDHC) interrupt request. */ + USDHC4_IRQn = 25, /**< uSDHC4 (Enhanced SDHC) interrupt request. */ + UART1_IRQn = 26, /**< UART1 interrupt request. */ + UART2_IRQn = 27, /**< UART2 interrupt request. */ + UART3_IRQn = 28, /**< UART3 interrupt request. */ + UART4_IRQn = 29, /**< UART4 interrupt request. */ + UART5_IRQn = 30, /**< UART5 interrupt request. */ + eCSPI1_IRQn = 31, /**< eCSPI1 interrupt request. */ + eCSPI2_IRQn = 32, /**< eCSPI2 interrupt request. */ + eCSPI3_IRQn = 33, /**< eCSPI3 interrupt request. */ + eCSPI4_IRQn = 34, /**< eCSPI4 interrupt request. */ + I2C4_IRQn = 35, /**< I2C4 interrupt request */ + I2C1_IRQn = 36, /**< I2C1 interrupt request. */ + I2C2_IRQn = 37, /**< I2C2 interrupt request. */ + I2C3_IRQn = 38, /**< I2C3 interrupt request. */ + RDC_IRQn = 39, /**< RDC interrupt request. */ + USB_IRQn = 40, /**< USB HISC Host interrupt request. */ + CSI2_IRQn = 41, /**< CSI interrupt */ + USB_OTG2_IRQn = 42, /**< USB OTG 2 interrupt request. */ + USB_OTG1_IRQn = 43, /**< USB OTG 1 interrupt request. */ + USB_PHY1_IRQn = 44, /**< UTMI0 interrupt request. */ + USB_PHY2_IRQn = 45, /**< UTMI1 interrupt request. */ + SSI1_IRQn = 46, /**< SSI1 interrupt request. */ + SSI2_IRQn = 47, /**< SSI2 interrupt request. */ + SSI3_IRQn = 48, /**< SSI3 interrupt request. */ + Temperature_Monitor_IRQn = 49, /**< Temperature Sensor (temp. greater than threshold) interrupt request. */ + ASRC_IRQn = 50, /**< ASRC interrupt request. */ + ESAI_IRQn = 51, /**< ESAI interrupt request */ + SPDIF_IRQn = 52, /**< SPDIF Rx/Tx interrupt. */ + MLB_ERROR_IRQn = 53, /**< MLB error interrupt request. */ + PMU1_IRQn = 54, /**< Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */ + GPT_IRQn = 55, /**< Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines. */ + EPIT1_IRQn = 56, /**< EPIT1 output compare interrupt. */ + EPIT2_IRQn = 57, /**< EPIT2 output compare interrupt. */ + GPIO1_INT7_IRQn = 58, /**< INT7 interrupt request. */ + GPIO1_INT6_IRQn = 59, /**< INT6 interrupt request. */ + GPIO1_INT5_IRQn = 60, /**< INT5 interrupt request. */ + GPIO1_INT4_IRQn = 61, /**< INT4 interrupt request. */ + GPIO1_INT3_IRQn = 62, /**< INT3 interrupt request. */ + GPIO1_INT2_IRQn = 63, /**< INT2 interrupt request. */ + GPIO1_INT1_IRQn = 64, /**< INT1 interrupt request. */ + GPIO1_INT0_IRQn = 65, /**< INT0 interrupt request. */ + GPIO1_INT15_0_IRQn = 66, /**< Combined interrupt indication for GPIO1 signals 0 - 15. */ + GPIO1_INT31_16_IRQn = 67, /**< Combined interrupt indication for GPIO1 signals 16 - 31. */ + GPIO2_INT15_0_IRQn = 68, /**< Combined interrupt indication for GPIO2 signals 0 - 15. */ + GPIO2_INT31_16_IRQn = 69, /**< Combined interrupt indication for GPIO2 signals 16 - 31. */ + GPIO3_INT15_0_IRQn = 70, /**< Combined interrupt indication for GPIO3 signals 0 - 15. */ + GPIO3_INT31_16_IRQn = 71, /**< Combined interrupt indication for GPIO3 signals 16 - 31. */ + GPIO4_INT15_0_IRQn = 72, /**< Combined interrupt indication for GPIO4 signals 0 - 15. */ + GPIO4_INT31_16_IRQn = 73, /**< Combined interrupt indication for GPIO4 signals 16 - 31. */ + GPIO5_INT15_0_IRQn = 74, /**< Combined interrupt indication for GPIO5 signals 0 - 15. */ + GPIO5_INT31_16_IRQn = 75, /**< Combined interrupt indication for GPIO5 signals 16 - 31. */ + GPIO6_INT15_0_IRQn = 76, /**< Combined interrupt indication for GPIO6 signals 0 - 15. */ + GPIO6_INT31_16_IRQn = 77, /**< Combined interrupt indication for GPIO6 signals 16 - 31. */ + GPIO7_INT15_0_IRQn = 78, /**< Combined interrupt indication for GPIO7 signals 0 - 15. */ + GPIO7_INT31_16_IRQn = 79, /**< Combined interrupt indication for GPIO7 signals 16 - 31. */ + WDOG1_IRQn = 80, /**< WDOG1 timer reset interrupt request. */ + WDOG2_IRQn = 81, /**< WDOG2 timer reset interrupt request. */ + KPP_IRQn = 82, /**< Key Pad interrupt request */ + PWM1_PWM5_IRQn = 83, /**< Cumulative interrupt line for PWM1/PWM5. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ + PWM2_PWM6_IRQn = 84, /**< Cumulative interrupt line for PWM2/PWM6. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ + PWM3_PWM7_IRQn = 85, /**< Cumulative interrupt line for PWM3/PWM7. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ + PWM4_PWM8_IRQn = 86, /**< Cumulative interrupt line for PWM4/PWM8. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ + CCM1_IRQn = 87, /**< CCM interrupt request 1. */ + CCM2_IRQn = 88, /**< CCM interrupt request 2. */ + GPC_IRQn = 89, /**< GPC interrupt request 1. */ + MU_A9_IRQn = 90, /**< Message unit interrupt to A9 core */ + SRC_IRQn = 91, /**< SRC interrupt request. */ + CPU_L2I_IRQn = 92, /**< L2 interrupt request. */ + CPU_PCEI_IRQn = 93, /**< Parity Check error interrupt request. */ + CPU_PUI_IRQn = 94, /**< Performance Unit interrupt. */ + CPU_CTI_IRQn = 95, /**< CTI trigger outputs interrupt. */ + SRC_CPU_WDOG_IRQn = 96, /**< Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 97, /**< SAI1 interrupt request. */ + SAI2_IRQn = 98, /**< SAI2 interrupt request. */ + MU_M4_IRQn = 99, /**< Message unit Interrupt to M4 core */ + ADC1_IRQn = 100, /**< ADC1 interrupt request. */ + ADC2_IRQn = 101, /**< ADC2 interrupt request. */ + ENET2_IRQn = 102, /**< ENET2 Interrupt Request. */ + ENET2_TI_IRQn = 103, /**< ENET2 1588 Timer interrupt [synchronous] request. */ + SJC_IRQn = 104, /**< SJC interrupt from General Purpose register. */ + CAAM1_IRQn = 105, /**< CAAM job ring 0 interrupt. */ + CAAM2_IRQn = 106, /**< CAAM job ring 1 interrupt. */ + QSPI1_IRQn = 107, /**< QSPI1 interrupt request. */ + TZASC_IRQn = 108, /**< TZASC (PL380) interrupt request. */ + QSPI2_IRQn = 109, /**< QSPI2 interrupt request. */ + FLEXCAN1_IRQn = 110, /**< FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */ + FLEXCAN2_IRQn = 111, /**< FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */ + Reserved2_IRQn = 112, /**< Reserved */ + Reserved3_IRQn = 113, /**< Reserved */ + Reserved4_IRQn = 114, /**< Reserved */ + Reserved5_IRQn = 115, /**< Reserved */ + SEMA4_CP0_IRQn = 116, /**< SEMA4 CP0 interrupt request */ + MLB_IRCI_IRQn = 117, /**< Interrupt request for channels [31:0]. Interrupt request for channels [63:32] available on IRQ #149 if SMX bit is set in MLB150 AHB control register (ACTL), otherwise interrupt for channels [63:32] interrupt is available on IRQ #158. */ + ENET1_IRQn = 118, /**< ENET1 Interrupt Request. */ + ENET1_TI_IRQn = 119, /**< ENET1 1588 Timer interrupt [synchronous] request. */ + PCIe1_IRQn = 120, /**< PCIe interrupt request 1. */ + PCIe2_IRQn = 121, /**< PCIe interrupt request 2. */ + PCIe3_IRQn = 122, /**< PCIe interrupt request 3. */ + PCIe4_IRQn = 123, /**< PCIe interrupt request 4. */ + DCIC1_IRQn = 124, /**< DCIC1 interrupt request. */ + DCIC2_IRQn = 125, /**< DCIC2 interrupt request. */ + MLB_LOCI_IRQn = 126, /**< Logical OR of channel[63:32] interrupt requests. */ + PMU2_IRQn = 127, /**< Brown out of core, gpu, and chip digital regulators occurred. */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC0; /**< Control register for hardware triggers, offset: 0x0 */ + __IO uint32_t HC1; /**< Control register for hardware triggers, offset: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x8 */ + __IO uint32_t R0; /**< Data result register for HW triggers, offset: 0xC */ + __IO uint32_t R1; /**< Data result register for HW triggers, offset: 0x10 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x14 */ + __IO uint32_t GC; /**< General control register, offset: 0x18 */ + __IO uint32_t GS; /**< General status register, offset: 0x1C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x20 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x24 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x28 */ +} ADC_Type, *ADC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + +/* ADC - Register accessors */ +#define ADC_HC0_REG(base) ((base)->HC0) +#define ADC_HC1_REG(base) ((base)->HC1) +#define ADC_HS_REG(base) ((base)->HS) +#define ADC_R0_REG(base) ((base)->R0) +#define ADC_R1_REG(base) ((base)->R1) +#define ADC_CFG_REG(base) ((base)->CFG) +#define ADC_GC_REG(base) ((base)->GC) +#define ADC_GS_REG(base) ((base)->GS) +#define ADC_CV_REG(base) ((base)->CV) +#define ADC_OFS_REG(base) ((base)->OFS) +#define ADC_CAL_REG(base) ((base)->CAL) + +/*! + * @} + */ /* end of group ADC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* HC0 Bit Fields */ +#define ADC_HC0_ADCH_MASK 0x1Fu +#define ADC_HC0_ADCH_SHIFT 0 +#define ADC_HC0_ADCH(x) (((uint32_t)(((uint32_t)(x))<BLOCK_ID) +#define AFE_PDBUF_REG(base) ((base)->PDBUF) +#define AFE_SWRST_REG(base) ((base)->SWRST) +#define AFE_BGREG_REG(base) ((base)->BGREG) +#define AFE_ACCESSAR_ID_REG(base) ((base)->ACCESSAR_ID) +#define AFE_PDADC_REG(base) ((base)->PDADC) +#define AFE_PDSARH_REG(base) ((base)->PDSARH) +#define AFE_PDSARL_REG(base) ((base)->PDSARL) +#define AFE_PDADCRFH_REG(base) ((base)->PDADCRFH) +#define AFE_PDADCRFL_REG(base) ((base)->PDADCRFL) +#define AFE_ADCGN_REG(base) ((base)->ADCGN) +#define AFE_REFTRIML_REG(base) ((base)->REFTRIML) +#define AFE_REFTRIMH_REG(base) ((base)->REFTRIMH) +#define AFE_DACAMP_REG(base) ((base)->DACAMP) +#define AFE_CLMPDAT_REG(base) ((base)->CLMPDAT) +#define AFE_CLMPAMP_REG(base) ((base)->CLMPAMP) +#define AFE_CLAMP_REG(base) ((base)->CLAMP) +#define AFE_INPBUF_REG(base) ((base)->INPBUF) +#define AFE_INPFLT_REG(base) ((base)->INPFLT) +#define AFE_ADCDGN_REG(base) ((base)->ADCDGN) +#define AFE_OFFDRV_REG(base) ((base)->OFFDRV) +#define AFE_INPCONFIG_REG(base) ((base)->INPCONFIG) +#define AFE_PROGDELAY_REG(base) ((base)->PROGDELAY) +#define AFE_ADCOMT_REG(base) ((base)->ADCOMT) +#define AFE_ALGDELAY_REG(base) ((base)->ALGDELAY) +#define AFE_ACC_ID_REG(base) ((base)->ACC_ID) +#define AFE_ACCSTA_REG(base) ((base)->ACCSTA) +#define AFE_ACCNOSLI_REG(base) ((base)->ACCNOSLI) +#define AFE_ACCCALCON_REG(base) ((base)->ACCCALCON) +#define AFE_BWEWRICTRL_REG(base) ((base)->BWEWRICTRL) +#define AFE_SELSLI_REG(base) ((base)->SELSLI) +#define AFE_SELBYT_REG(base) ((base)->SELBYT) +#define AFE_REDVAL_REG(base) ((base)->REDVAL) +#define AFE_WRIBYT_REG(base) ((base)->WRIBYT) + +/*! + * @} + */ /* end of group AFE_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- AFE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AFE_Register_Masks AFE Register Masks + * @{ + */ + +/* BLOCK_ID Bit Fields */ +#define AFE_BLOCK_ID_BLOCK_ID_MASK 0xFFu +#define AFE_BLOCK_ID_BLOCK_ID_SHIFT 0 +#define AFE_BLOCK_ID_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x))<ASRCTR) +#define ASRC_ASRIER_REG(base) ((base)->ASRIER) +#define ASRC_ASRCNCR_REG(base) ((base)->ASRCNCR) +#define ASRC_ASRCFG_REG(base) ((base)->ASRCFG) +#define ASRC_ASRCSR_REG(base) ((base)->ASRCSR) +#define ASRC_ASRCDR1_REG(base) ((base)->ASRCDR1) +#define ASRC_ASRCDR2_REG(base) ((base)->ASRCDR2) +#define ASRC_ASRSTR_REG(base) ((base)->ASRSTR) +#define ASRC_ASRPMn_REG(base,index) ((base)->ASRPMn[index]) +#define ASRC_ASRTFR1_REG(base) ((base)->ASRTFR1) +#define ASRC_ASRCCR_REG(base) ((base)->ASRCCR) +#define ASRC_ASRDI_REG(base,index) ((base)->ASRD[index].ASRDI) +#define ASRC_ASRDO_REG(base,index) ((base)->ASRD[index].ASRDO) +#define ASRC_ASRIDRHA_REG(base) ((base)->ASRIDRHA) +#define ASRC_ASRIDRLA_REG(base) ((base)->ASRIDRLA) +#define ASRC_ASRIDRHB_REG(base) ((base)->ASRIDRHB) +#define ASRC_ASRIDRLB_REG(base) ((base)->ASRIDRLB) +#define ASRC_ASRIDRHC_REG(base) ((base)->ASRIDRHC) +#define ASRC_ASRIDRLC_REG(base) ((base)->ASRIDRLC) +#define ASRC_ASR76K_REG(base) ((base)->ASR76K) +#define ASRC_ASR56K_REG(base) ((base)->ASR56K) +#define ASRC_ASRMCRA_REG(base) ((base)->ASRMCRA) +#define ASRC_ASRFSTA_REG(base) ((base)->ASRFSTA) +#define ASRC_ASRMCRB_REG(base) ((base)->ASRMCRB) +#define ASRC_ASRFSTB_REG(base) ((base)->ASRFSTB) +#define ASRC_ASRMCRC_REG(base) ((base)->ASRMCRC) +#define ASRC_ASRFSTC_REG(base) ((base)->ASRFSTC) +#define ASRC_ASRMCR1_REG(base,index) ((base)->ASRMCR1[index]) + +/*! + * @} + */ /* end of group ASRC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ASRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Register_Masks ASRC Register Masks + * @{ + */ + +/* ASRCTR Bit Fields */ +#define ASRC_ASRCTR_ASRCEN_MASK 0x1u +#define ASRC_ASRCTR_ASRCEN_SHIFT 0 +#define ASRC_ASRCTR_ASREA_MASK 0x2u +#define ASRC_ASRCTR_ASREA_SHIFT 1 +#define ASRC_ASRCTR_ASREB_MASK 0x4u +#define ASRC_ASRCTR_ASREB_SHIFT 2 +#define ASRC_ASRCTR_ASREC_MASK 0x8u +#define ASRC_ASRCTR_ASREC_SHIFT 3 +#define ASRC_ASRCTR_SRST_MASK 0x10u +#define ASRC_ASRCTR_SRST_SHIFT 4 +#define ASRC_ASRCTR_IDRA_MASK 0x2000u +#define ASRC_ASRCTR_IDRA_SHIFT 13 +#define ASRC_ASRCTR_USRA_MASK 0x4000u +#define ASRC_ASRCTR_USRA_SHIFT 14 +#define ASRC_ASRCTR_IDRB_MASK 0x8000u +#define ASRC_ASRCTR_IDRB_SHIFT 15 +#define ASRC_ASRCTR_USRB_MASK 0x10000u +#define ASRC_ASRCTR_USRB_SHIFT 16 +#define ASRC_ASRCTR_IDRC_MASK 0x20000u +#define ASRC_ASRCTR_IDRC_SHIFT 17 +#define ASRC_ASRCTR_USRC_MASK 0x40000u +#define ASRC_ASRCTR_USRC_SHIFT 18 +#define ASRC_ASRCTR_ATSA_MASK 0x100000u +#define ASRC_ASRCTR_ATSA_SHIFT 20 +#define ASRC_ASRCTR_ATSB_MASK 0x200000u +#define ASRC_ASRCTR_ATSB_SHIFT 21 +#define ASRC_ASRCTR_ATSC_MASK 0x400000u +#define ASRC_ASRCTR_ATSC_SHIFT 22 +/* ASRIER Bit Fields */ +#define ASRC_ASRIER_ADIEA_MASK 0x1u +#define ASRC_ASRIER_ADIEA_SHIFT 0 +#define ASRC_ASRIER_ADIEB_MASK 0x2u +#define ASRC_ASRIER_ADIEB_SHIFT 1 +#define ASRC_ASRIER_ADIEC_MASK 0x4u +#define ASRC_ASRIER_ADIEC_SHIFT 2 +#define ASRC_ASRIER_ADOEA_MASK 0x8u +#define ASRC_ASRIER_ADOEA_SHIFT 3 +#define ASRC_ASRIER_ADOEB_MASK 0x10u +#define ASRC_ASRIER_ADOEB_SHIFT 4 +#define ASRC_ASRIER_ADOEC_MASK 0x20u +#define ASRC_ASRIER_ADOEC_SHIFT 5 +#define ASRC_ASRIER_AOLIE_MASK 0x40u +#define ASRC_ASRIER_AOLIE_SHIFT 6 +#define ASRC_ASRIER_AFPWE_MASK 0x80u +#define ASRC_ASRIER_AFPWE_SHIFT 7 +/* ASRCNCR Bit Fields */ +#define ASRC_ASRCNCR_ANCA_MASK 0xFu +#define ASRC_ASRCNCR_ANCA_SHIFT 0 +#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x))<PTCR1) +#define AUDMUX_PDCR1_REG(base) ((base)->PDCR1) +#define AUDMUX_PTCR2_REG(base) ((base)->PTCR2) +#define AUDMUX_PDCR2_REG(base) ((base)->PDCR2) +#define AUDMUX_PTCR3_REG(base) ((base)->PTCR3) +#define AUDMUX_PDCR3_REG(base) ((base)->PDCR3) +#define AUDMUX_PTCR4_REG(base) ((base)->PTCR4) +#define AUDMUX_PDCR4_REG(base) ((base)->PDCR4) +#define AUDMUX_PTCR5_REG(base) ((base)->PTCR5) +#define AUDMUX_PDCR5_REG(base) ((base)->PDCR5) +#define AUDMUX_PTCR6_REG(base) ((base)->PTCR6) +#define AUDMUX_PDCR6_REG(base) ((base)->PDCR6) +#define AUDMUX_PTCR7_REG(base) ((base)->PTCR7) +#define AUDMUX_PDCR7_REG(base) ((base)->PDCR7) + +/*! + * @} + */ /* end of group AUDMUX_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- AUDMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AUDMUX_Register_Masks AUDMUX Register Masks + * @{ + */ + +/* PTCR1 Bit Fields */ +#define AUDMUX_PTCR1_SYN_MASK 0x800u +#define AUDMUX_PTCR1_SYN_SHIFT 11 +#define AUDMUX_PTCR1_RCSEL_MASK 0xF000u +#define AUDMUX_PTCR1_RCSEL_SHIFT 12 +#define AUDMUX_PTCR1_RCSEL(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define BCH_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define BCH_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define BCH_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define BCH_STATUS0_REG(base) ((base)->STATUS0) +#define BCH_STATUS0_SET_REG(base) ((base)->STATUS0_SET) +#define BCH_STATUS0_CLR_REG(base) ((base)->STATUS0_CLR) +#define BCH_STATUS0_TOG_REG(base) ((base)->STATUS0_TOG) +#define BCH_MODE_REG(base) ((base)->MODE) +#define BCH_MODE_SET_REG(base) ((base)->MODE_SET) +#define BCH_MODE_CLR_REG(base) ((base)->MODE_CLR) +#define BCH_MODE_TOG_REG(base) ((base)->MODE_TOG) +#define BCH_ENCODEPTR_REG(base) ((base)->ENCODEPTR) +#define BCH_ENCODEPTR_SET_REG(base) ((base)->ENCODEPTR_SET) +#define BCH_ENCODEPTR_CLR_REG(base) ((base)->ENCODEPTR_CLR) +#define BCH_ENCODEPTR_TOG_REG(base) ((base)->ENCODEPTR_TOG) +#define BCH_DATAPTR_REG(base) ((base)->DATAPTR) +#define BCH_DATAPTR_SET_REG(base) ((base)->DATAPTR_SET) +#define BCH_DATAPTR_CLR_REG(base) ((base)->DATAPTR_CLR) +#define BCH_DATAPTR_TOG_REG(base) ((base)->DATAPTR_TOG) +#define BCH_METAPTR_REG(base) ((base)->METAPTR) +#define BCH_METAPTR_SET_REG(base) ((base)->METAPTR_SET) +#define BCH_METAPTR_CLR_REG(base) ((base)->METAPTR_CLR) +#define BCH_METAPTR_TOG_REG(base) ((base)->METAPTR_TOG) +#define BCH_LAYOUTSELECT_REG(base) ((base)->LAYOUTSELECT) +#define BCH_LAYOUTSELECT_SET_REG(base) ((base)->LAYOUTSELECT_SET) +#define BCH_LAYOUTSELECT_CLR_REG(base) ((base)->LAYOUTSELECT_CLR) +#define BCH_LAYOUTSELECT_TOG_REG(base) ((base)->LAYOUTSELECT_TOG) +#define BCH_FLASH0LAYOUT0_REG(base) ((base)->FLASH0LAYOUT0) +#define BCH_FLASH0LAYOUT0_SET_REG(base) ((base)->FLASH0LAYOUT0_SET) +#define BCH_FLASH0LAYOUT0_CLR_REG(base) ((base)->FLASH0LAYOUT0_CLR) +#define BCH_FLASH0LAYOUT0_TOG_REG(base) ((base)->FLASH0LAYOUT0_TOG) +#define BCH_FLASH0LAYOUT1_REG(base) ((base)->FLASH0LAYOUT1) +#define BCH_FLASH0LAYOUT1_SET_REG(base) ((base)->FLASH0LAYOUT1_SET) +#define BCH_FLASH0LAYOUT1_CLR_REG(base) ((base)->FLASH0LAYOUT1_CLR) +#define BCH_FLASH0LAYOUT1_TOG_REG(base) ((base)->FLASH0LAYOUT1_TOG) +#define BCH_FLASH1LAYOUT0_REG(base) ((base)->FLASH1LAYOUT0) +#define BCH_FLASH1LAYOUT0_SET_REG(base) ((base)->FLASH1LAYOUT0_SET) +#define BCH_FLASH1LAYOUT0_CLR_REG(base) ((base)->FLASH1LAYOUT0_CLR) +#define BCH_FLASH1LAYOUT0_TOG_REG(base) ((base)->FLASH1LAYOUT0_TOG) +#define BCH_FLASH1LAYOUT1_REG(base) ((base)->FLASH1LAYOUT1) +#define BCH_FLASH1LAYOUT1_SET_REG(base) ((base)->FLASH1LAYOUT1_SET) +#define BCH_FLASH1LAYOUT1_CLR_REG(base) ((base)->FLASH1LAYOUT1_CLR) +#define BCH_FLASH1LAYOUT1_TOG_REG(base) ((base)->FLASH1LAYOUT1_TOG) +#define BCH_FLASH2LAYOUT0_REG(base) ((base)->FLASH2LAYOUT0) +#define BCH_FLASH2LAYOUT0_SET_REG(base) ((base)->FLASH2LAYOUT0_SET) +#define BCH_FLASH2LAYOUT0_CLR_REG(base) ((base)->FLASH2LAYOUT0_CLR) +#define BCH_FLASH2LAYOUT0_TOG_REG(base) ((base)->FLASH2LAYOUT0_TOG) +#define BCH_FLASH2LAYOUT1_REG(base) ((base)->FLASH2LAYOUT1) +#define BCH_FLASH2LAYOUT1_SET_REG(base) ((base)->FLASH2LAYOUT1_SET) +#define BCH_FLASH2LAYOUT1_CLR_REG(base) ((base)->FLASH2LAYOUT1_CLR) +#define BCH_FLASH2LAYOUT1_TOG_REG(base) ((base)->FLASH2LAYOUT1_TOG) +#define BCH_FLASH3LAYOUT0_REG(base) ((base)->FLASH3LAYOUT0) +#define BCH_FLASH3LAYOUT0_SET_REG(base) ((base)->FLASH3LAYOUT0_SET) +#define BCH_FLASH3LAYOUT0_CLR_REG(base) ((base)->FLASH3LAYOUT0_CLR) +#define BCH_FLASH3LAYOUT0_TOG_REG(base) ((base)->FLASH3LAYOUT0_TOG) +#define BCH_FLASH3LAYOUT1_REG(base) ((base)->FLASH3LAYOUT1) +#define BCH_FLASH3LAYOUT1_SET_REG(base) ((base)->FLASH3LAYOUT1_SET) +#define BCH_FLASH3LAYOUT1_CLR_REG(base) ((base)->FLASH3LAYOUT1_CLR) +#define BCH_FLASH3LAYOUT1_TOG_REG(base) ((base)->FLASH3LAYOUT1_TOG) +#define BCH_DEBUG0_REG(base) ((base)->DEBUG0) +#define BCH_DEBUG0_SET_REG(base) ((base)->DEBUG0_SET) +#define BCH_DEBUG0_CLR_REG(base) ((base)->DEBUG0_CLR) +#define BCH_DEBUG0_TOG_REG(base) ((base)->DEBUG0_TOG) +#define BCH_DBGKESREAD_REG(base) ((base)->DBGKESREAD) +#define BCH_DBGKESREAD_SET_REG(base) ((base)->DBGKESREAD_SET) +#define BCH_DBGKESREAD_CLR_REG(base) ((base)->DBGKESREAD_CLR) +#define BCH_DBGKESREAD_TOG_REG(base) ((base)->DBGKESREAD_TOG) +#define BCH_DBGCSFEREAD_REG(base) ((base)->DBGCSFEREAD) +#define BCH_DBGCSFEREAD_SET_REG(base) ((base)->DBGCSFEREAD_SET) +#define BCH_DBGCSFEREAD_CLR_REG(base) ((base)->DBGCSFEREAD_CLR) +#define BCH_DBGCSFEREAD_TOG_REG(base) ((base)->DBGCSFEREAD_TOG) +#define BCH_DBGSYNDGENREAD_REG(base) ((base)->DBGSYNDGENREAD) +#define BCH_DBGSYNDGENREAD_SET_REG(base) ((base)->DBGSYNDGENREAD_SET) +#define BCH_DBGSYNDGENREAD_CLR_REG(base) ((base)->DBGSYNDGENREAD_CLR) +#define BCH_DBGSYNDGENREAD_TOG_REG(base) ((base)->DBGSYNDGENREAD_TOG) +#define BCH_DBGAHBMREAD_REG(base) ((base)->DBGAHBMREAD) +#define BCH_DBGAHBMREAD_SET_REG(base) ((base)->DBGAHBMREAD_SET) +#define BCH_DBGAHBMREAD_CLR_REG(base) ((base)->DBGAHBMREAD_CLR) +#define BCH_DBGAHBMREAD_TOG_REG(base) ((base)->DBGAHBMREAD_TOG) +#define BCH_BLOCKNAME_REG(base) ((base)->BLOCKNAME) +#define BCH_BLOCKNAME_SET_REG(base) ((base)->BLOCKNAME_SET) +#define BCH_BLOCKNAME_CLR_REG(base) ((base)->BLOCKNAME_CLR) +#define BCH_BLOCKNAME_TOG_REG(base) ((base)->BLOCKNAME_TOG) +#define BCH_VERSION_REG(base) ((base)->VERSION) +#define BCH_VERSION_SET_REG(base) ((base)->VERSION_SET) +#define BCH_VERSION_CLR_REG(base) ((base)->VERSION_CLR) +#define BCH_VERSION_TOG_REG(base) ((base)->VERSION_TOG) +#define BCH_DEBUG1_REG(base) ((base)->DEBUG1) +#define BCH_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) +#define BCH_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) +#define BCH_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) + +/*! + * @} + */ /* end of group BCH_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define BCH_CTRL_COMPLETE_IRQ_MASK 0x1u +#define BCH_CTRL_COMPLETE_IRQ_SHIFT 0 +#define BCH_CTRL_RSVD0_MASK 0x2u +#define BCH_CTRL_RSVD0_SHIFT 1 +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK 0x4u +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT 2 +#define BCH_CTRL_BM_ERROR_IRQ_MASK 0x8u +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT 3 +#define BCH_CTRL_RSVD1_MASK 0xF0u +#define BCH_CTRL_RSVD1_SHIFT 4 +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define CAN_CTRL1_REG(base) ((base)->CTRL1) +#define CAN_TIMER_REG(base) ((base)->TIMER) +#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) +#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) +#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) +#define CAN_ECR_REG(base) ((base)->ECR) +#define CAN_ESR1_REG(base) ((base)->ESR1) +#define CAN_IMASK2_REG(base) ((base)->IMASK2) +#define CAN_IMASK1_REG(base) ((base)->IMASK1) +#define CAN_IFLAG2_REG(base) ((base)->IFLAG2) +#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) +#define CAN_CTRL2_REG(base) ((base)->CTRL2) +#define CAN_ESR2_REG(base) ((base)->ESR2) +#define CAN_CRCR_REG(base) ((base)->CRCR) +#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) +#define CAN_RXFIR_REG(base) ((base)->RXFIR) +#define CAN_CS_REG(base,index) ((base)->MB[index].CS) +#define CAN_CS_COUNT 64 +#define CAN_ID_REG(base,index) ((base)->MB[index].ID) +#define CAN_ID_COUNT 64 +#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) +#define CAN_WORD0_COUNT 64 +#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) +#define CAN_WORD1_COUNT 64 +#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) +#define CAN_RXIMR_COUNT 64 +#define CAN_GFWR_REG(base) ((base)->GFWR) + +/*! + * @} + */ /* end of group CAN_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define CAN_MCR_MAXMB_MASK 0x7Fu +#define CAN_MCR_MAXMB_SHIFT 0 +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<CCR) +#define CCM_CCDR_REG(base) ((base)->CCDR) +#define CCM_CSR_REG(base) ((base)->CSR) +#define CCM_CCSR_REG(base) ((base)->CCSR) +#define CCM_CACRR_REG(base) ((base)->CACRR) +#define CCM_CBCDR_REG(base) ((base)->CBCDR) +#define CCM_CBCMR_REG(base) ((base)->CBCMR) +#define CCM_CSCMR1_REG(base) ((base)->CSCMR1) +#define CCM_CSCMR2_REG(base) ((base)->CSCMR2) +#define CCM_CSCDR1_REG(base) ((base)->CSCDR1) +#define CCM_CS1CDR_REG(base) ((base)->CS1CDR) +#define CCM_CS2CDR_REG(base) ((base)->CS2CDR) +#define CCM_CDCDR_REG(base) ((base)->CDCDR) +#define CCM_CHSCCDR_REG(base) ((base)->CHSCCDR) +#define CCM_CSCDR2_REG(base) ((base)->CSCDR2) +#define CCM_CSCDR3_REG(base) ((base)->CSCDR3) +#define CCM_CWDR_REG(base) ((base)->CWDR) +#define CCM_CDHIPR_REG(base) ((base)->CDHIPR) +#define CCM_CLPCR_REG(base) ((base)->CLPCR) +#define CCM_CISR_REG(base) ((base)->CISR) +#define CCM_CIMR_REG(base) ((base)->CIMR) +#define CCM_CCOSR_REG(base) ((base)->CCOSR) +#define CCM_CGPR_REG(base) ((base)->CGPR) +#define CCM_CCGR0_REG(base) ((base)->CCGR0) +#define CCM_CCGR1_REG(base) ((base)->CCGR1) +#define CCM_CCGR2_REG(base) ((base)->CCGR2) +#define CCM_CCGR3_REG(base) ((base)->CCGR3) +#define CCM_CCGR4_REG(base) ((base)->CCGR4) +#define CCM_CCGR5_REG(base) ((base)->CCGR5) +#define CCM_CCGR6_REG(base) ((base)->CCGR6) +#define CCM_CMEOR_REG(base) ((base)->CMEOR) + +/*! + * @} + */ /* end of group CCM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/* CCR Bit Fields */ +#define CCM_CCR_OSCNT_MASK 0x7Fu +#define CCM_CCR_OSCNT_SHIFT 0 +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x))<PLL_ARM) +#define CCM_ANALOG_PLL_ARM_SET_REG(base) ((base)->PLL_ARM_SET) +#define CCM_ANALOG_PLL_ARM_CLR_REG(base) ((base)->PLL_ARM_CLR) +#define CCM_ANALOG_PLL_ARM_TOG_REG(base) ((base)->PLL_ARM_TOG) +#define CCM_ANALOG_PLL_USB1_REG(base) ((base)->PLL_USB1) +#define CCM_ANALOG_PLL_USB1_SET_REG(base) ((base)->PLL_USB1_SET) +#define CCM_ANALOG_PLL_USB1_CLR_REG(base) ((base)->PLL_USB1_CLR) +#define CCM_ANALOG_PLL_USB1_TOG_REG(base) ((base)->PLL_USB1_TOG) +#define CCM_ANALOG_PLL_USB2_REG(base) ((base)->PLL_USB2) +#define CCM_ANALOG_PLL_USB2_SET_REG(base) ((base)->PLL_USB2_SET) +#define CCM_ANALOG_PLL_USB2_CLR_REG(base) ((base)->PLL_USB2_CLR) +#define CCM_ANALOG_PLL_USB2_TOG_REG(base) ((base)->PLL_USB2_TOG) +#define CCM_ANALOG_PLL_SYS_REG(base) ((base)->PLL_SYS) +#define CCM_ANALOG_PLL_SYS_SET_REG(base) ((base)->PLL_SYS_SET) +#define CCM_ANALOG_PLL_SYS_CLR_REG(base) ((base)->PLL_SYS_CLR) +#define CCM_ANALOG_PLL_SYS_TOG_REG(base) ((base)->PLL_SYS_TOG) +#define CCM_ANALOG_PLL_SYS_SS_REG(base) ((base)->PLL_SYS_SS) +#define CCM_ANALOG_PLL_AUDIO_REG(base) ((base)->PLL_AUDIO) +#define CCM_ANALOG_PLL_AUDIO_SET_REG(base) ((base)->PLL_AUDIO_SET) +#define CCM_ANALOG_PLL_AUDIO_CLR_REG(base) ((base)->PLL_AUDIO_CLR) +#define CCM_ANALOG_PLL_AUDIO_TOG_REG(base) ((base)->PLL_AUDIO_TOG) +#define CCM_ANALOG_PLL_AUDIO_NUM_REG(base) ((base)->PLL_AUDIO_NUM) +#define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) ((base)->PLL_AUDIO_DENOM) +#define CCM_ANALOG_PLL_VIDEO_REG(base) ((base)->PLL_VIDEO) +#define CCM_ANALOG_PLL_VIDEO_SET_REG(base) ((base)->PLL_VIDEO_SET) +#define CCM_ANALOG_PLL_VIDEO_CLR_REG(base) ((base)->PLL_VIDEO_CLR) +#define CCM_ANALOG_PLL_VIDEO_TOG_REG(base) ((base)->PLL_VIDEO_TOG) +#define CCM_ANALOG_PLL_VIDEO_NUM_REG(base) ((base)->PLL_VIDEO_NUM) +#define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) ((base)->PLL_VIDEO_DENOM) +#define CCM_ANALOG_PLL_ENET_REG(base) ((base)->PLL_ENET) +#define CCM_ANALOG_PLL_ENET_SET_REG(base) ((base)->PLL_ENET_SET) +#define CCM_ANALOG_PLL_ENET_CLR_REG(base) ((base)->PLL_ENET_CLR) +#define CCM_ANALOG_PLL_ENET_TOG_REG(base) ((base)->PLL_ENET_TOG) +#define CCM_ANALOG_PFD_480_REG(base) ((base)->PFD_480) +#define CCM_ANALOG_PFD_480_SET_REG(base) ((base)->PFD_480_SET) +#define CCM_ANALOG_PFD_480_CLR_REG(base) ((base)->PFD_480_CLR) +#define CCM_ANALOG_PFD_480_TOG_REG(base) ((base)->PFD_480_TOG) +#define CCM_ANALOG_PFD_528_REG(base) ((base)->PFD_528) +#define CCM_ANALOG_PFD_528_SET_REG(base) ((base)->PFD_528_SET) +#define CCM_ANALOG_PFD_528_CLR_REG(base) ((base)->PFD_528_CLR) +#define CCM_ANALOG_PFD_528_TOG_REG(base) ((base)->PFD_528_TOG) +#define CCM_ANALOG_MISC0_REG(base) ((base)->MISC0) +#define CCM_ANALOG_MISC0_SET_REG(base) ((base)->MISC0_SET) +#define CCM_ANALOG_MISC0_CLR_REG(base) ((base)->MISC0_CLR) +#define CCM_ANALOG_MISC0_TOG_REG(base) ((base)->MISC0_TOG) +#define CCM_ANALOG_MISC1_REG(base) ((base)->MISC1) +#define CCM_ANALOG_MISC1_SET_REG(base) ((base)->MISC1_SET) +#define CCM_ANALOG_MISC1_CLR_REG(base) ((base)->MISC1_CLR) +#define CCM_ANALOG_MISC1_TOG_REG(base) ((base)->MISC1_TOG) +#define CCM_ANALOG_MISC2_REG(base) ((base)->MISC2) +#define CCM_ANALOG_MISC2_SET_REG(base) ((base)->MISC2_SET) +#define CCM_ANALOG_MISC2_CLR_REG(base) ((base)->MISC2_CLR) +#define CCM_ANALOG_MISC2_TOG_REG(base) ((base)->MISC2_TOG) + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/* PLL_ARM Bit Fields */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<CSICR1) +#define CSI_CSICR2_REG(base) ((base)->CSICR2) +#define CSI_CSICR3_REG(base) ((base)->CSICR3) +#define CSI_CSISTATFIFO_REG(base) ((base)->CSISTATFIFO) +#define CSI_CSIRFIFO_REG(base) ((base)->CSIRFIFO) +#define CSI_CSIRXCNT_REG(base) ((base)->CSIRXCNT) +#define CSI_CSISR_REG(base) ((base)->CSISR) +#define CSI_CSIDMASA_STATFIFO_REG(base) ((base)->CSIDMASA_STATFIFO) +#define CSI_CSIDMATS_STATFIFO_REG(base) ((base)->CSIDMATS_STATFIFO) +#define CSI_CSIDMASA_FB1_REG(base) ((base)->CSIDMASA_FB1) +#define CSI_CSIDMASA_FB2_REG(base) ((base)->CSIDMASA_FB2) +#define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) +#define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) +#define CSI_CSICR18_REG(base) ((base)->CSICR18) +#define CSI_CSICR19_REG(base) ((base)->CSICR19) + +/*! + * @} + */ /* end of group CSI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/* CSICR1 Bit Fields */ +#define CSI_CSICR1_PIXEL_BIT_MASK 0x1u +#define CSI_CSICR1_PIXEL_BIT_SHIFT 0 +#define CSI_CSICR1_REDGE_MASK 0x2u +#define CSI_CSICR1_REDGE_SHIFT 1 +#define CSI_CSICR1_INV_PCLK_MASK 0x4u +#define CSI_CSICR1_INV_PCLK_SHIFT 2 +#define CSI_CSICR1_INV_DATA_MASK 0x8u +#define CSI_CSICR1_INV_DATA_SHIFT 3 +#define CSI_CSICR1_GCLK_MODE_MASK 0x10u +#define CSI_CSICR1_GCLK_MODE_SHIFT 4 +#define CSI_CSICR1_CLR_RXFIFO_MASK 0x20u +#define CSI_CSICR1_CLR_RXFIFO_SHIFT 5 +#define CSI_CSICR1_CLR_STATFIFO_MASK 0x40u +#define CSI_CSICR1_CLR_STATFIFO_SHIFT 6 +#define CSI_CSICR1_PACK_DIR_MASK 0x80u +#define CSI_CSICR1_PACK_DIR_SHIFT 7 +#define CSI_CSICR1_FCC_MASK 0x100u +#define CSI_CSICR1_FCC_SHIFT 8 +#define CSI_CSICR1_CCIR_EN_MASK 0x400u +#define CSI_CSICR1_CCIR_EN_SHIFT 10 +#define CSI_CSICR1_HSYNC_POL_MASK 0x800u +#define CSI_CSICR1_HSYNC_POL_SHIFT 11 +#define CSI_CSICR1_SOF_INTEN_MASK 0x10000u +#define CSI_CSICR1_SOF_INTEN_SHIFT 16 +#define CSI_CSICR1_SOF_POL_MASK 0x20000u +#define CSI_CSICR1_SOF_POL_SHIFT 17 +#define CSI_CSICR1_RXFF_INTEN_MASK 0x40000u +#define CSI_CSICR1_RXFF_INTEN_SHIFT 18 +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK 0x80000u +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT 19 +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK 0x100000u +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT 20 +#define CSI_CSICR1_STATFF_INTEN_MASK 0x200000u +#define CSI_CSICR1_STATFF_INTEN_SHIFT 21 +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK 0x400000u +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT 22 +#define CSI_CSICR1_RF_OR_INTEN_MASK 0x1000000u +#define CSI_CSICR1_RF_OR_INTEN_SHIFT 24 +#define CSI_CSICR1_SF_OR_INTEN_MASK 0x2000000u +#define CSI_CSICR1_SF_OR_INTEN_SHIFT 25 +#define CSI_CSICR1_COF_INT_EN_MASK 0x4000000u +#define CSI_CSICR1_COF_INT_EN_SHIFT 26 +#define CSI_CSICR1_VIDEO_MODE_MASK 0x8000000u +#define CSI_CSICR1_VIDEO_MODE_SHIFT 27 +#define CSI_CSICR1_PrP_IF_EN_MASK 0x10000000u +#define CSI_CSICR1_PrP_IF_EN_SHIFT 28 +#define CSI_CSICR1_EOF_INT_EN_MASK 0x20000000u +#define CSI_CSICR1_EOF_INT_EN_SHIFT 29 +#define CSI_CSICR1_EXT_VSYNC_MASK 0x40000000u +#define CSI_CSICR1_EXT_VSYNC_SHIFT 30 +#define CSI_CSICR1_SWAP16_EN_MASK 0x80000000u +#define CSI_CSICR1_SWAP16_EN_SHIFT 31 +/* CSICR2 Bit Fields */ +#define CSI_CSICR2_HSC_MASK 0xFFu +#define CSI_CSICR2_HSC_SHIFT 0 +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x))<DCICC) +#define DCIC_DCICIC_REG(base) ((base)->DCICIC) +#define DCIC_DCICS_REG(base) ((base)->DCICS) +#define DCIC_DCICRC_REG(base) ((base)->DCICRC) +#define DCIC_DCICRS_REG(base) ((base)->DCICRS) +#define DCIC_DCICRRS_REG(base) ((base)->DCICRRS) +#define DCIC_DCICRCS_REG(base) ((base)->DCICRCS) + +/*! + * @} + */ /* end of group DCIC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- DCIC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCIC_Register_Masks DCIC Register Masks + * @{ + */ + +/* DCICC Bit Fields */ +#define DCIC_DCICC_IC_EN_MASK 0x1u +#define DCIC_DCICC_IC_EN_SHIFT 0 +#define DCIC_DCICC_DE_POL_MASK 0x10u +#define DCIC_DCICC_DE_POL_SHIFT 4 +#define DCIC_DCICC_HSYNC_POL_MASK 0x20u +#define DCIC_DCICC_HSYNC_POL_SHIFT 5 +#define DCIC_DCICC_VSYNC_POL_MASK 0x40u +#define DCIC_DCICC_VSYNC_POL_SHIFT 6 +#define DCIC_DCICC_CLK_POL_MASK 0x80u +#define DCIC_DCICC_CLK_POL_SHIFT 7 +/* DCICIC Bit Fields */ +#define DCIC_DCICIC_EI_MASK_MASK 0x1u +#define DCIC_DCICIC_EI_MASK_SHIFT 0 +#define DCIC_DCICIC_FI_MASK_MASK 0x2u +#define DCIC_DCICIC_FI_MASK_SHIFT 1 +#define DCIC_DCICIC_FREEZE_MASK_MASK 0x8u +#define DCIC_DCICIC_FREEZE_MASK_SHIFT 3 +#define DCIC_DCICIC_EXT_SIG_EN_MASK 0x10000u +#define DCIC_DCICIC_EXT_SIG_EN_SHIFT 16 +/* DCICS Bit Fields */ +#define DCIC_DCICS_ROI_MATCH_STAT_MASK 0xFFFFu +#define DCIC_DCICS_ROI_MATCH_STAT_SHIFT 0 +#define DCIC_DCICS_ROI_MATCH_STAT(x) (((uint32_t)(((uint32_t)(x))<THRS) +#define DVFSC_COUN_REG(base) ((base)->COUN) +#define DVFSC_SIG1_REG(base) ((base)->SIG1) +#define DVFSC_DVFSSIG0_REG(base) ((base)->DVFSSIG0) +#define DVFSC_DVFSGPC0_REG(base) ((base)->DVFSGPC0) +#define DVFSC_DVFSGPC1_REG(base) ((base)->DVFSGPC1) +#define DVFSC_DVFSGPBT_REG(base) ((base)->DVFSGPBT) +#define DVFSC_DVFSEMAC_REG(base) ((base)->DVFSEMAC) +#define DVFSC_CNTR_REG(base) ((base)->CNTR) +#define DVFSC_DVFSLTR0_0_REG(base) ((base)->DVFSLTR0_0) +#define DVFSC_DVFSLTR0_1_REG(base) ((base)->DVFSLTR0_1) +#define DVFSC_DVFSLTR1_0_REG(base) ((base)->DVFSLTR1_0) +#define DVFSC_DVFSLTR1_1_REG(base) ((base)->DVFSLTR1_1) +#define DVFSC_DVFSPT0_REG(base) ((base)->DVFSPT0) +#define DVFSC_DVFSPT1_REG(base) ((base)->DVFSPT1) +#define DVFSC_DVFSPT2_REG(base) ((base)->DVFSPT2) +#define DVFSC_DVFSPT3_REG(base) ((base)->DVFSPT3) + +/*! + * @} + */ /* end of group DVFSC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- DVFSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DVFSC_Register_Masks DVFSC Register Masks + * @{ + */ + +/* THRS Bit Fields */ +#define DVFSC_THRS_PNCTHR_MASK 0x3Fu +#define DVFSC_THRS_PNCTHR_SHIFT 0 +#define DVFSC_THRS_PNCTHR(x) (((uint32_t)(((uint32_t)(x))<RXDATA) +#define ECSPI_TXDATA_REG(base) ((base)->TXDATA) +#define ECSPI_CONREG_REG(base) ((base)->CONREG) +#define ECSPI_CONFIGREG_REG(base) ((base)->CONFIGREG) +#define ECSPI_INTREG_REG(base) ((base)->INTREG) +#define ECSPI_DMAREG_REG(base) ((base)->DMAREG) +#define ECSPI_STATREG_REG(base) ((base)->STATREG) +#define ECSPI_PERIODREG_REG(base) ((base)->PERIODREG) +#define ECSPI_TESTREG_REG(base) ((base)->TESTREG) +#define ECSPI_MSGDATA_REG(base) ((base)->MSGDATA) + +/*! + * @} + */ /* end of group ECSPI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/* RXDATA Bit Fields */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK 0xFFFFFFFFu +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT 0 +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x))<CS[index].CSGCR1) +#define EIM_CSGCR2_REG(base,index) ((base)->CS[index].CSGCR2) +#define EIM_CSRCR1_REG(base,index) ((base)->CS[index].CSRCR1) +#define EIM_CSRCR2_REG(base,index) ((base)->CS[index].CSRCR2) +#define EIM_CSWCR1_REG(base,index) ((base)->CS[index].CSWCR1) +#define EIM_CSWCR2_REG(base,index) ((base)->CS[index].CSWCR2) +#define EIM_WCR_REG(base) ((base)->WCR) +#define EIM_DCR_REG(base) ((base)->DCR) +#define EIM_DSR_REG(base) ((base)->DSR) +#define EIM_WIAR_REG(base) ((base)->WIAR) +#define EIM_EAR_REG(base) ((base)->EAR) + +/*! + * @} + */ /* end of group EIM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/* CSGCR1 Bit Fields */ +#define EIM_CSGCR1_CSEN_MASK 0x1u +#define EIM_CSGCR1_CSEN_SHIFT 0 +#define EIM_CSGCR1_SWR_MASK 0x2u +#define EIM_CSGCR1_SWR_SHIFT 1 +#define EIM_CSGCR1_SRD_MASK 0x4u +#define EIM_CSGCR1_SRD_SHIFT 2 +#define EIM_CSGCR1_MUM_MASK 0x8u +#define EIM_CSGCR1_MUM_SHIFT 3 +#define EIM_CSGCR1_WFL_MASK 0x10u +#define EIM_CSGCR1_WFL_SHIFT 4 +#define EIM_CSGCR1_RFL_MASK 0x20u +#define EIM_CSGCR1_RFL_SHIFT 5 +#define EIM_CSGCR1_CRE_MASK 0x40u +#define EIM_CSGCR1_CRE_SHIFT 6 +#define EIM_CSGCR1_CREP_MASK 0x80u +#define EIM_CSGCR1_CREP_SHIFT 7 +#define EIM_CSGCR1_BL_MASK 0x700u +#define EIM_CSGCR1_BL_SHIFT 8 +#define EIM_CSGCR1_BL(x) (((uint32_t)(((uint32_t)(x))<EIR) +#define ENET_EIMR_REG(base) ((base)->EIMR) +#define ENET_RDAR_REG(base) ((base)->RDAR) +#define ENET_TDAR_REG(base) ((base)->TDAR) +#define ENET_ECR_REG(base) ((base)->ECR) +#define ENET_MMFR_REG(base) ((base)->MMFR) +#define ENET_MSCR_REG(base) ((base)->MSCR) +#define ENET_MIBC_REG(base) ((base)->MIBC) +#define ENET_RCR_REG(base) ((base)->RCR) +#define ENET_TCR_REG(base) ((base)->TCR) +#define ENET_PALR_REG(base) ((base)->PALR) +#define ENET_PAUR_REG(base) ((base)->PAUR) +#define ENET_OPD_REG(base) ((base)->OPD) +#define ENET_TXIC_REG(base,index) ((base)->TXIC[index]) +#define ENET_RXIC_REG(base,index) ((base)->RXIC[index]) +#define ENET_IAUR_REG(base) ((base)->IAUR) +#define ENET_IALR_REG(base) ((base)->IALR) +#define ENET_GAUR_REG(base) ((base)->GAUR) +#define ENET_GALR_REG(base) ((base)->GALR) +#define ENET_TFWR_REG(base) ((base)->TFWR) +#define ENET_RDSR1_REG(base) ((base)->RDSR1) +#define ENET_TDSR1_REG(base) ((base)->TDSR1) +#define ENET_MRBR1_REG(base) ((base)->MRBR1) +#define ENET_RDSR2_REG(base) ((base)->RDSR2) +#define ENET_TDSR2_REG(base) ((base)->TDSR2) +#define ENET_MRBR2_REG(base) ((base)->MRBR2) +#define ENET_RDSR_REG(base) ((base)->RDSR) +#define ENET_TDSR_REG(base) ((base)->TDSR) +#define ENET_MRBR_REG(base) ((base)->MRBR) +#define ENET_RSFL_REG(base) ((base)->RSFL) +#define ENET_RSEM_REG(base) ((base)->RSEM) +#define ENET_RAEM_REG(base) ((base)->RAEM) +#define ENET_RAFL_REG(base) ((base)->RAFL) +#define ENET_TSEM_REG(base) ((base)->TSEM) +#define ENET_TAEM_REG(base) ((base)->TAEM) +#define ENET_TAFL_REG(base) ((base)->TAFL) +#define ENET_TIPG_REG(base) ((base)->TIPG) +#define ENET_FTRL_REG(base) ((base)->FTRL) +#define ENET_TACC_REG(base) ((base)->TACC) +#define ENET_RACC_REG(base) ((base)->RACC) +#define ENET_RCMR_REG(base,index) ((base)->RCMR[index]) +#define ENET_DMACFG_REG(base,index) ((base)->DMACFG[index]) +#define ENET_RDAR1_REG(base) ((base)->RDAR1) +#define ENET_TDAR1_REG(base) ((base)->TDAR1) +#define ENET_RDAR2_REG(base) ((base)->RDAR2) +#define ENET_TDAR2_REG(base) ((base)->TDAR2) +#define ENET_QOS_REG(base) ((base)->QOS) +#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) +#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) +#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) +#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) +#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) +#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) +#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) +#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) +#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) +#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) +#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) +#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) +#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) +#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) +#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) +#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) +#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) +#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) +#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) +#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) +#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) +#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) +#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) +#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) +#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) +#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) +#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) +#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) +#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) +#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) +#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) +#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) +#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) +#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) +#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) +#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) +#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) +#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) +#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) +#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) +#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) +#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) +#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) +#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) +#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) +#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) +#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) +#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) +#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) +#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) +#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) +#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) +#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) +#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) +#define ENET_ATCR_REG(base) ((base)->ATCR) +#define ENET_ATVR_REG(base) ((base)->ATVR) +#define ENET_ATOFF_REG(base) ((base)->ATOFF) +#define ENET_ATPER_REG(base) ((base)->ATPER) +#define ENET_ATCOR_REG(base) ((base)->ATCOR) +#define ENET_ATINC_REG(base) ((base)->ATINC) +#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) +#define ENET_TGSR_REG(base) ((base)->TGSR) +#define ENET_TCSR_REG(base,index) ((base)->TC[index].TCSR) +#define ENET_TCCR_REG(base,index) ((base)->TC[index].TCCR) + +/*! + * @} + */ /* end of group ENET_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/* EIR Bit Fields */ +#define ENET_EIR_RXB1_MASK 0x1u +#define ENET_EIR_RXB1_SHIFT 0 +#define ENET_EIR_RXF1_MASK 0x2u +#define ENET_EIR_RXF1_SHIFT 1 +#define ENET_EIR_TXB1_MASK 0x4u +#define ENET_EIR_TXB1_SHIFT 2 +#define ENET_EIR_TXF1_MASK 0x8u +#define ENET_EIR_TXF1_SHIFT 3 +#define ENET_EIR_RXB2_MASK 0x10u +#define ENET_EIR_RXB2_SHIFT 4 +#define ENET_EIR_RXF2_MASK 0x20u +#define ENET_EIR_RXF2_SHIFT 5 +#define ENET_EIR_TXB2_MASK 0x40u +#define ENET_EIR_TXB2_SHIFT 6 +#define ENET_EIR_TXF2_MASK 0x80u +#define ENET_EIR_TXF2_SHIFT 7 +#define ENET_EIR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIR_RXFLUSH_0_SHIFT 12 +#define ENET_EIR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIR_RXFLUSH_1_SHIFT 13 +#define ENET_EIR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIR_RXFLUSH_2_SHIFT 14 +#define ENET_EIR_TS_TIMER_MASK 0x8000u +#define ENET_EIR_TS_TIMER_SHIFT 15 +#define ENET_EIR_TS_AVAIL_MASK 0x10000u +#define ENET_EIR_TS_AVAIL_SHIFT 16 +#define ENET_EIR_WAKEUP_MASK 0x20000u +#define ENET_EIR_WAKEUP_SHIFT 17 +#define ENET_EIR_PLR_MASK 0x40000u +#define ENET_EIR_PLR_SHIFT 18 +#define ENET_EIR_UN_MASK 0x80000u +#define ENET_EIR_UN_SHIFT 19 +#define ENET_EIR_RL_MASK 0x100000u +#define ENET_EIR_RL_SHIFT 20 +#define ENET_EIR_LC_MASK 0x200000u +#define ENET_EIR_LC_SHIFT 21 +#define ENET_EIR_EBERR_MASK 0x400000u +#define ENET_EIR_EBERR_SHIFT 22 +#define ENET_EIR_MII_MASK 0x800000u +#define ENET_EIR_MII_SHIFT 23 +#define ENET_EIR_RXB_MASK 0x1000000u +#define ENET_EIR_RXB_SHIFT 24 +#define ENET_EIR_RXF_MASK 0x2000000u +#define ENET_EIR_RXF_SHIFT 25 +#define ENET_EIR_TXB_MASK 0x4000000u +#define ENET_EIR_TXB_SHIFT 26 +#define ENET_EIR_TXF_MASK 0x8000000u +#define ENET_EIR_TXF_SHIFT 27 +#define ENET_EIR_GRA_MASK 0x10000000u +#define ENET_EIR_GRA_SHIFT 28 +#define ENET_EIR_BABT_MASK 0x20000000u +#define ENET_EIR_BABT_SHIFT 29 +#define ENET_EIR_BABR_MASK 0x40000000u +#define ENET_EIR_BABR_SHIFT 30 +/* EIMR Bit Fields */ +#define ENET_EIMR_RXB1_MASK 0x1u +#define ENET_EIMR_RXB1_SHIFT 0 +#define ENET_EIMR_RXF1_MASK 0x2u +#define ENET_EIMR_RXF1_SHIFT 1 +#define ENET_EIMR_TXB1_MASK 0x4u +#define ENET_EIMR_TXB1_SHIFT 2 +#define ENET_EIMR_TXF1_MASK 0x8u +#define ENET_EIMR_TXF1_SHIFT 3 +#define ENET_EIMR_RXB2_MASK 0x10u +#define ENET_EIMR_RXB2_SHIFT 4 +#define ENET_EIMR_RXF2_MASK 0x20u +#define ENET_EIMR_RXF2_SHIFT 5 +#define ENET_EIMR_TXB2_MASK 0x40u +#define ENET_EIMR_TXB2_SHIFT 6 +#define ENET_EIMR_TXF2_MASK 0x80u +#define ENET_EIMR_TXF2_SHIFT 7 +#define ENET_EIMR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIMR_RXFLUSH_0_SHIFT 12 +#define ENET_EIMR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIMR_RXFLUSH_1_SHIFT 13 +#define ENET_EIMR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIMR_RXFLUSH_2_SHIFT 14 +#define ENET_EIMR_TS_TIMER_MASK 0x8000u +#define ENET_EIMR_TS_TIMER_SHIFT 15 +#define ENET_EIMR_TS_AVAIL_MASK 0x10000u +#define ENET_EIMR_TS_AVAIL_SHIFT 16 +#define ENET_EIMR_WAKEUP_MASK 0x20000u +#define ENET_EIMR_WAKEUP_SHIFT 17 +#define ENET_EIMR_PLR_MASK 0x40000u +#define ENET_EIMR_PLR_SHIFT 18 +#define ENET_EIMR_UN_MASK 0x80000u +#define ENET_EIMR_UN_SHIFT 19 +#define ENET_EIMR_RL_MASK 0x100000u +#define ENET_EIMR_RL_SHIFT 20 +#define ENET_EIMR_LC_MASK 0x200000u +#define ENET_EIMR_LC_SHIFT 21 +#define ENET_EIMR_EBERR_MASK 0x400000u +#define ENET_EIMR_EBERR_SHIFT 22 +#define ENET_EIMR_MII_MASK 0x800000u +#define ENET_EIMR_MII_SHIFT 23 +#define ENET_EIMR_RXB_MASK 0x1000000u +#define ENET_EIMR_RXB_SHIFT 24 +#define ENET_EIMR_RXF_MASK 0x2000000u +#define ENET_EIMR_RXF_SHIFT 25 +#define ENET_EIMR_TXB_MASK 0x4000000u +#define ENET_EIMR_TXB_SHIFT 26 +#define ENET_EIMR_TXF_MASK 0x8000000u +#define ENET_EIMR_TXF_SHIFT 27 +#define ENET_EIMR_GRA_MASK 0x10000000u +#define ENET_EIMR_GRA_SHIFT 28 +#define ENET_EIMR_BABT_MASK 0x20000000u +#define ENET_EIMR_BABT_SHIFT 29 +#define ENET_EIMR_BABR_MASK 0x40000000u +#define ENET_EIMR_BABR_SHIFT 30 +/* RDAR Bit Fields */ +#define ENET_RDAR_RDAR_MASK 0x1000000u +#define ENET_RDAR_RDAR_SHIFT 24 +/* TDAR Bit Fields */ +#define ENET_TDAR_TDAR_MASK 0x1000000u +#define ENET_TDAR_TDAR_SHIFT 24 +/* ECR Bit Fields */ +#define ENET_ECR_RESET_MASK 0x1u +#define ENET_ECR_RESET_SHIFT 0 +#define ENET_ECR_ETHEREN_MASK 0x2u +#define ENET_ECR_ETHEREN_SHIFT 1 +#define ENET_ECR_MAGICEN_MASK 0x4u +#define ENET_ECR_MAGICEN_SHIFT 2 +#define ENET_ECR_SLEEP_MASK 0x8u +#define ENET_ECR_SLEEP_SHIFT 3 +#define ENET_ECR_EN1588_MASK 0x10u +#define ENET_ECR_EN1588_SHIFT 4 +#define ENET_ECR_SPEED_MASK 0x20u +#define ENET_ECR_SPEED_SHIFT 5 +#define ENET_ECR_DBGEN_MASK 0x40u +#define ENET_ECR_DBGEN_SHIFT 6 +#define ENET_ECR_DBSWP_MASK 0x100u +#define ENET_ECR_DBSWP_SHIFT 8 +#define ENET_ECR_SVLANEN_MASK 0x200u +#define ENET_ECR_SVLANEN_SHIFT 9 +#define ENET_ECR_VLANUSE2ND_MASK 0x400u +#define ENET_ECR_VLANUSE2ND_SHIFT 10 +#define ENET_ECR_SVLANDBL_MASK 0x800u +#define ENET_ECR_SVLANDBL_SHIFT 11 +/* MMFR Bit Fields */ +#define ENET_MMFR_DATA_MASK 0xFFFFu +#define ENET_MMFR_DATA_SHIFT 0 +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CR) +#define EPIT_SR_REG(base) ((base)->SR) +#define EPIT_LR_REG(base) ((base)->LR) +#define EPIT_CMPR_REG(base) ((base)->CMPR) +#define EPIT_CNR_REG(base) ((base)->CNR) + +/*! + * @} + */ /* end of group EPIT_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- EPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Register_Masks EPIT Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define EPIT_CR_EN_MASK 0x1u +#define EPIT_CR_EN_SHIFT 0 +#define EPIT_CR_ENMOD_MASK 0x2u +#define EPIT_CR_ENMOD_SHIFT 1 +#define EPIT_CR_OCIEN_MASK 0x4u +#define EPIT_CR_OCIEN_SHIFT 2 +#define EPIT_CR_RLD_MASK 0x8u +#define EPIT_CR_RLD_SHIFT 3 +#define EPIT_CR_PRESCALAR_MASK 0xFFF0u +#define EPIT_CR_PRESCALAR_SHIFT 4 +#define EPIT_CR_PRESCALAR(x) (((uint32_t)(((uint32_t)(x))<ETDR) +#define ESAI_ERDR_REG(base) ((base)->ERDR) +#define ESAI_ECR_REG(base) ((base)->ECR) +#define ESAI_ESR_REG(base) ((base)->ESR) +#define ESAI_TFCR_REG(base) ((base)->TFCR) +#define ESAI_TFSR_REG(base) ((base)->TFSR) +#define ESAI_RFCR_REG(base) ((base)->RFCR) +#define ESAI_RFSR_REG(base) ((base)->RFSR) +#define ESAI_TX_REG(base,index) ((base)->TX[index]) +#define ESAI_TSR_REG(base) ((base)->TSR) +#define ESAI_RX_REG(base,index) ((base)->RX[index]) +#define ESAI_SAISR_REG(base) ((base)->SAISR) +#define ESAI_SAICR_REG(base) ((base)->SAICR) +#define ESAI_TCR_REG(base) ((base)->TCR) +#define ESAI_TCCR_REG(base) ((base)->TCCR) +#define ESAI_RCR_REG(base) ((base)->RCR) +#define ESAI_RCCR_REG(base) ((base)->RCCR) +#define ESAI_TSMA_REG(base) ((base)->TSMA) +#define ESAI_TSMB_REG(base) ((base)->TSMB) +#define ESAI_RSMA_REG(base) ((base)->RSMA) +#define ESAI_RSMB_REG(base) ((base)->RSMB) +#define ESAI_PRRC_REG(base) ((base)->PRRC) +#define ESAI_PCRC_REG(base) ((base)->PCRC) + +/*! + * @} + */ /* end of group ESAI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ESAI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Register_Masks ESAI Register Masks + * @{ + */ + +/* ETDR Bit Fields */ +#define ESAI_ETDR_ETDR_MASK 0xFFFFFFFFu +#define ESAI_ETDR_ETDR_SHIFT 0 +#define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define GIS_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define GIS_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define GIS_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define GIS_CONFIG0_REG(base) ((base)->CONFIG0) +#define GIS_CONFIG0_SET_REG(base) ((base)->CONFIG0_SET) +#define GIS_CONFIG0_CLR_REG(base) ((base)->CONFIG0_CLR) +#define GIS_CONFIG0_TOG_REG(base) ((base)->CONFIG0_TOG) +#define GIS_CONFIG1_REG(base) ((base)->CONFIG1) +#define GIS_CONFIG1_SET_REG(base) ((base)->CONFIG1_SET) +#define GIS_CONFIG1_CLR_REG(base) ((base)->CONFIG1_CLR) +#define GIS_CONFIG1_TOG_REG(base) ((base)->CONFIG1_TOG) +#define GIS_FB0_REG(base) ((base)->FB0) +#define GIS_FB1_REG(base) ((base)->FB1) +#define GIS_PXP_FB0_REG(base) ((base)->PXP_FB0) +#define GIS_PXP_FB1_REG(base) ((base)->PXP_FB1) +#define GIS_CH0_CTRL_REG(base) ((base)->CH0_CTRL) +#define GIS_CH0_CTRL_SET_REG(base) ((base)->CH0_CTRL_SET) +#define GIS_CH0_CTRL_CLR_REG(base) ((base)->CH0_CTRL_CLR) +#define GIS_CH0_CTRL_TOG_REG(base) ((base)->CH0_CTRL_TOG) +#define GIS_CH0_ADDR0_REG(base) ((base)->CH0_ADDR0) +#define GIS_CH0_ADDR0_SET_REG(base) ((base)->CH0_ADDR0_SET) +#define GIS_CH0_ADDR0_CLR_REG(base) ((base)->CH0_ADDR0_CLR) +#define GIS_CH0_ADDR0_TOG_REG(base) ((base)->CH0_ADDR0_TOG) +#define GIS_CH0_DATA0_REG(base) ((base)->CH0_DATA0) +#define GIS_CH0_ADDR1_REG(base) ((base)->CH0_ADDR1) +#define GIS_CH0_ADDR1_SET_REG(base) ((base)->CH0_ADDR1_SET) +#define GIS_CH0_ADDR1_CLR_REG(base) ((base)->CH0_ADDR1_CLR) +#define GIS_CH0_ADDR1_TOG_REG(base) ((base)->CH0_ADDR1_TOG) +#define GIS_CH0_DATA1_REG(base) ((base)->CH0_DATA1) +#define GIS_CH0_ADDR2_REG(base) ((base)->CH0_ADDR2) +#define GIS_CH0_ADDR2_SET_REG(base) ((base)->CH0_ADDR2_SET) +#define GIS_CH0_ADDR2_CLR_REG(base) ((base)->CH0_ADDR2_CLR) +#define GIS_CH0_ADDR2_TOG_REG(base) ((base)->CH0_ADDR2_TOG) +#define GIS_CH0_DATA2_REG(base) ((base)->CH0_DATA2) +#define GIS_CH0_ADDR3_REG(base) ((base)->CH0_ADDR3) +#define GIS_CH0_ADDR3_SET_REG(base) ((base)->CH0_ADDR3_SET) +#define GIS_CH0_ADDR3_CLR_REG(base) ((base)->CH0_ADDR3_CLR) +#define GIS_CH0_ADDR3_TOG_REG(base) ((base)->CH0_ADDR3_TOG) +#define GIS_CH0_DATA3_REG(base) ((base)->CH0_DATA3) +#define GIS_CH1_CTRL_REG(base) ((base)->CH1_CTRL) +#define GIS_CH1_CTRL_SET_REG(base) ((base)->CH1_CTRL_SET) +#define GIS_CH1_CTRL_CLR_REG(base) ((base)->CH1_CTRL_CLR) +#define GIS_CH1_CTRL_TOG_REG(base) ((base)->CH1_CTRL_TOG) +#define GIS_CH1_ADDR0_REG(base) ((base)->CH1_ADDR0) +#define GIS_CH1_ADDR0_SET_REG(base) ((base)->CH1_ADDR0_SET) +#define GIS_CH1_ADDR0_CLR_REG(base) ((base)->CH1_ADDR0_CLR) +#define GIS_CH1_ADDR0_TOG_REG(base) ((base)->CH1_ADDR0_TOG) +#define GIS_CH1_DATA0_REG(base) ((base)->CH1_DATA0) +#define GIS_CH1_ADDR1_REG(base) ((base)->CH1_ADDR1) +#define GIS_CH1_ADDR1_SET_REG(base) ((base)->CH1_ADDR1_SET) +#define GIS_CH1_ADDR1_CLR_REG(base) ((base)->CH1_ADDR1_CLR) +#define GIS_CH1_ADDR1_TOG_REG(base) ((base)->CH1_ADDR1_TOG) +#define GIS_CH1_DATA1_REG(base) ((base)->CH1_DATA1) +#define GIS_CH1_ADDR2_REG(base) ((base)->CH1_ADDR2) +#define GIS_CH1_ADDR2_SET_REG(base) ((base)->CH1_ADDR2_SET) +#define GIS_CH1_ADDR2_CLR_REG(base) ((base)->CH1_ADDR2_CLR) +#define GIS_CH1_ADDR2_TOG_REG(base) ((base)->CH1_ADDR2_TOG) +#define GIS_CH1_DATA2_REG(base) ((base)->CH1_DATA2) +#define GIS_CH1_ADDR3_REG(base) ((base)->CH1_ADDR3) +#define GIS_CH1_ADDR3_SET_REG(base) ((base)->CH1_ADDR3_SET) +#define GIS_CH1_ADDR3_CLR_REG(base) ((base)->CH1_ADDR3_CLR) +#define GIS_CH1_ADDR3_TOG_REG(base) ((base)->CH1_ADDR3_TOG) +#define GIS_CH1_DATA3_REG(base) ((base)->CH1_DATA3) +#define GIS_CH2_CTRL_REG(base) ((base)->CH2_CTRL) +#define GIS_CH2_CTRL_SET_REG(base) ((base)->CH2_CTRL_SET) +#define GIS_CH2_CTRL_CLR_REG(base) ((base)->CH2_CTRL_CLR) +#define GIS_CH2_CTRL_TOG_REG(base) ((base)->CH2_CTRL_TOG) +#define GIS_CH2_ADDR0_REG(base) ((base)->CH2_ADDR0) +#define GIS_CH2_ADDR0_SET_REG(base) ((base)->CH2_ADDR0_SET) +#define GIS_CH2_ADDR0_CLR_REG(base) ((base)->CH2_ADDR0_CLR) +#define GIS_CH2_ADDR0_TOG_REG(base) ((base)->CH2_ADDR0_TOG) +#define GIS_CH2_DATA0_REG(base) ((base)->CH2_DATA0) +#define GIS_CH2_ADDR1_REG(base) ((base)->CH2_ADDR1) +#define GIS_CH2_ADDR1_SET_REG(base) ((base)->CH2_ADDR1_SET) +#define GIS_CH2_ADDR1_CLR_REG(base) ((base)->CH2_ADDR1_CLR) +#define GIS_CH2_ADDR1_TOG_REG(base) ((base)->CH2_ADDR1_TOG) +#define GIS_CH2_DATA1_REG(base) ((base)->CH2_DATA1) +#define GIS_CH2_ADDR2_REG(base) ((base)->CH2_ADDR2) +#define GIS_CH2_ADDR2_SET_REG(base) ((base)->CH2_ADDR2_SET) +#define GIS_CH2_ADDR2_CLR_REG(base) ((base)->CH2_ADDR2_CLR) +#define GIS_CH2_ADDR2_TOG_REG(base) ((base)->CH2_ADDR2_TOG) +#define GIS_CH2_DATA2_REG(base) ((base)->CH2_DATA2) +#define GIS_CH2_ADDR3_REG(base) ((base)->CH2_ADDR3) +#define GIS_CH2_ADDR3_SET_REG(base) ((base)->CH2_ADDR3_SET) +#define GIS_CH2_ADDR3_CLR_REG(base) ((base)->CH2_ADDR3_CLR) +#define GIS_CH2_ADDR3_TOG_REG(base) ((base)->CH2_ADDR3_TOG) +#define GIS_CH2_DATA3_REG(base) ((base)->CH2_DATA3) +#define GIS_CH3_CTRL_REG(base) ((base)->CH3_CTRL) +#define GIS_CH3_CTRL_SET_REG(base) ((base)->CH3_CTRL_SET) +#define GIS_CH3_CTRL_CLR_REG(base) ((base)->CH3_CTRL_CLR) +#define GIS_CH3_CTRL_TOG_REG(base) ((base)->CH3_CTRL_TOG) +#define GIS_CH3_ADDR0_REG(base) ((base)->CH3_ADDR0) +#define GIS_CH3_ADDR0_SET_REG(base) ((base)->CH3_ADDR0_SET) +#define GIS_CH3_ADDR0_CLR_REG(base) ((base)->CH3_ADDR0_CLR) +#define GIS_CH3_ADDR0_TOG_REG(base) ((base)->CH3_ADDR0_TOG) +#define GIS_CH3_DATA0_REG(base) ((base)->CH3_DATA0) +#define GIS_CH3_ADDR1_REG(base) ((base)->CH3_ADDR1) +#define GIS_CH3_ADDR1_SET_REG(base) ((base)->CH3_ADDR1_SET) +#define GIS_CH3_ADDR1_CLR_REG(base) ((base)->CH3_ADDR1_CLR) +#define GIS_CH3_ADDR1_TOG_REG(base) ((base)->CH3_ADDR1_TOG) +#define GIS_CH3_DATA1_REG(base) ((base)->CH3_DATA1) +#define GIS_CH3_ADDR2_REG(base) ((base)->CH3_ADDR2) +#define GIS_CH3_ADDR2_SET_REG(base) ((base)->CH3_ADDR2_SET) +#define GIS_CH3_ADDR2_CLR_REG(base) ((base)->CH3_ADDR2_CLR) +#define GIS_CH3_ADDR2_TOG_REG(base) ((base)->CH3_ADDR2_TOG) +#define GIS_CH3_DATA2_REG(base) ((base)->CH3_DATA2) +#define GIS_CH3_ADDR3_REG(base) ((base)->CH3_ADDR3) +#define GIS_CH3_ADDR3_SET_REG(base) ((base)->CH3_ADDR3_SET) +#define GIS_CH3_ADDR3_CLR_REG(base) ((base)->CH3_ADDR3_CLR) +#define GIS_CH3_ADDR3_TOG_REG(base) ((base)->CH3_ADDR3_TOG) +#define GIS_CH3_DATA3_REG(base) ((base)->CH3_DATA3) +#define GIS_CH4_CTRL_REG(base) ((base)->CH4_CTRL) +#define GIS_CH4_CTRL_SET_REG(base) ((base)->CH4_CTRL_SET) +#define GIS_CH4_CTRL_CLR_REG(base) ((base)->CH4_CTRL_CLR) +#define GIS_CH4_CTRL_TOG_REG(base) ((base)->CH4_CTRL_TOG) +#define GIS_CH4_ADDR0_REG(base) ((base)->CH4_ADDR0) +#define GIS_CH4_ADDR0_SET_REG(base) ((base)->CH4_ADDR0_SET) +#define GIS_CH4_ADDR0_CLR_REG(base) ((base)->CH4_ADDR0_CLR) +#define GIS_CH4_ADDR0_TOG_REG(base) ((base)->CH4_ADDR0_TOG) +#define GIS_CH4_DATA0_REG(base) ((base)->CH4_DATA0) +#define GIS_CH4_ADDR1_REG(base) ((base)->CH4_ADDR1) +#define GIS_CH4_ADDR1_SET_REG(base) ((base)->CH4_ADDR1_SET) +#define GIS_CH4_ADDR1_CLR_REG(base) ((base)->CH4_ADDR1_CLR) +#define GIS_CH4_ADDR1_TOG_REG(base) ((base)->CH4_ADDR1_TOG) +#define GIS_CH4_DATA1_REG(base) ((base)->CH4_DATA1) +#define GIS_CH4_ADDR2_REG(base) ((base)->CH4_ADDR2) +#define GIS_CH4_ADDR2_SET_REG(base) ((base)->CH4_ADDR2_SET) +#define GIS_CH4_ADDR2_CLR_REG(base) ((base)->CH4_ADDR2_CLR) +#define GIS_CH4_ADDR2_TOG_REG(base) ((base)->CH4_ADDR2_TOG) +#define GIS_CH4_DATA2_REG(base) ((base)->CH4_DATA2) +#define GIS_CH4_ADDR3_REG(base) ((base)->CH4_ADDR3) +#define GIS_CH4_ADDR3_SET_REG(base) ((base)->CH4_ADDR3_SET) +#define GIS_CH4_ADDR3_CLR_REG(base) ((base)->CH4_ADDR3_CLR) +#define GIS_CH4_ADDR3_TOG_REG(base) ((base)->CH4_ADDR3_TOG) +#define GIS_CH4_DATA3_REG(base) ((base)->CH4_DATA3) +#define GIS_CH5_CTRL_REG(base) ((base)->CH5_CTRL) +#define GIS_CH5_CTRL_SET_REG(base) ((base)->CH5_CTRL_SET) +#define GIS_CH5_CTRL_CLR_REG(base) ((base)->CH5_CTRL_CLR) +#define GIS_CH5_CTRL_TOG_REG(base) ((base)->CH5_CTRL_TOG) +#define GIS_CH5_ADDR0_REG(base) ((base)->CH5_ADDR0) +#define GIS_CH5_ADDR0_SET_REG(base) ((base)->CH5_ADDR0_SET) +#define GIS_CH5_ADDR0_CLR_REG(base) ((base)->CH5_ADDR0_CLR) +#define GIS_CH5_ADDR0_TOG_REG(base) ((base)->CH5_ADDR0_TOG) +#define GIS_CH5_DATA0_REG(base) ((base)->CH5_DATA0) +#define GIS_CH5_ADDR1_REG(base) ((base)->CH5_ADDR1) +#define GIS_CH5_ADDR1_SET_REG(base) ((base)->CH5_ADDR1_SET) +#define GIS_CH5_ADDR1_CLR_REG(base) ((base)->CH5_ADDR1_CLR) +#define GIS_CH5_ADDR1_TOG_REG(base) ((base)->CH5_ADDR1_TOG) +#define GIS_CH5_DATA1_REG(base) ((base)->CH5_DATA1) +#define GIS_CH5_ADDR2_REG(base) ((base)->CH5_ADDR2) +#define GIS_CH5_ADDR2_SET_REG(base) ((base)->CH5_ADDR2_SET) +#define GIS_CH5_ADDR2_CLR_REG(base) ((base)->CH5_ADDR2_CLR) +#define GIS_CH5_ADDR2_TOG_REG(base) ((base)->CH5_ADDR2_TOG) +#define GIS_CH5_DATA2_REG(base) ((base)->CH5_DATA2) +#define GIS_CH5_ADDR3_REG(base) ((base)->CH5_ADDR3) +#define GIS_CH5_ADDR3_SET_REG(base) ((base)->CH5_ADDR3_SET) +#define GIS_CH5_ADDR3_CLR_REG(base) ((base)->CH5_ADDR3_CLR) +#define GIS_CH5_ADDR3_TOG_REG(base) ((base)->CH5_ADDR3_TOG) +#define GIS_CH5_DATA3_REG(base) ((base)->CH5_DATA3) +#define GIS_DEBUG0_REG(base) ((base)->DEBUG0) +#define GIS_DEBUG1_REG(base) ((base)->DEBUG1) +#define GIS_VERSION_REG(base) ((base)->VERSION) + +/*! + * @} + */ /* end of group GIS_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GIS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GIS_Register_Masks GIS Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define GIS_CTRL_ENABLE_MASK 0x1u +#define GIS_CTRL_ENABLE_SHIFT 0 +#define GIS_CTRL_FB_START_MASK 0x2u +#define GIS_CTRL_FB_START_SHIFT 1 +#define GIS_CTRL_LCDIF_SEL_MASK 0x4u +#define GIS_CTRL_LCDIF_SEL_SHIFT 2 +#define GIS_CTRL_CSI_SEL_MASK 0x8u +#define GIS_CTRL_CSI_SEL_SHIFT 3 +#define GIS_CTRL_CSI0_IRQ_POLARITY_MASK 0x10u +#define GIS_CTRL_CSI0_IRQ_POLARITY_SHIFT 4 +#define GIS_CTRL_CSI1_IRQ_POLARITY_MASK 0x20u +#define GIS_CTRL_CSI1_IRQ_POLARITY_SHIFT 5 +#define GIS_CTRL_PXP_IRQ_POLARITY_MASK 0x40u +#define GIS_CTRL_PXP_IRQ_POLARITY_SHIFT 6 +#define GIS_CTRL_LCDIF0_IRQ_POLARITY_MASK 0x80u +#define GIS_CTRL_LCDIF0_IRQ_POLARITY_SHIFT 7 +#define GIS_CTRL_LCDIF1_IRQ_POLARITY_MASK 0x100u +#define GIS_CTRL_LCDIF1_IRQ_POLARITY_SHIFT 8 +#define GIS_CTRL_CLKGATE_MASK 0x40000000u +#define GIS_CTRL_CLKGATE_SHIFT 30 +#define GIS_CTRL_SFTRST_MASK 0x80000000u +#define GIS_CTRL_SFTRST_SHIFT 31 +/* CTRL_SET Bit Fields */ +#define GIS_CTRL_SET_ENABLE_MASK 0x1u +#define GIS_CTRL_SET_ENABLE_SHIFT 0 +#define GIS_CTRL_SET_FB_START_MASK 0x2u +#define GIS_CTRL_SET_FB_START_SHIFT 1 +#define GIS_CTRL_SET_LCDIF_SEL_MASK 0x4u +#define GIS_CTRL_SET_LCDIF_SEL_SHIFT 2 +#define GIS_CTRL_SET_CSI_SEL_MASK 0x8u +#define GIS_CTRL_SET_CSI_SEL_SHIFT 3 +#define GIS_CTRL_SET_CSI0_IRQ_POLARITY_MASK 0x10u +#define GIS_CTRL_SET_CSI0_IRQ_POLARITY_SHIFT 4 +#define GIS_CTRL_SET_CSI1_IRQ_POLARITY_MASK 0x20u +#define GIS_CTRL_SET_CSI1_IRQ_POLARITY_SHIFT 5 +#define GIS_CTRL_SET_PXP_IRQ_POLARITY_MASK 0x40u +#define GIS_CTRL_SET_PXP_IRQ_POLARITY_SHIFT 6 +#define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_MASK 0x80u +#define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_SHIFT 7 +#define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_MASK 0x100u +#define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_SHIFT 8 +#define GIS_CTRL_SET_CLKGATE_MASK 0x40000000u +#define GIS_CTRL_SET_CLKGATE_SHIFT 30 +#define GIS_CTRL_SET_SFTRST_MASK 0x80000000u +#define GIS_CTRL_SET_SFTRST_SHIFT 31 +/* CTRL_CLR Bit Fields */ +#define GIS_CTRL_CLR_ENABLE_MASK 0x1u +#define GIS_CTRL_CLR_ENABLE_SHIFT 0 +#define GIS_CTRL_CLR_FB_START_MASK 0x2u +#define GIS_CTRL_CLR_FB_START_SHIFT 1 +#define GIS_CTRL_CLR_LCDIF_SEL_MASK 0x4u +#define GIS_CTRL_CLR_LCDIF_SEL_SHIFT 2 +#define GIS_CTRL_CLR_CSI_SEL_MASK 0x8u +#define GIS_CTRL_CLR_CSI_SEL_SHIFT 3 +#define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_MASK 0x10u +#define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_SHIFT 4 +#define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_MASK 0x20u +#define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_SHIFT 5 +#define GIS_CTRL_CLR_PXP_IRQ_POLARITY_MASK 0x40u +#define GIS_CTRL_CLR_PXP_IRQ_POLARITY_SHIFT 6 +#define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_MASK 0x80u +#define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_SHIFT 7 +#define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_MASK 0x100u +#define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_SHIFT 8 +#define GIS_CTRL_CLR_CLKGATE_MASK 0x40000000u +#define GIS_CTRL_CLR_CLKGATE_SHIFT 30 +#define GIS_CTRL_CLR_SFTRST_MASK 0x80000000u +#define GIS_CTRL_CLR_SFTRST_SHIFT 31 +/* CTRL_TOG Bit Fields */ +#define GIS_CTRL_TOG_ENABLE_MASK 0x1u +#define GIS_CTRL_TOG_ENABLE_SHIFT 0 +#define GIS_CTRL_TOG_FB_START_MASK 0x2u +#define GIS_CTRL_TOG_FB_START_SHIFT 1 +#define GIS_CTRL_TOG_LCDIF_SEL_MASK 0x4u +#define GIS_CTRL_TOG_LCDIF_SEL_SHIFT 2 +#define GIS_CTRL_TOG_CSI_SEL_MASK 0x8u +#define GIS_CTRL_TOG_CSI_SEL_SHIFT 3 +#define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_MASK 0x10u +#define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_SHIFT 4 +#define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_MASK 0x20u +#define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_SHIFT 5 +#define GIS_CTRL_TOG_PXP_IRQ_POLARITY_MASK 0x40u +#define GIS_CTRL_TOG_PXP_IRQ_POLARITY_SHIFT 6 +#define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_MASK 0x80u +#define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_SHIFT 7 +#define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_MASK 0x100u +#define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_SHIFT 8 +#define GIS_CTRL_TOG_CLKGATE_MASK 0x40000000u +#define GIS_CTRL_TOG_CLKGATE_SHIFT 30 +#define GIS_CTRL_TOG_SFTRST_MASK 0x80000000u +#define GIS_CTRL_TOG_SFTRST_SHIFT 31 +/* CONFIG0 Bit Fields */ +#define GIS_CONFIG0_CH0_MAPPING_MASK 0x7u +#define GIS_CONFIG0_CH0_MAPPING_SHIFT 0 +#define GIS_CONFIG0_CH0_MAPPING(x) (((uint32_t)(((uint32_t)(x))<CNTR) +#define GPC_PGR_REG(base) ((base)->PGR) +#define GPC_IMR1_REG(base) ((base)->IMR1) +#define GPC_IMR2_REG(base) ((base)->IMR2) +#define GPC_IMR3_REG(base) ((base)->IMR3) +#define GPC_IMR4_REG(base) ((base)->IMR4) +#define GPC_ISR1_REG(base) ((base)->ISR1) +#define GPC_ISR2_REG(base) ((base)->ISR2) +#define GPC_ISR3_REG(base) ((base)->ISR3) +#define GPC_ISR4_REG(base) ((base)->ISR4) +#define GPC_A9_LPSR_REG(base) ((base)->A9_LPSR) +#define GPC_M4_LPSR_REG(base) ((base)->M4_LPSR) +#define GPC_DR_REG(base) ((base)->DR) + +/*! + * @} + */ /* end of group GPC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/* CNTR Bit Fields */ +#define GPC_CNTR_gpu_vpu_pdn_req_MASK 0x1u +#define GPC_CNTR_gpu_vpu_pdn_req_SHIFT 0 +#define GPC_CNTR_gpu_vpu_pup_req_MASK 0x2u +#define GPC_CNTR_gpu_vpu_pup_req_SHIFT 1 +#define GPC_CNTR_MEGA_PDN_REQ_MASK 0x4u +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT 2 +#define GPC_CNTR_MEGA_PUP_REQ_MASK 0x8u +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT 3 +#define GPC_CNTR_DISPLAY_PDN_REQ_MASK 0x10u +#define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT 4 +#define GPC_CNTR_DISPLAY_PUP_REQ_MASK 0x20u +#define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT 5 +#define GPC_CNTR_PCIE_PHY_PDN_REQ_MASK 0x40u +#define GPC_CNTR_PCIE_PHY_PDN_REQ_SHIFT 6 +#define GPC_CNTR_PCIE_PHY_PUP_REQ_MASK 0x80u +#define GPC_CNTR_PCIE_PHY_PUP_REQ_SHIFT 7 +#define GPC_CNTR_DVFS0CR_MASK 0x10000u +#define GPC_CNTR_DVFS0CR_SHIFT 16 +#define GPC_CNTR_VADC_ANALOG_OFF_MASK 0x20000u +#define GPC_CNTR_VADC_ANALOG_OFF_SHIFT 17 +#define GPC_CNTR_VADC_EXT_PWD_N_MASK 0x40000u +#define GPC_CNTR_VADC_EXT_PWD_N_SHIFT 18 +#define GPC_CNTR_GPCIRQM_MASK 0x200000u +#define GPC_CNTR_GPCIRQM_SHIFT 21 +#define GPC_CNTR_L2_PGE_MASK 0x400000u +#define GPC_CNTR_L2_PGE_SHIFT 22 +/* PGR Bit Fields */ +#define GPC_PGR_DRCIC_MASK 0x60000000u +#define GPC_PGR_DRCIC_SHIFT 29 +#define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x))<DR) +#define GPIO_GDIR_REG(base) ((base)->GDIR) +#define GPIO_PSR_REG(base) ((base)->PSR) +#define GPIO_ICR1_REG(base) ((base)->ICR1) +#define GPIO_ICR2_REG(base) ((base)->ICR2) +#define GPIO_IMR_REG(base) ((base)->IMR) +#define GPIO_ISR_REG(base) ((base)->ISR) +#define GPIO_EDGE_SEL_REG(base) ((base)->EDGE_SEL) + +/*! + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* DR Bit Fields */ +#define GPIO_DR_DR_MASK 0xFFFFFFFFu +#define GPIO_DR_DR_SHIFT 0 +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x))<CTRL0) +#define GPMI_CTRL0_SET_REG(base) ((base)->CTRL0_SET) +#define GPMI_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) +#define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) +#define GPMI_COMPARE_REG(base) ((base)->COMPARE) +#define GPMI_ECCCTRL_REG(base) ((base)->ECCCTRL) +#define GPMI_ECCCTRL_SET_REG(base) ((base)->ECCCTRL_SET) +#define GPMI_ECCCTRL_CLR_REG(base) ((base)->ECCCTRL_CLR) +#define GPMI_ECCCTRL_TOG_REG(base) ((base)->ECCCTRL_TOG) +#define GPMI_ECCCOUNT_REG(base) ((base)->ECCCOUNT) +#define GPMI_PAYLOAD_REG(base) ((base)->PAYLOAD) +#define GPMI_AUXILIARY_REG(base) ((base)->AUXILIARY) +#define GPMI_CTRL1_REG(base) ((base)->CTRL1) +#define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define GPMI_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define GPMI_TIMING0_REG(base) ((base)->TIMING0) +#define GPMI_TIMING1_REG(base) ((base)->TIMING1) +#define GPMI_TIMING2_REG(base) ((base)->TIMING2) +#define GPMI_DATA_REG(base) ((base)->DATA) +#define GPMI_STAT_REG(base) ((base)->STAT) +#define GPMI_DEBUG_REG(base) ((base)->DEBUG) +#define GPMI_VERSION_REG(base) ((base)->VERSION) +#define GPMI_DEBUG2_REG(base) ((base)->DEBUG2) +#define GPMI_DEBUG3_REG(base) ((base)->DEBUG3) +#define GPMI_READ_DDR_DLL_CTRL_REG(base) ((base)->READ_DDR_DLL_CTRL) +#define GPMI_WRITE_DDR_DLL_CTRL_REG(base) ((base)->WRITE_DDR_DLL_CTRL) +#define GPMI_READ_DDR_DLL_STS_REG(base) ((base)->READ_DDR_DLL_STS) +#define GPMI_WRITE_DDR_DLL_STS_REG(base) ((base)->WRITE_DDR_DLL_STS) + +/*! + * @} + */ /* end of group GPMI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/* CTRL0 Bit Fields */ +#define GPMI_CTRL0_XFER_COUNT_MASK 0xFFFFu +#define GPMI_CTRL0_XFER_COUNT_SHIFT 0 +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<CR) +#define GPT_PR_REG(base) ((base)->PR) +#define GPT_SR_REG(base) ((base)->SR) +#define GPT_IR_REG(base) ((base)->IR) +#define GPT_OCR1_REG(base) ((base)->OCR1) +#define GPT_OCR2_REG(base) ((base)->OCR2) +#define GPT_OCR3_REG(base) ((base)->OCR3) +#define GPT_ICR1_REG(base) ((base)->ICR1) +#define GPT_ICR2_REG(base) ((base)->ICR2) +#define GPT_CNT_REG(base) ((base)->CNT) + +/*! + * @} + */ /* end of group GPT_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define GPT_CR_EN_MASK 0x1u +#define GPT_CR_EN_SHIFT 0 +#define GPT_CR_ENMOD_MASK 0x2u +#define GPT_CR_ENMOD_SHIFT 1 +#define GPT_CR_DBGEN_MASK 0x4u +#define GPT_CR_DBGEN_SHIFT 2 +#define GPT_CR_WAITEN_MASK 0x8u +#define GPT_CR_WAITEN_SHIFT 3 +#define GPT_CR_DOZEEN_MASK 0x10u +#define GPT_CR_DOZEEN_SHIFT 4 +#define GPT_CR_STOPEN_MASK 0x20u +#define GPT_CR_STOPEN_SHIFT 5 +#define GPT_CR_CLKSRC_MASK 0x1C0u +#define GPT_CR_CLKSRC_SHIFT 6 +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<IADR) +#define I2C_IFDR_REG(base) ((base)->IFDR) +#define I2C_I2CR_REG(base) ((base)->I2CR) +#define I2C_I2SR_REG(base) ((base)->I2SR) +#define I2C_I2DR_REG(base) ((base)->I2DR) + +/*! + * @} + */ /* end of group I2C_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* IADR Bit Fields */ +#define I2C_IADR_ADR_MASK 0xFEu +#define I2C_IADR_ADR_SHIFT 1 +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x))<TCSR) +#define I2S_TCR1_REG(base) ((base)->TCR1) +#define I2S_TCR2_REG(base) ((base)->TCR2) +#define I2S_TCR3_REG(base) ((base)->TCR3) +#define I2S_TCR4_REG(base) ((base)->TCR4) +#define I2S_TCR5_REG(base) ((base)->TCR5) +#define I2S_TDR_REG(base,index) ((base)->TDR[index]) +#define I2S_TFR_REG(base,index) ((base)->TFR[index]) +#define I2S_TMR_REG(base) ((base)->TMR) +#define I2S_RCSR_REG(base) ((base)->RCSR) +#define I2S_RCR1_REG(base) ((base)->RCR1) +#define I2S_RCR2_REG(base) ((base)->RCR2) +#define I2S_RCR3_REG(base) ((base)->RCR3) +#define I2S_RCR4_REG(base) ((base)->RCR4) +#define I2S_RCR5_REG(base) ((base)->RCR5) +#define I2S_RDR_REG(base,index) ((base)->RDR[index]) +#define I2S_RFR_REG(base,index) ((base)->RFR[index]) +#define I2S_RMR_REG(base) ((base)->RMR) + +/*! + * @} + */ /* end of group I2S_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x1Fu +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO00) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_HSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_MCLK) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_PIXCLK) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_VSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDIO) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_COL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_CRS) +#define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_RX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_TX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL0) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL1) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL2) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL3) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL4) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW0) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW1) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW2) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW3) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW4) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA08) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA09) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA10) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA11) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA12) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA13) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA14) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA15) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA16) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA17) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA18) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA19) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA20) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA21) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA22) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA23) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_ENABLE) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_HSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_RESET) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_VSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_ALE) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE0_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE1_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CLE) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_RE_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_READY_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WE_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WP_B) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DQS) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS0_B) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS1_B) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DQS) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS0_B) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS1_B) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD0) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD1) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD2) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD3) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RXC) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD0) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD1) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD2) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD3) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TXC) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD0) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD1) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD2) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD3) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RXC) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD0) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD1) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD2) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD3) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TXC) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA4) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA5) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA6) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA7) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_STROBE) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR00) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR01) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR02) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR03) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR04) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR05) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR06) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR07) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR08) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR09) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR10) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR11) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR12) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR13) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR14) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR15) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM1) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM2) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM3) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RAS_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CAS_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS0_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS1_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDWE_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT1) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA1) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA2) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE1) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCLK0_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS0_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS1_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS2_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS3_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RESET) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_HSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_MCLK) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_PIXCLK) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_VSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDIO) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_COL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_CRS) +#define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_RX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_TX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL0) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL1) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL2) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL3) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL4) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW0) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW1) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW2) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW3) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW4) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA08) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA09) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA10) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA11) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA12) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA13) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA14) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA15) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA16) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA17) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA18) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA19) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA20) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA21) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA22) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA23) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_ENABLE) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_HSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_RESET) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_VSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_ALE) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE0_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE1_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CLE) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_RE_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_READY_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WE_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WP_B) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DQS) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS0_B) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS1_B) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DQS) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS0_B) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS1_B) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD0) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD1) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD2) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD3) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RXC) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD0) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD1) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD2) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD3) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TXC) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD0) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD1) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD2) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD3) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RXC) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD0) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD1) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD2) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD3) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TXC) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA4) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA5) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA6) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA7) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_STROBE) +#define IOMUXC_SW_PAD_CTL_GRP_ADDDS_REG(base) ((base)->SW_PAD_CTL_GRP_ADDDS) +#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE_CTL) +#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_REG(base) ((base)->SW_PAD_CTL_GRP_DDRPKE) +#define IOMUXC_SW_PAD_CTL_GRP_DDRPK_REG(base) ((base)->SW_PAD_CTL_GRP_DDRPK) +#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_REG(base) ((base)->SW_PAD_CTL_GRP_DDRHYS) +#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE) +#define IOMUXC_SW_PAD_CTL_GRP_B0DS_REG(base) ((base)->SW_PAD_CTL_GRP_B0DS) +#define IOMUXC_SW_PAD_CTL_GRP_B1DS_REG(base) ((base)->SW_PAD_CTL_GRP_B1DS) +#define IOMUXC_SW_PAD_CTL_GRP_CTLDS_REG(base) ((base)->SW_PAD_CTL_GRP_CTLDS) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_REG(base) ((base)->SW_PAD_CTL_GRP_DDR_TYPE) +#define IOMUXC_SW_PAD_CTL_GRP_B2DS_REG(base) ((base)->SW_PAD_CTL_GRP_B2DS) +#define IOMUXC_SW_PAD_CTL_GRP_B3DS_REG(base) ((base)->SW_PAD_CTL_GRP_B3DS) +#define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_OTG_ID_SELECT_INPUT) +#define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_UH1_ID_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT) +#define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN1_IPP_IND_CANRX_SELECT_INPUT) +#define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN2_IPP_IND_CANRX_SELECT_INPUT) +#define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_0) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_1) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_2) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_3) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_4) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_5) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_6) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_7) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_8) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_9) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_11) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_12) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_13) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_14) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_15) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_16) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_17) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_18) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_19) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_20) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_21) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_22) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_23) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_10) +#define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_HSYNC_SELECT_INPUT) +#define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_PIXCLK_SELECT_INPUT) +#define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_VSYNC_SELECT_INPUT) +#define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_REG(base) ((base)->CSI1_TVDECODER_IN_FIELD_SELECT_INPUT) +#define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET1_IPG_CLK_RMII_SELECT_INPUT) +#define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT) +#define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT) +#define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET2_IPG_CLK_RMII_SELECT_INPUT) +#define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT) +#define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FSR_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FST_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKR_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKT_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKR_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKT_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO0_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO1_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT) +#define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SCL_IN_SELECT_INPUT) +#define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SDA_IN_SELECT_INPUT) +#define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SCL_IN_SELECT_INPUT) +#define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SDA_IN_SELECT_INPUT) +#define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SCL_IN_SELECT_INPUT) +#define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SDA_IN_SELECT_INPUT) +#define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SCL_IN_SELECT_INPUT) +#define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SDA_IN_SELECT_INPUT) +#define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_5) +#define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_6) +#define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_7) +#define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_5) +#define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_6) +#define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_7) +#define IOMUXC_LCD1_BUSY_SELECT_INPUT_REG(base) ((base)->LCD1_BUSY_SELECT_INPUT) +#define IOMUXC_LCD2_BUSY_SELECT_INPUT_REG(base) ((base)->LCD2_BUSY_SELECT_INPUT) +#define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_CLK_IN_SELECT_INPUT) +#define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_DATA_IN_SELECT_INPUT) +#define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_SIG_IN_SELECT_INPUT) +#define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT) +#define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0) +#define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT) +#define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT) +#define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT) +#define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT) +#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0) +#define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT) +#define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT) +#define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT) +#define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_14) +#define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_15) +#define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_REG(base) ((base)->SPDIF_SPDIF_IN1_SELECT_INPUT) +#define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_REG(base) ((base)->SPDIF_TX_CLK2_SELECT_INPUT) +#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG2_OC_SELECT_INPUT) +#define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG_OC_SELECT_INPUT) +#define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_CARD_DET_SELECT_INPUT) +#define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_WP_ON_SELECT_INPUT) +#define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_CARD_DET_SELECT_INPUT) +#define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_WP_ON_SELECT_INPUT) +#define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_CARD_DET_SELECT_INPUT) +#define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_WP_ON_SELECT_INPUT) + +/*! + * @} + */ /* end of group IOMUXC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<GPR0) +#define IOMUXC_GPR_GPR1_REG(base) ((base)->GPR1) +#define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2) +#define IOMUXC_GPR_GPR3_REG(base) ((base)->GPR3) +#define IOMUXC_GPR_GPR4_REG(base) ((base)->GPR4) +#define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5) +#define IOMUXC_GPR_GPR6_REG(base) ((base)->GPR6) +#define IOMUXC_GPR_GPR7_REG(base) ((base)->GPR7) +#define IOMUXC_GPR_GPR8_REG(base) ((base)->GPR8) +#define IOMUXC_GPR_GPR9_REG(base) ((base)->GPR9) +#define IOMUXC_GPR_GPR10_REG(base) ((base)->GPR10) +#define IOMUXC_GPR_GPR11_REG(base) ((base)->GPR11) +#define IOMUXC_GPR_GPR12_REG(base) ((base)->GPR12) +#define IOMUXC_GPR_GPR13_REG(base) ((base)->GPR13) + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/* GPR0 Bit Fields */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK 0x80u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT 7 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK 0x100u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT 8 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK 0x200u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT 9 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK 0x400u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT 10 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK 0x800u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT 11 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK 0x1000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT 12 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK 0x2000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT 13 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK 0x4000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT 14 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK 0x8000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT 15 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK 0x10000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT 16 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK 0x20000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT 17 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK 0x40000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT 18 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK 0x80000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT 19 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK 0x100000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT 20 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK 0x200000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT 21 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK 0x400000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT 22 +/* GPR1 Bit Fields */ +#define IOMUXC_GPR_GPR1_ACT_CS0_MASK 0x1u +#define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT 0 +#define IOMUXC_GPR_GPR1_ADDRS0_MASK 0x6u +#define IOMUXC_GPR_GPR1_ADDRS0_SHIFT 1 +#define IOMUXC_GPR_GPR1_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<KPCR) +#define KPP_KPSR_REG(base) ((base)->KPSR) +#define KPP_KDDR_REG(base) ((base)->KDDR) +#define KPP_KPDR_REG(base) ((base)->KPDR) + +/*! + * @} + */ /* end of group KPP_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/* KPCR Bit Fields */ +#define KPP_KPCR_KRE_MASK 0xFFu +#define KPP_KPCR_KRE_SHIFT 0 +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x))<RL) +#define LCDIF_RL_SET_REG(base) ((base)->RL_SET) +#define LCDIF_RL_CLR_REG(base) ((base)->RL_CLR) +#define LCDIF_RL_TOG_REG(base) ((base)->RL_TOG) +#define LCDIF_CTRL1_REG(base) ((base)->CTRL1) +#define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define LCDIF_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define LCDIF_CTRL2_REG(base) ((base)->CTRL2) +#define LCDIF_CTRL2_SET_REG(base) ((base)->CTRL2_SET) +#define LCDIF_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) +#define LCDIF_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) +#define LCDIF_TRANSFER_COUNT_REG(base) ((base)->TRANSFER_COUNT) +#define LCDIF_CUR_BUF_REG(base) ((base)->CUR_BUF) +#define LCDIF_NEXT_BUF_REG(base) ((base)->NEXT_BUF) +#define LCDIF_TIMING_REG(base) ((base)->TIMING) +#define LCDIF_VDCTRL0_REG(base) ((base)->VDCTRL0) +#define LCDIF_VDCTRL0_SET_REG(base) ((base)->VDCTRL0_SET) +#define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR) +#define LCDIF_VDCTRL0_TOG_REG(base) ((base)->VDCTRL0_TOG) +#define LCDIF_VDCTRL1_REG(base) ((base)->VDCTRL1) +#define LCDIF_VDCTRL2_REG(base) ((base)->VDCTRL2) +#define LCDIF_VDCTRL3_REG(base) ((base)->VDCTRL3) +#define LCDIF_VDCTRL4_REG(base) ((base)->VDCTRL4) +#define LCDIF_DVICTRL0_REG(base) ((base)->DVICTRL0) +#define LCDIF_DVICTRL1_REG(base) ((base)->DVICTRL1) +#define LCDIF_DVICTRL2_REG(base) ((base)->DVICTRL2) +#define LCDIF_DVICTRL3_REG(base) ((base)->DVICTRL3) +#define LCDIF_DVICTRL4_REG(base) ((base)->DVICTRL4) +#define LCDIF_CSC_COEFF0_REG(base) ((base)->CSC_COEFF0) +#define LCDIF_CSC_COEFF1_REG(base) ((base)->CSC_COEFF1) +#define LCDIF_CSC_COEFF2_REG(base) ((base)->CSC_COEFF2) +#define LCDIF_CSC_COEFF3_REG(base) ((base)->CSC_COEFF3) +#define LCDIF_CSC_COEFF4_REG(base) ((base)->CSC_COEFF4) +#define LCDIF_CSC_OFFSET_REG(base) ((base)->CSC_OFFSET) +#define LCDIF_CSC_LIMIT_REG(base) ((base)->CSC_LIMIT) +#define LCDIF_DATA_REG(base) ((base)->DATA) +#define LCDIF_BM_ERROR_STAT_REG(base) ((base)->BM_ERROR_STAT) +#define LCDIF_CRC_STAT_REG(base) ((base)->CRC_STAT) +#define LCDIF_STAT_REG(base) ((base)->STAT) +#define LCDIF_VERSION_REG(base) ((base)->VERSION) +#define LCDIF_DEBUG0_REG(base) ((base)->DEBUG0) +#define LCDIF_DEBUG1_REG(base) ((base)->DEBUG1) +#define LCDIF_DEBUG2_REG(base) ((base)->DEBUG2) +#define LCDIF_THRES_REG(base) ((base)->THRES) +#define LCDIF_AS_CTRL_REG(base) ((base)->AS_CTRL) +#define LCDIF_AS_BUF_REG(base) ((base)->AS_BUF) +#define LCDIF_AS_NEXT_BUF_REG(base) ((base)->AS_NEXT_BUF) +#define LCDIF_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) +#define LCDIF_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) +#define LCDIF_SYNC_DELAY_REG(base) ((base)->SYNC_DELAY) +#define LCDIF_DEBUG3_REG(base) ((base)->DEBUG3) +#define LCDIF_DEBUG4_REG(base) ((base)->DEBUG4) +#define LCDIF_DEBUG5_REG(base) ((base)->DEBUG5) + +/*! + * @} + */ /* end of group LCDIF_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/* RL Bit Fields */ +#define LCDIF_RL_RUN_MASK 0x1u +#define LCDIF_RL_RUN_SHIFT 0 +#define LCDIF_RL_DATA_FORMAT_24_BIT_MASK 0x2u +#define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT 1 +#define LCDIF_RL_DATA_FORMAT_18_BIT_MASK 0x4u +#define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT 2 +#define LCDIF_RL_DATA_FORMAT_16_BIT_MASK 0x8u +#define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT 3 +#define LCDIF_RL_RSRVD0_MASK 0x10u +#define LCDIF_RL_RSRVD0_SHIFT 4 +#define LCDIF_RL_MASTER_MASK 0x20u +#define LCDIF_RL_MASTER_SHIFT 5 +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK 0x40u +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT 6 +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK 0x80u +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT 7 +#define LCDIF_RL_WORD_LENGTH_MASK 0x300u +#define LCDIF_RL_WORD_LENGTH_SHIFT 8 +#define LCDIF_RL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<CTRL) + +/*! + * @} + */ /* end of group LDB_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- LDB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LDB_Register_Masks LDB Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define LDB_CTRL_ch0_mode_MASK 0x3u +#define LDB_CTRL_ch0_mode_SHIFT 0 +#define LDB_CTRL_ch0_mode(x) (((uint32_t)(((uint32_t)(x))<PCCCR) +#define LMEM_PCCLCR_REG(base) ((base)->PCCLCR) +#define LMEM_PCCSAR_REG(base) ((base)->PCCSAR) +#define LMEM_PCCCVR_REG(base) ((base)->PCCCVR) +#define LMEM_PSCCR_REG(base) ((base)->PSCCR) +#define LMEM_PSCLCR_REG(base) ((base)->PSCLCR) +#define LMEM_PSCSAR_REG(base) ((base)->PSCSAR) +#define LMEM_PSCCVR_REG(base) ((base)->PSCCVR) + +/*! + * @} + */ /* end of group LMEM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- LMEM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Masks LMEM Register Masks + * @{ + */ + +/* PCCCR Bit Fields */ +#define LMEM_PCCCR_ENCACHE_MASK 0x1u +#define LMEM_PCCCR_ENCACHE_SHIFT 0 +#define LMEM_PCCCR_ENWRBUF_MASK 0x2u +#define LMEM_PCCCR_ENWRBUF_SHIFT 1 +#define LMEM_PCCCR_PCCR2_MASK 0x4u +#define LMEM_PCCCR_PCCR2_SHIFT 2 +#define LMEM_PCCCR_PCCR3_MASK 0x8u +#define LMEM_PCCCR_PCCR3_SHIFT 3 +#define LMEM_PCCCR_INVW0_MASK 0x1000000u +#define LMEM_PCCCR_INVW0_SHIFT 24 +#define LMEM_PCCCR_PUSHW0_MASK 0x2000000u +#define LMEM_PCCCR_PUSHW0_SHIFT 25 +#define LMEM_PCCCR_INVW1_MASK 0x4000000u +#define LMEM_PCCCR_INVW1_SHIFT 26 +#define LMEM_PCCCR_PUSHW1_MASK 0x8000000u +#define LMEM_PCCCR_PUSHW1_SHIFT 27 +#define LMEM_PCCCR_GO_MASK 0x80000000u +#define LMEM_PCCCR_GO_SHIFT 31 +/* PCCLCR Bit Fields */ +#define LMEM_PCCLCR_LGO_MASK 0x1u +#define LMEM_PCCLCR_LGO_SHIFT 0 +#define LMEM_PCCLCR_CACHEADDR_MASK 0x1FFCu +#define LMEM_PCCLCR_CACHEADDR_SHIFT 2 +#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<PLASC) +#define MCM_PLAMC_REG(base) ((base)->PLAMC) +#define MCM_FADR_REG(base) ((base)->FADR) +#define MCM_FATR_REG(base) ((base)->FATR) +#define MCM_FDR_REG(base) ((base)->FDR) + +/*! + * @} + */ /* end of group MCM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/* PLASC Bit Fields */ +#define MCM_PLASC_ASC_MASK 0xFFu +#define MCM_PLASC_ASC_SHIFT 0 +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<MLBC0) +#define MLB_MS0_REG(base) ((base)->MS0) +#define MLB_MLBPC2_REG(base) ((base)->MLBPC2.MLBPC2) +#define MLB_MS1_REG(base) ((base)->MS1) +#define MLB_MSS_REG(base) ((base)->MSS) +#define MLB_MSD_REG(base) ((base)->MSD) +#define MLB_MIEN_REG(base) ((base)->MIEN) +#define MLB_MLBC1_REG(base) ((base)->MLBC1) +#define MLB_HCTL_REG(base) ((base)->HCTL) +#define MLB_HCMR0_REG(base) ((base)->HCMR0) +#define MLB_HCMR1_REG(base) ((base)->HCMR1) +#define MLB_HCER0_REG(base) ((base)->HCER0) +#define MLB_HCER1_REG(base) ((base)->HCER1) +#define MLB_HCBR0_REG(base) ((base)->HCBR0) +#define MLB_HCBR1_REG(base) ((base)->HCBR1) +#define MLB_MDAT0_REG(base) ((base)->MDAT0) +#define MLB_MDAT1_REG(base) ((base)->MDAT1) +#define MLB_MDAT2_REG(base) ((base)->MDAT2) +#define MLB_MDAT3_REG(base) ((base)->MDAT3) +#define MLB_MDWE0_REG(base) ((base)->MDWE0) +#define MLB_MDWE1_REG(base) ((base)->MDWE1) +#define MLB_MDWE2_REG(base) ((base)->MDWE2) +#define MLB_MDWE3_REG(base) ((base)->MDWE3) +#define MLB_MCTL_REG(base) ((base)->MCTL) +#define MLB_MADR_REG(base) ((base)->MADR) +#define MLB_ACTL_REG(base) ((base)->ACTL) +#define MLB_ACSR0_REG(base) ((base)->ACSR0) +#define MLB_ACSR1_REG(base) ((base)->ACSR1) +#define MLB_ACMR0_REG(base) ((base)->ACMR0) +#define MLB_ACMR1_REG(base) ((base)->ACMR1) + +/*! + * @} + */ /* end of group MLB_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- MLB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MLB_Register_Masks MLB Register Masks + * @{ + */ + +/* MLBC0 Bit Fields */ +#define MLB_MLBC0_MLBEN_MASK 0x1u +#define MLB_MLBC0_MLBEN_SHIFT 0 +#define MLB_MLBC0_MLBCLK_2_0_MASK 0x1Cu +#define MLB_MLBC0_MLBCLK_2_0_SHIFT 2 +#define MLB_MLBC0_MLBCLK_2_0(x) (((uint32_t)(((uint32_t)(x))<MDCTL) +#define MMDC_MDPDC_REG(base) ((base)->MDPDC) +#define MMDC_MDOTC_REG(base) ((base)->MDOTC) +#define MMDC_MDCFG0_REG(base) ((base)->MDCFG0) +#define MMDC_MDCFG1_REG(base) ((base)->MDCFG1) +#define MMDC_MDCFG2_REG(base) ((base)->MDCFG2) +#define MMDC_MDMISC_REG(base) ((base)->MDMISC) +#define MMDC_MDSCR_REG(base) ((base)->MDSCR) +#define MMDC_MDREF_REG(base) ((base)->MDREF) +#define MMDC_MDRWD_REG(base) ((base)->MDRWD) +#define MMDC_MDOR_REG(base) ((base)->MDOR) +#define MMDC_MDMRR_REG(base) ((base)->MDMRR) +#define MMDC_MDCFG3LP_REG(base) ((base)->MDCFG3LP) +#define MMDC_MDMR4_REG(base) ((base)->MDMR4) +#define MMDC_MDASP_REG(base) ((base)->MDASP) +#define MMDC_MAARCR_REG(base) ((base)->MAARCR) +#define MMDC_MAPSR_REG(base) ((base)->MAPSR) +#define MMDC_MAEXIDR0_REG(base) ((base)->MAEXIDR0) +#define MMDC_MAEXIDR1_REG(base) ((base)->MAEXIDR1) +#define MMDC_MADPCR0_REG(base) ((base)->MADPCR0) +#define MMDC_MADPCR1_REG(base) ((base)->MADPCR1) +#define MMDC_MADPSR0_REG(base) ((base)->MADPSR0) +#define MMDC_MADPSR1_REG(base) ((base)->MADPSR1) +#define MMDC_MADPSR2_REG(base) ((base)->MADPSR2) +#define MMDC_MADPSR3_REG(base) ((base)->MADPSR3) +#define MMDC_MADPSR4_REG(base) ((base)->MADPSR4) +#define MMDC_MADPSR5_REG(base) ((base)->MADPSR5) +#define MMDC_MASBS0_REG(base) ((base)->MASBS0) +#define MMDC_MASBS1_REG(base) ((base)->MASBS1) +#define MMDC_MAGENP_REG(base) ((base)->MAGENP) +#define MMDC_MPZQHWCTRL_REG(base) ((base)->MPZQHWCTRL) +#define MMDC_MPZQSWCTRL_REG(base) ((base)->MPZQSWCTRL) +#define MMDC_MPWLGCR_REG(base) ((base)->MPWLGCR) +#define MMDC_MPWLDECTRL0_REG(base) ((base)->MPWLDECTRL0) +#define MMDC_MPWLDECTRL1_REG(base) ((base)->MPWLDECTRL1) +#define MMDC_MPWLDLST_REG(base) ((base)->MPWLDLST) +#define MMDC_MPODTCTRL_REG(base) ((base)->MPODTCTRL) +#define MMDC_MPRDDQBY0DL_REG(base) ((base)->MPRDDQBY0DL) +#define MMDC_MPRDDQBY1DL_REG(base) ((base)->MPRDDQBY1DL) +#define MMDC_MPRDDQBY2DL_REG(base) ((base)->MPRDDQBY2DL) +#define MMDC_MPRDDQBY3DL_REG(base) ((base)->MPRDDQBY3DL) +#define MMDC_MPWRDQBY0DL_REG(base) ((base)->MPWRDQBY0DL) +#define MMDC_MPWRDQBY1DL_REG(base) ((base)->MPWRDQBY1DL) +#define MMDC_MPWRDQBY2DL_REG(base) ((base)->MPWRDQBY2DL) +#define MMDC_MPWRDQBY3DL_REG(base) ((base)->MPWRDQBY3DL) +#define MMDC_MPDGCTRL0_REG(base) ((base)->MPDGCTRL0) +#define MMDC_MPDGCTRL1_REG(base) ((base)->MPDGCTRL1) +#define MMDC_MPDGDLST0_REG(base) ((base)->MPDGDLST0) +#define MMDC_MPRDDLCTL_REG(base) ((base)->MPRDDLCTL) +#define MMDC_MPRDDLST_REG(base) ((base)->MPRDDLST) +#define MMDC_MPWRDLCTL_REG(base) ((base)->MPWRDLCTL) +#define MMDC_MPWRDLST_REG(base) ((base)->MPWRDLST) +#define MMDC_MPSDCTRL_REG(base) ((base)->MPSDCTRL) +#define MMDC_MPZQLP2CTL_REG(base) ((base)->MPZQLP2CTL) +#define MMDC_MPRDDLHWCTL_REG(base) ((base)->MPRDDLHWCTL) +#define MMDC_MPWRDLHWCTL_REG(base) ((base)->MPWRDLHWCTL) +#define MMDC_MPRDDLHWST0_REG(base) ((base)->MPRDDLHWST0) +#define MMDC_MPRDDLHWST1_REG(base) ((base)->MPRDDLHWST1) +#define MMDC_MPWRDLHWST0_REG(base) ((base)->MPWRDLHWST0) +#define MMDC_MPWRDLHWST1_REG(base) ((base)->MPWRDLHWST1) +#define MMDC_MPWLHWERR_REG(base) ((base)->MPWLHWERR) +#define MMDC_MPDGHWST0_REG(base) ((base)->MPDGHWST0) +#define MMDC_MPDGHWST1_REG(base) ((base)->MPDGHWST1) +#define MMDC_MPDGHWST2_REG(base) ((base)->MPDGHWST2) +#define MMDC_MPDGHWST3_REG(base) ((base)->MPDGHWST3) +#define MMDC_MPPDCMPR1_REG(base) ((base)->MPPDCMPR1) +#define MMDC_MPPDCMPR2_REG(base) ((base)->MPPDCMPR2) +#define MMDC_MPSWDAR0_REG(base) ((base)->MPSWDAR0) +#define MMDC_MPSWDRDR0_REG(base) ((base)->MPSWDRDR0) +#define MMDC_MPSWDRDR1_REG(base) ((base)->MPSWDRDR1) +#define MMDC_MPSWDRDR2_REG(base) ((base)->MPSWDRDR2) +#define MMDC_MPSWDRDR3_REG(base) ((base)->MPSWDRDR3) +#define MMDC_MPSWDRDR4_REG(base) ((base)->MPSWDRDR4) +#define MMDC_MPSWDRDR5_REG(base) ((base)->MPSWDRDR5) +#define MMDC_MPSWDRDR6_REG(base) ((base)->MPSWDRDR6) +#define MMDC_MPSWDRDR7_REG(base) ((base)->MPSWDRDR7) +#define MMDC_MPMUR0_REG(base) ((base)->MPMUR0) +#define MMDC_MPWRCADL_REG(base) ((base)->MPWRCADL) +#define MMDC_MPDCCR_REG(base) ((base)->MPDCCR) + +/*! + * @} + */ /* end of group MMDC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- MMDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Register_Masks MMDC Register Masks + * @{ + */ + +/* MDCTL Bit Fields */ +#define MMDC_MDCTL_DSIZ_MASK 0x30000u +#define MMDC_MDCTL_DSIZ_SHIFT 16 +#define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x))<TR[index]) +#define MU_TR_COUNT 4 +#define MU_RR_REG(base,index) ((base)->RR[index]) +#define MU_RR_COUNT 4 +#define MU_SR_REG(base) ((base)->SR) +#define MU_CR_REG(base) ((base)->CR) + +/*! + * @} + */ /* end of group MU_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/* TR Bit Fields */ +#define MU_TR_TR0_MASK 0xFFFFFFFFu +#define MU_TR_TR0_SHIFT 0 +#define MU_TR_TR0(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define OCOTP_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define OCOTP_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define OCOTP_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define OCOTP_TIMING_REG(base) ((base)->TIMING) +#define OCOTP_DATA_REG(base) ((base)->DATA) +#define OCOTP_READ_CTRL_REG(base) ((base)->READ_CTRL) +#define OCOTP_READ_FUSE_DATA_REG(base) ((base)->READ_FUSE_DATA) +#define OCOTP_SW_STICKY_REG(base) ((base)->SW_STICKY) +#define OCOTP_SCS_REG(base) ((base)->SCS) +#define OCOTP_SCS_SET_REG(base) ((base)->SCS_SET) +#define OCOTP_SCS_CLR_REG(base) ((base)->SCS_CLR) +#define OCOTP_SCS_TOG_REG(base) ((base)->SCS_TOG) +#define OCOTP_VERSION_REG(base) ((base)->VERSION) +#define OCOTP_LOCK_REG(base) ((base)->LOCK) +#define OCOTP_CFG0_REG(base) ((base)->CFG0) +#define OCOTP_CFG1_REG(base) ((base)->CFG1) +#define OCOTP_CFG2_REG(base) ((base)->CFG2) +#define OCOTP_CFG3_REG(base) ((base)->CFG3) +#define OCOTP_CFG4_REG(base) ((base)->CFG4) +#define OCOTP_CFG5_REG(base) ((base)->CFG5) +#define OCOTP_CFG6_REG(base) ((base)->CFG6) +#define OCOTP_MEM0_REG(base) ((base)->MEM0) +#define OCOTP_MEM1_REG(base) ((base)->MEM1) +#define OCOTP_MEM2_REG(base) ((base)->MEM2) +#define OCOTP_MEM3_REG(base) ((base)->MEM3) +#define OCOTP_MEM4_REG(base) ((base)->MEM4) +#define OCOTP_ANA0_REG(base) ((base)->ANA0) +#define OCOTP_ANA1_REG(base) ((base)->ANA1) +#define OCOTP_ANA2_REG(base) ((base)->ANA2) +#define OCOTP_SRK0_REG(base) ((base)->SRK0) +#define OCOTP_SRK1_REG(base) ((base)->SRK1) +#define OCOTP_SRK2_REG(base) ((base)->SRK2) +#define OCOTP_SRK3_REG(base) ((base)->SRK3) +#define OCOTP_SRK4_REG(base) ((base)->SRK4) +#define OCOTP_SRK5_REG(base) ((base)->SRK5) +#define OCOTP_SRK6_REG(base) ((base)->SRK6) +#define OCOTP_SRK7_REG(base) ((base)->SRK7) +#define OCOTP_RESP0_REG(base) ((base)->RESP0) +#define OCOTP_HSJC_RESP1_REG(base) ((base)->HSJC_RESP1) +#define OCOTP_MAC0_REG(base) ((base)->MAC0) +#define OCOTP_MAC1_REG(base) ((base)->MAC1) +#define OCOTP_MAC2_REG(base) ((base)->MAC2) +#define OCOTP_GP1_REG(base) ((base)->GP1) +#define OCOTP_GP2_REG(base) ((base)->GP2) +#define OCOTP_MISC_CONF_REG(base) ((base)->MISC_CONF) +#define OCOTP_FIELD_RETURN_REG(base) ((base)->FIELD_RETURN) +#define OCOTP_SRK_REVOKE_REG(base) ((base)->SRK_REVOKE) +#define OCOTP_GP30_REG(base) ((base)->GP30) +#define OCOTP_GP31_REG(base) ((base)->GP31) +#define OCOTP_GP32_REG(base) ((base)->GP32) +#define OCOTP_GP33_REG(base) ((base)->GP33) +#define OCOTP_GP34_REG(base) ((base)->GP34) +#define OCOTP_GP35_REG(base) ((base)->GP35) +#define OCOTP_GP36_REG(base) ((base)->GP36) + +/*! + * @} + */ /* end of group OCOTP_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define OCOTP_CTRL_ADDR_MASK 0x7Fu +#define OCOTP_CTRL_ADDR_SHIFT 0 +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<PCIE_PHY_CTRL) +#define PGC_PCIE_PHY_PUPSCR_REG(base) ((base)->PCIE_PHY_PUPSCR) +#define PGC_PCIE_PHY_PDNSCR_REG(base) ((base)->PCIE_PHY_PDNSCR) +#define PGC_PCIE_PHY_SR_REG(base) ((base)->PCIE_PHY_SR) +#define PGC_MEGA_CTRL_REG(base) ((base)->MEGA_CTRL) +#define PGC_MEGA_PUPSCR_REG(base) ((base)->MEGA_PUPSCR) +#define PGC_MEGA_PDNSCR_REG(base) ((base)->MEGA_PDNSCR) +#define PGC_MEGA_SR_REG(base) ((base)->MEGA_SR) +#define PGC_DISPLAY_CTRL_REG(base) ((base)->DISPLAY_CTRL) +#define PGC_DISPLAY_PUPSCR_REG(base) ((base)->DISPLAY_PUPSCR) +#define PGC_DISPLAY_PDNSCR_REG(base) ((base)->DISPLAY_PDNSCR) +#define PGC_DISPLAY_SR_REG(base) ((base)->DISPLAY_SR) +#define PGC_GPU_CTRL_REG(base) ((base)->GPU_CTRL) +#define PGC_GPU_PUPSCR_REG(base) ((base)->GPU_PUPSCR) +#define PGC_GPU_PDNSCR_REG(base) ((base)->GPU_PDNSCR) +#define PGC_GPU_SR_REG(base) ((base)->GPU_SR) +#define PGC_CPU_CTRL_REG(base) ((base)->CPU_CTRL) +#define PGC_CPU_PUPSCR_REG(base) ((base)->CPU_PUPSCR) +#define PGC_CPU_PDNSCR_REG(base) ((base)->CPU_PDNSCR) +#define PGC_CPU_SR_REG(base) ((base)->CPU_SR) + +/*! + * @} + */ /* end of group PGC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/* PCIE_PHY_CTRL Bit Fields */ +#define PGC_PCIE_PHY_CTRL_PCR_MASK 0x1u +#define PGC_PCIE_PHY_CTRL_PCR_SHIFT 0 +/* PCIE_PHY_PUPSCR Bit Fields */ +#define PGC_PCIE_PHY_PUPSCR_SW_MASK 0x3Fu +#define PGC_PCIE_PHY_PUPSCR_SW_SHIFT 0 +#define PGC_PCIE_PHY_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<REG_1P1) +#define PMU_REG_3P0_REG(base) ((base)->REG_3P0) +#define PMU_REG_2P5_REG(base) ((base)->REG_2P5) +#define PMU_REG_CORE_REG(base) ((base)->REG_CORE) +#define PMU_MISC0_REG(base) ((base)->MISC0) +#define PMU_MISC1_REG(base) ((base)->MISC1) +#define PMU_MISC1_SET_REG(base) ((base)->MISC1_SET) +#define PMU_MISC1_CLR_REG(base) ((base)->MISC1_CLR) +#define PMU_MISC1_TOG_REG(base) ((base)->MISC1_TOG) +#define PMU_MISC2_REG(base) ((base)->MISC2) +#define PMU_MISC2_SET_REG(base) ((base)->MISC2_SET) +#define PMU_MISC2_CLR_REG(base) ((base)->MISC2_CLR) +#define PMU_MISC2_TOG_REG(base) ((base)->MISC2_TOG) +#define PMU_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) +#define PMU_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) +#define PMU_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) + +/*! + * @} + */ /* end of group PMU_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/* REG_1P1 Bit Fields */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P1_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P1_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P1_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P1_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<PWMCR) +#define PWM_PWMSR_REG(base) ((base)->PWMSR) +#define PWM_PWMIR_REG(base) ((base)->PWMIR) +#define PWM_PWMSAR_REG(base) ((base)->PWMSAR) +#define PWM_PWMPR_REG(base) ((base)->PWMPR) +#define PWM_PWMCNR_REG(base) ((base)->PWMCNR) + +/*! + * @} + */ /* end of group PWM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/* PWMCR Bit Fields */ +#define PWM_PWMCR_EN_MASK 0x1u +#define PWM_PWMCR_EN_SHIFT 0 +#define PWM_PWMCR_REPEAT_MASK 0x6u +#define PWM_PWMCR_REPEAT_SHIFT 1 +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define PXP_STAT_REG(base) ((base)->STAT) +#define PXP_OUT_CTRL_REG(base) ((base)->OUT_CTRL) +#define PXP_OUT_BUF_REG(base) ((base)->OUT_BUF) +#define PXP_OUT_BUF2_REG(base) ((base)->OUT_BUF2) +#define PXP_OUT_PITCH_REG(base) ((base)->OUT_PITCH) +#define PXP_OUT_LRC_REG(base) ((base)->OUT_LRC) +#define PXP_OUT_PS_ULC_REG(base) ((base)->OUT_PS_ULC) +#define PXP_OUT_PS_LRC_REG(base) ((base)->OUT_PS_LRC) +#define PXP_OUT_AS_ULC_REG(base) ((base)->OUT_AS_ULC) +#define PXP_OUT_AS_LRC_REG(base) ((base)->OUT_AS_LRC) +#define PXP_PS_CTRL_REG(base) ((base)->PS_CTRL) +#define PXP_PS_BUF_REG(base) ((base)->PS_BUF) +#define PXP_PS_UBUF_REG(base) ((base)->PS_UBUF) +#define PXP_PS_VBUF_REG(base) ((base)->PS_VBUF) +#define PXP_PS_PITCH_REG(base) ((base)->PS_PITCH) +#define PXP_PS_BACKGROUND_REG(base) ((base)->PS_BACKGROUND) +#define PXP_PS_SCALE_REG(base) ((base)->PS_SCALE) +#define PXP_PS_OFFSET_REG(base) ((base)->PS_OFFSET) +#define PXP_PS_CLRKEYLOW_REG(base) ((base)->PS_CLRKEYLOW) +#define PXP_PS_CLRKEYHIGH_REG(base) ((base)->PS_CLRKEYHIGH) +#define PXP_AS_CTRL_REG(base) ((base)->AS_CTRL) +#define PXP_AS_BUF_REG(base) ((base)->AS_BUF) +#define PXP_AS_PITCH_REG(base) ((base)->AS_PITCH) +#define PXP_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) +#define PXP_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) +#define PXP_CSC1_COEF0_REG(base) ((base)->CSC1_COEF0) +#define PXP_CSC1_COEF1_REG(base) ((base)->CSC1_COEF1) +#define PXP_CSC1_COEF2_REG(base) ((base)->CSC1_COEF2) +#define PXP_CSC2_CTRL_REG(base) ((base)->CSC2_CTRL) +#define PXP_CSC2_COEF0_REG(base) ((base)->CSC2_COEF0) +#define PXP_CSC2_COEF1_REG(base) ((base)->CSC2_COEF1) +#define PXP_CSC2_COEF2_REG(base) ((base)->CSC2_COEF2) +#define PXP_CSC2_COEF3_REG(base) ((base)->CSC2_COEF3) +#define PXP_CSC2_COEF4_REG(base) ((base)->CSC2_COEF4) +#define PXP_CSC2_COEF5_REG(base) ((base)->CSC2_COEF5) +#define PXP_LUT_CTRL_REG(base) ((base)->LUT_CTRL) +#define PXP_LUT_ADDR_REG(base) ((base)->LUT_ADDR) +#define PXP_LUT_DATA_REG(base) ((base)->LUT_DATA) +#define PXP_LUT_EXTMEM_REG(base) ((base)->LUT_EXTMEM) +#define PXP_CFA_REG(base) ((base)->CFA) +#define PXP_HIST_CTRL_REG(base) ((base)->HIST_CTRL) +#define PXP_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) +#define PXP_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) +#define PXP_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) +#define PXP_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) +#define PXP_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) +#define PXP_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) +#define PXP_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) +#define PXP_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) +#define PXP_POWER_REG(base) ((base)->POWER) +#define PXP_NEXT_REG(base) ((base)->NEXT) + +/*! + * @} + */ /* end of group PXP_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define PXP_CTRL_ENABLE_MASK 0x1u +#define PXP_CTRL_ENABLE_SHIFT 0 +#define PXP_CTRL_IRQ_ENABLE_MASK 0x2u +#define PXP_CTRL_IRQ_ENABLE_SHIFT 1 +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK 0x10u +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT 4 +#define PXP_CTRL_RSVD0_MASK 0xE0u +#define PXP_CTRL_RSVD0_SHIFT 5 +#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define QuadSPI_IPCR_REG(base) ((base)->IPCR) +#define QuadSPI_FLSHCR_REG(base) ((base)->FLSHCR) +#define QuadSPI_BUF0CR_REG(base) ((base)->BUF0CR) +#define QuadSPI_BUF1CR_REG(base) ((base)->BUF1CR) +#define QuadSPI_BUF2CR_REG(base) ((base)->BUF2CR) +#define QuadSPI_BUF3CR_REG(base) ((base)->BUF3CR) +#define QuadSPI_BFGENCR_REG(base) ((base)->BFGENCR) +#define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND) +#define QuadSPI_BUF1IND_REG(base) ((base)->BUF1IND) +#define QuadSPI_BUF2IND_REG(base) ((base)->BUF2IND) +#define QuadSPI_SFAR_REG(base) ((base)->SFAR) +#define QuadSPI_SMPR_REG(base) ((base)->SMPR) +#define QuadSPI_RBSR_REG(base) ((base)->RBSR) +#define QuadSPI_RBCT_REG(base) ((base)->RBCT) +#define QuadSPI_TBSR_REG(base) ((base)->TBSR) +#define QuadSPI_TBDR_REG(base) ((base)->TBDR) +#define QuadSPI_SR_REG(base) ((base)->SR) +#define QuadSPI_FR_REG(base) ((base)->FR) +#define QuadSPI_RSER_REG(base) ((base)->RSER) +#define QuadSPI_SPNDST_REG(base) ((base)->SPNDST) +#define QuadSPI_SPTRCLR_REG(base) ((base)->SPTRCLR) +#define QuadSPI_SFA1AD_REG(base) ((base)->SFA1AD) +#define QuadSPI_SFA2AD_REG(base) ((base)->SFA2AD) +#define QuadSPI_SFB1AD_REG(base) ((base)->SFB1AD) +#define QuadSPI_SFB2AD_REG(base) ((base)->SFB2AD) +#define QuadSPI_RBDR_REG(base,index) ((base)->RBDR[index]) +#define QuadSPI_LUTKEY_REG(base) ((base)->LUTKEY) +#define QuadSPI_LCKCR_REG(base) ((base)->LCKCR) +#define QuadSPI_LUT_REG(base,index) ((base)->LUT[index]) + +/*! + * @} + */ /* end of group QuadSPI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define QuadSPI_MCR_SWRSTSD_MASK 0x1u +#define QuadSPI_MCR_SWRSTSD_SHIFT 0 +#define QuadSPI_MCR_SWRSTHD_MASK 0x2u +#define QuadSPI_MCR_SWRSTHD_SHIFT 1 +#define QuadSPI_MCR_DQS_EN_MASK 0x40u +#define QuadSPI_MCR_DQS_EN_SHIFT 6 +#define QuadSPI_MCR_DDR_EN_MASK 0x80u +#define QuadSPI_MCR_DDR_EN_SHIFT 7 +#define QuadSPI_MCR_CLR_RXF_MASK 0x400u +#define QuadSPI_MCR_CLR_RXF_SHIFT 10 +#define QuadSPI_MCR_CLR_TXF_MASK 0x800u +#define QuadSPI_MCR_CLR_TXF_SHIFT 11 +#define QuadSPI_MCR_MDIS_MASK 0x4000u +#define QuadSPI_MCR_MDIS_SHIFT 14 +#define QuadSPI_MCR_SCLKCFG_MASK 0xFF000000u +#define QuadSPI_MCR_SCLKCFG_SHIFT 24 +#define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x))<VIR) +#define RDC_STAT_REG(base) ((base)->STAT) +#define RDC_INTCTRL_REG(base) ((base)->INTCTRL) +#define RDC_INTSTAT_REG(base) ((base)->INTSTAT) +#define RDC_MDA_REG(base,index) ((base)->MDA[index]) +#define RDC_PDAP_REG(base,index) ((base)->PDAP[index]) +#define RDC_MRSA_REG(base,index) ((base)->MR[index].MRSA) +#define RDC_MREA_REG(base,index) ((base)->MR[index].MREA) +#define RDC_MRC_REG(base,index) ((base)->MR[index].MRC) +#define RDC_MRVS_REG(base,index) ((base)->MR[index].MRVS) + +/*! + * @} + */ /* end of group RDC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- RDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Register_Masks RDC Register Masks + * @{ + */ + +/* VIR Bit Fields */ +#define RDC_VIR_NDID_MASK 0xFu +#define RDC_VIR_NDID_SHIFT 0 +#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x))<GATE[index]) +#define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) +#define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks + * @{ + */ + +/* GATE Bit Fields */ +#define RDC_SEMAPHORE_GATE_GTFSM_MASK 0xFu +#define RDC_SEMAPHORE_GATE_GTFSM_SHIFT 0 +#define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x))<ROMPATCHD[index]) +#define ROMC_ROMPATCHCNTL_REG(base) ((base)->ROMPATCHCNTL) +#define ROMC_ROMPATCHENH_REG(base) ((base)->ROMPATCHENH) +#define ROMC_ROMPATCHENL_REG(base) ((base)->ROMPATCHENL) +#define ROMC_ROMPATCHA_REG(base,index) ((base)->ROMPATCHA[index]) +#define ROMC_ROMPATCHSR_REG(base) ((base)->ROMPATCHSR) + +/*! + * @} + */ /* end of group ROMC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/* ROMPATCHD Bit Fields */ +#define ROMC_ROMPATCHD_DATAX_MASK 0xFFFFFFFFu +#define ROMC_ROMPATCHD_DATAX_SHIFT 0 +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) +#define SDMAARM_INTR_REG(base) ((base)->INTR) +#define SDMAARM_STOP_STAT_REG(base) ((base)->STOP_STAT) +#define SDMAARM_HSTART_REG(base) ((base)->HSTART) +#define SDMAARM_EVTOVR_REG(base) ((base)->EVTOVR) +#define SDMAARM_DSPOVR_REG(base) ((base)->DSPOVR) +#define SDMAARM_HOSTOVR_REG(base) ((base)->HOSTOVR) +#define SDMAARM_EVTPEND_REG(base) ((base)->EVTPEND) +#define SDMAARM_RESET_REG(base) ((base)->RESET) +#define SDMAARM_EVTERR_REG(base) ((base)->EVTERR) +#define SDMAARM_INTRMASK_REG(base) ((base)->INTRMASK) +#define SDMAARM_PSW_REG(base) ((base)->PSW) +#define SDMAARM_EVTERRDBG_REG(base) ((base)->EVTERRDBG) +#define SDMAARM_CONFIG_REG(base) ((base)->CONFIG) +#define SDMAARM_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK) +#define SDMAARM_ONCE_ENB_REG(base) ((base)->ONCE_ENB) +#define SDMAARM_ONCE_DATA_REG(base) ((base)->ONCE_DATA) +#define SDMAARM_ONCE_INSTR_REG(base) ((base)->ONCE_INSTR) +#define SDMAARM_ONCE_STAT_REG(base) ((base)->ONCE_STAT) +#define SDMAARM_ONCE_CMD_REG(base) ((base)->ONCE_CMD) +#define SDMAARM_ILLINSTADDR_REG(base) ((base)->ILLINSTADDR) +#define SDMAARM_CHN0ADDR_REG(base) ((base)->CHN0ADDR) +#define SDMAARM_EVT_MIRROR_REG(base) ((base)->EVT_MIRROR) +#define SDMAARM_EVT_MIRROR2_REG(base) ((base)->EVT_MIRROR2) +#define SDMAARM_XTRIG_CONF1_REG(base) ((base)->XTRIG_CONF1) +#define SDMAARM_XTRIG_CONF2_REG(base) ((base)->XTRIG_CONF2) +#define SDMAARM_SDMA_CHNPRI_REG(base,index) ((base)->SDMA_CHNPRI[index]) +#define SDMAARM_CHNENBL_REG(base,index) ((base)->CHNENBL[index]) + +/*! + * @} + */ /* end of group SDMAARM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/* MC0PTR Bit Fields */ +#define SDMAARM_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu +#define SDMAARM_MC0PTR_MC0PTR_SHIFT 0 +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<DC0PTR) +#define SDMABP_INTR_REG(base) ((base)->INTR) +#define SDMABP_STOP_STAT_REG(base) ((base)->STOP_STAT) +#define SDMABP_DSTART_REG(base) ((base)->DSTART) +#define SDMABP_EVTERR_REG(base) ((base)->EVTERR) +#define SDMABP_INTRMASK_REG(base) ((base)->INTRMASK) +#define SDMABP_EVTERRDBG_REG(base) ((base)->EVTERRDBG) + +/*! + * @} + */ /* end of group SDMABP_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SDMABP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMABP_Register_Masks SDMABP Register Masks + * @{ + */ + +/* DC0PTR Bit Fields */ +#define SDMABP_DC0PTR_DC0PTR_MASK 0xFFFFFFFFu +#define SDMABP_DC0PTR_DC0PTR_SHIFT 0 +#define SDMABP_DC0PTR_DC0PTR(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) +#define SDMACORE_CCPTR_REG(base) ((base)->CCPTR.CCPTR) +#define SDMACORE_CCR_REG(base) ((base)->CCR.CCR) +#define SDMACORE_NCR_REG(base) ((base)->NCR.NCR) +#define SDMACORE_EVENTS_REG(base) ((base)->EVENTS.EVENTS) +#define SDMACORE_CCPRI_REG(base) ((base)->CCPRI.CCPRI) +#define SDMACORE_NCPRI_REG(base) ((base)->NCPRI.NCPRI) +#define SDMACORE_ECOUNT_REG(base) ((base)->ECOUNT.ECOUNT) +#define SDMACORE_ECTL_REG(base) ((base)->ECTL.ECTL) +#define SDMACORE_EAA_REG(base) ((base)->EAA.EAA) +#define SDMACORE_EAB_REG(base) ((base)->EAB.EAB) +#define SDMACORE_EAM_REG(base) ((base)->EAM.EAM) +#define SDMACORE_ED_REG(base) ((base)->ED.ED) +#define SDMACORE_EDM_REG(base) ((base)->EDM.EDM) +#define SDMACORE_RTB_REG(base) ((base)->RTB) +#define SDMACORE_TB_REG(base) ((base)->TB.TB) +#define SDMACORE_OSTAT_REG(base) ((base)->OSTAT.OSTAT) +#define SDMACORE_MCHN0ADDR_REG(base) ((base)->MCHN0ADDR.MCHN0ADDR) +#define SDMACORE_ENDIANNESS_REG(base) ((base)->ENDIANNESS.ENDIANNESS) +#define SDMACORE_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK.SDMA_LOCK) +#define SDMACORE_EVENTS2_REG(base) ((base)->EVENTS2.EVENTS2) + +/*! + * @} + */ /* end of group SDMACORE_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SDMACORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMACORE_Register_Masks SDMACORE Register Masks + * @{ + */ + +/* MC0PTR Bit Fields */ +#define SDMACORE_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu +#define SDMACORE_MC0PTR_MC0PTR_SHIFT 0 +#define SDMACORE_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<GATE00) +#define SEMA4_GATE01_REG(base) ((base)->GATE01) +#define SEMA4_GATE02_REG(base) ((base)->GATE02) +#define SEMA4_GATE03_REG(base) ((base)->GATE03) +#define SEMA4_GATE04_REG(base) ((base)->GATE04) +#define SEMA4_GATE05_REG(base) ((base)->GATE05) +#define SEMA4_GATE06_REG(base) ((base)->GATE06) +#define SEMA4_GATE07_REG(base) ((base)->GATE07) +#define SEMA4_GATE08_REG(base) ((base)->GATE08) +#define SEMA4_GATE09_REG(base) ((base)->GATE09) +#define SEMA4_GATE10_REG(base) ((base)->GATE10) +#define SEMA4_GATE11_REG(base) ((base)->GATE11) +#define SEMA4_GATE12_REG(base) ((base)->GATE12) +#define SEMA4_GATE13_REG(base) ((base)->GATE13) +#define SEMA4_GATE14_REG(base) ((base)->GATE14) +#define SEMA4_GATE15_REG(base) ((base)->GATE15) +#define SEMA4_CPINE_REG(base,index) ((base)->CPnINE[index].INE) +#define SEMA4_CPNTF_REG(base,index) ((base)->CPnNTF[index].NTF) +#define SEMA4_RSTGT_REG(base) ((base)->RSTGT) +#define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) + +/*! + * @} + */ /* end of group SEMA4_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SEMA4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks + * @{ + */ + +/* GATE00 Bit Fields */ +#define SEMA4_GATE00_GTFSM_MASK 0x3u +#define SEMA4_GATE00_GTFSM_SHIFT 0 +#define SEMA4_GATE00_GTFSM(x) (((uint8_t)(((uint8_t)(x))<GPUSR1) +#define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) +#define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) +#define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) +#define SJC_DCR_REG(base) ((base)->DCR.DCR) +#define SJC_SSR_REG(base) ((base)->SSR.SSR) +#define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) + +/*! + * @} + */ /* end of group SJC_Register_Accessor_Macros */ + + /* ---------------------------------------------------------------------------- + -- SJC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SJC_Register_Masks SJC Register Masks + * @{ + */ + +/* GPUSR1 Bit Fields */ +#define SJC_GPUSR1_A_DBG_MASK 0x1u +#define SJC_GPUSR1_A_DBG_SHIFT 0 +#define SJC_GPUSR1_A_WFI_MASK 0x2u +#define SJC_GPUSR1_A_WFI_SHIFT 1 +#define SJC_GPUSR1_S_STAT_MASK 0x1Cu +#define SJC_GPUSR1_S_STAT_SHIFT 2 +#define SJC_GPUSR1_S_STAT(x) (((uint32_t)(((uint32_t)(x))<HPLR) +#define SNVS_HPCOMR_REG(base) ((base)->HPCOMR) +#define SNVS_HPCR_REG(base) ((base)->HPCR) +#define SNVS_HPSR_REG(base) ((base)->HPSR) +#define SNVS_HPRTCMR_REG(base) ((base)->HPRTCMR) +#define SNVS_HPRTCLR_REG(base) ((base)->HPRTCLR) +#define SNVS_HPTAMR_REG(base) ((base)->HPTAMR) +#define SNVS_HPTALR_REG(base) ((base)->HPTALR) +#define SNVS_LPLR_REG(base) ((base)->LPLR) +#define SNVS_LPCR_REG(base) ((base)->LPCR) +#define SNVS_LPSR_REG(base) ((base)->LPSR) +#define SNVS_LPSMCMR_REG(base) ((base)->LPSMCMR) +#define SNVS_LPSMCLR_REG(base) ((base)->LPSMCLR) +#define SNVS_LPGPR_REG(base) ((base)->LPGPR) +#define SNVS_HPVIDR1_REG(base) ((base)->HPVIDR1) +#define SNVS_HPVIDR2_REG(base) ((base)->HPVIDR2) + +/*! + * @} + */ /* end of group SNVS_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/* HPLR Bit Fields */ +#define SNVS_HPLR_MC_SL_MASK 0x10u +#define SNVS_HPLR_MC_SL_SHIFT 4 +#define SNVS_HPLR_GPR_SL_MASK 0x20u +#define SNVS_HPLR_GPR_SL_SHIFT 5 +/* HPCOMR Bit Fields */ +#define SNVS_HPCOMR_LP_SWR_MASK 0x10u +#define SNVS_HPCOMR_LP_SWR_SHIFT 4 +#define SNVS_HPCOMR_LP_SWR_DIS_MASK 0x20u +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT 5 +#define SNVS_HPCOMR_NPSWA_EN_MASK 0x80000000u +#define SNVS_HPCOMR_NPSWA_EN_SHIFT 31 +/* HPCR Bit Fields */ +#define SNVS_HPCR_RTC_EN_MASK 0x1u +#define SNVS_HPCR_RTC_EN_SHIFT 0 +#define SNVS_HPCR_HPTA_EN_MASK 0x2u +#define SNVS_HPCR_HPTA_EN_SHIFT 1 +#define SNVS_HPCR_PI_EN_MASK 0x8u +#define SNVS_HPCR_PI_EN_SHIFT 3 +#define SNVS_HPCR_PI_FREQ_MASK 0xF0u +#define SNVS_HPCR_PI_FREQ_SHIFT 4 +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x))<PRR[index]) + +/*! + * @} + */ /* end of group SPBA_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/* PRR Bit Fields */ +#define SPBA_PRR_RARA_MASK 0x1u +#define SPBA_PRR_RARA_SHIFT 0 +#define SPBA_PRR_RARB_MASK 0x2u +#define SPBA_PRR_RARB_SHIFT 1 +#define SPBA_PRR_RARC_MASK 0x4u +#define SPBA_PRR_RARC_SHIFT 2 +#define SPBA_PRR_ROI_MASK 0x30000u +#define SPBA_PRR_ROI_SHIFT 16 +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x))<SCR) +#define SPDIF_SRCD_REG(base) ((base)->SRCD) +#define SPDIF_SRPC_REG(base) ((base)->SRPC) +#define SPDIF_SIE_REG(base) ((base)->SIE) +#define SPDIF_SIS_REG(base) ((base)->SIS) +#define SPDIF_SIC_REG(base) ((base)->SIC) +#define SPDIF_SRL_REG(base) ((base)->SRL.SRL) +#define SPDIF_SRR_REG(base) ((base)->SRR.SRR) +#define SPDIF_SRCSH_REG(base) ((base)->SRCSH.SRCSH) +#define SPDIF_SRCSL_REG(base) ((base)->SRCSL.SRCSL) +#define SPDIF_SRU_REG(base) ((base)->SRU.SRU) +#define SPDIF_SRQ_REG(base) ((base)->SRQ.SRQ) +#define SPDIF_STL_REG(base) ((base)->STL.STL) +#define SPDIF_STR_REG(base) ((base)->STR.STR) +#define SPDIF_STCSCH_REG(base) ((base)->STCSCH.STCSCH) +#define SPDIF_STCSCL_REG(base) ((base)->STCSCL.STCSCL) +#define SPDIF_SRFM_REG(base) ((base)->SRFM) +#define SPDIF_STC_REG(base) ((base)->STC) + +/*! + * @} + */ /* end of group SPDIF_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/* SCR Bit Fields */ +#define SPDIF_SCR_USrc_Sel_MASK 0x3u +#define SPDIF_SCR_USrc_Sel_SHIFT 0 +#define SPDIF_SCR_USrc_Sel(x) (((uint32_t)(((uint32_t)(x))<SCR) +#define SRC_SBMR1_REG(base) ((base)->SBMR1) +#define SRC_SRSR_REG(base) ((base)->SRSR) +#define SRC_SISR_REG(base) ((base)->SISR) +#define SRC_SIMR_REG(base) ((base)->SIMR) +#define SRC_SBMR2_REG(base) ((base)->SBMR2) +#define SRC_GPR1_REG(base) ((base)->GPR1) +#define SRC_GPR2_REG(base) ((base)->GPR2) +#define SRC_GPR3_REG(base) ((base)->GPR3) +#define SRC_GPR4_REG(base) ((base)->GPR4) +#define SRC_GPR5_REG(base) ((base)->GPR5) +#define SRC_GPR6_REG(base) ((base)->GPR6) +#define SRC_GPR7_REG(base) ((base)->GPR7) +#define SRC_GPR8_REG(base) ((base)->GPR8) +#define SRC_GPR9_REG(base) ((base)->GPR9) +#define SRC_GPR10_REG(base) ((base)->GPR10) + +/*! + * @} + */ /* end of group SRC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/* SCR Bit Fields */ +#define SRC_SCR_warm_reset_enable_MASK 0x1u +#define SRC_SCR_warm_reset_enable_SHIFT 0 +#define SRC_SCR_sw_gpu_rst_MASK 0x2u +#define SRC_SCR_sw_gpu_rst_SHIFT 1 +#define SRC_SCR_m4c_rst_MASK 0x8u +#define SRC_SCR_m4c_rst_SHIFT 3 +#define SRC_SCR_m4c_non_sclr_rst_MASK 0x10u +#define SRC_SCR_m4c_non_sclr_rst_SHIFT 4 +#define SRC_SCR_warm_rst_bypass_count_MASK 0x60u +#define SRC_SCR_warm_rst_bypass_count_SHIFT 5 +#define SRC_SCR_warm_rst_bypass_count(x) (((uint32_t)(((uint32_t)(x))<STX[index]) +#define SSI_SRX_REG(base,index) ((base)->SRX[index]) +#define SSI_SCR_REG(base) ((base)->SCR) +#define SSI_SISR_REG(base) ((base)->SISR) +#define SSI_SIER_REG(base) ((base)->SIER) +#define SSI_STCR_REG(base) ((base)->STCR) +#define SSI_SRCR_REG(base) ((base)->SRCR) +#define SSI_STCCR_REG(base) ((base)->STCCR) +#define SSI_SRCCR_REG(base) ((base)->SRCCR) +#define SSI_SFCSR_REG(base) ((base)->SFCSR) +#define SSI_SACNT_REG(base) ((base)->SACNT) +#define SSI_SACADD_REG(base) ((base)->SACADD) +#define SSI_SACDAT_REG(base) ((base)->SACDAT) +#define SSI_SATAG_REG(base) ((base)->SATAG) +#define SSI_STMSK_REG(base) ((base)->STMSK) +#define SSI_SRMSK_REG(base) ((base)->SRMSK) +#define SSI_SACCST_REG(base) ((base)->SACCST) +#define SSI_SACCEN_REG(base) ((base)->SACCEN) +#define SSI_SACCDIS_REG(base) ((base)->SACCDIS) + +/*! + * @} + */ /* end of group SSI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SSI_Register_Masks SSI Register Masks + * @{ + */ + +/* STX Bit Fields */ +#define SSI_STX_STXn_MASK 0xFFFFFFFFu +#define SSI_STX_STXn_SHIFT 0 +#define SSI_STX_STXn(x) (((uint32_t)(((uint32_t)(x))<TEMPSENSE0) +#define TEMPMON_TEMPSENSE0_SET_REG(base) ((base)->TEMPSENSE0_SET) +#define TEMPMON_TEMPSENSE0_CLR_REG(base) ((base)->TEMPSENSE0_CLR) +#define TEMPMON_TEMPSENSE0_TOG_REG(base) ((base)->TEMPSENSE0_TOG) +#define TEMPMON_TEMPSENSE1_REG(base) ((base)->TEMPSENSE1) +#define TEMPMON_TEMPSENSE1_SET_REG(base) ((base)->TEMPSENSE1_SET) +#define TEMPMON_TEMPSENSE1_CLR_REG(base) ((base)->TEMPSENSE1_CLR) +#define TEMPMON_TEMPSENSE1_TOG_REG(base) ((base)->TEMPSENSE1_TOG) +#define TEMPMON_TEMPSENSE2_REG(base) ((base)->TEMPSENSE2) +#define TEMPMON_TEMPSENSE2_SET_REG(base) ((base)->TEMPSENSE2_SET) +#define TEMPMON_TEMPSENSE2_CLR_REG(base) ((base)->TEMPSENSE2_CLR) +#define TEMPMON_TEMPSENSE2_TOG_REG(base) ((base)->TEMPSENSE2_TOG) + +/*! + * @} + */ /* end of group TEMPMON_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/* TEMPSENSE0 Bit Fields */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK 0x1u +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT 0 +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK 0x2u +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT 1 +#define TEMPMON_TEMPSENSE0_FINISHED_MASK 0x4u +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT 2 +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK 0xFFF00u +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT 8 +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x))<URXD) +#define UART_UTXD_REG(base) ((base)->UTXD) +#define UART_UCR1_REG(base) ((base)->UCR1) +#define UART_UCR2_REG(base) ((base)->UCR2) +#define UART_UCR3_REG(base) ((base)->UCR3) +#define UART_UCR4_REG(base) ((base)->UCR4) +#define UART_UFCR_REG(base) ((base)->UFCR) +#define UART_USR1_REG(base) ((base)->USR1) +#define UART_USR2_REG(base) ((base)->USR2) +#define UART_UESC_REG(base) ((base)->UESC) +#define UART_UTIM_REG(base) ((base)->UTIM) +#define UART_UBIR_REG(base) ((base)->UBIR) +#define UART_UBMR_REG(base) ((base)->UBMR) +#define UART_UBRC_REG(base) ((base)->UBRC) +#define UART_ONEMS_REG(base) ((base)->ONEMS) +#define UART_UTS_REG(base) ((base)->UTS) +#define UART_UMCR_REG(base) ((base)->UMCR) + +/*! + * @} + */ /* end of group UART_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* URXD Bit Fields */ +#define UART_URXD_RX_DATA_MASK 0xFFu +#define UART_URXD_RX_DATA_SHIFT 0 +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<UOG1_ID) +#define USBC_UOG1_HWGENERAL_REG(base) ((base)->UOG1_HWGENERAL) +#define USBC_UOG1_HWHOST_REG(base) ((base)->UOG1_HWHOST) +#define USBC_UOG1_HWDEVICE_REG(base) ((base)->UOG1_HWDEVICE) +#define USBC_UOG1_HWTXBUF_REG(base) ((base)->UOG1_HWTXBUF) +#define USBC_UOG1_HWRXBUF_REG(base) ((base)->UOG1_HWRXBUF) +#define USBC_UOG1_GPTIMER0LD_REG(base) ((base)->UOG1_GPTIMER0LD) +#define USBC_UOG1_GPTIMER0CTRL_REG(base) ((base)->UOG1_GPTIMER0CTRL) +#define USBC_UOG1_GPTIMER1LD_REG(base) ((base)->UOG1_GPTIMER1LD) +#define USBC_UOG1_GPTIMER1CTRL_REG(base) ((base)->UOG1_GPTIMER1CTRL) +#define USBC_UOG1_SBUSCFG_REG(base) ((base)->UOG1_SBUSCFG) +#define USBC_UOG1_CAPLENGTH_REG(base) ((base)->UOG1_CAPLENGTH) +#define USBC_UOG1_HCIVERSION_REG(base) ((base)->UOG1_HCIVERSION) +#define USBC_UOG1_HCSPARAMS_REG(base) ((base)->UOG1_HCSPARAMS) +#define USBC_UOG1_HCCPARAMS_REG(base) ((base)->UOG1_HCCPARAMS) +#define USBC_UOG1_DCIVERSION_REG(base) ((base)->UOG1_DCIVERSION) +#define USBC_UOG1_DCCPARAMS_REG(base) ((base)->UOG1_DCCPARAMS) +#define USBC_UOG1_USBCMD_REG(base) ((base)->UOG1_USBCMD) +#define USBC_UOG1_USBSTS_REG(base) ((base)->UOG1_USBSTS) +#define USBC_UOG1_USBINTR_REG(base) ((base)->UOG1_USBINTR) +#define USBC_UOG1_FRINDEX_REG(base) ((base)->UOG1_FRINDEX) +#define USBC_UOG1_PERIODICLISTBASE_REG(base) ((base)->UOG1_PERIODICLISTBASE) +#define USBC_UOG1_DEVICEADDR_REG(base) ((base)->UOG1_DEVICEADDR) +#define USBC_UOG1_ASYNCLISTADDR_REG(base) ((base)->UOG1_ASYNCLISTADDR.UOG1_ASYNCLISTADDR) +#define USBC_UOG1_ENDPTLISTADDR_REG(base) ((base)->UOG1_ENDPTLISTADDR.UOG1_ENDPTLISTADDR) +#define USBC_UOG1_BURSTSIZE_REG(base) ((base)->UOG1_BURSTSIZE) +#define USBC_UOG1_TXFILLTUNING_REG(base) ((base)->UOG1_TXFILLTUNING) +#define USBC_UOG1_ENDPTNAK_REG(base) ((base)->UOG1_ENDPTNAK) +#define USBC_UOG1_ENDPTNAKEN_REG(base) ((base)->UOG1_ENDPTNAKEN) +#define USBC_UOG1_CONFIGFLAG_REG(base) ((base)->UOG1_CONFIGFLAG) +#define USBC_UOG1_PORTSC1_REG(base) ((base)->UOG1_PORTSC1) +#define USBC_UOG1_OTGSC_REG(base) ((base)->UOG1_OTGSC) +#define USBC_UOG1_USBMODE_REG(base) ((base)->UOG1_USBMODE) +#define USBC_UOG1_ENDPTSETUPSTAT_REG(base) ((base)->UOG1_ENDPTSETUPSTAT) +#define USBC_UOG1_ENDPTPRIME_REG(base) ((base)->UOG1_ENDPTPRIME) +#define USBC_UOG1_ENDPTFLUSH_REG(base) ((base)->UOG1_ENDPTFLUSH) +#define USBC_UOG1_ENDPTSTAT_REG(base) ((base)->UOG1_ENDPTSTAT) +#define USBC_UOG1_ENDPTCOMPLETE_REG(base) ((base)->UOG1_ENDPTCOMPLETE) +#define USBC_UOG1_ENDPTCTRL0_REG(base) ((base)->UOG1_ENDPTCTRL0) +#define USBC_UOG1_ENDPTCTRL1_REG(base) ((base)->UOG1_ENDPTCTRL1) +#define USBC_UOG1_ENDPTCTRL2_REG(base) ((base)->UOG1_ENDPTCTRL2) +#define USBC_UOG1_ENDPTCTRL3_REG(base) ((base)->UOG1_ENDPTCTRL3) +#define USBC_UOG1_ENDPTCTRL4_REG(base) ((base)->UOG1_ENDPTCTRL4) +#define USBC_UOG1_ENDPTCTRL5_REG(base) ((base)->UOG1_ENDPTCTRL5) +#define USBC_UOG1_ENDPTCTRL6_REG(base) ((base)->UOG1_ENDPTCTRL6) +#define USBC_UOG1_ENDPTCTRL7_REG(base) ((base)->UOG1_ENDPTCTRL7) +#define USBC_UOG2_ID_REG(base) ((base)->UOG2_ID) +#define USBC_UOG2_HWGENERAL_REG(base) ((base)->UOG2_HWGENERAL) +#define USBC_UOG2_HWHOST_REG(base) ((base)->UOG2_HWHOST) +#define USBC_UOG2_HWDEVICE_REG(base) ((base)->UOG2_HWDEVICE) +#define USBC_UOG2_HWTXBUF_REG(base) ((base)->UOG2_HWTXBUF) +#define USBC_UOG2_HWRXBUF_REG(base) ((base)->UOG2_HWRXBUF) +#define USBC_UOG2_GPTIMER0LD_REG(base) ((base)->UOG2_GPTIMER0LD) +#define USBC_UOG2_GPTIMER0CTRL_REG(base) ((base)->UOG2_GPTIMER0CTRL) +#define USBC_UOG2_GPTIMER1LD_REG(base) ((base)->UOG2_GPTIMER1LD) +#define USBC_UOG2_GPTIMER1CTRL_REG(base) ((base)->UOG2_GPTIMER1CTRL) +#define USBC_UOG2_SBUSCFG_REG(base) ((base)->UOG2_SBUSCFG) +#define USBC_UOG2_CAPLENGTH_REG(base) ((base)->UOG2_CAPLENGTH) +#define USBC_UOG2_HCIVERSION_REG(base) ((base)->UOG2_HCIVERSION) +#define USBC_UOG2_HCSPARAMS_REG(base) ((base)->UOG2_HCSPARAMS) +#define USBC_UOG2_HCCPARAMS_REG(base) ((base)->UOG2_HCCPARAMS) +#define USBC_UOG2_DCIVERSION_REG(base) ((base)->UOG2_DCIVERSION) +#define USBC_UOG2_DCCPARAMS_REG(base) ((base)->UOG2_DCCPARAMS) +#define USBC_UOG2_USBCMD_REG(base) ((base)->UOG2_USBCMD) +#define USBC_UOG2_USBSTS_REG(base) ((base)->UOG2_USBSTS) +#define USBC_UOG2_USBINTR_REG(base) ((base)->UOG2_USBINTR) +#define USBC_UOG2_FRINDEX_REG(base) ((base)->UOG2_FRINDEX) +#define USBC_UOG2_PERIODICLISTBASE_REG(base) ((base)->UOG2_PERIODICLISTBASE) +#define USBC_UOG2_DEVICEADDR_REG(base) ((base)->UOG2_DEVICEADDR) +#define USBC_UOG2_ASYNCLISTADDR_REG(base) ((base)->UOG2_ASYNCLISTADDR.UOG2_ASYNCLISTADDR) +#define USBC_UOG2_ENDPTLISTADDR_REG(base) ((base)->UOG2_ENDPTLISTADDR.UOG2_ENDPTLISTADDR) +#define USBC_UOG2_BURSTSIZE_REG(base) ((base)->UOG2_BURSTSIZE) +#define USBC_UOG2_TXFILLTUNING_REG(base) ((base)->UOG2_TXFILLTUNING) +#define USBC_UOG2_ENDPTNAK_REG(base) ((base)->UOG2_ENDPTNAK) +#define USBC_UOG2_ENDPTNAKEN_REG(base) ((base)->UOG2_ENDPTNAKEN) +#define USBC_UOG2_CONFIGFLAG_REG(base) ((base)->UOG2_CONFIGFLAG) +#define USBC_UOG2_PORTSC1_REG(base) ((base)->UOG2_PORTSC1) +#define USBC_UOG2_OTGSC_REG(base) ((base)->UOG2_OTGSC) +#define USBC_UOG2_USBMODE_REG(base) ((base)->UOG2_USBMODE) +#define USBC_UOG2_ENDPTSETUPSTAT_REG(base) ((base)->UOG2_ENDPTSETUPSTAT) +#define USBC_UOG2_ENDPTPRIME_REG(base) ((base)->UOG2_ENDPTPRIME) +#define USBC_UOG2_ENDPTFLUSH_REG(base) ((base)->UOG2_ENDPTFLUSH) +#define USBC_UOG2_ENDPTSTAT_REG(base) ((base)->UOG2_ENDPTSTAT) +#define USBC_UOG2_ENDPTCOMPLETE_REG(base) ((base)->UOG2_ENDPTCOMPLETE) +#define USBC_UOG2_ENDPTCTRL0_REG(base) ((base)->UOG2_ENDPTCTRL0) +#define USBC_UOG2_ENDPTCTRL1_REG(base) ((base)->UOG2_ENDPTCTRL1) +#define USBC_UOG2_ENDPTCTRL2_REG(base) ((base)->UOG2_ENDPTCTRL2) +#define USBC_UOG2_ENDPTCTRL3_REG(base) ((base)->UOG2_ENDPTCTRL3) +#define USBC_UOG2_ENDPTCTRL4_REG(base) ((base)->UOG2_ENDPTCTRL4) +#define USBC_UOG2_ENDPTCTRL5_REG(base) ((base)->UOG2_ENDPTCTRL5) +#define USBC_UOG2_ENDPTCTRL6_REG(base) ((base)->UOG2_ENDPTCTRL6) +#define USBC_UOG2_ENDPTCTRL7_REG(base) ((base)->UOG2_ENDPTCTRL7) +#define USBC_UH1_ID_REG(base) ((base)->UH1_ID) +#define USBC_UH1_HWGENERAL_REG(base) ((base)->UH1_HWGENERAL) +#define USBC_UH1_HWHOST_REG(base) ((base)->UH1_HWHOST) +#define USBC_UH1_HWTXBUF_REG(base) ((base)->UH1_HWTXBUF) +#define USBC_UH1_HWRXBUF_REG(base) ((base)->UH1_HWRXBUF) +#define USBC_UH1_GPTIMER0LD_REG(base) ((base)->UH1_GPTIMER0LD) +#define USBC_UH1_GPTIMER0CTRL_REG(base) ((base)->UH1_GPTIMER0CTRL) +#define USBC_UH1_GPTIMER1LD_REG(base) ((base)->UH1_GPTIMER1LD) +#define USBC_UH1_GPTIMER1CTRL_REG(base) ((base)->UH1_GPTIMER1CTRL) +#define USBC_UH1_SBUSCFG_REG(base) ((base)->UH1_SBUSCFG) +#define USBC_UH1_CAPLENGTH_REG(base) ((base)->UH1_CAPLENGTH) +#define USBC_UH1_HCIVERSION_REG(base) ((base)->UH1_HCIVERSION) +#define USBC_UH1_HCSPARAMS_REG(base) ((base)->UH1_HCSPARAMS) +#define USBC_UH1_HCCPARAMS_REG(base) ((base)->UH1_HCCPARAMS) +#define USBC_UH1_USBCMD_REG(base) ((base)->UH1_USBCMD) +#define USBC_UH1_USBSTS_REG(base) ((base)->UH1_USBSTS) +#define USBC_UH1_USBINTR_REG(base) ((base)->UH1_USBINTR) +#define USBC_UH1_FRINDEX_REG(base) ((base)->UH1_FRINDEX) +#define USBC_UH1_PERIODICLISTBASE_REG(base) ((base)->UH1_PERIODICLISTBASE) +#define USBC_UH1_ASYNCLISTADDR_REG(base) ((base)->UH1_ASYNCLISTADDR) +#define USBC_UH1_BURSTSIZE_REG(base) ((base)->UH1_BURSTSIZE) +#define USBC_UH1_TXFILLTUNING_REG(base) ((base)->UH1_TXFILLTUNING) +#define USBC_UH1_CONFIGFLAG_REG(base) ((base)->UH1_CONFIGFLAG) +#define USBC_UH1_PORTSC1_REG(base) ((base)->UH1_PORTSC1) +#define USBC_UH1_USBMODE_REG(base) ((base)->UH1_USBMODE) + +/*! + * @} + */ /* end of group USBC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- USBC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBC_Register_Masks USBC Register Masks + * @{ + */ + +/* UOG1_ID Bit Fields */ +#define USBC_UOG1_ID_ID_MASK 0x3Fu +#define USBC_UOG1_ID_ID_SHIFT 0 +#define USBC_UOG1_ID_ID(x) (((uint32_t)(((uint32_t)(x))<USB_x_PHY_STS) +#define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) +#define USBNC_USB_OTG1_CTRL_REG(base) ((base)->USB_OTG1_CTRL) +#define USBNC_USB_OTG2_CTRL_REG(base) ((base)->USB_OTG2_CTRL) +#define USBNC_USB_UH_CTRL_REG(base) ((base)->USB_UH_CTRL) +#define USBNC_USB_UH_HSIC_CTRL_REG(base) ((base)->USB_UH_HSIC_CTRL) +#define USBNC_USB_OTG1_PHY_CTRL_0_REG(base) ((base)->USB_OTG1_PHY_CTRL_0) +#define USBNC_USB_OTG2_PHY_CTRL_0_REG(base) ((base)->USB_OTG2_PHY_CTRL_0) + +/*! + * @} + */ /* end of group USBNC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/* USB_x_PHY_STS Bit Fields */ +#define USBNC_USB_x_PHY_STS_LINE_STATE_MASK 0x3u +#define USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT 0 +#define USBNC_USB_x_PHY_STS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x))<PWD) +#define USBPHY_PWD_SET_REG(base) ((base)->PWD_SET) +#define USBPHY_PWD_CLR_REG(base) ((base)->PWD_CLR) +#define USBPHY_PWD_TOG_REG(base) ((base)->PWD_TOG) +#define USBPHY_TX_REG(base) ((base)->TX) +#define USBPHY_TX_SET_REG(base) ((base)->TX_SET) +#define USBPHY_TX_CLR_REG(base) ((base)->TX_CLR) +#define USBPHY_TX_TOG_REG(base) ((base)->TX_TOG) +#define USBPHY_RX_REG(base) ((base)->RX) +#define USBPHY_RX_SET_REG(base) ((base)->RX_SET) +#define USBPHY_RX_CLR_REG(base) ((base)->RX_CLR) +#define USBPHY_RX_TOG_REG(base) ((base)->RX_TOG) +#define USBPHY_CTRL_REG(base) ((base)->CTRL) +#define USBPHY_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define USBPHY_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define USBPHY_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define USBPHY_STATUS_REG(base) ((base)->STATUS) +#define USBPHY_DEBUG_REG(base) ((base)->DEBUG) +#define USBPHY_DEBUG_SET_REG(base) ((base)->DEBUG_SET) +#define USBPHY_DEBUG_CLR_REG(base) ((base)->DEBUG_CLR) +#define USBPHY_DEBUG_TOG_REG(base) ((base)->DEBUG_TOG) +#define USBPHY_DEBUG0_STATUS_REG(base) ((base)->DEBUG0_STATUS) +#define USBPHY_DEBUG1_REG(base) ((base)->DEBUG1) +#define USBPHY_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) +#define USBPHY_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) +#define USBPHY_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) +#define USBPHY_VERSION_REG(base) ((base)->VERSION) + +/*! + * @} + */ /* end of group USBPHY_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/* PWD Bit Fields */ +#define USBPHY_PWD_RSVD0_MASK 0x3FFu +#define USBPHY_PWD_RSVD0_SHIFT 0 +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<USB1_VBUS_DETECT) +#define USB_ANALOG_USB1_VBUS_DETECT_SET_REG(base) ((base)->USB1_VBUS_DETECT_SET) +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(base) ((base)->USB1_VBUS_DETECT_CLR) +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(base) ((base)->USB1_VBUS_DETECT_TOG) +#define USB_ANALOG_USB1_CHRG_DETECT_REG(base) ((base)->USB1_CHRG_DETECT) +#define USB_ANALOG_USB1_CHRG_DETECT_SET_REG(base) ((base)->USB1_CHRG_DETECT_SET) +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(base) ((base)->USB1_CHRG_DETECT_CLR) +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(base) ((base)->USB1_CHRG_DETECT_TOG) +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(base) ((base)->USB1_VBUS_DETECT_STAT) +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(base) ((base)->USB1_CHRG_DETECT_STAT) +#define USB_ANALOG_USB1_MISC_REG(base) ((base)->USB1_MISC) +#define USB_ANALOG_USB1_MISC_SET_REG(base) ((base)->USB1_MISC_SET) +#define USB_ANALOG_USB1_MISC_CLR_REG(base) ((base)->USB1_MISC_CLR) +#define USB_ANALOG_USB1_MISC_TOG_REG(base) ((base)->USB1_MISC_TOG) +#define USB_ANALOG_USB2_VBUS_DETECT_REG(base) ((base)->USB2_VBUS_DETECT) +#define USB_ANALOG_USB2_VBUS_DETECT_SET_REG(base) ((base)->USB2_VBUS_DETECT_SET) +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(base) ((base)->USB2_VBUS_DETECT_CLR) +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(base) ((base)->USB2_VBUS_DETECT_TOG) +#define USB_ANALOG_USB2_CHRG_DETECT_REG(base) ((base)->USB2_CHRG_DETECT) +#define USB_ANALOG_USB2_CHRG_DETECT_SET_REG(base) ((base)->USB2_CHRG_DETECT_SET) +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(base) ((base)->USB2_CHRG_DETECT_CLR) +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(base) ((base)->USB2_CHRG_DETECT_TOG) +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(base) ((base)->USB2_VBUS_DETECT_STAT) +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(base) ((base)->USB2_CHRG_DETECT_STAT) +#define USB_ANALOG_USB2_MISC_REG(base) ((base)->USB2_MISC) +#define USB_ANALOG_USB2_MISC_SET_REG(base) ((base)->USB2_MISC_SET) +#define USB_ANALOG_USB2_MISC_CLR_REG(base) ((base)->USB2_MISC_CLR) +#define USB_ANALOG_USB2_MISC_TOG_REG(base) ((base)->USB2_MISC_TOG) +#define USB_ANALOG_DIGPROG_REG(base) ((base)->DIGPROG) + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/* USB1_VBUS_DETECT Bit Fields */ +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<CFC1) +#define VDEC_BRSTGT_REG(base) ((base)->BRSTGT) +#define VDEC_HZPOS_REG(base) ((base)->HZPOS) +#define VDEC_VRTPOS_REG(base) ((base)->VRTPOS) +#define VDEC_HVSHFT_REG(base) ((base)->HVSHFT) +#define VDEC_HSIGS_REG(base) ((base)->HSIGS) +#define VDEC_HSIGE_REG(base) ((base)->HSIGE) +#define VDEC_VSCON1_REG(base) ((base)->VSCON1) +#define VDEC_VSCON2_REG(base) ((base)->VSCON2) +#define VDEC_YCDEL_REG(base) ((base)->YCDEL) +#define VDEC_AFTCLP_REG(base) ((base)->AFTCLP) +#define VDEC_DCOFF_REG(base) ((base)->DCOFF) +#define VDEC_CSID_REG(base) ((base)->CSID) +#define VDEC_CBGN_REG(base) ((base)->CBGN) +#define VDEC_CRGN_REG(base) ((base)->CRGN) +#define VDEC_CNTR_REG(base) ((base)->CNTR) +#define VDEC_BRT_REG(base) ((base)->BRT) +#define VDEC_HUE_REG(base) ((base)->HUE) +#define VDEC_CHBTH_REG(base) ((base)->CHBTH) +#define VDEC_SHPIMP_REG(base) ((base)->SHPIMP) +#define VDEC_CHPLLIM_REG(base) ((base)->CHPLLIM) +#define VDEC_VIDMOD_REG(base) ((base)->VIDMOD) +#define VDEC_VIDSTS_REG(base) ((base)->VIDSTS) +#define VDEC_NOISE_REG(base) ((base)->NOISE) +#define VDEC_STDDBG_REG(base) ((base)->STDDBG) +#define VDEC_MANOVR_REG(base) ((base)->MANOVR) +#define VDEC_VSSGTH_REG(base) ((base)->VSSGTH) +#define VDEC_DBGFBH_REG(base) ((base)->DBGFBH) +#define VDEC_DBGFBL_REG(base) ((base)->DBGFBL) +#define VDEC_HACTS_REG(base) ((base)->HACTS) +#define VDEC_HACTE_REG(base) ((base)->HACTE) +#define VDEC_VACTS_REG(base) ((base)->VACTS) +#define VDEC_VACTE_REG(base) ((base)->VACTE) +#define VDEC_HSTIP_REG(base) ((base)->HSTIP) +#define VDEC_BLSCRCR_REG(base) ((base)->BLSCRCR) +#define VDEC_BLSCRCB_REG(base) ((base)->BLSCRCB) +#define VDEC_LMAGC2_REG(base) ((base)->LMAGC2) +#define VDEC_CHAGC2_REG(base) ((base)->CHAGC2) +#define VDEC_MINTH_REG(base) ((base)->MINTH) +#define VDEC_VFRQOH_REG(base) ((base)->VFRQOH) +#define VDEC_VFRQOL_REG(base) ((base)->VFRQOL) +#define VDEC_ASYNCLKFREQ1_REG(base) ((base)->ASYNCLKFREQ1) +#define VDEC_ASYNCLKFREQ2_REG(base) ((base)->ASYNCLKFREQ2) +#define VDEC_ASYNCLKFREQ3_REG(base) ((base)->ASYNCLKFREQ3) +#define VDEC_ASYNCLKFREQ4_REG(base) ((base)->ASYNCLKFREQ4) + +/*! + * @} + */ /* end of group VDEC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- VDEC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VDEC_Register_Masks VDEC Register Masks + * @{ + */ + +/* CFC1 Bit Fields */ +#define VDEC_CFC1_rc_combmode_override_MASK 0xFu +#define VDEC_CFC1_rc_combmode_override_SHIFT 0 +#define VDEC_CFC1_rc_combmode_override(x) (((uint32_t)(((uint32_t)(x))<WCR) +#define WDOG_WSR_REG(base) ((base)->WSR) +#define WDOG_WRSR_REG(base) ((base)->WRSR) +#define WDOG_WICR_REG(base) ((base)->WICR) +#define WDOG_WMCR_REG(base) ((base)->WMCR) + +/*! + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* WCR Bit Fields */ +#define WDOG_WCR_WDZST_MASK 0x1u +#define WDOG_WCR_WDZST_SHIFT 0 +#define WDOG_WCR_WDBG_MASK 0x2u +#define WDOG_WCR_WDBG_SHIFT 1 +#define WDOG_WCR_WDE_MASK 0x4u +#define WDOG_WCR_WDE_SHIFT 2 +#define WDOG_WCR_WDT_MASK 0x8u +#define WDOG_WCR_WDT_SHIFT 3 +#define WDOG_WCR_SRS_MASK 0x10u +#define WDOG_WCR_SRS_SHIFT 4 +#define WDOG_WCR_WDA_MASK 0x20u +#define WDOG_WCR_WDA_SHIFT 5 +#define WDOG_WCR_SRE_MASK 0x40u +#define WDOG_WCR_SRE_SHIFT 6 +#define WDOG_WCR_WDW_MASK 0x80u +#define WDOG_WCR_WDW_SHIFT 7 +#define WDOG_WCR_WT_MASK 0xFF00u +#define WDOG_WCR_WT_SHIFT 8 +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<MISC0) +#define XTALOSC24M_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL) +#define XTALOSC24M_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) +#define XTALOSC24M_OSC_CONFIG0_REG(base) ((base)->OSC_CONFIG0) +#define XTALOSC24M_OSC_CONFIG0_SET_REG(base) ((base)->OSC_CONFIG0_SET) +#define XTALOSC24M_OSC_CONFIG0_CLR_REG(base) ((base)->OSC_CONFIG0_CLR) +#define XTALOSC24M_OSC_CONFIG0_TOG_REG(base) ((base)->OSC_CONFIG0_TOG) +#define XTALOSC24M_OSC_CONFIG1_REG(base) ((base)->OSC_CONFIG1) +#define XTALOSC24M_OSC_CONFIG1_SET_REG(base) ((base)->OSC_CONFIG1_SET) +#define XTALOSC24M_OSC_CONFIG1_CLR_REG(base) ((base)->OSC_CONFIG1_CLR) +#define XTALOSC24M_OSC_CONFIG1_TOG_REG(base) ((base)->OSC_CONFIG1_TOG) +#define XTALOSC24M_OSC_CONFIG2_REG(base) ((base)->OSC_CONFIG2) +#define XTALOSC24M_OSC_CONFIG2_SET_REG(base) ((base)->OSC_CONFIG2_SET) +#define XTALOSC24M_OSC_CONFIG2_CLR_REG(base) ((base)->OSC_CONFIG2_CLR) +#define XTALOSC24M_OSC_CONFIG2_TOG_REG(base) ((base)->OSC_CONFIG2_TOG) + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/* MISC0 Bit Fields */ +#define XTALOSC24M_MISC0_REFTOP_PWD_MASK 0x1u +#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT 0 +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK 0x8u +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT 3 +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK 0x70u +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT 4 +#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<DS_ADDR) +#define uSDHC_BLK_ATT_REG(base) ((base)->BLK_ATT) +#define uSDHC_CMD_ARG_REG(base) ((base)->CMD_ARG) +#define uSDHC_CMD_XFR_TYP_REG(base) ((base)->CMD_XFR_TYP) +#define uSDHC_CMD_RSP0_REG(base) ((base)->CMD_RSP0) +#define uSDHC_CMD_RSP1_REG(base) ((base)->CMD_RSP1) +#define uSDHC_CMD_RSP2_REG(base) ((base)->CMD_RSP2) +#define uSDHC_CMD_RSP3_REG(base) ((base)->CMD_RSP3) +#define uSDHC_DATA_BUFF_ACC_PORT_REG(base) ((base)->DATA_BUFF_ACC_PORT) +#define uSDHC_PRES_STATE_REG(base) ((base)->PRES_STATE) +#define uSDHC_PROT_CTRL_REG(base) ((base)->PROT_CTRL) +#define uSDHC_SYS_CTRL_REG(base) ((base)->SYS_CTRL) +#define uSDHC_INT_STATUS_REG(base) ((base)->INT_STATUS) +#define uSDHC_INT_STATUS_EN_REG(base) ((base)->INT_STATUS_EN) +#define uSDHC_INT_SIGNAL_EN_REG(base) ((base)->INT_SIGNAL_EN) +#define uSDHC_AUTOCMD12_ERR_STATUS_REG(base) ((base)->AUTOCMD12_ERR_STATUS) +#define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP) +#define uSDHC_WTMK_LVL_REG(base) ((base)->WTMK_LVL) +#define uSDHC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) +#define uSDHC_FORCE_EVENT_REG(base) ((base)->FORCE_EVENT) +#define uSDHC_ADMA_ERR_STATUS_REG(base) ((base)->ADMA_ERR_STATUS) +#define uSDHC_ADMA_SYS_ADDR_REG(base) ((base)->ADMA_SYS_ADDR) +#define uSDHC_DLL_CTRL_REG(base) ((base)->DLL_CTRL) +#define uSDHC_DLL_STATUS_REG(base) ((base)->DLL_STATUS) +#define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base) ((base)->CLK_TUNE_CTRL_STATUS) +#define uSDHC_VEND_SPEC_REG(base) ((base)->VEND_SPEC) +#define uSDHC_MMC_BOOT_REG(base) ((base)->MMC_BOOT) +#define uSDHC_VEND_SPEC2_REG(base) ((base)->VEND_SPEC2) +#define uSDHC_TUNING_CTRL_REG(base) ((base)->TUNING_CTRL) + +/*! + * @} + */ /* end of group uSDHC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- uSDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup uSDHC_Register_Masks uSDHC Register Masks + * @{ + */ + +/* DS_ADDR Bit Fields */ +#define uSDHC_DS_ADDR_DS_ADDR_MASK 0xFFFFFFFCu +#define uSDHC_DS_ADDR_DS_ADDR_SHIFT 2 +#define uSDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x))< + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000u + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + GPR_IRQn = 0, /**< Used to notify cores on exception condition while boot */ + DAP_IRQn = 1, /**< DAP Interrupt */ + SDMA_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */ + DBGMON_IRQn = 3, /**< DBGMON Sync Interrupt */ + SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */ + LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */ + SIM2_IRQn = 6, /**< SIM Interrupt */ + CSI_IRQn = 7, /**< CSI Interrupt */ + PXP1_IRQn = 8, /**< PXP Interrupt */ + Reserved_IRQn = 9, /**< Reserved */ + WDOG3_IRQn = 10, /**< Watchdog Timer reset */ + SEMA4_HS_M4_IRQn = 11, /**< SEMA4-HS M4 Interrupt Request */ + APBHDMA_IRQn = 12, /**< GPMI operation channel 0 description complete interrupt */ + EIM_IRQn = 13, /**< EIM Interrupt */ + BCH_IRQn = 14, /**< BCH operation complete interrupt */ + GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */ + UART6_IRQn = 16, /**< UART-6 ORed interrupt */ + FTM1_IRQn = 17, /**< Flex Timer1 Fault / Counter / Channel interrupt */ + FTM2_IRQn = 18, /**< Flex Timer2 Fault / Counter / Channel interrupt */ + SNVS_CONSOLIDATED_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */ + SNVS_SECURITY_IRQn = 20, /**< SRTC Security Interrupt. TZ. */ + CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted */ + uSDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ + uSDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ + uSDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */ + MIPI_CSI_IRQn = 25, /**< MIPI CSI interrupt */ + UART1_IRQn = 26, /**< UART-1 ORed interrupt */ + UART2_IRQn = 27, /**< UART-2 ORed interrupt */ + UART3_IRQn = 28, /**< UART-3 ORed interrupt */ + UART4_IRQn = 29, /**< UART-4 ORed interrupt */ + UART5_IRQn = 30, /**< UART-5 ORed interrupt */ + eCSPI1_IRQn = 31, /**< eCSPI1 interrupt request line to the core. */ + eCSPI2_IRQn = 32, /**< eCSPI2 interrupt request line to the core. */ + eCSPI3_IRQn = 33, /**< eCSPI3 interrupt request line to the core. */ + eCSPI4_IRQn = 34, /**< eCSPI4 interrupt request line to the core. */ + I2C1_IRQn = 35, /**< I2C-1 Interrupt */ + I2C2_IRQn = 36, /**< I2C-2 Interrupt */ + I2C3_IRQn = 37, /**< I2C-3 Interrupt */ + I2C4_IRQn = 38, /**< I2C-4 Interrupt */ + RDC_IRQn = 39, /**< RDC interrupt */ + USB_OH3_OTG2_1_IRQn = 40, /**< USB OH3 OTG2 */ + MIPI_DSI_IRQn = 41, /**< MIPI CSI Interrupt */ + USB_OH3_OTG2_2_IRQn = 42, /**< USB OH3 OTG2 */ + USB_OH2_OTG_IRQn = 43, /**< USB OH2 OTG */ + USB_OTG1_IRQn = 44, /**< USB OTG1 Interrupt */ + USB_OTG2_IRQn = 45, /**< USB OTG2 Interrupt */ + PXP2_IRQn = 46, /**< PXP interrupt */ + SCTR1_IRQn = 47, /**< ISO7816IP Interrupt */ + SCTR2_IRQn = 48, /**< ISO7816IP Interrupt */ + Analog_TempSensor_IRQn = 49, /**< TempSensor (Temperature low alarm). */ + SAI3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */ + Analog_brown_out_IRQn = 51, /**< Brown-out event on either analog regulators. */ + GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_INT15_0_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_INT31_16_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_INT15_0_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_INT31_16_IRQn = 67, /**< Combined interrupt indication for GPIO2 signals 16 throughout 31 */ + GPIO3_INT15_0_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_INT31_16_IRQn = 69, /**< Combined interrupt indication for GPIO3 signals 16 throughout 31 */ + GPIO4_INT15_0_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ + GPIO4_INT31_16_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ + GPIO5_INT15_0_IRQn = 72, /**< Combined interrupt indication for GPIO5 signals 0 throughout 15 */ + GPIO5_INT31_16_IRQn = 73, /**< Combined interrupt indication for GPIO5 signals 16 throughout 31 */ + GPIO6_INT15_0_IRQn = 74, /**< Combined interrupt indication for GPIO6 signals 0 throughtout 15 */ + GPIO6_INT31_16_IRQn = 75, /**< Combined interrupt indication for GPIO6 signals 16 throughtout 31 */ + GPIO7_INT15_0_IRQn = 76, /**< Combined interrupt indication for GPIO7 signals 0 throughout 15 */ + GPIO7_INT31_16_IRQn = 77, /**< Combined interrupt indication for GPIO7 signals 16 throughout 31 */ + WDOG1_IRQn = 78, /**< Watchdog Timer reset */ + WDOG2_IRQn = 79, /**< Watchdog Timer reset */ + KPP_IRQn = 80, /**< Keypad Interrupt */ + PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + CCM1_IRQn = 85, /**< CCM, Interrupt Request 1 */ + CCM2_IRQn = 86, /**< CCM, Interrupt Request 2 */ + GPC_IRQn = 87, /**< GPC Interrupt Request 1 */ + MU_A7_IRQn = 88, /**< Interrupt to A7 */ + SRC_IRQn = 89, /**< SRC interrupt request */ + SIM1_IRQn = 90, /**< Sim Interrupt */ + RTIC_IRQn = 91, /**< RTIC Interrupt */ + CPU_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[0]) + Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[1]) */ + CPU_CTI_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[0]) + CTI trigger outputs (internal: nCTIIRQ[1]) */ + CCM_SRC_GPC_IRQn = 94, /**< SRC GPC Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */ + SAI2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */ + MU_M4_IRQn = 97, /**< Interrupt to M4 */ + ADC1_IRQn = 98, /**< ADC-1 Interrupt */ + ADC2_IRQn = 99, /**< ADC-2 Interrupt */ + ENET2_MAC0_TRANS1_IRQn = 100, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ + ENET2_MAC0_TRANS2_IRQn = 101, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ + ENET2_MAC0_IRQ_IRQn = 102, /**< MAC 0 IRQ */ + ENET2_1588_TIMER_IRQ_IRQn = 103, /**< MAC 0 1588 Timer Interrupt - synchronous */ + TPR_IRQn = 104, /**< IRQ TPR IRQ */ + CAAM_QUEUE_IRQn = 105, /**< WRAPPER CAAM interrupt queue for JQ */ + CAAM_ERROR_IRQn = 106, /**< WRAPPER CAAM interrupt queue for JQ */ + QSPI_IRQn = 107, /**< QSPI Interrupt */ + TZASC1_IRQn = 108, /**< TZASC (PL380) interrupt */ + WDOG4_IRQn = 109, /**< Watchdog Timer reset */ + FLEXCAN1_IRQn = 110, /**< FlexCAN1 Interrupt */ + FLEXCAN2_IRQn = 111, /**< FlexCAN2 Interrupt */ + PERFMON1_IRQn = 112, /**< General interrupt */ + PERFMON2_IRQn = 113, /**< General interrupt */ + CAAM_WRAPPER1_IRQn = 114, /**< CAAM interrupt queue for JQ */ + CAAM_WRAPPER2_IRQn = 115, /**< Recoverable error interrupt */ + SEMA4_HS_A7_IRQn = 116, /**< SEMA4-HS processor A7 Interrupt Request */ + EPDC_IRQn = 117, /**< EPDC Interrupt */ + ENET1_MAC0_TRANS1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET1_MAC0_TRANS2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET1_MAC0_IRQn = 120, /**< MAC 0 IRQ */ + ENET1_1588_TIMER_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */ + PCIE_CTRL1_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL2_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL3_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL4_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + UART7_IRQn = 126, /**< UART-7 ORed interrupt */ + PCIE_CTRL_REQUEST_IRQn = 127, /**< Channels [63:32] interrupts requests */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CH_A_CFG1; /**< Channel A configuration 1, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CH_A_CFG2; /**< Channel A configuration 2, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CH_B_CFG1; /**< , offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CH_B_CFG2; /**< Channel B Configuration 2, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH_C_CFG1; /**< Channel C Configuration 1, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CH_C_CFG2; /**< Channel C Configuration 2, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CH_D_CFG1; /**< Channel D Configuration 1, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CH_D_CFG2; /**< Channel D Configuration 2, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CH_SW_CFG; /**< Channel Software Configuration, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __IO uint32_t TIMER_UNIT; /**< Timer Unit, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DMA_FIFO; /**< DMA FIFO, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t FIFO_STATUS; /**< FIFO Status, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t INT_SIG_EN; /**< , offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t INT_STATUS; /**< , offset: 0xE0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CHA_B_CNV_RSLT; /**< Channel A and B Conversion Result, offset: 0xF0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CHC_D_CNV_RSLT; /**< Channel C and D Conversion Result, offset: 0x100 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH_SW_CNV_RSLT; /**< Channel Software Conversion Result, offset: 0x110 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA_FIFO_DAT; /**< DMA FIFO Data, offset: 0x120 */ + uint8_t RESERVED_18[12]; + __IO uint32_t ADC_CFG; /**< ADC Configuration, offset: 0x130 */ +} ADC_Type, *ADC_MemMapPtr; +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + + +/* ADC - Register accessors */ +#define ADC_CH_A_CFG1_REG(base) ((base)->CH_A_CFG1) +#define ADC_CH_A_CFG2_REG(base) ((base)->CH_A_CFG2) +#define ADC_CH_B_CFG1_REG(base) ((base)->CH_B_CFG1) +#define ADC_CH_B_CFG2_REG(base) ((base)->CH_B_CFG2) +#define ADC_CH_C_CFG1_REG(base) ((base)->CH_C_CFG1) +#define ADC_CH_C_CFG2_REG(base) ((base)->CH_C_CFG2) +#define ADC_CH_D_CFG1_REG(base) ((base)->CH_D_CFG1) +#define ADC_CH_D_CFG2_REG(base) ((base)->CH_D_CFG2) +#define ADC_CH_SW_CFG_REG(base) ((base)->CH_SW_CFG) +#define ADC_TIMER_UNIT_REG(base) ((base)->TIMER_UNIT) +#define ADC_DMA_FIFO_REG(base) ((base)->DMA_FIFO) +#define ADC_FIFO_STATUS_REG(base) ((base)->FIFO_STATUS) +#define ADC_INT_SIG_EN_REG(base) ((base)->INT_SIG_EN) +#define ADC_INT_EN_REG(base) ((base)->INT_EN) +#define ADC_INT_STATUS_REG(base) ((base)->INT_STATUS) +#define ADC_CHA_B_CNV_RSLT_REG(base) ((base)->CHA_B_CNV_RSLT) +#define ADC_CHC_D_CNV_RSLT_REG(base) ((base)->CHC_D_CNV_RSLT) +#define ADC_CH_SW_CNV_RSLT_REG(base) ((base)->CH_SW_CNV_RSLT) +#define ADC_DMA_FIFO_DAT_REG(base) ((base)->DMA_FIFO_DAT) +#define ADC_ADC_CFG_REG(base) ((base)->ADC_CFG) + +/*! + * @} + */ /* end of group ADC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* CH_A_CFG1 Bit Fields */ +#define ADC_CH_A_CFG1_CHA_TIMER_MASK 0xFFFFFFu +#define ADC_CH_A_CFG1_CHA_TIMER_SHIFT 0 +#define ADC_CH_A_CFG1_CHA_TIMER(x) (((uint32_t)(((uint32_t)(x))<CTRL0) +#define APBH_CTRL0_SET_REG(base) ((base)->CTRL0_SET) +#define APBH_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) +#define APBH_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) +#define APBH_CTRL1_REG(base) ((base)->CTRL1) +#define APBH_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define APBH_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define APBH_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define APBH_CTRL2_REG(base) ((base)->CTRL2) +#define APBH_CTRL2_SET_REG(base) ((base)->CTRL2_SET) +#define APBH_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) +#define APBH_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) +#define APBH_CHANNEL_CTRL_REG(base) ((base)->CHANNEL_CTRL) +#define APBH_CHANNEL_CTRL_SET_REG(base) ((base)->CHANNEL_CTRL_SET) +#define APBH_CHANNEL_CTRL_CLR_REG(base) ((base)->CHANNEL_CTRL_CLR) +#define APBH_CHANNEL_CTRL_TOG_REG(base) ((base)->CHANNEL_CTRL_TOG) +#define APBH_DEVSEL_REG(base) ((base)->DEVSEL) +#define APBH_DMA_BURST_SIZE_REG(base) ((base)->DMA_BURST_SIZE) +#define APBH_DEBUG_REG(base) ((base)->DEBUG) +#define APBH_CH_CURCMDAR_REG(base,index) ((base)->CH[index].CH_CURCMDAR) +#define APBH_CH_NXTCMDAR_REG(base,index) ((base)->CH[index].CH_NXTCMDAR) +#define APBH_CH_CMD_REG(base,index) ((base)->CH[index].CH_CMD) +#define APBH_CH_BAR_REG(base,index) ((base)->CH[index].CH_BAR) +#define APBH_CH_SEMA_REG(base,index) ((base)->CH[index].CH_SEMA) +#define APBH_CH_DEBUG1_REG(base,index) ((base)->CH[index].CH_DEBUG1) +#define APBH_CH_DEBUG2_REG(base,index) ((base)->CH[index].CH_DEBUG2) +#define APBH_VERSION_REG(base) ((base)->VERSION) + +/*! + * @} + */ /* end of group APBH_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- APBH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Masks APBH Register Masks + * @{ + */ + +/* CTRL0 Bit Fields */ +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xFFFFu +#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT 0 +#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define BCH_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define BCH_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define BCH_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define BCH_STATUS0_REG(base) ((base)->STATUS0) +#define BCH_STATUS0_SET_REG(base) ((base)->STATUS0_SET) +#define BCH_STATUS0_CLR_REG(base) ((base)->STATUS0_CLR) +#define BCH_STATUS0_TOG_REG(base) ((base)->STATUS0_TOG) +#define BCH_MODE_REG(base) ((base)->MODE) +#define BCH_MODE_SET_REG(base) ((base)->MODE_SET) +#define BCH_MODE_CLR_REG(base) ((base)->MODE_CLR) +#define BCH_MODE_TOG_REG(base) ((base)->MODE_TOG) +#define BCH_ENCODEPTR_REG(base) ((base)->ENCODEPTR) +#define BCH_ENCODEPTR_SET_REG(base) ((base)->ENCODEPTR_SET) +#define BCH_ENCODEPTR_CLR_REG(base) ((base)->ENCODEPTR_CLR) +#define BCH_ENCODEPTR_TOG_REG(base) ((base)->ENCODEPTR_TOG) +#define BCH_DATAPTR_REG(base) ((base)->DATAPTR) +#define BCH_DATAPTR_SET_REG(base) ((base)->DATAPTR_SET) +#define BCH_DATAPTR_CLR_REG(base) ((base)->DATAPTR_CLR) +#define BCH_DATAPTR_TOG_REG(base) ((base)->DATAPTR_TOG) +#define BCH_METAPTR_REG(base) ((base)->METAPTR) +#define BCH_METAPTR_SET_REG(base) ((base)->METAPTR_SET) +#define BCH_METAPTR_CLR_REG(base) ((base)->METAPTR_CLR) +#define BCH_METAPTR_TOG_REG(base) ((base)->METAPTR_TOG) +#define BCH_LAYOUTSELECT_REG(base) ((base)->LAYOUTSELECT) +#define BCH_LAYOUTSELECT_SET_REG(base) ((base)->LAYOUTSELECT_SET) +#define BCH_LAYOUTSELECT_CLR_REG(base) ((base)->LAYOUTSELECT_CLR) +#define BCH_LAYOUTSELECT_TOG_REG(base) ((base)->LAYOUTSELECT_TOG) +#define BCH_FLASH0LAYOUT0_REG(base) ((base)->FLASH0LAYOUT0) +#define BCH_FLASH0LAYOUT0_SET_REG(base) ((base)->FLASH0LAYOUT0_SET) +#define BCH_FLASH0LAYOUT0_CLR_REG(base) ((base)->FLASH0LAYOUT0_CLR) +#define BCH_FLASH0LAYOUT0_TOG_REG(base) ((base)->FLASH0LAYOUT0_TOG) +#define BCH_FLASH0LAYOUT1_REG(base) ((base)->FLASH0LAYOUT1) +#define BCH_FLASH0LAYOUT1_SET_REG(base) ((base)->FLASH0LAYOUT1_SET) +#define BCH_FLASH0LAYOUT1_CLR_REG(base) ((base)->FLASH0LAYOUT1_CLR) +#define BCH_FLASH0LAYOUT1_TOG_REG(base) ((base)->FLASH0LAYOUT1_TOG) +#define BCH_FLASH1LAYOUT0_REG(base) ((base)->FLASH1LAYOUT0) +#define BCH_FLASH1LAYOUT0_SET_REG(base) ((base)->FLASH1LAYOUT0_SET) +#define BCH_FLASH1LAYOUT0_CLR_REG(base) ((base)->FLASH1LAYOUT0_CLR) +#define BCH_FLASH1LAYOUT0_TOG_REG(base) ((base)->FLASH1LAYOUT0_TOG) +#define BCH_FLASH1LAYOUT1_REG(base) ((base)->FLASH1LAYOUT1) +#define BCH_FLASH1LAYOUT1_SET_REG(base) ((base)->FLASH1LAYOUT1_SET) +#define BCH_FLASH1LAYOUT1_CLR_REG(base) ((base)->FLASH1LAYOUT1_CLR) +#define BCH_FLASH1LAYOUT1_TOG_REG(base) ((base)->FLASH1LAYOUT1_TOG) +#define BCH_FLASH2LAYOUT0_REG(base) ((base)->FLASH2LAYOUT0) +#define BCH_FLASH2LAYOUT0_SET_REG(base) ((base)->FLASH2LAYOUT0_SET) +#define BCH_FLASH2LAYOUT0_CLR_REG(base) ((base)->FLASH2LAYOUT0_CLR) +#define BCH_FLASH2LAYOUT0_TOG_REG(base) ((base)->FLASH2LAYOUT0_TOG) +#define BCH_FLASH2LAYOUT1_REG(base) ((base)->FLASH2LAYOUT1) +#define BCH_FLASH2LAYOUT1_SET_REG(base) ((base)->FLASH2LAYOUT1_SET) +#define BCH_FLASH2LAYOUT1_CLR_REG(base) ((base)->FLASH2LAYOUT1_CLR) +#define BCH_FLASH2LAYOUT1_TOG_REG(base) ((base)->FLASH2LAYOUT1_TOG) +#define BCH_FLASH3LAYOUT0_REG(base) ((base)->FLASH3LAYOUT0) +#define BCH_FLASH3LAYOUT0_SET_REG(base) ((base)->FLASH3LAYOUT0_SET) +#define BCH_FLASH3LAYOUT0_CLR_REG(base) ((base)->FLASH3LAYOUT0_CLR) +#define BCH_FLASH3LAYOUT0_TOG_REG(base) ((base)->FLASH3LAYOUT0_TOG) +#define BCH_FLASH3LAYOUT1_REG(base) ((base)->FLASH3LAYOUT1) +#define BCH_FLASH3LAYOUT1_SET_REG(base) ((base)->FLASH3LAYOUT1_SET) +#define BCH_FLASH3LAYOUT1_CLR_REG(base) ((base)->FLASH3LAYOUT1_CLR) +#define BCH_FLASH3LAYOUT1_TOG_REG(base) ((base)->FLASH3LAYOUT1_TOG) +#define BCH_DEBUG0_REG(base) ((base)->DEBUG0) +#define BCH_DEBUG0_SET_REG(base) ((base)->DEBUG0_SET) +#define BCH_DEBUG0_CLR_REG(base) ((base)->DEBUG0_CLR) +#define BCH_DEBUG0_TOG_REG(base) ((base)->DEBUG0_TOG) +#define BCH_DBGKESREAD_REG(base) ((base)->DBGKESREAD) +#define BCH_DBGKESREAD_SET_REG(base) ((base)->DBGKESREAD_SET) +#define BCH_DBGKESREAD_CLR_REG(base) ((base)->DBGKESREAD_CLR) +#define BCH_DBGKESREAD_TOG_REG(base) ((base)->DBGKESREAD_TOG) +#define BCH_DBGCSFEREAD_REG(base) ((base)->DBGCSFEREAD) +#define BCH_DBGCSFEREAD_SET_REG(base) ((base)->DBGCSFEREAD_SET) +#define BCH_DBGCSFEREAD_CLR_REG(base) ((base)->DBGCSFEREAD_CLR) +#define BCH_DBGCSFEREAD_TOG_REG(base) ((base)->DBGCSFEREAD_TOG) +#define BCH_DBGSYNDGENREAD_REG(base) ((base)->DBGSYNDGENREAD) +#define BCH_DBGSYNDGENREAD_SET_REG(base) ((base)->DBGSYNDGENREAD_SET) +#define BCH_DBGSYNDGENREAD_CLR_REG(base) ((base)->DBGSYNDGENREAD_CLR) +#define BCH_DBGSYNDGENREAD_TOG_REG(base) ((base)->DBGSYNDGENREAD_TOG) +#define BCH_DBGAHBMREAD_REG(base) ((base)->DBGAHBMREAD) +#define BCH_DBGAHBMREAD_SET_REG(base) ((base)->DBGAHBMREAD_SET) +#define BCH_DBGAHBMREAD_CLR_REG(base) ((base)->DBGAHBMREAD_CLR) +#define BCH_DBGAHBMREAD_TOG_REG(base) ((base)->DBGAHBMREAD_TOG) +#define BCH_BLOCKNAME_REG(base) ((base)->BLOCKNAME) +#define BCH_BLOCKNAME_SET_REG(base) ((base)->BLOCKNAME_SET) +#define BCH_BLOCKNAME_CLR_REG(base) ((base)->BLOCKNAME_CLR) +#define BCH_BLOCKNAME_TOG_REG(base) ((base)->BLOCKNAME_TOG) +#define BCH_VERSION_REG(base) ((base)->VERSION) +#define BCH_VERSION_SET_REG(base) ((base)->VERSION_SET) +#define BCH_VERSION_CLR_REG(base) ((base)->VERSION_CLR) +#define BCH_VERSION_TOG_REG(base) ((base)->VERSION_TOG) +#define BCH_DEBUG1_REG(base) ((base)->DEBUG1) +#define BCH_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) +#define BCH_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) +#define BCH_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) + +/*! + * @} + */ /* end of group BCH_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define BCH_CTRL_COMPLETE_IRQ_MASK 0x1u +#define BCH_CTRL_COMPLETE_IRQ_SHIFT 0 +#define BCH_CTRL_RSVD0_MASK 0x2u +#define BCH_CTRL_RSVD0_SHIFT 1 +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK 0x4u +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT 2 +#define BCH_CTRL_BM_ERROR_IRQ_MASK 0x8u +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT 3 +#define BCH_CTRL_RSVD1_MASK 0xF0u +#define BCH_CTRL_RSVD1_SHIFT 4 +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define CAN_CTRL1_REG(base) ((base)->CTRL1) +#define CAN_TIMER_REG(base) ((base)->TIMER) +#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) +#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) +#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) +#define CAN_ECR_REG(base) ((base)->ECR) +#define CAN_ESR1_REG(base) ((base)->ESR1) +#define CAN_IMASK2_REG(base) ((base)->IMASK2) +#define CAN_IMASK1_REG(base) ((base)->IMASK1) +#define CAN_IFLAG2_REG(base) ((base)->IFLAG2) +#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) +#define CAN_CTRL2_REG(base) ((base)->CTRL2) +#define CAN_ESR2_REG(base) ((base)->ESR2) +#define CAN_CRCR_REG(base) ((base)->CRCR) +#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) +#define CAN_RXFIR_REG(base) ((base)->RXFIR) +#define CAN_CS_REG(base,index) ((base)->MB[index].CS) +#define CAN_CS_COUNT 64 +#define CAN_ID_REG(base,index) ((base)->MB[index].ID) +#define CAN_ID_COUNT 64 +#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) +#define CAN_WORD0_COUNT 64 +#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) +#define CAN_WORD1_COUNT 64 +#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) +#define CAN_RXIMR_COUNT 64 +#define CAN_GFWR_REG(base) ((base)->GFWR) + +/*! + * @} + */ /* end of group CAN_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define CAN_MCR_MAXMB_MASK 0x7Fu +#define CAN_MCR_MAXMB_SHIFT 0 +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<GPR0) +#define CCM_GPR0_SET_REG(base) ((base)->GPR0_SET) +#define CCM_GPR0_CLR_REG(base) ((base)->GPR0_CLR) +#define CCM_GPR0_TOG_REG(base) ((base)->GPR0_TOG) +#define CCM_PLL_CTRL_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL) +#define CCM_PLL_CTRL_SET_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_SET) +#define CCM_PLL_CTRL_CLR_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_CLR) +#define CCM_PLL_CTRL_TOG_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_TOG) +#define CCM_CCGR_REG(base,index) ((base)->CCGR[index].CCGR) +#define CCM_CCGR_SET_REG(base,index) ((base)->CCGR[index].CCGR_SET) +#define CCM_CCGR_CLR_REG(base,index) ((base)->CCGR[index].CCGR_CLR) +#define CCM_CCGR_TOG_REG(base,index) ((base)->CCGR[index].CCGR_TOG) +#define CCM_TARGET_ROOT_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT) +#define CCM_TARGET_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_SET) +#define CCM_TARGET_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_CLR) +#define CCM_TARGET_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_TOG) +#define CCM_MISC_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC) +#define CCM_MISC_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_SET) +#define CCM_MISC_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_CLR) +#define CCM_MISC_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_TOG) +#define CCM_POST_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST) +#define CCM_POST_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_SET) +#define CCM_POST_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_CLR) +#define CCM_POST_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_TOG) +#define CCM_PRE_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE) +#define CCM_PRE_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_SET) +#define CCM_PRE_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_CLR) +#define CCM_PRE_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_TOG) +#define CCM_ACCESS_CTRL_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL) +#define CCM_ACCESS_CTRL_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_SET) +#define CCM_ACCESS_CTRL_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_CLR) +#define CCM_ACCESS_CTRL_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_TOG) + +/*! + * @} + */ /* end of group CCM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/* GPR0 Bit Fields */ +#define CCM_GPR0_GP0_MASK 0xFFFFFFFFu +#define CCM_GPR0_GP0_SHIFT 0 +#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x))<PLL_ARM) +#define CCM_ANALOG_PLL_ARM_SET_REG(base) ((base)->PLL_ARM_SET) +#define CCM_ANALOG_PLL_ARM_CLR_REG(base) ((base)->PLL_ARM_CLR) +#define CCM_ANALOG_PLL_ARM_TOG_REG(base) ((base)->PLL_ARM_TOG) +#define CCM_ANALOG_PLL_DDR_REG(base) ((base)->PLL_DDR) +#define CCM_ANALOG_PLL_DDR_SET_REG(base) ((base)->PLL_DDR_SET) +#define CCM_ANALOG_PLL_DDR_CLR_REG(base) ((base)->PLL_DDR_CLR) +#define CCM_ANALOG_PLL_DDR_TOG_REG(base) ((base)->PLL_DDR_TOG) +#define CCM_ANALOG_PLL_DDR_SS_REG(base) ((base)->PLL_DDR_SS) +#define CCM_ANALOG_PLL_DDR_NUM_REG(base) ((base)->PLL_DDR_NUM) +#define CCM_ANALOG_PLL_DDR_DENOM_REG(base) ((base)->PLL_DDR_DENOM) +#define CCM_ANALOG_PLL_480_REG(base) ((base)->PLL_480) +#define CCM_ANALOG_PLL_480_SET_REG(base) ((base)->PLL_480_SET) +#define CCM_ANALOG_PLL_480_CLR_REG(base) ((base)->PLL_480_CLR) +#define CCM_ANALOG_PLL_480_TOG_REG(base) ((base)->PLL_480_TOG) +#define CCM_ANALOG_PFD_480A_REG(base) ((base)->PFD_480A) +#define CCM_ANALOG_PFD_480A_SET_REG(base) ((base)->PFD_480A_SET) +#define CCM_ANALOG_PFD_480A_CLR_REG(base) ((base)->PFD_480A_CLR) +#define CCM_ANALOG_PFD_480A_TOG_REG(base) ((base)->PFD_480A_TOG) +#define CCM_ANALOG_PFD_480B_REG(base) ((base)->PFD_480B) +#define CCM_ANALOG_PFD_480B_SET_REG(base) ((base)->PFD_480B_SET) +#define CCM_ANALOG_PFD_480B_CLR_REG(base) ((base)->PFD_480B_CLR) +#define CCM_ANALOG_PFD_480B_TOG_REG(base) ((base)->PFD_480B_TOG) +#define CCM_ANALOG_PLL_ENET_REG(base) ((base)->PLL_ENET) +#define CCM_ANALOG_PLL_ENET_SET_REG(base) ((base)->PLL_ENET_SET) +#define CCM_ANALOG_PLL_ENET_CLR_REG(base) ((base)->PLL_ENET_CLR) +#define CCM_ANALOG_PLL_ENET_TOG_REG(base) ((base)->PLL_ENET_TOG) +#define CCM_ANALOG_PLL_AUDIO_REG(base) ((base)->PLL_AUDIO) +#define CCM_ANALOG_PLL_AUDIO_SET_REG(base) ((base)->PLL_AUDIO_SET) +#define CCM_ANALOG_PLL_AUDIO_CLR_REG(base) ((base)->PLL_AUDIO_CLR) +#define CCM_ANALOG_PLL_AUDIO_TOG_REG(base) ((base)->PLL_AUDIO_TOG) +#define CCM_ANALOG_PLL_AUDIO_SS_REG(base) ((base)->PLL_AUDIO_SS) +#define CCM_ANALOG_PLL_AUDIO_NUM_REG(base) ((base)->PLL_AUDIO_NUM) +#define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) ((base)->PLL_AUDIO_DENOM) +#define CCM_ANALOG_PLL_VIDEO_REG(base) ((base)->PLL_VIDEO) +#define CCM_ANALOG_PLL_VIDEO_SET_REG(base) ((base)->PLL_VIDEO_SET) +#define CCM_ANALOG_PLL_VIDEO_CLR_REG(base) ((base)->PLL_VIDEO_CLR) +#define CCM_ANALOG_PLL_VIDEO_TOG_REG(base) ((base)->PLL_VIDEO_TOG) +#define CCM_ANALOG_PLL_VIDEO_SS_REG(base) ((base)->PLL_VIDEO_SS) +#define CCM_ANALOG_PLL_VIDEO_NUM_REG(base) ((base)->PLL_VIDEO_NUM) +#define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) ((base)->PLL_VIDEO_DENOM) +#define CCM_ANALOG_CLK_MISC0_REG(base) ((base)->CLK_MISC0) +#define CCM_ANALOG_CLK_MISC0_SET_REG(base) ((base)->CLK_MISC0_SET) +#define CCM_ANALOG_CLK_MISC0_CLR_REG(base) ((base)->CLK_MISC0_CLR) +#define CCM_ANALOG_CLK_MISC0_TOG_REG(base) ((base)->CLK_MISC0_TOG) + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/* PLL_ARM Bit Fields */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<CSICR1) +#define CSI_CSICR2_REG(base) ((base)->CSICR2) +#define CSI_CSICR3_REG(base) ((base)->CSICR3) +#define CSI_CSISTATFIFO_REG(base) ((base)->CSISTATFIFO) +#define CSI_CSIRFIFO_REG(base) ((base)->CSIRFIFO) +#define CSI_CSIRXCNT_REG(base) ((base)->CSIRXCNT) +#define CSI_CSISR_REG(base) ((base)->CSISR) +#define CSI_CSIDMASA_STATFIFO_REG(base) ((base)->CSIDMASA_STATFIFO) +#define CSI_CSIDMATS_STATFIFO_REG(base) ((base)->CSIDMATS_STATFIFO) +#define CSI_CSIDMASA_FB1_REG(base) ((base)->CSIDMASA_FB1) +#define CSI_CSIDMASA_FB2_REG(base) ((base)->CSIDMASA_FB2) +#define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) +#define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) +#define CSI_CSICR18_REG(base) ((base)->CSICR18) + +/*! + * @} + */ /* end of group CSI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/* CSICR1 Bit Fields */ +#define CSI_CSICR1_PIXEL_BIT_MASK 0x1u +#define CSI_CSICR1_PIXEL_BIT_SHIFT 0 +#define CSI_CSICR1_REDGE_MASK 0x2u +#define CSI_CSICR1_REDGE_SHIFT 1 +#define CSI_CSICR1_INV_PCLK_MASK 0x4u +#define CSI_CSICR1_INV_PCLK_SHIFT 2 +#define CSI_CSICR1_INV_DATA_MASK 0x8u +#define CSI_CSICR1_INV_DATA_SHIFT 3 +#define CSI_CSICR1_GCLK_MODE_MASK 0x10u +#define CSI_CSICR1_GCLK_MODE_SHIFT 4 +#define CSI_CSICR1_CLR_RXFIFO_MASK 0x20u +#define CSI_CSICR1_CLR_RXFIFO_SHIFT 5 +#define CSI_CSICR1_CLR_STATFIFO_MASK 0x40u +#define CSI_CSICR1_CLR_STATFIFO_SHIFT 6 +#define CSI_CSICR1_PACK_DIR_MASK 0x80u +#define CSI_CSICR1_PACK_DIR_SHIFT 7 +#define CSI_CSICR1_FCC_MASK 0x100u +#define CSI_CSICR1_FCC_SHIFT 8 +#define CSI_CSICR1_CCIR_EN_MASK 0x400u +#define CSI_CSICR1_CCIR_EN_SHIFT 10 +#define CSI_CSICR1_HSYNC_POL_MASK 0x800u +#define CSI_CSICR1_HSYNC_POL_SHIFT 11 +#define CSI_CSICR1_SOF_INTEN_MASK 0x10000u +#define CSI_CSICR1_SOF_INTEN_SHIFT 16 +#define CSI_CSICR1_SOF_POL_MASK 0x20000u +#define CSI_CSICR1_SOF_POL_SHIFT 17 +#define CSI_CSICR1_RXFF_INTEN_MASK 0x40000u +#define CSI_CSICR1_RXFF_INTEN_SHIFT 18 +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK 0x80000u +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT 19 +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK 0x100000u +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT 20 +#define CSI_CSICR1_STATFF_INTEN_MASK 0x200000u +#define CSI_CSICR1_STATFF_INTEN_SHIFT 21 +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK 0x400000u +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT 22 +#define CSI_CSICR1_RF_OR_INTEN_MASK 0x1000000u +#define CSI_CSICR1_RF_OR_INTEN_SHIFT 24 +#define CSI_CSICR1_SF_OR_INTEN_MASK 0x2000000u +#define CSI_CSICR1_SF_OR_INTEN_SHIFT 25 +#define CSI_CSICR1_COF_INT_EN_MASK 0x4000000u +#define CSI_CSICR1_COF_INT_EN_SHIFT 26 +#define CSI_CSICR1_VIDEO_MODE_MASK 0x8000000u +#define CSI_CSICR1_VIDEO_MODE_SHIFT 27 +#define CSI_CSICR1_PrP_IF_EN_MASK 0x10000000u +#define CSI_CSICR1_PrP_IF_EN_SHIFT 28 +#define CSI_CSICR1_EOF_INT_EN_MASK 0x20000000u +#define CSI_CSICR1_EOF_INT_EN_SHIFT 29 +#define CSI_CSICR1_EXT_VSYNC_MASK 0x40000000u +#define CSI_CSICR1_EXT_VSYNC_SHIFT 30 +#define CSI_CSICR1_SWAP16_EN_MASK 0x80000000u +#define CSI_CSICR1_SWAP16_EN_SHIFT 31 +/* CSICR2 Bit Fields */ +#define CSI_CSICR2_HSC_MASK 0xFFu +#define CSI_CSICR2_HSC_SHIFT 0 +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x))<MSTR) +#define DDRC_STAT_REG(base) ((base)->STAT) +#define DDRC_MRCTRL0_REG(base) ((base)->MRCTRL0) +#define DDRC_MRCTRL1_REG(base) ((base)->MRCTRL1) +#define DDRC_MRSTAT_REG(base) ((base)->MRSTAT) +#define DDRC_DERATEEN_REG(base) ((base)->DERATEEN) +#define DDRC_DERATEINT_REG(base) ((base)->DERATEINT) +#define DDRC_PWRCTL_REG(base) ((base)->PWRCTL) +#define DDRC_PWRTMG_REG(base) ((base)->PWRTMG) +#define DDRC_HWLPCTL_REG(base) ((base)->HWLPCTL) +#define DDRC_RFSHCTL0_REG(base) ((base)->RFSHCTL0) +#define DDRC_RFSHCTL1_REG(base) ((base)->RFSHCTL1) +#define DDRC_RFSHCTL3_REG(base) ((base)->RFSHCTL3) +#define DDRC_RFSHTMG_REG(base) ((base)->RFSHTMG) +#define DDRC_INIT0_REG(base) ((base)->INIT0) +#define DDRC_INIT1_REG(base) ((base)->INIT1) +#define DDRC_INIT2_REG(base) ((base)->INIT2) +#define DDRC_INIT3_REG(base) ((base)->INIT3) +#define DDRC_INIT4_REG(base) ((base)->INIT4) +#define DDRC_INIT5_REG(base) ((base)->INIT5) +#define DDRC_RANKCTL_REG(base) ((base)->RANKCTL) +#define DDRC_DRAMTMG0_REG(base) ((base)->DRAMTMG0) +#define DDRC_DRAMTMG1_REG(base) ((base)->DRAMTMG1) +#define DDRC_DRAMTMG2_REG(base) ((base)->DRAMTMG2) +#define DDRC_DRAMTMG3_REG(base) ((base)->DRAMTMG3) +#define DDRC_DRAMTMG4_REG(base) ((base)->DRAMTMG4) +#define DDRC_DRAMTMG5_REG(base) ((base)->DRAMTMG5) +#define DDRC_DRAMTMG6_REG(base) ((base)->DRAMTMG6) +#define DDRC_DRAMTMG7_REG(base) ((base)->DRAMTMG7) +#define DDRC_DRAMTMG8_REG(base) ((base)->DRAMTMG8) +#define DDRC_ZQCTL0_REG(base) ((base)->ZQCTL0) +#define DDRC_ZQCTL1_REG(base) ((base)->ZQCTL1) +#define DDRC_ZQCTL2_REG(base) ((base)->ZQCTL2) +#define DDRC_ZQSTAT_REG(base) ((base)->ZQSTAT) +#define DDRC_DFITMG0_REG(base) ((base)->DFITMG0) +#define DDRC_DFITMG1_REG(base) ((base)->DFITMG1) +#define DDRC_DFILPCFG0_REG(base) ((base)->DFILPCFG0) +#define DDRC_DFIUPD0_REG(base) ((base)->DFIUPD0) +#define DDRC_DFIUPD1_REG(base) ((base)->DFIUPD1) +#define DDRC_DFIUPD2_REG(base) ((base)->DFIUPD2) +#define DDRC_DFIUPD3_REG(base) ((base)->DFIUPD3) +#define DDRC_DFIMISC_REG(base) ((base)->DFIMISC) +#define DDRC_ADDRMAP0_REG(base) ((base)->ADDRMAP0) +#define DDRC_ADDRMAP1_REG(base) ((base)->ADDRMAP1) +#define DDRC_ADDRMAP2_REG(base) ((base)->ADDRMAP2) +#define DDRC_ADDRMAP3_REG(base) ((base)->ADDRMAP3) +#define DDRC_ADDRMAP4_REG(base) ((base)->ADDRMAP4) +#define DDRC_ADDRMAP5_REG(base) ((base)->ADDRMAP5) +#define DDRC_ADDRMAP6_REG(base) ((base)->ADDRMAP6) +#define DDRC_ODTCFG_REG(base) ((base)->ODTCFG) +#define DDRC_ODTMAP_REG(base) ((base)->ODTMAP) +#define DDRC_SCHED_REG(base) ((base)->SCHED) +#define DDRC_SCHED1_REG(base) ((base)->SCHED1) +#define DDRC_PERFHPR1_REG(base) ((base)->PERFHPR1) +#define DDRC_PERFLPR1_REG(base) ((base)->PERFLPR1) +#define DDRC_PERFWR1_REG(base) ((base)->PERFWR1) +#define DDRC_PERFVPR1_REG(base) ((base)->PERFVPR1) +#define DDRC_PERFVPW1_REG(base) ((base)->PERFVPW1) +#define DDRC_DBG0_REG(base) ((base)->DBG0) +#define DDRC_DBG1_REG(base) ((base)->DBG1) +#define DDRC_DBGCAM_REG(base) ((base)->DBGCAM) +#define DDRC_DBGCMD_REG(base) ((base)->DBGCMD) +#define DDRC_DBGSTAT_REG(base) ((base)->DBGSTAT) +#define DDRC_SWCTL_REG(base) ((base)->SWCTL) +#define DDRC_SWSTAT_REG(base) ((base)->SWSTAT) + +/*! + * @} + */ /* end of group DDRC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- DDRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Masks DDRC Register Masks + * @{ + */ + +/* MSTR Bit Fields */ +#define DDRC_MSTR_DDR3_MASK 0x1u +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_LPDDR2_MASK 0x4u +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR3_MASK 0x8u +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_BURST_MODE_MASK 0x100u +#define DDRC_MSTR_BURST_MODE_SHIFT 8 +#define DDRC_MSTR_BURSTCHOP_MASK 0x200u +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x3000u +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<PSTAT) +#define DDRC_MP_PCCFG_REG(base) ((base)->PCCFG) +#define DDRC_MP_PCFGR_0_REG(base) ((base)->PCFGR_0) +#define DDRC_MP_PCFGW_0_REG(base) ((base)->PCFGW_0) +#define DDRC_MP_PCFGIDMASKCH_0_REG(base,index) ((base)->PCFGID[index].PCFGIDMASKCH_0) +#define DDRC_MP_PCFGIDVALUECH_0_REG(base,index) ((base)->PCFGID[index].PCFGIDVALUECH_0) +#define DDRC_MP_PCTRL_0_REG(base) ((base)->PCTRL_0) +#define DDRC_MP_PCFGQOS0_0_REG(base) ((base)->PCFGQOS0_0) +#define DDRC_MP_PCFGQOS1_0_REG(base) ((base)->PCFGQOS1_0) +#define DDRC_MP_PCFGWQOS0_0_REG(base) ((base)->PCFGWQOS0_0) +#define DDRC_MP_PCFGWQOS1_0_REG(base) ((base)->PCFGWQOS1_0) +#define DDRC_MP_SARBASE_REG(base,index) ((base)->SAR[index].SARBASE) +#define DDRC_MP_SARSIZE_REG(base,index) ((base)->SAR[index].SARSIZE) + +/*! + * @} + */ /* end of group DDRC_MP_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- DDRC_MP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_MP_Register_Masks DDRC_MP Register Masks + * @{ + */ + +/* PSTAT Bit Fields */ +#define DDRC_MP_PSTAT_RD_PORT_BUSY_0_MASK 0x1u +#define DDRC_MP_PSTAT_RD_PORT_BUSY_0_SHIFT 0 +/* PCCFG Bit Fields */ +#define DDRC_MP_PCCFG_GO2CRITICAL_EN_MASK 0x1u +#define DDRC_MP_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_MASK 0x10u +#define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +/* PCFGR_0 Bit Fields */ +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_MASK 0x3FFu +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY(x) (((uint32_t)(((uint32_t)(x))<PHY_CON0) +#define DDR_PHY_PHY_CON1_REG(base) ((base)->PHY_CON1) +#define DDR_PHY_PHY_CON2_REG(base) ((base)->PHY_CON2) +#define DDR_PHY_PHY_CON3_REG(base) ((base)->PHY_CON3) +#define DDR_PHY_PHY_CON4_REG(base) ((base)->PHY_CON4) +#define DDR_PHY_PHY_CON5_REG(base) ((base)->PHY_CON5) +#define DDR_PHY_LP_CON0_REG(base) ((base)->LP_CON0) +#define DDR_PHY_RODT_CON0_REG(base) ((base)->RODT_CON0) +#define DDR_PHY_OFFSET_RD_CON0_REG(base) ((base)->OFFSET_RD_CON0) +#define DDR_PHY_OFFSET_WR_CON0_REG(base) ((base)->OFFSET_WR_CON0) +#define DDR_PHY_GATE_CODE_CON0_REG(base) ((base)->GATE_CODE_CON0) +#define DDR_PHY_SHIFTC_CON0_REG(base) ((base)->SHIFTC_CON0) +#define DDR_PHY_CMD_SDLL_CON0_REG(base) ((base)->CMD_SDLL_CON0) +#define DDR_PHY_LVL_CON0_REG(base) ((base)->LVL_CON0) +#define DDR_PHY_LVL_CON3_REG(base) ((base)->LVL_CON3) +#define DDR_PHY_CMD_DESKEW_CON0_REG(base) ((base)->CMD_DESKEW_CON0) +#define DDR_PHY_CMD_DESKEW_CON1_REG(base) ((base)->CMD_DESKEW_CON1) +#define DDR_PHY_CMD_DESKEW_CON2_REG(base) ((base)->CMD_DESKEW_CON2) +#define DDR_PHY_CMD_DESKEW_CON3_REG(base) ((base)->CMD_DESKEW_CON3) +#define DDR_PHY_CMD_DESKEW_CON4_REG(base) ((base)->CMD_DESKEW_CON4) +#define DDR_PHY_DRVDS_CON0_REG(base) ((base)->DRVDS_CON0) +#define DDR_PHY_MDLL_CON0_REG(base) ((base)->MDLL_CON0) +#define DDR_PHY_MDLL_CON1_REG(base) ((base)->MDLL_CON1) +#define DDR_PHY_ZQ_CON0_REG(base) ((base)->ZQ_CON0) +#define DDR_PHY_ZQ_CON1_REG(base) ((base)->ZQ_CON1) +#define DDR_PHY_ZQ_CON2_REG(base) ((base)->ZQ_CON2) +#define DDR_PHY_RD_DESKEW_CON0_REG(base) ((base)->RD_DESKEW_CON0) +#define DDR_PHY_RD_DESKEW_CON3_REG(base) ((base)->RD_DESKEW_CON3) +#define DDR_PHY_RD_DESKEW_CON6_REG(base) ((base)->RD_DESKEW_CON6) +#define DDR_PHY_RD_DESKEW_CON9_REG(base) ((base)->RD_DESKEW_CON9) +#define DDR_PHY_RD_DESKEW_CON12_REG(base) ((base)->RD_DESKEW_CON12) +#define DDR_PHY_RD_DESKEW_CON15_REG(base) ((base)->RD_DESKEW_CON15) +#define DDR_PHY_RD_DESKEW_CON18_REG(base) ((base)->RD_DESKEW_CON18) +#define DDR_PHY_RD_DESKEW_CON21_REG(base) ((base)->RD_DESKEW_CON21) +#define DDR_PHY_WR_DESKEW_CON0_REG(base) ((base)->WR_DESKEW_CON0) +#define DDR_PHY_WR_DESKEW_CON3_REG(base) ((base)->WR_DESKEW_CON3) +#define DDR_PHY_WR_DESKEW_CON6_REG(base) ((base)->WR_DESKEW_CON6) +#define DDR_PHY_WR_DESKEW_CON9_REG(base) ((base)->WR_DESKEW_CON9) +#define DDR_PHY_WR_DESKEW_CON12_REG(base) ((base)->WR_DESKEW_CON12) +#define DDR_PHY_WR_DESKEW_CON15_REG(base) ((base)->WR_DESKEW_CON15) +#define DDR_PHY_WR_DESKEW_CON18_REG(base) ((base)->WR_DESKEW_CON18) +#define DDR_PHY_WR_DESKEW_CON21_REG(base) ((base)->WR_DESKEW_CON21) +#define DDR_PHY_DM_DESKEW_CON_REG(base) ((base)->DM_DESKEW_CON) +#define DDR_PHY_RDATA0_REG(base) ((base)->RDATA0) +#define DDR_PHY_STAT0_REG(base) ((base)->STAT0) + +/*! + * @} + */ /* end of group DDR_PHY_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- DDR_PHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDR_PHY_Register_Masks DDR_PHY Register Masks + * @{ + */ + +/* PHY_CON0 Bit Fields */ +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB_MASK 0x7u +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB_SHIFT 0 +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB(x) (((uint32_t)(((uint32_t)(x))<RXDATA) +#define ECSPI_TXDATA_REG(base) ((base)->TXDATA) +#define ECSPI_CONREG_REG(base) ((base)->CONREG) +#define ECSPI_CONFIGREG_REG(base) ((base)->CONFIGREG) +#define ECSPI_INTREG_REG(base) ((base)->INTREG) +#define ECSPI_DMAREG_REG(base) ((base)->DMAREG) +#define ECSPI_STATREG_REG(base) ((base)->STATREG) +#define ECSPI_PERIODREG_REG(base) ((base)->PERIODREG) +#define ECSPI_TESTREG_REG(base) ((base)->TESTREG) +#define ECSPI_MSGDATA_REG(base) ((base)->MSGDATA) + +/*! + * @} + */ /* end of group ECSPI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/* RXDATA Bit Fields */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK 0xFFFFFFFFu +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT 0 +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x))<CS[index].CSGCR1) +#define EIM_CSGCR2_REG(base,index) ((base)->CS[index].CSGCR2) +#define EIM_CSRCR1_REG(base,index) ((base)->CS[index].CSRCR1) +#define EIM_CSRCR2_REG(base,index) ((base)->CS[index].CSRCR2) +#define EIM_CSWCR1_REG(base,index) ((base)->CS[index].CSWCR1) +#define EIM_CSWCR2_REG(base,index) ((base)->CS[index].CSWCR2) +#define EIM_WCR_REG(base) ((base)->WCR) +#define EIM_DCR_REG(base) ((base)->DCR) +#define EIM_DSR_REG(base) ((base)->DSR) +#define EIM_WIAR_REG(base) ((base)->WIAR) +#define EIM_EAR_REG(base) ((base)->EAR) + +/*! + * @} + */ /* end of group EIM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/* CSGCR1 Bit Fields */ +#define EIM_CSGCR1_CSEN_MASK 0x1u +#define EIM_CSGCR1_CSEN_SHIFT 0 +#define EIM_CSGCR1_SWR_MASK 0x2u +#define EIM_CSGCR1_SWR_SHIFT 1 +#define EIM_CSGCR1_SRD_MASK 0x4u +#define EIM_CSGCR1_SRD_SHIFT 2 +#define EIM_CSGCR1_MUM_MASK 0x8u +#define EIM_CSGCR1_MUM_SHIFT 3 +#define EIM_CSGCR1_WFL_MASK 0x10u +#define EIM_CSGCR1_WFL_SHIFT 4 +#define EIM_CSGCR1_RFL_MASK 0x20u +#define EIM_CSGCR1_RFL_SHIFT 5 +#define EIM_CSGCR1_CRE_MASK 0x40u +#define EIM_CSGCR1_CRE_SHIFT 6 +#define EIM_CSGCR1_CREP_MASK 0x80u +#define EIM_CSGCR1_CREP_SHIFT 7 +#define EIM_CSGCR1_BL_MASK 0x700u +#define EIM_CSGCR1_BL_SHIFT 8 +#define EIM_CSGCR1_BL(x) (((uint32_t)(((uint32_t)(x))<EIR) +#define ENET_EIMR_REG(base) ((base)->EIMR) +#define ENET_RDAR_REG(base) ((base)->RDAR) +#define ENET_TDAR_REG(base) ((base)->TDAR) +#define ENET_ECR_REG(base) ((base)->ECR) +#define ENET_MMFR_REG(base) ((base)->MMFR) +#define ENET_MSCR_REG(base) ((base)->MSCR) +#define ENET_MIBC_REG(base) ((base)->MIBC) +#define ENET_RCR_REG(base) ((base)->RCR) +#define ENET_TCR_REG(base) ((base)->TCR) +#define ENET_PALR_REG(base) ((base)->PALR) +#define ENET_PAUR_REG(base) ((base)->PAUR) +#define ENET_OPD_REG(base) ((base)->OPD) +#define ENET_TXIC_REG(base,index) ((base)->TXIC[index]) +#define ENET_RXIC_REG(base,index) ((base)->RXIC[index]) +#define ENET_IAUR_REG(base) ((base)->IAUR) +#define ENET_IALR_REG(base) ((base)->IALR) +#define ENET_GAUR_REG(base) ((base)->GAUR) +#define ENET_GALR_REG(base) ((base)->GALR) +#define ENET_TFWR_REG(base) ((base)->TFWR) +#define ENET_RDSR1_REG(base) ((base)->RDSR1) +#define ENET_TDSR1_REG(base) ((base)->TDSR1) +#define ENET_MRBR1_REG(base) ((base)->MRBR1) +#define ENET_RDSR2_REG(base) ((base)->RDSR2) +#define ENET_TDSR2_REG(base) ((base)->TDSR2) +#define ENET_MRBR2_REG(base) ((base)->MRBR2) +#define ENET_RDSR_REG(base) ((base)->RDSR) +#define ENET_TDSR_REG(base) ((base)->TDSR) +#define ENET_MRBR_REG(base) ((base)->MRBR) +#define ENET_RSFL_REG(base) ((base)->RSFL) +#define ENET_RSEM_REG(base) ((base)->RSEM) +#define ENET_RAEM_REG(base) ((base)->RAEM) +#define ENET_RAFL_REG(base) ((base)->RAFL) +#define ENET_TSEM_REG(base) ((base)->TSEM) +#define ENET_TAEM_REG(base) ((base)->TAEM) +#define ENET_TAFL_REG(base) ((base)->TAFL) +#define ENET_TIPG_REG(base) ((base)->TIPG) +#define ENET_FTRL_REG(base) ((base)->FTRL) +#define ENET_TACC_REG(base) ((base)->TACC) +#define ENET_RACC_REG(base) ((base)->RACC) +#define ENET_RCMR_REG(base,index) ((base)->RCMR[index]) +#define ENET_DMACFG_REG(base,index) ((base)->DMACFG[index]) +#define ENET_RDAR1_REG(base) ((base)->RDAR1) +#define ENET_TDAR1_REG(base) ((base)->TDAR1) +#define ENET_RDAR2_REG(base) ((base)->RDAR2) +#define ENET_TDAR2_REG(base) ((base)->TDAR2) +#define ENET_QOS_REG(base) ((base)->QOS) +#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) +#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) +#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) +#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) +#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) +#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) +#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) +#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) +#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) +#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) +#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) +#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) +#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) +#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) +#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) +#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) +#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) +#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) +#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) +#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) +#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) +#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) +#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) +#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) +#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) +#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) +#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) +#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) +#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) +#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) +#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) +#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) +#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) +#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) +#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) +#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) +#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) +#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) +#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) +#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) +#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) +#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) +#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) +#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) +#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) +#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) +#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) +#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) +#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) +#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) +#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) +#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) +#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) +#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) +#define ENET_ATCR_REG(base) ((base)->ATCR) +#define ENET_ATVR_REG(base) ((base)->ATVR) +#define ENET_ATOFF_REG(base) ((base)->ATOFF) +#define ENET_ATPER_REG(base) ((base)->ATPER) +#define ENET_ATCOR_REG(base) ((base)->ATCOR) +#define ENET_ATINC_REG(base) ((base)->ATINC) +#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) +#define ENET_TGSR_REG(base) ((base)->TGSR) +#define ENET_TCSR_REG(base,index) ((base)->TC[index].TCSR) +#define ENET_TCCR_REG(base,index) ((base)->TC[index].TCCR) + +/*! + * @} + */ /* end of group ENET_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/* EIR Bit Fields */ +#define ENET_EIR_RXB1_MASK 0x1u +#define ENET_EIR_RXB1_SHIFT 0 +#define ENET_EIR_RXF1_MASK 0x2u +#define ENET_EIR_RXF1_SHIFT 1 +#define ENET_EIR_TXB1_MASK 0x4u +#define ENET_EIR_TXB1_SHIFT 2 +#define ENET_EIR_TXF1_MASK 0x8u +#define ENET_EIR_TXF1_SHIFT 3 +#define ENET_EIR_RXB2_MASK 0x10u +#define ENET_EIR_RXB2_SHIFT 4 +#define ENET_EIR_RXF2_MASK 0x20u +#define ENET_EIR_RXF2_SHIFT 5 +#define ENET_EIR_TXB2_MASK 0x40u +#define ENET_EIR_TXB2_SHIFT 6 +#define ENET_EIR_TXF2_MASK 0x80u +#define ENET_EIR_TXF2_SHIFT 7 +#define ENET_EIR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIR_RXFLUSH_0_SHIFT 12 +#define ENET_EIR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIR_RXFLUSH_1_SHIFT 13 +#define ENET_EIR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIR_RXFLUSH_2_SHIFT 14 +#define ENET_EIR_TS_TIMER_MASK 0x8000u +#define ENET_EIR_TS_TIMER_SHIFT 15 +#define ENET_EIR_TS_AVAIL_MASK 0x10000u +#define ENET_EIR_TS_AVAIL_SHIFT 16 +#define ENET_EIR_WAKEUP_MASK 0x20000u +#define ENET_EIR_WAKEUP_SHIFT 17 +#define ENET_EIR_PLR_MASK 0x40000u +#define ENET_EIR_PLR_SHIFT 18 +#define ENET_EIR_UN_MASK 0x80000u +#define ENET_EIR_UN_SHIFT 19 +#define ENET_EIR_RL_MASK 0x100000u +#define ENET_EIR_RL_SHIFT 20 +#define ENET_EIR_LC_MASK 0x200000u +#define ENET_EIR_LC_SHIFT 21 +#define ENET_EIR_EBERR_MASK 0x400000u +#define ENET_EIR_EBERR_SHIFT 22 +#define ENET_EIR_MII_MASK 0x800000u +#define ENET_EIR_MII_SHIFT 23 +#define ENET_EIR_RXB_MASK 0x1000000u +#define ENET_EIR_RXB_SHIFT 24 +#define ENET_EIR_RXF_MASK 0x2000000u +#define ENET_EIR_RXF_SHIFT 25 +#define ENET_EIR_TXB_MASK 0x4000000u +#define ENET_EIR_TXB_SHIFT 26 +#define ENET_EIR_TXF_MASK 0x8000000u +#define ENET_EIR_TXF_SHIFT 27 +#define ENET_EIR_GRA_MASK 0x10000000u +#define ENET_EIR_GRA_SHIFT 28 +#define ENET_EIR_BABT_MASK 0x20000000u +#define ENET_EIR_BABT_SHIFT 29 +#define ENET_EIR_BABR_MASK 0x40000000u +#define ENET_EIR_BABR_SHIFT 30 +/* EIMR Bit Fields */ +#define ENET_EIMR_RXB1_MASK 0x1u +#define ENET_EIMR_RXB1_SHIFT 0 +#define ENET_EIMR_RXF1_MASK 0x2u +#define ENET_EIMR_RXF1_SHIFT 1 +#define ENET_EIMR_TXB1_MASK 0x4u +#define ENET_EIMR_TXB1_SHIFT 2 +#define ENET_EIMR_TXF1_MASK 0x8u +#define ENET_EIMR_TXF1_SHIFT 3 +#define ENET_EIMR_RXB2_MASK 0x10u +#define ENET_EIMR_RXB2_SHIFT 4 +#define ENET_EIMR_RXF2_MASK 0x20u +#define ENET_EIMR_RXF2_SHIFT 5 +#define ENET_EIMR_TXB2_MASK 0x40u +#define ENET_EIMR_TXB2_SHIFT 6 +#define ENET_EIMR_TXF2_MASK 0x80u +#define ENET_EIMR_TXF2_SHIFT 7 +#define ENET_EIMR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIMR_RXFLUSH_0_SHIFT 12 +#define ENET_EIMR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIMR_RXFLUSH_1_SHIFT 13 +#define ENET_EIMR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIMR_RXFLUSH_2_SHIFT 14 +#define ENET_EIMR_TS_TIMER_MASK 0x8000u +#define ENET_EIMR_TS_TIMER_SHIFT 15 +#define ENET_EIMR_TS_AVAIL_MASK 0x10000u +#define ENET_EIMR_TS_AVAIL_SHIFT 16 +#define ENET_EIMR_WAKEUP_MASK 0x20000u +#define ENET_EIMR_WAKEUP_SHIFT 17 +#define ENET_EIMR_PLR_MASK 0x40000u +#define ENET_EIMR_PLR_SHIFT 18 +#define ENET_EIMR_UN_MASK 0x80000u +#define ENET_EIMR_UN_SHIFT 19 +#define ENET_EIMR_RL_MASK 0x100000u +#define ENET_EIMR_RL_SHIFT 20 +#define ENET_EIMR_LC_MASK 0x200000u +#define ENET_EIMR_LC_SHIFT 21 +#define ENET_EIMR_EBERR_MASK 0x400000u +#define ENET_EIMR_EBERR_SHIFT 22 +#define ENET_EIMR_MII_MASK 0x800000u +#define ENET_EIMR_MII_SHIFT 23 +#define ENET_EIMR_RXB_MASK 0x1000000u +#define ENET_EIMR_RXB_SHIFT 24 +#define ENET_EIMR_RXF_MASK 0x2000000u +#define ENET_EIMR_RXF_SHIFT 25 +#define ENET_EIMR_TXB_MASK 0x4000000u +#define ENET_EIMR_TXB_SHIFT 26 +#define ENET_EIMR_TXF_MASK 0x8000000u +#define ENET_EIMR_TXF_SHIFT 27 +#define ENET_EIMR_GRA_MASK 0x10000000u +#define ENET_EIMR_GRA_SHIFT 28 +#define ENET_EIMR_BABT_MASK 0x20000000u +#define ENET_EIMR_BABT_SHIFT 29 +#define ENET_EIMR_BABR_MASK 0x40000000u +#define ENET_EIMR_BABR_SHIFT 30 +/* RDAR Bit Fields */ +#define ENET_RDAR_RDAR_MASK 0x1000000u +#define ENET_RDAR_RDAR_SHIFT 24 +/* TDAR Bit Fields */ +#define ENET_TDAR_TDAR_MASK 0x1000000u +#define ENET_TDAR_TDAR_SHIFT 24 +/* ECR Bit Fields */ +#define ENET_ECR_RESET_MASK 0x1u +#define ENET_ECR_RESET_SHIFT 0 +#define ENET_ECR_ETHEREN_MASK 0x2u +#define ENET_ECR_ETHEREN_SHIFT 1 +#define ENET_ECR_MAGICEN_MASK 0x4u +#define ENET_ECR_MAGICEN_SHIFT 2 +#define ENET_ECR_SLEEP_MASK 0x8u +#define ENET_ECR_SLEEP_SHIFT 3 +#define ENET_ECR_EN1588_MASK 0x10u +#define ENET_ECR_EN1588_SHIFT 4 +#define ENET_ECR_SPEED_MASK 0x20u +#define ENET_ECR_SPEED_SHIFT 5 +#define ENET_ECR_DBGEN_MASK 0x40u +#define ENET_ECR_DBGEN_SHIFT 6 +#define ENET_ECR_DBSWP_MASK 0x100u +#define ENET_ECR_DBSWP_SHIFT 8 +#define ENET_ECR_SVLANEN_MASK 0x200u +#define ENET_ECR_SVLANEN_SHIFT 9 +#define ENET_ECR_VLANUSE2ND_MASK 0x400u +#define ENET_ECR_VLANUSE2ND_SHIFT 10 +#define ENET_ECR_SVLANDBL_MASK 0x800u +#define ENET_ECR_SVLANDBL_SHIFT 11 +/* MMFR Bit Fields */ +#define ENET_MMFR_DATA_MASK 0xFFFFu +#define ENET_MMFR_DATA_SHIFT 0 +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define EPDC_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define EPDC_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define EPDC_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define EPDC_WB_ADDR_TCE_REG(base) ((base)->WB_ADDR_TCE) +#define EPDC_WVADDR_REG(base) ((base)->WVADDR) +#define EPDC_WB_ADDR_REG(base) ((base)->WB_ADDR) +#define EPDC_RES_REG(base) ((base)->RES) +#define EPDC_FORMAT_REG(base) ((base)->FORMAT) +#define EPDC_FORMAT_SET_REG(base) ((base)->FORMAT_SET) +#define EPDC_FORMAT_CLR_REG(base) ((base)->FORMAT_CLR) +#define EPDC_FORMAT_TOG_REG(base) ((base)->FORMAT_TOG) +#define EPDC_WB_FIELD0_REG(base) ((base)->WB_FIELD0) +#define EPDC_WB_FIELD1_REG(base) ((base)->WB_FIELD1) +#define EPDC_WB_FIELD2_REG(base) ((base)->WB_FIELD2) +#define EPDC_WB_FIELD3_REG(base) ((base)->WB_FIELD3) +#define EPDC_FIFOCTRL_REG(base) ((base)->FIFOCTRL) +#define EPDC_FIFOCTRL_SET_REG(base) ((base)->FIFOCTRL_SET) +#define EPDC_FIFOCTRL_CLR_REG(base) ((base)->FIFOCTRL_CLR) +#define EPDC_FIFOCTRL_TOG_REG(base) ((base)->FIFOCTRL_TOG) +#define EPDC_UPD_ADDR_REG(base) ((base)->UPD_ADDR) +#define EPDC_UPD_STRIDE_REG(base) ((base)->UPD_STRIDE) +#define EPDC_UPD_CORD_REG(base) ((base)->UPD_CORD) +#define EPDC_UPD_SIZE_REG(base) ((base)->UPD_SIZE) +#define EPDC_UPD_CTRL_REG(base) ((base)->UPD_CTRL) +#define EPDC_UPD_CTRL_SET_REG(base) ((base)->UPD_CTRL_SET) +#define EPDC_UPD_CTRL_CLR_REG(base) ((base)->UPD_CTRL_CLR) +#define EPDC_UPD_CTRL_TOG_REG(base) ((base)->UPD_CTRL_TOG) +#define EPDC_UPD_FIXED_REG(base) ((base)->UPD_FIXED) +#define EPDC_UPD_FIXED_SET_REG(base) ((base)->UPD_FIXED_SET) +#define EPDC_UPD_FIXED_CLR_REG(base) ((base)->UPD_FIXED_CLR) +#define EPDC_UPD_FIXED_TOG_REG(base) ((base)->UPD_FIXED_TOG) +#define EPDC_TEMP_REG(base) ((base)->TEMP) +#define EPDC_AUTOWV_LUT_REG(base) ((base)->AUTOWV_LUT) +#define EPDC_LUT_STANDBY1_REG(base) ((base)->LUT_STANDBY1) +#define EPDC_LUT_STANDBY1_SET_REG(base) ((base)->LUT_STANDBY1_SET) +#define EPDC_LUT_STANDBY1_CLR_REG(base) ((base)->LUT_STANDBY1_CLR) +#define EPDC_LUT_STANDBY1_TOG_REG(base) ((base)->LUT_STANDBY1_TOG) +#define EPDC_LUT_STANDBY2_REG(base) ((base)->LUT_STANDBY2) +#define EPDC_LUT_STANDBY2_SET_REG(base) ((base)->LUT_STANDBY2_SET) +#define EPDC_LUT_STANDBY2_CLR_REG(base) ((base)->LUT_STANDBY2_CLR) +#define EPDC_LUT_STANDBY2_TOG_REG(base) ((base)->LUT_STANDBY2_TOG) +#define EPDC_TCE_CTRL_REG(base) ((base)->TCE_CTRL) +#define EPDC_TCE_CTRL_SET_REG(base) ((base)->TCE_CTRL_SET) +#define EPDC_TCE_CTRL_CLR_REG(base) ((base)->TCE_CTRL_CLR) +#define EPDC_TCE_CTRL_TOG_REG(base) ((base)->TCE_CTRL_TOG) +#define EPDC_TCE_SDCFG_REG(base) ((base)->TCE_SDCFG) +#define EPDC_TCE_SDCFG_SET_REG(base) ((base)->TCE_SDCFG_SET) +#define EPDC_TCE_SDCFG_CLR_REG(base) ((base)->TCE_SDCFG_CLR) +#define EPDC_TCE_SDCFG_TOG_REG(base) ((base)->TCE_SDCFG_TOG) +#define EPDC_TCE_GDCFG_REG(base) ((base)->TCE_GDCFG) +#define EPDC_TCE_GDCFG_SET_REG(base) ((base)->TCE_GDCFG_SET) +#define EPDC_TCE_GDCFG_CLR_REG(base) ((base)->TCE_GDCFG_CLR) +#define EPDC_TCE_GDCFG_TOG_REG(base) ((base)->TCE_GDCFG_TOG) +#define EPDC_TCE_HSCAN1_REG(base) ((base)->TCE_HSCAN1) +#define EPDC_TCE_HSCAN1_SET_REG(base) ((base)->TCE_HSCAN1_SET) +#define EPDC_TCE_HSCAN1_CLR_REG(base) ((base)->TCE_HSCAN1_CLR) +#define EPDC_TCE_HSCAN1_TOG_REG(base) ((base)->TCE_HSCAN1_TOG) +#define EPDC_TCE_HSCAN2_REG(base) ((base)->TCE_HSCAN2) +#define EPDC_TCE_HSCAN2_SET_REG(base) ((base)->TCE_HSCAN2_SET) +#define EPDC_TCE_HSCAN2_CLR_REG(base) ((base)->TCE_HSCAN2_CLR) +#define EPDC_TCE_HSCAN2_TOG_REG(base) ((base)->TCE_HSCAN2_TOG) +#define EPDC_TCE_VSCAN_REG(base) ((base)->TCE_VSCAN) +#define EPDC_TCE_VSCAN_SET_REG(base) ((base)->TCE_VSCAN_SET) +#define EPDC_TCE_VSCAN_CLR_REG(base) ((base)->TCE_VSCAN_CLR) +#define EPDC_TCE_VSCAN_TOG_REG(base) ((base)->TCE_VSCAN_TOG) +#define EPDC_TCE_OE_REG(base) ((base)->TCE_OE) +#define EPDC_TCE_OE_SET_REG(base) ((base)->TCE_OE_SET) +#define EPDC_TCE_OE_CLR_REG(base) ((base)->TCE_OE_CLR) +#define EPDC_TCE_OE_TOG_REG(base) ((base)->TCE_OE_TOG) +#define EPDC_TCE_POLARITY_REG(base) ((base)->TCE_POLARITY) +#define EPDC_TCE_POLARITY_SET_REG(base) ((base)->TCE_POLARITY_SET) +#define EPDC_TCE_POLARITY_CLR_REG(base) ((base)->TCE_POLARITY_CLR) +#define EPDC_TCE_POLARITY_TOG_REG(base) ((base)->TCE_POLARITY_TOG) +#define EPDC_TCE_TIMING1_REG(base) ((base)->TCE_TIMING1) +#define EPDC_TCE_TIMING1_SET_REG(base) ((base)->TCE_TIMING1_SET) +#define EPDC_TCE_TIMING1_CLR_REG(base) ((base)->TCE_TIMING1_CLR) +#define EPDC_TCE_TIMING1_TOG_REG(base) ((base)->TCE_TIMING1_TOG) +#define EPDC_TCE_TIMING2_REG(base) ((base)->TCE_TIMING2) +#define EPDC_TCE_TIMING2_SET_REG(base) ((base)->TCE_TIMING2_SET) +#define EPDC_TCE_TIMING2_CLR_REG(base) ((base)->TCE_TIMING2_CLR) +#define EPDC_TCE_TIMING2_TOG_REG(base) ((base)->TCE_TIMING2_TOG) +#define EPDC_TCE_TIMING3_REG(base) ((base)->TCE_TIMING3) +#define EPDC_TCE_TIMING3_SET_REG(base) ((base)->TCE_TIMING3_SET) +#define EPDC_TCE_TIMING3_CLR_REG(base) ((base)->TCE_TIMING3_CLR) +#define EPDC_TCE_TIMING3_TOG_REG(base) ((base)->TCE_TIMING3_TOG) +#define EPDC_PIGEON_CTRL0_REG(base) ((base)->PIGEON_CTRL0) +#define EPDC_PIGEON_CTRL0_SET_REG(base) ((base)->PIGEON_CTRL0_SET) +#define EPDC_PIGEON_CTRL0_CLR_REG(base) ((base)->PIGEON_CTRL0_CLR) +#define EPDC_PIGEON_CTRL0_TOG_REG(base) ((base)->PIGEON_CTRL0_TOG) +#define EPDC_PIGEON_CTRL1_REG(base) ((base)->PIGEON_CTRL1) +#define EPDC_PIGEON_CTRL1_SET_REG(base) ((base)->PIGEON_CTRL1_SET) +#define EPDC_PIGEON_CTRL1_CLR_REG(base) ((base)->PIGEON_CTRL1_CLR) +#define EPDC_PIGEON_CTRL1_TOG_REG(base) ((base)->PIGEON_CTRL1_TOG) +#define EPDC_IRQ_MASK1_REG(base) ((base)->IRQ_MASK1) +#define EPDC_IRQ_MASK1_SET_REG(base) ((base)->IRQ_MASK1_SET) +#define EPDC_IRQ_MASK1_CLR_REG(base) ((base)->IRQ_MASK1_CLR) +#define EPDC_IRQ_MASK1_TOG_REG(base) ((base)->IRQ_MASK1_TOG) +#define EPDC_IRQ_MASK2_REG(base) ((base)->IRQ_MASK2) +#define EPDC_IRQ_MASK2_SET_REG(base) ((base)->IRQ_MASK2_SET) +#define EPDC_IRQ_MASK2_CLR_REG(base) ((base)->IRQ_MASK2_CLR) +#define EPDC_IRQ_MASK2_TOG_REG(base) ((base)->IRQ_MASK2_TOG) +#define EPDC_IRQ1_REG(base) ((base)->IRQ1) +#define EPDC_IRQ1_SET_REG(base) ((base)->IRQ1_SET) +#define EPDC_IRQ1_CLR_REG(base) ((base)->IRQ1_CLR) +#define EPDC_IRQ1_TOG_REG(base) ((base)->IRQ1_TOG) +#define EPDC_IRQ2_REG(base) ((base)->IRQ2) +#define EPDC_IRQ2_SET_REG(base) ((base)->IRQ2_SET) +#define EPDC_IRQ2_CLR_REG(base) ((base)->IRQ2_CLR) +#define EPDC_IRQ2_TOG_REG(base) ((base)->IRQ2_TOG) +#define EPDC_IRQ_MASK_REG(base) ((base)->IRQ_MASK) +#define EPDC_IRQ_MASK_SET_REG(base) ((base)->IRQ_MASK_SET) +#define EPDC_IRQ_MASK_CLR_REG(base) ((base)->IRQ_MASK_CLR) +#define EPDC_IRQ_MASK_TOG_REG(base) ((base)->IRQ_MASK_TOG) +#define EPDC_IRQ_REG(base) ((base)->IRQ) +#define EPDC_IRQ_SET_REG(base) ((base)->IRQ_SET) +#define EPDC_IRQ_CLR_REG(base) ((base)->IRQ_CLR) +#define EPDC_IRQ_TOG_REG(base) ((base)->IRQ_TOG) +#define EPDC_STATUS_LUTS1_REG(base) ((base)->STATUS_LUTS1) +#define EPDC_STATUS_LUTS1_SET_REG(base) ((base)->STATUS_LUTS1_SET) +#define EPDC_STATUS_LUTS1_CLR_REG(base) ((base)->STATUS_LUTS1_CLR) +#define EPDC_STATUS_LUTS1_TOG_REG(base) ((base)->STATUS_LUTS1_TOG) +#define EPDC_STATUS_LUTS2_REG(base) ((base)->STATUS_LUTS2) +#define EPDC_STATUS_LUTS2_SET_REG(base) ((base)->STATUS_LUTS2_SET) +#define EPDC_STATUS_LUTS2_CLR_REG(base) ((base)->STATUS_LUTS2_CLR) +#define EPDC_STATUS_LUTS2_TOG_REG(base) ((base)->STATUS_LUTS2_TOG) +#define EPDC_STATUS_NEXTLUT_REG(base) ((base)->STATUS_NEXTLUT) +#define EPDC_STATUS_COL1_REG(base) ((base)->STATUS_COL1) +#define EPDC_STATUS_COL1_SET_REG(base) ((base)->STATUS_COL1_SET) +#define EPDC_STATUS_COL1_CLR_REG(base) ((base)->STATUS_COL1_CLR) +#define EPDC_STATUS_COL1_TOG_REG(base) ((base)->STATUS_COL1_TOG) +#define EPDC_STATUS_COL2_REG(base) ((base)->STATUS_COL2) +#define EPDC_STATUS_COL2_SET_REG(base) ((base)->STATUS_COL2_SET) +#define EPDC_STATUS_COL2_CLR_REG(base) ((base)->STATUS_COL2_CLR) +#define EPDC_STATUS_COL2_TOG_REG(base) ((base)->STATUS_COL2_TOG) +#define EPDC_STATUS_REG(base) ((base)->STATUS) +#define EPDC_STATUS_SET_REG(base) ((base)->STATUS_SET) +#define EPDC_STATUS_CLR_REG(base) ((base)->STATUS_CLR) +#define EPDC_STATUS_TOG_REG(base) ((base)->STATUS_TOG) +#define EPDC_UPD_COL_CORD_REG(base) ((base)->UPD_COL_CORD) +#define EPDC_UPD_COL_SIZE_REG(base) ((base)->UPD_COL_SIZE) +#define EPDC_HIST1_PARAM_REG(base) ((base)->HIST1_PARAM) +#define EPDC_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) +#define EPDC_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) +#define EPDC_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) +#define EPDC_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) +#define EPDC_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) +#define EPDC_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) +#define EPDC_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) +#define EPDC_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) +#define EPDC_GPIO_REG(base) ((base)->GPIO) +#define EPDC_GPIO_SET_REG(base) ((base)->GPIO_SET) +#define EPDC_GPIO_CLR_REG(base) ((base)->GPIO_CLR) +#define EPDC_GPIO_TOG_REG(base) ((base)->GPIO_TOG) +#define EPDC_VERSION_REG(base) ((base)->VERSION) +#define EPDC_PIGEON_0_0_REG(base) ((base)->PIGEON_0_0) +#define EPDC_PIGEON_0_1_REG(base) ((base)->PIGEON_0_1) +#define EPDC_PIGEON_0_2_REG(base) ((base)->PIGEON_0_2) +#define EPDC_PIGEON_1_0_REG(base) ((base)->PIGEON_1_0) +#define EPDC_PIGEON_1_1_REG(base) ((base)->PIGEON_1_1) +#define EPDC_PIGEON_1_2_REG(base) ((base)->PIGEON_1_2) +#define EPDC_PIGEON_2_0_REG(base) ((base)->PIGEON_2_0) +#define EPDC_PIGEON_2_1_REG(base) ((base)->PIGEON_2_1) +#define EPDC_PIGEON_2_2_REG(base) ((base)->PIGEON_2_2) +#define EPDC_PIGEON_3_0_REG(base) ((base)->PIGEON_3_0) +#define EPDC_PIGEON_3_1_REG(base) ((base)->PIGEON_3_1) +#define EPDC_PIGEON_3_2_REG(base) ((base)->PIGEON_3_2) +#define EPDC_PIGEON_4_0_REG(base) ((base)->PIGEON_4_0) +#define EPDC_PIGEON_4_1_REG(base) ((base)->PIGEON_4_1) +#define EPDC_PIGEON_4_2_REG(base) ((base)->PIGEON_4_2) +#define EPDC_PIGEON_5_0_REG(base) ((base)->PIGEON_5_0) +#define EPDC_PIGEON_5_1_REG(base) ((base)->PIGEON_5_1) +#define EPDC_PIGEON_5_2_REG(base) ((base)->PIGEON_5_2) +#define EPDC_PIGEON_6_0_REG(base) ((base)->PIGEON_6_0) +#define EPDC_PIGEON_6_1_REG(base) ((base)->PIGEON_6_1) +#define EPDC_PIGEON_6_2_REG(base) ((base)->PIGEON_6_2) +#define EPDC_PIGEON_7_0_REG(base) ((base)->PIGEON_7_0) +#define EPDC_PIGEON_7_1_REG(base) ((base)->PIGEON_7_1) +#define EPDC_PIGEON_7_2_REG(base) ((base)->PIGEON_7_2) +#define EPDC_PIGEON_8_0_REG(base) ((base)->PIGEON_8_0) +#define EPDC_PIGEON_8_1_REG(base) ((base)->PIGEON_8_1) +#define EPDC_PIGEON_8_2_REG(base) ((base)->PIGEON_8_2) +#define EPDC_PIGEON_9_0_REG(base) ((base)->PIGEON_9_0) +#define EPDC_PIGEON_9_1_REG(base) ((base)->PIGEON_9_1) +#define EPDC_PIGEON_9_2_REG(base) ((base)->PIGEON_9_2) +#define EPDC_PIGEON_10_0_REG(base) ((base)->PIGEON_10_0) +#define EPDC_PIGEON_10_1_REG(base) ((base)->PIGEON_10_1) +#define EPDC_PIGEON_10_2_REG(base) ((base)->PIGEON_10_2) +#define EPDC_PIGEON_11_0_REG(base) ((base)->PIGEON_11_0) +#define EPDC_PIGEON_11_1_REG(base) ((base)->PIGEON_11_1) +#define EPDC_PIGEON_11_2_REG(base) ((base)->PIGEON_11_2) +#define EPDC_PIGEON_12_0_REG(base) ((base)->PIGEON_12_0) +#define EPDC_PIGEON_12_1_REG(base) ((base)->PIGEON_12_1) +#define EPDC_PIGEON_12_2_REG(base) ((base)->PIGEON_12_2) +#define EPDC_PIGEON_13_0_REG(base) ((base)->PIGEON_13_0) +#define EPDC_PIGEON_13_1_REG(base) ((base)->PIGEON_13_1) +#define EPDC_PIGEON_13_2_REG(base) ((base)->PIGEON_13_2) +#define EPDC_PIGEON_14_0_REG(base) ((base)->PIGEON_14_0) +#define EPDC_PIGEON_14_1_REG(base) ((base)->PIGEON_14_1) +#define EPDC_PIGEON_14_2_REG(base) ((base)->PIGEON_14_2) +#define EPDC_PIGEON_15_0_REG(base) ((base)->PIGEON_15_0) +#define EPDC_PIGEON_15_1_REG(base) ((base)->PIGEON_15_1) +#define EPDC_PIGEON_15_2_REG(base) ((base)->PIGEON_15_2) +#define EPDC_PIGEON_16_0_REG(base) ((base)->PIGEON_16_0) +#define EPDC_PIGEON_16_1_REG(base) ((base)->PIGEON_16_1) +#define EPDC_PIGEON_16_2_REG(base) ((base)->PIGEON_16_2) + +/*! + * @} + */ /* end of group EPDC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- EPDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPDC_Register_Masks EPDC Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define EPDC_CTRL_LUT_DATA_SWIZZLE_MASK 0x30u +#define EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT 4 +#define EPDC_CTRL_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<PORT1_CNTL) +#define SIM_SETUP_REG(base) ((base)->SETUP) +#define SIM_PORT1_DETECT_REG(base) ((base)->PORT1_DETECT) +#define SIM_XMT_BUF_REG(base) ((base)->XMT_BUF) +#define SIM_RCV_BUF_REG(base) ((base)->RCV_BUF) +#define SIM_PORT0_CNTL_REG(base) ((base)->PORT0_CNTL) +#define SIM_CNTL_REG(base) ((base)->CNTL) +#define SIM_CLK_PRESCALER_REG(base) ((base)->CLK_PRESCALER) +#define SIM_RCV_THRESHOLD_REG(base) ((base)->RCV_THRESHOLD) +#define SIM_ENABLE_REG(base) ((base)->ENABLE) +#define SIM_XMT_STATUS_REG(base) ((base)->XMT_STATUS) +#define SIM_RCV_STATUS_REG(base) ((base)->RCV_STATUS) +#define SIM_INT_MASK_REG(base) ((base)->INT_MASK) +#define SIM_PORT0_DETECT_REG(base) ((base)->PORT0_DETECT) +#define SIM_DATA_FORMAT_REG(base) ((base)->DATA_FORMAT) +#define SIM_XMT_THRESHOLD_REG(base) ((base)->XMT_THRESHOLD) +#define SIM_GUARD_CNTL_REG(base) ((base)->GUARD_CNTL) +#define SIM_OD_CONFIG_REG(base) ((base)->OD_CONFIG) +#define SIM_RESET_CNTL_REG(base) ((base)->RESET_CNTL) +#define SIM_CHAR_WAIT_REG(base) ((base)->CHAR_WAIT) +#define SIM_GPCNT_REG(base) ((base)->GPCNT) +#define SIM_DIVISOR_REG(base) ((base)->DIVISOR) +#define SIM_BWT_REG(base) ((base)->BWT) +#define SIM_BGT_REG(base) ((base)->BGT) +#define SIM_BWT_H_REG(base) ((base)->BWT_H) +#define SIM_XMT_FIFO_STAT_REG(base) ((base)->XMT_FIFO_STAT) +#define SIM_RCV_FIFO_CNT_REG(base) ((base)->RCV_FIFO_CNT) +#define SIM_RCV_FIFO_WPTR_REG(base) ((base)->RCV_FIFO_WPTR) +#define SIM_RCV_FIFO_RPTR_REG(base) ((base)->RCV_FIFO_RPTR) + +/*! + * @} + */ /* end of group SIM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/* PORT1_CNTL Bit Fields */ +#define SIM_PORT1_CNTL_SAPD1_MASK 0x1u +#define SIM_PORT1_CNTL_SAPD1_SHIFT 0 +#define SIM_PORT1_CNTL_SVEN1_MASK 0x2u +#define SIM_PORT1_CNTL_SVEN1_SHIFT 1 +#define SIM_PORT1_CNTL_STEN1_MASK 0x4u +#define SIM_PORT1_CNTL_STEN1_SHIFT 2 +#define SIM_PORT1_CNTL_SRST1_MASK 0x8u +#define SIM_PORT1_CNTL_SRST1_SHIFT 3 +#define SIM_PORT1_CNTL_SCEN1_MASK 0x10u +#define SIM_PORT1_CNTL_SCEN1_SHIFT 4 +#define SIM_PORT1_CNTL_SCSP1_MASK 0x20u +#define SIM_PORT1_CNTL_SCSP1_SHIFT 5 +#define SIM_PORT1_CNTL_VOLT3_1_MASK 0x40u +#define SIM_PORT1_CNTL_VOLT3_1_SHIFT 6 +#define SIM_PORT1_CNTL_SFPD1_MASK 0x80u +#define SIM_PORT1_CNTL_SFPD1_SHIFT 7 +/* SETUP Bit Fields */ +#define SIM_SETUP_AMODE_MASK 0x1u +#define SIM_SETUP_AMODE_SHIFT 0 +#define SIM_SETUP_SPS_MASK 0x2u +#define SIM_SETUP_SPS_SHIFT 1 +/* PORT1_DETECT Bit Fields */ +#define SIM_PORT1_DETECT_SDIM1_MASK 0x1u +#define SIM_PORT1_DETECT_SDIM1_SHIFT 0 +#define SIM_PORT1_DETECT_SDI1_MASK 0x2u +#define SIM_PORT1_DETECT_SDI1_SHIFT 1 +#define SIM_PORT1_DETECT_SPDP1_MASK 0x4u +#define SIM_PORT1_DETECT_SPDP1_SHIFT 2 +#define SIM_PORT1_DETECT_SPDS1_MASK 0x8u +#define SIM_PORT1_DETECT_SPDS1_SHIFT 3 +/* XMT_BUF Bit Fields */ +#define SIM_XMT_BUF_XMT_MASK 0xFFu +#define SIM_XMT_BUF_XMT_SHIFT 0 +#define SIM_XMT_BUF_XMT(x) (((uint32_t)(((uint32_t)(x))<SC) +#define FTM_CNT_REG(base) ((base)->CNT) +#define FTM_MOD_REG(base) ((base)->MOD) +#define FTM_CSC_REG(base,index) ((base)->C[index].CSC) +#define FTM_CV_REG(base,index) ((base)->C[index].CV) +#define FTM_CNTIN_REG(base) ((base)->CNTIN) +#define FTM_STATUS_REG(base) ((base)->STATUS) +#define FTM_MODE_REG(base) ((base)->MODE) +#define FTM_SYNC_REG(base) ((base)->SYNC) +#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) +#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) +#define FTM_COMBINE_REG(base) ((base)->COMBINE) +#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) +#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) +#define FTM_POL_REG(base) ((base)->POL) +#define FTM_FILTER_REG(base) ((base)->FILTER) +#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) +#define FTM_CONF_REG(base) ((base)->CONF) +#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) +#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) +#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) +#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) + +/*! + * @} + */ /* end of group FTM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<LPCR_A7_BSC) +#define GPC_LPCR_A7_AD_REG(base) ((base)->LPCR_A7_AD) +#define GPC_LPCR_M4_REG(base) ((base)->LPCR_M4) +#define GPC_SLPCR_REG(base) ((base)->SLPCR) +#define GPC_MLPCR_REG(base) ((base)->MLPCR) +#define GPC_PGC_ACK_SEL_A7_REG(base) ((base)->PGC_ACK_SEL_A7) +#define GPC_PGC_ACK_SEL_M4_REG(base) ((base)->PGC_ACK_SEL_M4) +#define GPC_MISC_REG(base) ((base)->MISC) +#define GPC_IMR1_CORE0_A7_REG(base) ((base)->IMR1_CORE0_A7) +#define GPC_IMR2_CORE0_A7_REG(base) ((base)->IMR2_CORE0_A7) +#define GPC_IMR3_CORE0_A7_REG(base) ((base)->IMR3_CORE0_A7) +#define GPC_IMR4_CORE0_A7_REG(base) ((base)->IMR4_CORE0_A7) +#define GPC_IMR1_CORE1_A7_REG(base) ((base)->IMR1_CORE1_A7) +#define GPC_IMR2_CORE1_A7_REG(base) ((base)->IMR2_CORE1_A7) +#define GPC_IMR3_CORE1_A7_REG(base) ((base)->IMR3_CORE1_A7) +#define GPC_IMR4_CORE1_A7_REG(base) ((base)->IMR4_CORE1_A7) +#define GPC_IMR1_M4_REG(base) ((base)->IMR1_M4) +#define GPC_IMR2_M4_REG(base) ((base)->IMR2_M4) +#define GPC_IMR3_M4_REG(base) ((base)->IMR3_M4) +#define GPC_IMR4_M4_REG(base) ((base)->IMR4_M4) +#define GPC_ISR1_A7_REG(base) ((base)->ISR1_A7) +#define GPC_ISR2_A7_REG(base) ((base)->ISR2_A7) +#define GPC_ISR3_A7_REG(base) ((base)->ISR3_A7) +#define GPC_ISR4_A7_REG(base) ((base)->ISR4_A7) +#define GPC_ISR1_M4_REG(base) ((base)->ISR1_M4) +#define GPC_ISR2_M4_REG(base) ((base)->ISR2_M4) +#define GPC_ISR3_M4_REG(base) ((base)->ISR3_M4) +#define GPC_ISR4_M4_REG(base) ((base)->ISR4_M4) +#define GPC_SLT_CFG_REG(base,index) ((base)->SLT_CFG[index]) +#define GPC_PGC_CPU_MAPPING_REG(base) ((base)->PGC_CPU_MAPPING) +#define GPC_CPU_PGC_SW_PUP_REQ_REG(base) ((base)->CPU_PGC_SW_PUP_REQ) +#define GPC_PU_PGC_SW_PUP_REQ_REG(base) ((base)->PU_PGC_SW_PUP_REQ) +#define GPC_CPU_PGC_SW_PDN_REQ_REG(base) ((base)->CPU_PGC_SW_PDN_REQ) +#define GPC_PU_PGC_SW_PDN_REQ_REG(base) ((base)->PU_PGC_SW_PDN_REQ) +#define GPC_LPS_A7_REG(base) ((base)->LPS_A7) +#define GPC_LPS_M4_REG(base) ((base)->LPS_M4) +#define GPC_GPC_GPR_REG(base) ((base)->GPC_GPR) +#define GPC_GTOR_REG(base) ((base)->GTOR) +#define GPC_DEBUG_ADDR1_REG(base) ((base)->DEBUG_ADDR1) +#define GPC_DEBUG_ADDR2_REG(base) ((base)->DEBUG_ADDR2) +#define GPC_CPU_PGC_PUP_STATUS1_REG(base) ((base)->CPU_PGC_PUP_STATUS1) +#define GPC_A7_PU_PGC_PUP_STATUS_REG(base,index) ((base)->A7_PU_PGC_PUP_STATUS[index]) +#define GPC_M4_PU_PGC_PUP_STATUS_REG(base,index) ((base)->M4_PU_PGC_PUP_STATUS[index]) +#define GPC_CPU_PGC_PDN_STATUS1_REG(base) ((base)->CPU_PGC_PDN_STATUS1) +#define GPC_A7_PU_PGC_PDN_STATUS_REG(base,index) ((base)->A7_PU_PGC_PDN_STATUS[index]) +#define GPC_M4_PU_PGC_PDN_STATUS_REG(base,index) ((base)->M4_PU_PGC_PDN_STATUS[index]) +#define GPC_A7_MIX_PDN_FLG_REG(base) ((base)->A7_MIX_PDN_FLG) +#define GPC_A7_PU_PDN_FLG_REG(base) ((base)->A7_PU_PDN_FLG) +#define GPC_M4_MIX_PDN_FLG_REG(base) ((base)->M4_MIX_PDN_FLG) +#define GPC_M4_PU_PDN_FLG_REG(base) ((base)->M4_PU_PDN_FLG) + +/*! + * @} + */ /* end of group GPC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/* LPCR_A7_BSC Bit Fields */ +#define GPC_LPCR_A7_BSC_LPM0_MASK 0x3u +#define GPC_LPCR_A7_BSC_LPM0_SHIFT 0 +#define GPC_LPCR_A7_BSC_LPM0(x) (((uint32_t)(((uint32_t)(x))<A7CORE0_CTRL) +#define GPC_PGC_A7CORE0_PUPSCR_REG(base) ((base)->A7CORE0_PUPSCR) +#define GPC_PGC_A7CORE0_PDNSCR_REG(base) ((base)->A7CORE0_PDNSCR) +#define GPC_PGC_A7CORE0_SR_REG(base) ((base)->A7CORE0_SR) +#define GPC_PGC_A7CORE1_CTRL_REG(base) ((base)->A7CORE1_CTRL) +#define GPC_PGC_A7CORE1_PUPSCR_REG(base) ((base)->A7CORE1_PUPSCR) +#define GPC_PGC_A7CORE1_PDNSCR_REG(base) ((base)->A7CORE1_PDNSCR) +#define GPC_PGC_A7CORE1_SR_REG(base) ((base)->A7CORE1_SR) +#define GPC_PGC_A7SCU_CTRL_REG(base) ((base)->A7SCU_CTRL) +#define GPC_PGC_A7SCU_PUPSCR_REG(base) ((base)->A7SCU_PUPSCR) +#define GPC_PGC_A7SCU_PDNSCR_REG(base) ((base)->A7SCU_PDNSCR) +#define GPC_PGC_A7SCU_SR_REG(base) ((base)->A7SCU_SR) +#define GPC_PGC_SCU_AUXSW_REG(base) ((base)->SCU_AUXSW) +#define GPC_PGC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) +#define GPC_PGC_MIX_PUPSCR_REG(base) ((base)->MIX_PUPSCR) +#define GPC_PGC_MIX_PDNSCR_REG(base) ((base)->MIX_PDNSCR) +#define GPC_PGC_MIX_SR_REG(base) ((base)->MIX_SR) +#define GPC_PGC_MIPI_CTRL_REG(base) ((base)->MIPI_CTRL) +#define GPC_PGC_MIPI_PUPSCR_REG(base) ((base)->MIPI_PUPSCR) +#define GPC_PGC_MIPI_PDNSCR_REG(base) ((base)->MIPI_PDNSCR) +#define GPC_PGC_MIPI_SR_REG(base) ((base)->MIPI_SR) +#define GPC_PGC_MIPI_AUXSW_REG(base) ((base)->MIPI_AUXSW) +#define GPC_PGC_PCIE_CTRL_REG(base) ((base)->PCIE_CTRL) +#define GPC_PGC_PCIE_PUPSCR_REG(base) ((base)->PCIE_PUPSCR) +#define GPC_PGC_PCIE_PDNSCR_REG(base) ((base)->PCIE_PDNSCR) +#define GPC_PGC_PCIE_SR_REG(base) ((base)->PCIE_SR) +#define GPC_PGC_PCIE_AUXSW_REG(base) ((base)->PCIE_AUXSW) +#define GPC_PGC_HSIC_CTRL_REG(base) ((base)->HSIC_CTRL) +#define GPC_PGC_HSIC_PUPSCR_REG(base) ((base)->HSIC_PUPSCR) +#define GPC_PGC_HSIC_PDNSCR_REG(base) ((base)->HSIC_PDNSCR) +#define GPC_PGC_HSIC_SR_REG(base) ((base)->HSIC_SR) + +/*! + * @} + */ /* end of group GPC_PGC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPC_PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks + * @{ + */ + +/* A7CORE0_CTRL Bit Fields */ +#define GPC_PGC_A7CORE0_CTRL_PCR_MASK 0x1u +#define GPC_PGC_A7CORE0_CTRL_PCR_SHIFT 0 +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<DR) +#define GPIO_GDIR_REG(base) ((base)->GDIR) +#define GPIO_PSR_REG(base) ((base)->PSR) +#define GPIO_ICR1_REG(base) ((base)->ICR1) +#define GPIO_ICR2_REG(base) ((base)->ICR2) +#define GPIO_IMR_REG(base) ((base)->IMR) +#define GPIO_ISR_REG(base) ((base)->ISR) +#define GPIO_EDGE_SEL_REG(base) ((base)->EDGE_SEL) + +/*! + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* DR Bit Fields */ +#define GPIO_DR_DR_MASK 0xFFFFFFFFu +#define GPIO_DR_DR_SHIFT 0 +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x))<CTRL0) +#define GPMI_CTRL0_SET_REG(base) ((base)->CTRL0_SET) +#define GPMI_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) +#define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) +#define GPMI_COMPARE_REG(base) ((base)->COMPARE) +#define GPMI_ECCCTRL_REG(base) ((base)->ECCCTRL) +#define GPMI_ECCCTRL_SET_REG(base) ((base)->ECCCTRL_SET) +#define GPMI_ECCCTRL_CLR_REG(base) ((base)->ECCCTRL_CLR) +#define GPMI_ECCCTRL_TOG_REG(base) ((base)->ECCCTRL_TOG) +#define GPMI_ECCCOUNT_REG(base) ((base)->ECCCOUNT) +#define GPMI_PAYLOAD_REG(base) ((base)->PAYLOAD) +#define GPMI_AUXILIARY_REG(base) ((base)->AUXILIARY) +#define GPMI_CTRL1_REG(base) ((base)->CTRL1) +#define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define GPMI_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define GPMI_TIMING0_REG(base) ((base)->TIMING0) +#define GPMI_TIMING1_REG(base) ((base)->TIMING1) +#define GPMI_TIMING2_REG(base) ((base)->TIMING2) +#define GPMI_DATA_REG(base) ((base)->DATA) +#define GPMI_STAT_REG(base) ((base)->STAT) +#define GPMI_DEBUG_REG(base) ((base)->DEBUG) +#define GPMI_VERSION_REG(base) ((base)->VERSION) +#define GPMI_DEBUG2_REG(base) ((base)->DEBUG2) +#define GPMI_DEBUG3_REG(base) ((base)->DEBUG3) +#define GPMI_READ_DDR_DLL_CTRL_REG(base) ((base)->READ_DDR_DLL_CTRL) +#define GPMI_READ_DDR_DLL_STS_REG(base) ((base)->READ_DDR_DLL_STS) + +/*! + * @} + */ /* end of group GPMI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/* CTRL0 Bit Fields */ +#define GPMI_CTRL0_XFER_COUNT_MASK 0xFFFFu +#define GPMI_CTRL0_XFER_COUNT_SHIFT 0 +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<CR) +#define GPT_PR_REG(base) ((base)->PR) +#define GPT_SR_REG(base) ((base)->SR) +#define GPT_IR_REG(base) ((base)->IR) +#define GPT_OCR1_REG(base) ((base)->OCR1) +#define GPT_OCR2_REG(base) ((base)->OCR2) +#define GPT_OCR3_REG(base) ((base)->OCR3) +#define GPT_ICR1_REG(base) ((base)->ICR1) +#define GPT_ICR2_REG(base) ((base)->ICR2) +#define GPT_CNT_REG(base) ((base)->CNT) + +/*! + * @} + */ /* end of group GPT_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define GPT_CR_EN_MASK 0x1u +#define GPT_CR_EN_SHIFT 0 +#define GPT_CR_ENMOD_MASK 0x2u +#define GPT_CR_ENMOD_SHIFT 1 +#define GPT_CR_DBGEN_MASK 0x4u +#define GPT_CR_DBGEN_SHIFT 2 +#define GPT_CR_WAITEN_MASK 0x8u +#define GPT_CR_WAITEN_SHIFT 3 +#define GPT_CR_DOZEEN_MASK 0x10u +#define GPT_CR_DOZEEN_SHIFT 4 +#define GPT_CR_STOPEN_MASK 0x20u +#define GPT_CR_STOPEN_SHIFT 5 +#define GPT_CR_CLKSRC_MASK 0x1C0u +#define GPT_CR_CLKSRC_SHIFT 6 +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<IADR) +#define I2C_IFDR_REG(base) ((base)->IFDR) +#define I2C_I2CR_REG(base) ((base)->I2CR) +#define I2C_I2SR_REG(base) ((base)->I2SR) +#define I2C_I2DR_REG(base) ((base)->I2DR) + +/*! + * @} + */ /* end of group I2C_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* IADR Bit Fields */ +#define I2C_IADR_ADR_MASK 0xFEu +#define I2C_IADR_ADR_SHIFT 1 +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x))<TCSR) +#define I2S_TCR1_REG(base) ((base)->TCR1) +#define I2S_TCR2_REG(base) ((base)->TCR2) +#define I2S_TCR3_REG(base) ((base)->TCR3) +#define I2S_TCR4_REG(base) ((base)->TCR4) +#define I2S_TCR5_REG(base) ((base)->TCR5) +#define I2S_TDR_REG(base,index) ((base)->TDR[index]) +#define I2S_TFR_REG(base,index) ((base)->TFR[index]) +#define I2S_TMR_REG(base) ((base)->TMR) +#define I2S_RCSR_REG(base) ((base)->RCSR) +#define I2S_RCR1_REG(base) ((base)->RCR1) +#define I2S_RCR2_REG(base) ((base)->RCR2) +#define I2S_RCR3_REG(base) ((base)->RCR3) +#define I2S_RCR4_REG(base) ((base)->RCR4) +#define I2S_RCR5_REG(base) ((base)->RCR5) +#define I2S_RDR_REG(base,index) ((base)->RDR[index]) +#define I2S_RFR_REG(base,index) ((base)->RFR[index]) +#define I2S_RMR_REG(base) ((base)->RMR) + +/*! + * @} + */ /* end of group I2S_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x1Fu +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO14) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO15) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA08) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA09) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA10) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA11) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA12) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA13) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA14) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA15) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCLK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDLE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDOE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDSHR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE0) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE1) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE2) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE3) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDCLK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDOE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDRL) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDSP) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR0) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR1) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_COM) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_STAT) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_ENABLE) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_HSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_VSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_RESET) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA08) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA09) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA10) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA11) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA12) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA13) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA14) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA15) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA16) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA17) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA18) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA19) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA20) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA21) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA22) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA23) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RTS_B) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_CTS_B) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MOSI) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MISO) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SS0) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MOSI) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MISO) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SS0) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CD_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_WP) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CD_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_WP) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_STROBE) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_MCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD0) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD1) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD2) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD3) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RXC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD0) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD1) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD2) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD3) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TXC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO14) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO15) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA08) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA09) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA10) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA11) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA12) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA13) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA14) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA15) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCLK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDLE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDOE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDSHR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE0) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE1) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE2) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE3) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDCLK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDOE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDRL) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDSP) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR0) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR1) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_COM) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_STAT) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_ENABLE) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_HSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_VSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_RESET) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA08) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA09) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA10) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA11) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA12) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA13) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA14) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA15) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA16) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA17) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA18) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA19) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA20) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA21) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA22) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA23) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RTS_B) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_CTS_B) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MOSI) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MISO) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SS0) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MOSI) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MISO) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SS0) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CD_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_WP) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CD_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_WP) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_STROBE) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_MCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD0) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD1) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD2) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD3) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RXC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD0) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD1) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD2) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD3) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TXC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL) +#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN1_RX_SELECT_INPUT) +#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN2_RX_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_1_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_2_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_3_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_4_SELECT_INPUT) +#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_READY_SELECT_INPUT) +#define IOMUXC_CSI_DATA2_SELECT_INPUT_REG(base) ((base)->CSI_DATA2_SELECT_INPUT) +#define IOMUXC_CSI_DATA3_SELECT_INPUT_REG(base) ((base)->CSI_DATA3_SELECT_INPUT) +#define IOMUXC_CSI_DATA4_SELECT_INPUT_REG(base) ((base)->CSI_DATA4_SELECT_INPUT) +#define IOMUXC_CSI_DATA5_SELECT_INPUT_REG(base) ((base)->CSI_DATA5_SELECT_INPUT) +#define IOMUXC_CSI_DATA6_SELECT_INPUT_REG(base) ((base)->CSI_DATA6_SELECT_INPUT) +#define IOMUXC_CSI_DATA7_SELECT_INPUT_REG(base) ((base)->CSI_DATA7_SELECT_INPUT) +#define IOMUXC_CSI_DATA8_SELECT_INPUT_REG(base) ((base)->CSI_DATA8_SELECT_INPUT) +#define IOMUXC_CSI_DATA9_SELECT_INPUT_REG(base) ((base)->CSI_DATA9_SELECT_INPUT) +#define IOMUXC_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI_HSYNC_SELECT_INPUT) +#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI_PIXCLK_SELECT_INPUT) +#define IOMUXC_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI_VSYNC_SELECT_INPUT) +#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI1_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI1_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI2_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI2_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI3_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI3_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI4_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI4_SS0_B_SELECT_INPUT) +#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_REG(base) ((base)->CCM_ENET1_REF_CLK_SELECT_INPUT) +#define IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_MDIO_SELECT_INPUT) +#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET1_RX_CLK_SELECT_INPUT) +#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_REG(base) ((base)->CCM_ENET2_REF_CLK_SELECT_INPUT) +#define IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_MDIO_SELECT_INPUT) +#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET2_RX_CLK_SELECT_INPUT) +#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_IRQ_SELECT_INPUT) +#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_STAT_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH0_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH1_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH2_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH3_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH4_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH5_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH6_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH7_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHA_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHB_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH0_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH1_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH2_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH3_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH4_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH5_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH6_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH7_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHA_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHB_SELECT_INPUT) +#define IOMUXC_I2C1_SCL_SELECT_INPUT_REG(base) ((base)->I2C1_SCL_SELECT_INPUT) +#define IOMUXC_I2C1_SDA_SELECT_INPUT_REG(base) ((base)->I2C1_SDA_SELECT_INPUT) +#define IOMUXC_I2C2_SCL_SELECT_INPUT_REG(base) ((base)->I2C2_SCL_SELECT_INPUT) +#define IOMUXC_I2C2_SDA_SELECT_INPUT_REG(base) ((base)->I2C2_SDA_SELECT_INPUT) +#define IOMUXC_I2C3_SCL_SELECT_INPUT_REG(base) ((base)->I2C3_SCL_SELECT_INPUT) +#define IOMUXC_I2C3_SDA_SELECT_INPUT_REG(base) ((base)->I2C3_SDA_SELECT_INPUT) +#define IOMUXC_I2C4_SCL_SELECT_INPUT_REG(base) ((base)->I2C4_SCL_SELECT_INPUT) +#define IOMUXC_I2C4_SDA_SELECT_INPUT_REG(base) ((base)->I2C4_SDA_SELECT_INPUT) +#define IOMUXC_KPP_COL0_SELECT_INPUT_REG(base) ((base)->KPP_COL0_SELECT_INPUT) +#define IOMUXC_KPP_COL1_SELECT_INPUT_REG(base) ((base)->KPP_COL1_SELECT_INPUT) +#define IOMUXC_KPP_COL2_SELECT_INPUT_REG(base) ((base)->KPP_COL2_SELECT_INPUT) +#define IOMUXC_KPP_COL3_SELECT_INPUT_REG(base) ((base)->KPP_COL3_SELECT_INPUT) +#define IOMUXC_KPP_COL4_SELECT_INPUT_REG(base) ((base)->KPP_COL4_SELECT_INPUT) +#define IOMUXC_KPP_COL5_SELECT_INPUT_REG(base) ((base)->KPP_COL5_SELECT_INPUT) +#define IOMUXC_KPP_COL6_SELECT_INPUT_REG(base) ((base)->KPP_COL6_SELECT_INPUT) +#define IOMUXC_KPP_COL7_SELECT_INPUT_REG(base) ((base)->KPP_COL7_SELECT_INPUT) +#define IOMUXC_KPP_ROW0_SELECT_INPUT_REG(base) ((base)->KPP_ROW0_SELECT_INPUT) +#define IOMUXC_KPP_ROW1_SELECT_INPUT_REG(base) ((base)->KPP_ROW1_SELECT_INPUT) +#define IOMUXC_KPP_ROW2_SELECT_INPUT_REG(base) ((base)->KPP_ROW2_SELECT_INPUT) +#define IOMUXC_KPP_ROW3_SELECT_INPUT_REG(base) ((base)->KPP_ROW3_SELECT_INPUT) +#define IOMUXC_KPP_ROW4_SELECT_INPUT_REG(base) ((base)->KPP_ROW4_SELECT_INPUT) +#define IOMUXC_KPP_ROW5_SELECT_INPUT_REG(base) ((base)->KPP_ROW5_SELECT_INPUT) +#define IOMUXC_KPP_ROW6_SELECT_INPUT_REG(base) ((base)->KPP_ROW6_SELECT_INPUT) +#define IOMUXC_KPP_ROW7_SELECT_INPUT_REG(base) ((base)->KPP_ROW7_SELECT_INPUT) +#define IOMUXC_LCD_BUSY_SELECT_INPUT_REG(base) ((base)->LCD_BUSY_SELECT_INPUT) +#define IOMUXC_LCD_DATA00_SELECT_INPUT_REG(base) ((base)->LCD_DATA00_SELECT_INPUT) +#define IOMUXC_LCD_DATA01_SELECT_INPUT_REG(base) ((base)->LCD_DATA01_SELECT_INPUT) +#define IOMUXC_LCD_DATA02_SELECT_INPUT_REG(base) ((base)->LCD_DATA02_SELECT_INPUT) +#define IOMUXC_LCD_DATA03_SELECT_INPUT_REG(base) ((base)->LCD_DATA03_SELECT_INPUT) +#define IOMUXC_LCD_DATA04_SELECT_INPUT_REG(base) ((base)->LCD_DATA04_SELECT_INPUT) +#define IOMUXC_LCD_DATA05_SELECT_INPUT_REG(base) ((base)->LCD_DATA05_SELECT_INPUT) +#define IOMUXC_LCD_DATA06_SELECT_INPUT_REG(base) ((base)->LCD_DATA06_SELECT_INPUT) +#define IOMUXC_LCD_DATA07_SELECT_INPUT_REG(base) ((base)->LCD_DATA07_SELECT_INPUT) +#define IOMUXC_LCD_DATA08_SELECT_INPUT_REG(base) ((base)->LCD_DATA08_SELECT_INPUT) +#define IOMUXC_LCD_DATA09_SELECT_INPUT_REG(base) ((base)->LCD_DATA09_SELECT_INPUT) +#define IOMUXC_LCD_DATA10_SELECT_INPUT_REG(base) ((base)->LCD_DATA10_SELECT_INPUT) +#define IOMUXC_LCD_DATA11_SELECT_INPUT_REG(base) ((base)->LCD_DATA11_SELECT_INPUT) +#define IOMUXC_LCD_DATA12_SELECT_INPUT_REG(base) ((base)->LCD_DATA12_SELECT_INPUT) +#define IOMUXC_LCD_DATA13_SELECT_INPUT_REG(base) ((base)->LCD_DATA13_SELECT_INPUT) +#define IOMUXC_LCD_DATA14_SELECT_INPUT_REG(base) ((base)->LCD_DATA14_SELECT_INPUT) +#define IOMUXC_LCD_DATA15_SELECT_INPUT_REG(base) ((base)->LCD_DATA15_SELECT_INPUT) +#define IOMUXC_LCD_DATA16_SELECT_INPUT_REG(base) ((base)->LCD_DATA16_SELECT_INPUT) +#define IOMUXC_LCD_DATA17_SELECT_INPUT_REG(base) ((base)->LCD_DATA17_SELECT_INPUT) +#define IOMUXC_LCD_DATA18_SELECT_INPUT_REG(base) ((base)->LCD_DATA18_SELECT_INPUT) +#define IOMUXC_LCD_DATA19_SELECT_INPUT_REG(base) ((base)->LCD_DATA19_SELECT_INPUT) +#define IOMUXC_LCD_DATA20_SELECT_INPUT_REG(base) ((base)->LCD_DATA20_SELECT_INPUT) +#define IOMUXC_LCD_DATA21_SELECT_INPUT_REG(base) ((base)->LCD_DATA21_SELECT_INPUT) +#define IOMUXC_LCD_DATA22_SELECT_INPUT_REG(base) ((base)->LCD_DATA22_SELECT_INPUT) +#define IOMUXC_LCD_DATA23_SELECT_INPUT_REG(base) ((base)->LCD_DATA23_SELECT_INPUT) +#define IOMUXC_LCD_VSYNC_SELECT_INPUT_REG(base) ((base)->LCD_VSYNC_SELECT_INPUT) +#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI1_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI2_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI3_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS0_SELECT_INPUT) +#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS1_SELECT_INPUT) +#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_PD_SELECT_INPUT) +#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_TRXD_SELECT_INPUT) +#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_PD_SELECT_INPUT) +#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_TRXD_SELECT_INPUT) +#define IOMUXC_UART1_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_RTS_B_SELECT_INPUT) +#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART1_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART2_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_RTS_B_SELECT_INPUT) +#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART2_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART3_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_RTS_B_SELECT_INPUT) +#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART3_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART4_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_RTS_B_SELECT_INPUT) +#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART4_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART5_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_RTS_B_SELECT_INPUT) +#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART5_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART6_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_RTS_B_SELECT_INPUT) +#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART6_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART7_RTS_B_SELECT_INPUT_REG(base) ((base)->UART7_RTS_B_SELECT_INPUT) +#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART7_RX_DATA_SELECT_INPUT) +#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG2_OC_SELECT_INPUT) +#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG1_OC_SELECT_INPUT) +#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG2_ID_SELECT_INPUT) +#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG1_ID_SELECT_INPUT) +#define IOMUXC_SD3_CD_B_SELECT_INPUT_REG(base) ((base)->SD3_CD_B_SELECT_INPUT) +#define IOMUXC_SD3_WP_SELECT_INPUT_REG(base) ((base)->SD3_WP_SELECT_INPUT) + +/*! + * @} + */ /* end of group IOMUXC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/* SW_MUX_CTL_PAD_GPIO1_IO08 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<GPR0) +#define IOMUXC_GPR_GPR1_REG(base) ((base)->GPR1) +#define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2) +#define IOMUXC_GPR_GPR3_REG(base) ((base)->GPR3) +#define IOMUXC_GPR_GPR4_REG(base) ((base)->GPR4) +#define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5) +#define IOMUXC_GPR_GPR6_REG(base) ((base)->GPR6) +#define IOMUXC_GPR_GPR7_REG(base) ((base)->GPR7) +#define IOMUXC_GPR_GPR8_REG(base) ((base)->GPR8) +#define IOMUXC_GPR_GPR9_REG(base) ((base)->GPR9) +#define IOMUXC_GPR_GPR10_REG(base) ((base)->GPR10) +#define IOMUXC_GPR_GPR11_REG(base) ((base)->GPR11) +#define IOMUXC_GPR_GPR12_REG(base) ((base)->GPR12) +#define IOMUXC_GPR_GPR13_REG(base) ((base)->GPR13) +#define IOMUXC_GPR_GPR14_REG(base) ((base)->GPR14) +#define IOMUXC_GPR_GPR15_REG(base) ((base)->GPR15) +#define IOMUXC_GPR_GPR16_REG(base) ((base)->GPR16) +#define IOMUXC_GPR_GPR17_REG(base) ((base)->GPR17) +#define IOMUXC_GPR_GPR18_REG(base) ((base)->GPR18) +#define IOMUXC_GPR_GPR19_REG(base) ((base)->GPR19) +#define IOMUXC_GPR_GPR20_REG(base) ((base)->GPR20) +#define IOMUXC_GPR_GPR21_REG(base) ((base)->GPR21) +#define IOMUXC_GPR_GPR22_REG(base) ((base)->GPR22) + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/* GPR0 Bit Fields */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 +/* GPR1 Bit Fields */ +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS0_MASK 0x1u +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS0_SHIFT 0 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0_MASK 0x6u +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0_SHIFT 1 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO00) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_REG(base) ((base)->SW_PAD_CTL_PAD_TEST_MODE) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_REG(base) ((base)->SW_PAD_CTL_PAD_SRC_POR_B) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE0) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE1) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks + * @{ + */ + +/* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<IOMUXC_LPSR_GPR0) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_REG(base) ((base)->IOMUXC_LPSR_GPR1) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_REG(base) ((base)->IOMUXC_LPSR_GPR2) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_REG(base) ((base)->IOMUXC_LPSR_GPR3) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_REG(base) ((base)->IOMUXC_LPSR_GPR4) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_REG(base) ((base)->IOMUXC_LPSR_GPR5) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_REG(base) ((base)->IOMUXC_LPSR_GPR6) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_REG(base) ((base)->IOMUXC_LPSR_GPR7) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_REG(base) ((base)->IOMUXC_LPSR_GPR8) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_REG(base) ((base)->IOMUXC_LPSR_GPR9) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_REG(base) ((base)->IOMUXC_LPSR_GPR10) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_REG(base) ((base)->IOMUXC_LPSR_GPR11) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_REG(base) ((base)->IOMUXC_LPSR_GPR12) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_REG(base) ((base)->IOMUXC_LPSR_GPR13) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_REG(base) ((base)->IOMUXC_LPSR_GPR14) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_REG(base) ((base)->IOMUXC_LPSR_GPR15) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_REG(base) ((base)->IOMUXC_LPSR_GPR16) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_REG(base) ((base)->IOMUXC_LPSR_GPR17) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_REG(base) ((base)->IOMUXC_LPSR_GPR18) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_REG(base) ((base)->IOMUXC_LPSR_GPR19) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_REG(base) ((base)->IOMUXC_LPSR_GPR20) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_REG(base) ((base)->IOMUXC_LPSR_GPR21) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_REG(base) ((base)->IOMUXC_LPSR_GPR22) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_GPR_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_GPR_Register_Masks IOMUXC_LPSR_GPR Register Masks + * @{ + */ + +/* IOMUXC_LPSR_GPR0 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP(x) (((uint32_t)(((uint32_t)(x))<KPCR) +#define KPP_KPSR_REG(base) ((base)->KPSR) +#define KPP_KDDR_REG(base) ((base)->KDDR) +#define KPP_KPDR_REG(base) ((base)->KPDR) + +/*! + * @} + */ /* end of group KPP_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/* KPCR Bit Fields */ +#define KPP_KPCR_KRE_MASK 0xFFu +#define KPP_KPCR_KRE_SHIFT 0 +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x))<RL) +#define LCDIF_RL_SET_REG(base) ((base)->RL_SET) +#define LCDIF_RL_CLR_REG(base) ((base)->RL_CLR) +#define LCDIF_RL_TOG_REG(base) ((base)->RL_TOG) +#define LCDIF_CTRL1_REG(base) ((base)->CTRL1) +#define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define LCDIF_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define LCDIF_CTRL2_REG(base) ((base)->CTRL2) +#define LCDIF_CTRL2_SET_REG(base) ((base)->CTRL2_SET) +#define LCDIF_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) +#define LCDIF_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) +#define LCDIF_TRANSFER_COUNT_REG(base) ((base)->TRANSFER_COUNT) +#define LCDIF_CUR_BUF_REG(base) ((base)->CUR_BUF) +#define LCDIF_NEXT_BUF_REG(base) ((base)->NEXT_BUF) +#define LCDIF_TIMING_REG(base) ((base)->TIMING) +#define LCDIF_VDCTRL0_REG(base) ((base)->VDCTRL0) +#define LCDIF_VDCTRL0_SET_REG(base) ((base)->VDCTRL0_SET) +#define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR) +#define LCDIF_VDCTRL0_TOG_REG(base) ((base)->VDCTRL0_TOG) +#define LCDIF_VDCTRL1_REG(base) ((base)->VDCTRL1) +#define LCDIF_VDCTRL2_REG(base) ((base)->VDCTRL2) +#define LCDIF_VDCTRL3_REG(base) ((base)->VDCTRL3) +#define LCDIF_VDCTRL4_REG(base) ((base)->VDCTRL4) +#define LCDIF_DVICTRL0_REG(base) ((base)->DVICTRL0) +#define LCDIF_DVICTRL1_REG(base) ((base)->DVICTRL1) +#define LCDIF_DVICTRL2_REG(base) ((base)->DVICTRL2) +#define LCDIF_DVICTRL3_REG(base) ((base)->DVICTRL3) +#define LCDIF_DVICTRL4_REG(base) ((base)->DVICTRL4) +#define LCDIF_CSC_COEFF0_REG(base) ((base)->CSC_COEFF0) +#define LCDIF_CSC_COEFF1_REG(base) ((base)->CSC_COEFF1) +#define LCDIF_CSC_COEFF2_REG(base) ((base)->CSC_COEFF2) +#define LCDIF_CSC_COEFF3_REG(base) ((base)->CSC_COEFF3) +#define LCDIF_CSC_COEFF4_REG(base) ((base)->CSC_COEFF4) +#define LCDIF_CSC_OFFSET_REG(base) ((base)->CSC_OFFSET) +#define LCDIF_CSC_LIMIT_REG(base) ((base)->CSC_LIMIT) +#define LCDIF_DATA_REG(base) ((base)->DATA) +#define LCDIF_BM_ERROR_STAT_REG(base) ((base)->BM_ERROR_STAT) +#define LCDIF_CRC_STAT_REG(base) ((base)->CRC_STAT) +#define LCDIF_STAT_REG(base) ((base)->STAT) +#define LCDIF_VERSION_REG(base) ((base)->VERSION) +#define LCDIF_DEBUG0_REG(base) ((base)->DEBUG0) +#define LCDIF_DEBUG1_REG(base) ((base)->DEBUG1) +#define LCDIF_DEBUG2_REG(base) ((base)->DEBUG2) +#define LCDIF_THRES_REG(base) ((base)->THRES) +#define LCDIF_AS_CTRL_REG(base) ((base)->AS_CTRL) +#define LCDIF_AS_BUF_REG(base) ((base)->AS_BUF) +#define LCDIF_AS_NEXT_BUF_REG(base) ((base)->AS_NEXT_BUF) +#define LCDIF_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) +#define LCDIF_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) +#define LCDIF_SYNC_DELAY_REG(base) ((base)->SYNC_DELAY) +#define LCDIF_DEBUG3_REG(base) ((base)->DEBUG3) +#define LCDIF_DEBUG4_REG(base) ((base)->DEBUG4) +#define LCDIF_DEBUG5_REG(base) ((base)->DEBUG5) + +/*! + * @} + */ /* end of group LCDIF_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/* RL Bit Fields */ +#define LCDIF_RL_RUN_MASK 0x1u +#define LCDIF_RL_RUN_SHIFT 0 +#define LCDIF_RL_DATA_FORMAT_24_BIT_MASK 0x2u +#define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT 1 +#define LCDIF_RL_DATA_FORMAT_18_BIT_MASK 0x4u +#define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT 2 +#define LCDIF_RL_DATA_FORMAT_16_BIT_MASK 0x8u +#define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT 3 +#define LCDIF_RL_RSRVD0_MASK 0x10u +#define LCDIF_RL_RSRVD0_SHIFT 4 +#define LCDIF_RL_MASTER_MASK 0x20u +#define LCDIF_RL_MASTER_SHIFT 5 +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK 0x40u +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT 6 +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK 0x80u +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT 7 +#define LCDIF_RL_WORD_LENGTH_MASK 0x300u +#define LCDIF_RL_WORD_LENGTH_SHIFT 8 +#define LCDIF_RL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<PCCCR) +#define LMEM_PCCLCR_REG(base) ((base)->PCCLCR) +#define LMEM_PCCSAR_REG(base) ((base)->PCCSAR) +#define LMEM_PCCCVR_REG(base) ((base)->PCCCVR) +#define LMEM_PSCCR_REG(base) ((base)->PSCCR) +#define LMEM_PSCLCR_REG(base) ((base)->PSCLCR) +#define LMEM_PSCSAR_REG(base) ((base)->PSCSAR) +#define LMEM_PSCCVR_REG(base) ((base)->PSCCVR) + +/*! + * @} + */ /* end of group LMEM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- LMEM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Masks LMEM Register Masks + * @{ + */ + +/* PCCCR Bit Fields */ +#define LMEM_PCCCR_ENCACHE_MASK 0x1u +#define LMEM_PCCCR_ENCACHE_SHIFT 0 +#define LMEM_PCCCR_ENWRBUF_MASK 0x2u +#define LMEM_PCCCR_ENWRBUF_SHIFT 1 +#define LMEM_PCCCR_PCCR2_MASK 0x4u +#define LMEM_PCCCR_PCCR2_SHIFT 2 +#define LMEM_PCCCR_PCCR3_MASK 0x8u +#define LMEM_PCCCR_PCCR3_SHIFT 3 +#define LMEM_PCCCR_INVW0_MASK 0x1000000u +#define LMEM_PCCCR_INVW0_SHIFT 24 +#define LMEM_PCCCR_PUSHW0_MASK 0x2000000u +#define LMEM_PCCCR_PUSHW0_SHIFT 25 +#define LMEM_PCCCR_INVW1_MASK 0x4000000u +#define LMEM_PCCCR_INVW1_SHIFT 26 +#define LMEM_PCCCR_PUSHW1_MASK 0x8000000u +#define LMEM_PCCCR_PUSHW1_SHIFT 27 +#define LMEM_PCCCR_GO_MASK 0x80000000u +#define LMEM_PCCCR_GO_SHIFT 31 +/* PCCLCR Bit Fields */ +#define LMEM_PCCLCR_LGO_MASK 0x1u +#define LMEM_PCCLCR_LGO_SHIFT 0 +#define LMEM_PCCLCR_CACHEADDR_MASK 0x1FFCu +#define LMEM_PCCLCR_CACHEADDR_SHIFT 2 +#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<PLASC) +#define MCM_PLAMC_REG(base) ((base)->PLAMC) +#define MCM_FADR_REG(base) ((base)->FADR) +#define MCM_FATR_REG(base) ((base)->FATR) +#define MCM_FDR_REG(base) ((base)->FDR) + +/*! + * @} + */ /* end of group MCM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/* PLASC Bit Fields */ +#define MCM_PLASC_ASC_MASK 0xFFu +#define MCM_PLASC_ASC_SHIFT 0 +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CSIS_CMN_CTRL) +#define MIPI_CSI2_CSIS_CLK_CTRL_REG(base) ((base)->CSIS_CLK_CTRL) +#define MIPI_CSI2_CSIS_INT_MSK_REG(base) ((base)->CSIS_INT_MSK) +#define MIPI_CSI2_CSIS_INT_SRC_REG(base) ((base)->CSIS_INT_SRC) +#define MIPI_CSI2_DPHY_STATUS_REG(base) ((base)->DPHY_STATUS) +#define MIPI_CSI2_DPHY_CMN_CTRL_REG(base) ((base)->DPHY_CMN_CTRL) +#define MIPI_CSI2_DPHY_BCTRL_L_REG(base) ((base)->DPHY_BCTRL_L) +#define MIPI_CSI2_DPHY_BCTRL_H_REG(base) ((base)->DPHY_BCTRL_H) +#define MIPI_CSI2_DPHY_SCTRL_L_REG(base) ((base)->DPHY_SCTRL_L) +#define MIPI_CSI2_DPHY_SCTRL_H_REG(base) ((base)->DPHY_SCTRL_H) +#define MIPI_CSI2_ISP_CONFIG_CH0_REG(base) ((base)->ISP_CONFIG_CH0) +#define MIPI_CSI2_ISP_RESOL_CH0_REG(base) ((base)->ISP_RESOL_CH0) +#define MIPI_CSI2_ISP_SYNC_CH0_REG(base) ((base)->ISP_SYNC_CH0) +#define MIPI_CSI2_SDW_CONFIG_CH0_REG(base) ((base)->SDW_CONFIG_CH0) +#define MIPI_CSI2_SDW_RESOL_CH0_REG(base) ((base)->SDW_RESOL_CH0) +#define MIPI_CSI2_SDW_SYNC_CH0_REG(base) ((base)->SDW_SYNC_CH0) +#define MIPI_CSI2_DBG_CTRL_REG(base) ((base)->DBG_CTRL) +#define MIPI_CSI2_DBG_INTR_MSK_REG(base) ((base)->DBG_INTR_MSK) +#define MIPI_CSI2_DBG_INTR_SRC_REG(base) ((base)->DBG_INTR_SRC) +#define MIPI_CSI2_NON_IMG_DATA_REG(base) ((base)->NON_IMG_DATA) + +/*! + * @} + */ /* end of group MIPI_CSI2_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MIPI_CSI2 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_CSI2_Register_Masks MIPI_CSI2 Register Masks + * @{ + */ + +/* CSIS_CMN_CTRL Bit Fields */ +#define MIPI_CSI2_CSIS_CMN_CTRL_CSI_EN_MASK 0x1u +#define MIPI_CSI2_CSIS_CMN_CTRL_CSI_EN_SHIFT 0 +#define MIPI_CSI2_CSIS_CMN_CTRL_SW_REST_MASK 0x2u +#define MIPI_CSI2_CSIS_CMN_CTRL_SW_REST_SHIFT 1 +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_MASK 0x4u +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_SHIFT 2 +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_MASK 0xF8u +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_SHIFT 3 +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<VERSION) +#define MIPI_DSI_STATUS_REG(base) ((base)->STATUS) +#define MIPI_DSI_RGB_STATUS_REG(base) ((base)->RGB_STATUS) +#define MIPI_DSI_SWRST_REG(base) ((base)->SWRST) +#define MIPI_DSI_CLKCTRL_REG(base) ((base)->CLKCTRL) +#define MIPI_DSI_TIMEOUT_REG(base) ((base)->TIMEOUT) +#define MIPI_DSI_CONFIG_REG(base) ((base)->CONFIG) +#define MIPI_DSI_ESCMODE_REG(base) ((base)->ESCMODE) +#define MIPI_DSI_MDRESOL_REG(base) ((base)->MDRESOL) +#define MIPI_DSI_MVPORCH_REG(base) ((base)->MVPORCH) +#define MIPI_DSI_MHPORCH_REG(base) ((base)->MHPORCH) +#define MIPI_DSI_MSYNC_REG(base) ((base)->MSYNC) +#define MIPI_DSI_SDRESOL_REG(base) ((base)->SDRESOL) +#define MIPI_DSI_INTSRC_REG(base) ((base)->INTSRC) +#define MIPI_DSI_INTMSK_REG(base) ((base)->INTMSK) +#define MIPI_DSI_PKTHDR_REG(base) ((base)->PKTHDR) +#define MIPI_DSI_PAYLOAD_REG(base) ((base)->PAYLOAD) +#define MIPI_DSI_RXFIFO_REG(base) ((base)->RXFIFO) +#define MIPI_DSI_FIFOTHLD_REG(base) ((base)->FIFOTHLD) +#define MIPI_DSI_FIFOCTRL_REG(base) ((base)->FIFOCTRL) +#define MIPI_DSI_MEMACCHR_REG(base) ((base)->MEMACCHR) +#define MIPI_DSI_MULTI_PKT_REG(base) ((base)->MULTI_PKT) +#define MIPI_DSI_PLLCTRL_1G_REG(base) ((base)->PLLCTRL_1G) +#define MIPI_DSI_PLLCTRL_REG(base) ((base)->PLLCTRL) +#define MIPI_DSI_PLLCTRL1_REG(base) ((base)->PLLCTRL1) +#define MIPI_DSI_PLLCTRL2_REG(base) ((base)->PLLCTRL2) +#define MIPI_DSI_PLLTMR_REG(base) ((base)->PLLTMR) +#define MIPI_DSI_PHYCTRL_B1_REG(base) ((base)->PHYCTRL_B1) +#define MIPI_DSI_PHYCTRL_B2_REG(base) ((base)->PHYCTRL_B2) +#define MIPI_DSI_PHYCTRL_M1_REG(base) ((base)->PHYCTRL_M1) +#define MIPI_DSI_PHYCTRL_M2_REG(base) ((base)->PHYCTRL_M2) +#define MIPI_DSI_PHYTIMING_REG(base) ((base)->PHYTIMING) +#define MIPI_DSI_PHYTIMING1_REG(base) ((base)->PHYTIMING1) +#define MIPI_DSI_PHYTIMING2_REG(base) ((base)->PHYTIMING2) + +/*! + * @} + */ /* end of group MIPI_DSI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MIPI_DSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks + * @{ + */ + +/* VERSION Bit Fields */ +#define MIPI_DSI_VERSION_VERSION_MASK 0xFFFFFFFFu +#define MIPI_DSI_VERSION_VERSION_SHIFT 0 +#define MIPI_DSI_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x))<TR[index]) +#define MU_TR_COUNT 4 +#define MU_RR_REG(base,index) ((base)->RR[index]) +#define MU_RR_COUNT 4 +#define MU_SR_REG(base) ((base)->SR) +#define MU_CR_REG(base) ((base)->CR) + +/*! + * @} + */ /* end of group MU_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/* TR Bit Fields */ +#define MU_TR_TR0_MASK 0xFFFFFFFFu +#define MU_TR_TR0_SHIFT 0 +#define MU_TR_TR0(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define OCOTP_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define OCOTP_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define OCOTP_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define OCOTP_TIMING_REG(base) ((base)->TIMING) +#define OCOTP_DATA0_REG(base) ((base)->DATA0) +#define OCOTP_DATA1_REG(base) ((base)->DATA1) +#define OCOTP_DATA2_REG(base) ((base)->DATA2) +#define OCOTP_DATA3_REG(base) ((base)->DATA3) +#define OCOTP_READ_CTRL_REG(base) ((base)->READ_CTRL) +#define OCOTP_READ_FUSE_DATA0_REG(base) ((base)->READ_FUSE_DATA0) +#define OCOTP_READ_FUSE_DATA1_REG(base) ((base)->READ_FUSE_DATA1) +#define OCOTP_READ_FUSE_DATA2_REG(base) ((base)->READ_FUSE_DATA2) +#define OCOTP_READ_FUSE_DATA3_REG(base) ((base)->READ_FUSE_DATA3) +#define OCOTP_SW_STICKY_REG(base) ((base)->SW_STICKY) +#define OCOTP_SCS_REG(base) ((base)->SCS) +#define OCOTP_SCS_SET_REG(base) ((base)->SCS_SET) +#define OCOTP_SCS_CLR_REG(base) ((base)->SCS_CLR) +#define OCOTP_SCS_TOG_REG(base) ((base)->SCS_TOG) +#define OCOTP_CRC_ADDR_REG(base) ((base)->CRC_ADDR) +#define OCOTP_CRC_VALUE_REG(base) ((base)->CRC_VALUE) +#define OCOTP_VERSION_REG(base) ((base)->VERSION) +#define OCOTP_LOCK_REG(base) ((base)->LOCK) +#define OCOTP_TESTER0_REG(base) ((base)->TESTER0) +#define OCOTP_TESTER1_REG(base) ((base)->TESTER1) +#define OCOTP_TESTER2_REG(base) ((base)->TESTER2) +#define OCOTP_TESTER3_REG(base) ((base)->TESTER3) +#define OCOTP_TESTER4_REG(base) ((base)->TESTER4) +#define OCOTP_TESTER5_REG(base) ((base)->TESTER5) +#define OCOTP_BOOT_CFG0_REG(base) ((base)->BOOT_CFG0) +#define OCOTP_BOOT_CFG1_REG(base) ((base)->BOOT_CFG1) +#define OCOTP_BOOT_CFG2_REG(base) ((base)->BOOT_CFG2) +#define OCOTP_BOOT_CFG3_REG(base) ((base)->BOOT_CFG3) +#define OCOTP_BOOT_CFG4_REG(base) ((base)->BOOT_CFG4) +#define OCOTP_MEM_TRIM0_REG(base) ((base)->MEM_TRIM0) +#define OCOTP_MEM_TRIM1_REG(base) ((base)->MEM_TRIM1) +#define OCOTP_ANA0_REG(base) ((base)->ANA0) +#define OCOTP_ANA1_REG(base) ((base)->ANA1) +#define OCOTP_OTPMK0_REG(base) ((base)->OTPMK0) +#define OCOTP_OTPMK1_REG(base) ((base)->OTPMK1) +#define OCOTP_OTPMK2_REG(base) ((base)->OTPMK2) +#define OCOTP_OTPMK3_REG(base) ((base)->OTPMK3) +#define OCOTP_OTPMK4_REG(base) ((base)->OTPMK4) +#define OCOTP_OTPMK5_REG(base) ((base)->OTPMK5) +#define OCOTP_OTPMK6_REG(base) ((base)->OTPMK6) +#define OCOTP_OTPMK7_REG(base) ((base)->OTPMK7) +#define OCOTP_SRK0_REG(base) ((base)->SRK0) +#define OCOTP_SRK1_REG(base) ((base)->SRK1) +#define OCOTP_SRK2_REG(base) ((base)->SRK2) +#define OCOTP_SRK3_REG(base) ((base)->SRK3) +#define OCOTP_SRK4_REG(base) ((base)->SRK4) +#define OCOTP_SRK5_REG(base) ((base)->SRK5) +#define OCOTP_SRK6_REG(base) ((base)->SRK6) +#define OCOTP_SRK7_REG(base) ((base)->SRK7) +#define OCOTP_SJC_RESP0_REG(base) ((base)->SJC_RESP0) +#define OCOTP_SJC_RESP1_REG(base) ((base)->SJC_RESP1) +#define OCOTP_USB_ID_REG(base) ((base)->USB_ID) +#define OCOTP_FIELD_RETURN_REG(base) ((base)->FIELD_RETURN) +#define OCOTP_MAC_ADDR0_REG(base) ((base)->MAC_ADDR0) +#define OCOTP_MAC_ADDR1_REG(base) ((base)->MAC_ADDR1) +#define OCOTP_MAC_ADDR2_REG(base) ((base)->MAC_ADDR2) +#define OCOTP_SRK_REVOKE_REG(base) ((base)->SRK_REVOKE) +#define OCOTP_MAU_KEY0_REG(base) ((base)->MAU_KEY0) +#define OCOTP_MAU_KEY1_REG(base) ((base)->MAU_KEY1) +#define OCOTP_MAU_KEY2_REG(base) ((base)->MAU_KEY2) +#define OCOTP_MAU_KEY3_REG(base) ((base)->MAU_KEY3) +#define OCOTP_MAU_KEY4_REG(base) ((base)->MAU_KEY4) +#define OCOTP_MAU_KEY5_REG(base) ((base)->MAU_KEY5) +#define OCOTP_MAU_KEY6_REG(base) ((base)->MAU_KEY6) +#define OCOTP_MAU_KEY7_REG(base) ((base)->MAU_KEY7) +#define OCOTP_GP10_REG(base) ((base)->GP10) +#define OCOTP_GP11_REG(base) ((base)->GP11) +#define OCOTP_GP20_REG(base) ((base)->GP20) +#define OCOTP_GP21_REG(base) ((base)->GP21) +#define OCOTP_CRC_GP10_REG(base) ((base)->CRC_GP10) +#define OCOTP_CRC_GP11_REG(base) ((base)->CRC_GP11) +#define OCOTP_CRC_GP20_REG(base) ((base)->CRC_GP20) +#define OCOTP_CRC_GP21_REG(base) ((base)->CRC_GP21) + +/*! + * @} + */ /* end of group OCOTP_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define OCOTP_CTRL_ADDR_MASK 0xFu +#define OCOTP_CTRL_ADDR_SHIFT 0 +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<REG01) +#define PCIE_PHY_CMN_REG02_REG(base) ((base)->REG02) +#define PCIE_PHY_CMN_REG03_REG(base) ((base)->REG03) +#define PCIE_PHY_CMN_REG04_REG(base) ((base)->REG04) +#define PCIE_PHY_CMN_REG05_REG(base) ((base)->REG05) +#define PCIE_PHY_CMN_REG06_REG(base) ((base)->REG06) +#define PCIE_PHY_CMN_REG07_REG(base) ((base)->REG07) +#define PCIE_PHY_CMN_REG0B_REG(base) ((base)->REG0B) +#define PCIE_PHY_CMN_REG08_REG(base) ((base)->REG08) +#define PCIE_PHY_CMN_REG09_REG(base) ((base)->REG09) +#define PCIE_PHY_CMN_REG11_REG(base) ((base)->REG11) +#define PCIE_PHY_CMN_REG15_REG(base) ((base)->REG15) +#define PCIE_PHY_CMN_REG16_REG(base) ((base)->REG16) +#define PCIE_PHY_CMN_REG17_REG(base) ((base)->REG17) +#define PCIE_PHY_CMN_REG18_REG(base) ((base)->REG18) +#define PCIE_PHY_CMN_REG19_REG(base) ((base)->REG19) +#define PCIE_PHY_CMN_REG1A_REG(base) ((base)->REG1A) + +/*! + * @} + */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_CMN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_CMN_Register_Masks PCIE_PHY_CMN Register Masks + * @{ + */ + +/* REG01 Bit Fields */ +#define PCIE_PHY_CMN_REG01_TCODE_MASK 0xFu +#define PCIE_PHY_CMN_REG01_TCODE_SHIFT 0 +#define PCIE_PHY_CMN_REG01_TCODE(x) (((uint32_t)(((uint32_t)(x))<REG21) +#define PCIE_PHY_TRSV_REG22_REG(base) ((base)->REG22) +#define PCIE_PHY_TRSV_REG24_REG(base) ((base)->REG24) +#define PCIE_PHY_TRSV_REG2B_REG(base) ((base)->REG2B) +#define PCIE_PHY_TRSV_REG3A_REG(base) ((base)->REG3A) +#define PCIE_PHY_TRSV_REG3E_REG(base) ((base)->REG3E) +#define PCIE_PHY_TRSV_REG25_REG(base) ((base)->REG25) +#define PCIE_PHY_TRSV_REG26_REG(base) ((base)->REG26) +#define PCIE_PHY_TRSV_REG29_REG(base) ((base)->REG29) +#define PCIE_PHY_TRSV_REG31_REG(base) ((base)->REG31) +#define PCIE_PHY_TRSV_REG33_REG(base) ((base)->REG33) +#define PCIE_PHY_TRSV_REG36_REG(base) ((base)->REG36) +#define PCIE_PHY_TRSV_REG37_REG(base) ((base)->REG37) +#define PCIE_PHY_TRSV_REG38_REG(base) ((base)->REG38) +#define PCIE_PHY_TRSV_REG39_REG(base) ((base)->REG39) +#define PCIE_PHY_TRSV_REG40_REG(base) ((base)->REG40) +#define PCIE_PHY_TRSV_REG42_REG(base) ((base)->REG42) + +/*! + * @} + */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_TRSV Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_TRSV_Register_Masks PCIE_PHY_TRSV Register Masks + * @{ + */ + +/* REG21 Bit Fields */ +#define PCIE_PHY_TRSV_REG21_EMP_LVL_MASK 0x1Fu +#define PCIE_PHY_TRSV_REG21_EMP_LVL_SHIFT 0 +#define PCIE_PHY_TRSV_REG21_EMP_LVL(x) (((uint32_t)(((uint32_t)(x))<REG_1P0A) +#define PMU_REG_1P0A_SET_REG(base) ((base)->REG_1P0A_SET) +#define PMU_REG_1P0A_CLR_REG(base) ((base)->REG_1P0A_CLR) +#define PMU_REG_1P0A_TOG_REG(base) ((base)->REG_1P0A_TOG) +#define PMU_REG_1P0D_REG(base) ((base)->REG_1P0D) +#define PMU_REG_1P0D_SET_REG(base) ((base)->REG_1P0D_SET) +#define PMU_REG_1P0D_CLR_REG(base) ((base)->REG_1P0D_CLR) +#define PMU_REG_1P0D_TOG_REG(base) ((base)->REG_1P0D_TOG) +#define PMU_REG_HSIC_1P2_REG(base) ((base)->REG_HSIC_1P2) +#define PMU_REG_HSIC_1P2_SET_REG(base) ((base)->REG_HSIC_1P2_SET) +#define PMU_REG_HSIC_1P2_CLR_REG(base) ((base)->REG_HSIC_1P2_CLR) +#define PMU_REG_HSIC_1P2_TOG_REG(base) ((base)->REG_HSIC_1P2_TOG) +#define PMU_REG_LPSR_1P0_REG(base) ((base)->REG_LPSR_1P0) +#define PMU_REG_LPSR_1P0_SET_REG(base) ((base)->REG_LPSR_1P0_SET) +#define PMU_REG_LPSR_1P0_CLR_REG(base) ((base)->REG_LPSR_1P0_CLR) +#define PMU_REG_LPSR_1P0_TOG_REG(base) ((base)->REG_LPSR_1P0_TOG) +#define PMU_REF_REG(base) ((base)->REF) +#define PMU_REF_SET_REG(base) ((base)->REF_SET) +#define PMU_REF_CLR_REG(base) ((base)->REF_CLR) +#define PMU_REF_TOG_REG(base) ((base)->REF_TOG) +#define PMU_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL) +#define PMU_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) +#define PMU_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) +#define PMU_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) + +/*! + * @} + */ /* end of group PMU_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/* REG_1P0A Bit Fields */ +#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<PWMCR) +#define PWM_PWMSR_REG(base) ((base)->PWMSR) +#define PWM_PWMIR_REG(base) ((base)->PWMIR) +#define PWM_PWMSAR_REG(base) ((base)->PWMSAR) +#define PWM_PWMPR_REG(base) ((base)->PWMPR) +#define PWM_PWMCNR_REG(base) ((base)->PWMCNR) + +/*! + * @} + */ /* end of group PWM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/* PWMCR Bit Fields */ +#define PWM_PWMCR_EN_MASK 0x1u +#define PWM_PWMCR_EN_SHIFT 0 +#define PWM_PWMCR_REPEAT_MASK 0x6u +#define PWM_PWMCR_REPEAT_SHIFT 1 +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x))<HW_PXP_CTRL) +#define PXP_HW_PXP_STAT_REG(base) ((base)->HW_PXP_STAT) +#define PXP_HW_PXP_OUT_CTRL_REG(base) ((base)->HW_PXP_OUT_CTRL) +#define PXP_HW_PXP_OUT_BUF_REG(base) ((base)->HW_PXP_OUT_BUF) +#define PXP_HW_PXP_OUT_BUF2_REG(base) ((base)->HW_PXP_OUT_BUF2) +#define PXP_HW_PXP_OUT_PITCH_REG(base) ((base)->HW_PXP_OUT_PITCH) +#define PXP_HW_PXP_OUT_LRC_REG(base) ((base)->HW_PXP_OUT_LRC) +#define PXP_HW_PXP_OUT_PS_ULC_REG(base) ((base)->HW_PXP_OUT_PS_ULC) +#define PXP_HW_PXP_OUT_PS_LRC_REG(base) ((base)->HW_PXP_OUT_PS_LRC) +#define PXP_HW_PXP_OUT_AS_ULC_REG(base) ((base)->HW_PXP_OUT_AS_ULC) +#define PXP_HW_PXP_OUT_AS_LRC_REG(base) ((base)->HW_PXP_OUT_AS_LRC) +#define PXP_HW_PXP_PS_CTRL_REG(base) ((base)->HW_PXP_PS_CTRL) +#define PXP_HW_PXP_PS_BUF_REG(base) ((base)->HW_PXP_PS_BUF) +#define PXP_HW_PXP_PS_UBUF_REG(base) ((base)->HW_PXP_PS_UBUF) +#define PXP_HW_PXP_PS_VBUF_REG(base) ((base)->HW_PXP_PS_VBUF) +#define PXP_HW_PXP_PS_PITCH_REG(base) ((base)->HW_PXP_PS_PITCH) +#define PXP_HW_PXP_PS_BACKGROUND_0_REG(base) ((base)->HW_PXP_PS_BACKGROUND_0) +#define PXP_HW_PXP_PS_SCALE_REG(base) ((base)->HW_PXP_PS_SCALE) +#define PXP_HW_PXP_PS_OFFSET_REG(base) ((base)->HW_PXP_PS_OFFSET) +#define PXP_HW_PXP_PS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_0) +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_0) +#define PXP_HW_PXP_AS_CTRL_REG(base) ((base)->HW_PXP_AS_CTRL) +#define PXP_HW_PXP_AS_BUF_REG(base) ((base)->HW_PXP_AS_BUF) +#define PXP_HW_PXP_AS_PITCH_REG(base) ((base)->HW_PXP_AS_PITCH) +#define PXP_HW_PXP_AS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_0) +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_0) +#define PXP_HW_PXP_CSC1_COEF0_REG(base) ((base)->HW_PXP_CSC1_COEF0) +#define PXP_HW_PXP_CSC1_COEF1_REG(base) ((base)->HW_PXP_CSC1_COEF1) +#define PXP_HW_PXP_CSC1_COEF2_REG(base) ((base)->HW_PXP_CSC1_COEF2) +#define PXP_HW_PXP_CSC2_CTRL_REG(base) ((base)->HW_PXP_CSC2_CTRL) +#define PXP_HW_PXP_CSC2_COEF0_REG(base) ((base)->HW_PXP_CSC2_COEF0) +#define PXP_HW_PXP_CSC2_COEF1_REG(base) ((base)->HW_PXP_CSC2_COEF1) +#define PXP_HW_PXP_CSC2_COEF2_REG(base) ((base)->HW_PXP_CSC2_COEF2) +#define PXP_HW_PXP_CSC2_COEF3_REG(base) ((base)->HW_PXP_CSC2_COEF3) +#define PXP_HW_PXP_CSC2_COEF4_REG(base) ((base)->HW_PXP_CSC2_COEF4) +#define PXP_HW_PXP_CSC2_COEF5_REG(base) ((base)->HW_PXP_CSC2_COEF5) +#define PXP_HW_PXP_LUT_CTRL_REG(base) ((base)->HW_PXP_LUT_CTRL) +#define PXP_HW_PXP_LUT_ADDR_REG(base) ((base)->HW_PXP_LUT_ADDR) +#define PXP_HW_PXP_LUT_DATA_REG(base) ((base)->HW_PXP_LUT_DATA) +#define PXP_HW_PXP_LUT_EXTMEM_REG(base) ((base)->HW_PXP_LUT_EXTMEM) +#define PXP_HW_PXP_CFA_REG(base) ((base)->HW_PXP_CFA) +#define PXP_HW_PXP_ALPHA_A_CTRL_REG(base) ((base)->HW_PXP_ALPHA_A_CTRL) +#define PXP_HW_PXP_ALPHA_B_CTRL_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL) +#define PXP_HW_PXP_ALPHA_B_CTRL_1_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL_1) +#define PXP_HW_PXP_PS_BACKGROUND_1_REG(base) ((base)->HW_PXP_PS_BACKGROUND_1) +#define PXP_HW_PXP_PS_CLRKEYLOW_1_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_1) +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_1) +#define PXP_HW_PXP_AS_CLRKEYLOW_1_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_1) +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_1) +#define PXP_HW_PXP_CTRL2_REG(base) ((base)->HW_PXP_CTRL2) +#define PXP_HW_PXP_POWER_REG0_REG(base) ((base)->HW_PXP_POWER_REG0) +#define PXP_HW_PXP_POWER_REG1_REG(base) ((base)->HW_PXP_POWER_REG1) +#define PXP_HW_PXP_DATA_PATH_CTRL0_REG(base) ((base)->HW_PXP_DATA_PATH_CTRL0) +#define PXP_HW_PXP_DATA_PATH_CTRL1_REG(base) ((base)->HW_PXP_DATA_PATH_CTRL1) +#define PXP_HW_PXP_INIT_MEM_CTRL_REG(base) ((base)->HW_PXP_INIT_MEM_CTRL) +#define PXP_HW_PXP_INIT_MEM_DATA_REG(base) ((base)->HW_PXP_INIT_MEM_DATA) +#define PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(base) ((base)->HW_PXP_INIT_MEM_DATA_HIGH) +#define PXP_HW_PXP_IRQ_MASK_REG(base) ((base)->HW_PXP_IRQ_MASK) +#define PXP_HW_PXP_IRQ_REG(base) ((base)->HW_PXP_IRQ) +#define PXP_HW_PXP_NEXT_REG(base) ((base)->HW_PXP_NEXT) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH0) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH1) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH0) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH1) +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0) +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1) +#define PXP_HW_PXP_INPUT_FETCH_PITCH_REG(base) ((base)->HW_PXP_INPUT_FETCH_PITCH) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH1) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH0) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH1) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH0) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH1) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH0) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH1) +#define PXP_HW_PXP_INPUT_STORE_PITCH_REG(base) ((base)->HW_PXP_INPUT_STORE_PITCH) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH0) +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH0) +#define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_FILL_DATA_CH0) +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH1) +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH1) +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_H_CH0) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH0) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH1) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH0) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH1) +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0) +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1) +#define PXP_HW_PXP_DITHER_FETCH_PITCH_REG(base) ((base)->HW_PXP_DITHER_FETCH_PITCH) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH1) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH0) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH1) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH0) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH1) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH0) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH1) +#define PXP_HW_PXP_DITHER_STORE_PITCH_REG(base) ((base)->HW_PXP_DITHER_STORE_PITCH) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH0) +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH0) +#define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_FILL_DATA_CH0) +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH1) +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH1) +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_H_CH0) +#define PXP_HW_PXP_DITHER_CTRL_REG(base) ((base)->HW_PXP_DITHER_CTRL) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA0) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA1) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA2) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA3) +#define PXP_HW_PXP_HIST_A_CTRL_REG(base) ((base)->HW_PXP_HIST_A_CTRL) +#define PXP_HW_PXP_HIST_A_MASK_REG(base) ((base)->HW_PXP_HIST_A_MASK) +#define PXP_HW_PXP_HIST_A_BUF_SIZE_REG(base) ((base)->HW_PXP_HIST_A_BUF_SIZE) +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_REG(base) ((base)->HW_PXP_HIST_A_TOTAL_PIXEL) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_X) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_Y) +#define PXP_HW_PXP_HIST_A_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_A_RAW_STAT0) +#define PXP_HW_PXP_HIST_A_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_A_RAW_STAT1) +#define PXP_HW_PXP_HIST_B_CTRL_REG(base) ((base)->HW_PXP_HIST_B_CTRL) +#define PXP_HW_PXP_HIST_B_MASK_REG(base) ((base)->HW_PXP_HIST_B_MASK) +#define PXP_HW_PXP_HIST_B_BUF_SIZE_REG(base) ((base)->HW_PXP_HIST_B_BUF_SIZE) +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_REG(base) ((base)->HW_PXP_HIST_B_TOTAL_PIXEL) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_X) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_Y) +#define PXP_HW_PXP_HIST_B_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT0) +#define PXP_HW_PXP_HIST_B_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT1) +#define PXP_HW_PXP_HIST2_PARAM_REG(base) ((base)->HW_PXP_HIST2_PARAM) +#define PXP_HW_PXP_HIST4_PARAM_REG(base) ((base)->HW_PXP_HIST4_PARAM) +#define PXP_HW_PXP_HIST8_PARAM0_REG(base) ((base)->HW_PXP_HIST8_PARAM0) +#define PXP_HW_PXP_HIST8_PARAM1_REG(base) ((base)->HW_PXP_HIST8_PARAM1) +#define PXP_HW_PXP_HIST16_PARAM0_REG(base) ((base)->HW_PXP_HIST16_PARAM0) +#define PXP_HW_PXP_HIST16_PARAM1_REG(base) ((base)->HW_PXP_HIST16_PARAM1) +#define PXP_HW_PXP_HIST16_PARAM2_REG(base) ((base)->HW_PXP_HIST16_PARAM2) +#define PXP_HW_PXP_HIST16_PARAM3_REG(base) ((base)->HW_PXP_HIST16_PARAM3) +#define PXP_HW_PXP_HIST32_PARAM0_REG(base) ((base)->HW_PXP_HIST32_PARAM0) +#define PXP_HW_PXP_HIST32_PARAM1_REG(base) ((base)->HW_PXP_HIST32_PARAM1) +#define PXP_HW_PXP_HIST32_PARAM2_REG(base) ((base)->HW_PXP_HIST32_PARAM2) +#define PXP_HW_PXP_HIST32_PARAM3_REG(base) ((base)->HW_PXP_HIST32_PARAM3) +#define PXP_HW_PXP_HIST32_PARAM4_REG(base) ((base)->HW_PXP_HIST32_PARAM4) +#define PXP_HW_PXP_HIST32_PARAM5_REG(base) ((base)->HW_PXP_HIST32_PARAM5) +#define PXP_HW_PXP_HIST32_PARAM6_REG(base) ((base)->HW_PXP_HIST32_PARAM6) +#define PXP_HW_PXP_HIST32_PARAM7_REG(base) ((base)->HW_PXP_HIST32_PARAM7) +#define PXP_HW_PXP_COMP_CTRL_REG(base) ((base)->HW_PXP_COMP_CTRL) +#define PXP_HW_PXP_COMP_FORMAT0_REG(base) ((base)->HW_PXP_COMP_FORMAT0) +#define PXP_HW_PXP_COMP_FORMAT1_REG(base) ((base)->HW_PXP_COMP_FORMAT1) +#define PXP_HW_PXP_COMP_FORMAT2_REG(base) ((base)->HW_PXP_COMP_FORMAT2) +#define PXP_HW_PXP_COMP_MASK0_REG(base) ((base)->HW_PXP_COMP_MASK0) +#define PXP_HW_PXP_COMP_MASK1_REG(base) ((base)->HW_PXP_COMP_MASK1) +#define PXP_HW_PXP_COMP_BUFFER_SIZE_REG(base) ((base)->HW_PXP_COMP_BUFFER_SIZE) +#define PXP_HW_PXP_COMP_SOURCE_REG(base) ((base)->HW_PXP_COMP_SOURCE) +#define PXP_HW_PXP_COMP_TARGET_REG(base) ((base)->HW_PXP_COMP_TARGET) +#define PXP_HW_PXP_COMP_BUFFER_A_REG(base) ((base)->HW_PXP_COMP_BUFFER_A) +#define PXP_HW_PXP_COMP_BUFFER_B_REG(base) ((base)->HW_PXP_COMP_BUFFER_B) +#define PXP_HW_PXP_COMP_BUFFER_C_REG(base) ((base)->HW_PXP_COMP_BUFFER_C) +#define PXP_HW_PXP_COMP_BUFFER_D_REG(base) ((base)->HW_PXP_COMP_BUFFER_D) +#define PXP_HW_PXP_COMP_DEBUG_REG(base) ((base)->HW_PXP_COMP_DEBUG) +#define PXP_HW_PXP_BUS_MUX_REG(base) ((base)->HW_PXP_BUS_MUX) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX0) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX1) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX0) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX1) +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_FETCH) +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_STORE) + +/*! + * @} + */ /* end of group PXP_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/* HW_PXP_CTRL Bit Fields */ +#define PXP_HW_PXP_CTRL_ENABLE_MASK 0x1u +#define PXP_HW_PXP_CTRL_ENABLE_SHIFT 0 +#define PXP_HW_PXP_CTRL_IRQ_ENABLE_MASK 0x2u +#define PXP_HW_PXP_CTRL_IRQ_ENABLE_SHIFT 1 +#define PXP_HW_PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u +#define PXP_HW_PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 +#define PXP_HW_PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u +#define PXP_HW_PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 +#define PXP_HW_PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK 0x10u +#define PXP_HW_PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT 4 +#define PXP_HW_PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK 0x20u +#define PXP_HW_PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT 5 +#define PXP_HW_PXP_CTRL_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_CTRL_RSVD0_SHIFT 6 +#define PXP_HW_PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define QuadSPI_IPCR_REG(base) ((base)->IPCR) +#define QuadSPI_FLSHCR_REG(base) ((base)->FLSHCR) +#define QuadSPI_BUF0CR_REG(base) ((base)->BUF0CR) +#define QuadSPI_BUF1CR_REG(base) ((base)->BUF1CR) +#define QuadSPI_BUF2CR_REG(base) ((base)->BUF2CR) +#define QuadSPI_BUF3CR_REG(base) ((base)->BUF3CR) +#define QuadSPI_BFGENCR_REG(base) ((base)->BFGENCR) +#define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND) +#define QuadSPI_BUF1IND_REG(base) ((base)->BUF1IND) +#define QuadSPI_BUF2IND_REG(base) ((base)->BUF2IND) +#define QuadSPI_SFAR_REG(base) ((base)->SFAR) +#define QuadSPI_SMPR_REG(base) ((base)->SMPR) +#define QuadSPI_RBSR_REG(base) ((base)->RBSR) +#define QuadSPI_RBCT_REG(base) ((base)->RBCT) +#define QuadSPI_TBSR_REG(base) ((base)->TBSR) +#define QuadSPI_TBDR_REG(base) ((base)->TBDR) +#define QuadSPI_SR_REG(base) ((base)->SR) +#define QuadSPI_FR_REG(base) ((base)->FR) +#define QuadSPI_RSER_REG(base) ((base)->RSER) +#define QuadSPI_SPNDST_REG(base) ((base)->SPNDST) +#define QuadSPI_SPTRCLR_REG(base) ((base)->SPTRCLR) +#define QuadSPI_SFA1AD_REG(base) ((base)->SFA1AD) +#define QuadSPI_SFA2AD_REG(base) ((base)->SFA2AD) +#define QuadSPI_SFB1AD_REG(base) ((base)->SFB1AD) +#define QuadSPI_SFB2AD_REG(base) ((base)->SFB2AD) +#define QuadSPI_RBDR_REG(base,index) ((base)->RBDR[index]) +#define QuadSPI_LUTKEY_REG(base) ((base)->LUTKEY) +#define QuadSPI_LCKCR_REG(base) ((base)->LCKCR) +#define QuadSPI_LUT_REG(base,index) ((base)->LUT[index]) + +/*! + * @} + */ /* end of group QuadSPI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define QuadSPI_MCR_SWRSTSD_MASK 0x1u +#define QuadSPI_MCR_SWRSTSD_SHIFT 0 +#define QuadSPI_MCR_SWRSTHD_MASK 0x2u +#define QuadSPI_MCR_SWRSTHD_SHIFT 1 +#define QuadSPI_MCR_END_CFG_MASK 0xCu +#define QuadSPI_MCR_END_CFG_SHIFT 2 +#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x))<VIR) +#define RDC_STAT_REG(base) ((base)->STAT) +#define RDC_INTCTRL_REG(base) ((base)->INTCTRL) +#define RDC_INTSTAT_REG(base) ((base)->INTSTAT) +#define RDC_MDA_REG(base,index) ((base)->MDA[index]) +#define RDC_PDAP_REG(base,index) ((base)->PDAP[index]) +#define RDC_MRSA_REG(base,index) ((base)->MR[index].MRSA) +#define RDC_MREA_REG(base,index) ((base)->MR[index].MREA) +#define RDC_MRC_REG(base,index) ((base)->MR[index].MRC) +#define RDC_MRVS_REG(base,index) ((base)->MR[index].MRVS) + +/*! + * @} + */ /* end of group RDC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- RDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Register_Masks RDC Register Masks + * @{ + */ + +/* VIR Bit Fields */ +#define RDC_VIR_NDID_MASK 0xFu +#define RDC_VIR_NDID_SHIFT 0 +#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x))<GATE[index]) +#define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) +#define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks + * @{ + */ + +/* GATE Bit Fields */ +#define RDC_SEMAPHORE_GATE_GTFSM_MASK 0xFu +#define RDC_SEMAPHORE_GATE_GTFSM_SHIFT 0 +#define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x))<ROMPATCHD[index]) +#define ROMC_ROMPATCHCNTL_REG(base) ((base)->ROMPATCHCNTL) +#define ROMC_ROMPATCHENH_REG(base) ((base)->ROMPATCHENH) +#define ROMC_ROMPATCHENL_REG(base) ((base)->ROMPATCHENL) +#define ROMC_ROMPATCHA_REG(base,index) ((base)->ROMPATCHA[index]) +#define ROMC_ROMPATCHSR_REG(base) ((base)->ROMPATCHSR) + +/*! + * @} + */ /* end of group ROMC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/* ROMPATCHD Bit Fields */ +#define ROMC_ROMPATCHD_DATAX_MASK 0xFFFFFFFFu +#define ROMC_ROMPATCHD_DATAX_SHIFT 0 +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) +#define SDMAARM_INTR_REG(base) ((base)->INTR) +#define SDMAARM_STOP_STAT_REG(base) ((base)->STOP_STAT) +#define SDMAARM_HSTART_REG(base) ((base)->HSTART) +#define SDMAARM_EVTOVR_REG(base) ((base)->EVTOVR) +#define SDMAARM_DSPOVR_REG(base) ((base)->DSPOVR) +#define SDMAARM_HOSTOVR_REG(base) ((base)->HOSTOVR) +#define SDMAARM_EVTPEND_REG(base) ((base)->EVTPEND) +#define SDMAARM_RESET_REG(base) ((base)->RESET) +#define SDMAARM_EVTERR_REG(base) ((base)->EVTERR) +#define SDMAARM_INTRMASK_REG(base) ((base)->INTRMASK) +#define SDMAARM_PSW_REG(base) ((base)->PSW) +#define SDMAARM_EVTERRDBG_REG(base) ((base)->EVTERRDBG) +#define SDMAARM_CONFIG_REG(base) ((base)->CONFIG) +#define SDMAARM_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK) +#define SDMAARM_ONCE_ENB_REG(base) ((base)->ONCE_ENB) +#define SDMAARM_ONCE_DATA_REG(base) ((base)->ONCE_DATA) +#define SDMAARM_ONCE_INSTR_REG(base) ((base)->ONCE_INSTR) +#define SDMAARM_ONCE_STAT_REG(base) ((base)->ONCE_STAT) +#define SDMAARM_ONCE_CMD_REG(base) ((base)->ONCE_CMD) +#define SDMAARM_ILLINSTADDR_REG(base) ((base)->ILLINSTADDR) +#define SDMAARM_CHN0ADDR_REG(base) ((base)->CHN0ADDR) +#define SDMAARM_EVT_MIRROR_REG(base) ((base)->EVT_MIRROR) +#define SDMAARM_EVT_MIRROR2_REG(base) ((base)->EVT_MIRROR2) +#define SDMAARM_XTRIG_CONF1_REG(base) ((base)->XTRIG_CONF1) +#define SDMAARM_XTRIG_CONF2_REG(base) ((base)->XTRIG_CONF2) +#define SDMAARM_SDMA_CHNPRI_REG(base,index) ((base)->SDMA_CHNPRI[index]) +#define SDMAARM_CHNENBL_REG(base,index) ((base)->CHNENBL[index]) + +/*! + * @} + */ /* end of group SDMAARM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/* MC0PTR Bit Fields */ +#define SDMAARM_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu +#define SDMAARM_MC0PTR_MC0PTR_SHIFT 0 +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<GATE00) +#define SEMA4_GATE01_REG(base) ((base)->GATE01) +#define SEMA4_GATE02_REG(base) ((base)->GATE02) +#define SEMA4_GATE03_REG(base) ((base)->GATE03) +#define SEMA4_GATE04_REG(base) ((base)->GATE04) +#define SEMA4_GATE05_REG(base) ((base)->GATE05) +#define SEMA4_GATE06_REG(base) ((base)->GATE06) +#define SEMA4_GATE07_REG(base) ((base)->GATE07) +#define SEMA4_GATE08_REG(base) ((base)->GATE08) +#define SEMA4_GATE09_REG(base) ((base)->GATE09) +#define SEMA4_GATE10_REG(base) ((base)->GATE10) +#define SEMA4_GATE11_REG(base) ((base)->GATE11) +#define SEMA4_GATE12_REG(base) ((base)->GATE12) +#define SEMA4_GATE13_REG(base) ((base)->GATE13) +#define SEMA4_GATE14_REG(base) ((base)->GATE14) +#define SEMA4_GATE15_REG(base) ((base)->GATE15) +#define SEMA4_CPINE_REG(base,index) ((base)->CPnINE[index].INE) +#define SEMA4_CPNTF_REG(base,index) ((base)->CPnNTF[index].NTF) +#define SEMA4_RSTGT_REG(base) ((base)->RSTGT) +#define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) + +/*! + * @} + */ /* end of group SEMA4_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SEMA4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks + * @{ + */ + +/* GATE00 Bit Fields */ +#define SEMA4_GATE00_GTFSM_MASK 0x3u +#define SEMA4_GATE00_GTFSM_SHIFT 0 +#define SEMA4_GATE00_GTFSM(x) (((uint8_t)(((uint8_t)(x))<GPUSR1) +#define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) +#define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) +#define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) +#define SJC_DCR_REG(base) ((base)->DCR.DCR) +#define SJC_SSR_REG(base) ((base)->SSR.SSR) +#define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) + +/*! + * @} + */ /* end of group SJC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SJC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SJC_Register_Masks SJC Register Masks + * @{ + */ + +/* GPUSR1 Bit Fields */ +#define SJC_GPUSR1_A_DBG_MASK 0x1u +#define SJC_GPUSR1_A_DBG_SHIFT 0 +#define SJC_GPUSR1_A_WFI_MASK 0x2u +#define SJC_GPUSR1_A_WFI_SHIFT 1 +#define SJC_GPUSR1_S_STAT_MASK 0x1Cu +#define SJC_GPUSR1_S_STAT_SHIFT 2 +#define SJC_GPUSR1_S_STAT(x) (((uint32_t)(((uint32_t)(x))<HPLR) +#define SNVS_HPCOMR_REG(base) ((base)->HPCOMR) +#define SNVS_HPCR_REG(base) ((base)->HPCR) +#define SNVS_HPSR_REG(base) ((base)->HPSR) +#define SNVS_HPRTCMR_REG(base) ((base)->HPRTCMR) +#define SNVS_HPRTCLR_REG(base) ((base)->HPRTCLR) +#define SNVS_HPTAMR_REG(base) ((base)->HPTAMR) +#define SNVS_HPTALR_REG(base) ((base)->HPTALR) +#define SNVS_LPLR_REG(base) ((base)->LPLR) +#define SNVS_LPCR_REG(base) ((base)->LPCR) +#define SNVS_LPSR_REG(base) ((base)->LPSR) +#define SNVS_LPSMCMR_REG(base) ((base)->LPSMCMR) +#define SNVS_LPSMCLR_REG(base) ((base)->LPSMCLR) +#define SNVS_LPGPR_REG(base) ((base)->LPGPR) +#define SNVS_HPVIDR1_REG(base) ((base)->HPVIDR1) +#define SNVS_HPVIDR2_REG(base) ((base)->HPVIDR2) + +/*! + * @} + */ /* end of group SNVS_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/* HPLR Bit Fields */ +#define SNVS_HPLR_MC_SL_MASK 0x10u +#define SNVS_HPLR_MC_SL_SHIFT 4 +#define SNVS_HPLR_GPR_SL_MASK 0x20u +#define SNVS_HPLR_GPR_SL_SHIFT 5 +/* HPCOMR Bit Fields */ +#define SNVS_HPCOMR_LP_SWR_MASK 0x10u +#define SNVS_HPCOMR_LP_SWR_SHIFT 4 +#define SNVS_HPCOMR_LP_SWR_DIS_MASK 0x20u +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT 5 +#define SNVS_HPCOMR_NPSWA_EN_MASK 0x80000000u +#define SNVS_HPCOMR_NPSWA_EN_SHIFT 31 +/* HPCR Bit Fields */ +#define SNVS_HPCR_RTC_EN_MASK 0x1u +#define SNVS_HPCR_RTC_EN_SHIFT 0 +#define SNVS_HPCR_HPTA_EN_MASK 0x2u +#define SNVS_HPCR_HPTA_EN_SHIFT 1 +#define SNVS_HPCR_PI_EN_MASK 0x8u +#define SNVS_HPCR_PI_EN_SHIFT 3 +#define SNVS_HPCR_PI_FREQ_MASK 0xF0u +#define SNVS_HPCR_PI_FREQ_SHIFT 4 +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x))<PRR[index]) + +/*! + * @} + */ /* end of group SPBA_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/* PRR Bit Fields */ +#define SPBA_PRR_RARA_MASK 0x1u +#define SPBA_PRR_RARA_SHIFT 0 +#define SPBA_PRR_RARB_MASK 0x2u +#define SPBA_PRR_RARB_SHIFT 1 +#define SPBA_PRR_RARC_MASK 0x4u +#define SPBA_PRR_RARC_SHIFT 2 +#define SPBA_PRR_ROI_MASK 0x30000u +#define SPBA_PRR_ROI_SHIFT 16 +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x))<SCR) +#define SRC_A7RCR0_REG(base) ((base)->A7RCR0) +#define SRC_A7RCR1_REG(base) ((base)->A7RCR1) +#define SRC_M4RCR_REG(base) ((base)->M4RCR) +#define SRC_ERCR_REG(base) ((base)->ERCR) +#define SRC_HSICPHY_RCR_REG(base) ((base)->HSICPHY_RCR) +#define SRC_USBOPHY1_RCR_REG(base) ((base)->USBOPHY1_RCR) +#define SRC_USBOPHY2_RCR_REG(base) ((base)->USBOPHY2_RCR) +#define SRC_MIPIPHY_RCR_REG(base) ((base)->MIPIPHY_RCR) +#define SRC_PCIEPHY_RCR_REG(base) ((base)->PCIEPHY_RCR) +#define SRC_SBMR1_REG(base) ((base)->SBMR1) +#define SRC_SRSR_REG(base) ((base)->SRSR) +#define SRC_SISR_REG(base) ((base)->SISR) +#define SRC_SIMR_REG(base) ((base)->SIMR) +#define SRC_SBMR2_REG(base) ((base)->SBMR2) +#define SRC_GPR1_REG(base) ((base)->GPR1) +#define SRC_GPR2_REG(base) ((base)->GPR2) +#define SRC_GPR3_REG(base) ((base)->GPR3) +#define SRC_GPR4_REG(base) ((base)->GPR4) +#define SRC_GPR5_REG(base) ((base)->GPR5) +#define SRC_GPR6_REG(base) ((base)->GPR6) +#define SRC_GPR7_REG(base) ((base)->GPR7) +#define SRC_GPR8_REG(base) ((base)->GPR8) +#define SRC_GPR9_REG(base) ((base)->GPR9) +#define SRC_GPR10_REG(base) ((base)->GPR10) +#define SRC_DDRC_RCR_REG(base) ((base)->DDRC_RCR) + +/*! + * @} + */ /* end of group SRC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/* SCR Bit Fields */ +#define SRC_SCR_MASK_TEMPSENSE_RESET_MASK 0xF0u +#define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT 4 +#define SRC_SCR_MASK_TEMPSENSE_RESET(x) (((uint32_t)(((uint32_t)(x))<HW_ANADIG_TEMPSENSE0) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_TOG) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_REG(base) ((base)->HW_ANADIG_TEMPSENSE1) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_TOG) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_TOG) + +/*! + * @} + */ /* end of group TEMPMON_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/* HW_ANADIG_TEMPSENSE0 Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<URXD) +#define UART_UTXD_REG(base) ((base)->UTXD) +#define UART_UCR1_REG(base) ((base)->UCR1) +#define UART_UCR2_REG(base) ((base)->UCR2) +#define UART_UCR3_REG(base) ((base)->UCR3) +#define UART_UCR4_REG(base) ((base)->UCR4) +#define UART_UFCR_REG(base) ((base)->UFCR) +#define UART_USR1_REG(base) ((base)->USR1) +#define UART_USR2_REG(base) ((base)->USR2) +#define UART_UESC_REG(base) ((base)->UESC) +#define UART_UTIM_REG(base) ((base)->UTIM) +#define UART_UBIR_REG(base) ((base)->UBIR) +#define UART_UBMR_REG(base) ((base)->UBMR) +#define UART_UBRC_REG(base) ((base)->UBRC) +#define UART_ONEMS_REG(base) ((base)->ONEMS) +#define UART_UTS_REG(base) ((base)->UTS) +#define UART_UMCR_REG(base) ((base)->UMCR) + +/*! + * @} + */ /* end of group UART_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* URXD Bit Fields */ +#define UART_URXD_RX_DATA_MASK 0xFFu +#define UART_URXD_RX_DATA_SHIFT 0 +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<ID) +#define USB_HWGENERAL_REG(base) ((base)->HWGENERAL) +#define USB_HWHOST_REG(base) ((base)->HWHOST) +#define USB_HWDEVICE_REG(base) ((base)->HWDEVICE) +#define USB_HWTXBUF_REG(base) ((base)->HWTXBUF) +#define USB_HWRXBUF_REG(base) ((base)->HWRXBUF) +#define USB_GPTIMER0LD_REG(base) ((base)->GPTIMER0LD) +#define USB_GPTIMER0CTRL_REG(base) ((base)->GPTIMER0CTRL) +#define USB_GPTIMER1LD_REG(base) ((base)->GPTIMER1LD) +#define USB_GPTIMER1CTRL_REG(base) ((base)->GPTIMER1CTRL) +#define USB_SBUSCFG_REG(base) ((base)->SBUSCFG) +#define USB_CAPLENGTH_REG(base) ((base)->CAPLENGTH) +#define USB_HCIVERSION_REG(base) ((base)->HCIVERSION) +#define USB_HCSPARAMS_REG(base) ((base)->HCSPARAMS) +#define USB_HCCPARAMS_REG(base) ((base)->HCCPARAMS) +#define USB_DCIVERSION_REG(base) ((base)->DCIVERSION) +#define USB_DCCPARAMS_REG(base) ((base)->DCCPARAMS) +#define USB_USBCMD_REG(base) ((base)->USBCMD) +#define USB_USBSTS_REG(base) ((base)->USBSTS) +#define USB_USBINTR_REG(base) ((base)->USBINTR) +#define USB_FRINDEX_REG(base) ((base)->FRINDEX) +#define USB_PERIODICLISTBASE_REG(base) ((base)->PERIODICLISTBASE) +#define USB_DEVICEADDR_REG(base) ((base)->DEVICEADDR) +#define USB_ASYNCLISTADDR_REG(base) ((base)->ASYNCLISTADDR.ASYNCLISTADDR) +#define USB_ENDPTLISTADDR_REG(base) ((base)->ENDPTLISTADDR.ENDPTLISTADDR) +#define USB_BURSTSIZE_REG(base) ((base)->BURSTSIZE) +#define USB_TXFILLTUNING_REG(base) ((base)->TXFILLTUNING) +#define USB_ENDPTNAK_REG(base) ((base)->ENDPTNAK) +#define USB_ENDPTNAKEN_REG(base) ((base)->ENDPTNAKEN) +#define USB_CONFIGFLAG_REG(base) ((base)->CONFIGFLAG) +#define USB_PORTSC1_REG(base) ((base)->PORTSC1) +#define USB_OTGSC_REG(base) ((base)->OTGSC) +#define USB_USBMODE_REG(base) ((base)->USBMODE) +#define USB_ENDPTSETUPSTAT_REG(base) ((base)->ENDPTSETUPSTAT) +#define USB_ENDPTPRIME_REG(base) ((base)->ENDPTPRIME) +#define USB_ENDPTFLUSH_REG(base) ((base)->ENDPTFLUSH) +#define USB_ENDPTSTAT_REG(base) ((base)->ENDPTSTAT) +#define USB_ENDPTCOMPLETE_REG(base) ((base)->ENDPTCOMPLETE) +#define USB_ENDPTCTRL0_REG(base) ((base)->ENDPTCTRL0) +#define USB_ENDPTCTRL1_REG(base) ((base)->ENDPTCTRL1) +#define USB_ENDPTCTRL2_REG(base) ((base)->ENDPTCTRL2) +#define USB_ENDPTCTRL3_REG(base) ((base)->ENDPTCTRL3) +#define USB_ENDPTCTRL4_REG(base) ((base)->ENDPTCTRL4) +#define USB_ENDPTCTRL5_REG(base) ((base)->ENDPTCTRL5) +#define USB_ENDPTCTRL6_REG(base) ((base)->ENDPTCTRL6) +#define USB_ENDPTCTRL7_REG(base) ((base)->ENDPTCTRL7) + +/*! + * @} + */ /* end of group USB_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/* ID Bit Fields */ +#define USB_ID_ID_MASK 0x3Fu +#define USB_ID_ID_SHIFT 0 +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x))<OTG1_CTRL1) +#define USBNC_OTG1_CTRL2_REG(base) ((base)->OTG1_CTRL2) +#define USBNC_OTG1_PHY_CFG1_REG(base) ((base)->OTG1_PHY_CFG1) +#define USBNC_OTG1_PHY_CFG2_REG(base) ((base)->OTG1_PHY_CFG2) +#define USBNC_OTG1_PHY_STATUS_REG(base) ((base)->OTG1_PHY_STATUS) +#define USBNC_ADP_CFG1_REG(base) ((base)->ADP_CFG1) +#define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) +#define USBNC_ADP_STATUS_REG(base) ((base)->ADP_STATUS) +#define USBNC_OTG2_CTRL1_REG(base) ((base)->OTG2_CTRL1) +#define USBNC_OTG2_CTRL2_REG(base) ((base)->OTG2_CTRL2) +#define USBNC_OTG2_PHY_CFG1_REG(base) ((base)->OTG2_PHY_CFG1) +#define USBNC_OTG2_PHY_CFG2_REG(base) ((base)->OTG2_PHY_CFG2) +#define USBNC_OTG2_PHY_STATUS_REG(base) ((base)->OTG2_PHY_STATUS) +#define USBNC_HSIC_CTRL1_REG(base) ((base)->HSIC_CTRL1) +#define USBNC_HSIC_CTRL2_REG(base) ((base)->HSIC_CTRL2) +#define USBNC_UH_HSICPHY_CFG1_REG(base) ((base)->UH_HSICPHY_CFG1) + +/*! + * @} + */ /* end of group USBNC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/* OTG1_CTRL1 Bit Fields */ +#define USBNC_OTG1_CTRL1_OVER_CUR_DIS_MASK 0x80u +#define USBNC_OTG1_CTRL1_OVER_CUR_DIS_SHIFT 7 +#define USBNC_OTG1_CTRL1_OVER_CUR_POL_MASK 0x100u +#define USBNC_OTG1_CTRL1_OVER_CUR_POL_SHIFT 8 +#define USBNC_OTG1_CTRL1_PWR_POL_MASK 0x200u +#define USBNC_OTG1_CTRL1_PWR_POL_SHIFT 9 +#define USBNC_OTG1_CTRL1_WIE_MASK 0x400u +#define USBNC_OTG1_CTRL1_WIE_SHIFT 10 +#define USBNC_OTG1_CTRL1_WKUP_SW_EN_MASK 0x4000u +#define USBNC_OTG1_CTRL1_WKUP_SW_EN_SHIFT 14 +#define USBNC_OTG1_CTRL1_WKUP_SW_MASK 0x8000u +#define USBNC_OTG1_CTRL1_WKUP_SW_SHIFT 15 +#define USBNC_OTG1_CTRL1_WKUP_ID_EN_MASK 0x10000u +#define USBNC_OTG1_CTRL1_WKUP_ID_EN_SHIFT 16 +#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_MASK 0x20000u +#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_SHIFT 17 +#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_MASK 0x20000000u +#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_SHIFT 29 +#define USBNC_OTG1_CTRL1_WIR_MASK 0x80000000u +#define USBNC_OTG1_CTRL1_WIR_SHIFT 31 +/* OTG1_CTRL2 Bit Fields */ +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK 0x3u +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT 0 +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x))<WCR) +#define WDOG_WSR_REG(base) ((base)->WSR) +#define WDOG_WRSR_REG(base) ((base)->WRSR) +#define WDOG_WICR_REG(base) ((base)->WICR) +#define WDOG_WMCR_REG(base) ((base)->WMCR) + +/*! + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* WCR Bit Fields */ +#define WDOG_WCR_WDZST_MASK 0x1u +#define WDOG_WCR_WDZST_SHIFT 0 +#define WDOG_WCR_WDBG_MASK 0x2u +#define WDOG_WCR_WDBG_SHIFT 1 +#define WDOG_WCR_WDE_MASK 0x4u +#define WDOG_WCR_WDE_SHIFT 2 +#define WDOG_WCR_WDT_MASK 0x8u +#define WDOG_WCR_WDT_SHIFT 3 +#define WDOG_WCR_SRS_MASK 0x10u +#define WDOG_WCR_SRS_SHIFT 4 +#define WDOG_WCR_WDA_MASK 0x20u +#define WDOG_WCR_WDA_SHIFT 5 +#define WDOG_WCR_SRE_MASK 0x40u +#define WDOG_WCR_SRE_SHIFT 6 +#define WDOG_WCR_WDW_MASK 0x80u +#define WDOG_WCR_WDW_SHIFT 7 +#define WDOG_WCR_WT_MASK 0xFF00u +#define WDOG_WCR_WT_SHIFT 8 +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<CTRL_24M) +#define XTALOSC_CTRL_24M_SET_REG(base) ((base)->CTRL_24M_SET) +#define XTALOSC_CTRL_24M_CLR_REG(base) ((base)->CTRL_24M_CLR) +#define XTALOSC_CTRL_24M_TOG_REG(base) ((base)->CTRL_24M_TOG) +#define XTALOSC_RCOSC_CONFIG0_REG(base) ((base)->RCOSC_CONFIG0) +#define XTALOSC_RCOSC_CONFIG0_SET_REG(base) ((base)->RCOSC_CONFIG0_SET) +#define XTALOSC_RCOSC_CONFIG0_CLR_REG(base) ((base)->RCOSC_CONFIG0_CLR) +#define XTALOSC_RCOSC_CONFIG0_TOG_REG(base) ((base)->RCOSC_CONFIG0_TOG) +#define XTALOSC_RCOSC_CONFIG1_REG(base) ((base)->RCOSC_CONFIG1) +#define XTALOSC_RCOSC_CONFIG1_SET_REG(base) ((base)->RCOSC_CONFIG1_SET) +#define XTALOSC_RCOSC_CONFIG1_CLR_REG(base) ((base)->RCOSC_CONFIG1_CLR) +#define XTALOSC_RCOSC_CONFIG1_TOG_REG(base) ((base)->RCOSC_CONFIG1_TOG) +#define XTALOSC_RCOSC_CONFIG2_REG(base) ((base)->RCOSC_CONFIG2) +#define XTALOSC_RCOSC_CONFIG2_SET_REG(base) ((base)->RCOSC_CONFIG2_SET) +#define XTALOSC_RCOSC_CONFIG2_CLR_REG(base) ((base)->RCOSC_CONFIG2_CLR) +#define XTALOSC_RCOSC_CONFIG2_TOG_REG(base) ((base)->RCOSC_CONFIG2_TOG) +#define XTALOSC_OSC_32K_REG(base) ((base)->OSC_32K) +#define XTALOSC_OSC_32K_SET_REG(base) ((base)->OSC_32K_SET) +#define XTALOSC_OSC_32K_CLR_REG(base) ((base)->OSC_32K_CLR) +#define XTALOSC_OSC_32K_TOG_REG(base) ((base)->OSC_32K_TOG) + +/*! + * @} + */ /* end of group XTALOSC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- XTALOSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks + * @{ + */ + +/* CTRL_24M Bit Fields */ +#define XTALOSC_CTRL_24M_XTAL_24M_PWD_MASK 0x1u +#define XTALOSC_CTRL_24M_XTAL_24M_PWD_SHIFT 0 +#define XTALOSC_CTRL_24M_XTAL_24M_EN_MASK 0x2u +#define XTALOSC_CTRL_24M_XTAL_24M_EN_SHIFT 1 +#define XTALOSC_CTRL_24M_OSC_XTALOK_MASK 0x4u +#define XTALOSC_CTRL_24M_OSC_XTALOK_SHIFT 2 +#define XTALOSC_CTRL_24M_OSC_XTALOK_EN_MASK 0x8u +#define XTALOSC_CTRL_24M_OSC_XTALOK_EN_SHIFT 3 +#define XTALOSC_CTRL_24M_CLKGATE_CTRL_MASK 0x10u +#define XTALOSC_CTRL_24M_CLKGATE_CTRL_SHIFT 4 +#define XTALOSC_CTRL_24M_CLKGATE_DELAY_MASK 0xE0u +#define XTALOSC_CTRL_24M_CLKGATE_DELAY_SHIFT 5 +#define XTALOSC_CTRL_24M_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<DS_ADDR) +#define uSDHC_BLK_ATT_REG(base) ((base)->BLK_ATT) +#define uSDHC_CMD_ARG_REG(base) ((base)->CMD_ARG) +#define uSDHC_CMD_XFR_TYP_REG(base) ((base)->CMD_XFR_TYP) +#define uSDHC_CMD_RSP0_REG(base) ((base)->CMD_RSP0) +#define uSDHC_CMD_RSP1_REG(base) ((base)->CMD_RSP1) +#define uSDHC_CMD_RSP2_REG(base) ((base)->CMD_RSP2) +#define uSDHC_CMD_RSP3_REG(base) ((base)->CMD_RSP3) +#define uSDHC_DATA_BUFF_ACC_PORT_REG(base) ((base)->DATA_BUFF_ACC_PORT) +#define uSDHC_PRES_STATE_REG(base) ((base)->PRES_STATE) +#define uSDHC_PROT_CTRL_REG(base) ((base)->PROT_CTRL) +#define uSDHC_SYS_CTRL_REG(base) ((base)->SYS_CTRL) +#define uSDHC_INT_STATUS_REG(base) ((base)->INT_STATUS) +#define uSDHC_INT_STATUS_EN_REG(base) ((base)->INT_STATUS_EN) +#define uSDHC_INT_SIGNAL_EN_REG(base) ((base)->INT_SIGNAL_EN) +#define uSDHC_AUTOCMD12_ERR_STATUS_REG(base) ((base)->AUTOCMD12_ERR_STATUS) +#define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP) +#define uSDHC_WTMK_LVL_REG(base) ((base)->WTMK_LVL) +#define uSDHC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) +#define uSDHC_FORCE_EVENT_REG(base) ((base)->FORCE_EVENT) +#define uSDHC_ADMA_ERR_STATUS_REG(base) ((base)->ADMA_ERR_STATUS) +#define uSDHC_ADMA_SYS_ADDR_REG(base) ((base)->ADMA_SYS_ADDR) +#define uSDHC_DLL_CTRL_REG(base) ((base)->DLL_CTRL) +#define uSDHC_DLL_STATUS_REG(base) ((base)->DLL_STATUS) +#define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base) ((base)->CLK_TUNE_CTRL_STATUS) +#define uSDHC_STROBE_DLL_CTRL_REG(base) ((base)->STROBE_DLL_CTRL) +#define uSDHC_STROBE_DLL_STATUS_REG(base) ((base)->STROBE_DLL_STATUS) +#define uSDHC_VEND_SPEC_REG(base) ((base)->VEND_SPEC) +#define uSDHC_MMC_BOOT_REG(base) ((base)->MMC_BOOT) +#define uSDHC_VEND_SPEC2_REG(base) ((base)->VEND_SPEC2) +#define uSDHC_TUNING_CTRL_REG(base) ((base)->TUNING_CTRL) + +/*! + * @} + */ /* end of group uSDHC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- uSDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup uSDHC_Register_Masks uSDHC Register Masks + * @{ + */ + +/* DS_ADDR Bit Fields */ +#define uSDHC_DS_ADDR_DS_ADDR_MASK 0xFFFFFFFCu +#define uSDHC_DS_ADDR_DS_ADDR_SHIFT 2 +#define uSDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x))<> 2; + break; + case ccmRootmuxCanSysPllDiv1: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG); + break; + default: + return 0; + } + + return hz / (pre + 1) / (post + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_I2C_clock_freq + * Description : Get clock frequency applys to the I2C module + * + *END**************************************************************************/ +uint32_t get_i2c_clock_freq(I2C_Type *base) +{ + uint32_t root; + uint32_t hz; + uint32_t pre, post; + + switch ((uint32_t)base) { + case I2C1_BASE: + root = CCM_GetRootMux(CCM, ccmRootI2c1); + CCM_GetRootDivider(CCM, ccmRootI2c1, &pre, &post); + break; + case I2C2_BASE: + root = CCM_GetRootMux(CCM, ccmRootI2c2); + CCM_GetRootDivider(CCM, ccmRootI2c2, &pre, &post); + break; + case I2C3_BASE: + root = CCM_GetRootMux(CCM, ccmRootI2c3); + CCM_GetRootDivider(CCM, ccmRootI2c3, &pre, &post); + break; + case I2C4_BASE: + root = CCM_GetRootMux(CCM, ccmRootI2c4); + CCM_GetRootDivider(CCM, ccmRootI2c4, &pre, &post); + break; + default: + return 0; + } + + switch (root) { + case ccmRootmuxI2cOsc24m: + hz = 24000000; + break; + case ccmRootmuxI2cSysPllDiv4: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG) >> 2; + break; + default: + return 0; + } + + return hz / (pre + 1) / (post + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_uart_clock_freq + * Description : Get clock frequency applys to the UART module + * + *END**************************************************************************/ +uint32_t get_uart_clock_freq(UART_Type *base) +{ + uint32_t root; + uint32_t hz; + uint32_t pre, post; + + switch ((uint32_t)base) { + case UART1_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart1); + CCM_GetRootDivider(CCM, ccmRootUart1, &pre, &post); + break; + case UART2_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart2); + CCM_GetRootDivider(CCM, ccmRootUart2, &pre, &post); + break; + case UART3_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart3); + CCM_GetRootDivider(CCM, ccmRootUart3, &pre, &post); + break; + case UART4_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart4); + CCM_GetRootDivider(CCM, ccmRootUart4, &pre, &post); + break; + case UART5_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart5); + CCM_GetRootDivider(CCM, ccmRootUart5, &pre, &post); + break; + case UART6_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart6); + CCM_GetRootDivider(CCM, ccmRootUart6, &pre, &post); + break; + case UART7_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart7); + CCM_GetRootDivider(CCM, ccmRootUart7, &pre, &post); + break; + default: + return 0; + } + + switch (root) { + case ccmRootmuxUartOsc24m: + hz = 24000000; + break; + case ccmRootmuxUartSysPllDiv2: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG) >> 1; + break; + case ccmRootmuxUartSysPllDiv1: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG); + break; + default: + return 0; + } + + return hz / (pre + 1) / (post + 1); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/devices/MCIMX7D/clock_freq.h b/zephyr/imx/devices/MCIMX7D/clock_freq.h new file mode 100644 index 000000000..38602620a --- /dev/null +++ b/zephyr/imx/devices/MCIMX7D/clock_freq.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CLOCK_FREQ_H__ +#define __CLOCK_FREQ_H__ + +#include "device_imx.h" + +/*! + * @addtogroup clock_freq_helper + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Get clock frequency applies to the GPT module + * + * @param base GPT base pointer. + * @return clock frequency (in HZ) applies to the GPT module + */ +uint32_t get_gpt_clock_freq(GPT_Type *base); + +/*! + * @brief Get clock frequency applies to the ECSPI module + * + * @param base ECSPI base pointer. + * @return clock frequency (in HZ) applies to the ECSPI module + */ +uint32_t get_ecspi_clock_freq(ECSPI_Type *base); + +/*! + * @brief Get clock frequency applies to the FLEXCAN module + * + * @param base CAN base pointer. + * @return clock frequency (in HZ) applies to the FLEXCAN module + */ +uint32_t get_flexcan_clock_freq(CAN_Type *base); + +/*! + * @brief Get clock frequency applies to the I2C module + * + * @param base I2C base pointer. + * @return clock frequency (in HZ) applies to the I2C module + */ +uint32_t get_i2c_clock_freq(I2C_Type *base); + +/*! + * @brief Get clock frequency applies to the UART module + * + * @param base UART base pointer. + * @return clock frequency (in HZ) applies to the UART module + */ +uint32_t get_uart_clock_freq(UART_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CLOCK_FREQ_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/devices/device_imx.h b/zephyr/imx/devices/device_imx.h new file mode 100644 index 000000000..00f1e8b15 --- /dev/null +++ b/zephyr/imx/devices/device_imx.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* +** ################################################################### +** Abstract: +** Common include file for CMSIS register access layer headers. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ + +#ifndef __DEVICE_IMX_H__ +#define __DEVICE_IMX_H__ + +/* + * Include the cpu specific register header files. + * + * The CPU macro should be declared in the project or makefile. + */ +#if defined(CONFIG_SOC_MCIMX6X_M4) + + /* CMSIS-style register definitions */ + #include "MCIMX6X_M4.h" + #define RDC_SEMAPHORE_MASTER_SELF (5) + #define SEMA4_PROCESSOR_SELF (1) + +#elif defined(CONFIG_SOC_MCIMX7_M4) + + /* CMSIS-style register definitions */ + #include "MCIMX7D_M4.h" + + #define RDC_SEMAPHORE_MASTER_SELF (6) + #define SEMA4_PROCESSOR_SELF (1) + +#else + #error "No valid CPU defined!" +#endif + +#endif /* __DEVICE_IMX_H__ */ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/CMakeLists.txt b/zephyr/imx/drivers/CMakeLists.txt new file mode 100644 index 000000000..e72989696 --- /dev/null +++ b/zephyr/imx/drivers/CMakeLists.txt @@ -0,0 +1,21 @@ +zephyr_include_directories(.) + +if(CONFIG_SOC_MCIMX7_M4) +zephyr_library_sources( + ccm_imx7d.c + ccm_analog_imx7d.c +) +endif() + +if(CONFIG_SOC_MCIMX6X_M4) +zephyr_library_sources( + ccm_imx6sx.c + ccm_analog_imx6sx.c +) +endif() + +zephyr_library_sources_ifdef(CONFIG_COUNTER_IMX_EPIT epit.c) +zephyr_library_sources_ifdef(CONFIG_GPIO_IMX gpio_imx.c) +zephyr_library_sources_ifdef(CONFIG_I2C_IMX i2c_imx.c) +zephyr_library_sources_ifdef(CONFIG_IPM_IMX mu_imx.c) +zephyr_library_sources_ifdef(CONFIG_UART_IMX uart_imx.c) diff --git a/zephyr/imx/drivers/adc_imx6sx.c b/zephyr/imx/drivers/adc_imx6sx.c new file mode 100644 index 000000000..4b1946585 --- /dev/null +++ b/zephyr/imx/drivers/adc_imx6sx.c @@ -0,0 +1,519 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "adc_imx6sx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_Init + * Description : Initialize ADC to reset state and initialize with initialize + * structure. + * + *END**************************************************************************/ +void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig) +{ + assert(initConfig); + + /* Reset ADC register to its default value. */ + ADC_Deinit(base); + + /* Set hardware average function and number. */ + if (initConfig->averageNumber != adcAvgNumNone) + { + ADC_GC_REG(base) |= ADC_GC_AVGE_MASK; + ADC_CFG_REG(base) |= ADC_CFG_AVGS(initConfig->averageNumber); + } + + /* Set resolution mode. */ + ADC_CFG_REG(base) |= ADC_CFG_MODE(initConfig->resolutionMode); + + /* Set clock source. */ + ADC_SetClockSource(base, initConfig->clockSource, initConfig->divideRatio); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_Deinit + * Description : This function reset ADC module register content to its + * default value. + * + *END**************************************************************************/ +void ADC_Deinit(ADC_Type* base) +{ + /* Reset ADC Module Register content to default value */ + ADC_HC0_REG(base) = ADC_HC0_ADCH_MASK; + ADC_HC1_REG(base) = ADC_HC1_ADCH_MASK; + ADC_R0_REG(base) = 0x0; + ADC_R1_REG(base) = 0x0; + ADC_CFG_REG(base) = ADC_CFG_ADSTS(2); + ADC_GC_REG(base) = 0x0; + ADC_GS_REG(base) = ADC_GS_CALF_MASK | ADC_GS_AWKST_MASK; + ADC_CV_REG(base) = 0x0; + ADC_OFS_REG(base) = 0x0; + ADC_CAL_REG(base) = 0x0; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertResultOverwrite + * Description : Enable or disable ADC overwrite conversion result register. + * + *END**************************************************************************/ +void ADC_SetConvertResultOverwrite(ADC_Type* base, bool enable) +{ + if(enable) + ADC_CFG_REG(base) |= ADC_CFG_OVWREN_MASK; + else + ADC_CFG_REG(base) &= ~ADC_CFG_OVWREN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertTrigMode + * Description : This function is used to set conversion trigger mode. + * + *END**************************************************************************/ +void ADC_SetConvertTrigMode(ADC_Type* base, uint8_t mode) +{ + assert(mode <= adcHardwareTrigger); + + if(mode == adcHardwareTrigger) + ADC_CFG_REG(base) |= ADC_CFG_ADTRG_MASK; + else + ADC_CFG_REG(base) &= ~ADC_CFG_ADTRG_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertSpeed + * Description : This function is used to set conversion speed mode. + * + *END**************************************************************************/ +void ADC_SetConvertSpeed(ADC_Type* base, uint8_t mode) +{ + assert(mode <= adcHighSpeed); + + if(mode == adcHighSpeed) + ADC_CFG_REG(base) |= ADC_CFG_ADHSC_MASK; + else + ADC_CFG_REG(base) &= ~ADC_CFG_ADHSC_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetSampleTimeDuration + * Description : This function is used to set sample time duration. + * + *END**************************************************************************/ +void ADC_SetSampleTimeDuration(ADC_Type* base, uint8_t duration) +{ + assert(duration <= adcSamplePeriodClock24); + + switch(duration) + { + case adcSamplePeriodClock2: + ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(0U); + break; + + case adcSamplePeriodClock4: + ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(1U); + break; + + case adcSamplePeriodClock6: + ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(2U); + break; + + case adcSamplePeriodClock8: + ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(3U); + break; + + case adcSamplePeriodClock12: + ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(0U); + break; + + case adcSamplePeriodClock16: + ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(1U); + break; + + case adcSamplePeriodClock20: + ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(2U); + break; + + case adcSamplePeriodClock24: + ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(3U); + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetPowerMode + * Description : This function is used to set power mode. + * + *END**************************************************************************/ +void ADC_SetPowerMode(ADC_Type* base, uint8_t powerMode) +{ + assert(powerMode <= adcLowPowerMode); + + if(powerMode == adcLowPowerMode) + ADC_CFG_REG(base) |= ADC_CFG_ADLPC_MASK; + else + ADC_CFG_REG(base) &= ~ADC_CFG_ADLPC_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetClockSource + * Description : This function is used to set ADC clock source. + * + *END**************************************************************************/ +void ADC_SetClockSource(ADC_Type* base, uint8_t source, uint8_t div) +{ + assert(source <= adcAsynClock); + assert(div <= adcInputClockDiv8); + + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADIV_MASK)) | + ADC_CFG_ADIV(div); + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADICLK_MASK)) | + ADC_CFG_ADICLK(source); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAsynClockOutput + * Description : This function is used to enable asynchronous clock source output + * regardless of the state of ADC. + * + *END**************************************************************************/ +void ADC_SetAsynClockOutput(ADC_Type* base, bool enable) +{ + if(enable) + ADC_GC_REG(base) |= ADC_GC_ADACKEN_MASK; + else + ADC_GC_REG(base) &= ~ADC_GC_ADACKEN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCalibration + * Description : Enable or disable calibration function. + * + *END**************************************************************************/ +void ADC_SetCalibration(ADC_Type* base, bool enable) +{ + if(enable) + ADC_GC_REG(base) |= ADC_GC_CAL_MASK; + else + ADC_GC_REG(base) &= ~ADC_GC_CAL_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertCmd + * Description : Enable continuous conversion and start a conversion on target channel. + * This function is only used for software trigger mode. If configured as + * hardware trigger mode, this function just enable continuous conversion + * and not start the conversion. + * + *END**************************************************************************/ +void ADC_SetConvertCmd(ADC_Type* base, uint8_t channel, bool enable) +{ + uint8_t triggerMode; + + /* Enable continuous conversion. */ + if(enable) + { + ADC_GC_REG(base) |= ADC_GC_ADCO_MASK; + /* Start the conversion. */ + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + ADC_HC0_REG(base) = (ADC_HC0_REG(base) & (~ADC_HC0_ADCH_MASK)) | + ADC_HC0_ADCH(channel); + else /* Just set the channel. */ + ADC_HC1_REG(base) = (ADC_HC1_REG(base) & (~ADC_HC1_ADCH_MASK)) | + ADC_HC1_ADCH(channel); + } + else + ADC_GC_REG(base) &= ~ADC_GC_ADCO_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_TriggerSingleConvert + * Description : Enable single conversion and trigger single time conversion + * on target imput channel. If configured as hardware trigger + * mode, this function just set input channel and not start a + * conversion. + * + *END**************************************************************************/ +void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t channel) +{ + uint8_t triggerMode; + + /* Enable single conversion. */ + ADC_GC_REG(base) &= ~ADC_GC_ADCO_MASK; + /* Start the conversion. */ + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + ADC_HC0_REG(base) = (ADC_HC0_REG(base) & (~ADC_HC0_ADCH_MASK)) | + ADC_HC0_ADCH(channel); + else /* Just set the channel. */ + ADC_HC1_REG(base) = (ADC_HC1_REG(base) & (~ADC_HC1_ADCH_MASK)) | + ADC_HC1_ADCH(channel); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAverageNum + * Description : This function is used to enable hardware aaverage function + * and set hardware average number. If avgNum is equal to + * adcAvgNumNone, it means disable hardware average function. + * + *END**************************************************************************/ +void ADC_SetAverageNum(ADC_Type* base, uint8_t avgNum) +{ + assert(avgNum <= adcAvgNumNone); + + if(avgNum != adcAvgNumNone) + { + /* Enable hardware average function. */ + ADC_GC_REG(base) |= ADC_GC_AVGE_MASK; + /* Set hardware average number. */ + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_AVGS_MASK)) | + ADC_CFG_AVGS(avgNum); + } + else + { + /* Disable hardware average function. */ + ADC_GC_REG(base) &= ~ADC_GC_AVGE_MASK; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_StopConvert + * Description : This function is used to stop all conversions. + * + *END**************************************************************************/ +void ADC_StopConvert(ADC_Type* base) +{ + uint8_t triggerMode; + + triggerMode = ADC_GetConvertTrigMode(base); + /* According trigger mode to set specific register. */ + if(triggerMode == adcSoftwareTrigger) + ADC_HC0_REG(base) |= ADC_HC0_ADCH_MASK; + else + ADC_HC1_REG(base) |= ADC_HC1_ADCH_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_GetConvertResult + * Description : This function is used to get conversion result. + * + *END**************************************************************************/ +uint16_t ADC_GetConvertResult(ADC_Type* base) +{ + uint8_t triggerMode; + + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + return (uint16_t)((ADC_R0_REG(base) & ADC_R0_D_MASK) >> ADC_R0_D_SHIFT); + else + return (uint16_t)((ADC_R1_REG(base) & ADC_R1_D_MASK) >> ADC_R1_D_SHIFT); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCmpMode + * Description : This function is used to enable compare function + * and set comparer mode. + * + *END**************************************************************************/ +void ADC_SetCmpMode(ADC_Type* base, uint8_t cmpMode, uint16_t cmpVal1, uint16_t cmpVal2) +{ + assert(cmpMode <= adcCmpModeDisable); + + switch(cmpMode) + { + case adcCmpModeLessThanCmpVal1: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) &= ~(ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + break; + + case adcCmpModeGreaterThanCmpVal1: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACFGT_MASK) & (~ADC_GC_ACREN_MASK); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + break; + + case adcCmpModeOutRangNotInclusive: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACREN_MASK) & (~ADC_GC_ACFGT_MASK); + if(cmpVal1 <= cmpVal2) + { + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2); + } + break; + + case adcCmpModeInRangNotInclusive: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACREN_MASK) & (~ADC_GC_ACFGT_MASK); + if(cmpVal1 > cmpVal2) + { + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2); + } + break; + + case adcCmpModeInRangInclusive: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) |= ADC_GC_ACREN_MASK | ADC_GC_ACFGT_MASK; + if(cmpVal1 <= cmpVal2) + { + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2); + } + break; + + case adcCmpModeOutRangInclusive: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) |= ADC_GC_ACREN_MASK | ADC_GC_ACFGT_MASK; + if(cmpVal1 > cmpVal2) + { + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2); + } + break; + + case adcCmpModeDisable: + ADC_GC_REG(base) &= ~ADC_GC_ACFE_MASK; + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCorrectionMode + * Description : This function is used to set offset correct mode. + * + *END**************************************************************************/ +void ADC_SetCorrectionMode(ADC_Type* base, bool correctMode) +{ + if(correctMode) + ADC_OFS_REG(base) |= ADC_OFS_SIGN_MASK; + else + ADC_OFS_REG(base) &= ~ADC_OFS_SIGN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetIntCmd + * Description : Enables or disables ADC conversion complete interrupt request. + * + *END**************************************************************************/ +void ADC_SetIntCmd(ADC_Type* base, bool enable) +{ + uint8_t triggerMode; + + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + { + if(enable) + ADC_HC0_REG(base) |= ADC_HC0_AIEN_MASK; + else + ADC_HC0_REG(base) &= ~ADC_HC0_AIEN_MASK; + } + else + { + if(enable) + ADC_HC1_REG(base) |= ADC_HC1_AIEN_MASK; + else + ADC_HC1_REG(base) &= ~ADC_HC1_AIEN_MASK; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_IsConvertComplete + * Description : This function is used to get ADC conversion complete status. + * + *END**************************************************************************/ +bool ADC_IsConvertComplete(ADC_Type* base) +{ + uint8_t triggerMode; + + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + return (bool)((ADC_HS_REG(base) & ADC_HS_COCO0_MASK) >> ADC_HS_COCO0_SHIFT); + else + return (bool)((ADC_HS_REG(base) & ADC_HS_COCO1_MASK) >> ADC_HS_COCO1_SHIFT); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetDmaCmd + * Description : Enable or disable DMA request. + * + *END**************************************************************************/ +void ADC_SetDmaCmd(ADC_Type* base, bool enable) +{ + if (enable) + ADC_GC_REG(base) |= ADC_GC_DMAEN_MASK; + else + ADC_GC_REG(base) &= ~ADC_GC_DMAEN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/adc_imx6sx.h b/zephyr/imx/drivers/adc_imx6sx.h new file mode 100644 index 000000000..2b8f794c0 --- /dev/null +++ b/zephyr/imx/drivers/adc_imx6sx.h @@ -0,0 +1,513 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ADC_IMX6SX_H__ +#define __ADC_IMX6SX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup adc_imx6sx_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief ADC module initialize structure. */ +typedef struct _adc_init_config +{ + uint8_t clockSource; /*!< Select input clock source to generate the internal conversion clock.*/ + uint8_t divideRatio; /*!< Selects divide ratio used to generate the internal conversion clock.*/ + uint8_t averageNumber; /*!< The average number for hardware average function.*/ + uint8_t resolutionMode; /*!< Set ADC resolution mode.*/ +} adc_init_config_t; + +/*! @brief ADC hardware average number. */ +enum _adc_average_number +{ + adcAvgNum4 = 0U, /*!< ADC Hardware Average Number is set to 4.*/ + adcAvgNum8 = 1U, /*!< ADC Hardware Average Number is set to 8.*/ + adcAvgNum16 = 2U, /*!< ADC Hardware Average Number is set to 16.*/ + adcAvgNum32 = 3U, /*!< ADC Hardware Average Number is set to 32.*/ + adcAvgNumNone = 4U, /*!< Disable ADC Hardware Average.*/ +}; + +/*! @brief ADC conversion trigger select. */ +enum _adc_convert_trigger_mode +{ + adcSoftwareTrigger = 0U, /*!< ADC software trigger a conversion.*/ + adcHardwareTrigger = 1U, /*!< ADC hardware trigger a conversion.*/ +}; + +/*! @brief ADC conversion speed configure. */ +enum _adc_convert_speed_config +{ + adcNormalSpeed = 0U, /*!< ADC set as normal conversion speed.*/ + adcHighSpeed = 1U, /*!< ADC set as high conversion speed.*/ +}; + +/*! @brief ADC sample time duration. */ +enum _adc_sample_time_duration +{ + adcSamplePeriodClock2, /*!< The sample time duration is set as 2 ADC clocks.*/ + adcSamplePeriodClock4, /*!< The sample time duration is set as 4 ADC clocks.*/ + adcSamplePeriodClock6, /*!< The sample time duration is set as 6 ADC clocks.*/ + adcSamplePeriodClock8, /*!< The sample time duration is set as 8 ADC clocks.*/ + adcSamplePeriodClock12, /*!< The sample time duration is set as 12 ADC clocks.*/ + adcSamplePeriodClock16, /*!< The sample time duration is set as 16 ADC clocks.*/ + adcSamplePeriodClock20, /*!< The sample time duration is set as 20 ADC clocks.*/ + adcSamplePeriodClock24, /*!< The sample time duration is set as 24 ADC clocks.*/ +}; + +/*! @brief ADC low power configure. */ +enum _adc_power_mode +{ + adcNormalPowerMode = 0U, /*!< ADC hard block set as normal power mode.*/ + adcLowPowerMode = 1U, /*!< ADC hard block set as low power mode.*/ +}; + +/*! @brief ADC conversion resolution mode. */ +enum _adc_resolution_mode +{ + adcResolutionBit8 = 0U, /*!< ADC resolution set as 8 bit conversion mode.*/ + adcResolutionBit10 = 1U, /*!< ADC resolution set as 10 bit conversion mode.*/ + adcResolutionBit12 = 2U, /*!< ADC resolution set as 12 bit conversion mode.*/ +}; + +/*! @brief ADC input clock divide. */ +enum _adc_clock_divide +{ + adcInputClockDiv1 = 0U, /*!< Input clock divide 1 to generate internal clock.*/ + adcInputClockDiv2 = 1U, /*!< Input clock divide 2 to generate internal clock.*/ + adcInputClockDiv4 = 2U, /*!< Input clock divide 4 to generate internal clock.*/ + adcInputClockDiv8 = 3U, /*!< Input clock divide 8 to generate internal clock.*/ +}; + +/*! @brief ADC clock source. */ +enum _adc_clock_source +{ + adcIpgClock = 0U, /*!< Select ipg clock as input clock source.*/ + adcIpgClockDivide2 = 1U, /*!< Select ipg clock divide 2 as input clock source.*/ + adcAsynClock = 3U, /*!< Select asynchronous clock as input clock source.*/ +}; + +/*! @brief ADC comparer work mode configuration. */ +enum _adc_compare_mode +{ + adcCmpModeLessThanCmpVal1, /*!< Compare true if the result is less than compare value 1.*/ + adcCmpModeGreaterThanCmpVal1, /*!< Compare true if the result is greater than or equal to compare value 1.*/ + adcCmpModeOutRangNotInclusive, /*!< Compare true if the result is less than compare value 1 or the result is Greater than compare value 2.*/ + adcCmpModeInRangNotInclusive, /*!< Compare true if the result is less than compare value 1 and the result is greater than compare value 2.*/ + adcCmpModeInRangInclusive, /*!< Compare true if the result is greater than or equal to compare value 1 and the result is less than or equal to compare value 2.*/ + adcCmpModeOutRangInclusive, /*!< Compare true if the result is greater than or equal to compare value 1 or the result is less than or equal to compare value 2.*/ + adcCmpModeDisable, /*!< ADC compare function disable.*/ +}; + +/*! @brief ADC general status flag. */ +enum _adc_general_status_flag +{ + adcFlagAsynWakeUpInt = 1U << 0, /*!< Indicate asynchronous wake up interrupt occurred in stop mode.*/ + adcFlagCalibrateFailed = 1U << 1, /*!< Indicate the result of the calibration sequence.*/ + adcFlagConvertActive = 1U << 2, /*!< Indicate a conversion is in the process.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name ADC Module Initialization and Configuration Functions. + * @{ + */ + +/*! + * @brief Initialize ADC to reset state and initialize with initialize structure. + * + * @param base ADC base pointer. + * @param initConfig ADC initialize structure. + */ +void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig); + +/*! + * @brief This function reset ADC module register content to its default value. + * + * @param base ADC base pointer. + */ +void ADC_Deinit(ADC_Type* base); + +/*! + * @brief Enable or disable ADC module overwrite conversion result. + * + * @param base ADC base pointer. + * @param enable Enable/Disable conversion result overwire function. + * - true: Enable conversion result overwire. + * - false: Disable conversion result overwrite. + */ +void ADC_SetConvertResultOverwrite(ADC_Type* base, bool enable); + +/*! + * @brief This function set ADC module conversion trigger mode. + * + * @param base ADC base pointer. + * @param mode Conversion trigger (see @ref _adc_convert_trigger_mode enumeration). + */ +void ADC_SetConvertTrigMode(ADC_Type* base, uint8_t mode); + +/*! + * @brief This function is used to get conversion trigger mode. + * + * @param base ADC base pointer. + * @return Conversion trigger mode (see @ref _adc_convert_trigger_mode enumeration). + */ +static inline uint8_t ADC_GetConvertTrigMode(ADC_Type* base) +{ + return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADTRG_MASK) >> ADC_CFG_ADTRG_SHIFT); +} + +/*! + * @brief This function set ADC module conversion speed mode. + * + * @param base ADC base pointer. + * @param mode Conversion speed mode (see @ref _adc_convert_speed_config enumeration). + */ +void ADC_SetConvertSpeed(ADC_Type* base, uint8_t mode); + +/*! + * @brief This function get ADC module conversion speed mode. + * + * @param base ADC base pointer. + * @return Conversion speed mode. + */ +static inline uint8_t ADC_GetConvertSpeed(ADC_Type* base) +{ + return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADHSC_MASK) >> ADC_CFG_ADHSC_SHIFT); +} + +/*! + * @brief This function set ADC module sample time duration. + * + * @param base ADC base pointer. + * @param duration Sample time duration (see @ref _adc_sample_time_duration enumeration). + */ +void ADC_SetSampleTimeDuration(ADC_Type* base, uint8_t duration); + +/*! + * @brief This function set ADC module power mode. + * + * @param base ADC base pointer. + * @param powerMode power mode (see @ref _adc_power_mode enumeration). + */ +void ADC_SetPowerMode(ADC_Type* base, uint8_t powerMode); + +/*! + * @brief This function get ADC module power mode. + * + * @param base ADC base pointer. + * @return Power mode. + */ +static inline uint8_t ADC_GetPowerMode(ADC_Type* base) +{ + return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADLPC_MASK) >> ADC_CFG_ADLPC_SHIFT); +} + +/*! + * @brief This function set ADC module clock source. + * + * @param base ADC base pointer. + * @param source Conversion clock source (see @ref _adc_clock_source enumeration). + * @param div Input clock divide ratio (see @ref _adc_clock_divide enumeration). + */ +void ADC_SetClockSource(ADC_Type* base, uint8_t source, uint8_t div); + +/*! + * @brief This function enable asynchronous clock source output regardless of the + * state of ADC and input clock select of ADC module. Setting this bit + * allows the clock to be used even while the ADC is idle or operating from + * a different clock source. + * + * @param base ADC base pointer. + * @param enable Asynchronous clock output enable. + * - true: Enable asynchronous clock output regardless of the state of ADC; + * - false: Only enable if selected as ADC input clock source and a + * ADC conversion is active. + */ +void ADC_SetAsynClockOutput(ADC_Type* base, bool enable); + +/*@}*/ + +/*! + * @name ADC Calibration Control Functions. + * @{ + */ + +/*! + * @brief This function is used to enable or disable calibration function. + * + * @param base ADC base pointer. + * @param enable Enable/Disable calibration function. + * - true: Enable calibration function. + * - false: Disable calibration function. + */ +void ADC_SetCalibration(ADC_Type* base, bool enable); + +/*! + * @brief This function is used to get calibrate result value. + * + * @param base ADC base pointer. + * @return Calibration result value. + */ +static inline uint8_t ADC_GetCalibrationResult(ADC_Type* base) +{ + return (uint8_t)((ADC_CAL_REG(base) & ADC_CAL_CAL_CODE_MASK) >> ADC_CAL_CAL_CODE_SHIFT); +} + +/*@}*/ + +/*! + * @name ADC Module Conversion Control Functions. + * @{ + */ + +/*! + * @brief Enable continuous conversion and start a conversion on target channel. + * This function is only used for software trigger mode. If configured as + * hardware trigger mode, this function just enable continuous conversion mode + * and not start the conversion. + * + * @param base ADC base pointer. + * @param channel Input channel selection. + * @param enable Enable/Disable continuous conversion. + * - true: Enable and start continuous conversion. + * - false: Disable continuous conversion. + */ +void ADC_SetConvertCmd(ADC_Type* base, uint8_t channel, bool enable); + +/*! + * @brief Enable single conversion and trigger single time conversion + * on target input channel.If configured as hardware trigger + * mode, this function just set input channel and not start a + * conversion. + * + * @param base ADC base pointer. + * @param channel Input channel selection. + */ +void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t channel); + +/*! + * @brief Enable hardware average function and set hardware average number. + * + * @param base ADC base pointer. + * @param avgNum Hardware average number (see @ref _adc_average_number enumeration). + * If avgNum is equal to adcAvgNumNone, it means disable hardware + * average function. + */ +void ADC_SetAverageNum(ADC_Type* base, uint8_t avgNum); + +/*! + * @brief Set conversion resolution mode. + * + * @param base ADC base pointer. + * @param mode resolution mode (see @ref _adc_resolution_mode enumeration). + */ +static inline void ADC_SetResolutionMode(ADC_Type* base, uint8_t mode) +{ + assert(mode <= adcResolutionBit12); + + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_MODE_MASK)) | + ADC_CFG_MODE(mode); +} + +/*! + * @brief Set conversion resolution mode. + * + * @param base ADC base pointer. + * @return Resolution mode (see @ref _adc_resolution_mode enumeration). + */ +static inline uint8_t ADC_GetResolutionMode(ADC_Type* base) +{ + return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_MODE_MASK) >> ADC_CFG_MODE_SHIFT); +} + +/*! + * @brief Set conversion disabled. + * + * @param base ADC base pointer. + */ +void ADC_StopConvert(ADC_Type* base); + +/*! + * @brief Get right aligned conversion result. + * + * @param base ADC base pointer. + * @return Conversion result. + */ +uint16_t ADC_GetConvertResult(ADC_Type* base); + +/*@}*/ + +/*! + * @name ADC Comparer Control Functions. + * @{ + */ + +/*! + * @brief Enable compare function and set the compare work mode of ADC module. + * If cmpMode is equal to adcCmpModeDisable, it means to disable the compare function. + * @param base ADC base pointer. + * @param cmpMode Comparer work mode selected (see @ref _adc_compare_mode enumeration). + * - adcCmpModeLessThanCmpVal1: only set compare value 1; + * - adcCmpModeGreaterThanCmpVal1: only set compare value 1; + * - adcCmpModeOutRangNotInclusive: set compare value 1 less than or equal to compare value 2; + * - adcCmpModeInRangNotInclusive: set compare value 1 greater than compare value 2; + * - adcCmpModeInRangInclusive: set compare value 1 less than or equal to compare value 2; + * - adcCmpModeOutRangInclusive: set compare value 1 greater than compare value 2; + * - adcCmpModeDisable: unnecessary to set compare value 1 and compare value 2. + * @param cmpVal1 Compare threshold 1. + * @param cmpVal2 Compare threshold 2. + */ +void ADC_SetCmpMode(ADC_Type* base, uint8_t cmpMode, uint16_t cmpVal1, uint16_t cmpVal2); + +/*@}*/ + +/*! + * @name Offset Correction Control Functions. + * @{ + */ + +/*! + * @brief Set ADC module offset correct mode. + * + * @param base ADC base pointer. + * @param correctMode Offset correct mode. + * - true: The offset value is subtracted from the raw converted value; + * - false: The offset value is added with the raw result. + */ +void ADC_SetCorrectionMode(ADC_Type* base, bool correctMode); + +/*! + * @brief Set ADC module offset value. + * + * @param base ADC base pointer. + * @param val Offset value. + */ +static inline void ADC_SetOffsetVal(ADC_Type* base, uint16_t val) +{ + ADC_OFS_REG(base) = (ADC_OFS_REG(base) & (~ADC_OFS_OFS_MASK)) | + ADC_OFS_OFS(val); +} + +/*@}*/ + +/*! + * @name Interrupt and Flag Control Functions. + * @{ + */ + +/*! + * @brief Enables or disables ADC conversion complete interrupt request. + * + * @param base ADC base pointer. + * @param enable Enable/Disable ADC conversion complete interrupt. + * - true: Enable conversion complete interrupt. + * - false: Disable conversion complete interrupt. + */ +void ADC_SetIntCmd(ADC_Type* base, bool enable); + +/*! + * @brief Gets the ADC module conversion complete status flag state. + * + * @param base ADC base pointer. + * @retval true: A conversion is completed. + * @retval false: A conversion is not completed. + */ +bool ADC_IsConvertComplete(ADC_Type* base); + +/*! + * @brief Gets the ADC module general status flag state. + * + * @param base ADC base pointer. + * @param flags ADC status flag mask (see @ref _adc_general_status_flag enumeration). + * @return ADC status, each bit represents one status flag. + */ +static inline uint32_t ADC_GetStatusFlag(ADC_Type* base, uint32_t flags) +{ + return (uint32_t)(ADC_GS_REG(base) & flags); +} + +/*! + * @brief Clear one or more ADC status flag state. + * + * @param base ADC base pointer. + * @param flags ADC status flag mask (see @ref _adc_general_status_flag enumeration). + */ +static inline void ADC_ClearStatusFlag(ADC_Type* base, uint32_t flags) +{ + assert(flags < adcFlagConvertActive); + ADC_GS_REG(base) = flags; +} + +/*@}*/ + +/*! + * @name DMA Control Functions. + * @{ + */ + +/*! + * @brief Enable or Disable DMA request. + * + * @param base ADC base pointer. + * @param enable Enable/Disable ADC DMA request. + * - true: Enable DMA request. + * - false: Disable DMA request. + */ +void ADC_SetDmaCmd(ADC_Type* base, bool enable); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __ADC_IMX6SX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/adc_imx7d.c b/zephyr/imx/drivers/adc_imx7d.c new file mode 100644 index 000000000..f2deb5396 --- /dev/null +++ b/zephyr/imx/drivers/adc_imx7d.c @@ -0,0 +1,803 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "adc_imx7d.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * ADC Module Initialization and Configuration functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_Init + * Description : Initialize ADC to reset state and initialize with initialize + * structure. + * + *END**************************************************************************/ +void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig) +{ + assert(initConfig); + + /* Reset ADC register to its default value. */ + ADC_Deinit(base); + + /* Set ADC Module Sample Rate */ + ADC_SetSampleRate(base, initConfig->sampleRate); + + /* Enable ADC Build-in voltage level shifter */ + if (initConfig->levelShifterEnable) + ADC_LevelShifterEnable(base); + else + ADC_LevelShifterDisable(base); + + /* Wait until ADC module power-up completely. */ + while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_Deinit + * Description : This function reset ADC module register content to its + * default value. + * + *END**************************************************************************/ +void ADC_Deinit(ADC_Type* base) +{ + /* Stop all continues conversions */ + ADC_SetConvertCmd(base, adcLogicChA, false); + ADC_SetConvertCmd(base, adcLogicChB, false); + ADC_SetConvertCmd(base, adcLogicChC, false); + ADC_SetConvertCmd(base, adcLogicChD, false); + + /* Reset ADC Module Register content to default value */ + ADC_CH_A_CFG1_REG(base) = 0x0; + ADC_CH_A_CFG2_REG(base) = ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; + ADC_CH_B_CFG1_REG(base) = 0x0; + ADC_CH_B_CFG2_REG(base) = ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; + ADC_CH_C_CFG1_REG(base) = 0x0; + ADC_CH_C_CFG2_REG(base) = ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; + ADC_CH_D_CFG1_REG(base) = 0x0; + ADC_CH_D_CFG2_REG(base) = ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; + ADC_CH_SW_CFG_REG(base) = 0x0; + ADC_TIMER_UNIT_REG(base) = 0x0; + ADC_DMA_FIFO_REG(base) = ADC_DMA_FIFO_DMA_WM_LVL(0xF); + ADC_INT_SIG_EN_REG(base) = 0x0; + ADC_INT_EN_REG(base) = 0x0; + ADC_INT_STATUS_REG(base) = 0x0; + ADC_ADC_CFG_REG(base) = ADC_ADC_CFG_ADC_EN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetSampleRate + * Description : This function is used to set ADC module sample rate. + * + *END**************************************************************************/ +void ADC_SetSampleRate(ADC_Type* base, uint32_t sampleRate) +{ + uint8_t preDiv; + uint8_t coreTimerUnit; + + assert((sampleRate <= 1000000) && (sampleRate >= 1563)); + + for (preDiv = 0 ; preDiv < 6; preDiv++) + { + uint32_t divider = 24000000 >> (2 + preDiv); + divider /= sampleRate * 6; + if(divider <= 32) + { + coreTimerUnit = divider - 1; + break; + } + } + + if (0x6 == preDiv) + { + preDiv = 0x5; + coreTimerUnit = 0x1F; + } + + ADC_TIMER_UNIT_REG(base) = 0x0; + ADC_TIMER_UNIT_REG(base) = ADC_TIMER_UNIT_PRE_DIV(preDiv) | ADC_TIMER_UNIT_CORE_TIMER_UNIT(coreTimerUnit); +} + +/******************************************************************************* + * ADC Low power control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetClockDownCmd + * Description : This function is used to stop all digital part power. + * + *END**************************************************************************/ +void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown) +{ + if (clockDown) + ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_CLK_DOWN_MASK; + else + ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_CLK_DOWN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetPowerDownCmd + * Description : This function is used to power down ADC analogue core. + * Before entering into stop-mode, power down ADC analogue + * core first. + * + *END**************************************************************************/ +void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown) +{ + if (powerDown) + { + ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_PD_MASK; + /* Wait until power down action finish. */ + while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK)); + } + else + { + ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_PD_MASK; + } +} + +/******************************************************************************* + * ADC Convert Channel Initialization and Configuration functions. + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_LogicChInit + * Description : Initialize ADC Logic channel with initialization structure. + * + *END**************************************************************************/ +void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfig) +{ + assert(chInitConfig); + + /* Select input channel */ + ADC_SelectInputCh(base, logicCh, chInitConfig->inputChannel); + + /* Set Continuous Convert Rate. */ + if (chInitConfig->coutinuousEnable) + ADC_SetConvertRate(base, logicCh, chInitConfig->convertRate); + + /* Set Hardware average Number. */ + if (chInitConfig->averageEnable) + { + ADC_SetAverageNum(base, logicCh, chInitConfig->averageNumber); + ADC_SetAverageCmd(base, logicCh, true); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_LogicChDeinit + * Description : Reset target ADC logic channel registers to default value. + * + *END**************************************************************************/ +void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) = 0x0; + ADC_CH_A_CFG2_REG(base) = 0x8000; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) = 0x0; + ADC_CH_B_CFG2_REG(base) = 0x8000; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) = 0x0; + ADC_CH_C_CFG2_REG(base) = 0x8000; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) = 0x0; + ADC_CH_D_CFG2_REG(base) = 0x8000; + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) = 0x0; + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SelectInputCh + * Description : Select input channel for target logic channel. + * + *END**************************************************************************/ +void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SEL_MASK) | \ + ADC_CH_A_CFG1_CHA_SEL(inputCh); + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SEL_MASK) | \ + ADC_CH_B_CFG1_CHB_SEL(inputCh); + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SEL_MASK) | \ + ADC_CH_C_CFG1_CHC_SEL(inputCh); + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SEL_MASK) | \ + ADC_CH_D_CFG1_CHD_SEL(inputCh); + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_SEL_MASK) | \ + ADC_CH_SW_CFG_CH_SW_SEL(inputCh); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertRate + * Description : Set ADC conversion rate of target logic channel. + * + *END**************************************************************************/ +void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate) +{ + assert(logicCh <= adcLogicChD); + + /* Calculate ADC module's current sample rate */ + uint32_t sampleRate = (4000000 >> (2 + (ADC_TIMER_UNIT_REG(base) >> ADC_TIMER_UNIT_PRE_DIV_SHIFT))) / \ + ((ADC_TIMER_UNIT_REG(base) & ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK) + 1); + + uint32_t convertDiv = sampleRate / convertRate; + assert((sampleRate / convertRate) <= ADC_CH_A_CFG1_CHA_TIMER_MASK); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_TIMER_MASK) | \ + ADC_CH_A_CFG1_CHA_TIMER(convertDiv); + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_TIMER_MASK) | \ + ADC_CH_B_CFG1_CHB_TIMER(convertDiv); + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_TIMER_MASK) | \ + ADC_CH_C_CFG1_CHC_TIMER(convertDiv); + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_TIMER_MASK) | \ + ADC_CH_D_CFG1_CHD_TIMER(convertDiv); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAverageCmd + * Description : Set work state of hardware average feature of target + * logic channel. + * + *END**************************************************************************/ +void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable) +{ + assert(logicCh <= adcLogicChSW); + + if (enable) + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_AVG_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_AVG_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_AVG_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_AVG_EN_MASK; + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK; + break; + default: + break; + } + } + else + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_AVG_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_AVG_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_AVG_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_AVG_EN_MASK; + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) &= ~ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK; + break; + default: + break; + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAverageNum + * Description : Set hardware average number of target logic channel. + * + *END**************************************************************************/ +void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum) +{ + assert(logicCh <= adcLogicChSW); + assert(avgNum <= adcAvgNum32); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK) | \ + ADC_CH_A_CFG2_CHA_AVG_NUMBER(avgNum); + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK) | \ + ADC_CH_B_CFG2_CHB_AVG_NUMBER(avgNum); + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK) | \ + ADC_CH_C_CFG2_CHC_AVG_NUMBER(avgNum); + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK) | \ + ADC_CH_D_CFG2_CHD_AVG_NUMBER(avgNum); + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK) | \ + ADC_CH_SW_CFG_CH_SW_AVG_NUMBER(avgNum); + break; + default: + break; + } +} + +/******************************************************************************* + * ADC Conversion Control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertCmd + * Description : Set continuous convert work mode of target logic channel. + * + *END**************************************************************************/ +void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable) +{ + assert(logicCh <= adcLogicChD); + + if (enable) + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SINGLE_MASK) | + ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SINGLE_MASK) | + ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SINGLE_MASK) | + ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SINGLE_MASK) | + ADC_CH_D_CFG1_CHD_EN_MASK; + break; + default: + break; + } + } + else + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK; + break; + default: + break; + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_TriggerSingleConvert + * Description : Trigger single time convert on the target logic channel. + * + *END**************************************************************************/ +void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_SINGLE_MASK | ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_SINGLE_MASK | ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_SINGLE_MASK | ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_SINGLE_MASK | ADC_CH_D_CFG1_CHD_EN_MASK; + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_START_CONV_MASK; + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_StopConvert + * Description : Stop current convert on the target logic channel. + * + *END**************************************************************************/ +void ADC_StopConvert(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK; + break; + case adcLogicChSW: + /* Wait until ADC conversion finish. */ + while (ADC_CH_SW_CFG_REG(base) & ADC_CH_SW_CFG_START_CONV_MASK); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_GetConvertResult + * Description : Get 12-bit length right aligned convert result. + * + *END**************************************************************************/ +uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + return ADC_CHA_B_CNV_RSLT_REG(base) & ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK; + case adcLogicChB: + return ADC_CHA_B_CNV_RSLT_REG(base) >> ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT; + case adcLogicChC: + return ADC_CHC_D_CNV_RSLT_REG(base) & ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK; + case adcLogicChD: + return ADC_CHC_D_CNV_RSLT_REG(base) >> ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT; + case adcLogicChSW: + return ADC_CH_SW_CNV_RSLT_REG(base) & ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK; + default: + return 0; + } +} + +/******************************************************************************* + * ADC Comparer Control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCmpMode + * Description : Set the work mode of ADC module build-in comparer on target + * logic channel. + * + *END**************************************************************************/ +void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode) +{ + assert(logicCh <= adcLogicChD); + assert(cmpMode <= adcCmpModeOutOffInterval); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_CMP_MODE_MASK) | \ + ADC_CH_A_CFG2_CHA_CMP_MODE(cmpMode); + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_CMP_MODE_MASK) | \ + ADC_CH_B_CFG2_CHB_CMP_MODE(cmpMode); + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_CMP_MODE_MASK) | \ + ADC_CH_C_CFG2_CHC_CMP_MODE(cmpMode); + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_CMP_MODE_MASK) | \ + ADC_CH_D_CFG2_CHD_CMP_MODE(cmpMode); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCmpHighThres + * Description : Set ADC module build-in comparer high threshold on target + * logic channel. + * + *END**************************************************************************/ +void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold) +{ + assert(logicCh <= adcLogicChD); + assert(threshold <= 0xFFF); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK) | \ + ADC_CH_A_CFG2_CHA_HIGH_THRES(threshold); + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK) | \ + ADC_CH_B_CFG2_CHB_HIGH_THRES(threshold); + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK) | \ + ADC_CH_C_CFG2_CHC_HIGH_THRES(threshold); + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK) | \ + ADC_CH_D_CFG2_CHD_HIGH_THRES(threshold); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCmpLowThres + * Description : Set ADC module build-in comparer low threshold on target + * logic channel. + * + *END**************************************************************************/ +void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold) +{ + assert(logicCh <= adcLogicChD); + assert(threshold <= 0xFFF); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_LOW_THRES_MASK) | \ + ADC_CH_A_CFG2_CHA_LOW_THRES(threshold); + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_LOW_THRES_MASK) | \ + ADC_CH_B_CFG2_CHB_LOW_THRES(threshold); + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_LOW_THRES_MASK) | \ + ADC_CH_B_CFG2_CHB_LOW_THRES(threshold); + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_LOW_THRES_MASK) | \ + ADC_CH_D_CFG2_CHD_LOW_THRES(threshold); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAutoDisableCmd + * Description : Set the working mode of ADC module auto disable feature on + * target logic channel. + * + *END**************************************************************************/ +void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable) +{ + assert(logicCh <= adcLogicChD); + + if (enable) + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) |= ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) |= ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) |= ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) |= ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; + break; + default: + break; + } + } + else + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) &= ~ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) &= ~ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) &= ~ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) &= ~ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; + break; + default: + break; + } + } +} + +/******************************************************************************* + * Interrupt and Flag control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetIntCmd + * Description : Enables or disables ADC interrupt requests. + * + *END**************************************************************************/ +void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable) +{ + if (enable) + ADC_INT_EN_REG(base) |= intSource; + else + ADC_INT_EN_REG(base) &= ~intSource; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetIntSigCmd + * Description : Enables or disables ADC interrupt flag when interrupt + * condition met. + * + *END**************************************************************************/ +void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable) +{ + if (enable) + ADC_INT_SIG_EN_REG(base) |= intSignal; + else + ADC_INT_SIG_EN_REG(base) &= ~intSignal; +} + +/******************************************************************************* + * DMA & FIFO control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetDmaReset + * Description : Set the reset state of ADC internal DMA part. + * + *END**************************************************************************/ +void ADC_SetDmaReset(ADC_Type* base, bool active) +{ + if (active) + ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_RST_MASK; + else + ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_RST_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetDmaCmd + * Description : Set the work mode of ADC DMA part. + * + *END**************************************************************************/ +void ADC_SetDmaCmd(ADC_Type* base, bool enable) +{ + if (enable) + ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_EN_MASK; + else + ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_EN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetDmaFifoCmd + * Description : Set the work mode of ADC DMA FIFO part. + * + *END**************************************************************************/ +void ADC_SetDmaFifoCmd(ADC_Type* base, bool enable) +{ + if (enable) + ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_FIFO_EN_MASK; + else + ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_FIFO_EN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/adc_imx7d.h b/zephyr/imx/drivers/adc_imx7d.h new file mode 100644 index 000000000..57882597e --- /dev/null +++ b/zephyr/imx/drivers/adc_imx7d.h @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ADC_IMX7D_H__ +#define __ADC_IMX7D_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup adc_imx7d_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief ADC module initialization structure. */ +typedef struct _adc_init_config +{ + uint32_t sampleRate; /*!< The desired ADC sample rate.*/ + bool levelShifterEnable; /*!< The level shifter module configuration(Enable to power on ADC module).*/ +} adc_init_config_t; + +/*! @brief ADC logic channel initialization structure. */ +typedef struct _adc_logic_ch_init_config +{ + uint32_t convertRate; /*!< The continuous rate when continuous sample enabled.*/ + uint8_t inputChannel; /*!< The logic channel to be set.*/ + uint8_t averageNumber; /*!< The average number for hardware average function.*/ + bool coutinuousEnable; /*!< Continuous sample mode enable configuration.*/ + bool averageEnable; /*!< Hardware average enable configuration.*/ +} adc_logic_ch_init_config_t; + +/*! @brief ADC logic channel selection enumeration. */ +enum _adc_logic_ch_selection +{ + adcLogicChA = 0x0, /*!< ADC Logic Channel A.*/ + adcLogicChB = 0x1, /*!< ADC Logic Channel B.*/ + adcLogicChC = 0x2, /*!< ADC Logic Channel C.*/ + adcLogicChD = 0x3, /*!< ADC Logic Channel D.*/ + adcLogicChSW = 0x4, /*!< ADC Logic Channel Software.*/ +}; + +/*! @brief ADC hardware average number enumeration. */ +enum _adc_average_number +{ + adcAvgNum4 = 0x0, /*!< ADC Hardware Average Number is set to 4.*/ + adcAvgNum8 = 0x1, /*!< ADC Hardware Average Number is set to 8.*/ + adcAvgNum16 = 0x2, /*!< ADC Hardware Average Number is set to 16.*/ + adcAvgNum32 = 0x3, /*!< ADC Hardware Average Number is set to 32.*/ +}; + +/*! @brief ADC build-in comparer work mode configuration enumeration. */ +enum _adc_compare_mode +{ + adcCmpModeDisable = 0x0, /*!< ADC build-in comparator is disabled.*/ + adcCmpModeGreaterThanLow = 0x1, /*!< ADC build-in comparator is triggered when sample value greater than low threshold.*/ + adcCmpModeLessThanLow = 0x2, /*!< ADC build-in comparator is triggered when sample value less than low threshold.*/ + adcCmpModeInInterval = 0x3, /*!< ADC build-in comparator is triggered when sample value in interval between low and high threshold.*/ + adcCmpModeGreaterThanHigh = 0x5, /*!< ADC build-in comparator is triggered when sample value greater than high threshold.*/ + adcCmpModeLessThanHigh = 0x6, /*!< ADC build-in comparator is triggered when sample value less than high threshold.*/ + adcCmpModeOutOffInterval = 0x7, /*!< ADC build-in comparator is triggered when sample value out of interval between low and high threshold.*/ +}; + +/*! @brief This enumeration contains the settings for all of the ADC interrupt configurations. */ +enum _adc_interrupt +{ + adcIntLastFifoDataRead = ADC_INT_EN_LAST_FIFO_DATA_READ_EN_MASK, /*!< Last FIFO Data Read Interrupt Enable.*/ + adcIntConvertTimeoutChSw = ADC_INT_EN_SW_CH_COV_TO_INT_EN_MASK, /*!< Software Channel Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChD = ADC_INT_EN_CHD_COV_TO_INT_EN_MASK, /*!< Channel D Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChC = ADC_INT_EN_CHC_COV_TO_INT_EN_MASK, /*!< Channel C Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChB = ADC_INT_EN_CHB_COV_TO_INT_EN_MASK, /*!< Channel B Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChA = ADC_INT_EN_CHA_COV_TO_INT_EN_MASK, /*!< Channel A Conversion Time Out Interrupt Enable.*/ + adcIntConvertChSw = ADC_INT_EN_SW_CH_COV_INT_EN_MASK, /*!< Software Channel Conversion Interrupt Enable.*/ + adcIntConvertChD = ADC_INT_EN_CHD_COV_INT_EN_MASK, /*!< Channel D Conversion Interrupt Enable.*/ + adcIntConvertChC = ADC_INT_EN_CHC_COV_INT_EN_MASK, /*!< Channel C Conversion Interrupt Enable.*/ + adcIntConvertChB = ADC_INT_EN_CHB_COV_INT_EN_MASK, /*!< Channel B Conversion Interrupt Enable.*/ + adcIntConvertChA = ADC_INT_EN_CHA_COV_INT_EN_MASK, /*!< Channel A Conversion Interrupt Enable.*/ + adcIntFifoOverrun = ADC_INT_EN_FIFO_OVERRUN_INT_EN_MASK, /*!< FIFO overrun Interrupt Enable.*/ + adcIntFifoUnderrun = ADC_INT_EN_FIFO_UNDERRUN_INT_EN_MASK, /*!< FIFO underrun Interrupt Enable.*/ + adcIntDmaReachWatermark = ADC_INT_EN_DMA_REACH_WM_INT_EN_MASK, /*!< DMA Reach Watermark Level Interrupt Enable.*/ + adcIntCmpChD = ADC_INT_EN_CHD_CMP_INT_EN_MASK, /*!< Channel D Compare Interrupt Enable.*/ + adcIntCmpChC = ADC_INT_EN_CHC_CMP_INT_EN_MASK, /*!< Channel C Compare Interrupt Enable.*/ + adcIntCmpChB = ADC_INT_EN_CHB_CMP_INT_EN_MASK, /*!< Channel B Compare Interrupt Enable.*/ + adcIntCmpChA = ADC_INT_EN_CHA_CMP_INT_EN_MASK, /*!< Channel A Compare Interrupt Enable.*/ +}; + +/*! @brief Flag for ADC interrupt/DMA status check or polling status. */ +enum _adc_status_flag +{ + adcStatusLastFifoDataRead = ADC_INT_STATUS_LAST_FIFO_DATA_READ_MASK, /*!< Last FIFO Data Read status flag.*/ + adcStatusConvertTimeoutChSw = ADC_INT_STATUS_SW_CH_COV_TO_MASK, /*!< Software Channel Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChD = ADC_INT_STATUS_CHD_COV_TO_MASK, /*!< Channel D Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChC = ADC_INT_STATUS_CHC_COV_TO_MASK, /*!< Channel C Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChB = ADC_INT_STATUS_CHB_COV_TO_MASK, /*!< Channel B Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChA = ADC_INT_STATUS_CHA_COV_TO_MASK, /*!< Channel A Conversion Time Out status flag.*/ + adcStatusConvertChSw = ADC_INT_STATUS_SW_CH_COV_MASK, /*!< Software Channel Conversion status flag.*/ + adcStatusConvertChD = ADC_INT_STATUS_CHD_COV_MASK, /*!< Channel D Conversion status flag.*/ + adcStatusConvertChC = ADC_INT_STATUS_CHC_COV_MASK, /*!< Channel C Conversion status flag.*/ + adcStatusConvertChB = ADC_INT_STATUS_CHB_COV_MASK, /*!< Channel B Conversion status flag.*/ + adcStatusConvertChA = ADC_INT_STATUS_CHA_COV_MASK, /*!< Channel A Conversion status flag.*/ + adcStatusFifoOverrun = ADC_INT_STATUS_FIFO_OVERRUN_MASK, /*!< FIFO Overrun status flag.*/ + adcStatusFifoUnderrun = ADC_INT_STATUS_FIFO_UNDERRUN_MASK, /*!< FIFO Underrun status flag.*/ + adcStatusDmaReachWatermark = ADC_INT_STATUS_DMA_REACH_WM_MASK, /*!< DMA Reach Watermark Level status flag.*/ + adcStatusCmpChD = ADC_INT_STATUS_CHD_CMP_MASK, /*!< Channel D Compare status flag.*/ + adcStatusCmpChC = ADC_INT_STATUS_CHC_CMP_MASK, /*!< Channel C Compare status flag.*/ + adcStatusCmpChB = ADC_INT_STATUS_CHB_CMP_MASK, /*!< Channel B Compare status flag.*/ + adcStatusCmpChA = ADC_INT_STATUS_CHA_CMP_MASK, /*!< Channel A Compare status flag.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name ADC Module Initialization and Configuration functions. + * @{ + */ + +/*! + * @brief Initialize ADC to reset state and initialize with initialization structure. + * + * @param base ADC base pointer. + * @param initConfig ADC initialization structure. + */ +void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig); + +/*! + * @brief This function reset ADC module register content to its default value. + * + * @param base ADC base pointer. + */ +void ADC_Deinit(ADC_Type* base); + +/*! + * @brief This function Enable ADC module build-in Level Shifter. + * For i.MX 7Dual, Level Shifter should always be enabled. + * User can disable Level Shifter to save power. + * + * @param base ADC base pointer. + */ +static inline void ADC_LevelShifterEnable(ADC_Type* base) +{ + ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_EN_MASK; +} + +/*! + * @brief This function Disable ADC module build-in Level Shifter + * to save power. + * + * @param base ADC base pointer. + */ +static inline void ADC_LevelShifterDisable(ADC_Type* base) +{ + ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_EN_MASK; +} + +/*! + * @brief This function is used to set ADC module sample rate. + * + * @param base ADC base pointer. + * @param sampleRate Desired ADC sample rate. + */ +void ADC_SetSampleRate(ADC_Type* base, uint32_t sampleRate); + +/*@}*/ + +/*! + * @name ADC Low power control functions. + * @{ + */ + +/*! + * @brief This function is used to stop all digital part power. + * + * @param base ADC base pointer. + * @param clockDown Stop all ADC digital part or not. + * - true: Clock down. + * - false: Clock running. + */ +void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown); + +/*! + * @brief This function is used to power down ADC analogue core. + * Before entering into stop-mode, power down ADC analogue core first. + * @param base ADC base pointer. + * @param powerDown Power down ADC analogue core or not. + * - true: Power down the ADC analogue core. + * - false: Do not power down the ADC analogue core. + */ +void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown); + +/*@}*/ + +/*! + * @name ADC Convert Channel Initialization and Configuration functions. + * @{ + */ + +/*! + * @brief Initialize ADC Logic channel with initialization structure. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param chInitConfig ADC logic channel initialization structure. + */ +void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfig); + +/*! + * @brief Reset target ADC logic channel registers to default value. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh); + +/*! + * @brief Select input channel for target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param inputCh Input channel selection for target logic channel(vary from 0 to 15). + */ +void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh); + +/*! + * @brief Set ADC conversion rate of target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param convertRate ADC conversion rate in Hz. + */ +void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate); + +/*! + * @brief Set work state of hardware average feature of target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable hardware average + * - true: Enable hardware average of given logic channel. + * - false: Disable hardware average of given logic channel. + */ +void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable); + +/*! + * @brief Set hardware average number of target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param avgNum hardware average number(should select from @ref _adc_average_number enumeration). + */ +void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum); + +/*@}*/ + +/*! + * @name ADC Conversion Control functions. + * @{ + */ + +/*! + * @brief Set continuous convert work mode of target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable continuous convertion. + * - true: Enable continuous convertion. + * - false: Disable continuous convertion. + */ +void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable); + +/*! + * @brief Trigger single time convert on target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh); + +/*! + * @brief Stop current convert on target logic channel. + * For logic channel A ~ D, current conversion stops immediately. + * For Software channel, this function is waited until current conversion is finished. + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +void ADC_StopConvert(ADC_Type* base, uint8_t logicCh); + +/*! + * @brief Get 12-bit length right aligned convert result. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @return convert result on target logic channel. + */ +uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh); + +/*@}*/ + +/*! + * @name ADC Comparer Control functions. + * @{ + */ + +/*! + * @brief Set the work mode of ADC module build-in comparer on target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param cmpMode Comparer work mode selected from @ref _adc_compare_mode enumeration. + */ +void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode); + +/*! + * @brief Set ADC module build-in comparer high threshold on target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param threshold Comparer threshold in 12-bit unsigned int formate. + */ +void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold); + +/*! + * @brief Set ADC module build-in comparer low threshold on target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param threshold Comparer threshold in 12-bit unsigned int formate. + */ +void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold); + +/*! + * @brief Set the working mode of ADC module auto disable feature on target logic channel. + * This feature can disable continuous conversion when CMP condition matched. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable Auto Disable feature. + * - true: Enable Auto Disable feature. + * - false: Disable Auto Disable feature. + */ +void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable); + +/*@}*/ + +/*! + * @name Interrupt and Flag control functions. + * @{ + */ + +/*! + * @brief Enables or disables ADC interrupt requests. + * + * @param base ADC base pointer. + * @param intSource ADC interrupt sources to configuration. + * @param enable Enable/Disable given ADC interrupt. + * - true: Enable given ADC interrupt. + * - false: Disable given ADC interrupt. + */ +void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable); + +/*! + * @brief Enables or disables ADC interrupt flag when interrupt condition met. + * + * @param base ADC base pointer. + * @param intSignal ADC interrupt signals to configuration (see @ref _adc_interrupt enumeration). + * @param enable Enable/Disable given ADC interrupt flags. + * - true: Enable given ADC interrupt flags. + * - false: Disable given ADC interrupt flags. + */ +void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable); + +/*! + * @brief Gets the ADC status flag state. + * + * @param base ADC base pointer. + * @param flags ADC status flag mask defined in @ref _adc_status_flag enumeration. + * @return ADC status, each bit represents one status flag + */ +static inline uint32_t ADC_GetStatusFlag(ADC_Type* base, uint32_t flags) +{ + return (ADC_INT_STATUS_REG(base) & flags); +} + +/*! + * @brief Clear one or more ADC status flag state. + * + * @param base ADC base pointer. + * @param flags ADC status flag mask defined in @ref _adc_status_flag enumeration. + */ +static inline void ADC_ClearStatusFlag(ADC_Type* base, uint32_t flags) +{ + ADC_INT_STATUS_REG(base) &= ~flags; +} + +/*@}*/ + +/*! + * @name DMA & FIFO control functions. + * @{ + */ + +/*! + * @brief Set the reset state of ADC internal DMA part. + * + * @param base ADC base pointer. + * @param active Reset DMA & DMA FIFO or not. + * - true: Reset the DMA and DMA FIFO return to its reset value. + * - false: Do not reset DMA and DMA FIFO. + */ +void ADC_SetDmaReset(ADC_Type* base, bool active); + +/*! + * @brief Set the work mode of ADC DMA part. + * + * @param base ADC base pointer. + * @param enable Enable/Disable ADC DMA part. + * - true: Enable DMA, the data in DMA FIFO should move by SDMA. + * - false: Disable DMA, the data in DMA FIFO can only move by CPU. + */ +void ADC_SetDmaCmd(ADC_Type* base, bool enable); + +/*! + * @brief Set the work mode of ADC DMA FIFO part. + * + * @param base ADC base pointer. + * @param enable Enable/Disable DMA FIFO. + * - true: Enable DMA FIFO. + * - false: Disable DMA FIFO. + */ +void ADC_SetDmaFifoCmd(ADC_Type* base, bool enable); + +/*! + * @brief Select the logic channel that uses the DMA transfer. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +static inline void ADC_SetDmaCh(ADC_Type* base, uint32_t logicCh) +{ + assert(logicCh <= adcLogicChD); + ADC_DMA_FIFO_REG(base) = (ADC_DMA_FIFO_REG(base) & ~ADC_DMA_FIFO_DMA_CH_SEL_MASK) | \ + ADC_DMA_FIFO_DMA_CH_SEL(logicCh); +} + +/*! + * @brief Set the DMA request trigger watermark. + * + * @param base ADC base pointer. + * @param watermark DMA request trigger watermark. + */ +static inline void ADC_SetDmaWatermark(ADC_Type* base, uint32_t watermark) +{ + assert(watermark <= 0x1FF); + ADC_DMA_FIFO_REG(base) = (ADC_DMA_FIFO_REG(base) & ~ADC_DMA_FIFO_DMA_WM_LVL_MASK) | \ + ADC_DMA_FIFO_DMA_WM_LVL(watermark); +} + +/*! + * @brief Get the convert result from DMA FIFO. + * Data position: + * DMA_FIFO_DATA1(27~16bits) + * DMA_FIFO_DATA0(11~0bits) + * + * @param base ADC base pointer. + * @return Get 2 ADC transfer result from DMA FIFO. + */ +static inline uint32_t ADC_GetFifoData(ADC_Type* base) +{ + return ADC_DMA_FIFO_DAT_REG(base); +} + +/*! + * @brief Get the DMA FIFO full status + * + * @param base ADC base pointer. + * @retval true: DMA FIFO full. + * @retval false: DMA FIFO not full. + */ +static inline bool ADC_IsFifoFull(ADC_Type* base) +{ + return (bool)(ADC_FIFO_STATUS_REG(base) & ADC_FIFO_STATUS_FIFO_FULL_MASK); +} + +/*! + * @brief Get the DMA FIFO empty status + * + * @param base ADC base pointer. + * @retval true: DMA FIFO is empty. + * @retval false: DMA FIFO is not empty. + */ +static inline bool ADC_IsFifoEmpty(ADC_Type* base) +{ + return (bool)(ADC_FIFO_STATUS_REG(base) & ADC_FIFO_STATUS_FIFO_EMPTY_MASK); +} + +/*! + * @brief Get the entries number in DMA FIFO. + * + * @param base ADC base pointer. + * @return The numbers of data in DMA FIFO. + */ +static inline uint8_t ADC_GetFifoEntries(ADC_Type* base) +{ + return ADC_FIFO_STATUS_REG(base) & ADC_FIFO_STATUS_FIFO_ENTRIES_MASK; +} + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __ADC_IMX7D_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ccm_analog_imx6sx.c b/zephyr/imx/drivers/ccm_analog_imx6sx.c new file mode 100644 index 000000000..c0b417560 --- /dev/null +++ b/zephyr/imx/drivers/ccm_analog_imx6sx.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ccm_analog_imx6sx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_PowerUpPll + * Description : Power up PLL. + * + *END**************************************************************************/ +void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + /* Judge PLL_USB1 and PLL_USB2 according to register offset value. + Because the definition of power control bit is different from the other PLL.*/ + if((CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x10) || (CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x20)) + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); + else + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_PowerDownPll + * Description : Power down PLL. + * + *END**************************************************************************/ +void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + /* Judge PLL_USB1 and PLL_USB2 according to register offset value. + Because the definition of power control bit is different from the other PLL.*/ + if((CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x10) || (CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x20)) + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); + else + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_SetPllBypass + * Description : PLL bypass setting. + * + *END**************************************************************************/ +void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass) +{ + if(bypass) + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK; + else + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetPllFreq + * Description : Get PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetPllFreq(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + uint8_t divSelect; + float numerator, denomitor; + uint32_t hz = 0; + + if (CCM_ANALOG_IsPllBypassed(base, pllControl)) + return 24000000; + + switch(CCM_ANALOG_TUPLE_OFFSET(pllControl)) + { + /* Get PLL_ARM frequency. */ + case 0x0: + { + divSelect = CCM_ANALOG_PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK; + hz = 24000000 * divSelect / 2; + break; + } + /* Get PLL_USB1(PLL3) frequency. */ + case 0x10: + { + divSelect = CCM_ANALOG_PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK; + if(divSelect == 0) + hz = 480000000; + else if(divSelect == 1) + hz = 528000000; + break; + } + /* Get PLL_USB2 frequency. */ + case 0x20: + { + divSelect = CCM_ANALOG_PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK; + if(divSelect == 0) + hz = 480000000; + else if(divSelect == 1) + hz = 528000000; + break; + } + /* Get PLL_SYS(PLL2) frequency. */ + case 0x30: + { + divSelect = CCM_ANALOG_PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK; + if(divSelect == 0) + hz = 480000000; + else + hz = 528000000; + break; + } + /* Get PLL_AUDIO frequency. */ + case 0x70: + { + divSelect = CCM_ANALOG_PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK; + numerator = CCM_ANALOG_PLL_AUDIO_NUM & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK; + denomitor = CCM_ANALOG_PLL_AUDIO_DENOM & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK; + hz = (uint32_t)(24000000 * (divSelect + (numerator / denomitor))); + break; + } + /* Get PLL_VIDEO frequency. */ + case 0xA0: + { + divSelect = CCM_ANALOG_PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK; + numerator = CCM_ANALOG_PLL_VIDEO_NUM & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK; + denomitor = CCM_ANALOG_PLL_VIDEO_DENOM & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK; + hz = (uint32_t)(24000000 * (divSelect + (numerator / denomitor))); + break; + } + } + return hz; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetPfdFreq + * Description : Get PFD frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac) +{ + uint32_t main, frac; + + /* Judge whether pfdFrac is PLL2 PFD or not. */ + if(CCM_ANALOG_TUPLE_OFFSET(pfdFrac) == 0x100) + { + /* PFD should work with PLL2 without bypass */ + assert(!CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllSysControl)); + main = CCM_ANALOG_GetPllFreq(base, ccmAnalogPllSysControl); + } + else if(CCM_ANALOG_TUPLE_OFFSET(pfdFrac) == 0xF0) + { + /* PFD should work with PLL3 without bypass */ + assert(!CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllUsb1Control)); + main = CCM_ANALOG_GetPllFreq(base, ccmAnalogPllUsb1Control); + } + else + main = 0; + + frac = CCM_ANALOG_GetPfdFrac(base, pfdFrac); + + return main / frac * 18; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ccm_analog_imx6sx.h b/zephyr/imx/drivers/ccm_analog_imx6sx.h new file mode 100644 index 000000000..fdec7e08f --- /dev/null +++ b/zephyr/imx/drivers/ccm_analog_imx6sx.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCM_ANALOG_IMX6SX_H__ +#define __CCM_ANALOG_IMX6SX_H__ + +#include +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ccm_analog_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_ANALOG_TUPLE(reg, shift) ((offsetof(CCM_ANALOG_Type, reg) & 0xFFFF) | ((shift) << 16)) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFFFF) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0) +#define CCM_ANALOG_TUPLE_REG_SET(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 4) +#define CCM_ANALOG_TUPLE_REG_CLR(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 8) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((tuple) >> 16) & 0x1F) +#define CCM_ANALOG_TUPLE_OFFSET(tuple) ((tuple) & 0xFFFF) + +/*! + * @brief PLL control names for PLL power/bypass/lock/frequency operations. + * + * These constants define the PLL control names for PLL power/bypass/lock operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Powerdown/Power bit shift. + */ +enum _ccm_analog_pll_control +{ + ccmAnalogPllArmControl = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT), /*!< CCM Analog ARM PLL Control.*/ + ccmAnalogPllUsb1Control = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_POWER_SHIFT), /*!< CCM Analog USB1 PLL Control.*/ + ccmAnalogPllUsb2Control = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_POWER_SHIFT), /*!< CCM Analog USB2 PLL Control.*/ + ccmAnalogPllSysControl = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT), /*!< CCM Analog SYSTEM PLL Control.*/ + ccmAnalogPllAudioControl = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT), /*!< CCM Analog AUDIO PLL Control.*/ + ccmAnalogPllVideoControl = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT), /*!< CCM Analog VIDEO PLL Control.*/ + ccmAnalogPllEnetControl = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT), /*!< CCM Analog ETHERNET PLL Control.*/ +}; + +/*! + * @brief PLL clock names for clock enable/disable settings. + * + * These constants define the PLL clock names for PLL clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock enable bit shift. + */ +enum _ccm_analog_pll_clock +{ + ccmAnalogPllArmClock = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< CCM Analog ARM PLL Clock.*/ + ccmAnalogPllUsb1Clock = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< CCM Analog USB1 PLL Clock.*/ + ccmAnalogPllUsb2Clock = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< CCM Analog USB2 PLL Clock.*/ + ccmAnalogPllSysClock = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< CCM Analog SYSTEM PLL Clock.*/ + ccmAnalogPllAudioClock = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< CCM Analog AUDIO PLL Clock.*/ + ccmAnalogPllVideoClock = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< CCM Analog VIDEO PLL Clock.*/ + ccmAnalogPllEnetClock25Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< CCM Analog ETHERNET 25MHz PLL Clock.*/ + ccmAnalogPllEnet2Clock125Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT), /*!< CCM Analog ETHERNET2 125MHz PLL Clock.*/ + ccmAnalogPllEnet1Clock125Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT), /*!< CCM Analog ETHERNET1 125MHz PLL Clock.*/ +}; + +/*! + * @brief PFD gate names for clock gate settings, clock source is PLL2 and PLL3 + * + * These constants define the PFD gate names for PFD clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock gate bit shift. + */ +enum _ccm_analog_pfd_clkgate +{ + ccmAnalogPll2Pfd0ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD0 Clock Gate.*/ + ccmAnalogPll2Pfd1ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD1 Clock Gate.*/ + ccmAnalogPll2Pfd2ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD2 Clock Gate.*/ + ccmAnalogPll2Pfd3ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD3 Clock Gate.*/ + ccmAnalogPll3Pfd0ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD0 Clock Gate.*/ + ccmAnalogPll3Pfd1ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD1 Clock Gate.*/ + ccmAnalogPll3Pfd2ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD2 Clock Gate.*/ + ccmAnalogPll3Pfd3ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD3 Clock Gate.*/ +}; + +/*! + * @brief PFD fraction names for clock fractional divider operations. + * + * These constants define the PFD fraction names for PFD fractional divider operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Fraction bits shift + */ +enum _ccm_analog_pfd_frac +{ + ccmAnalogPll2Pfd0Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD0 fractional divider.*/ + ccmAnalogPll2Pfd1Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD1 fractional divider.*/ + ccmAnalogPll2Pfd2Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD2 fractional divider.*/ + ccmAnalogPll2Pfd3Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD3 fractional divider.*/ + ccmAnalogPll3Pfd0Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD0 fractional divider.*/ + ccmAnalogPll3Pfd1Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD1 fractional divider.*/ + ccmAnalogPll3Pfd2Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD2 fractional divider.*/ + ccmAnalogPll3Pfd3Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD3 fractional divider.*/ +}; + +/*! + * @brief PFD stable names for clock stable query + * + * These constants define the PFD stable names for clock stable query.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Stable bit shift. + */ +enum _ccm_analog_pfd_stable +{ + ccmAnalogPll2Pfd0Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD0 clock stable query.*/ + ccmAnalogPll2Pfd1Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD1 clock stable query.*/ + ccmAnalogPll2Pfd2Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD2 clock stable query.*/ + ccmAnalogPll2Pfd3Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD3 clock stable query.*/ + ccmAnalogPll3Pfd0Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD0 clock stable query.*/ + ccmAnalogPll3Pfd1Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD1 clock stable query.*/ + ccmAnalogPll3Pfd2Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD2 clock stable query.*/ + ccmAnalogPll3Pfd3Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD3 clock stable query.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Analog PLL Operation Functions + * @{ + */ + +/*! + * @brief Power up PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + */ +void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl); + +/*! + * @brief Power down PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + */ +void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl); + +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false: Do not bypass the PLL. + */ +void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass); + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CCM_ANALOG_IsPllBypassed(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_BYPASS_MASK); +} + +/*! + * @brief Check if PLL clock is locked + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL lock status. + * - true: The PLL is locked. + * - false: The PLL is not locked. + */ +static inline bool CCM_ANALOG_IsPllLocked(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_LOCK_MASK); +} + +/*! + * @brief Enable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) + */ +static inline void CCM_ANALOG_EnablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Disable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) + */ +static inline void CCM_ANALOG_DisablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Get PLL(involved all PLLs) clock frequency. + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL clock frequency in HZ. + */ +uint32_t CCM_ANALOG_GetPllFreq(CCM_ANALOG_Type * base, uint32_t pllControl); + +/*@}*/ + +/*! + * @name CCM Analog PFD Operation Functions + * @{ + */ + +/*! + * @brief Enable PFD clock + * + * @param base CCM_ANALOG base pointer. + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) + */ +static inline void CCM_ANALOG_EnablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate); +} + +/*! + * @brief Disable PFD clock + * + * @param base CCM_ANALOG base pointer. + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) + */ +static inline void CCM_ANALOG_DisablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate); +} + +/*! + * @brief Check if PFD clock is stable + * + * @param base CCM_ANALOG base pointer. + * @param pfdStable PFD stable identifier (see @ref _ccm_analog_pfd_stable enumeration) + * @return PFD clock stable status. + * - true: The PFD clock is stable. + * - false: The PFD clock is not stable. + */ +static inline bool CCM_ANALOG_IsPfdStable(CCM_ANALOG_Type * base, uint32_t pfdStable) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pfdStable) & (1 << CCM_ANALOG_TUPLE_SHIFT(pfdStable))); +} + + +/*! + * @brief Set PFD clock fraction + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @param value PFD clock fraction value + */ +static inline void CCM_ANALOG_SetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac, uint32_t value) +{ + assert(value >= 12 && value <= 35); + CCM_ANALOG_TUPLE_REG_CLR(base, pfdFrac) = CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK << CCM_ANALOG_TUPLE_SHIFT(pfdFrac); + CCM_ANALOG_TUPLE_REG_SET(base, pfdFrac) = value << CCM_ANALOG_TUPLE_SHIFT(pfdFrac); +} + +/*! + * @brief Get PFD clock fraction + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @return PFD clock fraction value + */ +static inline uint32_t CCM_ANALOG_GetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac) +{ + return (CCM_ANALOG_TUPLE_REG(base, pfdFrac) >> CCM_ANALOG_TUPLE_SHIFT(pfdFrac)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK; +} + +/*! + * @brief Get PFD clock frequency + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @return PFD clock frequency in HZ + */ +uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CCM_ANALOG_IMX6SX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ccm_analog_imx7d.c b/zephyr/imx/drivers/ccm_analog_imx7d.c new file mode 100644 index 000000000..6713eefed --- /dev/null +++ b/zephyr/imx/drivers/ccm_analog_imx7d.c @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ccm_analog_imx7d.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetArmPllFreq + * Description : Get ARM PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetArmPllFreq(CCM_ANALOG_Type * base) +{ + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllArmControl)) + return 24000000ul; + + return 12000000ul * (CCM_ANALOG_PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetSysPllFreq + * Description : Get system PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetSysPllFreq(CCM_ANALOG_Type * base) +{ + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPll480Control)) + return 24000000ul; + + if (CCM_ANALOG_PLL_480 & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) + return 528000000ul; + else + return 480000000ul; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetDdrPllFreq + * Description : Get DDR PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetDdrPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllDdrControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG) & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK; + divTestSelect = (CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG) & CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT; + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_DDR_SS_REG(base) & CCM_ANALOG_PLL_DDR_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_DDR_SS_REG(base) & CCM_ANALOG_PLL_DDR_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_DDR_DENOM_REG(base) & CCM_ANALOG_PLL_DDR_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_DDR_NUM_REG(base) & CCM_ANALOG_PLL_DDR_NUM_A_MASK)); + return (uint32_t)((24000000ul >> divTestSelect) * (divSelect + factor)); + } + else + { + return (24000000ul >> divTestSelect) * divSelect; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetEnetPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetEnetPllFreq(CCM_ANALOG_Type * base) +{ + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllEnetControl)) + return 24000000ul; + + return 1000000000ul; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetAudioPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetAudioPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divPostSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllAudioControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK; + divPostSelect = (CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) >> + CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT; + divTestSelect = (CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT; + + switch (divPostSelect) + { + case 0x0: + case 0x2: + divPostSelect = 0; + break; + case 0x1: + divPostSelect = 1; + break; + case 0x3: + divPostSelect = 2; + break; + } + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_AUDIO_SS_REG(base) & CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_AUDIO_SS_REG(base) & CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_AUDIO_NUM_REG(base) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)); + return (uint32_t)(((24000000ul >> divTestSelect) >> divPostSelect) * (divSelect + factor)); + } + else + { + return ((24000000ul >> divTestSelect) >> divPostSelect) * divSelect; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetVideoPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetVideoPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divPostSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllVideoControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK; + divPostSelect = (CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) >> + CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT; + divTestSelect = (CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT; + + switch (divPostSelect) + { + case 0x0: + case 0x2: + divPostSelect = 0; + break; + case 0x1: + divPostSelect = 1; + break; + case 0x3: + divPostSelect = 2; + break; + } + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_VIDEO_SS_REG(base) & CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_VIDEO_SS_REG(base) & CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_VIDEO_NUM_REG(base) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)); + return (uint32_t)(((24000000ul >> divTestSelect) >> divPostSelect) * (divSelect + factor)); + } + else + { + return ((24000000ul >> divTestSelect) >> divPostSelect) * divSelect; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetPfdFreq + * Description : Get PFD frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac) +{ + uint32_t main, frac; + + /* PFD should work with system PLL without bypass */ + assert(!CCM_ANALOG_IsPllBypassed(base, ccmAnalogPll480Control)); + + main = CCM_ANALOG_GetSysPllFreq(base); + frac = CCM_ANALOG_GetPfdFrac(base, pfdFrac); + + return main / frac * 18; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ccm_analog_imx7d.h b/zephyr/imx/drivers/ccm_analog_imx7d.h new file mode 100644 index 000000000..1af5baae5 --- /dev/null +++ b/zephyr/imx/drivers/ccm_analog_imx7d.h @@ -0,0 +1,398 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCM_ANALOG_IMX7D_H__ +#define __CCM_ANALOG_IMX7D_H__ + +#include +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ccm_analog_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_ANALOG_TUPLE(reg, shift) ((offsetof(CCM_ANALOG_Type, reg) & 0xFFFF) | ((shift) << 16)) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFFFF) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0) +#define CCM_ANALOG_TUPLE_REG_SET(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 4) +#define CCM_ANALOG_TUPLE_REG_CLR(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 8) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((tuple) >> 16) & 0x1F) + +/*! + * @brief PLL control names for PLL power/bypass/lock operations. + * + * These constants define the PLL control names for PLL power/bypass/lock operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Power down bit shift. + */ +enum _ccm_analog_pll_control +{ + ccmAnalogPllArmControl = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT), /*!< CCM Analog ARM PLL Control.*/ + ccmAnalogPllDdrControl = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT), /*!< CCM Analog DDR PLL Control.*/ + ccmAnalogPll480Control = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_POWERDOWN_SHIFT), /*!< CCM Analog 480M PLL Control.*/ + ccmAnalogPllEnetControl = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT), /*!< CCM Analog Ethernet PLL Control.*/ + ccmAnalogPllAudioControl = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT), /*!< CCM Analog AUDIO PLL Control.*/ + ccmAnalogPllVideoControl = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT), /*!< CCM Analog VIDEO PLL Control.*/ +}; + +/*! + * @brief PLL clock names for clock enable/disable settings. + * + * These constants define the PLL clock names for PLL clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock enable bit shift. + */ +enum _ccm_analog_pll_clock +{ + ccmAnalogPllArmClock = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT), /*!< CCM Analog ARM PLL Clock.*/ + ccmAnalogPllDdrClock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT), /*!< CCM Analog DDR PLL Clock.*/ + ccmAnalogPllDdrDiv2Clock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT), /*!< CCM Analog DDR PLL divided by 2 Clock.*/ + ccmAnalogPll480Clock = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT), /*!< CCM Analog 480M PLL Clock.*/ + ccmAnalogPllEnet25MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT), /*!< CCM Analog Ethernet 25M PLL Clock.*/ + ccmAnalogPllEnet40MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT), /*!< CCM Analog Ethernet 40M PLL Clock.*/ + ccmAnalogPllEnet50MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT), /*!< CCM Analog Ethernet 50M PLL Clock.*/ + ccmAnalogPllEnet100MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT), /*!< CCM Analog Ethernet 100M PLL Clock.*/ + ccmAnalogPllEnet125MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT), /*!< CCM Analog Ethernet 125M PLL Clock.*/ + ccmAnalogPllEnet250MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT), /*!< CCM Analog Ethernet 250M PLL Clock.*/ + ccmAnalogPllEnet500MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT), /*!< CCM Analog Ethernet 500M PLL Clock.*/ + ccmAnalogPllAudioClock = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT), /*!< CCM Analog AUDIO PLL Clock.*/ + ccmAnalogPllVideoClock = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT), /*!< CCM Analog VIDEO PLL Clock.*/ +}; + +/*! + * @brief PFD gate names for clock gate settings, clock source is system PLL(PLL_480) + * + * These constants define the PFD gate names for PFD clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock gate bit shift. + */ +enum _ccm_analog_pfd_clkgate +{ + ccmAnalogMainDiv1ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV1 Clock Gate.*/ + ccmAnalogMainDiv2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV2 Clock Gate.*/ + ccmAnalogMainDiv4ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV4 Clock Gate.*/ + ccmAnalogPfd0Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD0 DIV2 Clock Gate.*/ + ccmAnalogPfd1Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD1 DIV2 Clock Gate.*/ + ccmAnalogPfd2Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD2 DIV2 Clock Gate.*/ + ccmAnalogPfd0Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD0 DIV1 Clock Gate.*/ + ccmAnalogPfd1Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD1 DIV1 Clock Gate.*/ + ccmAnalogPfd2Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD2 DIV1 Clock Gate.*/ + ccmAnalogPfd3Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD3 DIV1 Clock Gate.*/ + ccmAnalogPfd4Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD4 DIV1 Clock Gate.*/ + ccmAnalogPfd5Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD5 DIV1 Clock Gate.*/ + ccmAnalogPfd6Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD6 DIV1 Clock Gate.*/ + ccmAnalogPfd7Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD7 DIV1 Clock Gate.*/ +}; + +/*! + * @brief PFD fraction names for clock fractional divider operations + * + * These constants define the PFD fraction names for PFD fractional divider operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Fraction bits shift. + */ +enum _ccm_analog_pfd_frac +{ + ccmAnalogPfd0Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT), /*!< CCM Analog 480A PFD0 fractional divider.*/ + ccmAnalogPfd1Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT), /*!< CCM Analog 480A PFD1 fractional divider.*/ + ccmAnalogPfd2Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT), /*!< CCM Analog 480A PFD2 fractional divider.*/ + ccmAnalogPfd3Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT), /*!< CCM Analog 480A PFD3 fractional divider.*/ + ccmAnalogPfd4Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT), /*!< CCM Analog 480B PFD4 fractional divider.*/ + ccmAnalogPfd5Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT), /*!< CCM Analog 480B PFD5 fractional divider.*/ + ccmAnalogPfd6Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT), /*!< CCM Analog 480B PFD6 fractional divider.*/ + ccmAnalogPfd7Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT), /*!< CCM Analog 480B PFD7 fractional divider.*/ +}; + +/*! + * @brief PFD stable names for clock stable query + * + * These constants define the PFD stable names for clock stable query.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Stable bit shift. + */ +enum _ccm_analog_pfd_stable +{ + ccmAnalogPfd0Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT), /*!< CCM Analog 480A PFD0 clock stable query.*/ + ccmAnalogPfd1Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT), /*!< CCM Analog 480A PFD1 clock stable query.*/ + ccmAnalogPfd2Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT), /*!< CCM Analog 480A PFD2 clock stable query.*/ + ccmAnalogPfd3Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT), /*!< CCM Analog 480A PFD3 clock stable query.*/ + ccmAnalogPfd4Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT), /*!< CCM Analog 480B PFD4 clock stable query.*/ + ccmAnalogPfd5Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT), /*!< CCM Analog 480B PFD5 clock stable query.*/ + ccmAnalogPfd6Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT), /*!< CCM Analog 480B PFD6 clock stable query.*/ + ccmAnalogPfd7Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT), /*!< CCM Analog 480B PFD7 clock stable query.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Analog PLL Operatoin Functions + * @{ + */ + +/*! + * @brief Power up PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + */ +static inline void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*! + * @brief Power down PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + */ +static inline void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false: Do not bypass the PLL. + */ +static inline void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass) +{ + if (bypass) + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK; + else + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CCM_ANALOG_IsPllBypassed(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_BYPASS_MASK); +} + +/*! + * @brief Check if PLL clock is locked + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL lock status. + * - true: The PLL clock is locked. + * - false: The PLL clock is not locked. + */ +static inline bool CCM_ANALOG_IsPllLocked(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_LOCK_MASK); +} + +/*! + * @brief Enable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) + */ +static inline void CCM_ANALOG_EnablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Disable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) + */ +static inline void CCM_ANALOG_DisablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Get ARM PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return ARM PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetArmPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get System PLL (PLL_480) clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return System PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetSysPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get DDR PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return DDR PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetDdrPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get ENET PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return ENET PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetEnetPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get Audio PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return Audio PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetAudioPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get Video PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return Video PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetVideoPllFreq(CCM_ANALOG_Type * base); + +/*@}*/ + +/*! + * @name CCM Analog PFD Operatoin Functions + * @{ + */ + +/*! + * @brief Enable PFD clock + * + * @param base CCM_ANALOG base pointer. + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) + */ +static inline void CCM_ANALOG_EnablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate); +} + +/*! + * @brief Disable PFD clock + * + * @param base CCM_ANALOG base pointer. + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) + */ +static inline void CCM_ANALOG_DisablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate); +} + +/*! + * @brief Check if PFD clock is stable + * + * @param base CCM_ANALOG base pointer. + * @param pfdStable PFD stable identifier (see @ref _ccm_analog_pfd_stable enumeration) + * @return PFD clock stable status. + * - true: The PFD clock is stable. + * - false: The PFD clock is not stable. + */ +static inline bool CCM_ANALOG_IsPfdStable(CCM_ANALOG_Type * base, uint32_t pfdStable) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pfdStable) & (1 << CCM_ANALOG_TUPLE_SHIFT(pfdStable))); +} + +/*! + * @brief Set PFD clock fraction + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @param value PFD clock fraction value + */ +static inline void CCM_ANALOG_SetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac, uint32_t value) +{ + assert(value >= 12 && value <= 35); + CCM_ANALOG_TUPLE_REG_CLR(base, pfdFrac) = CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_MASK << CCM_ANALOG_TUPLE_SHIFT(pfdFrac); + CCM_ANALOG_TUPLE_REG_SET(base, pfdFrac) = value << CCM_ANALOG_TUPLE_SHIFT(pfdFrac); +} + +/*! + * @brief Get PFD clock fraction + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @return PFD clock fraction value + */ +static inline uint32_t CCM_ANALOG_GetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac) +{ + return (CCM_ANALOG_TUPLE_REG(base, pfdFrac) >> CCM_ANALOG_TUPLE_SHIFT(pfdFrac)) & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK; +} + +/*! + * @brief Get PFD clock frequency + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @return PFD clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CCM_ANALOG_IMX7D_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ccm_imx6sx.c b/zephyr/imx/drivers/ccm_imx6sx.c new file mode 100644 index 000000000..27b2c8e17 --- /dev/null +++ b/zephyr/imx/drivers/ccm_imx6sx.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ccm_imx6sx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_SetClockEnableSignalOverrided + * Description : Override or do not override clock enable signal from module. + * + *END**************************************************************************/ +void CCM_SetClockEnableSignalOverrided(CCM_Type * base, uint32_t signal, bool control) +{ + if(control) + CCM_CMEOR_REG(base) |= signal; + else + CCM_CMEOR_REG(base) &= ~signal; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_SetMmdcHandshakeMask + * Description : Set handshake mask of MMDC module. + * + *END**************************************************************************/ +void CCM_SetMmdcHandshakeMask(CCM_Type * base, bool mask) +{ + if(mask) + CCM_CCDR_REG(base) |= CCM_CCDR_mmdc_mask_MASK; + else + CCM_CCDR_REG(base) &= ~CCM_CCDR_mmdc_mask_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ccm_imx6sx.h b/zephyr/imx/drivers/ccm_imx6sx.h new file mode 100644 index 000000000..17546e8fa --- /dev/null +++ b/zephyr/imx/drivers/ccm_imx6sx.h @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCM_IMX6SX_H__ +#define __CCM_IMX6SX_H__ + +#include +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ccm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_TUPLE(reg, shift, mask) ((offsetof(CCM_Type, reg) & 0xFF) | ((shift) << 8) | (((mask >> shift) & 0xFFFF) << 16)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFF)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8) & 0x1F) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 16) & 0xFFFF) << ((((tuple) >> 8) & 0x1F)))) + +/*! + * @brief Root control names for root clock setting. + * + * These constants define the root control names for root clock setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +enum _ccm_root_clock_control +{ + ccmRootPll1SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll1_sw_clk_sel_SHIFT, CCM_CCSR_pll1_sw_clk_sel_MASK), /*!< PLL1 SW Clock control name.*/ + ccmRootStepSel = CCM_TUPLE(CCSR, CCM_CCSR_step_sel_SHIFT, CCM_CCSR_step_sel_MASK), /*!< Step SW Clock control name.*/ + ccmRootPeriph2ClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk_sel_SHIFT, CCM_CBCDR_periph2_clk_sel_MASK), /*!< Peripheral2 Clock control name.*/ + ccmRootPrePeriph2ClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph2_clk_sel_SHIFT, CCM_CBCMR_pre_periph2_clk_sel_MASK), /*!< Pre Peripheral2 Clock control name.*/ + ccmRootPeriph2Clk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph2_clk2_sel_SHIFT, CCM_CBCMR_periph2_clk2_sel_MASK), /*!< Peripheral2 Clock2 Clock control name.*/ + ccmRootPll3SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll3_sw_clk_sel_SHIFT, CCM_CCSR_pll3_sw_clk_sel_MASK), /*!< PLL3 SW Clock control name.*/ + ccmRootOcramClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_clk_sel_SHIFT, CCM_CBCDR_ocram_clk_sel_MASK), /*!< OCRAM Clock control name.*/ + ccmRootOcramAltClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_alt_clk_sel_SHIFT, CCM_CBCDR_ocram_alt_clk_sel_MASK), /*!< OCRAM ALT Clock control name.*/ + ccmRootPeriphClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk_sel_SHIFT, CCM_CBCDR_periph_clk_sel_MASK), /*!< Peripheral Clock control name.*/ + ccmRootPeriphClk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph_clk2_sel_SHIFT, CCM_CBCMR_periph_clk2_sel_MASK), /*!< Peripheral Clock2 control name.*/ + ccmRootPrePeriphClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph_clk_sel_SHIFT, CCM_CBCMR_pre_periph_clk_sel_MASK), /*!< Pre Peripheral Clock control name.*/ + ccmRootPcieAxiClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pcie_axi_clk_sel_SHIFT, CCM_CBCMR_pcie_axi_clk_sel_MASK), /*!< PCIE AXI Clock control name.*/ + ccmRootPerclkClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_perclk_clk_sel_SHIFT, CCM_CSCMR1_perclk_clk_sel_MASK), /*!< Pre Clock control name.*/ + ccmRootUsdhc1ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc1_clk_sel_SHIFT, CCM_CSCMR1_usdhc1_clk_sel_MASK), /*!< USDHC1 Clock control name.*/ + ccmRootUsdhc2ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc2_clk_sel_SHIFT, CCM_CSCMR1_usdhc2_clk_sel_MASK), /*!< USDHC2 Clock control name.*/ + ccmRootUsdhc3ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc3_clk_sel_SHIFT, CCM_CSCMR1_usdhc3_clk_sel_MASK), /*!< USDHC3 Clock control name.*/ + ccmRootUsdhc4ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc4_clk_sel_SHIFT, CCM_CSCMR1_usdhc4_clk_sel_MASK), /*!< USDHC4 Clock control name.*/ + ccmRootAclkEimSlowSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_aclk_eim_slow_sel_SHIFT, CCM_CSCMR1_aclk_eim_slow_sel_MASK), /*!< ACLK EIM SLOW Clock control name.*/ + ccmRootGpuAxiSel = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_axi_sel_SHIFT, CCM_CBCMR_gpu_axi_sel_MASK), /*!< GPU AXI Clock control name.*/ + ccmRootGpuCoreSel = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_core_sel_SHIFT, CCM_CBCMR_gpu_core_sel_MASK), /*!< GPU Core Clock control name.*/ + ccmRootVidClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_vid_clk_sel_SHIFT, CCM_CSCMR2_vid_clk_sel_MASK), /*!< VID Clock control name.*/ + ccmRootEsaiClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_esai_clk_sel_SHIFT, CCM_CSCMR2_esai_clk_sel_MASK), /*!< ESAI Clock control name.*/ + ccmRootAudioClkSel = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_sel_SHIFT, CCM_CDCDR_audio_clk_sel_MASK), /*!< AUDIO Clock control name.*/ + ccmRootSpdif0ClkSel = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_sel_SHIFT, CCM_CDCDR_spdif0_clk_sel_MASK), /*!< SPDIF0 Clock control name.*/ + ccmRootSsi1ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi1_clk_sel_SHIFT, CCM_CSCMR1_ssi1_clk_sel_MASK), /*!< SSI1 Clock control name.*/ + ccmRootSsi2ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi2_clk_sel_SHIFT, CCM_CSCMR1_ssi2_clk_sel_MASK), /*!< SSI2 Clock control name.*/ + ccmRootSsi3ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi3_clk_sel_SHIFT, CCM_CSCMR1_ssi3_clk_sel_MASK), /*!< SSI3 Clock control name.*/ + ccmRootLcdif2ClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_clk_sel_SHIFT, CCM_CSCDR2_lcdif2_clk_sel_MASK), /*!< LCDIF2 Clock control name.*/ + ccmRootLcdif2PreClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_pre_clk_sel_SHIFT, CCM_CSCDR2_lcdif2_pre_clk_sel_MASK), /*!< LCDIF2 Pre Clock control name.*/ + ccmRootLdbDi1ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ldb_di1_clk_sel_SHIFT, CCM_CS2CDR_ldb_di1_clk_sel_MASK), /*!< LDB DI1 Clock control name.*/ + ccmRootLdbDi0ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ldb_di0_clk_sel_SHIFT, CCM_CS2CDR_ldb_di0_clk_sel_MASK), /*!< LDB DI0 Clock control name.*/ + ccmRootLcdif1ClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_clk_sel_SHIFT, CCM_CSCDR2_lcdif1_clk_sel_MASK), /*!< LCDIF1 Clock control name.*/ + ccmRootLcdif1PreClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_pre_clk_sel_SHIFT, CCM_CSCDR2_lcdif1_pre_clk_sel_MASK), /*!< LCDIF1 Pre Clock control name.*/ + ccmRootM4ClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_clk_sel_SHIFT, CCM_CHSCCDR_m4_clk_sel_MASK), /*!< M4 Clock control name.*/ + ccmRootM4PreClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_pre_clk_sel_SHIFT, CCM_CHSCCDR_m4_pre_clk_sel_MASK), /*!< M4 Pre Clock control name.*/ + ccmRootEnetClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_clk_sel_SHIFT, CCM_CHSCCDR_enet_clk_sel_MASK), /*!< Ethernet Clock control name.*/ + ccmRootEnetPreClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_pre_clk_sel_SHIFT, CCM_CHSCCDR_enet_pre_clk_sel_MASK), /*!< Ethernet Pre Clock control name.*/ + ccmRootQspi2ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_sel_SHIFT, CCM_CS2CDR_qspi2_clk_sel_MASK), /*!< QSPI2 Clock control name.*/ + ccmRootDisplayClkSel = CCM_TUPLE(CSCDR3, CCM_CSCDR3_display_clk_sel_SHIFT, CCM_CSCDR3_display_clk_sel_MASK), /*!< Display Clock control name.*/ + ccmRootCsiClkSel = CCM_TUPLE(CSCDR3, CCM_CSCDR3_csi_clk_sel_SHIFT, CCM_CSCDR3_csi_clk_sel_MASK), /*!< CSI Clock control name.*/ + ccmRootCanClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_can_clk_sel_SHIFT, CCM_CSCMR2_can_clk_sel_MASK), /*!< CAN Clock control name.*/ + ccmRootEcspiClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ecspi_clk_sel_SHIFT, CCM_CSCDR2_ecspi_clk_sel_MASK), /*!< ECSPI Clock control name.*/ + ccmRootUartClkSel = CCM_TUPLE(CSCDR1, CCM_CSCDR1_uart_clk_sel_SHIFT, CCM_CSCDR1_uart_clk_sel_MASK) /*!< UART Clock control name.*/ +}; + +/*! @brief Root clock select enumeration for pll1_sw_clk_sel. */ +enum _ccm_rootmux_pll1_sw_clk_sel +{ + ccmRootmuxPll1SwClkPll1MainClk = 0U, /*!< PLL1 SW Clock from PLL1 Main Clock.*/ + ccmRootmuxPll1SwClkStepClk = 1U, /*!< PLL1 SW Clock from Step Clock.*/ +}; + +/*! @brief Root clock select enumeration for step_sel. */ +enum _ccm_rootmux_step_sel +{ + ccmRootmuxStepOsc24m = 0U, /*!< Step Clock from OSC 24M.*/ + ccmRootmuxStepPll2Pfd2 = 1U, /*!< Step Clock from PLL2 PFD2.*/ +}; + +/*! @brief Root clock select enumeration for periph2_clk_sel. */ +enum _ccm_rootmux_periph2_clk_sel +{ + ccmRootmuxPeriph2ClkPrePeriph2Clk = 0U, /*!< Peripheral2 Clock from Pre Peripheral2 Clock.*/ + ccmRootmuxPeriph2ClkPeriph2Clk2 = 1U, /*!< Peripheral2 Clock from Peripheral2.*/ +}; + +/*! @brief Root clock select enumeration for pre_periph2_clk_sel. */ +enum _ccm_rootmux_pre_periph2_clk_sel +{ + ccmRootmuxPrePeriph2ClkPll2 = 0U, /*!< Pre Peripheral2 Clock from PLL2.*/ + ccmRootmuxPrePeriph2ClkPll2Pfd2 = 1U, /*!< Pre Peripheral2 Clock from PLL2 PFD2.*/ + ccmRootmuxPrePeriph2ClkPll2Pfd0 = 2U, /*!< Pre Peripheral2 Clock from PLL2 PFD0.*/ + ccmRootmuxPrePeriph2ClkPll4 = 3U, /*!< Pre Peripheral2 Clock from PLL4.*/ +}; + +/*! @brief Root clock select enumeration for periph2_clk2_sel. */ +enum _ccm_rootmux_periph2_clk2_sel +{ + ccmRootmuxPeriph2Clk2Pll3SwClk = 0U, /*!< Peripheral2 Clock from PLL3 SW Clock.*/ + ccmRootmuxPeriph2Clk2Osc24m = 1U, /*!< Peripheral2 Clock from OSC 24M.*/ +}; + +/*! @brief Root clock select enumeration for pll3_sw_clk_sel. */ +enum _ccm_rootmux_pll3_sw_clk_sel +{ + ccmRootmuxPll3SwClkPll3 = 0U, /*!< PLL3 SW Clock from PLL3.*/ + ccmRootmuxPll3SwClkPll3BypassClk = 1U, /*!< PLL3 SW Clock from PLL3 Bypass Clock.*/ +}; + +/*! @brief Root clock select enumeration for ocram_clk_sel. */ +enum _ccm_rootmux_ocram_clk_sel +{ + ccmRootmuxOcramClkPeriphClk = 0U, /*!< OCRAM Clock from Peripheral Clock.*/ + ccmRootmuxOcramClkOcramAltClk = 1U, /*!< OCRAM Clock from OCRAM ALT Clock.*/ +}; + +/*! @brief Root clock select enumeration for ocram_alt_clk_sel. */ +enum _ccm_rootmux_ocram_alt_clk_sel +{ + ccmRootmuxOcramAltClkPll2Pfd2 = 0U, /*!< OCRAM ALT Clock from PLL2 PFD2.*/ + ccmRootmuxOcramAltClkPll3Pfd1 = 1U, /*!< OCRAM ALT Clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for periph_clk_sel. */ +enum _ccm_rootmux_periph_clk_sel +{ + ccmRootmuxPeriphClkPrePeriphClkSel = 0U, /*!< Peripheral Clock from Pre Peripheral .*/ + ccmRootmuxPeriphClkPeriphClk2Sel = 1U, /*!< Peripheral Clock from Peripheral2.*/ +}; + +/*! @brief Root clock select enumeration for periph_clk2_sel. */ +enum _ccm_rootmux_periph_clk2_sel +{ + ccmRootmuxPeriphClk2Pll3SwClk = 0U, /*!< Peripheral Clock2 from from PLL3 SW Clock.*/ + ccmRootmuxPeriphClk2OSC24m = 1U, /*!< Peripheral Clock2 from OSC 24M.*/ + ccmRootmuxPeriphClk2Pll2 = 2U, /*!< Peripheral Clock2 from PLL2.*/ +}; + +/*! @brief Root clock select enumeration for pre_periph_clk_sel. */ +enum _ccm_rootmux_pre_periph_clk_sel +{ + ccmRootmuxPrePeriphClkPll2 = 0U, /*!< Pre Peripheral Clock from PLL2.*/ + ccmRootmuxPrePeriphClkPll2Pfd2 = 1U, /*!< Pre Peripheral Clock from PLL2 PFD2.*/ + ccmRootmuxPrePeriphClkPll2Pfd0 = 2U, /*!< Pre Peripheral Clock from PLL2 PFD0.*/ + ccmRootmuxPrePeriphClkPll2Pfd2div2 = 3U, /*!< Pre Peripheral Clock from PLL2 PFD2 divided by 2.*/ +}; + +/*! @brief Root clock select enumeration for pcie_axi_clk_sel. */ +enum _ccm_rootmux_pcie_axi_clk_sel +{ + ccmRootmuxPcieAxiClkAxiClk = 0U, /*!< PCIE AXI Clock from AXI Clock.*/ + ccmRootmuxPcieAxiClkAhbClk = 1U, /*!< PCIE AXI Clock from AHB Clock.*/ +}; + +/*! @brief Root clock select enumeration for perclk_clk_sel. */ +enum _ccm_rootmux_perclk_clk_sel +{ + ccmRootmuxPerclkClkIpgClkRoot = 0U, /*!< Perclk from IPG Clock Root.*/ + ccmRootmuxPerclkClkOsc24m = 1U, /*!< Perclk from OSC 24M.*/ +}; + +/*! @brief Root clock select enumeration for usdhc1_clk_sel. */ +enum _ccm_rootmux_usdhc1_clk_sel +{ + ccmRootmuxUsdhc1ClkPll2Pfd2 = 0U, /*!< USDHC1 Clock from PLL2 PFD2.*/ + ccmRootmuxUsdhc1ClkPll2Pfd0 = 1U, /*!< USDHC1 Clock from PLL2 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for usdhc2_clk_sel. */ +enum _ccm_rootmux_usdhc2_clk_sel +{ + ccmRootmuxUsdhc2ClkPll2Pfd2 = 0U, /*!< USDHC2 Clock from PLL2 PFD2.*/ + ccmRootmuxUsdhc2ClkPll2Pfd0 = 1U, /*!< USDHC2 Clock from PLL2 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for usdhc3_clk_sel. */ +enum _ccm_rootmux_usdhc3_clk_sel +{ + ccmRootmuxUsdhc3ClkPll2Pfd2 = 0U, /*!< USDHC3 Clock from PLL2 PFD2.*/ + ccmRootmuxUsdhc3ClkPll2Pfd0 = 1U, /*!< USDHC3 Clock from PLL2 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for usdhc4_clk_sel. */ +enum _ccm_rootmux_usdhc4_clk_sel +{ + ccmRootmuxUsdhc4ClkPll2Pfd2 = 0U, /*!< USDHC4 Clock from PLL2 PFD2.*/ + ccmRootmuxUsdhc4ClkPll2Pfd0 = 1U, /*!< USDHC4 Clock from PLL2 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for aclk_eim_slow_sel. */ +enum _ccm_rootmux_aclk_eim_slow_sel +{ + ccmRootmuxAclkEimSlowAxiClk = 0U, /*!< Aclk EimSlow Clock from AXI Clock.*/ + ccmRootmuxAclkEimSlowPll3SwClk = 1U, /*!< Aclk EimSlow Clock from PLL3 SW Clock.*/ + ccmRootmuxAclkEimSlowPll2Pfd2 = 2U, /*!< Aclk EimSlow Clock from PLL2 PFD2.*/ + ccmRootmuxAclkEimSlowPll3Pfd0 = 3U, /*!< Aclk EimSlow Clock from PLL3 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for gpu_axi_sel. */ +enum _ccm_rootmux_gpu_axi_sel +{ + ccmRootmuxGpuAxiPll2Pfd2 = 0U, /*!< GPU AXI Clock from PLL2 PFD2.*/ + ccmRootmuxGpuAxiPll3Pfd0 = 1U, /*!< GPU AXI Clock from PLL3 PFD0.*/ + ccmRootmuxGpuAxiPll2Pfd1 = 2U, /*!< GPU AXI Clock from PLL2 PFD1.*/ + ccmRootmuxGpuAxiPll2 = 3U, /*!< GPU AXI Clock from PLL2.*/ +}; + +/*! @brief Root clock select enumeration for gpu_core_sel. */ +enum _ccm_rootmux_gpu_core_sel +{ + ccmRootmuxGpuCorePll3Pfd1 = 0U, /*!< GPU Core Clock from PLL3 PFD1.*/ + ccmRootmuxGpuCorePll3Pfd0 = 1U, /*!< GPU Core Clock from PLL3 PFD0.*/ + ccmRootmuxGpuCorePll2 = 2U, /*!< GPU Core Clock from PLL2.*/ + ccmRootmuxGpuCorePll2Pfd2 = 3U, /*!< GPU Core Clock from PLL2 PFD2.*/ +}; + +/*! @brief Root clock select enumeration for vid_clk_sel. */ +enum _ccm_rootmux_vid_clk_sel +{ + ccmRootmuxVidClkPll3Pfd1 = 0U, /*!< VID Clock from PLL3 PFD1.*/ + ccmRootmuxVidClkPll3 = 1U, /*!< VID Clock from PLL3.*/ + ccmRootmuxVidClkPll3Pfd3 = 2U, /*!< VID Clock from PLL3 PFD3.*/ + ccmRootmuxVidClkPll4 = 3U, /*!< VID Clock from PLL4.*/ + ccmRootmuxVidClkPll5 = 4U, /*!< VID Clock from PLL5.*/ +}; + +/*! @brief Root clock select enumeration for esai_clk_sel. */ +enum _ccm_rootmux_esai_clk_sel +{ + ccmRootmuxEsaiClkPll4 = 0U, /*!< ESAI Clock from PLL4.*/ + ccmRootmuxEsaiClkPll3Pfd2 = 1U, /*!< ESAI Clock from PLL3 PFD2.*/ + ccmRootmuxEsaiClkPll5 = 2U, /*!< ESAI Clock from PLL5.*/ + ccmRootmuxEsaiClkPll3SwClk = 3U, /*!< ESAI Clock from PLL3 SW Clock.*/ +}; + +/*! @brief Root clock select enumeration for audio_clk_sel. */ +enum _ccm_rootmux_audio_clk_sel +{ + ccmRootmuxAudioClkPll4 = 0U, /*!< Audio Clock from PLL4.*/ + ccmRootmuxAudioClkPll3Pfd2 = 1U, /*!< Audio Clock from PLL3 PFD2.*/ + ccmRootmuxAudioClkPll5 = 2U, /*!< Audio Clock from PLL5.*/ + ccmRootmuxAudioClkPll3SwClk = 3U, /*!< Audio Clock from PLL3 SW Clock.*/ +}; + +/*! @brief Root clock select enumeration for spdif0_clk_sel. */ +enum _ccm_rootmux_spdif0_clk_sel +{ + ccmRootmuxSpdif0ClkPll4 = 0U, /*!< SPDIF0 Clock from PLL4.*/ + ccmRootmuxSpdif0ClkPll3Pfd2 = 1U, /*!< SPDIF0 Clock from PLL3 PFD2.*/ + ccmRootmuxSpdif0ClkPll5 = 2U, /*!< SPDIF0 Clock from PLL5.*/ + ccmRootmuxSpdif0ClkPll3SwClk = 3U, /*!< SPDIF0 Clock from PLL3 SW Clock.*/ +}; + +/*! @brief Root clock select enumeration for ssi1_clk_sel. */ +enum _ccm_rootmux_ssi1_clk_sel +{ + ccmRootmuxSsi1ClkPll3Pfd2 = 0U, /*!< SSI1 Clock from PLL3 PFD2.*/ + ccmRootmuxSsi1ClkPll5 = 1U, /*!< SSI1 Clock from PLL5.*/ + ccmRootmuxSsi1ClkPll4 = 2U, /*!< SSI1 Clock from PLL4.*/ +}; + +/*! @brief Root clock select enumeration for ssi2_clk_sel. */ +enum _ccm_rootmux_ssi2_clk_sel +{ + ccmRootmuxSsi2ClkPll3Pfd2 = 0U, /*!< SSI2 Clock from PLL3 PFD2.*/ + ccmRootmuxSsi2ClkPll5 = 1U, /*!< SSI2 Clock from PLL5.*/ + ccmRootmuxSsi2ClkPll4 = 2U, /*!< SSI2 Clock from PLL4.*/ +}; + +/*! @brief Root clock select enumeration for ssi3_clk_sel. */ +enum _ccm_rootmux_ssi3_clk_sel +{ + ccmRootmuxSsi3ClkPll3Pfd2 = 0U, /*!< SSI3 Clock from PLL3 PFD2.*/ + ccmRootmuxSsi3ClkPll5 = 1U, /*!< SSI3 Clock from PLL5.*/ + ccmRootmuxSsi3ClkPll4 = 2U, /*!< SSI3 Clock from PLL4.*/ +}; + +/*! @brief Root clock select enumeration for lcdif2_clk_sel. */ +enum _ccm_rootmux_lcdif2_clk_sel +{ + ccmRootmuxLcdif2ClkLcdif2PreClk = 0U, /*!< LCDIF2 Clock from LCDIF2 Pre Clock.*/ + ccmRootmuxLcdif2ClkIppDi0Clk = 1U, /*!< LCDIF2 Clock from IPP DI0 Clock.*/ + ccmRootmuxLcdif2ClkIppDi1Clk = 2U, /*!< LCDIF2 Clock from IPP DI0 Clock.*/ + ccmRootmuxLcdif2ClkLdbDi0Clk = 3U, /*!< LCDIF2 Clock from LDB DI0 Clock.*/ + ccmRootmuxLcdif2ClkLdbDi1Clk = 4U, /*!< LCDIF2 Clock from LDB DI0 Clock.*/ +}; + +/*! @brief Root clock select enumeration for lcdif2_pre_clk_sel. */ +enum _ccm_rootmux_lcdif2_pre_clk_sel +{ + ccmRootmuxLcdif2ClkPrePll2 = 0U, /*!< LCDIF2 Pre Clock from PLL2.*/ + ccmRootmuxLcdif2ClkPrePll3Pfd3 = 1U, /*!< LCDIF2 Pre Clock from PLL3 PFD3.*/ + ccmRootmuxLcdif2ClkPrePll5 = 2U, /*!< LCDIF2 Pre Clock from PLL3 PFD5.*/ + ccmRootmuxLcdif2ClkPrePll2Pfd0 = 3U, /*!< LCDIF2 Pre Clock from PLL2 PFD0.*/ + ccmRootmuxLcdif2ClkPrePll2Pfd3 = 4U, /*!< LCDIF2 Pre Clock from PLL2 PFD3.*/ + ccmRootmuxLcdif2ClkPrePll3Pfd1 = 5U, /*!< LCDIF2 Pre Clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for ldb_di1_clk_sel. */ +enum _ccm_rootmux_ldb_di1_clk_sel +{ + ccmRootmuxLdbDi1ClkPll3SwClk = 0U, /*!< lDB DI1 Clock from PLL3 SW Clock.*/ + ccmRootmuxLdbDi1ClkPll2Pfd0 = 1U, /*!< lDB DI1 Clock from PLL2 PFD0.*/ + ccmRootmuxLdbDi1ClkPll2Pfd2 = 2U, /*!< lDB DI1 Clock from PLL2 PFD2.*/ + ccmRootmuxLdbDi1ClkPll2 = 3U, /*!< lDB DI1 Clock from PLL2.*/ + ccmRootmuxLdbDi1ClkPll3Pfd3 = 4U, /*!< lDB DI1 Clock from PLL3 PFD3.*/ + ccmRootmuxLdbDi1ClkPll3Pfd2 = 5U, /*!< lDB DI1 Clock from PLL3 PFD2.*/ +}; + +/*! @brief Root clock select enumeration for ldb_di0_clk_sel. */ +enum _ccm_rootmux_ldb_di0_clk_sel +{ + ccmRootmuxLdbDi0ClkPll5 = 0U, /*!< lDB DI0 Clock from PLL5.*/ + ccmRootmuxLdbDi0ClkPll2Pfd0 = 1U, /*!< lDB DI0 Clock from PLL2 PFD0.*/ + ccmRootmuxLdbDi0ClkPll2Pfd2 = 2U, /*!< lDB DI0 Clock from PLL2 PFD2.*/ + ccmRootmuxLdbDi0ClkPll2Pfd3 = 3U, /*!< lDB DI0 Clock from PLL2 PFD3.*/ + ccmRootmuxLdbDi0ClkPll3Pfd1 = 4U, /*!< lDB DI0 Clock from PLL3 PFD1.*/ + ccmRootmuxLdbDi0ClkPll3Pfd3 = 5U, /*!< lDB DI0 Clock from PLL3 PFD3.*/ +}; + +/*! @brief Root clock select enumeration for lcdif1_clk_sel. */ +enum _ccm_rootmux_lcdif1_clk_sel +{ + ccmRootmuxLcdif1ClkLcdif1PreClk = 0U, /*!< LCDIF1 clock from LCDIF1 Pre Clock.*/ + ccmRootmuxLcdif1ClkIppDi0Clk = 1U, /*!< LCDIF1 clock from IPP DI0 Clock.*/ + ccmRootmuxLcdif1ClkIppDi1Clk = 2U, /*!< LCDIF1 clock from IPP DI1 Clock.*/ + ccmRootmuxLcdif1ClkLdbDi0Clk = 3U, /*!< LCDIF1 clock from LDB DI0 Clock.*/ + ccmRootmuxLcdif1ClkLdbDi1Clk = 4U, /*!< LCDIF1 clock from LDB DI1 Clock.*/ +}; + +/*! @brief Root clock select enumeration for lcdif1_pre_clk_sel. */ +enum _ccm_rootmux_lcdif1_pre_clk_sel +{ + ccmRootmuxLcdif1PreClkPll2 = 0U, /*!< LCDIF1 pre clock from PLL2.*/ + ccmRootmuxLcdif1PreClkPll3Pfd3 = 1U, /*!< LCDIF1 pre clock from PLL3 PFD3.*/ + ccmRootmuxLcdif1PreClkPll5 = 2U, /*!< LCDIF1 pre clock from PLL5.*/ + ccmRootmuxLcdif1PreClkPll2Pfd0 = 3U, /*!< LCDIF1 pre clock from PLL2 PFD0.*/ + ccmRootmuxLcdif1PreClkPll2Pfd1 = 4U, /*!< LCDIF1 pre clock from PLL2 PFD1.*/ + ccmRootmuxLcdif1PreClkPll3Pfd1 = 5U, /*!< LCDIF1 pre clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for m4_clk_sel. */ +enum _ccm_rootmux_m4_clk_sel +{ + ccmRootmuxM4ClkM4PreClk = 0U, /*!< M4 clock from M4 Pre Clock.*/ + ccmRootmuxM4ClkPll3Pfd3 = 1U, /*!< M4 clock from PLL3 PFD3.*/ + ccmRootmuxM4ClkIppDi0Clk = 2U, /*!< M4 clock from IPP DI0 Clock.*/ + ccmRootmuxM4ClkIppDi1Clk = 3U, /*!< M4 clock from IPP DI1 Clock.*/ + ccmRootmuxM4ClkLdbDi0Clk = 4U, /*!< M4 clock from LDB DI0 Clock.*/ + ccmRootmuxM4ClkLdbDi1Clk = 5U, /*!< M4 clock from LDB DI1 Clock.*/ +}; + +/*! @brief Root clock select enumeration for m4_pre_clk_sel. */ +enum _ccm_rootmux_m4_pre_clk_sel +{ + ccmRootmuxM4PreClkPll2 = 0U, /*!< M4 pre clock from PLL2.*/ + ccmRootmuxM4PreClkPll3SwClk = 1U, /*!< M4 pre clock from PLL3 SW Clock.*/ + ccmRootmuxM4PreClkOsc24m = 2U, /*!< M4 pre clock from OSC 24M.*/ + ccmRootmuxM4PreClkPll2Pfd0 = 3U, /*!< M4 pre clock from PLL2 PFD0.*/ + ccmRootmuxM4PreClkPll2Pfd2 = 4U, /*!< M4 pre clock from PLL2 PFD2.*/ + ccmRootmuxM4PreClkPll3Pfd3 = 5U, /*!< M4 pre clock from PLL3 PFD3.*/ +}; + +/*! @brief Root clock select enumeration for nent_clk_sel. */ +enum _ccm_rootmux_enet_clk_sel +{ + ccmRootmuxEnetClkEnetPreClk = 0U, /*!< Ethernet clock from Ethernet Pre Clock.*/ + ccmRootmuxEnetClkIppDi0Clk = 1U, /*!< Ethernet clock from IPP DI0 Clock.*/ + ccmRootmuxEnetClkIppDi1Clk = 2U, /*!< Ethernet clock from IPP DI1 Clock.*/ + ccmRootmuxEnetClkLdbDi0Clk = 3U, /*!< Ethernet clock from LDB DI0 Clock.*/ + ccmRootmuxEnetClkLdbDi1Clk = 4U, /*!< Ethernet clock from LDB DI1 Clock.*/ +}; + +/*! @brief Root clock select enumeration for enet_pre_clk_sel. */ +enum _ccm_rootmux_enet_pre_clk_sel +{ + ccmRootmuxEnetPreClkPll2 = 0U, /*!< Ethernet Pre clock from PLL2.*/ + ccmRootmuxEnetPreClkPll3SwClk = 1U, /*!< Ethernet Pre clock from PLL3 SW Clock.*/ + ccmRootmuxEnetPreClkPll5 = 2U, /*!< Ethernet Pre clock from PLL5.*/ + ccmRootmuxEnetPreClkPll2Pfd0 = 3U, /*!< Ethernet Pre clock from PLL2 PFD0.*/ + ccmRootmuxEnetPreClkPll2Pfd2 = 4U, /*!< Ethernet Pre clock from PLL2 PFD2.*/ + ccmRootmuxEnetPreClkPll3Pfd2 = 5U, /*!< Ethernet Pre clock from PLL3 PFD2.*/ +}; + +/*! @brief Root clock select enumeration for qspi2_clk_sel. */ +enum _ccm_rootmux_qspi2_clk_sel +{ + ccmRootmuxQspi2ClkPll2Pfd0 = 0U, /*!< QSPI2 Clock from PLL2 PFD0.*/ + ccmRootmuxQspi2ClkPll2 = 1U, /*!< QSPI2 Clock from PLL2.*/ + ccmRootmuxQspi2ClkPll3SwClk = 2U, /*!< QSPI2 Clock from PLL3 SW Clock.*/ + ccmRootmuxQspi2ClkPll2Pfd2 = 3U, /*!< QSPI2 Clock from PLL2 PFD2.*/ + ccmRootmuxQspi2ClkPll3Pfd3 = 4U, /*!< QSPI2 Clock from PLL3 PFD3.*/ +}; + +/*! @brief Root clock select enumeration for display_clk_sel. */ +enum _ccm_rootmux_display_clk_sel +{ + ccmRootmuxDisplayClkPll2 = 0U, /*!< Display Clock from PLL2.*/ + ccmRootmuxDisplayClkPll2Pfd2 = 1U, /*!< Display Clock from PLL2 PFD2.*/ + ccmRootmuxDisplayClkPll3SwClk = 2U, /*!< Display Clock from PLL3 SW Clock.*/ + ccmRootmuxDisplayClkPll3Pfd1 = 3U, /*!< Display Clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for csi_clk_sel. */ +enum _ccm_rootmux_csi_clk_sel +{ + ccmRootmuxCsiClkOSC24m = 0U, /*!< CSI Clock from OSC 24M.*/ + ccmRootmuxCsiClkPll2Pfd2 = 1U, /*!< CSI Clock from PLL2 PFD2.*/ + ccmRootmuxCsiClkPll3SwClkDiv2 = 2U, /*!< CSI Clock from PLL3 SW clock divided by 2.*/ + ccmRootmuxCsiClkPll3Pfd1 = 3U, /*!< CSI Clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for can_clk_sel. */ +enum _ccm_rootmux_can_clk_sel +{ + ccmRootmuxCanClkPll3SwClkDiv8 = 0U, /*!< CAN Clock from PLL3 SW clock divided by 8.*/ + ccmRootmuxCanClkOsc24m = 1U, /*!< CAN Clock from OSC 24M.*/ + ccmRootmuxCanClkPll3SwClkDiv6 = 2U, /*!< CAN Clock from PLL3 SW clock divided by 6.*/ + ccmRootmuxCanClkDisableFlexcanClk = 3U, /*!< Disable FlexCAN clock.*/ +}; + +/*! @brief Root clock select enumeration for ecspi_clk_sel. */ +enum _ccm_rootmux_ecspi_clk_sel +{ + ccmRootmuxEcspiClkPll3SwClkDiv8 = 0U, /*!< ecSPI Clock from PLL3 SW clock divided by 8.*/ + ccmRootmuxEcspiClkOsc24m = 1U, /*!< ecSPI Clock from OSC 24M.*/ +}; + +/*! @brief Root clock select enumeration for uart_clk_sel. */ +enum _ccm_rootmux_uart_clk_sel +{ + ccmRootmuxUartClkPll3SwClkDiv6 = 0U, /*!< UART Clock from PLL3 SW clock divided by 6.*/ + ccmRootmuxUartClkOsc24m = 1U, /*!< UART Clock from OSC 24M.*/ +}; + +/*! + * @brief Root control names for root divider setting. + * + * These constants define the root control names for root divider setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root divider setting bit field shift. + * - 16:31: Root divider setting bit field width. + */ +enum _ccm_root_div_control +{ + ccmRootArmPodf = CCM_TUPLE(CACRR, CCM_CACRR_arm_podf_SHIFT, CCM_CACRR_arm_podf_MASK), /*!< ARM Clock post divider control names.*/ + ccmRootFabricMmdcPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_fabric_mmdc_podf_SHIFT, CCM_CBCDR_fabric_mmdc_podf_MASK), /*!< Fabric MMDC Clock post divider control names.*/ + ccmRootPeriph2Clk2Podf = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk2_podf_SHIFT, CCM_CBCDR_periph2_clk2_podf_MASK), /*!< Peripheral2 Clock2 post divider control names.*/ + ccmRootOcramPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_podf_SHIFT, CCM_CBCDR_ocram_podf_MASK), /*!< OCRAM Clock post divider control names.*/ + ccmRootAhbPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ahb_podf_SHIFT, CCM_CBCDR_ahb_podf_MASK), /*!< AHB Clock post divider control names.*/ + ccmRootPeriphClk2Podf = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk2_podf_SHIFT, CCM_CBCDR_periph_clk2_podf_MASK), /*!< Peripheral Clock2 post divider control names.*/ + ccmRootPerclkPodf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_perclk_podf_SHIFT, CCM_CSCMR1_perclk_podf_MASK), /*!< Pre Clock post divider control names.*/ + ccmRootIpgPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ipg_podf_SHIFT, CCM_CBCDR_ipg_podf_MASK), /*!< IPG Clock post divider control names.*/ + ccmRootUsdhc1Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc1_podf_SHIFT, CCM_CSCDR1_usdhc1_podf_MASK), /*!< USDHC1 Clock post divider control names.*/ + ccmRootUsdhc2Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc2_podf_SHIFT, CCM_CSCDR1_usdhc2_podf_MASK), /*!< USDHC2 Clock post divider control names.*/ + ccmRootUsdhc3Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc3_podf_SHIFT, CCM_CSCDR1_usdhc3_podf_MASK), /*!< USDHC3 Clock post divider control names.*/ + ccmRootUsdhc4Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc4_podf_SHIFT, CCM_CSCDR1_usdhc4_podf_MASK), /*!< USDHC4 Clock post divider control names.*/ + ccmRootAclkEimSlowPodf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_aclk_eim_slow_podf_SHIFT, CCM_CSCMR1_aclk_eim_slow_podf_MASK), /*!< ACLK EIM SLOW Clock post divider control names.*/ + ccmRootGpuAxiPodf = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_axi_podf_SHIFT, CCM_CBCMR_gpu_axi_podf_MASK), /*!< GPU AXI Clock post divider control names.*/ + ccmRootGpuCorePodf = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_core_podf_SHIFT, CCM_CBCMR_gpu_core_podf_MASK), /*!< GPU Core Clock post divider control names.*/ + ccmRootVidClkPodf = CCM_TUPLE(CSCMR2, CCM_CSCMR2_vid_clk_podf_SHIFT, CCM_CSCMR2_vid_clk_podf_MASK), /*!< VID Clock post divider control names.*/ + ccmRootEsaiClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_esai_clk_podf_SHIFT, CCM_CS1CDR_esai_clk_podf_MASK), /*!< ESAI Clock pre divider control names.*/ + ccmRootEsaiClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_esai_clk_pred_SHIFT, CCM_CS1CDR_esai_clk_pred_MASK), /*!< ESAI Clock post divider control names.*/ + ccmRootAudioClkPodf = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_podf_SHIFT, CCM_CDCDR_audio_clk_podf_MASK), /*!< AUDIO Clock post divider control names.*/ + ccmRootAudioClkPred = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_pred_SHIFT, CCM_CDCDR_audio_clk_pred_MASK), /*!< AUDIO Clock pre divider control names.*/ + ccmRootSpdif0ClkPodf = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_podf_SHIFT, CCM_CDCDR_spdif0_clk_podf_MASK), /*!< SPDIF0 Clock post divider control names.*/ + ccmRootSpdif0ClkPred = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_pred_SHIFT, CCM_CDCDR_spdif0_clk_pred_MASK), /*!< SPDIF0 Clock pre divider control names.*/ + ccmRootSsi1ClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi1_clk_podf_SHIFT, CCM_CS1CDR_ssi1_clk_podf_MASK), /*!< SSI1 Clock post divider control names.*/ + ccmRootSsi1ClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi1_clk_pred_SHIFT, CCM_CS1CDR_ssi1_clk_pred_MASK), /*!< SSI1 Clock pre divider control names.*/ + ccmRootSsi2ClkPodf = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ssi2_clk_podf_SHIFT, CCM_CS2CDR_ssi2_clk_podf_MASK), /*!< SSI2 Clock post divider control names.*/ + ccmRootSsi2ClkPred = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ssi2_clk_pred_SHIFT, CCM_CS2CDR_ssi2_clk_pred_MASK), /*!< SSI2 Clock pre divider control names.*/ + ccmRootSsi3ClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi3_clk_podf_SHIFT, CCM_CS1CDR_ssi3_clk_podf_MASK), /*!< SSI3 Clock post divider control names.*/ + ccmRootSsi3ClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi3_clk_pred_SHIFT, CCM_CS1CDR_ssi3_clk_pred_MASK), /*!< SSI3 Clock pre divider control names.*/ + ccmRootLcdif2Podf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_lcdif2_podf_SHIFT, CCM_CSCMR1_lcdif2_podf_MASK), /*!< LCDIF2 Clock post divider control names.*/ + ccmRootLcdif2Pred = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_pred_SHIFT, CCM_CSCDR2_lcdif2_pred_MASK), /*!< LCDIF2 Clock pre divider control names.*/ + ccmRootLdbDi1Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ldb_di1_div_SHIFT, CCM_CSCMR2_ldb_di1_div_MASK), /*!< LDB DI1 Clock divider control names.*/ + ccmRootLdbDi0Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ldb_di0_div_SHIFT, CCM_CSCMR2_ldb_di0_div_MASK), /*!< LCDIDI0 Clock divider control names.*/ + ccmRootLcdif1Podf = CCM_TUPLE(CBCMR, CCM_CBCMR_lcdif1_podf_SHIFT, CCM_CBCMR_lcdif1_podf_MASK), /*!< LCDIF1 Clock post divider control names.*/ + ccmRootLcdif1Pred = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_pred_SHIFT, CCM_CSCDR2_lcdif1_pred_MASK), /*!< LCDIF1 Clock pre divider control names.*/ + ccmRootM4Podf = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_podf_SHIFT, CCM_CHSCCDR_m4_podf_MASK), /*!< M4 Clock post divider control names.*/ + ccmRootEnetPodf = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_podf_SHIFT, CCM_CHSCCDR_enet_podf_MASK), /*!< Ethernet Clock post divider control names.*/ + ccmRootQspi1Podf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_qspi1_podf_SHIFT, CCM_CSCMR1_qspi1_podf_MASK), /*!< QSPI1 Clock post divider control names.*/ + ccmRootQspi2ClkPodf = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_podf_SHIFT, CCM_CS2CDR_qspi2_clk_podf_MASK), /*!< QSPI2 Clock post divider control names.*/ + ccmRootQspi2ClkPred = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_pred_SHIFT, CCM_CS2CDR_qspi2_clk_pred_MASK), /*!< QSPI2 Clock pre divider control names.*/ + ccmRootDisplayPodf = CCM_TUPLE(CSCDR3, CCM_CSCDR3_display_podf_SHIFT, CCM_CSCDR3_display_podf_MASK), /*!< Display Clock post divider control names.*/ + ccmRootCsiPodf = CCM_TUPLE(CSCDR3, CCM_CSCDR3_csi_podf_SHIFT, CCM_CSCDR3_csi_podf_MASK), /*!< CSI Clock post divider control names.*/ + ccmRootCanClkPodf = CCM_TUPLE(CSCMR2, CCM_CSCMR2_can_clk_podf_SHIFT, CCM_CSCMR2_can_clk_podf_MASK), /*!< CAN Clock post divider control names.*/ + ccmRootEcspiClkPodf = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ecspi_clk_podf_SHIFT, CCM_CSCDR2_ecspi_clk_podf_MASK), /*!< ECSPI Clock post divider control names.*/ + ccmRootUartClkPodf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_uart_clk_podf_SHIFT, CCM_CSCDR1_uart_clk_podf_MASK) /*!< UART Clock post divider control names.*/ +}; + +/*! + * @brief CCM CCGR gate control for each module independently. + * + * These constants define the ccm ccgr clock gate for each module.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root divider setting bit field shift. + * - 16:31: Root divider setting bit field width. + */ +enum _ccm_ccgr_gate +{ + ccmCcgrGateAipsTz1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG0_SHIFT, CCM_CCGR0_CG0_MASK), /*!< AipsTz1 Clock Gate.*/ + ccmCcgrGateAipsTz2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG1_SHIFT, CCM_CCGR0_CG1_MASK), /*!< AipsTz2 Clock Gate.*/ + ccmCcgrGateApbhdmaHclk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG2_SHIFT, CCM_CCGR0_CG2_MASK), /*!< ApbhdmaH Clock Gate.*/ + ccmCcgrGateAsrcClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG3_SHIFT, CCM_CCGR0_CG3_MASK), /*!< Asrc Clock Gate.*/ + ccmCcgrGateCaamSecureMemClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG4_SHIFT, CCM_CCGR0_CG4_MASK), /*!< CaamSecureMem Clock Gate.*/ + ccmCcgrGateCaamWrapperAclk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG5_SHIFT, CCM_CCGR0_CG5_MASK), /*!< CaamWrapperA Clock Gate.*/ + ccmCcgrGateCaamWrapperIpg = CCM_TUPLE(CCGR0, CCM_CCGR0_CG6_SHIFT, CCM_CCGR0_CG6_MASK), /*!< CaamWrapperIpg Clock Gate.*/ + ccmCcgrGateCan1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG7_SHIFT, CCM_CCGR0_CG7_MASK), /*!< Can1 Clock Gate.*/ + ccmCcgrGateCan1SerialClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG8_SHIFT, CCM_CCGR0_CG8_MASK), /*!< Can1 Serial Clock Gate.*/ + ccmCcgrGateCan2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG9_SHIFT, CCM_CCGR0_CG9_MASK), /*!< Can2 Clock Gate.*/ + ccmCcgrGateCan2SerialClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG10_SHIFT, CCM_CCGR0_CG10_MASK), /*!< Can2 Serial Clock Gate.*/ + ccmCcgrGateArmDbgClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG11_SHIFT, CCM_CCGR0_CG11_MASK), /*!< Arm Debug Clock Gate.*/ + ccmCcgrGateDcic1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG12_SHIFT, CCM_CCGR0_CG12_MASK), /*!< Dcic1 Clock Gate.*/ + ccmCcgrGateDcic2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG13_SHIFT, CCM_CCGR0_CG13_MASK), /*!< Dcic2 Clock Gate.*/ + ccmCcgrGateAipsTz3Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG15_SHIFT, CCM_CCGR0_CG15_MASK), /*!< AipsTz3 Clock Gate.*/ + ccmCcgrGateEcspi1Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG0_SHIFT, CCM_CCGR1_CG0_MASK), /*!< Ecspi1 Clock Gate.*/ + ccmCcgrGateEcspi2Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG1_SHIFT, CCM_CCGR1_CG1_MASK), /*!< Ecspi2 Clock Gate.*/ + ccmCcgrGateEcspi3Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG2_SHIFT, CCM_CCGR1_CG2_MASK), /*!< Ecspi3 Clock Gate.*/ + ccmCcgrGateEcspi4Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG3_SHIFT, CCM_CCGR1_CG3_MASK), /*!< Ecspi4 Clock Gate.*/ + ccmCcgrGateEcspi5Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG4_SHIFT, CCM_CCGR1_CG4_MASK), /*!< Ecspi5 Clock Gate.*/ + ccmCcgrGateEpit1Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG6_SHIFT, CCM_CCGR1_CG6_MASK), /*!< Epit1 Clock Gate.*/ + ccmCcgrGateEpit2Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG7_SHIFT, CCM_CCGR1_CG7_MASK), /*!< Epit2 Clock Gate.*/ + ccmCcgrGateEsaiClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG8_SHIFT, CCM_CCGR1_CG8_MASK), /*!< Esai Clock Gate.*/ + ccmCcgrGateWakeupClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG9_SHIFT, CCM_CCGR1_CG9_MASK), /*!< Wakeup Clock Gate.*/ + ccmCcgrGateGptClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG10_SHIFT, CCM_CCGR1_CG10_MASK), /*!< Gpt Clock Gate.*/ + ccmCcgrGateGptSerialClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG11_SHIFT, CCM_CCGR1_CG11_MASK), /*!< Gpt Serial Clock Gate.*/ + ccmCcgrGateGpuClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG13_SHIFT, CCM_CCGR1_CG13_MASK), /*!< Gpu Clock Gate.*/ + ccmCcgrGateOcramSClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG14_SHIFT, CCM_CCGR1_CG14_MASK), /*!< OcramS Clock Gate.*/ + ccmCcgrGateCanfdClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG15_SHIFT, CCM_CCGR1_CG15_MASK), /*!< Canfd Clock Gate.*/ + ccmCcgrGateCsiClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG1_SHIFT, CCM_CCGR2_CG1_MASK), /*!< Csi Clock Gate.*/ + ccmCcgrGateI2c1Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG3_SHIFT, CCM_CCGR2_CG3_MASK), /*!< I2c1 Serial Clock Gate.*/ + ccmCcgrGateI2c2Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG4_SHIFT, CCM_CCGR2_CG4_MASK), /*!< I2c2 Serial Clock Gate.*/ + ccmCcgrGateI2c3Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG5_SHIFT, CCM_CCGR2_CG5_MASK), /*!< I2c3 Serial Clock Gate.*/ + ccmCcgrGateIimClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG6_SHIFT, CCM_CCGR2_CG6_MASK), /*!< Iim Clock Gate.*/ + ccmCcgrGateIomuxIptClkIo = CCM_TUPLE(CCGR2, CCM_CCGR2_CG7_SHIFT, CCM_CCGR2_CG7_MASK), /*!< Iomux Ipt Clock Gate.*/ + ccmCcgrGateIpmux1Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG8_SHIFT, CCM_CCGR2_CG8_MASK), /*!< Ipmux1 Clock Gate.*/ + ccmCcgrGateIpmux2Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG9_SHIFT, CCM_CCGR2_CG9_MASK), /*!< Ipmux2 Clock Gate.*/ + ccmCcgrGateIpmux3Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG10_SHIFT, CCM_CCGR2_CG10_MASK), /*!< Ipmux3 Clock Gate.*/ + ccmCcgrGateIpsyncIp2apbtTasc1 = CCM_TUPLE(CCGR2, CCM_CCGR2_CG11_SHIFT, CCM_CCGR2_CG11_MASK), /*!< IpsyncIp2apbtTasc1 Clock Gate.*/ + ccmCcgrGateLcdClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG14_SHIFT, CCM_CCGR2_CG14_MASK), /*!< Lcd Clock Gate.*/ + ccmCcgrGatePxpClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG15_SHIFT, CCM_CCGR2_CG15_MASK), /*!< Pxp Clock Gate.*/ + ccmCcgrGateM4Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG1_SHIFT, CCM_CCGR3_CG1_MASK), /*!< M4 Clock Gate.*/ + ccmCcgrGateEnetClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG2_SHIFT, CCM_CCGR3_CG2_MASK), /*!< Enet Clock Gate.*/ + ccmCcgrGateDispAxiClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG3_SHIFT, CCM_CCGR3_CG3_MASK), /*!< DispAxi Clock Gate.*/ + ccmCcgrGateLcdif2PixClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG4_SHIFT, CCM_CCGR3_CG4_MASK), /*!< Lcdif2Pix Clock Gate.*/ + ccmCcgrGateLcdif1PixClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG5_SHIFT, CCM_CCGR3_CG5_MASK), /*!< Lcdif1Pix Clock Gate.*/ + ccmCcgrGateLdbDi0Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG6_SHIFT, CCM_CCGR3_CG6_MASK), /*!< LdbDi0 Clock Gate.*/ + ccmCcgrGateQspi1Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG7_SHIFT, CCM_CCGR3_CG7_MASK), /*!< Qspi1 Clock Gate.*/ + ccmCcgrGateMlbClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG9_SHIFT, CCM_CCGR3_CG9_MASK), /*!< Mlb Clock Gate.*/ + ccmCcgrGateMmdcCoreAclkFastP0 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG10_SHIFT, CCM_CCGR3_CG10_MASK), /*!< Mmdc Core Aclk FastP0 Clock Gate.*/ + ccmCcgrGateMmdcCoreIpgClkP0 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG12_SHIFT, CCM_CCGR3_CG12_MASK), /*!< Mmdc Core Ipg Clk P0 Clock Gate.*/ + ccmCcgrGateMmdcCoreIpgClkP1 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG13_SHIFT, CCM_CCGR3_CG13_MASK), /*!< Mmdc Core Ipg Clk P1 Clock Gate.*/ + ccmCcgrGateOcramClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG14_SHIFT, CCM_CCGR3_CG14_MASK), /*!< Ocram Clock Gate.*/ + ccmCcgrGatePcieRoot = CCM_TUPLE(CCGR4, CCM_CCGR4_CG0_SHIFT, CCM_CCGR4_CG0_MASK), /*!< Pcie Clock Gate.*/ + ccmCcgrGateQspi2Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG5_SHIFT, CCM_CCGR4_CG5_MASK), /*!< Qspi2 Clock Gate.*/ + ccmCcgrGatePl301Mx6qper1Bch = CCM_TUPLE(CCGR4, CCM_CCGR4_CG6_SHIFT, CCM_CCGR4_CG6_MASK), /*!< Pl301Mx6qper1Bch Clock Gate.*/ + ccmCcgrGatePl301Mx6qper2Main = CCM_TUPLE(CCGR4, CCM_CCGR4_CG7_SHIFT, CCM_CCGR4_CG7_MASK), /*!< Pl301Mx6qper2Main Clock Gate.*/ + ccmCcgrGatePwm1Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG8_SHIFT, CCM_CCGR4_CG8_MASK), /*!< Pwm1 Clock Gate.*/ + ccmCcgrGatePwm2Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG9_SHIFT, CCM_CCGR4_CG9_MASK), /*!< Pwm2 Clock Gate.*/ + ccmCcgrGatePwm3Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG10_SHIFT, CCM_CCGR4_CG10_MASK), /*!< Pwm3 Clock Gate.*/ + ccmCcgrGatePwm4Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG11_SHIFT, CCM_CCGR4_CG11_MASK), /*!< Pwm4 Clock Gate.*/ + ccmCcgrGateRawnandUBchInptApb = CCM_TUPLE(CCGR4, CCM_CCGR4_CG12_SHIFT, CCM_CCGR4_CG12_MASK), /*!< RawnandUBchInptApb Clock Gate.*/ + ccmCcgrGateRawnandUGpmiBch = CCM_TUPLE(CCGR4, CCM_CCGR4_CG13_SHIFT, CCM_CCGR4_CG13_MASK), /*!< RawnandUGpmiBch Clock Gate.*/ + ccmCcgrGateRawnandUGpmiGpmiIo = CCM_TUPLE(CCGR4, CCM_CCGR4_CG14_SHIFT, CCM_CCGR4_CG14_MASK), /*!< RawnandUGpmiGpmiIo Clock Gate.*/ + ccmCcgrGateRawnandUGpmiInpApb = CCM_TUPLE(CCGR4, CCM_CCGR4_CG15_SHIFT, CCM_CCGR4_CG15_MASK), /*!< RawnandUGpmiInpApb Clock Gate.*/ + ccmCcgrGateRomClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG0_SHIFT, CCM_CCGR5_CG0_MASK), /*!< Rom Clock Gate.*/ + ccmCcgrGateSdmaClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG3_SHIFT, CCM_CCGR5_CG3_MASK), /*!< Sdma Clock Gate.*/ + ccmCcgrGateSpbaClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG6_SHIFT, CCM_CCGR5_CG6_MASK), /*!< Spba Clock Gate.*/ + ccmCcgrGateSpdifAudioClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG7_SHIFT, CCM_CCGR5_CG7_MASK), /*!< SpdifAudio Clock Gate.*/ + ccmCcgrGateSsi1Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG9_SHIFT, CCM_CCGR5_CG9_MASK), /*!< Ssi1 Clock Gate.*/ + ccmCcgrGateSsi2Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG10_SHIFT, CCM_CCGR5_CG10_MASK), /*!< Ssi2 Clock Gate.*/ + ccmCcgrGateSsi3Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG11_SHIFT, CCM_CCGR5_CG11_MASK), /*!< Ssi3 Clock Gate.*/ + ccmCcgrGateUartClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG12_SHIFT, CCM_CCGR5_CG12_MASK), /*!< Uart Clock Gate.*/ + ccmCcgrGateUartSerialClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG13_SHIFT, CCM_CCGR5_CG13_MASK), /*!< Uart Serial Clock Gate.*/ + ccmCcgrGateSai1Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG14_SHIFT, CCM_CCGR5_CG14_MASK), /*!< Sai1 Clock Gate.*/ + ccmCcgrGateSai2Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG15_SHIFT, CCM_CCGR5_CG15_MASK), /*!< Sai2 Clock Gate.*/ + ccmCcgrGateUsboh3Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG0_SHIFT, CCM_CCGR6_CG0_MASK), /*!< Usboh3 Clock Gate.*/ + ccmCcgrGateUsdhc1Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG1_SHIFT, CCM_CCGR6_CG1_MASK), /*!< Usdhc1 Clock Gate.*/ + ccmCcgrGateUsdhc2Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG2_SHIFT, CCM_CCGR6_CG2_MASK), /*!< Usdhc2 Clock Gate.*/ + ccmCcgrGateUsdhc3Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG3_SHIFT, CCM_CCGR6_CG3_MASK), /*!< Usdhc3 Clock Gate.*/ + ccmCcgrGateUsdhc4Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG4_SHIFT, CCM_CCGR6_CG4_MASK), /*!< Usdhc4 Clock Gate.*/ + ccmCcgrGateEimSlowClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG5_SHIFT, CCM_CCGR6_CG5_MASK), /*!< EimSlow Clock Gate.*/ + ccmCcgrGatePwm8Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG8_SHIFT, CCM_CCGR6_CG8_MASK), /*!< Pwm8 Clock Gate.*/ + ccmCcgrGateVadcClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG10_SHIFT, CCM_CCGR6_CG10_MASK), /*!< Vadc Clock Gate.*/ + ccmCcgrGateGisClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG11_SHIFT, CCM_CCGR6_CG11_MASK), /*!< Gis Clock Gate.*/ + ccmCcgrGateI2c4SerialClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG12_SHIFT, CCM_CCGR6_CG12_MASK), /*!< I2c4 Serial Clock Gate.*/ + ccmCcgrGatePwm5Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG13_SHIFT, CCM_CCGR6_CG13_MASK), /*!< Pwm5 Clock Gate.*/ + ccmCcgrGatePwm6Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG14_SHIFT, CCM_CCGR6_CG14_MASK), /*!< Pwm6 Clock Gate.*/ + ccmCcgrGatePwm7Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG15_SHIFT, CCM_CCGR6_CG15_MASK), /*!< Pwm7 Clock Gate.*/ +}; + +/*! @brief CCM gate control value. */ +enum _ccm_gate_value +{ + ccmClockNotNeeded = 0U, /*!< Clock always disabled.*/ + ccmClockNeededRun = 1U, /*!< Clock enabled when CPU is running.*/ + ccmClockNeededAll = 3U /*!< Clock always enabled.*/ +}; + +/*! @brief CCM override clock enable signal from module. */ +enum _ccm_overrided_enable_signal +{ + ccmOverridedSignalFromGpt = 1U << 5, /*!< Override clock enable signal from GPT.*/ + ccmOverridedSignalFromEpit = 1U << 6, /*!< Override clock enable signal from EPIT.*/ + ccmOverridedSignalFromUsdhc = 1U << 7, /*!< Override clock enable signal from USDHC.*/ + ccmOverridedSignalFromGpu = 1U << 10, /*!< Override clock enable signal from GPU.*/ + ccmOverridedSignalFromCan2Cpi = 1U << 28, /*!< Override clock enable signal from CAN2.*/ + ccmOverridedSignalFromCan1Cpi = 1U << 30 /*!< Override clock enable signal from CAN1.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Root Clock Setting + * @{ + */ + +/*! + * @brief Set clock root mux. + * User maybe need to set more than one mux node according to the clock tree + * description on the reference manual. + * + * @param base CCM base pointer. + * @param ccmRootClk Root clock control (see @ref _ccm_root_clock_control enumeration). + * @param mux Root mux value (see @ref _ccm_rootmux_xxx enumeration). + */ +static inline void CCM_SetRootMux(CCM_Type * base, uint32_t ccmRootClk, uint32_t mux) +{ + CCM_TUPLE_REG(base, ccmRootClk) = (CCM_TUPLE_REG(base, ccmRootClk) & (~CCM_TUPLE_MASK(ccmRootClk))) | + (((uint32_t)((mux) << CCM_TUPLE_SHIFT(ccmRootClk))) & CCM_TUPLE_MASK(ccmRootClk)); +} + +/*! + * @brief Get clock root mux. + * In order to get the clock source of root, user maybe need to get more than one + * node's mux value to obtain the final clock source of root. + * + * @param base CCM base pointer. + * @param ccmRootClk Root clock control (see @ref _ccm_root_clock_control enumeration). + * @return Root mux value (see @ref _ccm_rootmux_xxx enumeration). + */ +static inline uint32_t CCM_GetRootMux(CCM_Type * base, uint32_t ccmRootClk) +{ + return (CCM_TUPLE_REG(base, ccmRootClk) & CCM_TUPLE_MASK(ccmRootClk)) >> CCM_TUPLE_SHIFT(ccmRootClk); +} + +/*! + * @brief Set root clock divider. + * User should set the dividers carefully according to the clock tree on + * the reference manual. Take care of that the setting of one divider value + * may affect several clock root. + * + * @param base CCM base pointer. + * @param ccmRootDiv Root divider control (see @ref _ccm_root_div_control enumeration) + * @param div Divider value (divider = div + 1). + */ +static inline void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRootDiv, uint32_t div) +{ + CCM_TUPLE_REG(base, ccmRootDiv) = (CCM_TUPLE_REG(base, ccmRootDiv) & (~CCM_TUPLE_MASK(ccmRootDiv))) | + (((uint32_t)((div) << CCM_TUPLE_SHIFT(ccmRootDiv))) & CCM_TUPLE_MASK(ccmRootDiv)); +} + +/*! + * @brief Get root clock divider. + * In order to get divider value of clock root, user should get specific + * divider value according to the clock tree description on reference manual. + * Then calculate the root clock with those divider value. + * + * @param base CCM base pointer. + * @param ccmRootDiv Root control (see @ref _ccm_root_div_control enumeration). + * @param div Pointer to divider value store address. + * @return Root divider value. + */ +static inline uint32_t CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRootDiv) +{ + return (CCM_TUPLE_REG(base, ccmRootDiv) & CCM_TUPLE_MASK(ccmRootDiv)) >> CCM_TUPLE_SHIFT(ccmRootDiv); +} + +/*! + * @brief Set handshake mask of MMDC module. + * During divider ratio mmdc_axi_podf change or sync mux periph2_clk_sel + * change (but not jtag) or SRC request during warm reset, mask handshake with mmdc module. + * + * @param base CCM base pointer. + * @param mask True: mask handshake with MMDC; False: allow handshake with MMDC. + */ +void CCM_SetMmdcHandshakeMask(CCM_Type * base, bool mask); + +/*@}*/ + +/*! + * @name CCM Gate Control + * @{ + */ + +/*! + * @brief Set CCGR gate control for each module + * User should set specific gate for each module according to the description + * of the table of system clocks, gating and override in CCM chapter of + * reference manual. Take care of that one module may need to set more than + * one clock gate. + * + * @param base CCM base pointer. + * @param ccmGate Gate control for each module (see @ref _ccm_ccgr_gate enumeration). + * @param control Gate control value (see @ref _ccm_gate_value). + */ +static inline void CCM_ControlGate(CCM_Type * base, uint32_t ccmGate, uint32_t control) +{ + CCM_TUPLE_REG(base, ccmGate) = (CCM_TUPLE_REG(base, ccmGate) & (~CCM_TUPLE_MASK(ccmGate))) | + (((uint32_t)((control) << CCM_TUPLE_SHIFT(ccmGate))) & CCM_TUPLE_MASK(ccmGate)); +} + +/*! + * @brief Set override or do not override clock enable signal from module. + * This is applicable only for modules whose clock enable signals are used. + * + * @param base CCM base pointer. + * @param signal Overrided enable signal from module (see @ref _ccm_overrided_enable_signal enumeration). + * @param control Override / Do not override clock enable signal from module. + * - true: override clock enable signal. + * - false: Do not override clock enable signal. + */ +void CCM_SetClockEnableSignalOverrided(CCM_Type * base, uint32_t signal, bool control); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CCM_IMX6SX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ccm_imx7d.c b/zephyr/imx/drivers/ccm_imx7d.c new file mode 100644 index 000000000..11f2889a2 --- /dev/null +++ b/zephyr/imx/drivers/ccm_imx7d.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ccm_imx7d.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_SetDivider + * Description : Set root clock divider + * + *END**************************************************************************/ +void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t pre, uint32_t post) +{ + assert (pre < 8); + assert (post < 64); + + CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & + (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) | + CCM_TARGET_ROOT_PRE_PODF(pre) | CCM_TARGET_ROOT_POST_PODF(post); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_GetDivider + * Description : Get root clock divider + * + *END**************************************************************************/ +void CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t *pre, uint32_t *post) +{ + assert (pre && post); + + *pre = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT; + *post = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_UpdateRoot + * Description : Update clock root in one step, for dynamical clock switching + * + *END**************************************************************************/ +void CCM_UpdateRoot(CCM_Type * base, uint32_t ccmRoot, uint32_t mux, uint32_t pre, uint32_t post) +{ + assert (pre < 8); + assert (post < 64); + + CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & + (~(CCM_TARGET_ROOT_MUX_MASK | CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) | + CCM_TARGET_ROOT_MUX(mux) | CCM_TARGET_ROOT_PRE_PODF(pre) | CCM_TARGET_ROOT_POST_PODF(post); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ccm_imx7d.h b/zephyr/imx/drivers/ccm_imx7d.h new file mode 100644 index 000000000..088971829 --- /dev/null +++ b/zephyr/imx/drivers/ccm_imx7d.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCM_IMX7D_H__ +#define __CCM_IMX7D_H__ + +#include +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ccm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)root + off))) +#define CCM_REG(root) CCM_REG_OFF(root, 0) +#define CCM_REG_SET(root) CCM_REG_OFF(root, 4) +#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8) + +/*! @brief Root control names for root clock setting. */ +enum _ccm_root_control +{ + ccmRootM4 = (uint32_t)(&CCM_TARGET_ROOT1), /*!< ARM Cortex-M4 Clock control name.*/ + ccmRootAxi = (uint32_t)(&CCM_TARGET_ROOT16), /*!< AXI Clock control name.*/ + ccmRootAhb = (uint32_t)(&CCM_TARGET_ROOT32), /*!< AHB Clock control name.*/ + ccmRootIpg = (uint32_t)(&CCM_TARGET_ROOT33), /*!< IPG Clock control name.*/ + ccmRootQspi = (uint32_t)(&CCM_TARGET_ROOT85), /*!< QSPI Clock control name.*/ + ccmRootCan1 = (uint32_t)(&CCM_TARGET_ROOT89), /*!< CAN1 Clock control name.*/ + ccmRootCan2 = (uint32_t)(&CCM_TARGET_ROOT90), /*!< CAN2 Clock control name.*/ + ccmRootI2c1 = (uint32_t)(&CCM_TARGET_ROOT91), /*!< I2C1 Clock control name.*/ + ccmRootI2c2 = (uint32_t)(&CCM_TARGET_ROOT92), /*!< I2C2 Clock control name.*/ + ccmRootI2c3 = (uint32_t)(&CCM_TARGET_ROOT93), /*!< I2C3 Clock control name.*/ + ccmRootI2c4 = (uint32_t)(&CCM_TARGET_ROOT94), /*!< I2C4 Clock control name.*/ + ccmRootUart1 = (uint32_t)(&CCM_TARGET_ROOT95), /*!< UART1 Clock control name.*/ + ccmRootUart2 = (uint32_t)(&CCM_TARGET_ROOT96), /*!< UART2 Clock control name.*/ + ccmRootUart3 = (uint32_t)(&CCM_TARGET_ROOT97), /*!< UART3 Clock control name.*/ + ccmRootUart4 = (uint32_t)(&CCM_TARGET_ROOT98), /*!< UART4 Clock control name.*/ + ccmRootUart5 = (uint32_t)(&CCM_TARGET_ROOT99), /*!< UART5 Clock control name.*/ + ccmRootUart6 = (uint32_t)(&CCM_TARGET_ROOT100), /*!< UART6 Clock control name.*/ + ccmRootUart7 = (uint32_t)(&CCM_TARGET_ROOT101), /*!< UART7 Clock control name.*/ + ccmRootEcspi1 = (uint32_t)(&CCM_TARGET_ROOT102), /*!< ECSPI1 Clock control name.*/ + ccmRootEcspi2 = (uint32_t)(&CCM_TARGET_ROOT103), /*!< ECSPI2 Clock control name.*/ + ccmRootEcspi3 = (uint32_t)(&CCM_TARGET_ROOT104), /*!< ECSPI3 Clock control name.*/ + ccmRootEcspi4 = (uint32_t)(&CCM_TARGET_ROOT105), /*!< ECSPI4 Clock control name.*/ + ccmRootFtm1 = (uint32_t)(&CCM_TARGET_ROOT110), /*!< FTM1 Clock control name.*/ + ccmRootFtm2 = (uint32_t)(&CCM_TARGET_ROOT111), /*!< FTM2 Clock control name.*/ + ccmRootGpt1 = (uint32_t)(&CCM_TARGET_ROOT114), /*!< GPT1 Clock control name.*/ + ccmRootGpt2 = (uint32_t)(&CCM_TARGET_ROOT115), /*!< GPT2 Clock control name.*/ + ccmRootGpt3 = (uint32_t)(&CCM_TARGET_ROOT116), /*!< GPT3 Clock control name.*/ + ccmRootGpt4 = (uint32_t)(&CCM_TARGET_ROOT117), /*!< GPT4 Clock control name.*/ + ccmRootWdog = (uint32_t)(&CCM_TARGET_ROOT119), /*!< WDOG Clock control name.*/ +}; + +/*! @brief Clock source enumeration for ARM Cortex-M4 core. */ +enum _ccm_rootmux_m4 +{ + ccmRootmuxM4Osc24m = 0U, /*!< ARM Cortex-M4 Clock from OSC 24M.*/ + ccmRootmuxM4SysPllDiv2 = 1U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxM4EnetPll250m = 2U, /*!< ARM Cortex-M4 Clock from Ethernet PLL 250M.*/ + ccmRootmuxM4SysPllPfd2 = 3U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxM4DdrPllDiv2 = 4U, /*!< ARM Cortex-M4 Clock from DDR PLL divided by 2.*/ + ccmRootmuxM4AudioPll = 5U, /*!< ARM Cortex-M4 Clock from AUDIO PLL.*/ + ccmRootmuxM4VideoPll = 6U, /*!< ARM Cortex-M4 Clock from VIDEO PLL.*/ + ccmRootmuxM4UsbPll = 7U, /*!< ARM Cortex-M4 Clock from USB PLL.*/ +}; + +/*! @brief Clock source enumeration for AXI bus. */ +enum _ccm_rootmux_axi +{ + ccmRootmuxAxiOsc24m = 0U, /*!< AXI Clock from OSC 24M.*/ + ccmRootmuxAxiSysPllPfd1 = 1U, /*!< AXI Clock from SYSTEM PLL PFD1.*/ + ccmRootmuxAxiDdrPllDiv2 = 2U, /*!< AXI Clock DDR PLL divided by 2.*/ + ccmRootmuxAxiEnetPll250m = 3U, /*!< AXI Clock Ethernet PLL 250M.*/ + ccmRootmuxAxiSysPllPfd5 = 4U, /*!< AXI Clock SYSTEM PLL PFD5.*/ + ccmRootmuxAxiAudioPll = 5U, /*!< AXI Clock AUDIO PLL.*/ + ccmRootmuxAxiVideoPll = 6U, /*!< AXI Clock VIDEO PLL.*/ + ccmRootmuxAxiSysPllPfd7 = 7U, /*!< AXI Clock SYSTEM PLL PFD7.*/ +}; + +/*! @brief Clock source enumeration for AHB bus. */ +enum _ccm_rootmux_ahb +{ + ccmRootmuxAhbOsc24m = 0U, /*!< AHB Clock from OSC 24M.*/ + ccmRootmuxAhbSysPllPfd2 = 1U, /*!< AHB Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxAhbDdrPllDiv2 = 2U, /*!< AHB Clock from DDR PLL divided by 2.*/ + ccmRootmuxAhbSysPllPfd0 = 3U, /*!< AHB Clock from SYSTEM PLL PFD0.*/ + ccmRootmuxAhbEnetPll125m = 4U, /*!< AHB Clock from Ethernet PLL 125M.*/ + ccmRootmuxAhbUsbPll = 5U, /*!< AHB Clock from USB PLL.*/ + ccmRootmuxAhbAudioPll = 6U, /*!< AHB Clock from AUDIO PLL.*/ + ccmRootmuxAhbVideoPll = 7U, /*!< AHB Clock from VIDEO PLL.*/ +}; + +/*! @brief Clock source enumeration for IPG bus. */ +enum _ccm_rootmux_ipg +{ + ccmRootmuxIpgAHB = 0U, /*!< IPG Clock from AHB Clock.*/ +}; + +/*! @brief Clock source enumeration for QSPI peripheral. */ +enum _ccm_rootmux_qspi +{ + ccmRootmuxQspiOsc24m = 0U, /*!< QSPI Clock from OSC 24M.*/ + ccmRootmuxQspiSysPllPfd4 = 1U, /*!< QSPI Clock from SYSTEM PLL PFD4.*/ + ccmRootmuxQspiDdrPllDiv2 = 2U, /*!< QSPI Clock from DDR PLL divided by 2.*/ + ccmRootmuxQspiEnetPll500m = 3U, /*!< QSPI Clock from Ethernet PLL 500M.*/ + ccmRootmuxQspiSysPllPfd3 = 4U, /*!< QSPI Clock from SYSTEM PLL PFD3.*/ + ccmRootmuxQspiSysPllPfd2 = 5U, /*!< QSPI Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxQspiSysPllPfd6 = 6U, /*!< QSPI Clock from SYSTEM PLL PFD6.*/ + ccmRootmuxQspiSysPllPfd7 = 7U, /*!< QSPI Clock from SYSTEM PLL PFD7.*/ +}; + +/*! @brief Clock source enumeration for CAN peripheral. */ +enum _ccm_rootmux_can +{ + ccmRootmuxCanOsc24m = 0U, /*!< CAN Clock from OSC 24M.*/ + ccmRootmuxCanSysPllDiv4 = 1U, /*!< CAN Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxCanDdrPllDiv2 = 2U, /*!< CAN Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxCanSysPllDiv1 = 3U, /*!< CAN Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxCanEnetPll40m = 4U, /*!< CAN Clock from Ethernet PLL 40M.*/ + ccmRootmuxCanUsbPll = 5U, /*!< CAN Clock from USB PLL.*/ + ccmRootmuxCanExtClk1 = 6U, /*!< CAN Clock from External Clock1.*/ + ccmRootmuxCanExtClk34 = 7U, /*!< CAN Clock from External Clock34.*/ +}; + +/*! @brief Clock source enumeration for ECSPI peripheral. */ +enum _ccm_rootmux_ecspi +{ + ccmRootmuxEcspiOsc24m = 0U, /*!< ECSPI Clock from OSC 24M.*/ + ccmRootmuxEcspiSysPllDiv2 = 1U, /*!< ECSPI Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxEcspiEnetPll40m = 2U, /*!< ECSPI Clock from Ethernet PLL 40M.*/ + ccmRootmuxEcspiSysPllDiv4 = 3U, /*!< ECSPI Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxEcspiSysPllDiv1 = 4U, /*!< ECSPI Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxEcspiSysPllPfd4 = 5U, /*!< ECSPI Clock from SYSTEM PLL PFD4.*/ + ccmRootmuxEcspiEnetPll250m = 6U, /*!< ECSPI Clock from Ethernet PLL 250M.*/ + ccmRootmuxEcspiUsbPll = 7U, /*!< ECSPI Clock from USB PLL.*/ +}; + +/*! @brief Clock source enumeration for I2C peripheral. */ +enum _ccm_rootmux_i2c +{ + ccmRootmuxI2cOsc24m = 0U, /*!< I2C Clock from OSC 24M.*/ + ccmRootmuxI2cSysPllDiv4 = 1U, /*!< I2C Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxI2cEnetPll50m = 2U, /*!< I2C Clock from Ethernet PLL 50M.*/ + ccmRootmuxI2cDdrPllDiv2 = 3U, /*!< I2C Clock from DDR PLL divided by .*/ + ccmRootmuxI2cAudioPll = 4U, /*!< I2C Clock from AUDIO PLL.*/ + ccmRootmuxI2cVideoPll = 5U, /*!< I2C Clock from VIDEO PLL.*/ + ccmRootmuxI2cUsbPll = 6U, /*!< I2C Clock from USB PLL.*/ + ccmRootmuxI2cSysPllPfd2Div2 = 7U, /*!< I2C Clock from SYSTEM PLL PFD2 divided by 2.*/ +}; + +/*! @brief Clock source enumeration for UART peripheral. */ +enum _ccm_rootmux_uart +{ + ccmRootmuxUartOsc24m = 0U, /*!< UART Clock from OSC 24M.*/ + ccmRootmuxUartSysPllDiv2 = 1U, /*!< UART Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxUartEnetPll40m = 2U, /*!< UART Clock from Ethernet PLL 40M.*/ + ccmRootmuxUartEnetPll100m = 3U, /*!< UART Clock from Ethernet PLL 100M.*/ + ccmRootmuxUartSysPllDiv1 = 4U, /*!< UART Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxUartExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/ + ccmRootmuxUartExtClk34 = 6U, /*!< UART Clock from External Clock 34.*/ + ccmRootmuxUartUsbPll = 7U, /*!< UART Clock from USB PLL.*/ +}; + +/*! @brief Clock source enumeration for FlexTimer peripheral. */ +enum _ccm_rootmux_ftm +{ + ccmRootmuxFtmOsc24m = 0U, /*!< FTM Clock from OSC 24M.*/ + ccmRootmuxFtmEnetPll100m = 1U, /*!< FTM Clock from Ethernet PLL 100M.*/ + ccmRootmuxFtmSysPllDiv4 = 2U, /*!< FTM Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxFtmEnetPll40m = 3U, /*!< FTM Clock from Ethernet PLL 40M.*/ + ccmRootmuxFtmAudioPll = 4U, /*!< FTM Clock from AUDIO PLL.*/ + ccmRootmuxFtmExtClk3 = 5U, /*!< FTM Clock from External Clock 3.*/ + ccmRootmuxFtmRef1m = 6U, /*!< FTM Clock from Refernece Clock 1M.*/ + ccmRootmuxFtmVideoPll = 7U, /*!< FTM Clock from VIDEO PLL.*/ +}; + +/*! @brief Clock source enumeration for GPT peripheral. */ +enum _ccm_rootmux_gpt +{ + ccmRootmuxGptOsc24m = 0U, /*!< GPT Clock from OSC 24M.*/ + ccmRootmuxGptEnetPll100m = 1U, /*!< GPT Clock from Ethernet PLL 100M.*/ + ccmRootmuxGptSysPllPfd0 = 2U, /*!< GPT Clock from SYSTEM PLL PFD0.*/ + ccmRootmuxGptEnetPll40m = 3U, /*!< GPT Clock from Ethernet PLL 40M.*/ + ccmRootmuxGptVideoPll = 4U, /*!< GPT Clock from VIDEO PLL.*/ + ccmRootmuxGptRef1m = 5U, /*!< GPT Clock from Refernece Clock 1M.*/ + ccmRootmuxGptAudioPll = 6U, /*!< GPT Clock from AUDIO PLL.*/ + ccmRootmuxGptExtClk = 7U, /*!< GPT Clock from External Clock.*/ +}; + +/*! @brief Clock source enumeration for WDOG peripheral. */ +enum _ccm_rootmux_wdog +{ + ccmRootmuxWdogOsc24m = 0U, /*!< WDOG Clock from OSC 24M.*/ + ccmRootmuxWdogSysPllPfd2Div2 = 1U, /*!< WDOG Clock from SYSTEM PLL PFD2 divided by 2.*/ + ccmRootmuxWdogSysPllDiv4 = 2U, /*!< WDOG Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxWdogDdrPllDiv2 = 3U, /*!< WDOG Clock from DDR PLL divided by 2.*/ + ccmRootmuxWdogEnetPll125m = 4U, /*!< WDOG Clock from Ethernet PLL 125M.*/ + ccmRootmuxWdogUsbPll = 5U, /*!< WDOG Clock from USB PLL.*/ + ccmRootmuxWdogRef1m = 6U, /*!< WDOG Clock from Refernece Clock 1M.*/ + ccmRootmuxWdogSysPllPfd1Div2 = 7U, /*!< WDOG Clock from SYSTEM PLL PFD1 divided by 2.*/ +}; + +/*! @brief CCM PLL gate control. */ +enum _ccm_pll_gate +{ + ccmPllGateCkil = (uint32_t)(&CCM_PLL_CTRL0), /*!< Ckil PLL Gate.*/ + ccmPllGateArm = (uint32_t)(&CCM_PLL_CTRL1), /*!< ARM PLL Gate.*/ + ccmPllGateArmDiv1 = (uint32_t)(&CCM_PLL_CTRL2), /*!< ARM PLL Div1 Gate.*/ + ccmPllGateDdr = (uint32_t)(&CCM_PLL_CTRL3), /*!< DDR PLL Gate.*/ + ccmPllGateDdrDiv1 = (uint32_t)(&CCM_PLL_CTRL4), /*!< DDR PLL Div1 Gate.*/ + ccmPllGateDdrDiv2 = (uint32_t)(&CCM_PLL_CTRL5), /*!< DDR PLL Div2 Gate.*/ + ccmPllGateSys = (uint32_t)(&CCM_PLL_CTRL6), /*!< SYSTEM PLL Gate.*/ + ccmPllGateSysDiv1 = (uint32_t)(&CCM_PLL_CTRL7), /*!< SYSTEM PLL Div1 Gate.*/ + ccmPllGateSysDiv2 = (uint32_t)(&CCM_PLL_CTRL8), /*!< SYSTEM PLL Div2 Gate.*/ + ccmPllGateSysDiv4 = (uint32_t)(&CCM_PLL_CTRL9), /*!< SYSTEM PLL Div4 Gate.*/ + ccmPllGatePfd0 = (uint32_t)(&CCM_PLL_CTRL10), /*!< PFD0 Gate.*/ + ccmPllGatePfd0Div2 = (uint32_t)(&CCM_PLL_CTRL11), /*!< PFD0 Div2 Gate.*/ + ccmPllGatePfd1 = (uint32_t)(&CCM_PLL_CTRL12), /*!< PFD1 Gate.*/ + ccmPllGatePfd1Div2 = (uint32_t)(&CCM_PLL_CTRL13), /*!< PFD1 Div2 Gate.*/ + ccmPllGatePfd2 = (uint32_t)(&CCM_PLL_CTRL14), /*!< PFD2 Gate.*/ + ccmPllGatePfd2Div2 = (uint32_t)(&CCM_PLL_CTRL15), /*!< PDF2 Div2.*/ + ccmPllGatePfd3 = (uint32_t)(&CCM_PLL_CTRL16), /*!< PDF3 Gate.*/ + ccmPllGatePfd4 = (uint32_t)(&CCM_PLL_CTRL17), /*!< PDF4 Gate.*/ + ccmPllGatePfd5 = (uint32_t)(&CCM_PLL_CTRL18), /*!< PDF5 Gate.*/ + ccmPllGatePfd6 = (uint32_t)(&CCM_PLL_CTRL19), /*!< PDF6 Gate.*/ + ccmPllGatePfd7 = (uint32_t)(&CCM_PLL_CTRL20), /*!< PDF7 Gate.*/ + ccmPllGateEnet = (uint32_t)(&CCM_PLL_CTRL21), /*!< Ethernet PLL Gate.*/ + ccmPllGateEnet500m = (uint32_t)(&CCM_PLL_CTRL22), /*!< Ethernet 500M PLL Gate.*/ + ccmPllGateEnet250m = (uint32_t)(&CCM_PLL_CTRL23), /*!< Ethernet 250M PLL Gate.*/ + ccmPllGateEnet125m = (uint32_t)(&CCM_PLL_CTRL24), /*!< Ethernet 125M PLL Gate.*/ + ccmPllGateEnet100m = (uint32_t)(&CCM_PLL_CTRL25), /*!< Ethernet 100M PLL Gate.*/ + ccmPllGateEnet50m = (uint32_t)(&CCM_PLL_CTRL26), /*!< Ethernet 50M PLL Gate.*/ + ccmPllGateEnet40m = (uint32_t)(&CCM_PLL_CTRL27), /*!< Ethernet 40M PLL Gate.*/ + ccmPllGateEnet25m = (uint32_t)(&CCM_PLL_CTRL28), /*!< Ethernet 25M PLL Gate.*/ + ccmPllGateAudio = (uint32_t)(&CCM_PLL_CTRL29), /*!< AUDIO PLL Gate.*/ + ccmPllGateAudioDiv1 = (uint32_t)(&CCM_PLL_CTRL30), /*!< AUDIO PLL Div1 Gate.*/ + ccmPllGateVideo = (uint32_t)(&CCM_PLL_CTRL31), /*!< VIDEO PLL Gate.*/ + ccmPllGateVideoDiv1 = (uint32_t)(&CCM_PLL_CTRL32), /*!< VIDEO PLL Div1 Gate.*/ +}; + +/*! @brief CCM CCGR gate control. */ +enum _ccm_ccgr_gate +{ + ccmCcgrGateSimWakeup = (uint32_t)(&CCM_CCGR9), /*!< Wakeup Mix Bus Clock Gate.*/ + ccmCcgrGateIpmux1 = (uint32_t)(&CCM_CCGR10), /*!< IOMUX1 Clock Gate.*/ + ccmCcgrGateIpmux2 = (uint32_t)(&CCM_CCGR11), /*!< IOMUX2 Clock Gate.*/ + ccmCcgrGateIpmux3 = (uint32_t)(&CCM_CCGR12), /*!< IPMUX3 Clock Gate.*/ + ccmCcgrGateOcram = (uint32_t)(&CCM_CCGR17), /*!< OCRAM Clock Gate.*/ + ccmCcgrGateOcramS = (uint32_t)(&CCM_CCGR18), /*!< OCRAM S Clock Gate.*/ + ccmCcgrGateQspi = (uint32_t)(&CCM_CCGR21), /*!< QSPI Clock Gate.*/ + ccmCcgrGateAdc = (uint32_t)(&CCM_CCGR32), /*!< ADC Clock Gate.*/ + ccmCcgrGateRdc = (uint32_t)(&CCM_CCGR38), /*!< RDC Clock Gate.*/ + ccmCcgrGateMu = (uint32_t)(&CCM_CCGR39), /*!< MU Clock Gate.*/ + ccmCcgrGateSemaHs = (uint32_t)(&CCM_CCGR40), /*!< SEMA HS Clock Gate.*/ + ccmCcgrGateSema1 = (uint32_t)(&CCM_CCGR64), /*!< SEMA1 Clock Gate.*/ + ccmCcgrGateSema2 = (uint32_t)(&CCM_CCGR65), /*!< SEMA2 Clock Gate.*/ + ccmCcgrGateCan1 = (uint32_t)(&CCM_CCGR116), /*!< CAN1 Clock Gate.*/ + ccmCcgrGateCan2 = (uint32_t)(&CCM_CCGR117), /*!< CAN2 Clock Gate.*/ + ccmCcgrGateEcspi1 = (uint32_t)(&CCM_CCGR120), /*!< ECSPI1 Clock Gate.*/ + ccmCcgrGateEcspi2 = (uint32_t)(&CCM_CCGR121), /*!< ECSPI2 Clock Gate.*/ + ccmCcgrGateEcspi3 = (uint32_t)(&CCM_CCGR122), /*!< ECSPI3 Clock Gate.*/ + ccmCcgrGateEcspi4 = (uint32_t)(&CCM_CCGR123), /*!< ECSPI4 Clock Gate.*/ + ccmCcgrGateGpt1 = (uint32_t)(&CCM_CCGR124), /*!< GPT1 Clock Gate.*/ + ccmCcgrGateGpt2 = (uint32_t)(&CCM_CCGR125), /*!< GPT2 Clock Gate.*/ + ccmCcgrGateGpt3 = (uint32_t)(&CCM_CCGR126), /*!< GPT3 Clock Gate.*/ + ccmCcgrGateGpt4 = (uint32_t)(&CCM_CCGR127), /*!< GPT4 Clock Gate.*/ + ccmCcgrGateI2c1 = (uint32_t)(&CCM_CCGR136), /*!< I2C1 Clock Gate.*/ + ccmCcgrGateI2c2 = (uint32_t)(&CCM_CCGR137), /*!< I2C2 Clock Gate.*/ + ccmCcgrGateI2c3 = (uint32_t)(&CCM_CCGR138), /*!< I2C3 Clock Gate.*/ + ccmCcgrGateI2c4 = (uint32_t)(&CCM_CCGR139), /*!< I2C4 Clock Gate.*/ + ccmCcgrGateUart1 = (uint32_t)(&CCM_CCGR148), /*!< UART1 Clock Gate.*/ + ccmCcgrGateUart2 = (uint32_t)(&CCM_CCGR149), /*!< UART2 Clock Gate.*/ + ccmCcgrGateUart3 = (uint32_t)(&CCM_CCGR150), /*!< UART3 Clock Gate.*/ + ccmCcgrGateUart4 = (uint32_t)(&CCM_CCGR151), /*!< UART4 Clock Gate.*/ + ccmCcgrGateUart5 = (uint32_t)(&CCM_CCGR152), /*!< UART5 Clock Gate.*/ + ccmCcgrGateUart6 = (uint32_t)(&CCM_CCGR153), /*!< UART6 Clock Gate.*/ + ccmCcgrGateUart7 = (uint32_t)(&CCM_CCGR154), /*!< UART7 Clock Gate.*/ + ccmCcgrGateWdog1 = (uint32_t)(&CCM_CCGR156), /*!< WDOG1 Clock Gate.*/ + ccmCcgrGateWdog2 = (uint32_t)(&CCM_CCGR157), /*!< WDOG2 Clock Gate.*/ + ccmCcgrGateWdog3 = (uint32_t)(&CCM_CCGR158), /*!< WDOG3 Clock Gate.*/ + ccmCcgrGateWdog4 = (uint32_t)(&CCM_CCGR159), /*!< WDOG4 Clock Gate.*/ + ccmCcgrGateGpio1 = (uint32_t)(&CCM_CCGR160), /*!< GPIO1 Clock Gate.*/ + ccmCcgrGateGpio2 = (uint32_t)(&CCM_CCGR161), /*!< GPIO2 Clock Gate.*/ + ccmCcgrGateGpio3 = (uint32_t)(&CCM_CCGR162), /*!< GPIO3 Clock Gate.*/ + ccmCcgrGateGpio4 = (uint32_t)(&CCM_CCGR163), /*!< GPIO4 Clock Gate.*/ + ccmCcgrGateGpio5 = (uint32_t)(&CCM_CCGR164), /*!< GPIO5 Clock Gate.*/ + ccmCcgrGateGpio6 = (uint32_t)(&CCM_CCGR165), /*!< GPIO6 Clock Gate.*/ + ccmCcgrGateGpio7 = (uint32_t)(&CCM_CCGR166), /*!< GPIO7 Clock Gate.*/ + ccmCcgrGateIomux = (uint32_t)(&CCM_CCGR168), /*!< IOMUX Clock Gate.*/ + ccmCcgrGateIomuxLpsr = (uint32_t)(&CCM_CCGR169), /*!< IOMUX LPSR Clock Gate.*/ +}; + +/*! @brief CCM gate control value. */ +enum _ccm_gate_value +{ + ccmClockNotNeeded = 0x0U, /*!< Clock always disabled.*/ + ccmClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/ + ccmClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/ + ccmClockNeededAll = 0x3333U, /*!< Clock always enabled.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Root Setting + * @{ + */ + +/*! + * @brief Set clock root mux + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param mux Root mux value (see @ref _ccm_rootmux_xxx enumeration) + */ +static inline void CCM_SetRootMux(CCM_Type * base, uint32_t ccmRoot, uint32_t mux) +{ + CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & (~CCM_TARGET_ROOT_MUX_MASK)) | + CCM_TARGET_ROOT_MUX(mux); +} + +/*! + * @brief Get clock root mux + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @return root mux value (see @ref _ccm_rootmux_xxx enumeration) + */ +static inline uint32_t CCM_GetRootMux(CCM_Type * base, uint32_t ccmRoot) +{ + return (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; +} + +/*! + * @brief Enable clock root + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + */ +static inline void CCM_EnableRoot(CCM_Type * base, uint32_t ccmRoot) +{ + CCM_REG_SET(ccmRoot) = CCM_TARGET_ROOT_SET_ENABLE_MASK; +} + +/*! + * @brief Disable clock root + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + */ +static inline void CCM_DisableRoot(CCM_Type * base, uint32_t ccmRoot) +{ + CCM_REG_CLR(ccmRoot) = CCM_TARGET_ROOT_CLR_ENABLE_MASK; +} + +/*! + * @brief Check whether clock root is enabled + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @return CCM root enabled or not. + * - true: Clock root is enabled. + * - false: Clock root is disabled. + */ +static inline bool CCM_IsRootEnabled(CCM_Type * base, uint32_t ccmRoot) +{ + return (bool)(CCM_REG(ccmRoot) & CCM_TARGET_ROOT_ENABLE_MASK); +} + +/*! + * @brief Set root clock divider + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param pre Pre divider value (0-7, divider=n+1) + * @param post Post divider value (0-63, divider=n+1) + */ +void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t pre, uint32_t post); + +/*! + * @brief Get root clock divider + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param pre Pointer to pre divider value store address + * @param post Pointer to post divider value store address + */ +void CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t *pre, uint32_t *post); + +/*! + * @brief Update clock root in one step, for dynamical clock switching + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param root mux value (see @ref _ccm_rootmux_xxx enumeration) + * @param pre Pre divider value (0-7, divider=n+1) + * @param post Post divider value (0-63, divider=n+1) + */ +void CCM_UpdateRoot(CCM_Type * base, uint32_t ccmRoot, uint32_t mux, uint32_t pre, uint32_t post); + +/*@}*/ + +/*! + * @name CCM Gate Control + * @{ + */ + +/*! + * @brief Set PLL or CCGR gate control + * + * @param base CCM base pointer. + * @param ccmGate Gate control (see @ref _ccm_pll_gate and @ref _ccm_ccgr_gate enumeration) + * @param control Gate control value (see @ref _ccm_gate_value) + */ +static inline void CCM_ControlGate(CCM_Type * base, uint32_t ccmGate, uint32_t control) +{ + CCM_REG(ccmGate) = control; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CCM_IMX7D_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ecspi.c b/zephyr/imx/drivers/ecspi.c new file mode 100644 index 000000000..2a3a0c163 --- /dev/null +++ b/zephyr/imx/drivers/ecspi.c @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ecspi.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * eCSPI Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_Init + * Description : Initializes the eCSPI module according to the specified + * parameters in the initConfig. + * + *END**************************************************************************/ +void ECSPI_Init(ECSPI_Type* base, const ecspi_init_config_t* initConfig) +{ + /* Disable eCSPI module */ + ECSPI_CONREG_REG(base) = 0; + + /* Enable the eCSPI module before write to other registers */ + ECSPI_Enable(base); + + /* eCSPI CONREG Configuration */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_BURST_LENGTH(initConfig->burstLength) | + ECSPI_CONREG_CHANNEL_SELECT(initConfig->channelSelect); + ECSPI_CONREG_REG(base) |= initConfig->ecspiAutoStart ? ECSPI_CONREG_SMC_MASK : 0; + + /* eCSPI CONFIGREG Configuration */ + ECSPI_CONFIGREG_REG(base) = ECSPI_CONFIGREG_SCLK_PHA(((initConfig->clockPhase) & 1) << (initConfig->channelSelect)) | + ECSPI_CONFIGREG_SCLK_POL(((initConfig->clockPolarity) & 1) << (initConfig->channelSelect)); + + /* Master or Slave mode Configuration */ + if(initConfig->mode == ecspiMasterMode) + { + /* Set baud rate in bits per second */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_CHANNEL_MODE(1 << (initConfig->channelSelect)); + ECSPI_SetBaudRate(base, initConfig->clockRate, initConfig->baudRate); + } + else + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_CHANNEL_MODE(1 << (initConfig->channelSelect)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetSampClockSource + * Description : Configure the clock source for the sample period counter. + * + *END**************************************************************************/ +void ECSPI_SetSampClockSource(ECSPI_Type* base, uint32_t source) +{ + /* Select the clock source */ + if(source == ecspiSclk) + ECSPI_PERIODREG_REG(base) &= ~ECSPI_PERIODREG_CSRC_MASK; + else + ECSPI_PERIODREG_REG(base) |= ECSPI_PERIODREG_CSRC_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetBaudRate + * Description : Calculated the eCSPI baud rate in bits per second. + * + *END**************************************************************************/ +uint32_t ECSPI_SetBaudRate(ECSPI_Type* base, uint32_t sourceClockInHz, uint32_t bitsPerSec) +{ + uint32_t div, pre_div; + uint32_t post_baud; /* baud rate after post divider */ + uint32_t pre_baud; /* baud rate before pre divider */ + + if(sourceClockInHz <= bitsPerSec) + { + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_PRE_DIVIDER_MASK; + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_POST_DIVIDER_MASK; + return sourceClockInHz; + } + + div = sourceClockInHz / bitsPerSec; + if(div < 16) /* pre_divider is enough */ + { + if((sourceClockInHz - bitsPerSec * div) < ((bitsPerSec * (div + 1)) - sourceClockInHz)) + pre_div = div - 1; /* pre_divider value is one less than the real divider */ + else + pre_div = div; + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_PRE_DIVIDER_MASK)) | + ECSPI_CONREG_PRE_DIVIDER(pre_div); + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_POST_DIVIDER_MASK)) | + ECSPI_CONREG_POST_DIVIDER(0); + return sourceClockInHz / (pre_div + 1); + } + + pre_baud = bitsPerSec * 16; + for(div = 1; div < 16; div++) + { + post_baud = sourceClockInHz >> div; + if(post_baud < pre_baud) + break; + } + + if(div == 16) /* divider is not enough, set the biggest ones */ + { + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_PRE_DIVIDER(15); + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_POST_DIVIDER(15); + return post_baud / 16; + } + + /* find the closed one */ + if((post_baud - bitsPerSec * (post_baud / bitsPerSec)) < ((bitsPerSec * ((post_baud / bitsPerSec) + 1)) - post_baud)) + pre_div = post_baud / bitsPerSec - 1; + else + pre_div = post_baud / bitsPerSec; + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_PRE_DIVIDER_MASK)) | + ECSPI_CONREG_PRE_DIVIDER(pre_div); + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_POST_DIVIDER_MASK)) | + ECSPI_CONREG_POST_DIVIDER(div); + return post_baud / (pre_div + 1); +} + +/******************************************************************************* + * DMA management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetDMACmd + * Description : Enable or disable the specified DMA Source. + * + *END**************************************************************************/ +void ECSPI_SetDMACmd(ECSPI_Type* base, uint32_t source, bool enable) +{ + /* Configure the DAM source */ + if(enable) + ECSPI_DMAREG_REG(base) |= ((uint32_t)(1 << source)); + else + ECSPI_DMAREG_REG(base) &= ~((uint32_t)(1 << source)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetFIFOThreshold + * Description : Set the RXFIFO or TXFIFO threshold. + * + *END**************************************************************************/ +void ECSPI_SetFIFOThreshold(ECSPI_Type* base, uint32_t fifo, uint32_t threshold) +{ + /* configure the RXFIFO and TXFIFO threshold that can triggers a DMA/INT request */ + if(fifo == ecspiTxfifoThreshold) + ECSPI_DMAREG_REG(base) = (ECSPI_DMAREG_REG(base) & (~ECSPI_DMAREG_TX_THRESHOLD_MASK)) | + ECSPI_DMAREG_TX_THRESHOLD(threshold); + else + ECSPI_DMAREG_REG(base) = (ECSPI_DMAREG_REG(base) & (~ECSPI_DMAREG_RX_THRESHOLD_MASK)) | + ECSPI_DMAREG_RX_THRESHOLD(threshold); +} + +/******************************************************************************* + * Interrupts and flags management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetIntCmd + * Description : Enable or disable eCSPI interrupts. + * + *END**************************************************************************/ +void ECSPI_SetIntCmd(ECSPI_Type* base, uint32_t flags, bool enable) +{ + /* Configure the Interrupt source */ + if(enable) + ECSPI_INTREG_REG(base) |= flags; + else + ECSPI_INTREG_REG(base) &= ~flags; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/ecspi.h b/zephyr/imx/drivers/ecspi.h new file mode 100644 index 000000000..952ae14bb --- /dev/null +++ b/zephyr/imx/drivers/ecspi.h @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ECSPI_H__ +#define __ECSPI_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ecspi_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Channel select. */ +enum _ecspi_channel_select +{ + ecspiSelectChannel0 = 0U, /*!< Select Channel 0. Chip Select 0 (SS0) is asserted.*/ + ecspiSelectChannel1 = 1U, /*!< Select Channel 1. Chip Select 1 (SS1) is asserted.*/ + ecspiSelectChannel2 = 2U, /*!< Select Channel 2. Chip Select 2 (SS2) is asserted.*/ + ecspiSelectChannel3 = 3U, /*!< Select Channel 3. Chip Select 3 (SS3) is asserted.*/ +}; + +/*! @brief Channel mode. */ +enum _ecspi_master_slave_mode +{ + ecspiSlaveMode = 0U, /*!< Set Slave Mode.*/ + ecspiMasterMode = 1U, /*!< Set Master Mode.*/ +}; + +/*! @brief Clock phase. */ +enum _ecspi_clock_phase +{ + ecspiClockPhaseFirstEdge = 0U, /*!< Data is captured on the leading edge of the SCK and + changed on the following edge.*/ + ecspiClockPhaseSecondEdge = 1U, /*!< Data is changed on the leading edge of the SCK and + captured on the following edge.*/ +}; + +/*! @brief Clock polarity. */ +enum _ecspi_clock_polarity +{ + ecspiClockPolarityActiveHigh = 0U, /*!< Active-high eCSPI clock (idles low).*/ + ecspiClockPolarityActiveLow = 1U, /*!< Active-low eCSPI clock (idles high).*/ +}; + +/*! @brief SS signal polarity. */ +enum _ecspi_ss_polarity +{ + ecspiSSPolarityActiveLow = 0U, /*!< Active-low, eCSPI SS signal.*/ + ecspiSSPolarityActiveHigh = 1U, /*!< Active-high, eCSPI SS signal.*/ +}; + +/*! @brief Inactive state of data line. */ +enum _ecspi_dataline_inactivestate +{ + ecspiDataLineStayHigh = 0U, /*!< Data line inactive state stay high.*/ + ecspiDataLineStayLow = 1U, /*!< Data line inactive state stay low.*/ +}; + +/*! @brief Inactive state of SCLK. */ +enum _ecspi_sclk_inactivestate +{ + ecspiSclkStayLow = 0U, /*!< SCLK inactive state stay low.*/ + ecspiSclkStayHigh = 1U, /*!< SCLK line inactive state stay high.*/ +}; + +/*! @brief sample period counter clock source. */ +enum _ecspi_sampleperiod_clocksource +{ + ecspiSclk = 0U, /*!< Sample period counter clock from SCLK.*/ + ecspiLowFreq32K = 1U, /*!< Sample period counter clock from from LFRC (32.768 KHz).*/ +}; + +/*! @brief DMA Source definition. */ +enum _ecspi_dma_source +{ + ecspiDmaTxfifoEmpty = 7U, /*!< TXFIFO Empty DMA Request.*/ + ecspiDmaRxfifoRequest = 23U, /*!< RXFIFO DMA Request.*/ + ecspiDmaRxfifoTail = 31U, /*!< RXFIFO TAIL DMA Request.*/ +}; + +/*! @brief RXFIFO and TXFIFO threshold. */ +enum _ecspi_fifothreshold +{ + ecspiTxfifoThreshold = 0U, /*!< Defines the FIFO threshold that triggers a TX DMA/INT request.*/ + ecspiRxfifoThreshold = 16U, /*!< defines the FIFO threshold that triggers a RX DMA/INT request.*/ +}; + +/*! @brief Status flag. */ +enum _ecspi_status_flag +{ + ecspiFlagTxfifoEmpty = 1U << 0, /*!< TXFIFO Empty Flag.*/ + ecspiFlagTxfifoDataRequest = 1U << 1, /*!< TXFIFO Data Request Flag.*/ + ecspiFlagTxfifoFull = 1U << 2, /*!< TXFIFO Full Flag.*/ + ecspiFlagRxfifoReady = 1U << 3, /*!< RXFIFO Ready Flag.*/ + ecspiFlagRxfifoDataRequest = 1U << 4, /*!< RXFIFO Data Request Flag.*/ + ecspiFlagRxfifoFull = 1U << 5, /*!< RXFIFO Full Flag.*/ + ecspiFlagRxfifoOverflow = 1U << 6, /*!< RXFIFO Overflow Flag.*/ + ecspiFlagTxfifoTc = 1U << 7, /*!< TXFIFO Transform Completed Flag.*/ +}; + +/*! @brief Data Ready Control. */ +enum _ecspi_data_ready +{ + ecspiRdyNoCare = 0U, /*!< The SPI_RDY signal is ignored.*/ + ecspiRdyFallEdgeTrig = 1U, /*!< Burst is triggered by the falling edge of the SPI_RDY signal (edge-triggered).*/ + ecspiRdyLowLevelTrig = 2U, /*!< Burst is triggered by a low level of the SPI_RDY signal (level-triggered).*/ + ecspiRdyReserved = 3U, /*!< Reserved.*/ +}; + +/*! @brief Init structure. */ +typedef struct _ecspi_init_config +{ + uint32_t clockRate; /*!< Specifies ECSPII module clock freq.*/ + uint32_t baudRate; /*!< Specifies desired eCSPI baud rate.*/ + uint32_t channelSelect; /*!< Specifies the channel select.*/ + uint32_t mode; /*!< Specifies the mode.*/ + uint32_t burstLength; /*!< Specifies the length of a burst to be transferred.*/ + uint32_t clockPhase; /*!< Specifies the clock phase.*/ + uint32_t clockPolarity; /*!< Specifies the clock polarity.*/ + bool ecspiAutoStart; /*!< Specifies the start mode.*/ +} ecspi_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eCSPI Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the eCSPI module. + * + * @param base eCSPI base pointer. + * @param initConfig eCSPI initialization structure. + */ +void ECSPI_Init(ECSPI_Type* base, const ecspi_init_config_t* initConfig); + +/*! + * @brief Enables the specified eCSPI module. + * + * @param base eCSPI base pointer. + */ +static inline void ECSPI_Enable(ECSPI_Type* base) +{ + /* Enable the eCSPI. */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_EN_MASK; +} + +/*! + * @brief Disable the specified eCSPI module. + * + * @param base eCSPI base pointer. + */ +static inline void ECSPI_Disable(ECSPI_Type* base) +{ + /* Enable the eCSPI. */ + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_EN_MASK; +} + +/*! + * @brief Insert the number of wait states to be inserted in data transfers. + * + * @param base eCSPI base pointer. + * @param number the number of wait states. + */ +static inline void ECSPI_InsertWaitState(ECSPI_Type* base, uint32_t number) +{ + /* Configure the number of wait states inserted. */ + ECSPI_PERIODREG_REG(base) = (ECSPI_PERIODREG_REG(base) & (~ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)) | + ECSPI_PERIODREG_SAMPLE_PERIOD(number); +} + +/*! + * @brief Set the clock source for the sample period counter. + * + * @param base eCSPI base pointer. + * @param source The clock source (see @ref _ecspi_sampleperiod_clocksource enumeration). + */ +void ECSPI_SetSampClockSource(ECSPI_Type* base, uint32_t source); + +/*! + * @brief Set the eCSPI clocks insert between the chip select active edge + * and the first eCSPI clock edge. + * + * @param base eCSPI base pointer. + * @param delay The number of wait states. + */ +static inline void ECSPI_SetDelay(ECSPI_Type* base, uint32_t delay) +{ + /* Set the number of clocks insert. */ + ECSPI_PERIODREG_REG(base) = (ECSPI_PERIODREG_REG(base) & (~ECSPI_PERIODREG_CSD_CTL_MASK)) | + ECSPI_PERIODREG_CSD_CTL(delay); +} + +/*! + * @brief Set the inactive state of SCLK. + * + * @param base eCSPI base pointer. + * @param channel eCSPI channel select (see @ref _ecspi_channel_select enumeration). + * @param state SCLK inactive state (see @ref _ecspi_sclk_inactivestate enumeration). + */ +static inline void ECSPI_SetSCLKInactiveState(ECSPI_Type* base, uint32_t channel, uint32_t state) +{ + /* Configure the inactive state of SCLK. */ + ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SCLK_CTL(1 << channel))) | + ECSPI_CONFIGREG_SCLK_CTL((state & 1) << channel); +} + +/*! + * @brief Set the inactive state of data line. + * + * @param base eCSPI base pointer. + * @param channel eCSPI channel select (see @ref _ecspi_channel_select enumeration). + * @param state Data line inactive state (see @ref _ecspi_dataline_inactivestate enumeration). + */ +static inline void ECSPI_SetDataInactiveState(ECSPI_Type* base, uint32_t channel, uint32_t state) +{ + /* Set the inactive state of Data Line. */ + ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_DATA_CTL(1 << channel))) | + ECSPI_CONFIGREG_DATA_CTL((state & 1) << channel); +} + +/*! + * @brief Trigger a burst. + * + * @param base eCSPI base pointer. + */ +static inline void ECSPI_StartBurst(ECSPI_Type* base) +{ + /* Start a burst. */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_XCH_MASK; +} + +/*! + * @brief Set the burst length. + * + * @param base eCSPI base pointer. + * @param length The value of burst length. + */ +static inline void ECSPI_SetBurstLength(ECSPI_Type* base, uint32_t length) +{ + /* Set the burst length according to length. */ + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_BURST_LENGTH_MASK)) | + ECSPI_CONREG_BURST_LENGTH(length); +} + +/*! + * @brief Set eCSPI SS Wave Form. + * + * @param base eCSPI base pointer. + * @param channel eCSPI channel selected (see @ref _ecspi_channel_select enumeration). + * @param ssMultiBurst For master mode, set true for multiple burst and false for one burst. + * For slave mode, set true to complete burst by SS signal edges and false to complete + * burst by number of bits received. + */ +static inline void ECSPI_SetSSMultipleBurst(ECSPI_Type* base, uint32_t channel, bool ssMultiBurst) +{ + /* Set the SS wave form. */ + ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SS_CTL(1 << channel))) | + ECSPI_CONFIGREG_SS_CTL(ssMultiBurst << channel); +} + +/*! + * @brief Set eCSPI SS Polarity. + * + * @param base eCSPI base pointer. + * @param channel eCSPI channel selected (see @ref _ecspi_channel_select enumeration). + * @param polarity Set SS signal active logic (see @ref _ecspi_ss_polarity enumeration). + */ +static inline void ECSPI_SetSSPolarity(ECSPI_Type* base, uint32_t channel, uint32_t polarity) +{ + /* Set the SS polarity. */ + ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SS_POL(1 << channel))) | + ECSPI_CONFIGREG_SS_POL(polarity << channel); +} + +/*! + * @brief Set the Data Ready Control. + * + * @param base eCSPI base pointer. + * @param spidataready eCSPI data ready control (see @ref _ecspi_data_ready enumeration). + */ +static inline void ECSPI_SetSPIDataReady(ECSPI_Type* base, uint32_t spidataready) +{ + /* Set the Data Ready Control. */ + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_DRCTL_MASK)) | + ECSPI_CONREG_DRCTL(spidataready); +} + +/*! + * @brief Calculated the eCSPI baud rate in bits per second. + * The calculated baud rate must not exceed the desired baud rate. + * + * @param base eCSPI base pointer. + * @param sourceClockInHz eCSPI Clock(SCLK) (in Hz). + * @param bitsPerSec the value of Baud Rate. + * @return The calculated baud rate in bits-per-second, the nearest possible + * baud rate without exceeding the desired baud rate. + */ +uint32_t ECSPI_SetBaudRate(ECSPI_Type* base, uint32_t sourceClockInHz, uint32_t bitsPerSec); + +/*@}*/ + +/*! + * @name Data transfers functions + * @{ + */ + +/*! + * @brief Transmits a data to TXFIFO. + * + * @param base eCSPI base pointer. + * @param data Data to be transmitted. + */ +static inline void ECSPI_SendData(ECSPI_Type* base, uint32_t data) +{ + /* Write data to Transmit Data Register. */ + ECSPI_TXDATA_REG(base) = data; +} + +/*! + * @brief Receives a data from RXFIFO. + * + * @param base eCSPI base pointer. + * @return The value of received data. + */ +static inline uint32_t ECSPI_ReceiveData(ECSPI_Type* base) +{ + /* Read data from Receive Data Register. */ + return ECSPI_RXDATA_REG(base); +} + +/*! + * @brief Read the number of words in the RXFIFO. + * + * @param base eCSPI base pointer. + * @return The number of words in the RXFIFO. + */ +static inline uint32_t ECSPI_GetRxfifoCounter(ECSPI_Type* base) +{ + /* Get the number of words in the RXFIFO. */ + return ((ECSPI_TESTREG_REG(base) & ECSPI_TESTREG_RXCNT_MASK) >> ECSPI_TESTREG_RXCNT_SHIFT); +} + +/*! + * @brief Read the number of words in the TXFIFO. + * + * @param base eCSPI base pointer. + * @return The number of words in the TXFIFO. + */ +static inline uint32_t ECSPI_GetTxfifoCounter(ECSPI_Type* base) +{ + /* Get the number of words in the RXFIFO. */ + return ((ECSPI_TESTREG_REG(base) & ECSPI_TESTREG_TXCNT_MASK) >> ECSPI_TESTREG_TXCNT_SHIFT); +} + +/*@}*/ + +/*! + * @name DMA management functions + * @{ + */ + +/*! + * @brief Enable or disable the specified DMA Source. + * + * @param base eCSPI base pointer. + * @param source specifies DMA source (see @ref _ecspi_dma_source enumeration). + * @param enable Enable/Disable specified DMA Source. + * - true: Enable specified DMA Source. + * - false: Disable specified DMA Source. + */ +void ECSPI_SetDMACmd(ECSPI_Type* base, uint32_t source, bool enable); + +/*! + * @brief Set the burst length of a DMA operation. + * + * @param base eCSPI base pointer. + * @param length Specifies the burst length of a DMA operation. + */ +static inline void ECSPI_SetDMABurstLength(ECSPI_Type* base, uint32_t length) +{ + /* Configure the burst length of a DMA operation. */ + ECSPI_DMAREG_REG(base) = (ECSPI_DMAREG_REG(base) & (~ECSPI_DMAREG_RX_DMA_LENGTH_MASK)) | + ECSPI_DMAREG_RX_DMA_LENGTH(length); +} + +/*! + * @brief Set the RXFIFO or TXFIFO threshold. + * + * @param base eCSPI base pointer. + * @param fifo Data transfer FIFO (see @ref _ecspi_fifothreshold enumeration). + * @param threshold Threshold value. + */ +void ECSPI_SetFIFOThreshold(ECSPI_Type* base, uint32_t fifo, uint32_t threshold); + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Enable or disable the specified eCSPI interrupts. + * + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). + * @param enable Interrupt enable. + * - true: Enable specified eCSPI interrupts. + * - false: Disable specified eCSPI interrupts. + */ +void ECSPI_SetIntCmd(ECSPI_Type* base, uint32_t flags, bool enable); + +/*! + * @brief Checks whether the specified eCSPI flag is set or not. + * + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). + * @return eCSPI status, each bit represents one status flag. + */ +static inline uint32_t ECSPI_GetStatusFlag(ECSPI_Type* base, uint32_t flags) +{ + /* return the vale of eCSPI status. */ + return ECSPI_STATREG_REG(base) & flags; +} + +/*! + * @brief Clear one or more eCSPI status flag. + * + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). + */ +static inline void ECSPI_ClearStatusFlag(ECSPI_Type* base, uint32_t flags) +{ + /* Write 1 to the status bit. */ + ECSPI_STATREG_REG(base) = flags; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*__ECSPI_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/epit.c b/zephyr/imx/drivers/epit.c new file mode 100644 index 000000000..cf9aabdf6 --- /dev/null +++ b/zephyr/imx/drivers/epit.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "epit.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : EPIT_Init + * Description : Initializes the EPIT module according to the specified + * parameters in the initConfig. + * + *END**************************************************************************/ +void EPIT_Init(EPIT_Type* base, const epit_init_config_t* initConfig) +{ + assert(initConfig); + + EPIT_CR_REG(base) = 0; + + EPIT_SoftReset(base); + + EPIT_CR_REG(base) = (initConfig->freeRun ? EPIT_CR_RLD_MASK : 0) | + (initConfig->waitEnable ? EPIT_CR_WAITEN_MASK : 0) | + (initConfig->stopEnable ? EPIT_CR_STOPEN_MASK : 0) | + (initConfig->dbgEnable ? EPIT_CR_DBGEN_MASK : 0) | + (initConfig->enableMode ? EPIT_CR_ENMOD_MASK : 0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : EPIT_SetOverwriteCounter + * Description : Enable or disable EPIT overwrite counter immediately. + * + *END**************************************************************************/ +void EPIT_SetOverwriteCounter(EPIT_Type* base, bool enable) +{ + if(enable) + EPIT_CR_REG(base) |= EPIT_CR_IOVW_MASK; + else + EPIT_CR_REG(base) &= ~EPIT_CR_IOVW_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : EPIT_SetIntCmd + * Description : Enable or disable EPIT interrupt. + * + *END**************************************************************************/ +void EPIT_SetIntCmd(EPIT_Type* base, bool enable) +{ + if (enable) + EPIT_CR_REG(base) |= EPIT_CR_OCIEN_MASK; + else + EPIT_CR_REG(base) &= ~EPIT_CR_OCIEN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/epit.h b/zephyr/imx/drivers/epit.h new file mode 100644 index 000000000..dfe3f2ab8 --- /dev/null +++ b/zephyr/imx/drivers/epit.h @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EPIT_H__ +#define __EPIT_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup epit_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Clock source. */ +enum _epit_clock_source +{ + epitClockSourceOff = 0U, /*!< EPIT Clock Source Off.*/ + epitClockSourcePeriph = 1U, /*!< EPIT Clock Source from Peripheral Clock.*/ + epitClockSourceHighFreq = 2U, /*!< EPIT Clock Source from High Frequency Reference Clock.*/ + epitClockSourceLowFreq = 3U, /*!< EPIT Clock Source from Low Frequency Reference Clock.*/ +}; + +/*! @brief Output compare operation mode. */ +enum _epit_output_operation_mode +{ + epitOutputOperationDisconnected = 0U, /*!< EPIT Output Operation: Disconnected from pad.*/ + epitOutputOperationToggle = 1U, /*!< EPIT Output Operation: Toggle output pin.*/ + epitOutputOperationClear = 2U, /*!< EPIT Output Operation: Clear output pin.*/ + epitOutputOperationSet = 3U, /*!< EPIT Output Operation: Set putput pin.*/ +}; + +/*! @brief Structure to configure the running mode. */ +typedef struct _epit_init_config +{ + bool freeRun; /*!< true: set-and-forget mode, false: free-running mode. */ + bool waitEnable; /*!< EPIT enabled in wait mode. */ + bool stopEnable; /*!< EPIT enabled in stop mode. */ + bool dbgEnable; /*!< EPIT enabled in debug mode. */ + bool enableMode; /*!< true: counter starts counting from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0) when enabled, + false: counter restores the value that it was disabled when enabled. */ +} epit_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EPIT State Control + * @{ + */ + +/*! + * @brief Initialize EPIT to reset state and initialize running mode. + * + * @param base EPIT base pointer. + * @param initConfig EPIT initialize structure. + */ +void EPIT_Init(EPIT_Type* base, const epit_init_config_t* initConfig); + +/*! + * @brief Software reset of EPIT module. + * + * @param base EPIT base pointer. + */ +static inline void EPIT_SoftReset(EPIT_Type* base) +{ + EPIT_CR_REG(base) |= EPIT_CR_SWR_MASK; + /* Wait reset finished. */ + while (EPIT_CR_REG(base) & EPIT_CR_SWR_MASK) { } +} + +/*! + * @brief Set clock source of EPIT. + * + * @param base EPIT base pointer. + * @param source clock source (see @ref _epit_clock_source enumeration). + */ +static inline void EPIT_SetClockSource(EPIT_Type* base, uint32_t source) +{ + EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_CLKSRC_MASK) | EPIT_CR_CLKSRC(source); +} + +/*! + * @brief Get clock source of EPIT. + * + * @param base EPIT base pointer. + * @return clock source (see @ref _epit_clock_source enumeration). + */ +static inline uint32_t EPIT_GetClockSource(EPIT_Type* base) +{ + return (EPIT_CR_REG(base) & EPIT_CR_CLKSRC_MASK) >> EPIT_CR_CLKSRC_SHIFT; +} + +/*! + * @brief Set pre scaler of EPIT. + * + * @param base EPIT base pointer. + * @param prescaler Pre-scaler of EPIT (0-4095, divider = prescaler + 1). + */ +static inline void EPIT_SetPrescaler(EPIT_Type* base, uint32_t prescaler) +{ + assert(prescaler <= (EPIT_CR_PRESCALAR_MASK >> EPIT_CR_PRESCALAR_SHIFT)); + EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_PRESCALAR_MASK) | EPIT_CR_PRESCALAR(prescaler); +} + +/*! + * @brief Get pre scaler of EPIT. + * + * @param base EPIT base pointer. + * @return Pre-scaler of EPIT (0-4095). + */ +static inline uint32_t EPIT_GetPrescaler(EPIT_Type* base) +{ + return (EPIT_CR_REG(base) & EPIT_CR_PRESCALAR_MASK) >> EPIT_CR_PRESCALAR_SHIFT; +} + +/*! + * @brief Enable EPIT module. + * + * @param base EPIT base pointer. + */ +static inline void EPIT_Enable(EPIT_Type* base) +{ + EPIT_CR_REG(base) |= EPIT_CR_EN_MASK; +} + +/*! + * @brief Disable EPIT module. + * + * @param base EPIT base pointer. + */ +static inline void EPIT_Disable(EPIT_Type* base) +{ + EPIT_CR_REG(base) &= ~EPIT_CR_EN_MASK; +} + +/*! + * @brief Get EPIT counter value. + * + * @param base EPIT base pointer. + * @return EPIT counter value. + */ +static inline uint32_t EPIT_ReadCounter(EPIT_Type* base) +{ + return EPIT_CNR_REG(base); +} + +/*@}*/ + +/*! + * @name EPIT Output Signal Control + * @{ + */ + +/*! + * @brief Set EPIT output compare operation mode. + * + * @param base EPIT base pointer. + * @param mode EPIT output compare operation mode (see @ref _epit_output_operation_mode enumeration). + */ +static inline void EPIT_SetOutputOperationMode(EPIT_Type* base, uint32_t mode) +{ + EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_OM_MASK) | EPIT_CR_OM(mode); +} + +/*! + * @brief Get EPIT output compare operation mode. + * + * @param base EPIT base pointer. + * @return EPIT output operation mode (see @ref _epit_output_operation_mode enumeration). + */ +static inline uint32_t EPIT_GetOutputOperationMode(EPIT_Type* base) +{ + return (EPIT_CR_REG(base) & EPIT_CR_OM_MASK) >> EPIT_CR_OM_SHIFT; +} + +/*! + * @brief Set EPIT output compare value. + * + * @param base EPIT base pointer. + * @param value EPIT output compare value. + */ +static inline void EPIT_SetOutputCompareValue(EPIT_Type* base, uint32_t value) +{ + EPIT_CMPR_REG(base) = value; +} + +/*! + * @brief Get EPIT output compare value. + * + * @param base EPIT base pointer. + * @return EPIT output compare value. + */ +static inline uint32_t EPIT_GetOutputCompareValue(EPIT_Type* base) +{ + return EPIT_CMPR_REG(base); +} + +/*@}*/ + +/*! + * @name EPIT Data Load Control + * @{ + */ + +/*! + * @brief Set the value that is to be loaded into counter register. + * + * @param base EPIT base pointer. + * @param value Counter load value. + */ +static inline void EPIT_SetCounterLoadValue(EPIT_Type* base, uint32_t value) +{ + EPIT_LR_REG(base) = value; +} + +/*! + * @brief Get the value that loaded into counter register. + * + * @param base EPIT base pointer. + * @return The counter load value. + */ +static inline uint32_t EPIT_GetCounterLoadValue(EPIT_Type* base) +{ + return EPIT_LR_REG(base); +} + +/*! + * @brief Enable or disable EPIT overwrite counter immediately. + * + * @param base EPIT base pointer. + * @param enable Enable/Disable EPIT overwrite counter immediately. + * - true: Enable overwrite counter immediately. + * - false: Disable overwrite counter immediately. + */ +void EPIT_SetOverwriteCounter(EPIT_Type* base, bool enable); + +/*@}*/ + +/*! + * @name EPIT Interrupt and Status Control + * @{ + */ + +/*! + * @brief Get EPIT status of output compare interrupt flag. + * + * @param base EPIT base pointer. + * @return EPIT status of output compare interrupt flag. + */ +static inline uint32_t EPIT_GetStatusFlag(EPIT_Type* base) +{ + return EPIT_SR_REG(base) & EPIT_SR_OCIF_MASK; +} + +/*! + * @brief Clear EPIT Output compare interrupt flag. + * + * @param base EPIT base pointer. + */ +static inline void EPIT_ClearStatusFlag(EPIT_Type* base) +{ + EPIT_SR_REG(base) = EPIT_SR_OCIF_MASK; +} + +/*! + * @brief Enable or disable EPIT interrupt. + * + * @param base EPIT base pointer. + * @param enable Enable/Disable EPIT interrupt. + * - true: Enable interrupt. + * - false: Disable interrupt. + */ +void EPIT_SetIntCmd(EPIT_Type* base, bool enable); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*__EPIT_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/flexcan.c b/zephyr/imx/drivers/flexcan.c new file mode 100644 index 000000000..bd9290a81 --- /dev/null +++ b/zephyr/imx/drivers/flexcan.c @@ -0,0 +1,1073 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "flexcan.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT (31U) /*! format A&B RTR mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT (30U) /*! format A&B IDE mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT (15U) /*! format B RTR-2 mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT (14U) /*! format B IDE-2 mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK (0x3FFFFFFFU) /*! format A extended mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT (1U) /*! format A extended shift.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK (0x3FF80000U) /*! format A standard mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT (19U) /*! format A standard shift.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK (0x3FFFU) /*! format B extended mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1 (16U) /*! format B extended mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2 (0U) /*! format B extended mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK (0x7FFU) /*! format B standard mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1 (19U) /*! format B standard shift1.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2 (3U) /*! format B standard shift2.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK (0xFFU) /*! format C mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1 (24U) /*! format C shift1.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2 (16U) /*! format C shift2.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3 (8U) /*! format C shift3.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4 (0U) /*! format C shift4.*/ +#define FLEXCAN_BYTE_DATA_FIELD_MASK (0xFFU) /*! masks for byte data field.*/ +#define RxFifoFilterElementNum(x) ((x + 1) * 8) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * FLEXCAN Freeze control function + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_EnterFreezeMode + * Description : Set FlexCAN module enter freeze mode. + * + *END**************************************************************************/ +static void FLEXCAN_EnterFreezeMode(CAN_Type* base) +{ + /* Set Freeze, Halt */ + CAN_MCR_REG(base) |= CAN_MCR_FRZ_MASK; + CAN_MCR_REG(base) |= CAN_MCR_HALT_MASK; + /* Wait for entering the freeze mode */ + while (!(CAN_MCR_REG(base) & CAN_MCR_FRZ_ACK_MASK)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_ExitFreezeMode + * Description : Set FlexCAN module exit freeze mode. + * + *END**************************************************************************/ +static void FLEXCAN_ExitFreezeMode(CAN_Type* base) +{ + /* De-assert Freeze Mode */ + CAN_MCR_REG(base) &= ~CAN_MCR_HALT_MASK; + CAN_MCR_REG(base) &= ~CAN_MCR_FRZ_MASK; + /* Wait for exit the freeze mode */ + while (CAN_MCR_REG(base) & CAN_MCR_FRZ_ACK_MASK); +} + +/******************************************************************************* + * FlexCAN Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_Init + * Description : Initialize Flexcan module with given initialize structure. + * + *END**************************************************************************/ +void FLEXCAN_Init(CAN_Type* base, const flexcan_init_config_t* initConfig) +{ + assert(initConfig); + + /* Enable Flexcan module */ + FLEXCAN_Enable(base); + + /* Reset Flexcan module register content to default value */ + FLEXCAN_Deinit(base); + + /* Set maximum MessageBox numbers and + * Initialize all message buffers as inactive + */ + FLEXCAN_SetMaxMsgBufNum(base, initConfig->maxMsgBufNum); + + /* Initialize Flexcan module timing character */ + FLEXCAN_SetTiming(base, &initConfig->timing); + + /* Set desired operating mode */ + FLEXCAN_SetOperatingMode(base, initConfig->operatingMode); + + /* Disable Flexcan module */ + FLEXCAN_Disable(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_Deinit + * Description : This function reset Flexcan module register content to its + * default value. + * + *END**************************************************************************/ +void FLEXCAN_Deinit(CAN_Type* base) +{ + uint32_t i; + + /* Reset the FLEXCAN module */ + CAN_MCR_REG(base) |= CAN_MCR_SOFT_RST_MASK; + /* Wait for reset cycle to complete */ + while (CAN_MCR_REG(base) & CAN_MCR_SOFT_RST_MASK); + + /* Assert Flexcan module Freeze */ + FLEXCAN_EnterFreezeMode(base); + + /* Reset CTRL1 Register */ + CAN_CTRL1_REG(base) = 0x0; + + /* Reset CTRL2 Register */ + CAN_CTRL2_REG(base) = 0x0; + + /* Reset All Message Buffer Content */ + for (i = 0; i < CAN_CS_COUNT; i++) + { + base->MB[i].CS = 0x0; + base->MB[i].ID = 0x0; + base->MB[i].WORD0 = 0x0; + base->MB[i].WORD1 = 0x0; + } + + /* Reset Rx Individual Mask */ + for (i = 0; i < CAN_RXIMR_COUNT; i++) + CAN_RXIMR_REG(base, i) = 0x0; + + /* Reset Rx Mailboxes Global Mask */ + CAN_RXMGMASK_REG(base) = 0xFFFFFFFF; + + /* Reset Rx Buffer 14 Mask */ + CAN_RX14MASK_REG(base) = 0xFFFFFFFF; + + /* Reset Rx Buffer 15 Mask */ + CAN_RX15MASK_REG(base) = 0xFFFFFFFF; + + /* Rx FIFO Global Mask */ + CAN_RXFGMASK_REG(base) = 0xFFFFFFFF; + + /* Disable all MB interrupts */ + CAN_IMASK1_REG(base) = 0x0; + CAN_IMASK2_REG(base) = 0x0; + + // Clear all MB interrupt flags + CAN_IFLAG1_REG(base) = 0xFFFFFFFF; + CAN_IFLAG2_REG(base) = 0xFFFFFFFF; + + // Clear all Error interrupt flags + CAN_ESR1_REG(base) = 0xFFFFFFFF; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_Enable + * Description : This function is used to Enable the Flexcan Module. + * + *END**************************************************************************/ +void FLEXCAN_Enable(CAN_Type* base) +{ + /* Enable clock */ + CAN_MCR_REG(base) &= ~CAN_MCR_MDIS_MASK; + /* Wait until enabled */ + while (CAN_MCR_REG(base) & CAN_MCR_LPM_ACK_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_Disable + * Description : This function is used to Disable the CAN Module. + * + *END**************************************************************************/ +void FLEXCAN_Disable(CAN_Type* base) +{ + /* Disable clock*/ + CAN_MCR_REG(base) |= CAN_MCR_MDIS_MASK; + /* Wait until disabled */ + while (!(CAN_MCR_REG(base) & CAN_MCR_LPM_ACK_MASK)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetTiming + * Description : Sets the FlexCAN time segments for setting up bit rate. + * + *END**************************************************************************/ +void FLEXCAN_SetTiming(CAN_Type* base, const flexcan_timing_t* timing) +{ + assert(timing); + + /* Assert Flexcan module Freeze */ + FLEXCAN_EnterFreezeMode(base); + + /* Set Flexcan module Timing Character */ + CAN_CTRL1_REG(base) &= ~(CAN_CTRL1_PRESDIV_MASK | \ + CAN_CTRL1_RJW_MASK | \ + CAN_CTRL1_PSEG1_MASK | \ + CAN_CTRL1_PSEG2_MASK | \ + CAN_CTRL1_PROP_SEG_MASK); + CAN_CTRL1_REG(base) |= (CAN_CTRL1_PRESDIV(timing->preDiv) | \ + CAN_CTRL1_RJW(timing->rJumpwidth) | \ + CAN_CTRL1_PSEG1(timing->phaseSeg1) | \ + CAN_CTRL1_PSEG2(timing->phaseSeg2) | \ + CAN_CTRL1_PROP_SEG(timing->propSeg)); + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetOperatingMode + * Description : Set operation mode. + * + *END**************************************************************************/ +void FLEXCAN_SetOperatingMode(CAN_Type* base, uint8_t mode) +{ + assert((mode & flexcanNormalMode) || + (mode & flexcanListenOnlyMode) || + (mode & flexcanLoopBackMode)); + + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + if (mode & flexcanNormalMode) + CAN_MCR_REG(base) &= ~CAN_MCR_SUPV_MASK; + else + CAN_MCR_REG(base) |= CAN_MCR_SUPV_MASK; + + if (mode & flexcanListenOnlyMode) + CAN_CTRL1_REG(base) |= CAN_CTRL1_LOM_MASK; + else + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_LOM_MASK; + + if (mode & flexcanLoopBackMode) + CAN_CTRL1_REG(base) |= CAN_CTRL1_LPB_MASK; + else + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_LPB_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetMaxMsgBufNum + * Description : Set the maximum number of Message Buffers. + * + *END**************************************************************************/ +void FLEXCAN_SetMaxMsgBufNum(CAN_Type* base, uint32_t bufNum) +{ + assert((bufNum <= CAN_CS_COUNT) && (bufNum > 0)); + + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + /* Set the maximum number of MBs*/ + CAN_MCR_REG(base) = (CAN_MCR_REG(base) & (~CAN_MCR_MAXMB_MASK)) | CAN_MCR_MAXMB(bufNum-1); + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetAbortCmd + * Description : Set the Transmit abort feature enablement. + * + *END**************************************************************************/ +void FLEXCAN_SetAbortCmd(CAN_Type* base, bool enable) +{ + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_MCR_REG(base) |= CAN_MCR_AEN_MASK; + else + CAN_MCR_REG(base) &= ~CAN_MCR_AEN_MASK; + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetLocalPrioCmd + * Description : Set the local transmit priority enablement. + * + *END**************************************************************************/ +void FLEXCAN_SetLocalPrioCmd(CAN_Type* base, bool enable) +{ + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + CAN_MCR_REG(base) |= CAN_MCR_LPRIO_EN_MASK; + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_LBUF_MASK; + } + else + { + CAN_CTRL1_REG(base) |= CAN_CTRL1_LBUF_MASK; + CAN_MCR_REG(base) &= ~CAN_MCR_LPRIO_EN_MASK; + } + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetMatchPrioCmd + * Description : Set the Rx matching process priority. + * + *END**************************************************************************/ +void FLEXCAN_SetMatchPrioCmd(CAN_Type* base, bool priority) +{ + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + if (priority) + CAN_CTRL2_REG(base) |= CAN_CTRL2_MRP_MASK; + else + CAN_CTRL2_REG(base) &= ~CAN_CTRL2_MRP_MASK; + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/******************************************************************************* + * FlexCAN Message buffer control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetMsgBufPtr + * Description : Get message buffer pointer for transition. + * + *END**************************************************************************/ +flexcan_msgbuf_t* FLEXCAN_GetMsgBufPtr(CAN_Type* base, uint8_t msgBufIdx) +{ + assert(msgBufIdx < CAN_CS_COUNT); + + return (flexcan_msgbuf_t*) &base->MB[msgBufIdx]; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_LockRxMsgBuf + * Description : Locks the FlexCAN Rx message buffer. + * + *END**************************************************************************/ +bool FLEXCAN_LockRxMsgBuf(CAN_Type* base, uint8_t msgBufIdx) +{ + volatile uint32_t temp; + + /* Check if the MB to be Locked is enabled */ + if (msgBufIdx > (CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK)) + return false; + + /* ARM Core read MB's CS to lock MB */ + temp = base->MB[msgBufIdx].CS; + + /* Read temp itself to avoid ARMGCC warning */ + temp++; + + return true; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_UnlockAllRxMsgBuf + * Description : Unlocks the FlexCAN Rx message buffer. + * + *END**************************************************************************/ +uint16_t FLEXCAN_UnlockAllRxMsgBuf(CAN_Type* base) +{ + /* Read Free Running Timer to unlock all MessageBox */ + return CAN_TIMER_REG(base); +} + +/******************************************************************************* + * FlexCAN Interrupts and flags management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetMsgBufIntCmd + * Description : Enables/Disables the FlexCAN Message Buffer interrupt. + * + *END**************************************************************************/ +void FLEXCAN_SetMsgBufIntCmd(CAN_Type* base, uint8_t msgBufIdx, bool enable) +{ + volatile uint32_t* interruptMaskPtr; + uint8_t index; + + assert(msgBufIdx < CAN_CS_COUNT); + + if (msgBufIdx > 0x31) + { + index = msgBufIdx - 32; + interruptMaskPtr = &base->IMASK2; + } + else + { + index = msgBufIdx; + interruptMaskPtr = &base->IMASK1; + } + + if (enable) + *interruptMaskPtr |= 0x1 << index; + else + *interruptMaskPtr &= ~(0x1 << index); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetMsgBufStatusFlag + * Description : Gets the individual FlexCAN MB interrupt flag. + * + *END**************************************************************************/ +bool FLEXCAN_GetMsgBufStatusFlag(CAN_Type* base, uint8_t msgBufIdx) +{ + volatile uint32_t* interruptFlagPtr; + volatile uint8_t index; + + assert(msgBufIdx < CAN_CS_COUNT); + + if (msgBufIdx > 0x31) + { + index = msgBufIdx - 32; + interruptFlagPtr = &base->IFLAG2; + } + else + { + index = msgBufIdx; + interruptFlagPtr = &base->IFLAG1; + } + + return (bool)((*interruptFlagPtr >> index) & 0x1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_ClearMsgBufStatusFlag + * Description : Clears the interrupt flag of the message buffers. + * + *END**************************************************************************/ +void FLEXCAN_ClearMsgBufStatusFlag(CAN_Type* base, uint32_t msgBufIdx) +{ + volatile uint8_t index; + + assert(msgBufIdx < CAN_CS_COUNT); + + if (msgBufIdx > 0x31) + { + index = msgBufIdx - 32; + /* write 1 to clear. */ + base->IFLAG2 = 0x1 << index; + } + else + { + index = msgBufIdx; + /* write 1 to clear. */ + base->IFLAG1 = 0x1 << index; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetErrIntCmd + * Description : Enables error interrupt of the FlexCAN module. + * + *END**************************************************************************/ +void FLEXCAN_SetErrIntCmd(CAN_Type* base, uint32_t errorType, bool enable) +{ + assert((errorType & flexcanIntRxWarning) || + (errorType & flexcanIntTxWarning) || + (errorType & flexcanIntWakeUp) || + (errorType & flexcanIntBusOff) || + (errorType & flexcanIntError)); + + if (enable) + { + if (errorType & flexcanIntRxWarning) + { + CAN_MCR_REG(base) |= CAN_MCR_WRN_EN_MASK; + CAN_CTRL1_REG(base) |= CAN_CTRL1_RWRN_MSK_MASK; + } + + if (errorType & flexcanIntTxWarning) + { + CAN_MCR_REG(base) |= CAN_MCR_WRN_EN_MASK; + CAN_CTRL1_REG(base) |= CAN_CTRL1_TWRN_MSK_MASK; + } + + if (errorType & flexcanIntWakeUp) + CAN_MCR_REG(base) |= CAN_MCR_WAK_MSK_MASK; + + if (errorType & flexcanIntBusOff) + CAN_CTRL1_REG(base) |= CAN_CTRL1_BOFF_MSK_MASK; + + if (errorType & flexcanIntError) + CAN_CTRL1_REG(base) |= CAN_CTRL1_ERR_MSK_MASK; + } + else + { + if (errorType & flexcanIntRxWarning) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_RWRN_MSK_MASK; + + if (errorType & flexcanIntTxWarning) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_TWRN_MSK_MASK; + + if (errorType & flexcanIntWakeUp) + CAN_MCR_REG(base) &= ~CAN_MCR_WAK_MSK_MASK; + + if (errorType & flexcanIntBusOff) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_BOFF_MSK_MASK; + + if (errorType & flexcanIntError) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_ERR_MSK_MASK; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetErrStatusFlag + * Description : Gets the FlexCAN module interrupt flag. + * + *END**************************************************************************/ +uint32_t FLEXCAN_GetErrStatusFlag(CAN_Type* base, uint32_t errFlags) +{ + return CAN_ESR1_REG(base) & errFlags; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_ClearErrStatusFlag + * Description : Clears the interrupt flag of the FlexCAN module. + * + *END**************************************************************************/ +void FLEXCAN_ClearErrStatusFlag(CAN_Type* base, uint32_t errorType) +{ + /* The Interrupt flag must be cleared by writing it to '1'. + * Writing '0' has no effect. + */ + CAN_ESR1_REG(base) = errorType; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetErrCounter + * Description : Get the error counter of FlexCAN module. + * + *END**************************************************************************/ +void FLEXCAN_GetErrCounter(CAN_Type* base, uint8_t* txError, uint8_t* rxError) +{ + *txError = CAN_ECR_REG(base) & CAN_ECR_Tx_Err_Counter_MASK; + *rxError = (CAN_ECR_REG(base) & CAN_ECR_Rx_Err_Counter_MASK) >> \ + CAN_ECR_Rx_Err_Counter_SHIFT; +} + +/******************************************************************************* + * Rx FIFO management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_EnableRxFifo + * Description : Enables the Rx FIFO. + * + *END**************************************************************************/ +void FLEXCAN_EnableRxFifo(CAN_Type* base, uint8_t numOfFilters) +{ + uint8_t maxNumMb; + + assert(numOfFilters <= 0xF); + + /* Set Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + /* Set the number of the RX FIFO filters needed*/ + CAN_CTRL2_REG(base) = (CAN_CTRL2_REG(base) & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(numOfFilters); + + /* Enable RX FIFO*/ + CAN_MCR_REG(base) |= CAN_MCR_RFEN_MASK; + + /* RX FIFO global mask*/ + CAN_RXFGMASK_REG(base) = CAN_RXFGMASK_FGM31_FGM0_MASK; + + maxNumMb = (CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK) + 1; + + for (uint8_t i = 0; i < maxNumMb; i++) + { + /* RX individual mask*/ + CAN_RXIMR_REG(base,i) = CAN_RXIMR0_RXIMR63_MI31_MI0_MASK; + } + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_DisableRxFifo + * Description : Disables the Rx FIFO. + * + *END**************************************************************************/ +void FLEXCAN_DisableRxFifo(CAN_Type* base) +{ + /* Set Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + /* Disable RX FIFO*/ + CAN_MCR_REG(base) &= ~CAN_MCR_RFEN_MASK; + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxFifoFilterNum + * Description : Set the number of the Rx FIFO filters. + * + *END**************************************************************************/ +void FLEXCAN_SetRxFifoFilterNum(CAN_Type* base, uint32_t numOfFilters) +{ + assert(numOfFilters <= 0xF); + + /* Set Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + /* Set the number of RX FIFO ID filters*/ + CAN_CTRL2_REG(base) = (CAN_CTRL2_REG(base) & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(numOfFilters); + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxFifoFilter + * Description : Set the FlexCAN Rx FIFO fields. + * + *END**************************************************************************/ +void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table_t *idFilterTable) +{ + /* Set RX FIFO ID filter table elements*/ + uint32_t i, j, numOfFilters; + uint32_t val1 = 0, val2 = 0, val = 0; + volatile uint32_t *filterTable; + + numOfFilters = (CAN_CTRL2_REG(base) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT; + /* Rx FIFO Ocuppied First Message Box is MB6 */ + filterTable = (volatile uint32_t *)&(base->MB[6]); + + CAN_MCR_REG(base) |= CAN_MCR_IDAM(idFormat); + + switch (idFormat) + { + case flexcanRxFifoIdElementFormatA: + /* One full ID (standard and extended) per ID Filter Table element.*/ + if (idFilterTable->isRemoteFrame) + { + val = (uint32_t)0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT; + } + if (idFilterTable->isExtendedFrame) + { + val |= 0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT; + } + for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++) + { + if(idFilterTable->isExtendedFrame) + { + filterTable[i] = val + ((*(idFilterTable->idFilter + i)) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK); + }else + { + filterTable[i] = val + ((*(idFilterTable->idFilter + i)) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK); + } + } + break; + case flexcanRxFifoIdElementFormatB: + /* Two full standard IDs or two partial 14-bit (standard and extended) IDs*/ + /* per ID Filter Table element.*/ + if (idFilterTable->isRemoteFrame) + { + val1 = (uint32_t)0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT; + val2 = 0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT; + } + if (idFilterTable->isExtendedFrame) + { + val1 |= 0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT; + val2 |= 0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT; + } + j = 0; + for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++) + { + if (idFilterTable->isExtendedFrame) + { + filterTable[i] = val1 + (((*(idFilterTable->idFilter + j)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1); + filterTable[i] |= val2 + (((*(idFilterTable->idFilter + j + 1)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2); + }else + { + filterTable[i] = val1 + (((*(idFilterTable->idFilter + j)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1); + filterTable[i] |= val2 + (((*(idFilterTable->idFilter + j + 1)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2); + } + j = j + 2; + } + break; + case flexcanRxFifoIdElementFormatC: + /* Four partial 8-bit Standard IDs per ID Filter Table element.*/ + j = 0; + for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++) + { + filterTable[i] = (((*(idFilterTable->idFilter + j)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1); + filterTable[i] = (((*(idFilterTable->idFilter + j + 1)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2); + filterTable[i] = (((*(idFilterTable->idFilter + j + 2)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3); + filterTable[i] = (((*(idFilterTable->idFilter + j + 3)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4); + j = j + 4; + } + break; + case flexcanRxFifoIdElementFormatD: + /* All frames rejected.*/ + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetRxFifoPtr + * Description : Gets the FlexCAN Rx FIFO data pointer. + * + *END**************************************************************************/ +flexcan_msgbuf_t* FLEXCAN_GetRxFifoPtr(CAN_Type* base) +{ + /* Rx-Fifo occupy MB0 ~ MB5 */ + return (flexcan_msgbuf_t*)&base->MB; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetRxFifoInfo + * Description : Set the FlexCAN RX Fifo global mask. + * + *END**************************************************************************/ +uint16_t FLEXCAN_GetRxFifoInfo(CAN_Type* base) +{ + return CAN_RXFIR_REG(base) & CAN_RXFIR_IDHIT_MASK; +} + +/******************************************************************************* + * Rx Mask Setting functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxMaskMode + * Description : Set the Rx masking mode. + * + *END**************************************************************************/ +void FLEXCAN_SetRxMaskMode(CAN_Type* base, uint32_t mode) +{ + assert((mode == flexcanRxMaskGlobal) || + (mode == flexcanRxMaskIndividual)); + + /* Assert Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (mode == flexcanRxMaskIndividual) + CAN_MCR_REG(base) |= CAN_MCR_IRMQ_MASK; + else + CAN_MCR_REG(base) &= ~CAN_MCR_IRMQ_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxMaskRtrCmd + * Description : Set the remote trasmit request mask enablement. + * + *END**************************************************************************/ +void FLEXCAN_SetRxMaskRtrCmd(CAN_Type* base, bool enable) +{ + /* Assert Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_CTRL2_REG(base) |= CAN_CTRL2_EACEN_MASK; + else + CAN_CTRL2_REG(base) &= ~CAN_CTRL2_EACEN_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxGlobalMask + * Description : Set the FlexCAN RX global mask. + * + *END**************************************************************************/ +void FLEXCAN_SetRxGlobalMask(CAN_Type* base, uint32_t mask) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + /* load mask */ + CAN_RXMGMASK_REG(base) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxIndividualMask + * Description : Set the FlexCAN Rx individual mask for ID filtering in + * the Rx MBs and the Rx FIFO. + * + *END**************************************************************************/ +void FLEXCAN_SetRxIndividualMask(CAN_Type* base, uint32_t msgBufIdx, uint32_t mask) +{ + assert(msgBufIdx < CAN_RXIMR_COUNT); + + /* Assert Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + CAN_RXIMR_REG(base,msgBufIdx) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxMsgBuff14Mask + * Description : Set the FlexCAN RX Message Buffer BUF14 mask. + * + *END**************************************************************************/ +void FLEXCAN_SetRxMsgBuff14Mask(CAN_Type* base, uint32_t mask) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + /* load mask */ + CAN_RX14MASK_REG(base) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxMsgBuff15Mask + * Description : Set the FlexCAN RX Message Buffer BUF15 mask. + * + *END**************************************************************************/ +void FLEXCAN_SetRxMsgBuff15Mask(CAN_Type* base, uint32_t mask) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + /* load mask */ + CAN_RX15MASK_REG(base) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxFifoGlobalMask + * Description : Set the FlexCAN RX Fifo global mask. + * + *END**************************************************************************/ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type* base, uint32_t mask) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + /* load mask */ + CAN_RXFGMASK_REG(base) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/******************************************************************************* + * Misc. Functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetSelfWakeUpCmd + * Description : Enable/disable the FlexCAN self wakeup feature. + * + *END**************************************************************************/ +void FLEXCAN_SetSelfWakeUpCmd(CAN_Type* base, bool lpfEnable, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (lpfEnable) + CAN_MCR_REG(base) |= CAN_MCR_WAK_SRC_MASK; + else + CAN_MCR_REG(base) &= ~CAN_MCR_WAK_SRC_MASK; + + if (enable) + CAN_MCR_REG(base) |= CAN_MCR_SLF_WAK_MASK; + else + CAN_MCR_REG(base) &= ~CAN_MCR_SLF_WAK_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetSelfReceptionCmd + * Description : Enable/disable the FlexCAN self reception feature. + * + *END**************************************************************************/ +void FLEXCAN_SetSelfReceptionCmd(CAN_Type* base, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_MCR_REG(base) &= ~CAN_MCR_SRX_DIS_MASK; + else + CAN_MCR_REG(base) |= CAN_MCR_SRX_DIS_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxVoteCmd + * Description : Enable/disable the enhance FlexCAN Rx vote. + * + *END**************************************************************************/ +void FLEXCAN_SetRxVoteCmd(CAN_Type* base, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_CTRL1_REG(base) |= CAN_CTRL1_SMP_MASK; + else + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_SMP_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetAutoBusOffRecoverCmd + * Description : Enable/disable the Auto Busoff recover feature. + * + *END**************************************************************************/ +void FLEXCAN_SetAutoBusOffRecoverCmd(CAN_Type* base, bool enable) +{ + if (enable) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_BOFF_MSK_MASK; + else + CAN_CTRL1_REG(base) |= CAN_CTRL1_BOFF_MSK_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetTimeSyncCmd + * Description : Enable/disable the Time Sync feature. + * + *END**************************************************************************/ +void FLEXCAN_SetTimeSyncCmd(CAN_Type* base, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_CTRL1_REG(base) |= CAN_CTRL1_TSYN_MASK; + else + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_TSYN_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetAutoRemoteResponseCmd + * Description : Enable/disable the Auto Remote Response feature. + * + *END**************************************************************************/ +void FLEXCAN_SetAutoRemoteResponseCmd(CAN_Type* base, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_CTRL2_REG(base) &= ~CAN_CTRL2_RRS_MASK; + else + CAN_CTRL2_REG(base) |= CAN_CTRL2_RRS_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/flexcan.h b/zephyr/imx/drivers/flexcan.h new file mode 100644 index 000000000..5348364bc --- /dev/null +++ b/zephyr/imx/drivers/flexcan.h @@ -0,0 +1,712 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLEXCAN_H__ +#define __FLEXCAN_H__ + +#include +#include +#include +#include "device_imx.h" + +/* Start of section using anonymous unions. */ +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_msgbuf_code_rx +{ + flexcanRxInactive = 0x0, /*!< MB is not active. */ + flexcanRxFull = 0x2, /*!< MB is full. */ + flexcanRxEmpty = 0x4, /*!< MB is active and empty. */ + flexcanRxOverrun = 0x6, /*!< MB is overwritten into a full buffer. */ + flexcanRxBusy = 0x8, /*!< FlexCAN is updating the contents of the MB. */ + /*! The CPU must not access the MB. */ + flexcanRxRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ + /*! and transmit a Response Frame in return. */ + flexcanRxNotUsed = 0xF, /*!< Not used. */ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_msgbuf_code_tx +{ + flexcanTxInactive = 0x8, /*!< MB is not active. */ + flexcanTxAbort = 0x9, /*!< MB is aborted. */ + flexcanTxDataOrRemte = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ + /*!< MB is a TX Remote Request Frame (when MB RTR = 1). */ + flexcanTxTanswer = 0xE, /*!< MB is a TX Response Request Frame from. */ + /*! an incoming Remote Request Frame. */ + flexcanTxNotUsed = 0xF, /*!< Not used. */ +}; + +/*! @brief FlexCAN operation modes. */ +enum _flexcan_operatining_modes +{ + flexcanNormalMode = 0x1, /*!< Normal mode or user mode @internal gui name="Normal". */ + flexcanListenOnlyMode = 0x2, /*!< Listen-only mode @internal gui name="Listen-only". */ + flexcanLoopBackMode = 0x4, /*!< Loop-back mode @internal gui name="Loop back". */ +}; + +/*! @brief FlexCAN RX mask mode. */ +enum _flexcan_rx_mask_mode +{ + flexcanRxMaskGlobal = 0x0, /*!< Rx global mask. */ + flexcanRxMaskIndividual = 0x1, /*!< Rx individual mask. */ +}; + +/*! @brief The ID type used in rx matching process. */ +enum _flexcan_rx_mask_id_type +{ + flexcanRxMaskIdStd = 0x0, /*!< Standard ID. */ + flexcanRxMaskIdExt = 0x1, /*!< Extended ID. */ +}; + +/*! @brief FlexCAN error interrupt source enumeration. */ +enum _flexcan_interrutpt +{ + flexcanIntRxWarning = 0x01, /*!< Tx Warning interrupt source. */ + flexcanIntTxWarning = 0x02, /*!< Tx Warning interrupt source. */ + flexcanIntWakeUp = 0x04, /*!< Wake Up interrupt source. */ + flexcanIntBusOff = 0x08, /*!< Bus Off interrupt source. */ + flexcanIntError = 0x10, /*!< Error interrupt source. */ +}; + +/*! @brief FlexCAN error interrupt flags. */ +enum _flexcan_status_flag +{ + flexcanStatusSynch = CAN_ESR1_SYNCH_MASK, /*!< Bus Synchronized flag. */ + flexcanStatusTxWarningInt = CAN_ESR1_TWRN_INT_MASK, /*!< Tx Warning initerrupt flag. */ + flexcanStatusRxWarningInt = CAN_ESR1_RWRN_INT_MASK, /*!< Tx Warning initerrupt flag. */ + flexcanStatusBit1Err = CAN_ESR1_BIT1_ERR_MASK, /*!< Bit0 Error flag. */ + flexcanStatusBit0Err = CAN_ESR1_BIT0_ERR_MASK, /*!< Bit1 Error flag. */ + flexcanStatusAckErr = CAN_ESR1_ACK_ERR_MASK, /*!< Ack Error flag. */ + flexcanStatusCrcErr = CAN_ESR1_CRC_ERR_MASK, /*!< CRC Error flag. */ + flexcanStatusFrameErr = CAN_ESR1_FRM_ERR_MASK, /*!< Frame Error flag. */ + flexcanStatusStuffingErr = CAN_ESR1_STF_ERR_MASK, /*!< Stuffing Error flag. */ + flexcanStatusTxWarning = CAN_ESR1_TX_WRN_MASK, /*!< Tx Warning flag. */ + flexcanStatusRxWarning = CAN_ESR1_RX_WRN_MASK, /*!< Rx Warning flag. */ + flexcanStatusIdle = CAN_ESR1_IDLE_MASK, /*!< FlexCAN Idle flag. */ + flexcanStatusTransmitting = CAN_ESR1_TX_MASK, /*!< Trasmitting flag. */ + flexcanStatusFltConf = CAN_ESR1_FLT_CONF_MASK, /*!< Fault Config flag. */ + flexcanStatusReceiving = CAN_ESR1_RX_MASK, /*!< Receiving flag. */ + flexcanStatusBusOff = CAN_ESR1_BOFF_INT_MASK, /*!< Bus Off interrupt flag. */ + flexcanStatusError = CAN_ESR1_ERR_INT_MASK, /*!< Error interrupt flag. */ + flexcanStatusWake = CAN_ESR1_WAK_INT_MASK, /*!< Wake Up interrupt flag. */ +}; + +/*! @brief The id filter element type selection. */ +enum _flexcan_rx_fifo_id_element_format +{ + flexcanRxFifoIdElementFormatA = 0x0, /*!< One full ID (standard and extended) per ID Filter Table element. */ + flexcanRxFifoIdElementFormatB = 0x1, /*!< Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. */ + flexcanRxFifoIdElementFormatC = 0x2, /*!< Four partial 8-bit Standard IDs per ID Filter Table element. */ + flexcanRxFifoIdElementFormatD = 0x3, /*!< All frames rejected. */ +}; + +/*! @brief FlexCAN Rx FIFO filters number. */ +enum _flexcan_rx_fifo_filter_id_number +{ + flexcanRxFifoIdFilterNum8 = 0x0, /*!< 8 Rx FIFO Filters. @internal gui name="8 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum16 = 0x1, /*!< 16 Rx FIFO Filters. @internal gui name="16 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum24 = 0x2, /*!< 24 Rx FIFO Filters. @internal gui name="24 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum32 = 0x3, /*!< 32 Rx FIFO Filters. @internal gui name="32 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum40 = 0x4, /*!< 40 Rx FIFO Filters. @internal gui name="40 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum48 = 0x5, /*!< 48 Rx FIFO Filters. @internal gui name="48 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum56 = 0x6, /*!< 56 Rx FIFO Filters. @internal gui name="56 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum64 = 0x7, /*!< 64 Rx FIFO Filters. @internal gui name="64 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum72 = 0x8, /*!< 72 Rx FIFO Filters. @internal gui name="72 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum80 = 0x9, /*!< 80 Rx FIFO Filters. @internal gui name="80 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum88 = 0xA, /*!< 88 Rx FIFO Filters. @internal gui name="88 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum96 = 0xB, /*!< 96 Rx FIFO Filters. @internal gui name="96 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum104 = 0xC, /*!< 104 Rx FIFO Filters. @internal gui name="104 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum112 = 0xD, /*!< 112 Rx FIFO Filters. @internal gui name="112 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum120 = 0xE, /*!< 120 Rx FIFO Filters. @internal gui name="120 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum128 = 0xF, /*!< 128 Rx FIFO Filters. @internal gui name="128 Rx FIFO Filters" */ +}; + +/*! @brief FlexCAN RX FIFO ID filter table structure. */ +typedef struct _flexcan_id_table +{ + uint32_t *idFilter; /*!< Rx FIFO ID filter elements. */ + bool isRemoteFrame; /*!< Remote frame. */ + bool isExtendedFrame; /*!< Extended frame. */ +} flexcan_id_table_t; + +/*! @brief FlexCAN message buffer structure. */ +typedef struct _flexcan_msgbuf +{ + union + { + uint32_t cs; /*!< Code and Status. */ + struct + { + uint32_t timeStamp : 16; + uint32_t dlc : 4; + uint32_t rtr : 1; + uint32_t ide : 1; + uint32_t srr : 1; + uint32_t reserved1 : 1; + uint32_t code : 4; + uint32_t reserved2 : 4; + }; + }; + + union + { + uint32_t id; /*!< Message Buffer ID. */ + struct + { + uint32_t idExt : 18; + uint32_t idStd : 11; + uint32_t prio : 3; + }; + }; + + union + { + uint32_t word0; /*!< Bytes of the FlexCAN message. */ + struct + { + uint8_t data3; + uint8_t data2; + uint8_t data1; + uint8_t data0; + }; + }; + + union + { + uint32_t word1; /*!< Bytes of the FlexCAN message. */ + struct + { + uint8_t data7; + uint8_t data6; + uint8_t data5; + uint8_t data4; + }; + }; +} flexcan_msgbuf_t; + +/*! @brief FlexCAN timing-related structures. */ +typedef struct _flexcan_timing +{ + uint32_t preDiv; /*!< Clock pre divider. */ + uint32_t rJumpwidth; /*!< Resync jump width. */ + uint32_t phaseSeg1; /*!< Phase segment 1. */ + uint32_t phaseSeg2; /*!< Phase segment 2. */ + uint32_t propSeg; /*!< Propagation segment. */ +} flexcan_timing_t; + +/*! @brief FlexCAN module initialization structure. */ +typedef struct _flexcan_init_config +{ + flexcan_timing_t timing; /*!< Desired FlexCAN module timing configuration. */ + uint32_t operatingMode; /*!< Desired FlexCAN module operating mode. */ + uint8_t maxMsgBufNum; /*!< The maximal number of available message buffer. */ +} flexcan_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FlexCAN Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initialize FlexCAN module with given initialization structure. + * + * @param base CAN base pointer. + * @param initConfig CAN initialization structure (see @ref flexcan_init_config_t structure). + */ +void FLEXCAN_Init(CAN_Type* base, const flexcan_init_config_t* initConfig); + +/*! + * @brief This function reset FlexCAN module register content to its default value. + * + * @param base FlexCAN base pointer. + */ +void FLEXCAN_Deinit(CAN_Type* base); + +/*! + * @brief This function is used to Enable the FlexCAN Module. + * + * @param base FlexCAN base pointer. + */ +void FLEXCAN_Enable(CAN_Type* base); + +/*! + * @brief This function is used to Disable the FlexCAN Module. + * + * @param base FlexCAN base pointer. + */ +void FLEXCAN_Disable(CAN_Type* base); + +/*! + * @brief Sets the FlexCAN time segments for setting up bit rate. + * + * @param base FlexCAN base pointer. + * @param timing FlexCAN time segments, which need to be set for the bit rate (See @ref flexcan_timing_t structure). + */ +void FLEXCAN_SetTiming(CAN_Type* base, const flexcan_timing_t* timing); + +/*! + * @brief Set operation mode. + * + * @param base FlexCAN base pointer. + * @param mode Set an operation mode. + */ +void FLEXCAN_SetOperatingMode(CAN_Type* base, uint8_t mode); + +/*! + * @brief Set the maximum number of Message Buffers. + * + * @param base FlexCAN base pointer. + * @param bufNum Maximum number of message buffers. + */ +void FLEXCAN_SetMaxMsgBufNum(CAN_Type* base, uint32_t bufNum); + +/*! + * @brief Get the working status of FlexCAN module. + * + * @param base FlexCAN base pointer. + * @return - true: FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode. + * - false: FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode. + */ +static inline bool FLEXCAN_IsModuleReady(CAN_Type* base) +{ + return !((CAN_MCR_REG(base) >> CAN_MCR_NOT_RDY_SHIFT) & 0x1); +} + +/*! + * @brief Set the Transmit Abort feature enablement. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable Transmit Abort feature. + * - true: Enable Transmit Abort feature. + * - false: Disable Transmit Abort feature. + */ +void FLEXCAN_SetAbortCmd(CAN_Type* base, bool enable); + +/*! + * @brief Set the local transmit priority enablement. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable local transmit periority. + * - true: Transmit MB with highest local priority. + * - false: Transmit MB with lowest MB number. + */ +void FLEXCAN_SetLocalPrioCmd(CAN_Type* base, bool enable); + +/*! + * @brief Set the Rx matching process priority. + * + * @param base FlexCAN base pointer. + * @param priority Set Rx matching process priority. + * - true: Matching starts from Mailboxes and continues on Rx FIFO. + * - false: Matching starts from Rx FIFO and continues on Mailboxes. + */ +void FLEXCAN_SetMatchPrioCmd(CAN_Type* base, bool priority); + +/*@}*/ + +/*! + * @name FlexCAN Message buffer control functions + * @{ + */ + +/*! + * @brief Get message buffer pointer for transition. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx message buffer index. + * @return message buffer pointer. + */ +flexcan_msgbuf_t* FLEXCAN_GetMsgBufPtr(CAN_Type* base, uint8_t msgBufIdx); + +/*! + * @brief Locks the FlexCAN Rx message buffer. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer + * @return - true: Lock Rx Message Buffer successful. + * - false: Lock Rx Message Buffer failed. + */ +bool FLEXCAN_LockRxMsgBuf(CAN_Type* base, uint8_t msgBufIdx); + +/*! + * @brief Unlocks the FlexCAN Rx message buffer. + * + * @param base FlexCAN base pointer. + * @return current free run timer counter value. + */ +uint16_t FLEXCAN_UnlockAllRxMsgBuf(CAN_Type* base); + +/*@}*/ + +/*! + * @name FlexCAN Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Enables/Disables the FlexCAN Message Buffer interrupt. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @param enable Enables/Disables interrupt. + * - true: Enable Message Buffer interrupt. + * - disable: Disable Message Buffer interrupt. + */ +void FLEXCAN_SetMsgBufIntCmd(CAN_Type* base, uint8_t msgBufIdx, bool enable); + +/*! + * @brief Gets the individual FlexCAN MB interrupt flag. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @retval true: Message Buffer Interrupt is pending. + * @retval false: There is no Message Buffer Interrupt. + */ +bool FLEXCAN_GetMsgBufStatusFlag(CAN_Type* base, uint8_t msgBufIdx); + +/*! + * @brief Clears the interrupt flag of the message buffers. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + */ +void FLEXCAN_ClearMsgBufStatusFlag(CAN_Type* base, uint32_t msgBufIdx); + +/*! + * @brief Enables error interrupt of the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param errorSrc The interrupt source (see @ref _flexcan_interrutpt enumeration). + * @param enable Choose enable or disable. + */ +void FLEXCAN_SetErrIntCmd(CAN_Type* base, uint32_t errorSrc, bool enable); + +/*! + * @brief Gets the FlexCAN module interrupt flag. + * + * @param base FlexCAN base pointer. + * @param errFlags FlexCAN error flags (see @ref _flexcan_status_flag enumeration). + * @return The individual Message Buffer interrupt flag (0 and 1 are the flag value) + */ +uint32_t FLEXCAN_GetErrStatusFlag(CAN_Type* base, uint32_t errFlags); + +/*! + * @brief Clears the interrupt flag of the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param errFlags The value to be written to the interrupt flag1 register (see @ref _flexcan_status_flag enumeration). + */ +void FLEXCAN_ClearErrStatusFlag(CAN_Type* base, uint32_t errFlags); + +/*! + * @brief Get the error counter of FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param txError Tx_Err_Counter pointer. + * @param rxError Rx_Err_Counter pointer. + */ +void FLEXCAN_GetErrCounter(CAN_Type* base, uint8_t* txError, uint8_t* rxError); + +/*@}*/ + +/*! + * @name Rx FIFO management functions + * @{ + */ + +/*! + * @brief Enables the Rx FIFO. + * + * @param base FlexCAN base pointer. + * @param numOfFilters The number of Rx FIFO filters + */ +void FLEXCAN_EnableRxFifo(CAN_Type* base, uint8_t numOfFilters); + +/*! + * @brief Disables the Rx FIFO. + * + * @param base FlexCAN base pointer. + */ +void FLEXCAN_DisableRxFifo(CAN_Type* base); + +/*! + * @brief Set the number of the Rx FIFO filters. + * + * @param base FlexCAN base pointer. + * @param numOfFilters The number of Rx FIFO filters. + */ +void FLEXCAN_SetRxFifoFilterNum(CAN_Type* base, uint32_t numOfFilters); + +/*! + * @brief Set the FlexCAN Rx FIFO fields. + * + * @param base FlexCAN base pointer. + * @param idFormat The format of the Rx FIFO ID Filter Table Elements + * @param idFilterTable The ID filter table elements which contain RTR bit, IDE bit and RX message ID. + */ +void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table_t *idFilterTable); + +/*! + * @brief Gets the FlexCAN Rx FIFO data pointer. + * + * @param base FlexCAN base pointer. + * @return Rx FIFO data pointer. + */ +flexcan_msgbuf_t* FLEXCAN_GetRxFifoPtr(CAN_Type* base); + +/*! + * @brief Gets the FlexCAN Rx FIFO information. + * The return value indicates which Identifier Acceptance Filter + * (see Rx FIFO Structure) was hit by the received message. + * @param base FlexCAN base pointer. + * @return Rx FIFO filter number. + */ +uint16_t FLEXCAN_GetRxFifoInfo(CAN_Type* base); + +/*@}*/ + +/*! + * @name Rx Mask Setting functions + * @{ + */ + +/*! + * @brief Set the Rx masking mode. + * + * @param base FlexCAN base pointer. + * @param mode The FlexCAN Rx mask mode (see @ref _flexcan_rx_mask_mode enumeration). + */ +void FLEXCAN_SetRxMaskMode(CAN_Type* base, uint32_t mode); + +/*! + * @brief Set the remote trasmit request mask enablement. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable remote trasmit request mask. + * - true: Enable RTR matching judgement. + * - false: Disable RTR matching judgement. + */ +void FLEXCAN_SetRxMaskRtrCmd(CAN_Type* base, bool enable); + +/*! + * @brief Set the FlexCAN RX global mask. + * + * @param base FlexCAN base pointer. + * @param mask Rx Global mask. + */ +void FLEXCAN_SetRxGlobalMask(CAN_Type* base, uint32_t mask); + +/*! + * @brief Set the FlexCAN Rx individual mask for ID filtering in the Rx MBs and the Rx FIFO. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @param mask Individual mask + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type* base, uint32_t msgBufIdx, uint32_t mask); + +/*! + * @brief Set the FlexCAN RX Message Buffer BUF14 mask. + * + * @param base FlexCAN base pointer. + * @param mask Message Buffer BUF14 mask. + */ +void FLEXCAN_SetRxMsgBuff14Mask(CAN_Type* base, uint32_t mask); + +/*! + * @brief Set the FlexCAN RX Message Buffer BUF15 mask. + * + * @param base FlexCAN base pointer. + * @param mask Message Buffer BUF15 mask. + */ +void FLEXCAN_SetRxMsgBuff15Mask(CAN_Type* base, uint32_t mask); + +/*! + * @brief Set the FlexCAN RX Fifo global mask. + * + * @param base FlexCAN base pointer. + * @param mask Rx Fifo Global mask. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type* base, uint32_t mask); + +/*@}*/ + +/*! + * @name Misc. Functions + * @{ + */ + +/*! + * @brief Enable/disable the FlexCAN self wakeup feature. + * + * @param base FlexCAN base pointer. + * @param lpfEnable The low pass filter for Rx self wakeup feature enablement. + * @param enable The self wakeup feature enablement. + */ +void FLEXCAN_SetSelfWakeUpCmd(CAN_Type* base, bool lpfEnable, bool enable); + +/*! + * @brief Enable/Disable the FlexCAN self reception feature. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable self reception feature. + * - true: Enable self reception feature. + * - false: Disable self reception feature. + */ +void FLEXCAN_SetSelfReceptionCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the enhance FlexCAN Rx vote. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable FlexCAN Rx vote mechanism + * - true: Three samples are used to determine the value of the received bit. + * - false: Just one sample is used to determine the bit value. + */ +void FLEXCAN_SetRxVoteCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the Auto Busoff recover feature. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable Auto Busoff Recover + * - true: Enable Auto Bus Off recover feature. + * - false: Disable Auto Bus Off recover feature. + */ +void FLEXCAN_SetAutoBusOffRecoverCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the Time Sync feature. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable the Time Sync + * - true: Enable Time Sync feature. + * - false: Disable Time Sync feature. + */ +void FLEXCAN_SetTimeSyncCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the Auto Remote Response feature. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable the Auto Remote Response feature + * - true: Enable Auto Remote Response feature. + * - false: Disable Auto Remote Response feature. + */ +void FLEXCAN_SetAutoRemoteResponseCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the Glitch Filter Width when FLEXCAN enters the STOP mode. + * + * @param base FlexCAN base pointer. + * @param filterWidth The Glitch Filter Width. + */ +static inline void FLEXCAN_SetGlitchFilterWidth(CAN_Type* base, uint8_t filterWidth) +{ + CAN_GFWR_REG(base) = filterWidth; +} + +/*! + * @brief Get the lowest inactive message buffer number. + * + * @param base FlexCAN base pointer. + * @return bit 22-16 : The lowest number inactive Mailbox. + * bit 14 : Indicates whether the number content is valid or not. + * bit 13 : This bit indicates whether there is any inactive Mailbox. + */ +static inline uint32_t FLEXCAN_GetLowestInactiveMsgBuf(CAN_Type* base) +{ + return CAN_ESR2_REG(base); +} + +/*! + * @brief Set the Tx Arbitration Start Delay number. + * This function is used to optimize the transmit performance. + * For more information about to set this value, see the Chip Reference Manual. + * + * @param base FlexCAN base pointer. + * @param tasd The lowest number inactive Mailbox. + */ +static inline void FLEXCAN_SetTxArbitrationStartDelay(CAN_Type* base, uint8_t tasd) +{ + assert(tasd < 32); + CAN_CTRL2_REG(base) = (CAN_CTRL2_REG(base) & ~CAN_CTRL2_TASD_MASK) | CAN_CTRL2_TASD(tasd); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +#endif /* __FLEXCAN_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/gpio_imx.c b/zephyr/imx/drivers/gpio_imx.c new file mode 100644 index 000000000..ffefaf203 --- /dev/null +++ b/zephyr/imx/drivers/gpio_imx.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "gpio_imx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * GPIO Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : GPIO_Init + * Description : Initializes the GPIO module according to the specified + * parameters in the initConfig. + * + *END**************************************************************************/ +void GPIO_Init(GPIO_Type* base, const gpio_init_config_t* initConfig) +{ + uint32_t pin; + volatile uint32_t *icr; + + /* Register reset to default value */ + GPIO_IMR_REG(base) = 0; + GPIO_EDGE_SEL_REG(base) = 0; + + /* Get pin number */ + pin = initConfig->pin; + + /* Configure GPIO pin direction */ + if (initConfig->direction == gpioDigitalOutput) + GPIO_GDIR_REG(base) |= (1U << pin); + else + GPIO_GDIR_REG(base) &= ~(1U << pin); + + /* Configure GPIO pin interrupt mode */ + if(pin < 16) + icr = &GPIO_ICR1_REG(base); + else + { + icr = &GPIO_ICR2_REG(base); + pin -= 16; + } + switch(initConfig->interruptMode) + { + case(gpioIntLowLevel): + { + *icr &= ~(0x3<<(2*pin)); + break; + } + case(gpioIntHighLevel): + { + *icr = (*icr & (~(0x3<<(2*pin)))) | (0x1<<(2*pin)); + break; + } + case(gpioIntRisingEdge): + { + *icr = (*icr & (~(0x3<<(2*pin)))) | (0x2<<(2*pin)); + break; + } + case(gpioIntFallingEdge): + { + *icr |= (0x3<<(2*pin)); + break; + } + case(gpioNoIntmode): + { + break; + } + } +} + +/******************************************************************************* + * GPIO Read and Write Functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : GPIO_WritePinOutput + * Description : Sets the output level of the individual GPIO pin. + * + *END**************************************************************************/ +void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal) +{ + assert(pin < 32); + if (pinVal == gpioPinSet) + { + GPIO_DR_REG(base) |= (1U << pin); /* Set pin output to high level.*/ + } + else + { + GPIO_DR_REG(base) &= ~(1U << pin); /* Set pin output to low level.*/ + } +} + +/******************************************************************************* + * Interrupts and flags management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : GPIO_SetPinIntMode + * Description : Enable or Disable the specific pin interrupt. + * + *END**************************************************************************/ +void GPIO_SetPinIntMode(GPIO_Type* base, uint32_t pin, bool enable) +{ + assert(pin < 32); + + if(enable) + GPIO_IMR_REG(base) |= (1U << pin); + else + GPIO_IMR_REG(base) &= ~(1U << pin); +} + +/*FUNCTION********************************************************************** + * + * Function Name : GPIO_SetIntEdgeSelect + * Description : Enable or Disable the specific pin interrupt. + * + *END**************************************************************************/ + +void GPIO_SetIntEdgeSelect(GPIO_Type* base, uint32_t pin, bool enable) +{ + assert(pin < 32); + + if(enable) + GPIO_EDGE_SEL_REG(base) |= (1U << pin); + else + GPIO_EDGE_SEL_REG(base) &= ~(1U << pin); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/gpio_imx.h b/zephyr/imx/drivers/gpio_imx.h new file mode 100644 index 000000000..1af7cebfe --- /dev/null +++ b/zephyr/imx/drivers/gpio_imx.h @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GPIO_IMX_H__ +#define __GPIO_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + gpioDigitalInput = 0U, /*!< Set current pin as digital input.*/ + gpioDigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + gpioIntLowLevel = 0U, /*!< Set current pin interrupt is low-level sensitive.*/ + gpioIntHighLevel = 1U, /*!< Set current pin interrupt is high-level sensitive.*/ + gpioIntRisingEdge = 2U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + gpioIntFallingEdge = 3U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + gpioNoIntmode = 4U, /*!< Set current pin general IO functionality. */ +} gpio_interrupt_mode_t; + +/*! @brief GPIO pin(bit) value definition. */ +typedef enum _gpio_pin_action +{ + gpioPinClear = 0U, /*!< Clear GPIO Pin.*/ + gpioPinSet = 1U, /*!< Set GPIO Pin.*/ +} gpio_pin_action_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_init_config +{ + uint32_t pin; /*!< Specifies the pin number. */ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + gpio_interrupt_mode_t interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param initConfig pointer to a @ref gpio_init_config_t structure that + * contains the configuration information. + */ +void GPIO_Init(GPIO_Type* base, const gpio_init_config_t* initConfig); + +/*@}*/ + +/*! + * @name GPIO Read and Write Functions + * @{ + */ + +/*! + * @brief Reads the current input value of the pin when pin's direction is configured as input. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @return GPIO pin input value. + */ +static inline uint8_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)((GPIO_DR_REG(base) >> pin) & 1U); +} + +/*! + * @brief Reads the current input value of a specific GPIO port when port's direction are all configured as input. + * This function gets all 32-pin input as a 32-bit integer. + * + * @param base GPIO base pointer. + * @return GPIO port input data. + */ +static inline uint32_t GPIO_ReadPortInput(GPIO_Type* base) +{ + return GPIO_DR_REG(base); +} + +/*! + * @brief Reads the current pin output. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @return Current pin output value. + */ +static inline uint8_t GPIO_ReadPinOutput(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)((GPIO_DR_REG(base) >> pin) & 0x1U); +} + +/*! + * @brief Reads out all pin output status of the current port. + * This function operates all 32 port pins. + * + * @param base GPIO base pointer. + * @return Current port output status. + */ +static inline uint32_t GPIO_ReadPortOutput(GPIO_Type* base) +{ + return GPIO_DR_REG(base); +} + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pinVal pin output value (See @ref gpio_pin_action_t structure). + */ +void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal); + +/*! + * @brief Sets the output of the GPIO port pins to a specific logic value. + * This function operates all 32 port pins. + * + * @param base GPIO base pointer. + * @param portVal data to configure the GPIO output. + */ +static inline void GPIO_WritePortOutput(GPIO_Type* base, uint32_t portVal) +{ + GPIO_DR_REG(base) = portVal; +} + +/*@}*/ + +/*! + * @name GPIO Read Pad Status Functions + * @{ + */ + + /*! + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @return GPIO pin pad status value. + */ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)((GPIO_PSR_REG(base) >> pin) & 1U); +} + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Enable or Disable the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param pin GPIO pin number. + * @param enable Enable or disable interrupt. + * - true: Enable GPIO interrupt. + * - false: Disable GPIO interrupt. + */ +void GPIO_SetPinIntMode(GPIO_Type* base, uint32_t pin, bool enable); + +/*! + * @brief Check individual pin interrupt status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @return current pin interrupt status flag. + */ +static inline bool GPIO_IsIntPending(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (bool)((GPIO_ISR_REG(base) >> pin) & 1U); +} + +/*! + * @brief Clear pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + */ +static inline void GPIO_ClearStatusFlag(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + GPIO_ISR_REG(base) = (1U << pin); +} + +/*! + * @brief Enable or disable the edge select bit to override + * the ICR register's configuration. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param enable Enable or disable edge select bit. + */ +void GPIO_SetIntEdgeSelect(GPIO_Type* base, uint32_t pin, bool enable); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __GPIO_IMX_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/gpt.c b/zephyr/imx/drivers/gpt.c new file mode 100644 index 000000000..6c6d12c93 --- /dev/null +++ b/zephyr/imx/drivers/gpt.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "gpt.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : GPT_Init + * Description : Initialize GPT to reset state and initialize running mode + * + *END**************************************************************************/ +void GPT_Init(GPT_Type* base, const gpt_init_config_t* initConfig) +{ + assert(initConfig); + + base->CR = 0; + + GPT_SoftReset(base); + + base->CR = (initConfig->freeRun ? GPT_CR_FRR_MASK : 0) | + (initConfig->waitEnable ? GPT_CR_WAITEN_MASK : 0) | + (initConfig->stopEnable ? GPT_CR_STOPEN_MASK : 0) | + (initConfig->dozeEnable ? GPT_CR_DOZEEN_MASK : 0) | + (initConfig->dbgEnable ? GPT_CR_DBGEN_MASK : 0) | + (initConfig->enableMode ? GPT_CR_ENMOD_MASK : 0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : GPT_SetClockSource + * Description : Set clock source of GPT + * + *END**************************************************************************/ +void GPT_SetClockSource(GPT_Type* base, uint32_t source) +{ + assert(source <= gptClockSourceOsc); + + if (source == gptClockSourceOsc) + base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(source); + else + base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(source); +} + +/*FUNCTION********************************************************************** + * + * Function Name : GPT_SetIntCmd + * Description : Enable or disable GPT interrupts + * + *END**************************************************************************/ +void GPT_SetIntCmd(GPT_Type* base, uint32_t flags, bool enable) +{ + if (enable) + base->IR |= flags; + else + base->IR &= ~flags; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/gpt.h b/zephyr/imx/drivers/gpt.h new file mode 100644 index 000000000..3c95c1bc8 --- /dev/null +++ b/zephyr/imx/drivers/gpt.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GPT_H__ +#define __GPT_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup gpt_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Clock source. */ +enum _gpt_clock_source +{ + gptClockSourceNone = 0U, /*!< No source selected.*/ + gptClockSourcePeriph = 1U, /*!< Use peripheral module clock.*/ + gptClockSourceLowFreq = 4U, /*!< Use 32 K clock.*/ + gptClockSourceOsc = 5U, /*!< Use 24 M OSC clock.*/ +}; + +/*! @brief Input capture channel number. */ +enum _gpt_input_capture_channel +{ + gptInputCaptureChannel1 = 0U, /*!< Input Capture Channel1.*/ + gptInputCaptureChannel2 = 1U, /*!< Input Capture Channel2.*/ +}; + +/*! @brief Input capture operation mode. */ +enum _gpt_input_operation_mode +{ + gptInputOperationDisabled = 0U, /*!< Don't capture.*/ + gptInputOperationRiseEdge = 1U, /*!< Capture on rising edge of input pin.*/ + gptInputOperationFallEdge = 2U, /*!< Capture on falling edge of input pin.*/ + gptInputOperationBothEdge = 3U, /*!< Capture on both edges of input pin.*/ +}; + +/*! @brief Output compare channel number. */ +enum _gpt_output_compare_channel +{ + gptOutputCompareChannel1 = 0U, /*!< Output Compare Channel1.*/ + gptOutputCompareChannel2 = 1U, /*!< Output Compare Channel2.*/ + gptOutputCompareChannel3 = 2U, /*!< Output Compare Channel3.*/ +}; + +/*! @brief Output compare operation mode. */ +enum _gpt_output_operation_mode +{ + gptOutputOperationDisconnected = 0U, /*!< Don't change output pin.*/ + gptOutputOperationToggle = 1U, /*!< Toggle output pin.*/ + gptOutputOperationClear = 2U, /*!< Set output pin low.*/ + gptOutputOperationSet = 3U, /*!< Set output pin high.*/ + gptOutputOperationActivelow = 4U, /*!< Generate a active low pulse on output pin.*/ +}; + +/*! @brief Status flag. */ +enum _gpt_status_flag +{ + gptStatusFlagOutputCompare1 = 1U << 0, /*!< Output compare channel 1 event.*/ + gptStatusFlagOutputCompare2 = 1U << 1, /*!< Output compare channel 2 event.*/ + gptStatusFlagOutputCompare3 = 1U << 2, /*!< Output compare channel 3 event.*/ + gptStatusFlagInputCapture1 = 1U << 3, /*!< Capture channel 1 event.*/ + gptStatusFlagInputCapture2 = 1U << 4, /*!< Capture channel 2 event.*/ + gptStatusFlagRollOver = 1U << 5, /*!< Counter reaches maximum value and rolled over to 0 event.*/ +}; + +/*! @brief Structure to configure the running mode. */ +typedef struct _gpt_init_config +{ + bool freeRun; /*!< true: FreeRun mode, false: Restart mode. */ + bool waitEnable; /*!< GPT enabled in wait mode. */ + bool stopEnable; /*!< GPT enabled in stop mode. */ + bool dozeEnable; /*!< GPT enabled in doze mode. */ + bool dbgEnable; /*!< GPT enabled in debug mode. */ + bool enableMode; /*!< true: counter reset to 0 when enabled, false: counter retain its value when enabled. */ +} gpt_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPT State Control + * @{ + */ + +/*! + * @brief Initialize GPT to reset state and initialize running mode. + * + * @param base GPT base pointer. + * @param initConfig GPT mode setting configuration. + */ +void GPT_Init(GPT_Type* base, const gpt_init_config_t* initConfig); + +/*! + * @brief Software reset of GPT module. + * + * @param base GPT base pointer. + */ +static inline void GPT_SoftReset(GPT_Type* base) +{ + base->CR |= GPT_CR_SWR_MASK; + /* Wait reset finished. */ + while (base->CR & GPT_CR_SWR_MASK) {}; +} + +/*! + * @brief Set clock source of GPT. + * + * @param base GPT base pointer. + * @param source Clock source (see @ref _gpt_clock_source enumeration). + */ +void GPT_SetClockSource(GPT_Type* base, uint32_t source); + +/*! + * @brief Get clock source of GPT. + * + * @param base GPT base pointer. + * @return clock source (see @ref _gpt_clock_source enumeration). + */ +static inline uint32_t GPT_GetClockSource(GPT_Type* base) +{ + return (base->CR & GPT_CR_CLKSRC_MASK) >> GPT_CR_CLKSRC_SHIFT; +} + +/*! + * @brief Set pre scaler of GPT. + * + * @param base GPT base pointer. + * @param prescaler Pre-scaler of GPT (0-4095, divider = prescaler + 1). + */ +static inline void GPT_SetPrescaler(GPT_Type* base, uint32_t prescaler) +{ + assert(prescaler <= GPT_PR_PRESCALER_MASK); + + base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(prescaler); +} + +/*! + * @brief Get pre scaler of GPT. + * + * @param base GPT base pointer. + * @return pre scaler of GPT (0-4095). + */ +static inline uint32_t GPT_GetPrescaler(GPT_Type* base) +{ + return (base->PR & GPT_PR_PRESCALER_MASK) >> GPT_PR_PRESCALER_SHIFT; +} + +/*! + * @brief OSC 24M pre-scaler before selected by clock source. + * + * @param base GPT base pointer. + * @param prescaler OSC pre-scaler(0-15, divider = prescaler + 1). + */ +static inline void GPT_SetOscPrescaler(GPT_Type* base, uint32_t prescaler) +{ + assert(prescaler <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)); + + base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(prescaler); +} + +/*! + * @brief Get pre-scaler of GPT. + * + * @param base GPT base pointer. + * @return OSC pre scaler of GPT (0-15). + */ +static inline uint32_t GPT_GetOscPrescaler(GPT_Type* base) +{ + return (base->PR & GPT_PR_PRESCALER24M_MASK) >> GPT_PR_PRESCALER24M_SHIFT; +} + +/*! + * @brief Enable GPT module. + * + * @param base GPT base pointer. + */ +static inline void GPT_Enable(GPT_Type* base) +{ + base->CR |= GPT_CR_EN_MASK; +} + +/*! + * @brief Disable GPT module. + * + * @param base GPT base pointer. + */ +static inline void GPT_Disable(GPT_Type* base) +{ + base->CR &= ~GPT_CR_EN_MASK; +} + +/*! + * @brief Get GPT counter value. + * + * @param base GPT base pointer. + * @return GPT counter value. + */ +static inline uint32_t GPT_ReadCounter(GPT_Type* base) +{ + return base->CNT; +} + +/*@}*/ + +/*! + * @name GPT Input/Output Signal Control + * @{ + */ + +/*! + * @brief Set GPT operation mode of input capture channel. + * + * @param base GPT base pointer. + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @param mode GPT input capture operation mode (see @ref _gpt_input_operation_mode enumeration). + */ +static inline void GPT_SetInputOperationMode(GPT_Type* base, uint32_t channel, uint32_t mode) +{ + assert (channel <= gptInputCaptureChannel2); + + base->CR = (base->CR & ~(GPT_CR_IM1_MASK << (channel * 2))) | (GPT_CR_IM1(mode) << (channel * 2)); +} + +/*! + * @brief Get GPT operation mode of input capture channel. + * + * @param base GPT base pointer. + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @return GPT input capture operation mode (see @ref _gpt_input_operation_mode enumeration). + */ +static inline uint32_t GPT_GetInputOperationMode(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptInputCaptureChannel2); + + return (base->CR >> (GPT_CR_IM1_SHIFT + channel * 2)) & (GPT_CR_IM1_MASK >> GPT_CR_IM1_SHIFT); +} + +/*! + * @brief Get GPT input capture value of certain channel. + * + * @param base GPT base pointer. + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @return GPT input capture value. + */ +static inline uint32_t GPT_GetInputCaptureValue(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptInputCaptureChannel2); + + return *(&base->ICR1 + channel); +} + +/*! + * @brief Set GPT operation mode of output compare channel. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @param mode GPT output operation mode (see @ref _gpt_output_operation_mode enumeration). + */ +static inline void GPT_SetOutputOperationMode(GPT_Type* base, uint32_t channel, uint32_t mode) +{ + assert (channel <= gptOutputCompareChannel3); + + base->CR = (base->CR & ~(GPT_CR_OM1_MASK << (channel * 3))) | (GPT_CR_OM1(mode) << (channel * 3)); +} + +/*! + * @brief Get GPT operation mode of output compare channel. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @return GPT output operation mode (see @ref _gpt_output_operation_mode enumeration). + */ +static inline uint32_t GPT_GetOutputOperationMode(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptOutputCompareChannel3); + + return (base->CR >> (GPT_CR_OM1_SHIFT + channel * 3)) & (GPT_CR_OM1_MASK >> GPT_CR_OM1_SHIFT); +} + +/*! + * @brief Set GPT output compare value of output compare channel. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @param value GPT output compare value. + */ +static inline void GPT_SetOutputCompareValue(GPT_Type* base, uint32_t channel, uint32_t value) +{ + assert (channel <= gptOutputCompareChannel3); + + *(&base->OCR1 + channel) = value; +} + +/*! + * @brief Get GPT output compare value of output compare channel. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @return GPT output compare value. + */ +static inline uint32_t GPT_GetOutputCompareValue(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptOutputCompareChannel3); + + return *(&base->OCR1 + channel); +} + +/*! + * @brief Force GPT output action on output compare channel, ignoring comparator. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + */ +static inline void GPT_ForceOutput(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptOutputCompareChannel3); + + base->CR |= (GPT_CR_FO1_MASK << channel); +} + +/*@}*/ + +/*! + * @name GPT Interrupt and Status Control + * @{ + */ + +/*! + * @brief Get GPT status flag. + * + * @param base GPT base pointer. + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). + * @return GPT status, each bit represents one status flag. + */ +static inline uint32_t GPT_GetStatusFlag(GPT_Type* base, uint32_t flags) +{ + return base->SR & flags; +} + +/*! + * @brief Clear one or more GPT status flag. + * + * @param base GPT base pointer. + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). + */ +static inline void GPT_ClearStatusFlag(GPT_Type* base, uint32_t flags) +{ + base->SR = flags; +} + +/*! + * @brief Enable or Disable GPT interrupts. + * + * @param base GPT base pointer. + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). + * @param enable Enable/Disable GPT interrupts. + * -true: Enable GPT interrupts. + * -false: Disable GPT interrupts. + */ +void GPT_SetIntCmd(GPT_Type* base, uint32_t flags, bool enable); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __GPT_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/i2c_imx.c b/zephyr/imx/drivers/i2c_imx.c new file mode 100644 index 000000000..1d7dc0202 --- /dev/null +++ b/zephyr/imx/drivers/i2c_imx.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "i2c_imx.h" + +/******************************************************************************* + * Constant + ******************************************************************************/ +static const uint32_t i2cClkDivTab[][2] = +{ + {22, 0x20}, {24, 0x21}, {26, 0x22}, {28, 0x23}, {30, 0x00}, {32, 0x24}, {36, 0x25}, {40, 0x26}, + {42, 0x03}, {44, 0x27}, {48, 0x28}, {52, 0x05}, {56, 0x29}, {60, 0x06}, {64, 0x2A}, {72, 0x2B}, + {80, 0x2C}, {88, 0x09}, {96, 0x2D}, {104, 0x0A}, {112, 0x2E}, {128, 0x2F}, {144, 0x0C}, {160, 0x30}, + {192, 0x31}, {224, 0x32}, {240, 0x0F}, {256, 0x33}, {288, 0x10}, {320, 0x34}, {384, 0x35}, {448, 0x36}, + {480, 0x13}, {512, 0x37}, {576, 0x14}, {640, 0x38}, {768, 0x39}, {896, 0x3A}, {960, 0x17}, {1024, 0x3B}, + {1152, 0x18}, {1280, 0x3C}, {1536, 0x3D}, {1792, 0x3E}, {1920, 0x1B}, {2048, 0x3F}, {2304, 0x1C}, {2560, 0x1D}, + {3072, 0x1E}, {3840, 0x1F} +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * I2C Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : I2C_Init + * Description : Initialize I2C module with given initialize structure. + * + *END**************************************************************************/ +void I2C_Init(I2C_Type* base, const i2c_init_config_t* initConfig) +{ + assert(initConfig); + + /* Disable I2C Module. */ + I2C_I2CR_REG(base) &= ~I2C_I2CR_IEN_MASK; + + /* Reset I2C register to its default value. */ + I2C_Deinit(base); + + /* Set I2C Module own Slave Address. */ + I2C_SetSlaveAddress(base, initConfig->slaveAddress); + + /* Set I2C BaudRate according to i2c initialize struct. */ + I2C_SetBaudRate(base, initConfig->clockRate, initConfig->baudRate); +} + +/*FUNCTION********************************************************************** + * + * Function Name : I2C_Deinit + * Description : This function reset I2C module register content to + * its default value. + * + *END**************************************************************************/ +void I2C_Deinit(I2C_Type* base) +{ + /* Disable I2C Module */ + I2C_I2CR_REG(base) &= ~I2C_I2CR_IEN_MASK; + + /* Reset I2C Module Register content to default value */ + I2C_IADR_REG(base) = 0x0; + I2C_IFDR_REG(base) = 0x0; + I2C_I2CR_REG(base) = 0x0; +} + +/*FUNCTION********************************************************************** + * + * Function Name : I2C_SetBaudRate + * Description : This function is used to set the baud rate of I2C Module. + * + *END**************************************************************************/ +void I2C_SetBaudRate(I2C_Type* base, uint32_t clockRate, uint32_t baudRate) +{ + uint32_t clockDiv; + uint8_t clkDivIndex = 0; + + assert(baudRate <= 400000); + + /* Calculate accurate baudRate divider. */ + clockDiv = clockRate / baudRate; + + if (clockDiv < i2cClkDivTab[0][0]) + { + /* If clock divider is too small, using smallest legal divider */ + clkDivIndex = 0; + } + else if (clockDiv > i2cClkDivTab[sizeof(i2cClkDivTab)/sizeof(i2cClkDivTab[0]) - 1][0]) + { + /* If clock divider is too large, using largest legal divider */ + clkDivIndex = sizeof(i2cClkDivTab)/sizeof(i2cClkDivTab[0]) - 1; + } + else + { + while (i2cClkDivTab[clkDivIndex][0] < clockDiv) + clkDivIndex++; + } + + I2C_IFDR_REG(base) = i2cClkDivTab[clkDivIndex][1]; +} + +/******************************************************************************* + * I2C Bus Control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : I2C_SetAckBit + * Description : This function is used to set the Transmit Acknowledge + * action when receive data from other device. + * + *END**************************************************************************/ +void I2C_SetAckBit(I2C_Type* base, bool ack) +{ + if (ack) + I2C_I2CR_REG(base) &= ~I2C_I2CR_TXAK_MASK; + else + I2C_I2CR_REG(base) |= I2C_I2CR_TXAK_MASK; +} + +/******************************************************************************* + * Interrupts and flags management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : I2C_SetIntCmd + * Description : Enables or disables I2C interrupt requests. + * + *END**************************************************************************/ +void I2C_SetIntCmd(I2C_Type* base, bool enable) +{ + if (enable) + I2C_I2CR_REG(base) |= I2C_I2CR_IIEN_MASK; + else + I2C_I2CR_REG(base) &= ~I2C_I2CR_IIEN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/i2c_imx.h b/zephyr/imx/drivers/i2c_imx.h new file mode 100644 index 000000000..f5a2d2ad2 --- /dev/null +++ b/zephyr/imx/drivers/i2c_imx.h @@ -0,0 +1,284 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __I2C_IMX_H__ +#define __I2C_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup i2c_imx_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief I2C module initialization structure. */ +typedef struct _i2c_init_config +{ + uint32_t clockRate; /*!< Current I2C module clock freq. */ + uint32_t baudRate; /*!< Desired I2C baud rate. */ + uint8_t slaveAddress; /*!< I2C module's own address when addressed as slave device. */ +} i2c_init_config_t; + +/*! @brief Flag for I2C interrupt status check or polling status. */ +enum _i2c_status_flag +{ + i2cStatusTransferComplete = I2C_I2SR_ICF_MASK, /*!< Data Transfer complete flag. */ + i2cStatusAddressedAsSlave = I2C_I2SR_IAAS_MASK, /*!< Addressed as a slave flag. */ + i2cStatusBusBusy = I2C_I2SR_IBB_MASK, /*!< Bus is busy flag. */ + i2cStatusArbitrationLost = I2C_I2SR_IAL_MASK, /*!< Arbitration is lost flag. */ + i2cStatusSlaveReadWrite = I2C_I2SR_SRW_MASK, /*!< Master reading from slave flag(De-assert if master writing to slave). */ + i2cStatusInterrupt = I2C_I2SR_IIF_MASK, /*!< An interrupt is pending flag. */ + i2cStatusReceivedAck = I2C_I2SR_RXAK_MASK, /*!< No acknowledge detected flag. */ +}; + +/*! @brief I2C Bus role of this module. */ +enum _i2c_work_mode +{ + i2cModeSlave = 0x0, /*!< This module works as I2C Slave. */ + i2cModeMaster = I2C_I2CR_MSTA_MASK, /*!< This module works as I2C Master. */ +}; + +/*! @brief Data transfer direction. */ +enum _i2c_direction_mode +{ + i2cDirectionReceive = 0x0, /*!< This module works at receive mode. */ + i2cDirectionTransmit = I2C_I2CR_MTX_MASK, /*!< This module works at transmit mode. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name I2C Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initialize I2C module with given initialization structure. + * + * @param base I2C base pointer. + * @param initConfig I2C initialization structure (see @ref i2c_init_config_t). + */ +void I2C_Init(I2C_Type* base, const i2c_init_config_t* initConfig); + +/*! + * @brief This function reset I2C module register content to its default value. + * + * @param base I2C base pointer. + */ +void I2C_Deinit(I2C_Type* base); + +/*! + * @brief This function is used to Enable the I2C Module. + * + * @param base I2C base pointer. + */ +static inline void I2C_Enable(I2C_Type* base) +{ + I2C_I2CR_REG(base) |= I2C_I2CR_IEN_MASK; +} + +/*! + * @brief This function is used to Disable the I2C Module. + * + * @param base I2C base pointer. + */ +static inline void I2C_Disable(I2C_Type* base) +{ + I2C_I2CR_REG(base) &= ~I2C_I2CR_IEN_MASK; +} + +/*! + * @brief This function is used to set the baud rate of I2C Module. + * + * @param base I2C base pointer. + * @param clockRate I2C module clock frequency. + * @param baudRate Desired I2C module baud rate. + */ +void I2C_SetBaudRate(I2C_Type* base, uint32_t clockRate, uint32_t baudRate); + +/*! + * @brief This function is used to set the own I2C bus address when addressed as a slave. + * + * @param base I2C base pointer. + * @param slaveAddress Own I2C Bus address. + */ +static inline void I2C_SetSlaveAddress(I2C_Type* base, uint8_t slaveAddress) +{ + assert(slaveAddress < 0x80); + + I2C_IADR_REG(base) = (I2C_IADR_REG(base) & ~I2C_IADR_ADR_MASK) | I2C_IADR_ADR(slaveAddress); +} + +/*! + * @name I2C Bus Control functions + * @{ + */ + +/*! + * @brief This function is used to Generate a Repeat Start Signal on I2C Bus. + * + * @param base I2C base pointer. + */ +static inline void I2C_SendRepeatStart(I2C_Type* base) +{ + I2C_I2CR_REG(base) |= I2C_I2CR_RSTA_MASK; +} + +/*! + * @brief This function is used to select the I2C bus role of this module, + * both I2C Bus Master and Slave can be select. + * + * @param base I2C base pointer. + * @param mode I2C Bus role to set (see @ref _i2c_work_mode enumeration). + */ +static inline void I2C_SetWorkMode(I2C_Type* base, uint32_t mode) +{ + assert((mode == i2cModeMaster) || (mode == i2cModeSlave)); + + I2C_I2CR_REG(base) = (I2C_I2CR_REG(base) & ~I2C_I2CR_MSTA_MASK) | mode; +} + +/*! + * @brief This function is used to select the data transfer direction of this module, + * both Transmit and Receive can be select. + * + * @param base I2C base pointer. + * @param direction I2C Bus data transfer direction (see @ref _i2c_direction_mode enumeration). + */ +static inline void I2C_SetDirMode(I2C_Type* base, uint32_t direction) +{ + assert((direction == i2cDirectionReceive) || (direction == i2cDirectionTransmit)); + + I2C_I2CR_REG(base) = (I2C_I2CR_REG(base) & ~I2C_I2CR_MTX_MASK) | direction; +} + +/*! + * @brief This function is used to set the Transmit Acknowledge action when receive + * data from other device. + * + * @param base I2C base pointer. + * @param ack The ACK value answerback to remote I2C device. + * - true: An acknowledge signal is sent to the bus at the ninth clock bit. + * - false: No acknowledge signal response is sent. + */ +void I2C_SetAckBit(I2C_Type* base, bool ack); + +/*! + * @name Data transfers functions + * @{ + */ + +/*! + * @brief Writes one byte of data to the I2C bus. + * + * @param base I2C base pointer. + * @param byte The byte of data to transmit. + */ +static inline void I2C_WriteByte(I2C_Type* base, uint8_t byte) +{ + I2C_I2DR_REG(base) = byte; +} + +/*! + * @brief Returns the last byte of data read from the bus and initiate another read. + * + * In a master receive mode, calling this function initiates receiving the next byte of data. + * + * @param base I2C base pointer. + * @return This function returns the last byte received while the I2C module is configured in master + * receive or slave receive mode. + */ +static inline uint8_t I2C_ReadByte(I2C_Type* base) +{ + return (uint8_t)(I2C_I2DR_REG(base) & I2C_I2DR_DATA_MASK); +} + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Enable or disable I2C interrupt requests. + * + * @param base I2C base pointer. + * @param enable Enable/Disbale I2C interrupt. + * - true: Enable I2C interrupt. + * - false: Disable I2C interrupt. + */ +void I2C_SetIntCmd(I2C_Type* base, bool enable); + +/*! + * @brief Gets the I2C status flag state. + * + * @param base I2C base pointer. + * @param flags I2C status flag mask (see @ref _i2c_status_flag enumeration.) + * @return I2C status, each bit represents one status flag + */ +static inline uint32_t I2C_GetStatusFlag(I2C_Type* base, uint32_t flags) +{ + return (I2C_I2SR_REG(base) & flags); +} + +/*! + * @brief Clear one or more I2C status flag state. + * + * @param base I2C base pointer. + * @param flags I2C status flag mask (see @ref _i2c_status_flag enumeration.) + */ +static inline void I2C_ClearStatusFlag(I2C_Type* base, uint32_t flags) +{ + /* Write 0 to clear. */ + I2C_I2SR_REG(base) &= ~flags; +} + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __I2C_IMX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/lmem.c b/zephyr/imx/drivers/lmem.c new file mode 100644 index 000000000..4245599e9 --- /dev/null +++ b/zephyr/imx/drivers/lmem.c @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "lmem.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define LMEM_CACHE_LINE_SIZE 32 + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * System Cache control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_EnableSystemCache + * Description : This function enable the System Cache. + * + *END**************************************************************************/ +void LMEM_EnableSystemCache(LMEM_Type *base) +{ + /* set command to invalidate all ways */ + /* and write GO bit to initiate command */ + LMEM_PSCCR_REG(base) = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); + + /* Enable cache, enable write buffer */ + LMEM_PSCCR_REG(base) = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_DisableSystemCache + * Description : This function disable the System Cache. + * + *END**************************************************************************/ +void LMEM_DisableSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) = 0x0; + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCache + * Description : This function flush the System Cache. + * + *END**************************************************************************/ +void LMEM_FlushSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK ; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCacheLine + * Description : This function is called to push a line out of the System Cache. + * + *END**************************************************************************/ +static void LMEM_FlushSystemCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address >= 0x20000000); + + /* Invalidate by physical address */ + LMEM_PSCLCR_REG(base) = LMEM_PSCLCR_LADSEL_MASK | LMEM_PSCLCR_LCMD(2); + /* Set physical address and activate command */ + LMEM_PSCSAR_REG(base) = ((uint32_t)address & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCSAR_REG(base) & LMEM_PSCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCacheLines + * Description : This function is called to flush the System Cache by + * performing cache copy-backs. It must determine how + * many cache lines need to be copied back and then + * perform the copy-backs. + * + *END**************************************************************************/ +void LMEM_FlushSystemCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + + address = (void *) ((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + do + { + LMEM_FlushSystemCacheLine(base, address); + address = (void *) ((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCache + * Description : This function invalidate the System Cache. + * + *END**************************************************************************/ +void LMEM_InvalidateSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCacheLine + * Description : This function is called to invalidate a line out of + * the System Cache. + * + *END**************************************************************************/ +static void LMEM_InvalidateSystemCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address >= 0x20000000); + + /* Invalidate by physical address */ + LMEM_PSCLCR_REG(base) = LMEM_PSCLCR_LADSEL_MASK | LMEM_PSCLCR_LCMD(1); + /* Set physical address and activate command */ + LMEM_PSCSAR_REG(base) = ((uint32_t)address & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCSAR_REG(base) & LMEM_PSCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCacheLines + * Description : This function is responsible for performing an data + * cache invalidate. It must determine how many cache + * lines need to be invalidated and then perform the + * invalidation. + * + *END**************************************************************************/ +void LMEM_InvalidateSystemCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + address = (void *)((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + + do + { + LMEM_InvalidateSystemCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_EnableCodeCache + * Description : This function enable the Code Cache. + * + *END**************************************************************************/ +void LMEM_EnableCodeCache(LMEM_Type *base) +{ + /* set command to invalidate all ways, enable write buffer */ + /* and write GO bit to initiate command */ + LMEM_PCCCR_REG(base) = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); + + /* Enable cache, enable write buffer */ + LMEM_PCCCR_REG(base) = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_DisableCodeCache + * Description : This function disable the Code Cache. + * + *END**************************************************************************/ +void LMEM_DisableCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) = 0x0; + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCache + * Description : This function flush the Code Cache. + * + *END**************************************************************************/ +void LMEM_FlushCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCacheLine + * Description : This function is called to push a line out of the + * Code Cache. + * + *END**************************************************************************/ +static void LMEM_FlushCodeCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address < 0x20000000); + + /* Invalidate by physical address */ + LMEM_PCCLCR_REG(base) = LMEM_PCCLCR_LADSEL_MASK | LMEM_PCCLCR_LCMD(2); + /* Set physical address and activate command */ + LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCSAR_REG(base) & LMEM_PCCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCacheLines + * Description : This function is called to flush the instruction + * cache by performing cache copy-backs. It must + * determine how many cache lines need to be copied + * back and then perform the copy-backs. + * + *END**************************************************************************/ +void LMEM_FlushCodeCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + + address = (void *) ((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + do + { + LMEM_FlushCodeCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCache + * Description : This function invalidate the Code Cache. + * + *END**************************************************************************/ +void LMEM_InvalidateCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCacheLine + * Description : This function is called to invalidate a line out + * of the Code Cache. + * + *END**************************************************************************/ +static void LMEM_InvalidateCodeCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address < 0x20000000); + + /* Invalidate by physical address */ + LMEM_PCCLCR_REG(base) = LMEM_PCCLCR_LADSEL_MASK | LMEM_PCCLCR_LCMD(1); + /* Set physical address and activate command */ + LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCSAR_REG(base) & LMEM_PCCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCacheLines + * Description : This function is responsible for performing an + * Code Cache invalidate. It must determine + * how many cache lines need to be invalidated and then + * perform the invalidation. + * + *END**************************************************************************/ +void LMEM_InvalidateCodeCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + address = (void *)((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + + do + { + LMEM_InvalidateCodeCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); + __ISB(); + __DSB(); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/lmem.h b/zephyr/imx/drivers/lmem.h new file mode 100644 index 000000000..be4d8599c --- /dev/null +++ b/zephyr/imx/drivers/lmem.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __LMEM_H__ +#define __LMEM_H__ + +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup lmem_driver + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Processor System Cache control functions + * @{ + */ + +/*! + * @brief This function enable the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_EnableSystemCache(LMEM_Type *base); + +/*! + * @brief This function disable the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_DisableSystemCache(LMEM_Type *base); + +/*! + * @brief This function flush the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_FlushSystemCache(LMEM_Type *base); + +/*! + * @brief This function is called to flush the System Cache by performing cache copy-backs. + * It must determine how many cache lines need to be copied back and then + * perform the copy-backs. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of flush address space. + */ +void LMEM_FlushSystemCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*! + * @brief This function invalidate the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_InvalidateSystemCache(LMEM_Type *base); + +/*! + * @brief This function is responsible for performing an System Cache invalidate. + * It must determine how many cache lines need to be invalidated and then + * perform the invalidation. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of invalidate address space. + */ +void LMEM_InvalidateSystemCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*@}*/ + +/*! + * @name Processor Code Cache control functions + * @{ + */ + +/*! + * @brief This function enable the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_EnableCodeCache(LMEM_Type *base); + +/*! + * @brief This function disable the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_DisableCodeCache(LMEM_Type *base); + +/*! + * @brief This function flush the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_FlushCodeCache(LMEM_Type *base); + +/*! + * @brief This function is called to flush the Code Cache by performing cache copy-backs. + * It must determine how many cache lines need to be copied back and then + * perform the copy-backs. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of flush address space. + */ +void LMEM_FlushCodeCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*! + * @brief This function invalidate the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_InvalidateCodeCache(LMEM_Type *base); + +/*! + * @brief This function is responsible for performing an Code Cache invalidate. + * It must determine how many cache lines need to be invalidated and then + * perform the invalidation. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of invalidate address space. + */ +void LMEM_InvalidateCodeCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __LMEM_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/mu_imx.c b/zephyr/imx/drivers/mu_imx.c new file mode 100644 index 000000000..7a142fede --- /dev/null +++ b/zephyr/imx/drivers/mu_imx.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "mu_imx.h" + +/*FUNCTION********************************************************************** + * + * Function Name : MU_TrySendMsg + * Description : Try to send message to the other core. + * + *END**************************************************************************/ +mu_status_t MU_TrySendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + + // TX register is empty. + if(MU_IsTxEmpty(base, regIndex)) + { + base->TR[regIndex] = msg; + return kStatus_MU_Success; + } + + return kStatus_MU_TxNotEmpty; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_SendMsg + * Description : Wait and send message to the other core. + * + *END**************************************************************************/ +void MU_SendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + uint32_t mask = MU_SR_TE0_MASK >> regIndex; + // Wait TX register to be empty. + while (!(base->SR & mask)) { } + base->TR[regIndex] = msg; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_TryReceiveMsg + * Description : Try to receive message from the other core. + * + *END**************************************************************************/ +mu_status_t MU_TryReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg) +{ + assert(regIndex < MU_RR_COUNT); + + // RX register is full. + if(MU_IsRxFull(base, regIndex)) + { + *msg = base->RR[regIndex]; + return kStatus_MU_Success; + } + + return kStatus_MU_RxNotFull; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_ReceiveMsg + * Description : Wait to receive message from the other core. + * + *END**************************************************************************/ +void MU_ReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg) +{ + assert(regIndex < MU_TR_COUNT); + uint32_t mask = MU_SR_RF0_MASK >> regIndex; + + // Wait RX register to be full. + while (!(base->SR & mask)) { } + *msg = base->RR[regIndex]; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_TriggerGeneralInt + * Description : Trigger general purpose interrupt to the other core. + * + *END**************************************************************************/ +mu_status_t MU_TriggerGeneralInt(MU_Type * base, uint32_t index) +{ + // Previous interrupt has been accepted. + if (MU_IsGeneralIntAccepted(base, index)) + { + // All interrupts have been accepted, trigger now. + base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn + | (MU_CR_GIR0_MASK>>index); // Set GIRn + return kStatus_MU_Success; + } + + return kStatus_MU_IntPending; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_TrySetFlags + * Description : Try to set some bits of the 3-bit flag. + * + *END**************************************************************************/ +mu_status_t MU_TrySetFlags(MU_Type * base, uint32_t flags) +{ + if(MU_IsFlagPending(base)) + { + return kStatus_MU_FlagPending; + } + + base->CR = (base->CR & ~(MU_CR_GIRn_MASK | MU_CR_Fn_MASK)) | flags; + return kStatus_MU_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_SetFlags + * Description : Block to set some bits of the 3-bit flag. + * + *END**************************************************************************/ +void MU_SetFlags(MU_Type * base, uint32_t flags) +{ + while (MU_IsFlagPending(base)) { } + base->CR = (base->CR & ~(MU_CR_GIRn_MASK | MU_CR_Fn_MASK)) | flags; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/mu_imx.h b/zephyr/imx/drivers/mu_imx.h new file mode 100644 index 000000000..2e16afd7d --- /dev/null +++ b/zephyr/imx/drivers/mu_imx.h @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MU_IMX_H__ +#define __MU_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup mu_driver + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*!@brief Bit mask for general purpose interrupt 0 pending. */ +#define MU_SR_GIP0_MASK (1U<<31U) +/*!@brief Bit mask for RX full interrupt 0 pending. */ +#define MU_SR_RF0_MASK (1U<<27U) +/*!@brief Bit mask for TX empty interrupt 0 pending. */ +#define MU_SR_TE0_MASK (1U<<23U) +/*!@brief Bit mask for general purpose interrupt 0 enable. */ +#define MU_CR_GIE0_MASK (1U<<31U) +/*!@brief Bit mask for RX full interrupt 0 enable. */ +#define MU_CR_RIE0_MASK (1U<<27U) +/*!@brief Bit mask for TX empty interrupt 0 enable. */ +#define MU_CR_TIE0_MASK (1U<<23U) +/*!@brief Bit mask to trigger general purpose interrupt 0. */ +#define MU_CR_GIR0_MASK (1U<<19U) + +/*!@brief Number of general purpose interrupt. */ +#define MU_GPn_COUNT (4U) + +/* Mask for MU_CR_GIRN. When read-modify-write to MU_CR, should + pay attention to these bits in case of trigger interrupts by mistake.*/ + +/*! @brief MU status return codes. */ +typedef enum _mu_status +{ + kStatus_MU_Success = 0U, /*!< Success. */ + kStatus_MU_TxNotEmpty = 1U, /*!< TX register is not empty. */ + kStatus_MU_RxNotFull = 2U, /*!< RX register is not full. */ + kStatus_MU_FlagPending = 3U, /*!< Previous flags update pending. */ + kStatus_MU_EventPending = 4U, /*!< MU event is pending. */ + kStatus_MU_Initialized = 5U, /*!< MU driver has initialized previously. */ + kStatus_MU_IntPending = 6U, /*!< Previous general interrupt still pending. */ + kStatus_MU_Failed = 7U /*!< Execution failed. */ +} mu_status_t; + +/*! @brief MU message status. */ +typedef enum _mu_msg_status +{ + kMuTxEmpty0 = MU_SR_TE0_MASK, /*!< TX0 empty status. */ + kMuTxEmpty1 = MU_SR_TE0_MASK >> 1U, /*!< TX1 empty status. */ + kMuTxEmpty2 = MU_SR_TE0_MASK >> 2U, /*!< TX2 empty status. */ + kMuTxEmpty3 = MU_SR_TE0_MASK >> 3U, /*!< TX3 empty status. */ + kMuTxEmpty = kMuTxEmpty0 | + kMuTxEmpty1 | + kMuTxEmpty2 | + kMuTxEmpty3, /*!< TX empty status. */ + + kMuRxFull0 = MU_SR_RF0_MASK, /*!< RX0 full status. */ + kMuRxFull1 = MU_SR_RF0_MASK >> 1U, /*!< RX1 full status. */ + kMuRxFull2 = MU_SR_RF0_MASK >> 2U, /*!< RX2 full status. */ + kMuRxFull3 = MU_SR_RF0_MASK >> 3U, /*!< RX3 full status. */ + kMuRxFull = kMuRxFull0 | + kMuRxFull1 | + kMuRxFull2 | + kMuRxFull3, /*!< RX empty status. */ + + kMuGenInt0 = MU_SR_GIP0_MASK, /*!< General purpose interrupt 0 pending status. */ + kMuGenInt1 = MU_SR_GIP0_MASK >> 1U, /*!< General purpose interrupt 2 pending status. */ + kMuGenInt2 = MU_SR_GIP0_MASK >> 2U, /*!< General purpose interrupt 2 pending status. */ + kMuGenInt3 = MU_SR_GIP0_MASK >> 3U, /*!< General purpose interrupt 3 pending status. */ + kMuGenInt = kMuGenInt0 | + kMuGenInt1 | + kMuGenInt2 | + kMuGenInt3, /*!< General purpose interrupt pending status. */ + + kMuStatusAll = kMuTxEmpty | + kMuRxFull | + kMuGenInt, /*!< All MU status. */ + +} mu_msg_status_t; + +/*! @brief Power mode definition. */ +typedef enum _mu_power_mode +{ + kMuPowerModeRun = 0x00U, /*!< Run mode. */ + kMuPowerModeWait = 0x01U, /*!< WAIT mode. */ + kMuPowerModeStop = 0x02U, /*!< STOP mode. */ + kMuPowerModeDsm = 0x03U, /*!< DSM mode. */ +} mu_power_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization. + * @{ + */ +/*! + * @brief Initializes the MU module to reset state. + * This function sets the MU module control register to its default reset value. + * + * @param base Register base address for the module. + */ +static inline void MU_Init(MU_Type * base) +{ + // Clear GIEn, RIEn, TIEn, GIRn and ABFn. + base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MASK); +} + +/* @} */ + +/*! + * @name Send Messages. + * @{ + */ + +/*! + * @brief Try to send a message. + * + * This function tries to send a message, if the TX register is not empty, + * this function returns kStatus_MU_TxNotEmpty. + * + * @param base Register base address for the module. + * @param regIdex Tx register index. + * @param msg Message to send. + * @retval kStatus_MU_Success Message send successfully. + * @retval kStatus_MU_TxNotEmpty Message not send because TX is not empty. + */ +mu_status_t MU_TrySendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg); + +/*! + * @brief Block to send a message. + * + * This function waits until TX register is empty and send the message. + * + * @param base Register base address for the module. + * @param regIdex Tx register index. + * @param msg Message to send. + */ +void MU_SendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg); + +/*! + * @brief Check TX empty status. + * + * This function checks the specific transmit register empty status. + * + * @param base Register base address for the module. + * @param index TX register index to check. + * @retval true TX register is empty. + * @retval false TX register is not empty. + */ +static inline bool MU_IsTxEmpty(MU_Type * base, uint32_t index) +{ + return (bool)(base->SR & (MU_SR_TE0_MASK >> index)); +} + +/*! + * @brief Enable TX empty interrupt. + * + * This function enables specific TX empty interrupt. + * + * @param base Register base address for the module. + * @param index TX interrupt index to enable. + * + * Example: + @code + // To enable TX0 empty interrupts. + MU_EnableTxEmptyInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_EnableTxEmptyInt(MU_Type * base, uint32_t index) +{ + base->CR = (base->CR & ~ MU_CR_GIRn_MASK) // Clear GIRn + | (MU_CR_TIE0_MASK>>index); // Set TIEn +} + +/*! + * @brief Disable TX empty interrupt. + * + * This function disables specific TX empty interrupt. + * + * @param base Register base address for the module. + * @param disableMask Bitmap of the interrupts to disable. + * + * Example: + @code + // To disable TX0 empty interrupts. + MU_DisableTxEmptyInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_DisableTxEmptyInt(MU_Type * base, uint32_t index) +{ + base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_TIE0_MASK>>index)); // Clear GIRn , clear TIEn +} + +/* @} */ + +/*! + * @name Receive Messages. + * @{ + */ + +/*! + * @brief Try to receive a message. + * + * This function tries to receive a message, if the RX register is not full, + * this function returns kStatus_MU_RxNotFull. + * + * @param base Register base address for the module. + * @param regIdex Rx register index. + * @param msg Message to receive. + * @retval kStatus_MU_Success Message receive successfully. + * @retval kStatus_MU_RxNotFull Message not received because RX is not full. + */ +mu_status_t MU_TryReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg); + +/*! + * @brief Block to receive a message. + * + * This function waits until RX register is full and receive the message. + * + * @param base Register base address for the module. + * @param regIdex Rx register index. + * @param msg Message to receive. + */ +void MU_ReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg); + +/*! + * @brief Check RX full status. + * + * This function checks the specific receive register full status. + * + * @param base Register base address for the module. + * @param index RX register index to check. + * @retval true RX register is full. + * @retval false RX register is not full. + */ +static inline bool MU_IsRxFull(MU_Type * base, uint32_t index) +{ + return (bool)(base->SR & (MU_SR_RF0_MASK >> index)); +} + +/*! + * @brief Enable RX full interrupt. + * + * This function enables specific RX full interrupt. + * + * @param base Register base address for the module. + * @param index RX interrupt index to enable. + * + * Example: + @code + // To enable RX0 full interrupts. + MU_EnableRxFullInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_EnableRxFullInt(MU_Type * base, uint32_t index) +{ + base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn + | (MU_CR_RIE0_MASK>>index); // Set RIEn +} + +/*! + * @brief Disable RX full interrupt. + * + * This function disables specific RX full interrupt. + * + * @param base Register base address for the module. + * @param disableMask Bitmap of the interrupts to disable. + * + * Example: + @code + // To disable RX0 full interrupts. + MU_DisableRxFullInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_DisableRxFullInt(MU_Type * base, uint32_t index) +{ + base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_RIE0_MASK>>index)); // Clear GIRn, clear RIEn +} + +/* @} */ + +/*! + * @name General Purpose Interrupt. + * @{ + */ + +/*! + * @brief Enable general purpose interrupt. + * + * This function enables specific general purpose interrupt. + * + * @param base Register base address for the module. + * @param index General purpose interrupt index to enable. + * + * Example: + @code + // To enable general purpose interrupts 0. + MU_EnableGeneralInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_EnableGeneralInt(MU_Type * base, uint32_t index) +{ + base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn + | (MU_CR_GIE0_MASK>>index); // Set GIEn +} + +/*! + * @brief Disable general purpose interrupt. + * + * This function disables specific general purpose interrupt. + * + * @param base Register base address for the module. + * @param index General purpose interrupt index to disable. + * + * Example: + @code + // To disable general purpose interrupts 0. + MU_DisableGeneralInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_DisableGeneralInt(MU_Type * base, uint32_t index) +{ + base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_GIE0_MASK>>index)); // Clear GIRn, clear GIEn +} + +/*! + * @brief Check specific general purpose interrupt pending flag. + * + * This function checks the specific general purpose interrupt pending status. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt flag to check. + * @retval true General purpose interrupt is pending. + * @retval false General purpose interrupt is not pending. + */ +static inline bool MU_IsGeneralIntPending(MU_Type * base, uint32_t index) +{ + return (bool)(base->SR & (MU_SR_GIP0_MASK >> index)); +} + +/*! + * @brief Clear specific general purpose interrupt pending flag. + * + * This function clears the specific general purpose interrupt pending status. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt flag to clear. + */ +static inline void MU_ClearGeneralIntPending(MU_Type * base, uint32_t index) +{ + base->SR = (MU_SR_GIP0_MASK >> index); +} + +/*! + * @brief Trigger specific general purpose interrupt. + * + * This function triggers specific general purpose interrupt to other core. + * + * To ensure proper operations, make sure the correspond general purpose + * interrupt triggered previously has been accepted by the other core. The + * function MU_IsGeneralIntAccepted can be used for this check. If the + * previous general interrupt has not been accepted by the other core, this + * function does not trigger interrupt actually and returns an error. + * + * @param base Register base address for the module. + * @param index Index of general purpose interrupt to trigger. + * @retval kStatus_MU_Success Interrupt has been triggered successfully. + * @retval kStatus_MU_IntPending Previous interrupt has not been accepted. + */ +mu_status_t MU_TriggerGeneralInt(MU_Type * base, uint32_t index); + +/*! + * @brief Check specific general purpose interrupt is accepted or not. + * + * This function checks whether the specific general purpose interrupt has + * been accepted by the other core or not. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt to check. + * @retval true General purpose interrupt is accepted. + * @retval false General purpose interrupt is not accepted. + */ +static inline bool MU_IsGeneralIntAccepted(MU_Type * base, uint32_t index) +{ + return !(bool)(base->CR & (MU_CR_GIR0_MASK >> index)); +} + +/* @} */ + +/*! + * @name Flags + * @{ + */ + +/*! + * @brief Try to set some bits of the 3-bit flag reflect on the other MU side. + * + * This functions tries to set some bits of the 3-bit flag. If previous flags + * update is still pending, this function returns kStatus_MU_FlagPending. + * + * @param base Register base address for the module. + * @retval kStatus_MU_Success Flag set successfully. + * @retval kStatus_MU_FlagPending Previous flag update is pending. + */ +mu_status_t MU_TrySetFlags(MU_Type * base, uint32_t flags); + +/*! + * @brief Set some bits of the 3-bit flag reflect on the other MU side. + * + * This functions set some bits of the 3-bit flag. If previous flags update is + * still pending, this function blocks and polls to set the flag. + * + * @param base Register base address for the module. + */ +void MU_SetFlags(MU_Type * base, uint32_t flags); + +/*! + * @brief Checks whether the previous flag update is pending. + * + * After setting flags, the flags update request is pending until internally + * acknowledged. During the pending period, it is not allowed to set flags again. + * This function is used to check the pending status, it can be used together + * with function MU_TrySetFlags. + * + * @param base Register base address for the module. + * @return True if pending, false if not. + */ +static inline bool MU_IsFlagPending(MU_Type * base) +{ + return (bool)(base->SR & MU_SR_FUP_MASK); +} + +/*! + * @brief Get the current value of the 3-bit flag set by other side. + * + * This functions gets the current value of the 3-bit flag. + * + * @param base Register base address for the module. + * @return flags Current value of the 3-bit flag. + */ +static inline uint32_t MU_GetFlags(MU_Type * base) +{ + return base->SR & MU_SR_Fn_MASK; +} + +/* @} */ + +/*! + * @name Misc. + * @{ + */ + +/*! + * @brief Get the power mode of the other core. + * + * This functions gets the power mode of the other core. + * + * @param base Register base address for the module. + * @return powermode Power mode of the other core. + */ +static inline mu_power_mode_t MU_GetOtherCorePowerMode(MU_Type * base) +{ + return (mu_power_mode_t)((base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT); +} + +/*! + * @brief Get the event pending status. + * + * This functions gets the event pending status. To ensure events have been + * posted to the other side before entering STOP mode, verify the + * event pending status using this function. + * + * @param base Register base address for the module. + * @retval true Event is pending. + * @retval false Event is not pending. + */ +static inline bool MU_IsEventPending(MU_Type * base) +{ + return (bool)(base->SR & MU_SR_EP_MASK); +} + +/*! + * @brief Get the the MU message status. + * + * This functions gets TX/RX and general purpose interrupt pending status. The + * parameter is passed in as bitmask of the status to check. + * + * @param base Register base address for the module. + * @param statusToCheck The status to check, see mu_msg_status_t. + * @return Status checked. + * + * Example: + @code + // To check TX0 empty status. + MU_GetMsgStatus(MU0_BASE, kMuTxEmpty0); + + // To check all RX full status. + MU_GetMsgStatus(MU0_BASE, kMuRxFull); + + // To check general purpose interrupt 0 and 3 pending status. + MU_GetMsgStatus(MU0_BASE, kMuGenInt0 | kMuGenInt3); + + // To check all status. + MU_GetMsgStatus(MU0_BASE, kMuStatusAll); + + @endcode + */ +static inline uint32_t MU_GetMsgStatus(MU_Type * base, uint32_t statusToCheck) +{ + return base->SR & statusToCheck; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __MU_IMX_H__ */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/zephyr/imx/drivers/rdc.c b/zephyr/imx/drivers/rdc.c new file mode 100644 index 000000000..30cba440a --- /dev/null +++ b/zephyr/imx/drivers/rdc.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "rdc.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SetMrAccess + * Description : Set RDC memory region access permission for RDC domains + * + *END**************************************************************************/ +void RDC_SetMrAccess(RDC_Type * base, uint32_t mr, uint32_t startAddr, uint32_t endAddr, + uint8_t perm, bool enable, bool lock) +{ + base->MR[mr].MRSA = startAddr; + base->MR[mr].MREA = endAddr; + base->MR[mr].MRC = perm | (enable ? RDC_MRC_ENA_MASK : 0) | (lock ? RDC_MRC_LCK_MASK : 0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_GetMrAccess + * Description : Get RDC memory region access permission for RDC domains + * + *END**************************************************************************/ +uint8_t RDC_GetMrAccess(RDC_Type * base, uint32_t mr, uint32_t *startAddr, uint32_t *endAddr) +{ + if (startAddr) + *startAddr = base->MR[mr].MRSA; + if (endAddr) + *endAddr = base->MR[mr].MREA; + + return base->MR[mr].MRC & 0xFF; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_GetViolationStatus + * Description : Get RDC memory violation status + * + *END**************************************************************************/ +bool RDC_GetViolationStatus(RDC_Type * base, uint32_t mr, uint32_t *violationAddr, uint32_t *violationDomain) +{ + uint32_t mrvs; + + mrvs = base->MR[mr].MRVS; + + if (violationAddr) + *violationAddr = mrvs & RDC_MRVS_VADR_MASK; + if (violationDomain) + *violationDomain = (mrvs & RDC_MRVS_VDID_MASK) >> RDC_MRVS_VDID_SHIFT; + + return (bool)(mrvs & RDC_MRVS_AD_MASK); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/rdc.h b/zephyr/imx/drivers/rdc.h new file mode 100644 index 000000000..872e39d40 --- /dev/null +++ b/zephyr/imx/drivers/rdc.h @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RDC_H__ +#define __RDC_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup rdc_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name RDC State Control + * @{ + */ + +/*! + * @brief Get domain ID of core that is reading this + * + * @param base RDC base pointer. + * @return Domain ID of self core + */ +static inline uint32_t RDC_GetSelfDomainID(RDC_Type * base) +{ + return (base->STAT & RDC_STAT_DID_MASK) >> RDC_STAT_DID_SHIFT; +} + +/*! + * @brief Check whether memory region controlled by RDC is accessible after low power recovery + * + * @param base RDC base pointer. + * @return Memory region power status. + * - true: on and accessible. + * - false: off. + */ +static inline bool RDC_IsMemPowered(RDC_Type * base) +{ + return (bool)(base->STAT & RDC_STAT_PDS_MASK); +} + +/*! + * @brief Check whether there's pending RDC memory region restoration interrupt + * + * @param base RDC base pointer. + * @return RDC interrupt status + * - true: Interrupt pending. + * - false: No interrupt pending. + */ +static inline bool RDC_IsIntPending(RDC_Type * base) +{ + return (bool)(base->INTSTAT); +} + +/*! + * @brief Clear interrupt status + * + * @param base RDC base pointer. + */ +static inline void RDC_ClearStatusFlag(RDC_Type * base) +{ + base->INTSTAT = RDC_INTSTAT_INT_MASK; +} + +/*! + * @brief Set RDC interrupt mode + * + * @param base RDC base pointer + * @param enable RDC interrupt control. + * - true: enable interrupt. + * - false: disable interrupt. + */ +static inline void RDC_SetIntCmd(RDC_Type * base, bool enable) +{ + base->INTCTRL = enable ? RDC_INTCTRL_RCI_EN_MASK : 0; +} + +/*@}*/ + +/*! + * @name RDC Domain Control + * @{ + */ + +/*! + * @brief Set RDC domain ID for RDC master + * + * @param base RDC base pointer + * @param mda RDC master assignment (see @ref _rdc_mda in rdc_defs_.h) + * @param domainId RDC domain ID (0-3) + * @param lock Whether to lock this setting? Once locked, no one can change the domain assignment until reset + */ +static inline void RDC_SetDomainID(RDC_Type * base, uint32_t mda, uint32_t domainId, bool lock) +{ + assert (domainId <= RDC_MDA_DID_MASK); + + base->MDA[mda] = RDC_MDA_DID(domainId) | (lock ? RDC_MDA_LCK_MASK : 0); +} + +/*! + * @brief Get RDC domain ID for RDC master + * + * @param base RDC base pointer + * @param mda RDC master assignment (see @ref _rdc_mda in rdc_defs_.h) + * @return RDC domain ID (0-3) + */ +static inline uint32_t RDC_GetDomainID(RDC_Type * base, uint32_t mda) +{ + return base->MDA[mda] & RDC_MDA_DID_MASK; +} + +/*! + * @brief Set RDC peripheral access permission for RDC domains + * + * @param base RDC base pointer + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @param perm RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) + * @param sreq Force acquiring SEMA42 to access this peripheral or not + * @param lock Whether to lock this setting or not. Once locked, no one can change the RDC setting until reset + */ +static inline void RDC_SetPdapAccess(RDC_Type * base, uint32_t pdap, uint8_t perm, bool sreq, bool lock) +{ + base->PDAP[pdap] = perm | (sreq ? RDC_PDAP_SREQ_MASK : 0) | (lock ? RDC_PDAP_LCK_MASK : 0); +} + +/*! + * @brief Get RDC peripheral access permission for RDC domains + * + * @param base RDC base pointer + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @return RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) + */ +static inline uint8_t RDC_GetPdapAccess(RDC_Type * base, uint32_t pdap) +{ + return base->PDAP[pdap] & 0xFF; +} + +/*! + * @brief Check whether RDC semaphore is required to access the peripheral + * + * @param base RDC base pointer + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @return RDC semaphore required or not. + * - true: RDC semaphore is required. + * - false: RDC semaphore is not required. + */ +static inline bool RDC_IsPdapSemaphoreRequired(RDC_Type * base, uint32_t pdap) +{ + return (bool)(base->PDAP[pdap] & RDC_PDAP_SREQ_MASK); +} + +/*! + * @brief Set RDC memory region access permission for RDC domains + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_.h) + * @param startAddr memory region start address (inclusive) + * @param endAddr memory region end address (exclusive) + * @param perm RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) + * @param enable Enable this memory region for RDC control or not + * @param lock Whether to lock this setting or not. Once locked, no one can change the RDC setting until reset + */ +void RDC_SetMrAccess(RDC_Type * base, uint32_t mr, uint32_t startAddr, uint32_t endAddr, + uint8_t perm, bool enable, bool lock); + +/*! + * @brief Get RDC memory region access permission for RDC domains + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_.h) + * @param startAddr pointer to get memory region start address (inclusive), NULL is allowed. + * @param endAddr pointer to get memory region end address (exclusive), NULL is allowed. + * @return RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) + */ +uint8_t RDC_GetMrAccess(RDC_Type * base, uint32_t mr, uint32_t *startAddr, uint32_t *endAddr); + + +/*! + * @brief Check whether the memory region is enabled + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see _rdc_mr in rdc_defs_.h) + * @return Memory region enabled or not. + * - true: Memory region is enabled. + * - false: Memory region is not enabled. + */ +static inline bool RDC_IsMrEnabled(RDC_Type * base, uint32_t mr) +{ + return (bool)(base->MR[mr].MRC & RDC_MRC_ENA_MASK); +} + +/*! + * @brief Get memory violation status + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_.h) + * @param violationAddr Pointer to store violation address, NULL allowed + * @param violationDomain Pointer to store domain ID causing violation, NULL allowed + * @return Memory violation occurred or not. + * - true: violation happened. + * - false: No violation happened. + */ +bool RDC_GetViolationStatus(RDC_Type * base, uint32_t mr, uint32_t *violationAddr, uint32_t *violationDomain); + +/*! + * @brief Clear RDC violation status + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_.h) + */ +static inline void RDC_ClearViolationStatus(RDC_Type * base, uint32_t mr) +{ + base->MR[mr].MRVS = RDC_MRVS_AD_MASK; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __RDC_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/rdc_defs_imx6sx.h b/zephyr/imx/drivers/rdc_defs_imx6sx.h new file mode 100644 index 000000000..abcfa1b5b --- /dev/null +++ b/zephyr/imx/drivers/rdc_defs_imx6sx.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RDC_DEFS_IMX6SX__ +#define __RDC_DEFS_IMX6SX__ + +/*! + * @addtogroup rdc_def_imx6sx + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief RDC master assignment. */ +enum _rdc_mda +{ + rdcMdaA9L2Cache = 0U, /*!< A9 L2 Cache RDC Master. */ + rdcMdaM4 = 1U, /*!< M4 RDC Master. */ + rdcMdaGpu = 2U, /*!< GPU RDC Master. */ + rdcMdaCsi1 = 3U, /*!< Csi1 RDC Master. */ + rdcMdaCsi2 = 4U, /*!< Csi2 RDC Master. */ + rdcMdaLcdif1 = 5U, /*!< Lcdif1 RDC Master. */ + rdcMdaLcdif2 = 6U, /*!< Lcdif2 RDC Master. */ + rdcMdaPxp = 7U, /*!< Pxp RDC Master. */ + rdcMdaPcieCtrl = 8U, /*!< Pcie Ctrl RDC Master. */ + rdcMdaDap = 9U, /*!< Dap RDC Master. */ + rdcMdaCaam = 10U, /*!< Caam RDC Master. */ + rdcMdaSdmaPeriph = 11U, /*!< Sdma Periph RDC Master. */ + rdcMdaSdmaBurst = 12U, /*!< Sdma Burst RDC Master. */ + rdcMdaApbhdma = 13U, /*!< Apbhdma RDC Master. */ + rdcMdaRawnand = 14U, /*!< Rawnand RDC Master. */ + rdcMdaUsdhc1 = 15U, /*!< Usdhc1 RDC Master. */ + rdcMdaUsdhc2 = 16U, /*!< Usdhc2 RDC Master. */ + rdcMdaUsdhc3 = 17U, /*!< Usdhc3 RDC Master. */ + rdcMdaUsdhc4 = 18U, /*!< Usdhc4 RDC Master. */ + rdcMdaUsb = 19U, /*!< USB RDC Master. */ + rdcMdaMlb = 20U, /*!< MLB RDC Master. */ + rdcMdaTestPort = 21U, /*!< Test Port RDC Master. */ + rdcMdaEnet1Tx = 22U, /*!< Enet1 Tx RDC Master. */ + rdcMdaEnet1Rx = 23U, /*!< Enet1 Rx Master. */ + rdcMdaEnet2Tx = 24U, /*!< Enet2 Tx RDC Master. */ + rdcMdaEnet2Rx = 25U, /*!< Enet2 Rx RDC Master. */ + rdcMdaSdmaPort = 26U, /*!< Sdma Port RDC Master. */ +}; + +/*! @brief RDC peripheral assignment. */ +enum _rdc_pdap +{ + rdcPdapPwm1 = 0U, /*!< Pwm1 RDC Peripheral. */ + rdcPdapPwm2 = 1U, /*!< Pwm2 RDC Peripheral. */ + rdcPdapPwm3 = 2U, /*!< Pwm3 RDC Peripheral. */ + rdcPdapPwm4 = 3U, /*!< Pwm4 RDC Peripheral. */ + rdcPdapCan1 = 4U, /*!< Can1 RDC Peripheral. */ + rdcPdapCan2 = 5U, /*!< Can2 RDC Peripheral. */ + rdcPdapGpt = 6U, /*!< Gpt RDC Peripheral. */ + rdcPdapGpio1 = 7U, /*!< Gpio1 RDC Peripheral. */ + rdcPdapGpio2 = 8U, /*!< Gpio2 RDC Peripheral. */ + rdcPdapGpio3 = 9U, /*!< Gpio3 RDC Peripheral. */ + rdcPdapGpio4 = 10U, /*!< Gpio4 RDC Peripheral. */ + rdcPdapGpio5 = 11U, /*!< Gpio5 RDC Peripheral. */ + rdcPdapGpio6 = 12U, /*!< Gpio6 RDC Peripheral. */ + rdcPdapGpio7 = 13U, /*!< Gpio7 RDC Peripheral. */ + rdcPdapKpp = 14U, /*!< Kpp RDC Peripheral. */ + rdcPdapWdog1 = 15U, /*!< Wdog1 RDC Peripheral. */ + rdcPdapWdog2 = 16U, /*!< Wdog2 RDC Peripheral. */ + rdcPdapCcm = 17U, /*!< Ccm RDC Peripheral. */ + rdcPdapAnatopDig = 18U, /*!< AnatopDig RDC Peripheral. */ + rdcPdapSnvsHp = 19U, /*!< SnvsHp RDC Peripheral. */ + rdcPdapEpit1 = 20U, /*!< Epit1 RDC Peripheral. */ + rdcPdapEpit2 = 21U, /*!< Epit2 RDC Peripheral. */ + rdcPdapSrc = 22U, /*!< Src RDC Peripheral. */ + rdcPdapGpc = 23U, /*!< Gpc RDC Peripheral. */ + rdcPdapIomuxc = 24U, /*!< Iomuxc RDC Peripheral. */ + rdcPdapIomuxcGpr = 25U, /*!< IomuxcGpr RDC Peripheral. */ + rdcPdapCanfdCan1 = 26U, /*!< Canfd Can1 RDC Peripheral. */ + rdcPdapSdma = 27U, /*!< Sdma RDC Peripheral. */ + rdcPdapCanfdCan2 = 28U, /*!< Canfd Can2 RDC Peripheral. */ + rdcPdapRdcSema421 = 29U, /*!< Rdc Sema421 RDC Peripheral. */ + rdcPdapRdcSema422 = 30U, /*!< Rdc Sema422 RDC Peripheral. */ + rdcPdapRdc = 31U, /*!< Rdc RDC Peripheral. */ + rdcPdapAipsTz1GlobalEnable1 = 32U, /*!< AipsTz1GlobalEnable1 RDC Peripheral. */ + rdcPdapAipsTz1GlobalEnable2 = 33U, /*!< AipsTz1GlobalEnable2 RDC Peripheral. */ + rdcPdapUsb02hPl301 = 34U, /*!< Usb02hPl301 RDC Peripheral. */ + rdcPdapUsb02hUsb = 35U, /*!< Usb02hUsb RDC Peripheral. */ + rdcPdapEnet1 = 36U, /*!< Enet1 RDC Peripheral. */ + rdcPdapMlb2550 = 37U, /*!< Mlb2550 RDC Peripheral. */ + rdcPdapUsdhc1 = 38U, /*!< Usdhc1 RDC Peripheral. */ + rdcPdapUsdhc2 = 39U, /*!< Usdhc2 RDC Peripheral. */ + rdcPdapUsdhc3 = 40U, /*!< Usdhc3 RDC Peripheral. */ + rdcPdapUsdhc4 = 41U, /*!< Usdhc4 RDC Peripheral. */ + rdcPdapI2c1 = 42U, /*!< I2c1 RDC Peripheral. */ + rdcPdapI2c2 = 43U, /*!< I2c2 RDC Peripheral. */ + rdcPdapI2c3 = 44U, /*!< I2c3 RDC Peripheral. */ + rdcPdapRomcp = 45U, /*!< Romcp RDC Peripheral. */ + rdcPdapMmdc = 46U, /*!< Mmdc RDC Peripheral. */ + rdcPdapEnet2 = 47U, /*!< Enet2 RDC Peripheral. */ + rdcPdapEim = 48U, /*!< Eim RDC Peripheral. */ + rdcPdapOcotpCtrlWrapper = 49U, /*!< OcotpCtrlWrapper RDC Peripheral. */ + rdcPdapCsu = 50U, /*!< Csu RDC Peripheral. */ + rdcPdapPerfmon1 = 51U, /*!< Perfmon1 RDC Peripheral. */ + rdcPdapPerfmon2 = 52U, /*!< Perfmon2 RDC Peripheral. */ + rdcPdapAxiMon = 53U, /*!< AxiMon RDC Peripheral. */ + rdcPdapTzasc1 = 54U, /*!< Tzasc1 RDC Peripheral. */ + rdcPdapSai1 = 55U, /*!< Sai1 RDC Peripheral. */ + rdcPdapAudmux = 56U, /*!< Audmux RDC Peripheral. */ + rdcPdapSai2 = 57U, /*!< Sai2 RDC Peripheral. */ + rdcPdapQspi1 = 58U, /*!< Qspi1 RDC Peripheral. */ + rdcPdapQspi2 = 59U, /*!< Qspi2 RDC Peripheral. */ + rdcPdapUart2 = 60U, /*!< Uart2 RDC Peripheral. */ + rdcPdapUart3 = 61U, /*!< Uart3 RDC Peripheral. */ + rdcPdapUart4 = 62U, /*!< Uart4 RDC Peripheral. */ + rdcPdapUart5 = 63U, /*!< Uart5 RDC Peripheral. */ + rdcPdapI2c4 = 64U, /*!< I2c4 RDC Peripheral. */ + rdcPdapQosc = 65U, /*!< Qosc RDC Peripheral. */ + rdcPdapCaam = 66U, /*!< Caam RDC Peripheral. */ + rdcPdapDap = 67U, /*!< Dap RDC Peripheral. */ + rdcPdapAdc1 = 68U, /*!< Adc1 RDC Peripheral. */ + rdcPdapAdc2 = 69U, /*!< Adc2 RDC Peripheral. */ + rdcPdapWdog3 = 70U, /*!< Wdog3 RDC Peripheral. */ + rdcPdapEcspi5 = 71U, /*!< Ecspi5 RDC Peripheral. */ + rdcPdapSema4 = 72U, /*!< Sema4 RDC Peripheral. */ + rdcPdapMuA = 73U, /*!< MuA RDC Peripheral. */ + rdcPdapCanfdCpu = 74U, /*!< Canfd Cpu RDC Peripheral. */ + rdcPdapMuB = 75U, /*!< MuB RDC Peripheral. */ + rdcPdapUart6 = 76U, /*!< Uart6 RDC Peripheral. */ + rdcPdapPwm5 = 77U, /*!< Pwm5 RDC Peripheral. */ + rdcPdapPwm6 = 78U, /*!< Pwm6 RDC Peripheral. */ + rdcPdapPwm7 = 79U, /*!< Pwm7 RDC Peripheral. */ + rdcPdapPwm8 = 80U, /*!< Pwm8 RDC Peripheral. */ + rdcPdapAipsTz3GlobalEnable0 = 81U, /*!< AipsTz3GlobalEnable0 RDC Peripheral. */ + rdcPdapAipsTz3GlobalEnable1 = 82U, /*!< AipsTz3GlobalEnable1 RDC Peripheral. */ + rdcPdapSpdif = 84U, /*!< Spdif RDC Peripheral. */ + rdcPdapEcspi1 = 85U, /*!< Ecspi1 RDC Peripheral. */ + rdcPdapEcspi2 = 86U, /*!< Ecspi2 RDC Peripheral. */ + rdcPdapEcspi3 = 87U, /*!< Ecspi3 RDC Peripheral. */ + rdcPdapEcspi4 = 88U, /*!< Ecspi4 RDC Peripheral. */ + rdcPdapUart1 = 91U, /*!< Uart1 RDC Peripheral. */ + rdcPdapEsai = 92U, /*!< Esai RDC Peripheral. */ + rdcPdapSsi1 = 93U, /*!< Ssi1 RDC Peripheral. */ + rdcPdapSsi2 = 94U, /*!< Ssi2 RDC Peripheral. */ + rdcPdapSsi3 = 95U, /*!< Ssi3 RDC Peripheral. */ + rdcPdapAsrc = 96U, /*!< Asrc RDC Peripheral. */ + rdcPdapSpbaMaMegamix = 98U, /*!< SpbaMaMegamix RDC Peripheral. */ + rdcPdapGis = 99U, /*!< Gis RDC Peripheral. */ + rdcPdapDcic1 = 100U, /*!< Dcic1 RDC Peripheral. */ + rdcPdapDcic2 = 101U, /*!< Dcic2 RDC Peripheral. */ + rdcPdapCsi1 = 102U, /*!< Csi1 RDC Peripheral. */ + rdcPdapPxp = 103U, /*!< Pxp RDC Peripheral. */ + rdcPdapCsi2 = 104U, /*!< Csi2 RDC Peripheral. */ + rdcPdapLcdif1 = 105U, /*!< Lcdif1 RDC Peripheral. */ + rdcPdapLcdif2 = 106U, /*!< Lcdif2 RDC Peripheral. */ + rdcPdapVadc = 107U, /*!< Vadc RDC Peripheral. */ + rdcPdapVdec = 108U, /*!< Vdec RDC Peripheral. */ + rdcPdapSpDisplaymix = 109U, /*!< SpDisplaymix RDC Peripheral. */ +}; + +/*! @brief RDC memory region */ +enum _rdc_mr +{ + rdcMrMmdc = 0U, /*!< alignment 4096 */ + rdcMrMmdcLast = 7U, /*!< alignment 4096 */ + rdcMrQspi1 = 8U, /*!< alignment 4096 */ + rdcMrQspi1Last = 15U, /*!< alignment 4096 */ + rdcMrQspi2 = 16U, /*!< alignment 4096 */ + rdcMrQspi2Last = 23U, /*!< alignment 4096 */ + rdcMrWeim = 24U, /*!< alignment 4096 */ + rdcMrWeimLast = 31U, /*!< alignment 4096 */ + rdcMrPcie = 32U, /*!< alignment 4096 */ + rdcMrPcieLast = 39U, /*!< alignment 4096 */ + rdcMrOcram = 40U, /*!< alignment 128 */ + rdcMrOcramLast = 44U, /*!< alignment 128 */ + rdcMrOcramS = 45U, /*!< alignment 128 */ + rdcMrOcramSLast = 49U, /*!< alignment 128 */ + rdcMrOcramL2 = 50U, /*!< alignment 128 */ + rdcMrOcramL2Last = 54U, /*!< alignment 128 */ +}; + +#endif /* __RDC_DEFS_IMX6SX__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/rdc_defs_imx7d.h b/zephyr/imx/drivers/rdc_defs_imx7d.h new file mode 100644 index 000000000..294d0ad64 --- /dev/null +++ b/zephyr/imx/drivers/rdc_defs_imx7d.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RDC_DEFS_IMX7D__ +#define __RDC_DEFS_IMX7D__ + +/*! + * @addtogroup rdc_def_imx7d + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief RDC master assignment. */ +enum _rdc_mda +{ + rdcMdaA7 = 0U, /*!< ARM Cortex-A7 RDC Master. */ + rdcMdaM4 = 1U, /*!< ARM Cortex-M4 RDC Master. */ + rdcMdaPcie = 2U, /*!< PCIe RDC Master. */ + rdcMdaCsi = 3U, /*!< CSI RDC Master. */ + rdcMdaEpdc = 4U, /*!< EPDC RDC Master. */ + rdcMdaLcdif = 5U, /*!< LCDIF RDC Master. */ + rdcMdaDisplayPort = 6U, /*!< DISPLAY PORT RDC Master. */ + rdcMdaPxp = 7U, /*!< PXP RDC Master. */ + rdcMdaCoresight = 8U, /*!< CORESIGHT RDC Master. */ + rdcMdaDap = 9U, /*!< DAP RDC Master. */ + rdcMdaCaam = 10U, /*!< CAAM RDC Master. */ + rdcMdaSdmaPeriph = 11U, /*!< SDMA PERIPHERAL RDC Master. */ + rdcMdaSdmaBurst = 12U, /*!< SDMA BURST RDC Master. */ + rdcMdaApbhdma = 13U, /*!< APBH DMA RDC Master. */ + rdcMdaRawnand = 14U, /*!< RAW NAND RDC Master. */ + rdcMdaUsdhc1 = 15U, /*!< USDHC1 RDC Master. */ + rdcMdaUsdhc2 = 16U, /*!< USDHC2 RDC Master. */ + rdcMdaUsdhc3 = 17U, /*!< USDHC3 RDC Master. */ + rdcMdaNc1 = 18U, /*!< NC1 RDC Master. */ + rdcMdaUsb = 19U, /*!< USB RDC Master. */ + rdcMdaNc2 = 20U, /*!< NC2 RDC Master. */ + rdcMdaTest = 21U, /*!< TEST RDC Master. */ + rdcMdaEnet1Tx = 22U, /*!< Ethernet1 Tx RDC Master. */ + rdcMdaEnet1Rx = 23U, /*!< Ethernet1 Rx RDC Master. */ + rdcMdaEnet2Tx = 24U, /*!< Ethernet2 Tx RDC Master. */ + rdcMdaEnet2Rx = 25U, /*!< Ethernet2 Rx RDC Master. */ + rdcMdaSdmaPort = 26U, /*!< SDMA PORT RDC Master. */ +}; + +/*! @brief RDC peripheral assignment. */ +enum _rdc_pdap +{ + rdcPdapGpio1 = 0U, /*!< GPIO1 RDC Peripheral. */ + rdcPdapGpio2 = 1U, /*!< GPIO2 RDC Peripheral. */ + rdcPdapGpio3 = 2U, /*!< GPIO3 RDC Peripheral. */ + rdcPdapGpio4 = 3U, /*!< GPIO4 RDC Peripheral. */ + rdcPdapGpio5 = 4U, /*!< GPIO5 RDC Peripheral. */ + rdcPdapGpio6 = 5U, /*!< GPIO6 RDC Peripheral. */ + rdcPdapGpio7 = 6U, /*!< GPIO7 RDC Peripheral. */ + rdcPdapIomuxcLpsrGpr = 7U, /*!< IOMXUC LPSR GPR RDC Peripheral. */ + rdcPdapWdog1 = 8U, /*!< WDOG1 RDC Peripheral. */ + rdcPdapWdog2 = 9U, /*!< WDOG2 RDC Peripheral. */ + rdcPdapWdog3 = 10U, /*!< WDOG3 RDC Peripheral. */ + rdcPdapWdog4 = 11U, /*!< WDOG4 RDC Peripheral. */ + rdcPdapIomuxcLpsr = 12U, /*!< IOMUXC LPSR RDC Peripheral. */ + rdcPdapGpt1 = 13U, /*!< GPT1 RDC Peripheral. */ + rdcPdapGpt2 = 14U, /*!< GPT2 RDC Peripheral. */ + rdcPdapGpt3 = 15U, /*!< GPT3 RDC Peripheral. */ + rdcPdapGpt4 = 16U, /*!< GPT4 RDC Peripheral. */ + rdcPdapRomcp = 17U, /*!< ROMCP RDC Peripheral. */ + rdcPdapKpp = 18U, /*!< KPP RDC Peripheral. */ + rdcPdapIomuxc = 19U, /*!< IOMUXC RDC Peripheral. */ + rdcPdapIomuxcGpr = 20U, /*!< IOMUXC GPR RDC Peripheral. */ + rdcPdapOcotpCtrl = 21U, /*!< OCOTP CTRL RDC Peripheral. */ + rdcPdapAnatopDig = 22U, /*!< ANATOPDIG RDC Peripheral. */ + rdcPdapSnvs = 23U, /*!< SNVS RDC Peripheral. */ + rdcPdapCcm = 24U, /*!< CCM RDC Peripheral. */ + rdcPdapSrc = 25U, /*!< SRC RDC Peripheral. */ + rdcPdapGpc = 26U, /*!< GPC RDC Peripheral. */ + rdcPdapSemaphore1 = 27U, /*!< SEMAPHORE1 RDC Peripheral. */ + rdcPdapSemaphore2 = 28U, /*!< SEMAPHORE2 RDC Peripheral. */ + rdcPdapRdc = 29U, /*!< RDC RDC Peripheral. */ + rdcPdapCsu = 30U, /*!< CSU RDC Peripheral. */ + rdcPdapReserved1 = 31U, /*!< Reserved1 RDC Peripheral. */ + rdcPdapReserved2 = 32U, /*!< Reserved2 RDC Peripheral. */ + rdcPdapAdc1 = 33U, /*!< ADC1 RDC Peripheral. */ + rdcPdapAdc2 = 34U, /*!< ADC2 RDC Peripheral. */ + rdcPdapEcspi4 = 35U, /*!< ECSPI4 RDC Peripheral. */ + rdcPdapFlexTimer1 = 36U, /*!< FTM1 RDC Peripheral. */ + rdcPdapFlexTimer2 = 37U, /*!< FTM2 RDC Peripheral. */ + rdcPdapPwm1 = 38U, /*!< PWM1 RDC Peripheral. */ + rdcPdapPwm2 = 39U, /*!< PWM2 RDC Peripheral. */ + rdcPdapPwm3 = 40U, /*!< PWM3 RDC Peripheral. */ + rdcPdapPwm4 = 41U, /*!< PWM4 RDC Peripheral. */ + rdcPdapSystemCounterRead = 42U, /*!< System Counter Read RDC Peripheral. */ + rdcPdapSystemCounterCompare = 43U, /*!< System Counter Compare RDC Peripheral. */ + rdcPdapSystemCounterControl = 44U, /*!< System Counter Control RDC Peripheral. */ + rdcPdapPcie = 45U, /*!< PCIE RDC Peripheral. */ + rdcPdapReserved3 = 46U, /*!< Reserved3 RDC Peripheral. */ + rdcPdapEpdc = 47U, /*!< EPDC RDC Peripheral. */ + rdcPdapPxp = 48U, /*!< PXP RDC Peripheral. */ + rdcPdapCsi = 49U, /*!< CSI RDC Peripheral. */ + rdcPdapReserved4 = 50U, /*!< Reserved4 RDC Peripheral. */ + rdcPdapLcdif = 51U, /*!< LCDIF RDC Peripheral. */ + rdcPdapReserved5 = 52U, /*!< Reserved5 RDC Peripheral. */ + rdcPdapMipiCsi = 53U, /*!< MIPI CSI RDC Peripheral. */ + rdcPdapMipiDsi = 54U, /*!< MIPI DSI RDC Peripheral. */ + rdcPdapReserved6 = 55U, /*!< Reserved6 RDC Peripheral. */ + rdcPdapTzasc = 56U, /*!< TZASC RDC Peripheral. */ + rdcPdapDdrPhy = 57U, /*!< DDR PHY RDC Peripheral. */ + rdcPdapDdrc = 58U, /*!< DDRC RDC Peripheral. */ + rdcPdapReserved7 = 59U, /*!< Reserved7 RDC Peripheral. */ + rdcPdapPerfMon1 = 60U, /*!< PerfMon1 RDC Peripheral. */ + rdcPdapPerfMon2 = 61U, /*!< PerfMon2 RDC Peripheral. */ + rdcPdapAxi = 62U, /*!< AXI RDC Peripheral. */ + rdcPdapQosc = 63U, /*!< QOSC RDC Peripheral. */ + rdcPdapFlexCan1 = 64U, /*!< FLEXCAN1 RDC Peripheral. */ + rdcPdapFlexCan2 = 65U, /*!< FLEXCAN2 RDC Peripheral. */ + rdcPdapI2c1 = 66U, /*!< I2C1 RDC Peripheral. */ + rdcPdapI2c2 = 67U, /*!< I2C2 RDC Peripheral. */ + rdcPdapI2c3 = 68U, /*!< I2C3 RDC Peripheral. */ + rdcPdapI2c4 = 69U, /*!< I2C4 RDC Peripheral. */ + rdcPdapUart4 = 70U, /*!< UART4 RDC Peripheral. */ + rdcPdapUart5 = 71U, /*!< UART5 RDC Peripheral. */ + rdcPdapUart6 = 72U, /*!< UART6 RDC Peripheral. */ + rdcPdapUart7 = 73U, /*!< UART7 RDC Peripheral. */ + rdcPdapMuA = 74U, /*!< MUA RDC Peripheral. */ + rdcPdapMuB = 75U, /*!< MUB RDC Peripheral. */ + rdcPdapSemaphoreHs = 76U, /*!< SEMAPHORE HS RDC Peripheral. */ + rdcPdapUsbPl301 = 77U, /*!< USB PL301 RDC Peripheral. */ + rdcPdapReserved8 = 78U, /*!< Reserved8 RDC Peripheral. */ + rdcPdapReserved9 = 79U, /*!< Reserved9 RDC Peripheral. */ + rdcPdapReserved10 = 80U, /*!< Reserved10 RDC Peripheral. */ + rdcPdapUSB1Otg1 = 81U, /*!< USB2 OTG1 RDC Peripheral. */ + rdcPdapUSB2Otg2 = 82U, /*!< USB2 OTG2 RDC Peripheral. */ + rdcPdapUSB3Host = 83U, /*!< USB3 HOST RDC Peripheral. */ + rdcPdapUsdhc1 = 84U, /*!< USDHC1 RDC Peripheral. */ + rdcPdapUsdhc2 = 85U, /*!< USDHC2 RDC Peripheral. */ + rdcPdapUsdhc3 = 86U, /*!< USDHC3 RDC Peripheral. */ + rdcPdapReserved11 = 87U, /*!< Reserved11 RDC Peripheral. */ + rdcPdapReserved12 = 88U, /*!< Reserved12 RDC Peripheral. */ + rdcPdapSim1 = 89U, /*!< SIM1 RDC Peripheral. */ + rdcPdapSim2 = 90U, /*!< SIM2 RDC Peripheral. */ + rdcPdapQspi = 91U, /*!< QSPI RDC Peripheral. */ + rdcPdapWeim = 92U, /*!< WEIM RDC Peripheral. */ + rdcPdapSdma = 93U, /*!< SDMA RDC Peripheral. */ + rdcPdapEnet1 = 94U, /*!< Eneternet1 RDC Peripheral. */ + rdcPdapEnet2 = 95U, /*!< Eneternet2 RDC Peripheral. */ + rdcPdapReserved13 = 96U, /*!< Reserved13 RDC Peripheral. */ + rdcPdapReserved14 = 97U, /*!< Reserved14 RDC Peripheral. */ + rdcPdapEcspi1 = 98U, /*!< ECSPI1 RDC Peripheral. */ + rdcPdapEcspi2 = 99U, /*!< ECSPI2 RDC Peripheral. */ + rdcPdapEcspi3 = 100U, /*!< ECSPI3 RDC Peripheral. */ + rdcPdapReserved15 = 101U, /*!< Reserved15 RDC Peripheral. */ + rdcPdapUart1 = 102U, /*!< UART1 RDC Peripheral. */ + rdcPdapReserved16 = 103U, /*!< Reserved16 RDC Peripheral. */ + rdcPdapUart3 = 104U, /*!< UART3 RDC Peripheral. */ + rdcPdapUart2 = 105U, /*!< UART2 RDC Peripheral. */ + rdcPdapSai1 = 106U, /*!< SAI1 RDC Peripheral. */ + rdcPdapSai2 = 107U, /*!< SAI2 RDC Peripheral. */ + rdcPdapSai3 = 108U, /*!< SAI3 RDC Peripheral. */ + rdcPdapReserved17 = 109U, /*!< Reserved17 RDC Peripheral. */ + rdcPdapReserved18 = 110U, /*!< Reserved18 RDC Peripheral. */ + rdcPdapSpba = 111U, /*!< SPBA RDC Peripheral. */ + rdcPdapDap = 112U, /*!< DAP RDC Peripheral. */ + rdcPdapReserved19 = 113U, /*!< Reserved19 RDC Peripheral. */ + rdcPdapReserved20 = 114U, /*!< Reserved20 RDC Peripheral. */ + rdcPdapReserved21 = 115U, /*!< Reserved21 RDC Peripheral. */ + rdcPdapCaam = 116U, /*!< CAAM RDC Peripheral. */ + rdcPdapReserved22 = 117U, /*!< Reserved22 RDC Peripheral. */ +}; + +/*! @brief RDC memory region. */ +enum _rdc_mr +{ + rdcMrMmdc = 0U, /*!< alignment 4096 */ + rdcMrMmdcLast = 7U, /*!< alignment 4096 */ + rdcMrQspi = 8U, /*!< alignment 4096 */ + rdcMrQspiLast = 15U, /*!< alignment 4096 */ + rdcMrWeim = 16U, /*!< alignment 4096 */ + rdcMrWeimLast = 23U, /*!< alignment 4096 */ + rdcMrPcie = 24U, /*!< alignment 4096 */ + rdcMrPcieLast = 31U, /*!< alignment 4096 */ + rdcMrOcram = 32U, /*!< alignment 128 */ + rdcMrOcramLast = 36U, /*!< alignment 128 */ + rdcMrOcramS = 37U, /*!< alignment 128 */ + rdcMrOcramSLast = 41U, /*!< alignment 128 */ + rdcMrOcramEpdc = 42U, /*!< alignment 128 */ + rdcMrOcramEpdcLast = 46U, /*!< alignment 128 */ + rdcMrOcramPxp = 47U, /*!< alignment 128 */ + rdcMrOcramPxpLast = 51U, /*!< alignment 128 */ +}; + +#endif /* __RDC_DEFS_IMX7D__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/rdc_semaphore.c b/zephyr/imx/drivers/rdc_semaphore.c new file mode 100644 index 000000000..3f97d90f9 --- /dev/null +++ b/zephyr/imx/drivers/rdc_semaphore.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "rdc_semaphore.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * Private Functions + ******************************************************************************/ +static RDC_SEMAPHORE_Type *RDC_SEMAPHORE_GetGate(uint32_t *pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + + if (*pdap < 64) + semaphore = RDC_SEMAPHORE1; + else + { + semaphore = RDC_SEMAPHORE2; + *pdap -= 64; + } + + return semaphore; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_TryLock + * Description : Lock RDC semaphore for shared peripheral access + * + *END**************************************************************************/ +rdc_semaphore_status_t RDC_SEMAPHORE_TryLock(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + semaphore->GATE[index] = RDC_SEMAPHORE_GATE_GTFSM(RDC_SEMAPHORE_MASTER_SELF + 1); + + return ((semaphore->GATE[index] & RDC_SEMAPHORE_GATE_GTFSM_MASK) == + RDC_SEMAPHORE_GATE_GTFSM(RDC_SEMAPHORE_MASTER_SELF + 1)) ? + statusRdcSemaphoreSuccess : statusRdcSemaphoreBusy; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_Lock + * Description : Lock RDC semaphore for shared peripheral access, polling until + * success. + * + *END**************************************************************************/ +void RDC_SEMAPHORE_Lock(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + do { + /* Wait gate status free */ + while (semaphore->GATE[index] & RDC_SEMAPHORE_GATE_GTFSM_MASK) { } + semaphore->GATE[index] = RDC_SEMAPHORE_GATE_GTFSM(RDC_SEMAPHORE_MASTER_SELF + 1); + } while ((semaphore->GATE[index] & RDC_SEMAPHORE_GATE_GTFSM_MASK) != + RDC_SEMAPHORE_GATE_GTFSM(RDC_SEMAPHORE_MASTER_SELF + 1)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_Unlock + * Description : Unlock RDC semaphore + * + *END**************************************************************************/ +void RDC_SEMAPHORE_Unlock(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + semaphore->GATE[index] = RDC_SEMAPHORE_GATE_GTFSM(0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_GetLockDomainID + * Description : Get domain ID which locks the semaphore + * + *END**************************************************************************/ +uint32_t RDC_SEMAPHORE_GetLockDomainID(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + return (semaphore->GATE[index] & RDC_SEMAPHORE_GATE_LDOM_MASK) >> RDC_SEMAPHORE_GATE_LDOM_SHIFT; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_GetLockMaster + * Description : Get master index which locks the semaphore + * + *END**************************************************************************/ +uint32_t RDC_SEMAPHORE_GetLockMaster(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + uint8_t master; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + master = (semaphore->GATE[index] & RDC_SEMAPHORE_GATE_GTFSM_MASK) >> RDC_SEMAPHORE_GATE_GTFSM_SHIFT; + + return master == 0 ? RDC_SEMAPHORE_MASTER_NONE : master - 1; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_Reset + * Description : Reset RDC semaphore to unlocked status + * + *END**************************************************************************/ +void RDC_SEMAPHORE_Reset(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + /* The reset state machine must be in idle state */ + assert ((semaphore->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) == 0); + + semaphore->RSTGT_W = 0xE2; + semaphore->RSTGT_W = 0x1D | RDC_SEMAPHORE_RSTGT_W_RSTGTN(index); +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_ResetAll + * Description : Reset all RDC semaphores to unlocked status for certain + * RDC_SEMAPHORE instance + * + *END**************************************************************************/ +void RDC_SEMAPHORE_ResetAll(RDC_SEMAPHORE_Type *base) +{ + /* The reset state machine must be in idle state */ + assert ((base->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) == 0); + + base->RSTGT_W = 0xE2; + base->RSTGT_W = 0x1D | RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/rdc_semaphore.h b/zephyr/imx/drivers/rdc_semaphore.h new file mode 100644 index 000000000..ec990b8b9 --- /dev/null +++ b/zephyr/imx/drivers/rdc_semaphore.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RDC_SEMAPHORE_H__ +#define __RDC_SEMAPHORE_H__ + +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup rdc_semaphore_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define RDC_SEMAPHORE_MASTER_NONE (0xFF) + +/*! @brief RDC Semaphore status return codes. */ +typedef enum _rdc_semaphore_status +{ + statusRdcSemaphoreSuccess = 0U, /*!< Success. */ + statusRdcSemaphoreBusy = 1U, /*!< RDC semaphore has been locked by other processor. */ +} rdc_semaphore_status_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name RDC_SEMAPHORE State Control + * @{ + */ + +/*! + * @brief Lock RDC semaphore for shared peripheral access + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @retval statusRdcSemaphoreSuccess Lock the semaphore successfully. + * @retval statusRdcSemaphoreBusy Semaphore has been locked by other processor. + */ +rdc_semaphore_status_t RDC_SEMAPHORE_TryLock(uint32_t pdap); + +/*! + * @brief Lock RDC semaphore for shared peripheral access, polling until success. + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + */ +void RDC_SEMAPHORE_Lock(uint32_t pdap); + +/*! + * @brief Unlock RDC semaphore + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + */ +void RDC_SEMAPHORE_Unlock(uint32_t pdap); + +/*! + * @brief Get domain ID which locks the semaphore + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @return domain ID which locks the RDC semaphore + */ +uint32_t RDC_SEMAPHORE_GetLockDomainID(uint32_t pdap); + +/*! + * @brief Get master index which locks the semaphore + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @return master index which locks the RDC semaphore, or RDC_SEMAPHORE_MASTER_NONE + * to indicate it is not locked. + */ +uint32_t RDC_SEMAPHORE_GetLockMaster(uint32_t pdap); + +/*@}*/ + +/*! + * @name RDC_SEMAPHORE Reset Control + * @{ + */ + +/*! + * @brief Reset RDC semaphore to unlocked status + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + */ +void RDC_SEMAPHORE_Reset(uint32_t pdap); + +/*! + * @brief Reset all RDC semaphore to unlocked status for certain RDC_SEMAPHORE instance + * + * @param base RDC semaphore base pointer. + */ +void RDC_SEMAPHORE_ResetAll(RDC_SEMAPHORE_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __RDC_SEMAPHORE_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/sema4.c b/zephyr/imx/drivers/sema4.c new file mode 100644 index 000000000..aabdfecef --- /dev/null +++ b/zephyr/imx/drivers/sema4.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "sema4.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_TryLock + * Description : Lock SEMA4 gate for exclusive access between multicore + * + *END**************************************************************************/ +sema4_status_t SEMA4_TryLock(SEMA4_Type *base, uint32_t gateIndex) +{ + __IO uint8_t *gate; + + assert(gateIndex < 16); + + gate = &base->GATE00 + gateIndex; + + *gate = SEMA4_GATE00_GTFSM(SEMA4_PROCESSOR_SELF + 1); + + return ((*gate & SEMA4_GATE00_GTFSM_MASK) == SEMA4_GATE00_GTFSM(SEMA4_PROCESSOR_SELF + 1)) ? + statusSema4Success : statusSema4Busy; +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_Lock + * Description : Lock SEMA4 gate for exclusive access between multicore, + * polling until success + * + *END**************************************************************************/ +void SEMA4_Lock(SEMA4_Type *base, uint32_t gateIndex) +{ + __IO uint8_t *gate; + + assert(gateIndex < 16); + + gate = &base->GATE00 + gateIndex; + + do { + /* Wait gate status free */ + while (*gate & SEMA4_GATE00_GTFSM_MASK) { } + *gate = SEMA4_GATE00_GTFSM(SEMA4_PROCESSOR_SELF + 1); + } while ((*gate & SEMA4_GATE00_GTFSM_MASK) != SEMA4_GATE00_GTFSM(SEMA4_PROCESSOR_SELF + 1)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_Unlock + * Description : Unlock SEMA4 gate + * + *END**************************************************************************/ +void SEMA4_Unlock(SEMA4_Type *base, uint32_t gateIndex) +{ + __IO uint8_t *gate; + + assert(gateIndex < 16); + + gate = &base->GATE00 + gateIndex; + + *gate = SEMA4_GATE00_GTFSM(0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_GetLockProcessor + * Description : Get master index which locks the semaphore + * + *END**************************************************************************/ +uint32_t SEMA4_GetLockProcessor(SEMA4_Type *base, uint32_t gateIndex) +{ + __IO uint8_t *gate; + uint8_t proc; + + assert(gateIndex < 16); + + gate = &base->GATE00 + gateIndex; + + proc = (*gate & SEMA4_GATE00_GTFSM_MASK) >> SEMA4_GATE00_GTFSM_SHIFT; + + return proc == 0 ? SEMA4_PROCESSOR_NONE : proc - 1; +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_ResetGate + * Description : Reset SEMA4 gate to unlocked status + * + *END**************************************************************************/ +void SEMA4_ResetGate(SEMA4_Type *base, uint32_t gateIndex) +{ + assert(gateIndex < 16); + + /* The reset state machine must be in idle state */ + assert ((base->RSTGT & 0x30) == 0); + + base->RSTGT = 0xE2; + base->RSTGT = 0x1D | SEMA4_RSTGT_RSTGTN(gateIndex); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_ResetAllGates + * Description : Reset all SEMA4 gates to unlocked status for certain + * SEMA4 instance + * + *END**************************************************************************/ +void SEMA4_ResetAllGates(SEMA4_Type *base) +{ + /* The reset state machine must be in idle state */ + assert ((base->RSTGT & 0x30) == 0); + + base->RSTGT = 0xE2; + base->RSTGT = 0x1D | SEMA4_RSTGT_RSTGTN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_ResetNotification + * Description : Reset SEMA4 IRQ notifications + * + *END**************************************************************************/ +void SEMA4_ResetNotification(SEMA4_Type *base, uint32_t gateIndex) +{ + assert(gateIndex < 16); + + /* The reset state machine must be in idle state */ + assert ((base->RSTNTF & 0x30) == 0); + + base->RSTNTF = 0x47; + base->RSTNTF = 0xB8 | SEMA4_RSTNTF_RSTNTN(gateIndex); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_ResetAllNotifications + * Description : Reset all SEMA4 gates to unlocked status for certain + * SEMA4 instance + * + *END**************************************************************************/ +void SEMA4_ResetAllNotifications(SEMA4_Type *base) +{ + /* The reset state machine must be in idle state */ + assert ((base->RSTNTF & 0x30) == 0); + + base->RSTNTF = 0x47; + base->RSTNTF = 0xB8 | SEMA4_RSTNTF_RSTNTN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_SetIntCmd + * Description : Enable or disable SEMA4 IRQ notification. + * + *END**************************************************************************/ +void SEMA4_SetIntCmd(SEMA4_Type * base, uint16_t intMask, bool enable) +{ + if (enable) + base->CPnINE[SEMA4_PROCESSOR_SELF].INE |= intMask; + else + base->CPnINE[SEMA4_PROCESSOR_SELF].INE &= ~intMask; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/sema4.h b/zephyr/imx/drivers/sema4.h new file mode 100644 index 000000000..ff77185f0 --- /dev/null +++ b/zephyr/imx/drivers/sema4.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SEMA4_H__ +#define __SEMA4_H__ + +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup sema4_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SEMA4_PROCESSOR_NONE (0xFF) +#define SEMA4_GATE_STATUS_FLAG(gate) ((uint16_t)(1U << ((gate) ^ 7))) + +/*! @brief Status flag. */ +enum _sema4_status_flag +{ + sema4StatusFlagGate0 = 1U << 7, /*!< Sema4 Gate 0 flag. */ + sema4StatusFlagGate1 = 1U << 6, /*!< Sema4 Gate 1 flag. */ + sema4StatusFlagGate2 = 1U << 5, /*!< Sema4 Gate 2 flag. */ + sema4StatusFlagGate3 = 1U << 4, /*!< Sema4 Gate 3 flag. */ + sema4StatusFlagGate4 = 1U << 3, /*!< Sema4 Gate 4 flag. */ + sema4StatusFlagGate5 = 1U << 2, /*!< Sema4 Gate 5 flag. */ + sema4StatusFlagGate6 = 1U << 1, /*!< Sema4 Gate 6 flag. */ + sema4StatusFlagGate7 = 1U << 0, /*!< Sema4 Gate 7 flag. */ + sema4StatusFlagGate8 = 1U << 15, /*!< Sema4 Gate 8 flag. */ + sema4StatusFlagGate9 = 1U << 14, /*!< Sema4 Gate 9 flag. */ + sema4StatusFlagGate10 = 1U << 13, /*!< Sema4 Gate 10 flag. */ + sema4StatusFlagGate11 = 1U << 12, /*!< Sema4 Gate 11 flag. */ + sema4StatusFlagGate12 = 1U << 11, /*!< Sema4 Gate 12 flag. */ + sema4StatusFlagGate13 = 1U << 10, /*!< Sema4 Gate 13 flag. */ + sema4StatusFlagGate14 = 1U << 9, /*!< Sema4 Gate 14 flag. */ + sema4StatusFlagGate15 = 1U << 8, /*!< Sema4 Gate 15 flag. */ +}; + +/*! @brief SEMA4 reset finite state machine. */ +enum _sema4_reset_state +{ + sema4ResetIdle = 0U, /*!< Idle, waiting for the first data pattern write. */ + sema4ResetMid = 1U, /*!< Waiting for the second data pattern write. */ + sema4ResetFinished = 2U, /*!< Reset completed. Software can't get this state. */ +}; + +/*! @brief SEMA4 status return codes. */ +typedef enum _sema4_status +{ + statusSema4Success = 0U, /*!< Success. */ + statusSema4Busy = 1U, /*!< SEMA4 gate has been locked by other processor. */ +} sema4_status_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SEMA4 State Control + * @{ + */ + +/*! + * @brief Lock SEMA4 gate for exclusive access between multicore. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + * @retval statusSema4Success Lock the gate successfully. + * @retval statusSema4Busy SEMA4 gate has been locked by other processor. + */ +sema4_status_t SEMA4_TryLock(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Lock SEMA4 gate for exclusive access between multicore, polling until success. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + */ +void SEMA4_Lock(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Unlock SEMA4 gate. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + */ +void SEMA4_Unlock(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Get processor number which locks the SEMA4 gate. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + * @return processor number which locks the SEMA4 gate, or SEMA4_PROCESSOR_NONE + * to indicate the gate is not locked. + */ +uint32_t SEMA4_GetLockProcessor(SEMA4_Type *base, uint32_t gateIndex); + +/*@}*/ + +/*! + * @name SEMA4 Reset Control + * @{ + */ + +/*! + * @brief Reset SEMA4 gate to unlocked status. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + */ +void SEMA4_ResetGate(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Reset all SEMA4 gates to unlocked status. + * + * @param base SEMA4 base pointer. + */ +void SEMA4_ResetAllGates(SEMA4_Type *base); + +/*! + * @brief Get bus master number which performing the gate reset function. + * This function gets the bus master number which performing the + * gate reset function. + * + * @param base SEMA4 base pointer. + * @return Bus master number. + */ +static inline uint8_t SEMA4_GetGateResetBus(SEMA4_Type *base) +{ + return (uint8_t)(base->RSTGT & 7); +} + +/*! + * @brief Get sema4 gate reset state. + * This function gets current state of the sema4 reset gate finite + * state machine. + * + * @param base SEMA4 base pointer. + * @return Current state (see @ref _sema4_reset_state). + */ +static inline uint8_t SEMA4_GetGateResetState(SEMA4_Type *base) +{ + return (uint8_t)((base->RSTGT & 0x30) >> 4); +} + +/*! + * @brief Reset SEMA4 IRQ notification. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + */ +void SEMA4_ResetNotification(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Reset all IRQ notifications. + * + * @param base SEMA4 base pointer. + */ +void SEMA4_ResetAllNotifications(SEMA4_Type *base); + +/*! + * @brief Get bus master number which performing the notification reset function. + * This function gets the bus master number which performing the notification + * reset function. + * + * @param base SEMA4 base pointer. + * @return Bus master number. + */ +static inline uint8_t SEMA4_GetNotificationResetBus(SEMA4_Type *base) +{ + return (uint8_t)(base->RSTNTF & 7); +} + +/*! + * @brief Get sema4 notification reset state. + * + * This function gets current state of the sema4 reset notification finite state machine. + * + * @param base SEMA4 base pointer. + * @return Current state (See @ref _sema4_reset_state). + */ +static inline uint8_t SEMA4_GetNotificationResetState(SEMA4_Type *base) +{ + return (uint8_t)((base->RSTNTF & 0x30) >> 4); +} + +/*@}*/ + +/*! + * @name SEMA4 Interrupt and Status Control + * @{ + */ + +/*! + * @brief Get SEMA4 notification status. + * + * @param base SEMA4 base pointer. + * @param flags SEMA4 gate status mask (See @ref _sema4_status_flag). + * @return SEMA4 notification status bits. If bit value is set, the corresponding + * gate's notification is available. + */ +static inline uint16_t SEMA4_GetStatusFlag(SEMA4_Type * base, uint16_t flags) +{ + return base->CPnNTF[SEMA4_PROCESSOR_SELF].NTF & flags; +} + +/*! + * @brief Enable or disable SEMA4 IRQ notification. + * + * @param base SEMA4 base pointer. + * @param intMask SEMA4 gate status mask (see @ref _sema4_status_flag). + * @param enable Enable/Disable Sema4 interrupt, only those gates whose intMask is set are affected. + * - true: Enable Sema4 interrupt. + * - false: Disable Sema4 interrupt. + */ +void SEMA4_SetIntCmd(SEMA4_Type * base, uint16_t intMask, bool enable); + +/*! + * @brief check whether SEMA4 IRQ notification enabled. + * + * @param base SEMA4 base pointer. + * @param flags SEMA4 gate status mask (see @ref _sema4_status_flag). + * @return SEMA4 notification interrupt enable status bits. If bit value is set, + * the corresponding gate's notification is enabled + */ +static inline uint16_t SEMA4_GetIntEnabled(SEMA4_Type * base, uint16_t flags) +{ + return base->CPnINE[SEMA4_PROCESSOR_SELF].INE & flags; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __SEMA4_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/uart_imx.c b/zephyr/imx/drivers/uart_imx.c new file mode 100644 index 000000000..e3bfcdf49 --- /dev/null +++ b/zephyr/imx/drivers/uart_imx.c @@ -0,0 +1,612 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "uart_imx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_Init + * Description : This function initializes the module according to uart + * initialize structure. + * + *END**************************************************************************/ +void UART_Init(UART_Type* base, const uart_init_config_t* initConfig) +{ + assert(initConfig); + + /* Disable UART Module. */ + UART_UCR1_REG(base) &= ~UART_UCR1_UARTEN_MASK; + + /* Reset UART register to its default value. */ + UART_Deinit(base); + + /* Set UART data word length, stop bit count, parity mode and communication + * direction according to uart init struct, disable RTS hardware flow + * control. */ + UART_UCR2_REG(base) |= (initConfig->wordLength | + initConfig->stopBitNum | + initConfig->parity | + initConfig->direction | + UART_UCR2_IRTS_MASK); + + /* For imx family device, UARTs are used in MUXED mode, + * so that this bit should always be set.*/ + UART_UCR3_REG(base) |= UART_UCR3_RXDMUXSEL_MASK; + + /* Set BaudRate according to uart initialize struct. */ + /* Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)) */ + UART_SetBaudRate(base, initConfig->clockRate, initConfig->baudRate); +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_Deinit + * Description : This function reset Uart module register content to its + * default value. + * + *END**************************************************************************/ +void UART_Deinit(UART_Type* base) +{ + /* Disable UART Module */ + UART_UCR1_REG(base) &= ~UART_UCR1_UARTEN_MASK; + + /* Reset UART Module Register content to default value */ + UART_UCR1_REG(base) = 0x0; + UART_UCR2_REG(base) = UART_UCR2_SRST_MASK; + UART_UCR3_REG(base) = UART_UCR3_DSR_MASK | + UART_UCR3_DCD_MASK | + UART_UCR3_RI_MASK; + UART_UCR4_REG(base) = UART_UCR4_CTSTL(32); + UART_UFCR_REG(base) = UART_UFCR_TXTL(2) | UART_UFCR_RXTL(1); + UART_UESC_REG(base) = UART_UESC_ESC_CHAR(0x2B); + UART_UTIM_REG(base) = 0x0; + UART_ONEMS_REG(base) = 0x0; + UART_UTS_REG(base) = UART_UTS_TXEMPTY_MASK | UART_UTS_RXEMPTY_MASK; + UART_UMCR_REG(base) = 0x0; + + /* Reset the transmit and receive state machines, all FIFOs and register + * USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD and UTS[6-3]. */ + UART_UCR2_REG(base) &= ~UART_UCR2_SRST_MASK; + while (!(UART_UCR2_REG(base) & UART_UCR2_SRST_MASK)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetBaudRate + * Description : + * + *END**************************************************************************/ +void UART_SetBaudRate(UART_Type* base, uint32_t clockRate, uint32_t baudRate) +{ + uint32_t numerator; + uint32_t denominator; + uint32_t divisor; + uint32_t refFreqDiv; + uint32_t divider = 1; + + /* get the approximately maximum divisor */ + numerator = clockRate; + denominator = baudRate << 4; + divisor = 1; + + while (denominator != 0) + { + divisor = denominator; + denominator = numerator % denominator; + numerator = divisor; + } + + numerator = clockRate / divisor; + denominator = (baudRate << 4) / divisor; + + /* numerator ranges from 1 ~ 7 * 64k */ + /* denominator ranges from 1 ~ 64k */ + if ((numerator > (UART_UBIR_INC_MASK * 7)) || + (denominator > UART_UBIR_INC_MASK)) + { + uint32_t m = (numerator - 1) / (UART_UBIR_INC_MASK * 7) + 1; + uint32_t n = (denominator - 1) / UART_UBIR_INC_MASK + 1; + uint32_t max = m > n ? m : n; + numerator /= max; + denominator /= max; + if (0 == numerator) + numerator = 1; + if (0 == denominator) + denominator = 1; + } + divider = (numerator - 1) / UART_UBIR_INC_MASK + 1; + + switch (divider) + { + case 1: + refFreqDiv = 0x05; + break; + case 2: + refFreqDiv = 0x04; + break; + case 3: + refFreqDiv = 0x03; + break; + case 4: + refFreqDiv = 0x02; + break; + case 5: + refFreqDiv = 0x01; + break; + case 6: + refFreqDiv = 0x00; + break; + case 7: + refFreqDiv = 0x06; + break; + default: + refFreqDiv = 0x05; + } + + UART_UFCR_REG(base) &= ~UART_UFCR_RFDIV_MASK; + UART_UFCR_REG(base) |= UART_UFCR_RFDIV(refFreqDiv); + UART_UBIR_REG(base) = UART_UBIR_INC(denominator - 1); + UART_UBMR_REG(base) = UART_UBMR_MOD(numerator / divider - 1); + UART_ONEMS_REG(base) = UART_ONEMS_ONEMS(clockRate/(1000 * divider)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetInvertCmd + * Description : This function is used to set the polarity of UART signal. + * The polarity of Tx and Rx can be set separately. + * + *END**************************************************************************/ +void UART_SetInvertCmd(UART_Type* base, uint32_t direction, bool invert) +{ + assert((direction & uartDirectionTx) || (direction & uartDirectionRx)); + + if (invert) + { + if (direction & UART_UCR2_RXEN_MASK) + UART_UCR4_REG(base) |= UART_UCR4_INVR_MASK; + if (direction & UART_UCR2_TXEN_MASK) + UART_UCR3_REG(base) |= UART_UCR3_INVT_MASK; + } + else + { + if (direction & UART_UCR2_RXEN_MASK) + UART_UCR4_REG(base) &= ~UART_UCR4_INVR_MASK; + if (direction & UART_UCR2_TXEN_MASK) + UART_UCR3_REG(base) &= ~UART_UCR3_INVT_MASK; + } +} + +/******************************************************************************* + * Low Power Mode functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetDozeMode + * Description : This function is used to set UART enable condition in the + * DOZE state. + * + *END**************************************************************************/ +void UART_SetDozeMode(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR1_REG(base) &= UART_UCR1_DOZE_MASK; + else + UART_UCR1_REG(base) |= ~UART_UCR1_DOZE_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetLowPowerMode + * Description : This function is used to set UART enable condition of the + * UART low power feature. + * + *END**************************************************************************/ +void UART_SetLowPowerMode(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR4_REG(base) &= ~UART_UCR4_LPBYP_MASK; + else + UART_UCR4_REG(base) |= UART_UCR4_LPBYP_MASK; +} + +/******************************************************************************* + * Interrupt and Flag control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetIntCmd + * Description : This function is used to set the enable condition of + * specific UART interrupt source. The available interrupt + * source can be select from uart_int_source enumeration. + * + *END**************************************************************************/ +void UART_SetIntCmd(UART_Type* base, uint32_t intSource, bool enable) +{ + volatile uint32_t* uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (intSource >> 16)); + uart_mask = (1 << (intSource & 0x0000FFFF)); + + if (enable) + *uart_reg |= uart_mask; + else + *uart_reg &= ~uart_mask; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_GetStatusFlag + * Description : This function is used to get the current status of specific + * UART status flag. The available status flag can be select + * from uart_status_flag & uart_interrupt_flag enumeration. + * + *END**************************************************************************/ +/* +bool UART_GetStatusFlag(UART_Type* base, uint32_t flag) +{ + volatile uint32_t* uart_reg = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + return (bool)((*uart_reg >> (flag & 0x0000FFFF)) & 0x1); +} +*/ + +/*FUNCTION********************************************************************** + * + * Function Name : UART_ClearStatusFlag + * Description : This function is used to get the current status + * of specific UART status flag. The available status + * flag can be select from uart_status_flag & + * uart_interrupt_flag enumeration. + * + *END**************************************************************************/ +void UART_ClearStatusFlag(UART_Type* base, uint32_t flag) +{ + volatile uint32_t* uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + uart_mask = (1 << (flag & 0x0000FFFF)); + + /* write 1 to clear. */ + *uart_reg = uart_mask; +} + +/******************************************************************************* + * DMA control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetDmaCmd + * Description : This function is used to set the enable condition of + * specific UART DMA source. The available DMA + * source can be select from uart_dma_source enumeration. + * + *END**************************************************************************/ +void UART_SetDmaCmd(UART_Type* base, uint32_t dmaSource, bool enable) +{ + volatile uint32_t* uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (dmaSource >> 16)); + uart_mask = (1 << (dmaSource & 0x0000FFFF)); + if (enable) + *uart_reg |= uart_mask; + else + *uart_reg &= ~uart_mask; +} + +/******************************************************************************* + * Hardware Flow control and Modem Signal functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetRtsFlowCtrlCmd + * Description : This function is used to set the enable condition of RTS + * Hardware flow control. + * + *END**************************************************************************/ +void UART_SetRtsFlowCtrlCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR2_REG(base) &= ~UART_UCR2_IRTS_MASK; + else + UART_UCR2_REG(base) |= UART_UCR2_IRTS_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetCtsFlowCtrlCmd + * Description : This function is used to set the enable condition of CTS + * auto control. if CTS control is enabled, the CTS_B pin will + * be controlled by the receiver, otherwise the CTS_B pin will + * controlled by UART_CTSPinCtrl function. + * + *END**************************************************************************/ +void UART_SetCtsFlowCtrlCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR2_REG(base) |= UART_UCR2_CTSC_MASK; + else + UART_UCR2_REG(base) &= ~UART_UCR2_CTSC_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetCtsPinLevel + * Description : This function is used to control the CTS_B pin state when + * auto CTS control is disabled. + * The CTS_B pin is low (active) + * The CTS_B pin is high (inactive) + * + *END**************************************************************************/ +void UART_SetCtsPinLevel(UART_Type* base, bool active) +{ + if (active) + UART_UCR2_REG(base) |= UART_UCR2_CTS_MASK; + else + UART_UCR2_REG(base) &= ~UART_UCR2_CTS_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetModemMode + * Description : This function is used to set the role(DTE/DCE) of UART module + * in RS-232 communication. + * + *END**************************************************************************/ +void UART_SetModemMode(UART_Type* base, uint32_t mode) +{ + assert((mode == uartModemModeDce) || (mode == uartModemModeDte)); + + if (uartModemModeDce == mode) + UART_UFCR_REG(base) &= ~UART_UFCR_DCEDTE_MASK; + else + UART_UFCR_REG(base) |= UART_UFCR_DCEDTE_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetDtrPinLevel + * Description : This function is used to set the pin state of + * DSR pin(for DCE mode) or DTR pin(for DTE mode) for the + * modem interface. + * + *END**************************************************************************/ +void UART_SetDtrPinLevel(UART_Type* base, bool active) +{ + if (active) + UART_UCR3_REG(base) |= UART_UCR3_DSR_MASK; + else + UART_UCR3_REG(base) &= ~UART_UCR3_DSR_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetDcdPinLevel + * Description : This function is used to set the pin state of + * DCD pin. THIS FUNCTION IS FOR DCE MODE ONLY. + * + *END**************************************************************************/ +void UART_SetDcdPinLevel(UART_Type* base, bool active) +{ + if (active) + UART_UCR3_REG(base) |= UART_UCR3_DCD_MASK; + else + UART_UCR3_REG(base) &= ~UART_UCR3_DCD_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetRiPinLevel + * Description : This function is used to set the pin state of + * RI pin. THIS FUNCTION IS FOR DCE MODE ONLY. + * + *END**************************************************************************/ +void UART_SetRiPinLevel(UART_Type* base, bool active) +{ + if (active) + UART_UCR3_REG(base) |= UART_UCR3_RI_MASK; + else + UART_UCR3_REG(base) &= ~UART_UCR3_RI_MASK; +} + +/******************************************************************************* + * Multiprocessor and RS-485 functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_Putchar9 + * Description : This function is used to send 9 Bits length data in + * RS-485 Multidrop mode. + * + *END**************************************************************************/ +void UART_Putchar9(UART_Type* base, uint16_t data) +{ + assert(data <= 0x1FF); + + if (data & 0x0100) + UART_UMCR_REG(base) |= UART_UMCR_TXB8_MASK; + else + UART_UMCR_REG(base) &= ~UART_UMCR_TXB8_MASK; + UART_UTXD_REG(base) = (data & UART_UTXD_TX_DATA_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_Getchar9 + * Description : This functions is used to receive 9 Bits length data in + * RS-485 Multidrop mode. + * + *END**************************************************************************/ +uint16_t UART_Getchar9(UART_Type* base) +{ + uint16_t rxData = UART_URXD_REG(base); + + if (rxData & UART_URXD_PRERR_MASK) + { + rxData = (rxData & 0x00FF) | 0x0100; + } + else + { + rxData &= 0x00FF; + } + + return rxData; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetMultidropMode + * Description : This function is used to set the enable condition of + * 9-Bits data or Multidrop mode. + * + *END**************************************************************************/ +void UART_SetMultidropMode(UART_Type* base, bool enable) +{ + if (enable) + UART_UMCR_REG(base) |= UART_UMCR_MDEN_MASK; + else + UART_UMCR_REG(base) &= ~UART_UMCR_MDEN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetSlaveAddressDetectCmd + * Description : This function is used to set the enable condition of + * Automatic Address Detect Mode. + * + *END**************************************************************************/ +void UART_SetSlaveAddressDetectCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UMCR_REG(base) |= UART_UMCR_SLAM_MASK; + else + UART_UMCR_REG(base) &= ~UART_UMCR_SLAM_MASK; +} + +/******************************************************************************* + * IrDA control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetIrDACmd + * Description : This function is used to set the enable condition of + * IrDA Mode. + * + *END**************************************************************************/ +void UART_SetIrDACmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR1_REG(base) |= UART_UCR1_IREN_MASK; + else + UART_UCR1_REG(base) &= ~UART_UCR1_IREN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetIrDAVoteClock + * Description : This function is used to set the clock for the IR pulsed + * vote logic. The available clock can be select from + * uart_irda_vote_clock enumeration. + * + *END**************************************************************************/ +void UART_SetIrDAVoteClock(UART_Type* base, uint32_t voteClock) +{ + assert((voteClock == uartIrdaVoteClockSampling) || \ + (voteClock == uartIrdaVoteClockReference)); + + if (uartIrdaVoteClockSampling == voteClock) + UART_UCR4_REG(base) |= UART_UCR4_IRSC_MASK; + else + UART_UCR4_REG(base) &= ~UART_UCR4_IRSC_MASK; +} + +/******************************************************************************* + * Misc. functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetAutoBaudRateCmd + * Description : This function is used to set the enable condition of + * Automatic Baud Rate Detection feature. + * + *END**************************************************************************/ +void UART_SetAutoBaudRateCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR1_REG(base) |= UART_UCR1_ADBR_MASK; + else + UART_UCR1_REG(base) &= ~UART_UCR1_ADBR_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SendBreakChar + * Description : This function is used to send BREAK character.It is + * important that SNDBRK is asserted high for a sufficient + * period of time to generate a valid BREAK. + * + *END**************************************************************************/ +void UART_SendBreakChar(UART_Type* base, bool active) +{ + if (active) + UART_UCR1_REG(base) |= UART_UCR1_SNDBRK_MASK; + else + UART_UCR1_REG(base) &= ~UART_UCR1_SNDBRK_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetEscapeDecectCmd + * Description : This function is used to set the enable condition of + * Escape Sequence Detection feature. + * + *END**************************************************************************/ +void UART_SetEscapeDecectCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR2_REG(base) |= UART_UCR2_ESCEN_MASK; + else + UART_UCR2_REG(base) &= ~UART_UCR2_ESCEN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/uart_imx.h b/zephyr/imx/drivers/uart_imx.h new file mode 100644 index 000000000..911b4e683 --- /dev/null +++ b/zephyr/imx/drivers/uart_imx.h @@ -0,0 +1,779 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_IMX_H__ +#define __UART_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup uart_imx_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Uart module initialization structure. */ +typedef struct _uart_init_config +{ + uint32_t clockRate; /*!< Current UART module clock freq. */ + uint32_t baudRate; /*!< Desired UART baud rate. */ + uint32_t wordLength; /*!< Data bits in one frame. */ + uint32_t stopBitNum; /*!< Number of stop bits in one frame. */ + uint32_t parity; /*!< Parity error check mode of this module. */ + uint32_t direction; /*!< Data transfer direction of this module. */ +} uart_init_config_t; + +/*! @brief UART number of data bits in a character. */ +enum _uart_word_length +{ + uartWordLength7Bits = 0x0, /*!< One character has 7 bits. */ + uartWordLength8Bits = UART_UCR2_WS_MASK, /*!< One character has 8 bits. */ +}; + +/*! @brief UART number of stop bits. */ +enum _uart_stop_bit_num +{ + uartStopBitNumOne = 0x0, /*!< One bit Stop. */ + uartStopBitNumTwo = UART_UCR2_STPB_MASK, /*!< Two bits Stop. */ +}; + +/*! @brief UART parity mode. */ +enum _uart_partity_mode +{ + uartParityDisable = 0x0, /*!< Parity error check disabled. */ + uartParityEven = UART_UCR2_PREN_MASK, /*!< Even error check is selected. */ + uartParityOdd = UART_UCR2_PREN_MASK | UART_UCR2_PROE_MASK, /*!< Odd error check is selected. */ +}; + +/*! @brief Data transfer direction. */ +enum _uart_direction_mode +{ + uartDirectionDisable = 0x0, /*!< Both Tx and Rx are disabled. */ + uartDirectionTx = UART_UCR2_TXEN_MASK, /*!< Tx is enabled. */ + uartDirectionRx = UART_UCR2_RXEN_MASK, /*!< Rx is enabled. */ + uartDirectionTxRx = UART_UCR2_TXEN_MASK | UART_UCR2_RXEN_MASK, /*!< Both Tx and Rx are enabled. */ +}; + +/*! @brief This enumeration contains the settings for all of the UART interrupt configurations. */ +enum _uart_interrupt +{ + uartIntAutoBaud = 0x0080000F, /*!< Automatic baud rate detection Interrupt Enable. */ + uartIntTxReady = 0x0080000D, /*!< transmitter ready Interrupt Enable. */ + uartIntIdle = 0x0080000C, /*!< IDLE Interrupt Enable. */ + uartIntRxReady = 0x00800009, /*!< Receiver Ready Interrupt Enable. */ + uartIntTxEmpty = 0x00800006, /*!< Transmitter Empty Interrupt Enable. */ + uartIntRtsDelta = 0x00800005, /*!< RTS Delta Interrupt Enable. */ + uartIntEscape = 0x0084000F, /*!< Escape Sequence Interrupt Enable. */ + uartIntRts = 0x00840004, /*!< Request to Send Interrupt Enable. */ + uartIntAgingTimer = 0x00840003, /*!< Aging Timer Interrupt Enable. */ + uartIntDtr = 0x0088000D, /*!< Data Terminal Ready Interrupt Enable. */ + uartIntParityError = 0x0088000C, /*!< Parity Error Interrupt Enable. */ + uartIntFrameError = 0x0088000B, /*!< Frame Error Interrupt Enable. */ + uartIntDcd = 0x00880009, /*!< Data Carrier Detect Interrupt Enable. */ + uartIntRi = 0x00880008, /*!< Ring Indicator Interrupt Enable. */ + uartIntRxDs = 0x00880006, /*!< Receive Status Interrupt Enable. */ + uartInttAirWake = 0x00880005, /*!< Asynchronous IR WAKE Interrupt Enable. */ + uartIntAwake = 0x00880004, /*!< Asynchronous WAKE Interrupt Enable. */ + uartIntDtrDelta = 0x00880003, /*!< Data Terminal Ready Delta Interrupt Enable. */ + uartIntAutoBaudCnt = 0x00880000, /*!< Autobaud Counter Interrupt Enable. */ + uartIntIr = 0x008C0008, /*!< Serial Infrared Interrupt Enable. */ + uartIntWake = 0x008C0007, /*!< WAKE Interrupt Enable. */ + uartIntTxComplete = 0x008C0003, /*!< TransmitComplete Interrupt Enable. */ + uartIntBreakDetect = 0x008C0002, /*!< BREAK Condition Detected Interrupt Enable. */ + uartIntRxOverrun = 0x008C0001, /*!< Receiver Overrun Interrupt Enable. */ + uartIntRxDataReady = 0x008C0000, /*!< Receive Data Ready Interrupt Enable. */ + uartIntRs485SlaveAddrMatch = 0x00B80003, /*!< RS-485 Slave Address Detected Interrupt Enable. */ +}; + +/*! @brief Flag for UART interrupt/DMA status check or polling status. */ +enum _uart_status_flag +{ + uartStatusRxCharReady = 0x0000000F, /*!< Rx Character Ready Flag. */ + uartStatusRxError = 0x0000000E, /*!< Rx Error Detect Flag. */ + uartStatusRxOverrunError = 0x0000000D, /*!< Rx Overrun Flag. */ + uartStatusRxFrameError = 0x0000000C, /*!< Rx Frame Error Flag. */ + uartStatusRxBreakDetect = 0x0000000B, /*!< Rx Break Detect Flag. */ + uartStatusRxParityError = 0x0000000A, /*!< Rx Parity Error Flag. */ + uartStatusParityError = 0x0094000F, /*!< Parity Error Interrupt Flag. */ + uartStatusRtsStatus = 0x0094000E, /*!< RTS_B Pin Status Flag. */ + uartStatusTxReady = 0x0094000D, /*!< Transmitter Ready Interrupt/DMA Flag. */ + uartStatusRtsDelta = 0x0094000C, /*!< RTS Delta Flag. */ + uartStatusEscape = 0x0094000B, /*!< Escape Sequence Interrupt Flag. */ + uartStatusFrameError = 0x0094000A, /*!< Frame Error Interrupt Flag. */ + uartStatusRxReady = 0x00940009, /*!< Receiver Ready Interrupt/DMA Flag. */ + uartStatusAgingTimer = 0x00940008, /*!< Ageing Timer Interrupt Flag. */ + uartStatusDtrDelta = 0x00940007, /*!< DTR Delta Flag. */ + uartStatusRxDs = 0x00940006, /*!< Receiver IDLE Interrupt Flag. */ + uartStatustAirWake = 0x00940005, /*!< Asynchronous IR WAKE Interrupt Flag. */ + uartStatusAwake = 0x00940004, /*!< Asynchronous WAKE Interrupt Flag. */ + uartStatusRs485SlaveAddrMatch = 0x00940003, /*!< RS-485 Slave Address Detected Interrupt Flag. */ + uartStatusAutoBaud = 0x0098000F, /*!< Automatic Baud Rate Detect Complete Flag. */ + uartStatusTxEmpty = 0x0098000E, /*!< Transmit Buffer FIFO Empty. */ + uartStatusDtr = 0x0098000D, /*!< DTR edge triggered interrupt flag. */ + uartStatusIdle = 0x0098000C, /*!< Idle Condition Flag. */ + uartStatusAutoBaudCntStop = 0x0098000B, /*!< Autobaud Counter Stopped Flag. */ + uartStatusRiDelta = 0x0098000A, /*!< Ring Indicator Delta Flag. */ + uartStatusRi = 0x00980009, /*!< Ring Indicator Input Flag. */ + uartStatusIr = 0x00980008, /*!< Serial Infrared Interrupt Flag. */ + uartStatusWake = 0x00980007, /*!< Wake Flag. */ + uartStatusDcdDelta = 0x00980006, /*!< Data Carrier Detect Delta Flag. */ + uartStatusDcd = 0x00980005, /*!< Data Carrier Detect Input Flag. */ + uartStatusRts = 0x00980004, /*!< RTS Edge Triggered Interrupt Flag. */ + uartStatusTxComplete = 0x00980003, /*!< Transmitter Complete Flag. */ + uartStatusBreakDetect = 0x00980002, /*!< BREAK Condition Detected Flag. */ + uartStatusRxOverrun = 0x00980001, /*!< Overrun Error Flag. */ + uartStatusRxDataReady = 0x00980000, /*!< Receive Data Ready Flag. */ +}; + +/*! @brief The events generate the DMA Request. */ +enum _uart_dma +{ + uartDmaRxReady = 0x00800008, /*!< Receive Ready DMA Enable. */ + uartDmaTxReady = 0x00800003, /*!< Transmitter Ready DMA Enable. */ + uartDmaAgingTimer = 0x00800002, /*!< Aging DMA Timer Enable. */ + uartDmaIdle = 0x008C0006, /*!< DMA IDLE Condition Detected Interrupt Enable. */ +}; + +/*! @brief RTS pin interrupt trigger edge. */ +enum _uart_rts_int_trigger_edge +{ + uartRtsTriggerEdgeRising = UART_UCR2_RTEC(0), /*!< RTS pin interrupt triggered on rising edge. */ + uartRtsTriggerEdgeFalling = UART_UCR2_RTEC(1), /*!< RTS pin interrupt triggered on falling edge. */ + uartRtsTriggerEdgeBoth = UART_UCR2_RTEC(2), /*!< RTS pin interrupt triggered on both edge. */ +}; + +/*! @brief UART module modem role selections. */ +enum _uart_modem_mode +{ + uartModemModeDce = 0, /*!< UART module works as DCE. */ + uartModemModeDte = UART_UFCR_DCEDTE_MASK, /*!< UART module works as DTE. */ +}; + +/*! @brief DTR pin interrupt trigger edge. */ +enum _uart_dtr_int_trigger_edge +{ + uartDtrTriggerEdgeRising = UART_UCR3_DPEC(0), /*!< DTR pin interrupt triggered on rising edge. */ + uartDtrTriggerEdgeFalling = UART_UCR3_DPEC(1), /*!< DTR pin interrupt triggered on falling edge. */ + uartDtrTriggerEdgeBoth = UART_UCR3_DPEC(2), /*!< DTR pin interrupt triggered on both edge. */ +}; + +/*! @brief IrDA vote clock selections. */ +enum _uart_irda_vote_clock +{ + uartIrdaVoteClockSampling = 0x0, /*!< The vote logic uses the sampling clock (16x baud rate) for normal operation. */ + uartIrdaVoteClockReference = UART_UCR4_IRSC_MASK, /*!< The vote logic uses the UART reference clock. */ +}; + +/*! @brief UART module Rx Idle condition selections. */ +enum _uart_rx_idle_condition +{ + uartRxIdleMoreThan4Frames = UART_UCR1_ICD(0), /*!< Idle for more than 4 frames. */ + uartRxIdleMoreThan8Frames = UART_UCR1_ICD(1), /*!< Idle for more than 8 frames. */ + uartRxIdleMoreThan16Frames = UART_UCR1_ICD(2), /*!< Idle for more than 16 frames. */ + uartRxIdleMoreThan32Frames = UART_UCR1_ICD(3), /*!< Idle for more than 32 frames. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name UART Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initialize UART module with given initialization structure. + * + * @param base UART base pointer. + * @param initConfig UART initialization structure (see @ref uart_init_config_t structure above). + */ +void UART_Init(UART_Type* base, const uart_init_config_t* initConfig); + +/*! + * @brief This function reset UART module register content to its default value. + * + * @param base UART base pointer. + */ +void UART_Deinit(UART_Type* base); + +/*! + * @brief This function is used to Enable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Enable(UART_Type* base) +{ + UART_UCR1_REG(base) |= UART_UCR1_UARTEN_MASK; +} + +/*! + * @brief This function is used to Disable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Disable(UART_Type* base) +{ + UART_UCR1_REG(base) &= ~UART_UCR1_UARTEN_MASK; +} + +/*! + * @brief This function is used to set the baud rate of UART Module. + * + * @param base UART base pointer. + * @param clockRate UART module clock frequency. + * @param baudRate Desired UART module baud rate. + */ +void UART_SetBaudRate(UART_Type* base, uint32_t clockRate, uint32_t baudRate); + +/*! + * @brief This function is used to set the transform direction of UART Module. + * + * @param base UART base pointer. + * @param direction UART transfer direction (see @ref _uart_direction_mode enumeration). + */ +static inline void UART_SetDirMode(UART_Type* base, uint32_t direction) +{ + assert((direction & uartDirectionTx) || (direction & uartDirectionRx)); + + UART_UCR2_REG(base) = (UART_UCR2_REG(base) & ~(UART_UCR2_RXEN_MASK | UART_UCR2_TXEN_MASK)) | direction; +} + +/*! + * @brief This function is used to set the number of frames RXD is allowed to + * be idle before an idle condition is reported. The available condition + * can be select from @ref _uart_idle_condition enumeration. + * + * @param base UART base pointer. + * @param idleCondition The condition that an idle condition is reported + * (see @ref _uart_idle_condition enumeration). + */ +static inline void UART_SetRxIdleCondition(UART_Type* base, uint32_t idleCondition) +{ + assert(idleCondition <= uartRxIdleMoreThan32Frames); + + UART_UCR1_REG(base) = (UART_UCR1_REG(base) & ~UART_UCR1_ICD_MASK) | idleCondition; +} + +/*! + * @brief This function is used to set the polarity of UART signal. The polarity + * of Tx and Rx can be set separately. + * + * @param base UART base pointer. + * @param direction UART transfer direction (see @ref _uart_direction_mode enumeration). + * @param invert Set true to invert the polarity of UART signal. + */ +void UART_SetInvertCmd(UART_Type* base, uint32_t direction, bool invert); + +/*@}*/ + +/*! + * @name Low Power Mode functions. + * @{ + */ + +/*! + * @brief This function is used to set UART enable condition in the DOZE state. + * + * @param base UART base pointer. + * @param enable Enable/Disable UART module in doze mode. + * - true: Enable UART module in doze mode. + * - false: Disable UART module in doze mode. + */ +void UART_SetDozeMode(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set UART enable condition of the UART low power feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable UART module low power feature. + * - true: Enable UART module low power feature. + * - false: Disable UART module low power feature. + */ +void UART_SetLowPowerMode(UART_Type* base, bool enable); + +/*@}*/ + +/*! + * @name Data transfer functions. + * @{ + */ + +/*! + * @brief This function is used to send data in RS-232 and IrDA Mode. + * A independent 9 Bits RS-485 send data function is provided. + * + * @param base UART base pointer. + * @param data Data to be set through UART module. + */ +static inline void UART_Putchar(UART_Type* base, uint8_t data) +{ + UART_UTXD_REG(base) = (data & UART_UTXD_TX_DATA_MASK); +} + +/*! + * @brief This function is used to receive data in RS-232 and IrDA Mode. + * A independent 9 Bits RS-485 receive data function is provided. + * + * @param base UART base pointer. + * @return The data received from UART module. + */ +static inline uint8_t UART_Getchar(UART_Type* base) +{ + return (uint8_t)(UART_URXD_REG(base) & UART_URXD_RX_DATA_MASK); +} + +/*@}*/ + +/*! + * @name Interrupt and Flag control functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * specific UART interrupt source. The available interrupt + * source can be select from @ref _uart_interrupt enumeration. + * + * @param base UART base pointer. + * @param intSource Available interrupt source for this module. + * @param enable Enable/Disable corresponding interrupt. + * - true: Enable corresponding interrupt. + * - false: Disable corresponding interrupt. + */ +void UART_SetIntCmd(UART_Type* base, uint32_t intSource, bool enable); + +/*! + * @brief This function is used to get the current status of specific + * UART status flag(including interrupt flag). The available + * status flag can be select from @ref _uart_status_flag enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to check. + * @return current state of corresponding status flag. + */ +static inline bool UART_GetStatusFlag(UART_Type* base, uint32_t flag){ + volatile uint32_t* uart_reg = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + return (bool)((*uart_reg >> (flag & 0x0000FFFF)) & 0x1); +} + +/*! + * @brief This function is used to get the current status + * of specific UART status flag. The available status + * flag can be select from @ref _uart_status_flag enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to clear. + */ +void UART_ClearStatusFlag(UART_Type* base, uint32_t flag); + +/*@}*/ + +/*! + * @name DMA control functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * specific UART DMA source. The available DMA source + * can be select from @ref _uart_dma enumeration. + * + * @param base UART base pointer. + * @param dmaSource The Event that can generate DMA request. + * @param enable Enable/Disable corresponding DMA source. + * - true: Enable corresponding DMA source. + * - false: Disable corresponding DMA source. + */ +void UART_SetDmaCmd(UART_Type* base, uint32_t dmaSource, bool enable); + +/*@}*/ + +/*! + * @name FIFO control functions. + * @{ + */ + +/*! + * @brief This function is used to set the watermark of UART Tx FIFO. + * A maskable interrupt is generated whenever the data level in + * the TxFIFO falls below the Tx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Tx FIFO watermark. + */ +static inline void UART_SetTxFifoWatermark(UART_Type* base, uint8_t watermark) +{ + assert((watermark >= 2) && (watermark <= 32)); + UART_UFCR_REG(base) = (UART_UFCR_REG(base) & ~UART_UFCR_TXTL_MASK) | UART_UFCR_TXTL(watermark); +} + +/*! + * @brief This function is used to set the watermark of UART Rx FIFO. + * A maskable interrupt is generated whenever the data level in + * the RxFIFO reaches the Rx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Rx FIFO watermark. + */ +static inline void UART_SetRxFifoWatermark(UART_Type* base, uint8_t watermark) +{ + assert(watermark <= 32); + UART_UFCR_REG(base) = (UART_UFCR_REG(base) & ~UART_UFCR_RXTL_MASK) | UART_UFCR_RXTL(watermark); +} + +/*@}*/ + +/*! + * @name Hardware Flow control and Modem Signal functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of RTS + * Hardware flow control. + * + * @param base UART base pointer. + * @param enable Enable/Disbale RTS hardware flow control. + * - true: Enable RTS hardware flow control. + * - false: Disbale RTS hardware flow control. + */ +void UART_SetRtsFlowCtrlCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the RTS interrupt trigger edge. + * The available trigger edge can be select from + * @ref _uart_rts_trigger_edge enumeration. + * + * @param base UART base pointer. + * @param triggerEdge Available RTS pin interrupt trigger edge. + */ +static inline void UART_SetRtsIntTriggerEdge(UART_Type* base, uint32_t triggerEdge) +{ + assert((triggerEdge == uartRtsTriggerEdgeRising) || \ + (triggerEdge == uartRtsTriggerEdgeFalling) || \ + (triggerEdge == uartRtsTriggerEdgeBoth)); + + UART_UCR2_REG(base) = (UART_UCR2_REG(base) & ~UART_UCR2_RTEC_MASK) | triggerEdge; +} + + +/*! + * @brief This function is used to set the enable condition of CTS + * auto control. if CTS control is enabled, the CTS_B pin + * is controlled by the receiver, otherwise the CTS_B pin is + * controlled by UART_CTSPinCtrl function. + * + * @param base UART base pointer. + * @param enable Enable/Disable CTS auto control. + * - true: Enable CTS auto control. + * - false: Disable CTS auto control. + */ +void UART_SetCtsFlowCtrlCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to control the CTS_B pin state when + * auto CTS control is disabled. + * The CTS_B pin is low(active) + * The CTS_B pin is high(inactive) + * + * @param base UART base pointer. + * @param active The CTS_B pin state to set. + * - true: the CTS_B pin active; + * - false: the CTS_B pin inactive. + */ +void UART_SetCtsPinLevel(UART_Type* base, bool active); + +/*! + * @brief This function is used to set the auto CTS_B pin control + * trigger level. The CTS_B pin is de-asserted when + * Rx FIFO reach CTS trigger level. + * + * @param base UART base pointer. + * @param triggerLevel Auto CTS_B pin control trigger level. + */ +static inline void UART_SetCtsTriggerLevel(UART_Type* base, uint8_t triggerLevel) +{ + assert(triggerLevel <= 32); + UART_UCR4_REG(base) = (UART_UCR4_REG(base) & ~UART_UCR4_CTSTL_MASK) | UART_UCR4_CTSTL(triggerLevel); +} + +/*! + * @brief This function is used to set the role (DTE/DCE) of UART module + * in RS-232 communication. + * + * @param base UART base pointer. + * @param mode The role(DTE/DCE) of UART module (see @ref _uart_modem_mode enumeration). + */ +void UART_SetModemMode(UART_Type* base, uint32_t mode); + +/*! + * @brief This function is used to set the edge of DTR_B (DCE) or + * DSR_B (DTE) on which an interrupt is generated. + * + * @param base UART base pointer. + * @param triggerEdge The trigger edge on which an interrupt is generated + * (see @ref _uart_dtr_trigger_edge enumeration above). + */ +static inline void UART_SetDtrIntTriggerEdge(UART_Type* base, uint32_t triggerEdge) +{ + assert((triggerEdge == uartDtrTriggerEdgeRising) || \ + (triggerEdge == uartDtrTriggerEdgeFalling) || \ + (triggerEdge == uartDtrTriggerEdgeBoth)); + + UART_UCR3_REG(base) = (UART_UCR3_REG(base) & ~UART_UCR3_DPEC_MASK) | triggerEdge; +} + +/*! + * @brief This function is used to set the pin state of DSR pin(for DCE mode) + * or DTR pin(for DTE mode) for the modem interface. + * + * @param base UART base pointer. + * @param active The state of DSR pin. + * - true: DSR/DTR pin is logic one. + * - false: DSR/DTR pin is logic zero. + */ +void UART_SetDtrPinLevel(UART_Type* base, bool active); + +/*! + * @brief This function is used to set the pin state of + * DCD pin. THIS FUNCTION IS FOR DCE MODE ONLY. + * + * @param base UART base pointer. + * @param active The state of DCD pin. + * - true: DCD_B pin is logic one (DCE mode) + * - false: DCD_B pin is logic zero (DCE mode) + */ +void UART_SetDcdPinLevel(UART_Type* base, bool active); + +/*! + * @brief This function is used to set the pin state of + * RI pin. THIS FUNCTION IS FOR DCE MODE ONLY. + * + * @param base UART base pointer. + * @param active The state of RI pin. + * - true: RI_B pin is logic one (DCE mode) + * - false: RI_B pin is logic zero (DCE mode) + */ +void UART_SetRiPinLevel(UART_Type* base, bool active); + +/*@}*/ + +/*! + * @name Multiprocessor and RS-485 functions. + * @{ + */ + +/*! + * @brief This function is used to send 9 Bits length data in + * RS-485 Multidrop mode. + * + * @param base UART base pointer. + * @param data Data(9 bits) to be set through UART module. + */ +void UART_Putchar9(UART_Type* base, uint16_t data); + +/*! + * @brief This functions is used to receive 9 Bits length data in + * RS-485 Multidrop mode. + * + * @param base UART base pointer. + * @return The data(9 bits) received from UART module. + */ +uint16_t UART_Getchar9(UART_Type* base); + +/*! + * @brief This function is used to set the enable condition of + * 9-Bits data or Multidrop mode. + * + * @param base UART base pointer. + * @param enable Enable/Disable Multidrop mode. + * - true: Enable Multidrop mode. + * - false: Disable Multidrop mode. + */ +void UART_SetMultidropMode(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the enable condition of + * Automatic Address Detect Mode. + * + * @param base UART base pointer. + * @param enable Enable/Disable Automatic Address Detect mode. + * - true: Enable Automatic Address Detect mode. + * - false: Disable Automatic Address Detect mode. + */ +void UART_SetSlaveAddressDetectCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the slave address char + * that the receiver tries to detect. + * + * @param base UART base pointer. + * @param slaveAddress The slave to detect. + */ +static inline void UART_SetSlaveAddress(UART_Type* base, uint8_t slaveAddress) +{ + UART_UMCR_REG(base) = (UART_UMCR_REG(base) & ~UART_UMCR_SLADDR_MASK) | \ + UART_UMCR_SLADDR(slaveAddress); +} + +/*@}*/ + +/*! + * @name IrDA control functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * IrDA Mode. + * + * @param base UART base pointer. + * @param enable Enable/Disable IrDA mode. + * - true: Enable IrDA mode. + * - false: Disable IrDA mode. + */ +void UART_SetIrDACmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the clock for the IR pulsed + * vote logic. The available clock can be select from + * @ref _uart_irda_vote_clock enumeration. + * + * @param base UART base pointer. + * @param voteClock The available IrDA vote clock selection. + */ +void UART_SetIrDAVoteClock(UART_Type* base, uint32_t voteClock); + +/*@}*/ + +/*! + * @name Misc. functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * Automatic Baud Rate Detection feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable Automatic Baud Rate Detection feature. + * - true: Enable Automatic Baud Rate Detection feature. + * - false: Disable Automatic Baud Rate Detection feature. + */ +void UART_SetAutoBaudRateCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to read the current value of Baud Rate + * Count Register value. this counter is used by Auto Baud Rate + * Detect feature. + * + * @param base UART base pointer. + * @return Current Baud Rate Count Register value. + */ +static inline uint16_t UART_ReadBaudRateCount(UART_Type* base) +{ + return (uint16_t)(UART_UBRC_REG(base) & UART_UBRC_BCNT_MASK); +} + +/*! + * @brief This function is used to send BREAK character.It is + * important that SNDBRK is asserted high for a sufficient + * period of time to generate a valid BREAK. + * + * @param base UART base pointer. + * @param active Asserted high to generate BREAK. + * - true: Generate BREAK character. + * - false: Stop generate BREAK character. + */ +void UART_SendBreakChar(UART_Type* base, bool active); + +/*! + * @brief This function is used to Enable/Disable the Escape + * Sequence Decection feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable Escape Sequence Decection. + * - true: Enable Escape Sequence Decection. + * - false: Disable Escape Sequence Decection. + */ +void UART_SetEscapeDecectCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the enable condition of + * Escape Sequence Detection feature. + * + * @param base UART base pointer. + * @param escapeChar The Escape Character to detect. + */ +static inline void UART_SetEscapeChar(UART_Type* base, uint8_t escapeChar) +{ + UART_UESC_REG(base) = (UART_UESC_REG(base) & ~UART_UESC_ESC_CHAR_MASK) | \ + UART_UESC_ESC_CHAR(escapeChar); +} + +/*! + * @brief This function is used to set the maximum time interval (in ms) + * allowed between escape characters. + * + * @param base UART base pointer. + * @param timerInterval Maximum time interval allowed between escape characters. + */ +static inline void UART_SetEscapeTimerInterval(UART_Type* base, uint16_t timerInterval) +{ + assert(timerInterval <= 0xFFF); + UART_UTIM_REG(base) = (UART_UTIM_REG(base) & ~UART_UTIM_TIM_MASK) | \ + UART_UTIM_TIM(timerInterval); +} + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __UART_IMX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/wdog_imx.c b/zephyr/imx/drivers/wdog_imx.c new file mode 100644 index 000000000..c8c62d214 --- /dev/null +++ b/zephyr/imx/drivers/wdog_imx.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "wdog_imx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : WDOG_Enable + * Description : Configure WDOG funtions, call once only + * + *END**************************************************************************/ +void WDOG_Enable(WDOG_Type *base, uint8_t timeout) +{ + uint16_t wcr = base->WCR & (~WDOG_WCR_WT_MASK); + base->WCR = wcr | WDOG_WCR_WT(timeout) | WDOG_WCR_WDE_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : WDOG_Reset + * Description : Assert WDOG reset signal + * + *END**************************************************************************/ +void WDOG_Reset(WDOG_Type *base, bool wda, bool srs) +{ + uint16_t wcr = base->WCR; + + if (wda) + wcr &= ~WDOG_WCR_WDA_MASK; + if (srs) + wcr &= ~WDOG_WCR_SRS_MASK; + + base->WCR = wcr; +} + +/*FUNCTION********************************************************************** + * + * Function Name : WDOG_Refresh + * Description : Refresh the WDOG to prevent timeout + * + *END**************************************************************************/ +void WDOG_Refresh(WDOG_Type *base) +{ + base->WSR = 0x5555; + base->WSR = 0xAAAA; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/imx/drivers/wdog_imx.h b/zephyr/imx/drivers/wdog_imx.h new file mode 100644 index 000000000..8b053df10 --- /dev/null +++ b/zephyr/imx/drivers/wdog_imx.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __WDOG_IMX_H__ +#define __WDOG_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup wdog_imx_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The reset source of latest reset. */ +enum _wdog_reset_source +{ + wdogResetSourcePor = WDOG_WRSR_POR_MASK, /*!< Indicates the reset is the result of a power on reset.*/ + wdogResetSourceTimeout = WDOG_WRSR_TOUT_MASK, /*!< Indicates the reset is the result of a WDOG timeout.*/ + wdogResetSourceSwRst = WDOG_WRSR_SFTW_MASK, /*!< Indicates the reset is the result of a software reset.*/ +}; + +/*! @brief Structure to configure the running mode. */ +typedef struct _wdog_init_config +{ + bool wdw; /*!< true: suspend in low power wait, false: not suspend */ + bool wdt; /*!< true: assert WDOG_B when timeout, false: not assert WDOG_B */ + bool wdbg; /*!< true: suspend in debug mode, false: not suspend */ + bool wdzst; /*!< true: suspend in doze and stop mode, false: not suspend */ +} wdog_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name WDOG State Control + * @{ + */ + +/*! + * @brief Configure WDOG functions, call once only + * + * @param base WDOG base pointer. + * @param initConfig WDOG mode configuration + */ +static inline void WDOG_Init(WDOG_Type *base, const wdog_init_config_t *initConfig) +{ + base->WCR |= (initConfig->wdw ? WDOG_WCR_WDW_MASK : 0) | + (initConfig->wdt ? WDOG_WCR_WDT_MASK : 0) | + (initConfig->wdbg ? WDOG_WCR_WDBG_MASK : 0) | + (initConfig->wdzst ? WDOG_WCR_WDZST_MASK : 0); +} + +/*! + * @brief Enable WDOG with timeout, call once only + * + * @param base WDOG base pointer. + * @param timeout WDOG timeout ((n+1)/2 second) + */ +void WDOG_Enable(WDOG_Type *base, uint8_t timeout); + +/*! + * @brief Assert WDOG software reset signal + * + * @param base WDOG base pointer. + * @param wda WDOG reset. + * - true: Assert WDOG_B. + * - false: No impact on WDOG_B. + * @param srs System reset. + * - true: Assert system reset WDOG_RESET_B_DEB. + * - false: No impact on system reset. + */ +void WDOG_Reset(WDOG_Type *base, bool wda, bool srs); + +/*! + * @brief Get the latest reset source generated due to + * WatchDog Timer. + * + * @param base WDOG base pointer. + * @return The latest reset source (see @ref _wdog_reset_source enumeration). + */ +static inline uint32_t WDOG_GetResetSource(WDOG_Type *base) +{ + return base->WRSR; +} + +/*! + * @brief Refresh the WDOG to prevent timeout + * + * @param base WDOG base pointer. + */ +void WDOG_Refresh(WDOG_Type *base); + +/*! + * @brief Disable WDOG power down counter + * + * @param base WDOG base pointer. + */ +static inline void WDOG_DisablePowerdown(WDOG_Type *base) +{ + base->WMCR &= ~WDOG_WMCR_PDE_MASK; +} + +/*@}*/ + +/*! + * @name WDOG Interrupt Control + * @{ + */ + +/*! + * @brief Enable WDOG interrupt + * + * @param base WDOG base pointer. + * @param time how long before the timeout must the interrupt occur (n/2 seconds). + */ +static inline void WDOG_EnableInt(WDOG_Type *base, uint8_t time) +{ + base->WICR = WDOG_WICR_WIE_MASK | WDOG_WICR_WICT(time); +} + +/*! + * @brief Check whether WDOG interrupt is pending + * + * @param base WDOG base pointer. + * @return WDOG interrupt status. + * - true: Pending. + * - false: Not pending. + */ +static inline bool WDOG_IsIntPending(WDOG_Type *base) +{ + return (bool)(base->WICR & WDOG_WICR_WTIS_MASK); +} + +/*! + * @brief Clear WDOG interrupt status + * + * @param base WDOG base pointer. + */ +static inline void WDOG_ClearStatusFlag(WDOG_Type *base) +{ + base->WICR |= WDOG_WICR_WTIS_MASK; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __WDOG_IMX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/zephyr/middleware/usb/CMakeLists.txt b/zephyr/middleware/usb/CMakeLists.txt new file mode 100644 index 000000000..4e653bcbe --- /dev/null +++ b/zephyr/middleware/usb/CMakeLists.txt @@ -0,0 +1,15 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(./include) +add_subdirectory_ifdef( + CONFIG_USB_DEVICE_DRIVER + device + ) +add_subdirectory_ifdef( + CONFIG_USB_DEVICE_DRIVER + phy + ) diff --git a/zephyr/middleware/usb/device/CMakeLists.txt b/zephyr/middleware/usb/device/CMakeLists.txt new file mode 100644 index 000000000..61f2f8d4c --- /dev/null +++ b/zephyr/middleware/usb/device/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) +zephyr_library_sources_ifdef(CONFIG_USB_DC_NXP_EHCI usb_device_ehci.c) +zephyr_library_sources_ifdef(CONFIG_USB_DC_NXP_LPCIP3511 usb_device_lpcip3511.c) diff --git a/zephyr/middleware/usb/device/usb_device.h b/zephyr/middleware/usb/device/usb_device.h new file mode 100644 index 000000000..2f9358f6c --- /dev/null +++ b/zephyr/middleware/usb/device/usb_device.h @@ -0,0 +1,660 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_DEVICE_H__ +#define __USB_DEVICE_H__ + +#include "usb.h" + +/*! + * @addtogroup usb_device_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Defines Get/Set status Types */ +typedef enum _usb_device_status +{ + kUSB_DeviceStatusTestMode = 1U, /*!< Test mode */ + kUSB_DeviceStatusSpeed, /*!< Current speed */ + kUSB_DeviceStatusOtg, /*!< OTG status */ + kUSB_DeviceStatusDevice, /*!< Device status */ + kUSB_DeviceStatusEndpoint, /*!< Endpoint state usb_device_endpoint_status_t */ + kUSB_DeviceStatusDeviceState, /*!< Device state */ + kUSB_DeviceStatusAddress, /*!< Device address */ + kUSB_DeviceStatusSynchFrame, /*!< Current frame */ + kUSB_DeviceStatusBus, /*!< Bus status */ + kUSB_DeviceStatusBusSuspend, /*!< Bus suspend */ + kUSB_DeviceStatusBusSleep, /*!< Bus suspend */ + kUSB_DeviceStatusBusResume, /*!< Bus resume */ + kUSB_DeviceStatusRemoteWakeup, /*!< Remote wakeup state */ + kUSB_DeviceStatusBusSleepResume, /*!< Bus resume */ +#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U) + kUSB_DeviceStatusGetCurrentFrameCount, /*!< Get current frame count */ +#endif +} usb_device_status_t; + +/*! @brief Defines USB 2.0 device state */ +typedef enum _usb_device_state +{ + kUSB_DeviceStateConfigured = 0U, /*!< Device state, Configured*/ + kUSB_DeviceStateAddress, /*!< Device state, Address*/ + kUSB_DeviceStateDefault, /*!< Device state, Default*/ + kUSB_DeviceStateAddressing, /*!< Device state, Address setting*/ + kUSB_DeviceStateTestMode, /*!< Device state, Test mode*/ +} usb_device_state_t; + +/*! @brief Defines endpoint state */ +typedef enum _usb_endpoint_status +{ + kUSB_DeviceEndpointStateIdle = 0U, /*!< Endpoint state, idle*/ + kUSB_DeviceEndpointStateStalled, /*!< Endpoint state, stalled*/ +} usb_device_endpoint_status_t; + +/*! @brief Control endpoint index */ +#define USB_CONTROL_ENDPOINT (0U) +/*! @brief Control endpoint maxPacketSize */ +#define USB_CONTROL_MAX_PACKET_SIZE (64U) + +#if (USB_DEVICE_CONFIG_EHCI && (USB_CONTROL_MAX_PACKET_SIZE != (64U))) +#error For high speed, USB_CONTROL_MAX_PACKET_SIZE must be 64!!! +#endif + +/*! @brief The setup packet size of USB control transfer. */ +#define USB_SETUP_PACKET_SIZE (8U) +/*! @brief USB endpoint mask */ +#define USB_ENDPOINT_NUMBER_MASK (0x0FU) + +/*! @brief uninitialized value */ +#define USB_UNINITIALIZED_VAL_32 (0xFFFFFFFFU) + +/*! @brief the endpoint callback length of cancelled transfer */ +#define USB_CANCELLED_TRANSFER_LENGTH (0xFFFFFFFFU) + +/*! @brief invalid tranfer buffer addresss */ +#define USB_INVALID_TRANSFER_BUFFER (0xFFFFFFFEU) + +#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U) +/* USB device IP3511 max frame count */ +#define USB_DEVICE_IP3511_MAX_FRAME_COUNT (0x000007FFU) +/* USB device EHCI max frame count */ +#define USB_DEVICE_EHCI_MAX_FRAME_COUNT (0x00003FFFU) +/* USB device EHCI max frame count */ +#define USB_DEVICE_KHCI_MAX_FRAME_COUNT (0x000007FFU) + +/*! @brief usb device controller max frame count */ +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_KHCI_MAX_FRAME_COUNT) +#elif (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_IP3511_MAX_FRAME_COUNT) +#elif ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +#define USB_DEVICE_MAX_FRAME_COUNT (USB_DEVICE_EHCI_MAX_FRAME_COUNT) +#endif +#endif + +/*! @brief Available common EVENT types in device callback */ +typedef enum _usb_device_event +{ + kUSB_DeviceEventBusReset = 1U, /*!< USB bus reset signal detected */ + kUSB_DeviceEventSuspend, /*!< USB bus suspend signal detected */ + kUSB_DeviceEventResume, /*!< USB bus resume signal detected. The resume signal is driven by itself or a host */ + kUSB_DeviceEventSleeped, /*!< USB bus LPM suspend signal detected */ + kUSB_DeviceEventLPMResume, /*!< USB bus LPM resume signal detected. The resume signal is driven by itself or a host + */ + kUSB_DeviceEventError, /*!< An error is happened in the bus. */ + kUSB_DeviceEventDetach, /*!< USB device is disconnected from a host. */ + kUSB_DeviceEventAttach, /*!< USB device is connected to a host. */ + kUSB_DeviceEventSetConfiguration, /*!< Set configuration. */ + kUSB_DeviceEventSetInterface, /*!< Set interface. */ + + kUSB_DeviceEventGetDeviceDescriptor, /*!< Get device descriptor. */ + kUSB_DeviceEventGetConfigurationDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetStringDescriptor, /*!< Get string descriptor. */ + kUSB_DeviceEventGetHidDescriptor, /*!< Get HID descriptor. */ + kUSB_DeviceEventGetHidReportDescriptor, /*!< Get HID report descriptor. */ + kUSB_DeviceEventGetHidPhysicalDescriptor, /*!< Get HID physical descriptor. */ + kUSB_DeviceEventGetBOSDescriptor, /*!< Get configuration descriptor. */ + kUSB_DeviceEventGetDeviceQualifierDescriptor, /*!< Get device qualifier descriptor. */ + kUSB_DeviceEventVendorRequest, /*!< Vendor request. */ + kUSB_DeviceEventSetRemoteWakeup, /*!< Enable or disable remote wakeup function. */ + kUSB_DeviceEventGetConfiguration, /*!< Get current configuration index */ + kUSB_DeviceEventGetInterface, /*!< Get current interface alternate setting value */ + kUSB_DeviceEventSetBHNPEnable, +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + kUSB_DeviceEventDcdDetectionfinished, /*!< The DCD detection finished */ +#endif +} usb_device_event_t; + +/*! @brief Endpoint callback message structure */ +typedef struct _usb_device_endpoint_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_endpoint_callback_message_struct_t; + +/*! + * @brief Endpoint callback function typedef. + * + * This callback function is used to notify the upper layer what the transfer result is. + * This callback pointer is passed when a specified endpoint is initialized by calling API #USB_DeviceInitEndpoint. + * + * @param handle The device handle. It equals to the value returned from #USB_DeviceInit. + * @param message The result of a transfer, which includes transfer buffer, transfer length, and whether is in a + * setup phase. + * phase for control pipe. + * @param callbackParam The parameter for this callback. It is same with + * usb_device_endpoint_callback_struct_t::callbackParam. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_endpoint_callback_t)(usb_device_handle handle, + usb_device_endpoint_callback_message_struct_t *message, + void *callbackParam); + +/*! + * @brief Device callback function typedef. + * + * This callback function is used to notify the upper layer that the device status has changed. + * This callback pointer is passed by calling API #USB_DeviceInit. + * + * @param handle The device handle. It equals the value returned from #USB_DeviceInit. + * @param callbackEvent The callback event type. See enumeration #usb_device_event_t. + * @param eventParam The event parameter for this callback. The parameter type is determined by the callback event. + * + * @return A USB error code or kStatus_USB_Success. + */ +typedef usb_status_t (*usb_device_callback_t)(usb_device_handle handle, uint32_t callbackEvent, void *eventParam); + +/*! @brief Endpoint callback structure */ +typedef struct _usb_device_endpoint_callback_struct +{ + usb_device_endpoint_callback_t callbackFn; /*!< Endpoint callback function*/ + void *callbackParam; /*!< Parameter for callback function*/ + uint8_t isBusy; +} usb_device_endpoint_callback_struct_t; + +/*! @brief Endpoint initialization structure */ +typedef struct _usb_device_endpoint_init_struct +{ + uint16_t maxPacketSize; /*!< Endpoint maximum packet size */ + uint8_t endpointAddress; /*!< Endpoint address*/ + uint8_t transferType; /*!< Endpoint transfer type*/ + uint8_t zlt; /*!< ZLT flag*/ + uint8_t interval; /*!< Endpoint interval*/ +} usb_device_endpoint_init_struct_t; + +/*! @brief Endpoint status structure */ +typedef struct _usb_device_endpoint_status_struct +{ + uint8_t endpointAddress; /*!< Endpoint address */ + uint16_t endpointStatus; /*!< Endpoint status : idle or stalled */ +} usb_device_endpoint_status_struct_t; + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @name USB device APIs + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device stack. + * + * This function initializes the USB device module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration #usb_controller_index_t. + * @param[in] deviceCallback Function pointer of the device callback. + * @param[out] handle It is an out parameter used to return the pointer of the device handle to the caller. + * + * @retval kStatus_USB_Success The device is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. + * @retval kStatus_USB_Busy Cannot allocate a device handle. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller according to the controller id. + * @retval kStatus_USB_InvalidControllerInterface The controller driver interfaces is invalid. There is an empty + * interface entity. + * @retval kStatus_USB_Error The macro USB_DEVICE_CONFIG_ENDPOINTS is more than the IP's endpoint number. + * Or, the device has been initialized. + * Or, the mutex or message queue is created failed. + */ +extern usb_status_t USB_DeviceInit(uint8_t controllerId, + usb_device_callback_t deviceCallback, + usb_device_handle *handle); + +/*! + * @brief Enables the device functionality. + * + * The function enables the device functionality, so that the device can be recognized by the host when the device + * detects that it has been connected to a host. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is run successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceRun(usb_device_handle handle); + +/*! + * @brief Disables the device functionality. + * + * The function disables the device functionality. After this function called, even if the device is detached to the + * host, + * it can't work. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceStop(usb_device_handle handle); + +/*! + * @brief De-initializes the device controller. + * + * The function de-initializes the device controller specified by the handle. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device is stopped successfully. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + */ +extern usb_status_t USB_DeviceDeinit(usb_device_handle handle); + +/*! + * @brief Sends data through a specified endpoint. + * + * The function is used to send data through a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. The function is not reentrant. + * @param[in] length The data length need to be sent. + * + * @retval kStatus_USB_Success The send request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the sending request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceSendRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receives data through a specified endpoint. + * + * The function is used to receive data through a specified endpoint. The function is not reentrant. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @retval kStatus_USB_Success The receive request is sent successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_Busy Cannot allocate DTDS for current transfer in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error The device is doing reset. + * + * @note The return value indicates whether the receiving request is successful or not. The transfer done is notified by + * the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue on the application level. + * The subsequent transfer can begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +extern usb_status_t USB_DeviceRecvRequest(usb_device_handle handle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The transfer is cancelled. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceCancel(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Initializes a specified endpoint. + * + * The function is used to initialize a specified endpoint. The corresponding endpoint callback is also initialized. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] epInit Endpoint initialization structure. See the structure usb_device_endpoint_init_struct_t. + * @param[in] epCallback Endpoint callback structure. See the structure + * usb_device_endpoint_callback_struct_t. + * + * @retval kStatus_USB_Success The endpoint is initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The epInit or epCallback is NULL pointer. Or the endpoint number is + * more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceInitEndpoint(usb_device_handle handle, + usb_device_endpoint_init_struct_t *epInit, + usb_device_endpoint_callback_struct_t *epCallback); + +/*! + * @brief Deinitializes a specified endpoint. + * + * The function is used to deinitializes a specified endpoint. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is de-initialized successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_Busy The endpoint is busy in EHCI driver. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceDeinitEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Stalls a specified endpoint. + * + * The function is used to stall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceStallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to unstall a specified endpoint. + * + * @param[in] handle The device handle received from #USB_DeviceInit. + * @param[in] endpointAddress Endpoint address, bit7 is the direction of endpoint, 1U - IN, and 0U - OUT. + * + * @retval kStatus_USB_Success The endpoint is un-stalled successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The endpoint number is more than USB_DEVICE_CONFIG_ENDPOINTS. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + */ +extern usb_status_t USB_DeviceUnstallEndpoint(usb_device_handle handle, uint8_t endpointAddress); + +/*! + * @brief Gets the status of the selected item. + * + * The function is used to get the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[out] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Get status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_InvalidParameter The parameter is NULL pointer. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type. + */ +extern usb_status_t USB_DeviceGetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +/*! + * @brief Sets the status of the selected item. + * + * The function is used to set the status of the selected item. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] type The selected item. See the structure #usb_device_status_t. + * @param[in] param The parameter type is determined by the selected item. + * + * @retval kStatus_USB_Success Set status successfully. + * @retval kStatus_USB_InvalidHandle The handle is a NULL pointer. Or the controller handle is invalid. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_Error Unsupported type or the parameter is NULL pointer. + */ +extern usb_status_t USB_DeviceSetStatus(usb_device_handle handle, usb_device_status_t type, void *param); + +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) +/*! + * @brief Enable the device dcd module. + * + * The function enable the device dcd module. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The device could run. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer. Or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceDcdEnable(usb_device_handle handle); + +/*! + * @brief Disable the device dcd module. + * + * The function disable the device dcd module. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * + * @retval kStatus_USB_Success The dcd is reset and stopped. + * @retval kStatus_USB_ControllerNotFound Cannot find the controller. + * @retval kStatus_USB_InvalidHandle The device handle is a NULL pointer or the controller handle is invalid. + * + */ +extern usb_status_t USB_DeviceDcdDisable(usb_device_handle handle); +#endif + +#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) +/*! + * @brief Device task function. + * + * The function is used to handle the controller message. + * This function should not be called in the application directly. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceTaskFunction(void *deviceHandle); +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) +/*! + * @brief Device KHCI task function. + * + * The function is used to handle the KHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceKhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) +/*! + * @brief Device EHCI task function. + * + * The function is used to handle the EHCI controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceEhciTaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/*! + * @brief Device ehci DCD ISR function. + * + * The function is the ehci DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceEhciIsrHSDCDFunction(void *deviceHandle); +#endif +#endif +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#if ((defined(USB_DEVICE_CONFIG_USE_TASK)) && (USB_DEVICE_CONFIG_USE_TASK > 0U)) +/*! + * @brief Device LPC ip3511 controller task function. + * + * The function is used to handle the LPC ip3511 controller message. + * In the bare metal environment, this function should be called periodically in the main function. + * In the RTOS environment, this function should be used as a function entry to create a task. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +#define USB_DeviceLpcIp3511TaskFunction(deviceHandle) USB_DeviceTaskFunction(deviceHandle) +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/*! + * @brief Device IP3511 DCD ISR function. + * + * The function is the IP3511 DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceLpcIp3511IsrDCDFunction(void *deviceHandle); +#endif +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_KHCI)) && (USB_DEVICE_CONFIG_KHCI > 0U)) +/*! + * @brief Device KHCI ISR function. + * + * The function is the KHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceKhciIsrFunction(void *deviceHandle); +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) +#if (defined(FSL_FEATURE_SOC_USBDCD_COUNT) && (FSL_FEATURE_SOC_USBDCD_COUNT > 0U)) +#if 0U /* it is not implemented yet */ +/*! + * @brief Device KHCI DCD ISR function. + * + * The function is the KHCI DCD interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDcdIsrFunction(void *deviceHandle); +#endif +#endif +#endif +#endif + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) +/*! + * @brief Device EHCI ISR function. + * + * The function is the EHCI interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceEhciIsrFunction(void *deviceHandle); +#endif + +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +/*! + * @brief Device LPC USB ISR function. + * + * The function is the LPC USB interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle); +#endif + +#if (((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_DWC3)) && (USB_DEVICE_CONFIG_DWC3 > 0U))) +/*! + * @brief Device USB DWC3 ISR function. + * + * The function is the USB interrupt service routine. + * + * @param[in] deviceHandle The device handle got from #USB_DeviceInit. + */ +extern void USB_DeviceDwc3IsrFunction(void *deviceHandle); +#endif + +/*! + * @brief Gets the device stack version function. + * + * The function is used to get the device stack version. + * + * @param[out] version The version structure pointer to keep the device stack version. + * + */ +extern void USB_DeviceGetVersion(uint32_t *version); + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) || \ + (((defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)))) +/*! + * @brief Update the hardware tick. + * + * The function is used to update the hardware tick. + * + * @param[in] handle The device handle got from #USB_DeviceInit. + * @param[in] tick Current hardware tick(uint is ms). + * + */ +extern usb_status_t USB_DeviceUpdateHwTick(usb_device_handle handle, uint64_t tick); +#endif + +/*! @}*/ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @}*/ + +#endif /* __USB_DEVICE_H__ */ diff --git a/zephyr/middleware/usb/device/usb_device_dci.h b/zephyr/middleware/usb/device/usb_device_dci.h new file mode 100644 index 000000000..08880b516 --- /dev/null +++ b/zephyr/middleware/usb/device/usb_device_dci.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_DEVICE_DCI_H__ +#define __USB_DEVICE_DCI_H__ + +/*! + * @addtogroup usb_device_controller_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Macro to define controller handle */ +#define usb_device_controller_handle usb_device_handle +#define USB_DEVICE_MESSAGES_SIZE \ + (sizeof(uint32_t) * (1U + (sizeof(usb_device_callback_message_struct_t) - 1U) / sizeof(uint32_t))) +/*! @brief Available notify types for device notification */ +typedef enum _usb_device_notification +{ + kUSB_DeviceNotifyBusReset = 0x10U, /*!< Reset signal detected */ + kUSB_DeviceNotifySuspend, /*!< Suspend signal detected */ + kUSB_DeviceNotifyResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyLPMSleep, /*!< LPM signal detected */ + kUSB_DeviceNotifyLPMResume, /*!< Resume signal detected */ + kUSB_DeviceNotifyError, /*!< Errors happened in bus */ + kUSB_DeviceNotifyDetach, /*!< Device disconnected from a host */ + kUSB_DeviceNotifyAttach, /*!< Device connected to a host */ +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + kUSB_DeviceNotifyDcdDetectFinished, /*!< Device charger detection finished */ +#endif +} usb_device_notification_t; + +/*! @brief Device notification message structure */ +typedef struct _usb_device_callback_message_struct +{ + uint8_t *buffer; /*!< Transferred buffer */ + uint32_t length; /*!< Transferred data length */ + uint8_t code; /*!< Notification code */ + uint8_t isSetup; /*!< Is in a setup phase */ +} usb_device_callback_message_struct_t; + +/*! @brief Control type for controller */ +typedef enum _usb_device_control_type +{ + kUSB_DeviceControlRun = 0U, /*!< Enable the device functionality */ + kUSB_DeviceControlStop, /*!< Disable the device functionality */ + kUSB_DeviceControlEndpointInit, /*!< Initialize a specified endpoint */ + kUSB_DeviceControlEndpointDeinit, /*!< De-initialize a specified endpoint */ + kUSB_DeviceControlEndpointStall, /*!< Stall a specified endpoint */ + kUSB_DeviceControlEndpointUnstall, /*!< Un-stall a specified endpoint */ + kUSB_DeviceControlGetDeviceStatus, /*!< Get device status */ + kUSB_DeviceControlGetEndpointStatus, /*!< Get endpoint status */ + kUSB_DeviceControlSetDeviceAddress, /*!< Set device address */ + kUSB_DeviceControlGetSynchFrame, /*!< Get current frame */ + kUSB_DeviceControlResume, /*!< Drive controller to generate a resume signal in USB bus */ + kUSB_DeviceControlSleepResume, /*!< Drive controller to generate a LPM resume signal in USB bus */ + kUSB_DeviceControlSuspend, /*!< Drive controller to enter into suspend mode */ + kUSB_DeviceControlSleep, /*!< Drive controller to enter into sleep mode */ + kUSB_DeviceControlSetDefaultStatus, /*!< Set controller to default status */ + kUSB_DeviceControlGetSpeed, /*!< Get current speed */ + kUSB_DeviceControlGetOtgStatus, /*!< Get OTG status */ + kUSB_DeviceControlSetOtgStatus, /*!< Set OTG status */ + kUSB_DeviceControlSetTestMode, /*!< Drive xCHI into test mode */ + kUSB_DeviceControlGetRemoteWakeUp, /*!< Get flag of LPM Remote Wake-up Enabled by USB host. */ +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + kUSB_DeviceControlDcdDisable, /*!< disable dcd module function. */ + kUSB_DeviceControlDcdEnable, /*!< enable dcd module function. */ +#endif + kUSB_DeviceControlPreSetDeviceAddress, /*!< Pre set device address */ + kUSB_DeviceControlUpdateHwTick, /*!< update hardware tick */ +#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U) + kUSB_DeviceControlGetCurrentFrameCount, /*!< Get current frame count */ +#endif +} usb_device_control_type_t; + +/*! @brief USB device controller initialization function typedef */ +typedef usb_status_t (*usb_device_controller_init_t)(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *controllerHandle); + +/*! @brief USB device controller de-initialization function typedef */ +typedef usb_status_t (*usb_device_controller_deinit_t)(usb_device_controller_handle controllerHandle); + +/*! @brief USB device controller send data function typedef */ +typedef usb_status_t (*usb_device_controller_send_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller receive data function typedef */ +typedef usb_status_t (*usb_device_controller_recv_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! @brief USB device controller cancel transfer function in a specified endpoint typedef */ +typedef usb_status_t (*usb_device_controller_cancel_t)(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress); + +/*! @brief USB device controller control function typedef */ +typedef usb_status_t (*usb_device_controller_control_t)(usb_device_controller_handle controllerHandle, + usb_device_control_type_t command, + void *param); + +/*! @brief USB device controller interface structure */ +typedef struct _usb_device_controller_interface_struct +{ + usb_device_controller_init_t deviceInit; /*!< Controller initialization */ + usb_device_controller_deinit_t deviceDeinit; /*!< Controller de-initialization */ + usb_device_controller_send_t deviceSend; /*!< Controller send data */ + usb_device_controller_recv_t deviceRecv; /*!< Controller receive data */ + usb_device_controller_cancel_t deviceCancel; /*!< Controller cancel transfer */ + usb_device_controller_control_t deviceControl; /*!< Controller control */ +} usb_device_controller_interface_struct_t; + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief Notify the device that the controller status changed. + * + * This function is used to notify the device that the controller status changed. + * + * @param handle The device handle. It equals the value returned from USB_DeviceInit. + * @param message The device callback message handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceNotificationTrigger(void *handle, void *msg); +/*! @}*/ + +#endif /* __USB_DEVICE_DCI_H__ */ diff --git a/zephyr/middleware/usb/device/usb_device_ehci.c b/zephyr/middleware/usb/device/usb_device_ehci.c new file mode 100644 index 000000000..823abc6a3 --- /dev/null +++ b/zephyr/middleware/usb/device/usb_device_ehci.c @@ -0,0 +1,1974 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017,2019 - 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#define DT_DRV_COMPAT nxp_mcux_usbd + +#include "usb_dc_mcux.h" + +#if ((defined(USB_DEVICE_CONFIG_EHCI)) && (USB_DEVICE_CONFIG_EHCI > 0U)) + +#include "usb_device_ehci.h" +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#include "usb_phy.h" +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +#include "usb_hsdcd.h" +#elif (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) +#include "usb_phydcd.h" +#endif +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(USB_STACK_USE_DEDICATED_RAM) && (USB_STACK_USE_DEDICATED_RAM > 0U) + +#error The SOC does not suppoort dedicated RAM case. + +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState); +static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, + usb_device_endpoint_init_struct_t *epInit); +static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep); +static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpoint, + uint8_t direction); +static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState); +static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState); +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState); +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Apply for QH buffer, 2048-byte alignment */ +USB_RAM_ADDRESS_ALIGNMENT(2048) +USB_CONTROLLER_DATA static uint8_t qh_buffer[(USB_DEVICE_CONFIG_EHCI - 1) * 2048 + + 2 * USB_DEVICE_CONFIG_ENDPOINTS * 2 * sizeof(usb_device_ehci_qh_struct_t)]; + +/* Apply for DTD buffer, 32-byte alignment */ +USB_RAM_ADDRESS_ALIGNMENT(32) +USB_CONTROLLER_DATA static usb_device_ehci_dtd_struct_t s_UsbDeviceEhciDtd[USB_DEVICE_CONFIG_EHCI] + [USB_DEVICE_CONFIG_EHCI_MAX_DTD]; + +/* Apply for ehci device state structure */ +static usb_device_ehci_state_struct_t g_UsbDeviceEhciState[USB_DEVICE_CONFIG_EHCI]; + +/* Apply for whether the corresponding g_UsbDeviceEhciState is used or not, if used, it is set to 1, if not used, it is + * set to 0 */ +static uint8_t g_UsbDeviceEhciStateStatus[USB_DEVICE_CONFIG_EHCI]= {0}; + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * @brief EHCI get USB base address. + * + * This function is used to get USB base address according to EHCI controller ID. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * @param[in] baseArray USB base address array. + * @param[in] baseCount The number of elements of baseArray. + * + * @retval USB base address. + */ +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U))) || \ + ((defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) +static void *USB_EhciGetBase(uint8_t controllerId, uint32_t *baseArray, uint8_t baseCount) +{ + uint8_t instance; + + if (controllerId < (uint8_t)kUSB_ControllerEhci0) + { + return NULL; + } + + controllerId = controllerId - (uint8_t)kUSB_ControllerEhci0; + + for (instance = 0; instance < baseCount; instance++) + { + if (0U == baseArray[instance]) + { + controllerId++; + } + else + { + break; + } + } + if (controllerId >= baseCount) + { + return NULL; + } + + return (void *)(uint8_t *)baseArray[controllerId]; +} +#endif + +/*! + * @brief Set device controller state to default state. + * + * The function is used to set device controller state to default state. + * The function will be called when USB_DeviceEhciInit called or the control type kUSB_DeviceControlGetEndpointStatus + * received in USB_DeviceEhciControl. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciSetDefaultState(usb_device_ehci_state_struct_t *ehciState) +{ + usb_device_ehci_dtd_struct_t *p; + + /* Initialize the dtd free queue */ + ehciState->dtdFree = ehciState->dtd; + p = ehciState->dtdFree; + for (uint32_t i = 1U; i < USB_DEVICE_CONFIG_EHCI_MAX_DTD; i++) + { + p->nextDtdPointer = (uint32_t)&ehciState->dtd[i]; + p = (usb_device_ehci_dtd_struct_t *)p->nextDtdPointer; + } + p->nextDtdPointer = 0U; + ehciState->dtdCount = USB_DEVICE_CONFIG_EHCI_MAX_DTD; + + /* Not use interrupt threshold. */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ITC_MASK; + ehciState->registerBase->USBCMD |= USBHS_USBCMD_ITC(0U); + + /* Disable setup lockout, please refer to "Control Endpoint Operation" section in RM. */ + ehciState->registerBase->USBMODE |= USBHS_USBMODE_SLOM_MASK; + +/* Set the endian by using CPU's endian */ +#if defined(CONFIG_BIG_ENDIAN) + ehciState->registerBase->USBMODE |= USBHS_USBMODE_ES_MASK; +#else + ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_ES_MASK; +#endif + /* Initialize the QHs of endpoint. */ + for (uint32_t i = 0U; i < (USB_DEVICE_CONFIG_ENDPOINTS * 2U); i++) + { + ehciState->qh[i].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[i].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = + USB_CONTROL_MAX_PACKET_SIZE; + ehciState->dtdHard[i] = NULL; + ehciState->dtdTail[i] = NULL; + ehciState->qh[i].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; + } + + /* Add QH buffer address to USBHS_EPLISTADDR_REG */ + ehciState->registerBase->EPLISTADDR = (uint32_t)ehciState->qh; + + /* Clear device address */ + ehciState->registerBase->DEVICEADDR = 0U; + +#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) + ehciState->registerBase->OTGSC = ehciState->registerBase->OTGSC & 0x0000FFFFU; + ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIE_MASK; +#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ + + /* Enable USB Interrupt, USB Error Interrupt, Port Change detect Interrupt, USB-Reset Interrupt*/ + ehciState->registerBase->USBINTR = + (USBHS_USBINTR_UE_MASK | USBHS_USBINTR_UEE_MASK | USBHS_USBINTR_PCE_MASK | USBHS_USBINTR_URE_MASK +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + | USBHS_USBINTR_SLE_MASK +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + ); + + /* Clear reset flag */ + ehciState->isResetting = 0U; +} + +/*! + * @brief Initialize a specified endpoint. + * + * The function is used to initialize a specified endpoint. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param epInit The endpoint initialization structure pointer. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointInit(usb_device_ehci_state_struct_t *ehciState, + usb_device_endpoint_init_struct_t *epInit) +{ + uint32_t primeBit = 1UL << ((epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK) + + ((epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint16_t maxPacketSize = epInit->maxPacketSize & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK; + uint8_t endpoint = (epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK); + uint8_t direction = (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + uint8_t transferType = epInit->transferType & USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK; + + /* Cancel pending transfer of the endpoint */ + (void)USB_DeviceEhciCancel(ehciState, epInit->endpointAddress); + + if ((0U != (ehciState->registerBase->EPPRIME & primeBit)) || (0U != (ehciState->registerBase->EPSR & primeBit))) + { + return kStatus_USB_Busy; + } + + /* Make the endpoint max packet size align with USB Specification 2.0. */ + if (USB_ENDPOINT_ISOCHRONOUS == transferType) + { + if (maxPacketSize > USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE) + { + maxPacketSize = USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE; + } + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = + 1UL + ((((uint32_t)epInit->maxPacketSize) & USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK) >> + USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT); + } + else + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.mult = 0U; + } + + /* Save the max packet size of the endpoint */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize = + maxPacketSize; + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.zlt = epInit->zlt; + if ((USB_CONTROL_ENDPOINT == endpoint)) + { + /* Set ZLT bit. disable control endpoint automatic zlt by default,only send zlt when it is needed*/ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt = 1U; + } + else + { + /* Set ZLT bit. */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt = + ((0U == epInit->zlt) ? 1U : 0U); + } + + /* Enable the endpoint. */ + if ((USB_CONTROL_ENDPOINT == endpoint)) + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 1U; + ehciState->registerBase->EPCR0 |= + ((0U != direction) ? + (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); + } + else + { + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.ios = 0U; + ehciState->registerBase->EPCR[endpoint - 1U] |= + ((0U != direction)? + (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXR_MASK | ((uint32_t)transferType << USBHS_EPCR_TXT_SHIFT)) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXR_MASK | ((uint32_t)transferType << USBHS_EPCR_RXT_SHIFT))); + } + + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 1U; + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize a specified endpoint. + * + * The function is used to de-initialize a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be disabled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointDeinit(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint32_t primeBit = + 1UL << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t endpoint = (ep & USB_ENDPOINT_NUMBER_MASK); + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + uint8_t index = ((uint8_t)((uint32_t)endpoint << 1U)) | direction; + + ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened = 0U; + + /* Cancel the transfer of the endpoint */ + (void)USB_DeviceEhciCancel(ehciState, ep); + if ((0U != (ehciState->registerBase->EPPRIME & primeBit)) || (0U != (ehciState->registerBase->EPSR & primeBit))) + { + return kStatus_USB_Busy; + } + + /* Clear endpoint state */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristics = 0U; + /* Disable the endpoint */ + if (0U == endpoint) + { + ehciState->registerBase->EPCR0 &= + ~((0U != direction) ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK | USBHS_EPCR_TXS_MASK) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK | USBHS_EPCR_RXS_MASK)); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] &= + ~((0U != direction) ? (USBHS_EPCR_TXE_MASK | USBHS_EPCR_TXT_MASK | USBHS_EPCR_TXS_MASK) : + (USBHS_EPCR_RXE_MASK | USBHS_EPCR_RXT_MASK | USBHS_EPCR_RXS_MASK)); + } + + return kStatus_USB_Success; +} + +/*! + * @brief Stall a specified endpoint. + * + * The function is used to stall a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be stalled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointStall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + if (0U == endpoint) + { + /* Cancel the transfer of the endpoint */ + (void)USB_DeviceEhciCancel(ehciState, 0x00); + (void)USB_DeviceEhciCancel(ehciState, 0x80); + ehciState->registerBase->EPCR0 |= (USBHS_EPCR_TXS_MASK | USBHS_EPCR_RXS_MASK); + } + else + { + /* Cancel the transfer of the endpoint */ + (void)USB_DeviceEhciCancel(ehciState, ep); + + ehciState->registerBase->EPCR[endpoint - 1U] |= ((0U != direction) ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + + return kStatus_USB_Success; +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * Current transfer of the endpoint will be cancelled and the specified endpoint will be un-stalled. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciEndpointUnstall(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t endpoint = ep & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + (ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + /* Clear the endpoint stall state */ + if (0U == endpoint) + { + ehciState->registerBase->EPCR0 &= ~((0U != direction) ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + } + else + { + ehciState->registerBase->EPCR[endpoint - 1U] &= + ~((0U != direction) ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK); + ehciState->registerBase->EPCR[endpoint - 1U] |= ((0U != direction) ? USBHS_EPCR_TXR_MASK : USBHS_EPCR_RXR_MASK); + } + /* Cancel the transfer of the endpoint */ + (void)USB_DeviceEhciCancel(ehciState, ep); + + return kStatus_USB_Success; +} + +/*! + * @brief Get setup packet data. + * + * The function is used to get setup packet data and copy to a backup buffer. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param ep The endpoint number. + * + */ +static void USB_DeviceEhciFillSetupBuffer(usb_device_ehci_state_struct_t *ehciState, uint8_t ep) +{ + uint8_t waitingSafelyAccess = 1U; + uint8_t index = (ep * 2U) | USB_OUT; + + /* Write 1U to clear corresponding bit in EPSETUPSR. */ + ehciState->registerBase->EPSETUPSR = 1UL << ep; + + while (0U != waitingSafelyAccess) + { + /* Set the setup tripwire bit. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_SUTW_MASK; + + /* Copy setup packet data to backup buffer */ + ehciState->qh[index].setupBufferBack[0] = ehciState->qh[index].setupBuffer[0]; + ehciState->qh[index].setupBufferBack[1] = ehciState->qh[index].setupBuffer[1]; + + /* Read the USBCMD[SUTW] bit. If set, jump out from the while loop; if cleared continue */ + if (0U != (ehciState->registerBase->USBCMD & USBHS_USBCMD_SUTW_MASK)) + { + waitingSafelyAccess = 0U; + } + } + /* Clear the setup tripwire bit */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_SUTW_MASK; +} + +/*! + * @brief Cancel the transfer of the control pipe. + * + * The function is used to cancel the transfer of the control pipe. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param endpoint The endpoint number. + * @param direction The direction of the endpoint. + * + */ +static void USB_DeviceEhciCancelControlPipe(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpoint, + uint8_t direction) +{ + usb_device_ehci_dtd_struct_t *currentDtd; + uint32_t index = ((uint32_t)endpoint << 1U) + (uint32_t)direction; + usb_device_callback_message_struct_t message; + + message.buffer = NULL; + message.length = 0U; + /* Get the dtd of the control pipe */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (NULL != currentDtd) + { + /* Pass the transfer buffer address */ + if (NULL == message.buffer) + { + uint32_t bufferAddress = currentDtd->bufferPointerPage[0]; + message.buffer = (uint8_t *)((bufferAddress & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + /* If the dtd is active, set the message length to USB_CANCELLED_TRANSFER_LENGTH. Or set the length by using + * finished length. */ + if (0U != (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) + { + message.length = USB_CANCELLED_TRANSFER_LENGTH; + } + else + { + message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - + currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); + } + + /* Move the dtd head pointer to next. */ + /* If the pointer of the head equals to the tail, set the dtd queue to null. */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + else + { + ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((0U != currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0U == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); + message.isSetup = 0U; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + message.length = 0U; + } + + /* Clear the token field of the dtd. */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + /* Add the dtd to the free dtd queue. */ + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + + /* Get the next in-used dtd. */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } +} + +/*! + * @brief Handle the endpoint token done interrupt. + * + * The function is used to handle the endpoint token done interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptTokenDone(usb_device_ehci_state_struct_t *ehciState) +{ + uint32_t status; + uint32_t primeBit; + usb_device_ehci_dtd_struct_t *currentDtd; + void *temp; + usb_device_callback_message_struct_t message; + uint8_t endpoint; + uint8_t direction; + uint8_t count; + uint8_t index; + + /* Get the EPSETUPSR to check the setup packect received in which one endpoint. */ + status = ehciState->registerBase->EPSETUPSR; + + if (0U != status) + { + for (endpoint = 0U; endpoint < USB_DEVICE_CONFIG_ENDPOINTS; endpoint++) + { + /* Check the endpoint receive the setup packet. */ + if (0U != (status & (1UL << endpoint))) + { + /* Get last setup packet */ + temp = (void *)&ehciState->qh[(uint8_t)((uint32_t)endpoint << 1U) + USB_OUT].setupBufferBack; + usb_setup_struct_t *deviceSetup = (usb_setup_struct_t *)temp; + + /* Check the direction of the data phase. */ + direction = (deviceSetup->bmRequestType & USB_REQUEST_TYPE_DIR_IN) >> USB_REQUEST_TYPE_DIR_SHIFT; + /* Cancel the data phase transfer */ + USB_DeviceEhciCancelControlPipe(ehciState, endpoint, direction); + /* Cancel the status phase transfer */ + USB_DeviceEhciCancelControlPipe(ehciState, endpoint, 1U ^ direction); + message.code = (endpoint) | (USB_OUT << 0x07U); + message.buffer = (uint8_t *)deviceSetup; + message.length = USB_SETUP_PACKET_SIZE; + message.isSetup = 1U; + /* Fill the setup packet to the backup buffer */ + USB_DeviceEhciFillSetupBuffer(ehciState, endpoint); + /* Notify the up layer the EHCI status changed. */ + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } + } + /* Read the USBHS_EPCOMPLETE_REG to get the endpoint transfer done status */ + status = ehciState->registerBase->EPCOMPLETE; + /* Clear the endpoint transfer done status */ + ehciState->registerBase->EPCOMPLETE = status; + + if (0U != status) + { + for (count = 0U; count < 32U; count++) + { + /* Check the transfer is done or not in the specified endpoint. */ + if (0U != (status & (1UL << count))) + { + if (count > 15U) + { + endpoint = count - 16U; + direction = USB_IN; + } + else + { + endpoint = count; + direction = USB_OUT; + } + if (endpoint >= USB_DEVICE_CONFIG_ENDPOINTS) + { + continue; + } + index = (endpoint << 1U) + direction; + message.buffer = NULL; + message.length = 0U; + if ((USB_CONTROL_ENDPOINT == endpoint) && (USB_IN == direction)) + { + if (1U == ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.zlt) + { + if (0U == + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt) + { + /*disable zlt after send zlt*/ + ehciState->qh[index] + .capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt = 1U; + } + } + } + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (NULL != currentDtd) + { + uint8_t isTokenDone = 0; + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + + while (NULL != currentDtd) + { + /* Don't handle the active dtd. */ + if ((0U != + (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) || + (0U != currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) + { + if ((0U == (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & + USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) && + (0U != currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc)) + { + isTokenDone = 1U; + } + break; + } + currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + + if ((0U == isTokenDone) && (NULL != currentDtd)) + { + break; + } + + /* Get the in-used dtd of the specified endpoint. */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (NULL != currentDtd) + { + /* Don't handle the active dtd. */ + if (0U != (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) + { + break; + } + + /* Save the transfer buffer address */ + if (NULL == message.buffer) + { + message.buffer = + (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + /* Save the transferred data length */ + message.length += (currentDtd->reservedUnion.originalBufferInfo.originalBufferLength - + currentDtd->dtdTokenUnion.dtdTokenBitmap.totalBytes); + + /* Move the dtd queue head pointer to next */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + else + { + ehciState->dtdHard[index] = + (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((0U != currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0U == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + message.code = endpoint | (uint8_t)((uint32_t)direction << 0x07U); + message.isSetup = 0U; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + message.length = 0U; + } + /* Clear the token field of the dtd */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + /* Get the next in-used dtd */ + currentDtd = (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & + USB_DEVICE_ECHI_DTD_POINTER_MASK); + + if ((NULL != currentDtd) && (0U != (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & + USB_DEVICE_ECHI_DTD_STATUS_ACTIVE))) + { + primeBit = 1UL << (endpoint + 16U * direction); + + /* Try to prime the next dtd. */ + ehciState->registerBase->EPPRIME = primeBit; + + /* Whether the endpoint transmit/receive buffer is ready or not. If not, wait for prime bit + * cleared and prime the next dtd. */ + if (0U == (ehciState->registerBase->EPSR & primeBit)) + { + /* Wait for the endpoint prime bit cleared by HW */ + while (0U != (ehciState->registerBase->EPPRIME & primeBit)) + { + } + + /* If the endpoint transmit/receive buffer is not ready */ + if (0U == (ehciState->registerBase->EPSR & primeBit)) + { + /* Prime next dtd and prime the transfer */ + ehciState->qh[index].nextDtdPointer = (uint32_t)currentDtd; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + ehciState->registerBase->EPPRIME = primeBit; + } + } + } + } + } + } + } + } +} + +/*! + * @brief Handle the port status change interrupt. + * + * The function is used to handle the port status change interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptPortChange(usb_device_ehci_state_struct_t *ehciState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + + /* Whether the port is doing reset. */ + if (0U == (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK)) + { + /* If not, update the USB speed. */ + if (0U != (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_HSP_MASK)) + { + ehciState->speed = USB_SPEED_HIGH; + } + else + { + ehciState->speed = USB_SPEED_FULL; + } + + /* If the device reset flag is non-zero, notify the up layer the device reset finished. */ + if (0U != ehciState->isResetting) + { + message.code = (uint8_t)kUSB_DeviceNotifyBusReset; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + ehciState->isResetting = 0U; + } + } + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if ((0U != ehciState->isSuspending) && (0U == (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK))) + { + /* Set the resume flag */ + ehciState->isSuspending = 0U; + + message.code = (uint8_t)kUSB_DeviceNotifyResume; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ +} + +/*! + * @brief Handle the reset interrupt. + * + * The function is used to handle the reset interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptReset(usb_device_ehci_state_struct_t *ehciState) +{ + uint32_t status = 0U; + + /* Clear the setup flag */ + status = ehciState->registerBase->EPSETUPSR; + ehciState->registerBase->EPSETUPSR = status; + /* Clear the endpoint complete flag */ + status = ehciState->registerBase->EPCOMPLETE; + ehciState->registerBase->EPCOMPLETE = status; + + do + { + /* Flush the pending transfers */ + ehciState->registerBase->EPFLUSH = USBHS_EPFLUSH_FERB_MASK | USBHS_EPFLUSH_FETB_MASK; + } while (0U != (ehciState->registerBase->EPPRIME & (USBHS_EPPRIME_PERB_MASK | USBHS_EPPRIME_PETB_MASK))); + + /* Whether is the port reset. If yes, set the isResetting flag. Or, notify the up layer. */ + if (0U != (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_PR_MASK)) + { + ehciState->isResetting = 1U; + } + else + { + usb_device_callback_message_struct_t message; + message.buffer = (uint8_t *)NULL; + message.code = (uint8_t)kUSB_DeviceNotifyBusReset; + message.length = 0U; + message.isSetup = 0U; + + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } +} + +/*! + * @brief Handle the sof interrupt. + * + * The function is used to handle the sof interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptSof(usb_device_ehci_state_struct_t *ehciState) +{ +} + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief Handle the suspend interrupt. + * + * The function is used to handle the suspend interrupt. + * + * @param ehciState Pointer of the device EHCI state structure. + * + */ +static void USB_DeviceEhciInterruptSuspend(usb_device_ehci_state_struct_t *ehciState) +{ + /* If the port is in suspend state, notify the up layer */ + if (0U != (ehciState->registerBase->PORTSC1 & USBHS_PORTSC1_SUSP_MASK)) + { +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +#else + if (0U != (ehciState->registerPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)) +#endif + { + usb_device_callback_message_struct_t message; + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + message.code = (uint8_t)kUSB_DeviceNotifySuspend; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } +} +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + +/*! + * @brief Get dtds and link to QH. + * + * The function is used to get dtds and link to QH. + * + * @param ehciState Pointer of the device EHCI state structure. + * @param endpointAddress The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * @param buffer The memory address needed to be transferred. + * @param length Data length. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceEhciTransfer(usb_device_ehci_state_struct_t *ehciState, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + usb_device_ehci_dtd_struct_t *dtd; + usb_device_ehci_dtd_struct_t *dtdHard; + uint32_t index = (((uint32_t)endpointAddress & USB_ENDPOINT_NUMBER_MASK) << 1U) | + (((uint32_t)endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT); + uint32_t primeBit = 1UL << ((endpointAddress & USB_ENDPOINT_NUMBER_MASK) + + ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint32_t epStatus = primeBit; + uint32_t sendLength; + uint32_t currentIndex = 0U; + uint32_t dtdRequestCount = (length + USB_DEVICE_ECHI_DTD_TOTAL_BYTES - 1U) / USB_DEVICE_ECHI_DTD_TOTAL_BYTES; + uint8_t qhIdle = 0U; + uint8_t waitingSafelyAccess = 1U; + uint32_t primeTimesCount = 0U; + OSA_SR_ALLOC(); + + if (NULL == ehciState) + { + return kStatus_USB_InvalidHandle; + } + + if (0U == ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.isOpened) + { + return kStatus_USB_Error; + } + /* Return error when ehci is doing reset */ + if (0U != ehciState->isResetting) + { + return kStatus_USB_Error; + } + + if (0U == dtdRequestCount) + { + dtdRequestCount = 1U; + } + + OSA_ENTER_CRITICAL(); + /* The free dtd count need to not less than the transfer requests. */ + if (dtdRequestCount > (uint32_t)ehciState->dtdCount) + { + OSA_EXIT_CRITICAL(); + return kStatus_USB_Busy; + } + + do + { + /* The transfer length need to not more than USB_DEVICE_ECHI_DTD_TOTAL_BYTES for each dtd. */ + if (length > USB_DEVICE_ECHI_DTD_TOTAL_BYTES) + { + sendLength = USB_DEVICE_ECHI_DTD_TOTAL_BYTES; + } + else + { + sendLength = length; + } + length -= sendLength; + + /* Get a free dtd */ + dtd = ehciState->dtdFree; + + ehciState->dtdFree = (usb_device_ehci_dtd_struct_t *)dtd->nextDtdPointer; + ehciState->dtdCount--; + + /* Save the dtd head when current active buffer offset is zero. */ + if (0U == currentIndex) + { + dtdHard = dtd; + } + + /* Set the dtd field */ + dtd->nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + dtd->dtdTokenUnion.dtdToken = 0U; + dtd->bufferPointerPage[0] = (uint32_t)(buffer + currentIndex); + dtd->bufferPointerPage[1] = + (dtd->bufferPointerPage[0] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK) & USB_DEVICE_ECHI_DTD_PAGE_MASK; + dtd->bufferPointerPage[2] = dtd->bufferPointerPage[1] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + dtd->bufferPointerPage[3] = dtd->bufferPointerPage[2] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + dtd->bufferPointerPage[4] = dtd->bufferPointerPage[3] + USB_DEVICE_ECHI_DTD_PAGE_BLOCK; + + dtd->dtdTokenUnion.dtdTokenBitmap.totalBytes = sendLength; + + /* Save the data length needed to be transferred. */ + dtd->reservedUnion.originalBufferInfo.originalBufferLength = sendLength; + /* Save the original buffer address */ + dtd->reservedUnion.originalBufferInfo.originalBufferOffest = + dtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK; + dtd->reservedUnion.originalBufferInfo.dtdInvalid = 0U; + + /* Set the IOC field in last dtd. */ + if (0U == length) + { + dtd->dtdTokenUnion.dtdTokenBitmap.ioc = 1U; + } + + /* Set dtd active */ + dtd->dtdTokenUnion.dtdTokenBitmap.status = USB_DEVICE_ECHI_DTD_STATUS_ACTIVE; + + /* Move the buffer offset index */ + currentIndex += sendLength; + + /* Add dtd to the in-used dtd queue */ + if (NULL != (ehciState->dtdTail[index])) + { + ehciState->dtdTail[index]->nextDtdPointer = (uint32_t)dtd; + ehciState->dtdTail[index] = dtd; + } + else + { + ehciState->dtdHard[index] = dtd; + ehciState->dtdTail[index] = dtd; + qhIdle = 1U; + } + } while (0U != length); +#if (defined USB_DEVICE_CONTROLLER_AUTO_CONTROL_TRANSFER_ZLP) && (USB_DEVICE_CONTROLLER_AUTO_CONTROL_TRANSFER_ZLP) + if ((USB_CONTROL_ENDPOINT == (endpointAddress & USB_ENDPOINT_NUMBER_MASK)) && + (USB_IN == ((endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT))) + { + uint8_t setupindex = ((endpointAddress & USB_ENDPOINT_NUMBER_MASK)* 2U); + /* Get last setup packet */ + temp = (void *)&ehciState->qh[setupindex].setupBufferBack[0]; + usb_setup_struct_t *deviceSetup = (usb_setup_struct_t *)temp; + if (1U == ehciState->qh[index].endpointStatusUnion.endpointStatusBitmap.zlt) + { + if ((0U != sendLength) && (sendLength < deviceSetup->wLength) && + (0U == + (sendLength % ehciState->qh[index] + .capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.maxPacketSize))) + { + /* enable ZLT. */ + ehciState->qh[index].capabilttiesCharacteristicsUnion.capabilttiesCharacteristicsBitmap.zlt = 0U; + } + } + } +#endif + /* If the QH is not empty */ + if (0U == qhIdle) + { + /* If the prime bit is set, nothing need to do. */ + if (0U != (ehciState->registerBase->EPPRIME & primeBit)) + { + OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; + } + + /* To safely a dtd */ + while (0U != waitingSafelyAccess) + { + /* set the ATDTW flag to USBHS_USBCMD_REG. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_ATDTW_MASK; + /* Read EPSR */ + epStatus = ehciState->registerBase->EPSR; + /* Wait the ATDTW bit set */ + if (0U != (ehciState->registerBase->USBCMD & USBHS_USBCMD_ATDTW_MASK)) + { + waitingSafelyAccess = 0U; + } + } + /* Clear the ATDTW bit */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_ATDTW_MASK; + } + + /* If QH is empty or the endpoint is not primed, need to link current dtd head to the QH. */ + /* When the endpoint is not primed if qhIdle is zero, it means the QH is empty. */ + if ((0U != qhIdle) || (0U == (epStatus & primeBit))) + { + ehciState->qh[index].nextDtdPointer = (uint32_t)dtdHard; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + /*make sure dtd is linked to dqh*/ + __DSB(); + ehciState->registerBase->EPPRIME = primeBit; + while (0U == (ehciState->registerBase->EPSR & primeBit)) + { + primeTimesCount++; + if (primeTimesCount == USB_DEVICE_MAX_TRANSFER_PRIME_TIMES) + { + OSA_EXIT_CRITICAL(); + return kStatus_USB_Error; + } + if (0U != (ehciState->registerBase->EPCOMPLETE & primeBit)) + { + break; + } + else + { + ehciState->registerBase->EPPRIME = primeBit; + } + } + } + + OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +/*! + * @brief Get a valid device EHCI state for the device EHCI instance. + * + * This function gets a valid device EHCI state for the USB device EHCI module specified by the controllerId. + * + * @param instanceIndex The instanceIndex is used for other EHCI device structure to identify their instance index. + * + * @return A valid EHCI state or NULL. + */ +static void *USB_EhciGetValidEhciState(uint8_t *instanceIndex) +{ + for (uint8_t instance = 0; instance < USB_DEVICE_CONFIG_EHCI; instance++) + { + if (0U == g_UsbDeviceEhciStateStatus[instance]) + { + g_UsbDeviceEhciStateStatus[instance] = 1U; + *instanceIndex = instance; + return (void *)(&g_UsbDeviceEhciState[instance]); + } + } + return NULL; +} + +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/* The device dcd callback */ +static usb_hsdcd_status_t USB_DeviceEhciIsrHSDCDCallback(void *handle, uint32_t event, void *param) +{ + usb_hsdcd_status_t error = kStatus_hsdcd_Success; + usb_device_callback_message_struct_t message; + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)handle; + + if (ehciState == NULL) + { + return kStatus_hsdcd_Error; + } + + /*messsgae buffer contain event information*/ + message.buffer = (uint8_t *)param; + message.length = 0U; + message.isSetup = 0U; + message.code = (uint8_t)kUSB_DeviceNotifyDcdDetectFinished; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + + return error; +} + +void USB_DeviceEhciIsrHSDCDFunction(void *deviceHandle) +{ + struct usb_device_struct *handle = (struct usb_device_struct *)deviceHandle; + usb_device_ehci_state_struct_t *ehciState; + if (NULL == deviceHandle) + { + return; + } + ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); + USB_HSDcdIsrFunction(ehciState->dcdHandle); +} +#elif (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) +/* The device dcd callback */ +static usb_phydcd_status_t USB_DeviceEhciIsrPHYDCDCallback(void *handle, uint32_t event, void *param) +{ + usb_phydcd_status_t error = kStatus_phydcd_Success; + usb_device_callback_message_struct_t message; + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)handle; + + if (ehciState == NULL) + { + return kStatus_phydcd_Error; + } + + /*messsgae buffer contain event information*/ + message.buffer = (uint8_t *)param; + message.length = 0U; + message.isSetup = 0U; + message.code = (uint8_t)kUSB_DeviceNotifyDcdDetectFinished; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + + return error; +} +#endif + +/*! + * @brief Initialize the USB device EHCI instance. + * + * This function initializes the USB device EHCI module specified by the controllerId. + * + * @param controllerId The controller id of the USB IP. Please refer to enumeration type usb_controller_index_t. + * @param handle Pointer of the device handle, used to identify the device object is belonged to. + * @param ehciHandle It is out parameter, is used to return pointer of the device EHCI handle to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *ehciHandle) +{ + usb_device_ehci_state_struct_t *ehciState = NULL; + uint32_t ehci_base[] = USBHS_BASE_ADDRS; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + uint32_t usbnc_base[] = USBNC_BASE_ADDRS; +#endif +#endif + uint8_t intanceIndex; + void *temp; +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U))) + + usb_device_callback_message_struct_t message; +#endif + +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + uint32_t hsdcd_base[] = USBHSDCD_BASE_ADDRS; + USBHSDCD_Type *base; + usb_hsdcd_config_struct_t dcdParamConfig; + usb_hsdcd_status_t dcdError = kStatus_hsdcd_Success; +#elif (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + ((defined FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) + + uint8_t index; + usb_phydcd_config_struct_t phyDcdParamConfig; + usb_phydcd_status_t phyDcdError = kStatus_phydcd_Success; +#endif + + if ((controllerId < (uint8_t)kUSB_ControllerEhci0) || + ((uint32_t)((uint32_t)controllerId - (uint32_t)kUSB_ControllerEhci0) >= (sizeof(ehci_base) / sizeof(uint32_t)))) + { + return kStatus_USB_ControllerNotFound; + } + + ehciState = USB_EhciGetValidEhciState(&intanceIndex); + if(NULL == ehciState) + { + return kStatus_USB_InvalidHandle; + } + ehciState->dtd = s_UsbDeviceEhciDtd[intanceIndex]; + temp = (void *)&qh_buffer[intanceIndex * 2048U]; + ehciState->qh = (usb_device_ehci_qh_struct_t *)temp; + + ehciState->controllerId = controllerId; + + ehciState->registerBase = (USBHS_Type *)ehci_base[controllerId - (uint8_t)kUSB_ControllerEhci0]; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + ehciState->registerPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerNcBase = + (USBNC_Type *)USB_EhciGetBase(controllerId, &usbnc_base[0], sizeof(usbnc_base) / sizeof(uint32_t)); +#endif + +#endif + /* Reset the controller. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RST_MASK; + while (0U != (ehciState->registerBase->USBCMD & USBHS_USBCMD_RST_MASK)) + { + } + + /* Get the HW's endpoint count */ + ehciState->endpointCount = + (uint8_t)((ehciState->registerBase->DCCPARAMS & USBHS_DCCPARAMS_DEN_MASK) >> USBHS_DCCPARAMS_DEN_SHIFT); + + if (ehciState->endpointCount < USB_DEVICE_CONFIG_ENDPOINTS) + { + return kStatus_USB_Error; + } + ehciState->deviceHandle = (struct usb_device_struct *)handle; + + /* Clear the controller mode field and set to device mode. */ + ehciState->registerBase->USBMODE &= ~USBHS_USBMODE_CM_MASK; + ehciState->registerBase->USBMODE |= USBHS_USBMODE_CM(0x02U); + + /* Set the EHCI to default status. */ + USB_DeviceEhciSetDefaultState(ehciState); + *ehciHandle = (usb_device_controller_handle)ehciState; +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + base = (USBHSDCD_Type *)USB_EhciGetBase(controllerId, &hsdcd_base[0], sizeof(hsdcd_base) / sizeof(uint32_t)); + dcdParamConfig.dcdCallback = USB_DeviceEhciIsrHSDCDCallback; + dcdParamConfig.dcdCallbackParam = (void *)ehciState; + dcdError = USB_HSDCD_Init(base, &dcdParamConfig, &ehciState->dcdHandle); + if (kStatus_hsdcd_Success != dcdError) + { + return kStatus_USB_Error; + } + + if (0U != (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK)) + { + /* Device is connected to a host. */ + message.code = (uint8_t)kUSB_DeviceNotifyAttach; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + (void)USB_HSDCD_Control(ehciState->dcdHandle, kUSB_DeviceHSDcdRun, NULL); + } +#elif (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) + + index = controllerId - (uint8_t)kUSB_ControllerEhci0; + + phyDcdParamConfig.dcdCallback = USB_DeviceEhciIsrPHYDCDCallback; + phyDcdParamConfig.dcdCallbackParam = (void *)ehciState; + + phyDcdError = + USB_PHYDCD_Init(index, (usb_phydcd_config_struct_t *)&phyDcdParamConfig, (void *)&ehciState->dcdHandle); + if(kStatus_phydcd_Success != phyDcdError) + { + return kStatus_USB_Error; + } + + if (0U != (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK)) + { + /* Device is connected to a host. */ + message.code = (uint8_t)kUSB_DeviceNotifyAttach; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + + (void)USB_PHYDCD_Control(ehciState->dcdHandle, kUSB_DevicePHYDcdRun, NULL); + } +#endif +#if DT_INST_NODE_HAS_PROP(0, maximum_speed) + if (!strncmp(DT_INST_PROP(0, maximum_speed), "full-speed", 10)) + { + ehciState->registerBase->PORTSC1 |= USB_PORTSC1_PFSC_MASK; + } +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize the USB device EHCI instance. + * + * This function de-initializes the USB device EHCI module. + * + * @param ehciHandle Pointer of the device EHCI handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + + if (NULL == ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + for (uint8_t instance = 0; instance < USB_DEVICE_CONFIG_EHCI; instance++) + { + if (ehciState == &g_UsbDeviceEhciState[instance]) + { + g_UsbDeviceEhciStateStatus[instance] = 0; + } + } + + /* Disable all interrupt. */ + ehciState->registerBase->USBINTR = 0U; + /* Stop the device functionality. */ + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + /* Reset the controller. */ + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RST_MASK; + +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + (void)USB_HSDCD_Deinit(ehciState->dcdHandle); +#elif (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) + (void)USB_PHYDCD_Deinit(ehciState->dcdHandle); +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief Send data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to hold the data need to be sent. + * @param length The data length need to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the sending request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + /* Add dtd to the QH */ + return USB_DeviceEhciTransfer( + (usb_device_ehci_state_struct_t *)ehciHandle, + (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_IN << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Receive data through a specified endpoint. + * + * This function Receives data through a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param endpointAddress Endpoint index. + * @param buffer The memory address to save the received data. + * @param length The data length want to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + /* Add dtd to the QH */ + return USB_DeviceEhciTransfer( + (usb_device_ehci_state_struct_t *)ehciHandle, + (endpointAddress & USB_ENDPOINT_NUMBER_MASK) | (USB_OUT << USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT), + buffer, length); +} + +/*! + * @brief Cancel the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + usb_device_callback_message_struct_t message; + usb_device_ehci_dtd_struct_t *currentDtd; + uint32_t primeBit = + 1UL << ((ep & USB_ENDPOINT_NUMBER_MASK) + ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x03U)); + uint8_t index = + ((ep & USB_ENDPOINT_NUMBER_MASK) << 1U) | ((ep & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> 0x07U); + uint8_t flag = 0; + + OSA_SR_ALLOC(); + + if (NULL == ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + + OSA_ENTER_CRITICAL(); + + message.buffer = NULL; + message.length = USB_CANCELLED_TRANSFER_LENGTH; + + /* Get the first dtd */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + + /* In the next loop, USB_DeviceNotificationTrigger function may trigger a new transfer and the context always + * keep in the critical section, so the Dtd sequence would still keep non-empty and the loop would be endless. + * We set the Dtd's dtdInvalid in this while and add an if statement in the next loop so that this issue could + * be fixed. + */ + while (NULL != currentDtd) + { + currentDtd->reservedUnion.originalBufferInfo.dtdInvalid = 1U; + currentDtd = (usb_device_ehci_dtd_struct_t *)(currentDtd->nextDtdPointer & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + + /* Get the first dtd */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + while (NULL != currentDtd) + { + /* this if statement is used with the previous while loop to avoid the endless loop */ + if (0U == currentDtd->reservedUnion.originalBufferInfo.dtdInvalid) + { + break; + } + else + { + if (0U != (currentDtd->dtdTokenUnion.dtdTokenBitmap.status & USB_DEVICE_ECHI_DTD_STATUS_ACTIVE)) + { + /* Flush the endpoint to stop a transfer. */ + do + { + /* Set the corresponding bit(s) in the EPFLUSH register */ + ehciState->registerBase->EPFLUSH |= primeBit; + + /* Wait until all bits in the EPFLUSH register are cleared. */ + while (0U != (ehciState->registerBase->EPFLUSH & primeBit)) + { + } + /* + * Read the EPSR register to ensure that for all endpoints + * commanded to be flushed, that the corresponding bits + * are now cleared. + */ + } while (0U != (ehciState->registerBase->EPSR & primeBit)); + } + + /* Save the original buffer address. */ + if (NULL == message.buffer) + { + message.buffer = (uint8_t *)((currentDtd->bufferPointerPage[0] & USB_DEVICE_ECHI_DTD_PAGE_MASK) | + (currentDtd->reservedUnion.originalBufferInfo.originalBufferOffest)); + } + + /* Remove the dtd from the dtd in-used queue. */ + if (ehciState->dtdHard[index] == ehciState->dtdTail[index]) + { + ehciState->dtdHard[index] = NULL; + ehciState->dtdTail[index] = NULL; + } + else + { + ehciState->dtdHard[index] = (usb_device_ehci_dtd_struct_t *)ehciState->dtdHard[index]->nextDtdPointer; + } + + /* When the ioc is set or the dtd queue is empty, the up layer will be notified. */ + if ((0U != currentDtd->dtdTokenUnion.dtdTokenBitmap.ioc) || + (0U == ((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK))) + { + flag = 1; + } + /* Clear the token field. */ + currentDtd->dtdTokenUnion.dtdToken = 0U; + /* Save the dtd to the free queue. */ + currentDtd->nextDtdPointer = (uint32_t)ehciState->dtdFree; + ehciState->dtdFree = currentDtd; + ehciState->dtdCount++; + } + /* Get the next dtd. */ + currentDtd = + (usb_device_ehci_dtd_struct_t *)((uint32_t)ehciState->dtdHard[index] & USB_DEVICE_ECHI_DTD_POINTER_MASK); + } + if (NULL == currentDtd) + { + /* Set the QH to empty. */ + ehciState->qh[index].nextDtdPointer = USB_DEVICE_ECHI_DTD_TERMINATE_MASK; + ehciState->qh[index].dtdTokenUnion.dtdToken = 0U; + } + OSA_EXIT_CRITICAL(); + + if (0U != flag) + { + message.code = ep; + message.isSetup = 0U; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + message.buffer = NULL; + } + + return kStatus_USB_Success; +} + +/*! + * @brief Control the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param ehciHandle Pointer of the device EHCI handle. + * @param type The selected item. Please refer to enumeration type usb_device_control_type_t. + * @param param The param type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, usb_device_control_type_t type, void *param) +{ + usb_device_ehci_state_struct_t *ehciState = (usb_device_ehci_state_struct_t *)ehciHandle; + usb_status_t error = kStatus_USB_Error; +#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U) + uint32_t *temp32; +#endif + uint16_t *temp16; + uint8_t *temp8; +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + struct usb_device_struct *deviceHandle; +#endif +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + uint64_t startTick; +#endif +#endif + + if (NULL == ehciHandle) + { + return kStatus_USB_InvalidHandle; + } + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + deviceHandle = (struct usb_device_struct *)ehciState->deviceHandle; +#endif + + switch (type) + { + case kUSB_DeviceControlRun: + ehciState->registerBase->USBCMD |= USBHS_USBCMD_RS_MASK; + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlStop: + ehciState->registerBase->USBCMD &= ~USBHS_USBCMD_RS_MASK; + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlEndpointInit: + if (NULL != param) + { + error = USB_DeviceEhciEndpointInit(ehciState, (usb_device_endpoint_init_struct_t *)param); + } + break; + case kUSB_DeviceControlEndpointDeinit: + if (NULL != param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointDeinit(ehciState, *temp8); + } + break; + case kUSB_DeviceControlEndpointStall: + if (NULL != param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointStall(ehciState, *temp8); + } + break; + case kUSB_DeviceControlEndpointUnstall: + if (NULL != param) + { + temp8 = (uint8_t *)param; + error = USB_DeviceEhciEndpointUnstall(ehciState, *temp8); + } + break; + case kUSB_DeviceControlGetDeviceStatus: + if (NULL != param) + { + temp16 = (uint16_t *)param; + *temp16 = ((uint16_t)USB_DEVICE_CONFIG_SELF_POWER + << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT)) +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + | ((uint16_t)deviceHandle->remotewakeup + << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT)) +#endif + ; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetEndpointStatus: + if (NULL != param) + { + usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param; + uint8_t ep = (endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK; + uint8_t direction = + ((endpointStatus->endpointAddress) & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK) >> + USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT; + + if (ep < USB_DEVICE_CONFIG_ENDPOINTS) + { + if (0U != ep) + { + endpointStatus->endpointStatus = + (0U != (ehciState->registerBase->EPCR[ep - 1U] & + ((0U != direction) ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK))) ? + (uint16_t)kUSB_DeviceEndpointStateStalled : + (uint16_t)kUSB_DeviceEndpointStateIdle; + } + else + { + endpointStatus->endpointStatus = + (0U != (ehciState->registerBase->EPCR0 & + ((0U != direction) ? USBHS_EPCR_TXS_MASK : USBHS_EPCR_RXS_MASK))) ? + (uint16_t)kUSB_DeviceEndpointStateStalled : + (uint16_t)kUSB_DeviceEndpointStateIdle; + } + error = kStatus_USB_Success; + } + } + break; + case kUSB_DeviceControlPreSetDeviceAddress: + if (NULL != param) + { + temp8 = (uint8_t *)param; + ehciState->registerBase->DEVICEADDR = + ((((uint32_t)(*temp8)) << USBHS_DEVICEADDR_USBADR_SHIFT) | USBHS_DEVICEADDR_USBADRA_MASK); + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlSetDeviceAddress: + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlGetSynchFrame: + break; +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U) + case kUSB_DeviceControlResume: +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_FPR_MASK; + startTick = deviceHandle->hwTick; + while ((deviceHandle->hwTick - startTick) < 10U) + { + __NOP(); + } + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_FPR_MASK; + error = kStatus_USB_Success; + break; +#endif /* USB_DEVICE_CONFIG_REMOTE_WAKEUP */ + case kUSB_DeviceControlSuspend: + ehciState->registerBase->OTGSC |= 0x007F0000U; + ehciState->registerPhyBase->PWD = 0xFFFFFFFFU; + /* ehciState->registerBase->OTGCTL |= ((1U<<10) | (1U<<17) | (1U<<16)); */ + while (0U != (ehciState->registerPhyBase->CTRL & (USBPHY_CTRL_UTMI_SUSPENDM_MASK))) + { + __NOP(); + } + /* ehciState->registerPhyBase->CTRL |= ((1U << 21) | (1U << 22) | (1U << 23)); */ + ehciState->registerBase->USBSTS |= USBHS_USBSTS_SRI_MASK; +#if (defined(FSL_FEATURE_USBPHY_28FDSOI) && (FSL_FEATURE_USBPHY_28FDSOI > 0U)) + ehciState->registerPhyBase->USB1_VBUS_DETECT_SET |= USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK; +#endif + ehciState->registerBase->PORTSC1 |= USBHS_PORTSC1_PHCD_MASK; +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) +#if (defined(USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)) + ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_ENVBUSCHG_WKUP_MASK | USBPHY_CTRL_ENIDCHG_WKUP_MASK | + USBPHY_CTRL_ENDPDMCHG_WKUP_MASK | USBPHY_CTRL_ENIRQRESUMEDETECT_MASK; +#endif + ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK | + USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL |= USBNC_USB_OTGn_CTRL_WIE_MASK; +#else + ehciState->registerBase->USBGENCTRL = USBHS_USBGENCTRL_WU_IE_MASK; +#endif + ehciState->registerPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; + ehciState->isSuspending = 1U; + error = kStatus_USB_Success; + break; +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + case kUSB_DeviceControlSetDefaultStatus: + for (uint8_t count = 0U; count < USB_DEVICE_CONFIG_ENDPOINTS; count++) + { + (void)USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_IN << 0x07U))); + (void)USB_DeviceEhciEndpointDeinit(ehciState, (count | (USB_OUT << 0x07U))); + } + USB_DeviceEhciSetDefaultState(ehciState); + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlGetSpeed: + if (NULL != param) + { + temp8 = (uint8_t *)param; + *temp8 = ehciState->speed; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetOtgStatus: + break; + case kUSB_DeviceControlSetOtgStatus: + break; +#if (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) + case kUSB_DeviceControlSetTestMode: + if (param) + { + temp8 = (uint8_t *)param; + ehciState->registerBase->PORTSC1 |= ((uint32_t)(*temp8) << 16U); + error = kStatus_USB_Success; + } + break; +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + + case kUSB_DeviceControlUpdateHwTick: + /*udpate 1ms time tick*/ +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +#ifndef USBHSDCD_IRQS + USB_HSDcdIsrFunction(ehciState->dcdHandle); +#endif +#elif (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) + (void)USB_PHYDCD_TimerIsrFunction(ehciState->dcdHandle); +#endif + + error = kStatus_USB_Success; + break; + case kUSB_DeviceControlDcdEnable: + +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + if (kStatus_hsdcd_Success == USB_HSDCD_Control(ehciState->dcdHandle, kUSB_DeviceHSDcdEnable, NULL)) + { + error = kStatus_USB_Success; + } +#elif (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) + if (kStatus_phydcd_Success == USB_PHYDCD_Control(ehciState->dcdHandle, kUSB_DevicePHYDcdEnable, NULL)) + { + error = kStatus_USB_Success; + } +#endif + + break; + case kUSB_DeviceControlDcdDisable: + +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + if (kStatus_hsdcd_Success == USB_HSDCD_Control(ehciState->dcdHandle, kUSB_DeviceHSDcdDisable, NULL)) + { + error = kStatus_USB_Success; + } +#elif (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) + if (kStatus_phydcd_Success == USB_PHYDCD_Control(ehciState->dcdHandle, kUSB_DevicePHYDcdDisable, NULL)) + { + error = kStatus_USB_Success; + } +#endif + + break; +#endif +#if defined(USB_DEVICE_CONFIG_GET_SOF_COUNT) && (USB_DEVICE_CONFIG_GET_SOF_COUNT > 0U) + case kUSB_DeviceControlGetCurrentFrameCount: + if (NULL != param) + { + temp32 = (uint32_t *)param; + if (USB_SPEED_HIGH == ehciState->speed) + { + *temp32 = ehciState->registerBase->FRINDEX & (USB_DEVICE_MAX_FRAME_COUNT); + } + else /* if not high speed, change to use frame count */ + { + *temp32 = (ehciState->registerBase->FRINDEX & (USB_DEVICE_MAX_FRAME_COUNT)) / 8U; + } + error = kStatus_USB_Success; + } + break; +#endif + default: + /*no action*/ + break; + } + + return error; +} + +/*! + * @brief Handle the EHCI device interrupt. + * + * The function is used to handle the EHCI device interrupt. + * + * @param deviceHandle The device handle got from USB_DeviceInit. + * + */ +void USB_DeviceEhciIsrFunction(void *deviceHandle) +{ + struct usb_device_struct *handle = (struct usb_device_struct *)deviceHandle; + usb_device_ehci_state_struct_t *ehciState; + uint32_t status; + + if (NULL == deviceHandle) + { + return; + } + + ehciState = (usb_device_ehci_state_struct_t *)(handle->controllerHandle); + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + + if (0U != (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIE_MASK)) + { + if (0U != (ehciState->registerNcBase->USB_OTGn_CTRL & USBNC_USB_OTGn_CTRL_WIR_MASK)) + { + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerNcBase->USB_OTGn_CTRL &= ~USBNC_USB_OTGn_CTRL_WIE_MASK; + } + } + else + { + } + +#else + if (0U != (ehciState->registerBase->USBGENCTRL & USBHS_USBGENCTRL_WU_IE_MASK)) + { + if (0U != (ehciState->registerBase->USBGENCTRL & (1UL << 8))) + { + ehciState->registerBase->USBGENCTRL &= ~(1UL << 8); + ehciState->registerBase->USBGENCTRL |= USBHS_USBGENCTRL_WU_INT_CLR_MASK; + ehciState->registerBase->PORTSC1 &= ~USBHS_PORTSC1_PHCD_MASK; + ehciState->registerBase->USBGENCTRL &= ~USBHS_USBGENCTRL_WU_IE_MASK; + } + } + else + { + } +#endif + +#endif + +#if defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE > 0U) + if ((ehciState->registerBase->OTGSC & USBHS_OTGSC_BSVIS_MASK) != 0U) + { + usb_device_callback_message_struct_t message; + + ehciState->registerBase->OTGSC |= USBHS_OTGSC_BSVIS_MASK; + + message.buffer = (uint8_t *)NULL; + message.length = 0U; + message.isSetup = 0U; + if (0U != (ehciState->registerBase->OTGSC & USBHS_OTGSC_BSV_MASK)) + { + /* Device is connected to a host. */ + message.code = (uint8_t)kUSB_DeviceNotifyAttach; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) && \ + (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + + (void)USB_HSDCD_Control(ehciState->dcdHandle, kUSB_DeviceHSDcdRun, NULL); +#elif (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U)) + (void)USB_PHYDCD_Control(ehciState->dcdHandle, kUSB_DevicePHYDcdRun, NULL); +#endif + } + else + { + /* Device is disconnected from a host. */ + message.code = (uint8_t)kUSB_DeviceNotifyDetach; + (void)USB_DeviceNotificationTrigger(ehciState->deviceHandle, &message); + } + } +#endif /* USB_DEVICE_CONFIG_DETACH_ENABLE */ + + status = ehciState->registerBase->USBSTS; + status &= ehciState->registerBase->USBINTR; + + ehciState->registerBase->USBSTS = status; + +#if defined(USB_DEVICE_CONFIG_ERROR_HANDLING) && (USB_DEVICE_CONFIG_ERROR_HANDLING > 0U) + if (0U != (status & USBHS_USBSTS_UEI_MASK)) + { + /* Error interrupt */ + USB_DeviceEhciInterruptError(ehciState); + } +#endif /* USB_DEVICE_CONFIG_ERROR_HANDLING */ + + if (0U != (status & USBHS_USBSTS_URI_MASK)) + { + /* Reset interrupt */ + USB_DeviceEhciInterruptReset(ehciState); + } + + if (0U != (status & USBHS_USBSTS_UI_MASK)) + { + /* Token done interrupt */ + USB_DeviceEhciInterruptTokenDone(ehciState); + } + + if (0U != (status & USBHS_USBSTS_PCI_MASK)) + { + /* Port status change interrupt */ + USB_DeviceEhciInterruptPortChange(ehciState); + } + +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if (0U != (status & USBHS_USBSTS_SLI_MASK)) + { + /* Suspend interrupt */ + USB_DeviceEhciInterruptSuspend(ehciState); + } +#endif /* USB_DEVICE_CONFIG_LOW_POWER_MODE */ + + if (0U != (status & USBHS_USBSTS_SRI_MASK)) + { + /* Sof interrupt */ + USB_DeviceEhciInterruptSof(ehciState); + } +} + +#endif /* USB_DEVICE_CONFIG_EHCI */ diff --git a/zephyr/middleware/usb/device/usb_device_ehci.h b/zephyr/middleware/usb/device/usb_device_ehci.h new file mode 100644 index 000000000..2f7567db5 --- /dev/null +++ b/zephyr/middleware/usb/device/usb_device_ehci.h @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_DEVICE_EHCI_H__ +#define __USB_DEVICE_EHCI_H__ + +/*! + * @addtogroup usb_device_controller_ehci_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The maximum value of ISO type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_ISO_MAX_PACKET_SIZE (1024U) + +/*! @brief The maximum value of interrupt type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_INTERUPT_MAX_PACKET_SIZE (1024U) + +/*! @brief The maximum value of bulk type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_BULK_MAX_PACKET_SIZE (512U) + +/*! @brief The maximum value of control type maximum packet size for HS in USB specification 2.0 */ +#define USB_DEVICE_MAX_HS_CONTROL_MAX_PACKET_SIZE (64U) + +#define USB_DEVICE_MAX_TRANSFER_PRIME_TIMES \ + (10000000U) /* The max prime times of EPPRIME, if still doesn't take effect, means status has been reset*/ + +/* Device QH */ +#define USB_DEVICE_EHCI_QH_POINTER_MASK (0xFFFFFFC0U) +#define USB_DEVICE_EHCI_QH_MULT_MASK (0xC0000000U) +#define USB_DEVICE_EHCI_QH_ZLT_MASK (0x20000000U) +#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE_MASK (0x07FF0000U) +#define USB_DEVICE_EHCI_QH_MAX_PACKET_SIZE (0x00000800U) +#define USB_DEVICE_EHCI_QH_IOS_MASK (0x00008000U) + +/* Device DTD */ +#define USB_DEVICE_ECHI_DTD_POINTER_MASK (0xFFFFFFE0U) +#define USB_DEVICE_ECHI_DTD_TERMINATE_MASK (0x00000001U) +#define USB_DEVICE_ECHI_DTD_PAGE_MASK (0xFFFFF000U) +#define USB_DEVICE_ECHI_DTD_PAGE_OFFSET_MASK (0x00000FFFU) +#define USB_DEVICE_ECHI_DTD_PAGE_BLOCK (0x00001000U) +#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES_MASK (0x7FFF0000U) +#define USB_DEVICE_ECHI_DTD_TOTAL_BYTES (0x00004000U) +#define USB_DEVICE_ECHI_DTD_IOC_MASK (0x00008000U) +#define USB_DEVICE_ECHI_DTD_MULTIO_MASK (0x00000C00U) +#define USB_DEVICE_ECHI_DTD_STATUS_MASK (0x000000FFU) +#define USB_DEVICE_EHCI_DTD_STATUS_ERROR_MASK (0x00000068U) +#define USB_DEVICE_ECHI_DTD_STATUS_ACTIVE (0x00000080U) +#define USB_DEVICE_ECHI_DTD_STATUS_HALTED (0x00000040U) +#define USB_DEVICE_ECHI_DTD_STATUS_DATA_BUFFER_ERROR (0x00000020U) +#define USB_DEVICE_ECHI_DTD_STATUS_TRANSACTION_ERROR (0x00000008U) + +typedef struct _usb_device_ehci_qh_struct +{ + union + { + volatile uint32_t capabilttiesCharacteristics; + struct + { + volatile uint32_t reserved1 : 15; + volatile uint32_t ios : 1; + volatile uint32_t maxPacketSize : 11; + volatile uint32_t reserved2 : 2; + volatile uint32_t zlt : 1; + volatile uint32_t mult : 2; + } capabilttiesCharacteristicsBitmap; + } capabilttiesCharacteristicsUnion; + volatile uint32_t currentDtdPointer; + volatile uint32_t nextDtdPointer; + union + { + volatile uint32_t dtdToken; + struct + { + volatile uint32_t status : 8; + volatile uint32_t reserved1 : 2; + volatile uint32_t multiplierOverride : 2; + volatile uint32_t reserved2 : 3; + volatile uint32_t ioc : 1; + volatile uint32_t totalBytes : 15; + volatile uint32_t reserved3 : 1; + } dtdTokenBitmap; + } dtdTokenUnion; + volatile uint32_t bufferPointerPage[5]; + volatile uint32_t reserved1; + uint32_t setupBuffer[2]; + uint32_t setupBufferBack[2]; + union + { + uint32_t endpointStatus; + struct + { + uint32_t isOpened : 1; + uint32_t zlt: 1; + uint32_t : 30; + } endpointStatusBitmap; + } endpointStatusUnion; + uint32_t reserved2; +} usb_device_ehci_qh_struct_t; + +typedef struct _usb_device_ehci_dtd_struct +{ + volatile uint32_t nextDtdPointer; + union + { + volatile uint32_t dtdToken; + struct + { + volatile uint32_t status : 8; + volatile uint32_t reserved1 : 2; + volatile uint32_t multiplierOverride : 2; + volatile uint32_t reserved2 : 3; + volatile uint32_t ioc : 1; + volatile uint32_t totalBytes : 15; + volatile uint32_t reserved3 : 1; + } dtdTokenBitmap; + } dtdTokenUnion; + volatile uint32_t bufferPointerPage[5]; + union + { + volatile uint32_t reserved; + struct + { + uint32_t originalBufferOffest : 12; + uint32_t originalBufferLength : 19; + uint32_t dtdInvalid : 1; + } originalBufferInfo; + } reservedUnion; +} usb_device_ehci_dtd_struct_t; + +/*! @brief EHCI state structure */ +typedef struct _usb_device_ehci_state_struct +{ + struct usb_device_struct *deviceHandle; /*!< Device handle used to identify the device object is belonged to */ + USBHS_Type *registerBase; /*!< The base address of the register */ +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + USBPHY_Type *registerPhyBase; /*!< The base address of the PHY register */ +#if (defined(FSL_FEATURE_SOC_USBNC_COUNT) && (FSL_FEATURE_SOC_USBNC_COUNT > 0U)) + USBNC_Type *registerNcBase; /*!< The base address of the USBNC register */ +#endif +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) || \ + (defined(FSL_FEATURE_SOC_USB_ANALOG_COUNT) && (FSL_FEATURE_SOC_USB_ANALOG_COUNT > 0U))) + void *dcdHandle; /*!< Dcd handle used to identify the device object belongs to */ +#endif + usb_device_ehci_qh_struct_t *qh; /*!< The QH structure base address */ + usb_device_ehci_dtd_struct_t *dtd; /*!< The DTD structure base address */ + usb_device_ehci_dtd_struct_t *dtdFree; /*!< The idle DTD list head */ + usb_device_ehci_dtd_struct_t + *dtdHard[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list head for each endpoint */ + usb_device_ehci_dtd_struct_t + *dtdTail[USB_DEVICE_CONFIG_ENDPOINTS * 2]; /*!< The transferring DTD list tail for each endpoint */ + uint8_t dtdCount; /*!< The idle DTD node count */ + uint8_t endpointCount; /*!< The endpoint number of EHCI */ + uint8_t isResetting; /*!< Whether a PORT reset is occurring or not */ + uint8_t controllerId; /*!< Controller ID */ + uint8_t speed; /*!< Current speed of EHCI */ + uint8_t isSuspending; /*!< Is suspending of the PORT */ +} usb_device_ehci_state_struct_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name USB device EHCI functions + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief Initializes the USB device EHCI instance. + * + * This function initializes the USB device EHCI module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration type usb_controller_index_t. + * @param[in] handle Pointer of the device handle used to identify the device object is belonged to. + * @param[out] ehciHandle An out parameter used to return the pointer of the device EHCI handle to the caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *ehciHandle); + +/*! + * @brief Deinitializes the USB device EHCI instance. + * + * This function deinitializes the USB device EHCI module. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciDeinit(usb_device_controller_handle ehciHandle); + +/*! + * @brief Sends data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. + * @param[in] length The data length to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value means whether the sending request is successful or not. The transfer completion is indicated + * by the + * corresponding callback function. + * Currently, only one transfer request can be supported for a specific endpoint. + * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer can begin only when the previous transfer is done (a notification is received through the + * endpoint + * callback). + */ +usb_status_t USB_DeviceEhciSend(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receive data through a specified endpoint. + * + * This function Receives data through a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length want to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value just means if the receiving request is successful or not; the transfer done is notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for one specific endpoint. + * If there is a specific requirement to support multiple transfer requests for one specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer could begin only when the previous transfer is done (get notification through the endpoint + * callback). + */ +usb_status_t USB_DeviceEhciRecv(usb_device_controller_handle ehciHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciCancel(usb_device_controller_handle ehciHandle, uint8_t ep); + +/*! + * @brief Controls the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param[in] ehciHandle Pointer of the device EHCI handle. + * @param[in] type The selected item. See enumeration type usb_device_control_type_t. + * @param[in,out] param The parameter type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceEhciControl(usb_device_controller_handle ehciHandle, + usb_device_control_type_t type, + void *param); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __USB_DEVICE_EHCI_H__ */ diff --git a/zephyr/middleware/usb/device/usb_device_lpcip3511.c b/zephyr/middleware/usb/device/usb_device_lpcip3511.c new file mode 100644 index 000000000..a0f78be3f --- /dev/null +++ b/zephyr/middleware/usb/device/usb_device_lpcip3511.c @@ -0,0 +1,2335 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017,2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "usb_dc_mcux.h" +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + ((defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U))) +#include "usb_hsdcd.h" +#endif +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) +#include "usb_phy.h" +#endif +#endif +#if (((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) || \ + ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U))) +#include "usb_device_lpcip3511.h" + +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + +#define USB_LPC3511IP_INTSTAT_DEV_INT_MASK USBHSD_INTSTAT_DEV_INT_MASK +#define USB_LPC3511IP_INTSTAT_FRAME_INT_MASK USBHSD_INTSTAT_FRAME_INT_MASK + +#define USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK +#define USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK + +#define USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_MASK USBHSD_DEVCMDSTAT_LPM_REWP_MASK +#define USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_SHIFT USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT + +#define USB_LPC3511IP_DEVCMDSTAT_Speed_MASK USBHSD_DEVCMDSTAT_Speed_MASK + +#define USB_LPC3511IP_DEVCMDSTAT_DCON_MASK USBHSD_DEVCMDSTAT_DCON_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK USBHSD_DEVCMDSTAT_DEV_EN_MASK +#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK USBHSD_DEVCMDSTAT_LPM_SUP_MASK +#define USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK +#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK USBHSD_DEVCMDSTAT_LPM_SUS_MASK + +#define USB_LPC3511IP_USB_LPM_HIRD_SW USBHSD_LPM_HIRD_SW + +#define USB_LPC3511IP_DEVCMDSTAT_DEV_ADDR_MASK USBHSD_DEVCMDSTAT_DEV_ADDR_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK USBHSD_DEVCMDSTAT_DSUS_MASK +#define USB_LPC3511IP_INFO_ERR_CODE_MASK USBHSD_INFO_ERR_CODE_MASK +#define USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK USBHSD_DEVCMDSTAT_SETUP_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DRES_C_MASK USBHSD_DEVCMDSTAT_DRES_C_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DSUS_C_MASK USBHSD_DEVCMDSTAT_DSUS_C_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DCON_C_MASK USBHSD_DEVCMDSTAT_DCON_C_MASK +#define USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK +#else +#define USB_LPC3511IP_INTSTAT_DEV_INT_MASK USB_INTSTAT_DEV_INT_MASK +#define USB_LPC3511IP_INTSTAT_FRAME_INT_MASK USB_INTSTAT_FRAME_INT_MASK + +#define USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK USB_DEVCMDSTAT_INTONNAK_AO_MASK +#define USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK USB_DEVCMDSTAT_INTONNAK_AI_MASK + +#define USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_MASK USB_DEVCMDSTAT_LPM_REWP_MASK +#define USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_SHIFT USB_DEVCMDSTAT_LPM_REWP_SHIFT + +#define USB_LPC3511IP_DEVCMDSTAT_DCON_MASK USB_DEVCMDSTAT_DCON_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK USB_DEVCMDSTAT_DEV_EN_MASK +#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK USB_DEVCMDSTAT_LPM_SUP_MASK +#define USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK +#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK USB_DEVCMDSTAT_LPM_SUP_MASK +#define USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK USB_DEVCMDSTAT_LPM_SUS_MASK + +#define USB_LPC3511IP_USB_LPM_HIRD_SW USB_LPM_HIRD_SW + +#define USB_LPC3511IP_DEVCMDSTAT_DEV_ADDR_MASK USB_DEVCMDSTAT_DEV_ADDR_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK USB_DEVCMDSTAT_DSUS_MASK +#define USB_LPC3511IP_INFO_ERR_CODE_MASK USB_INFO_ERR_CODE_MASK +#define USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK USB_DEVCMDSTAT_SETUP_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DRES_C_MASK USB_DEVCMDSTAT_DRES_C_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DSUS_C_MASK USB_DEVCMDSTAT_DSUS_C_MASK +#define USB_LPC3511IP_DEVCMDSTAT_DCON_C_MASK USB_DEVCMDSTAT_DCON_C_MASK +#define USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK +#endif + +#define USB_LPC3511IP_USB_LPM_ADPPROBE_MASK (0x00100000u) + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* on Aruba IP3511 (USB0 FS), there are 8 physical EPs, on IP3511 HS (USB1 FS), there are 10 physical EPs. */ +#define USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK (0xFFFFu) + +/*! @brief endpoint command status, buffer address offset */ +#define USB_LPC3511IPHS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK (0x000007FFu) +#define USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_SHIFT (11) +#define USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_MASK (0x03FFF800u) +#define USB_LPC3511IPFS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK (0x0000FFFFu) +#define USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_SHIFT (16) +#define USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_MASK (0x03FF0000u) + +#define USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK (0x01UL << 26) +#define USB_LPC3511IP_ENDPOINT_RFTV_MASK (0x01UL << 27) +#define USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK (0x01UL << 28) +#define USB_LPC3511IP_ENDPOINT_STALL_MASK (0x01UL << 29) +#define USB_LPC3511IP_ENDPOINT_STALL_SHIFT (29) +#define USB_LPC3511IP_ENDPOINT_DISABLE_MASK (0x01UL << 30) +#define USB_LPC3511IP_ENDPOINT_ACTIVE_MASK (0x01UL << 31) +#define USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT (26) + +#define USB_LPC3511IP_DEVCMDSTAT_INTERRUPT_WC_MASK (0x0F000000u) + +#define USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(lpcState, index, odd, value) \ + *((volatile uint32_t *)(((uint32_t)((lpcState)->epCommandStatusList)) | ((uint32_t)(index) << 3) | \ + ((((uint32_t)(odd)) & 1UL) << 2U))) &= (value) + +/*! @brief Set endpoint command/status value */ +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#define USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpcState, index, odd, value, NBytes, address) \ + \ + *((volatile uint32_t *)(((uint32_t)((lpcState)->epCommandStatusList)) | ((uint32_t)(index) << 3) | \ + (((((uint32_t)(odd)) & 1UL)) << 2U))) = \ + ((0U != lpc3511IpState->controllerSpeed) ? \ + \ + ((uint32_t)(value) | ((uint32_t)(NBytes) << USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_SHIFT) | \ + (((uint32_t)(address) >> 6) & USB_LPC3511IPHS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK)) : \ + \ + ((uint32_t)(value) | ((uint32_t)(NBytes) << USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_SHIFT) | \ + (((uint32_t)(address) >> 6) & USB_LPC3511IPFS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK))) +#else +#define USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpcState, index, odd, value, NBytes, address) \ + \ + *((volatile uint32_t *)(((uint32_t)((lpcState)->epCommandStatusList)) | ((uint32_t)(index) << 3) | \ + (((((uint32_t)(odd)) & 1U)) << 2U))) = \ + ((uint32_t)(value) | ((uint32_t)(NBytes) << USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_SHIFT) | \ + (((uint32_t)(address) >> 6) & USB_LPC3511IPFS_ENDPOINT_BUFFER_ADDRESS_OFFSET_MASK)) +#endif + +#define USB_LPC3511IP_ENDPOINT_DES_INDEX(endpoint) \ + (((((endpoint)) & 0x0FU) << 1) + \ + ((0U != ((endpoint)&USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK)) ? (1U) : (0U))) + +#define USB_LPC3511IP_GET_MULTIPLE_OF_64(n) ((((uint32_t)n) + 63U) & 0xFFFFFFC0U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +static usb_status_t USB_DeviceLpc3511IpTransaction(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + usb_device_lpc3511ip_endpoint_state_struct_t *epState, + uint8_t endpointIndex); +static usb_status_t USB_DeviceLpc3511IpControlPreSetDeviceAddress(usb_device_controller_handle controllerHandle, + void *param); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* define the reserved buffer for endpoint max packet copy */ + +#define SETUP_TRANSFER_DATA_OFFSET (0U) +#define CONTROL_TRANSFER_DATA_OFFSET ((USB_DATA_ALIGN_SIZE_MULTIPLE(8U) >> 2)) +#define ZERO_TRANSFER_DATA_OFFSET ((USB_DATA_ALIGN_SIZE_MULTIPLE(8U) >> 2) + (USB_DATA_ALIGN_SIZE_MULTIPLE(64U) >> 2)) +#define RESERVED_EP_DATA_OFFSET \ + ((USB_DATA_ALIGN_SIZE_MULTIPLE(8U) >> 2) + (USB_DATA_ALIGN_SIZE_MULTIPLE(64U) >> 2) + \ + (USB_DATA_ALIGN_SIZE_MULTIPLE(4U) >> 2)) + +#if defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) +USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static uint32_t + s_SetupAndEpReservedData[USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY] + [USB_DATA_ALIGN_SIZE_MULTIPLE((USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE >> 2)) + + RESERVED_EP_DATA_OFFSET]; +#else +USB_GLOBAL USB_RAM_ADDRESS_ALIGNMENT(USB_DATA_ALIGN_SIZE) static uint32_t + s_SetupAndEpReservedData[USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS][RESERVED_EP_DATA_OFFSET]; +#endif + +static usb_device_lpc3511ip_state_struct_t + s_UsbDeviceLpc3511IpState[USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS]; + +/* LPC3511IP controller driver instances and endpoint command/status list, EPLISTSTART's value is the buffer pointer. */ +#if ((USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) == 1U) +USB_CONTROLLER_DATA USB_RAM_ADDRESS_ALIGNMENT(256) static uint32_t + s_EpCommandStatusList1[((USB_DEVICE_IP3511_ENDPOINTS_NUM)) * 4]; +#define LPC_CONTROLLER_ENDPOINT_LIST_ARRAY \ + { \ + &s_EpCommandStatusList1[0] \ + } + +#elif ((USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) == 2U) +USB_CONTROLLER_DATA USB_RAM_ADDRESS_ALIGNMENT(256) static uint32_t + s_EpCommandStatusList1[(USB_DEVICE_IP3511_ENDPOINTS_NUM)*4]; +USB_CONTROLLER_DATA USB_RAM_ADDRESS_ALIGNMENT(256) static uint32_t + s_EpCommandStatusList2[(USB_DEVICE_IP3511_ENDPOINTS_NUM)*4]; +#define LPC_CONTROLLER_ENDPOINT_LIST_ARRAY \ + { \ + &s_EpCommandStatusList1[0], &s_EpCommandStatusList2[0] \ + } + +#else +#error "increase the instance count." +#endif + +#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) +#if (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == (USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS)) +#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 1U +#elif ((USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == USB_DEVICE_CONFIG_LPCIP3511FS) && \ + (!USB_DEVICE_CONFIG_LPCIP3511HS)) +#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 1U +#elif ((USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == USB_DEVICE_CONFIG_LPCIP3511HS) && \ + (!USB_DEVICE_CONFIG_LPCIP3511FS)) +#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 1U +#else +#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 0U +#endif + +#else +#define USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER 0U + +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) + +static inline uint8_t USB_DeviceLpcIp3511MaxPacketNeedCopy(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ +#if (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == (USB_DEVICE_CONFIG_LPCIP3511HS + USB_DEVICE_CONFIG_LPCIP3511FS)) + return 1U; +#elif (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == USB_DEVICE_CONFIG_LPCIP3511HS) + return (lpc3511IpState->controllerSpeed); +#elif (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY == USB_DEVICE_CONFIG_LPCIP3511FS) +#if (defined USB_DEVICE_CONFIG_LPCIP3511HS) && (USB_DEVICE_CONFIG_LPCIP3511HS) + if (0U != lpc3511IpState->controllerSpeed) + { + return 0U; + } + else + { + return 1U; + } +#else + return 1U; +#endif +#endif +} + +static uint8_t *USB_DeviceLpcIp3511MallocMaxPacketBuffer(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + uint32_t multile64) +{ + uint32_t bitsIndex; + uint32_t numIndex; + OSA_SR_ALLOC(); + + multile64 = ((multile64 + 63U) / 64U); + bitsIndex = 0U; + OSA_ENTER_CRITICAL(); + do + { + numIndex = 0U; + for (; numIndex < multile64; ++numIndex) + { + if (bitsIndex >= USB_DEVICE_IP3511_BITS_FOR_RESERVED_BUFFER) + { + OSA_EXIT_CRITICAL(); + return NULL; /* fail */ + } + if (0U != (lpc3511IpState->epReservedBufferBits[(bitsIndex / 8U)] & + (uint8_t)(0x01U << (bitsIndex & 0x00000007U)))) /* has allocated */ + { + bitsIndex++; + break; + } + bitsIndex++; + } + } while (numIndex < multile64); + + if (numIndex >= multile64) + { + /* set the bits */ + for (numIndex = 0U; numIndex < multile64; ++numIndex) + { + lpc3511IpState->epReservedBufferBits[((bitsIndex - multile64 + numIndex) / 8U)] |= + (uint8_t)(0x01U << ((bitsIndex - multile64 + numIndex) & 0x00000007U)); + } + OSA_EXIT_CRITICAL(); + return lpc3511IpState->epReservedBuffer + ((bitsIndex - multile64) * 64U); + } + else + { + OSA_EXIT_CRITICAL(); + return NULL; + } +} + +static void USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + uint8_t *buffer, + uint32_t bufferSize) +{ + uint32_t bitsIndex; + int32_t temp; + uint8_t bitsNum; + OSA_SR_ALLOC(); + + if ((buffer < lpc3511IpState->epReservedBuffer) || + (buffer >= (lpc3511IpState->epReservedBuffer + USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE))) + { + return; + } + /*misra 10.8*/ + temp = ((buffer - lpc3511IpState->epReservedBuffer) / 64); + bitsIndex = (uint32_t)temp; + + OSA_ENTER_CRITICAL(); + for (bitsNum = 0; bitsNum < ((bufferSize + 63U) / 64U); ++bitsNum) + { + lpc3511IpState->epReservedBufferBits[((bitsIndex + bitsNum) / 8U)] &= + (uint8_t)(~(0x01U << ((bitsIndex + bitsNum) & 0x00000007U))); /* clear the bit */ + } + OSA_EXIT_CRITICAL(); +} +#endif + +static usb_device_lpc3511ip_endpoint_state_struct_t *USB_DeviceLpc3511IpGetEndpointStateStruct( + usb_device_lpc3511ip_state_struct_t *lpc3511IpState, uint8_t endpointIndex) +{ + if (endpointIndex <= ((uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM * 2U)) + { + return &(lpc3511IpState->endpointState[endpointIndex]); + } + + return NULL; +} + +/*! + * @brief Write the command/status entry to start a transfer. + * + * The function is used to start a transfer by writing the command/status entry. + * + * @param lpc3511IpState Pointer of the controller state structure. + * @param endpoint Endpoint number. + * @param direction The direction of the endpoint, 0U - USB_OUT, 1U - USB_IN. + * @param buffer The memory address to save the received data, or the memory address to hold the data need to + * be sent. + * @param length The length of the data. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceLpc3511IpEndpointPrime(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + usb_device_lpc3511ip_endpoint_state_struct_t *epState, + uint8_t endpointIndex, + uint8_t *buffer, + uint32_t length) +{ + uint8_t odd; + + OSA_SR_ALLOC(); + + /* Enter critical */ + OSA_ENTER_CRITICAL(); + + /* Flag the endpoint is busy. */ + epState->stateUnion.stateBitField.transferring = 1U; + + /* update the endpoint status */ + epState->transferPrimedLength += length; +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + if ((endpointIndex >> 1U) != USB_ENDPOINT_CONTROL) + { + odd = (uint8_t)epState->stateUnion.stateBitField.producerOdd; + epState->stateUnion.stateBitField.doubleBufferBusy++; + epState->stateUnion.stateBitField.producerOdd ^= 1U; + } + else +#endif + { + odd = 0U; + } + epState->epBufferStatusUnion[odd].epBufferStatusField.transactionLength = (uint16_t)length; + + /* when receive the zero length packet, the controller will set 4 bytes buffer as 0x00 */ + if (buffer == NULL) + { + buffer = lpc3511IpState->zeroTransactionData; + } + + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT( + lpc3511IpState, endpointIndex, odd, + (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT) | + USB_LPC3511IP_ENDPOINT_ACTIVE_MASK, + length, (uint32_t)buffer); + if (0U != (epState->stateUnion.stateBitField.epControlDefault & + ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT))) + { + epState->stateUnion.stateBitField.epControlDefault &= + (~((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT)); + } + /* Exit critical */ + OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; +} + +#if 0 +/*! + * @brief Prime a next setup transfer. + * + * The function is used to prime a buffer in control out pipe to wait for receiving the host's setup packet. + * + * @param lpc3511IpState Pointer of the controller state structure. + * + */ +static void USB_DeviceLpc3511IpPrimeNextSetup(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, 0, 1, 0, 8, lpc3511IpState->setupData); +} +#endif + +/*! + * @brief reset ip3511. + * + * @param lpc3511IpState Pointer of the controller state structure. + * + */ +static void USB_DeviceLpc3511IpSetDefaultState(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ + uint32_t index = 0; + uint8_t usbAddress; + usb_status_t error = kStatus_USB_Error; + /* zero the command/status list buffer and disable all endpoints */ + for (index = 0; index < 4U; ++index) + { + lpc3511IpState->epCommandStatusList[index] = 0x00000000U; + } + for (index = 4U; index < (uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM * 4U; ++index) + { + lpc3511IpState->epCommandStatusList[index] = USB_LPC3511IP_ENDPOINT_DISABLE_MASK; + } + + /* set address as 0 */ + usbAddress = 0U; + error = USB_DeviceLpc3511IpControlPreSetDeviceAddress(lpc3511IpState, &usbAddress); + if (kStatus_USB_Success == error) + { + /*no action, just for misra4.7*/ + } + lpc3511IpState->registerBase->EPLISTSTART = (uint32_t)lpc3511IpState->epCommandStatusList; +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + if (0U != lpc3511IpState->controllerSpeed) + { + if ((USBHSD_DATABUFSTART_DA_BUF_MASK & (uint32_t)lpc3511IpState->setupData) != + lpc3511IpState->registerBase->DATABUFSTART) + { + /* please use the dedicated ram */ + } + } + else +#endif + { + /* all data buffer is in the same 4M range with this setup data buffer */ + lpc3511IpState->registerBase->DATABUFSTART = (uint32_t)lpc3511IpState->setupData; + } + /* reset registers */ + lpc3511IpState->registerBase->EPINUSE = 0x0; + lpc3511IpState->registerBase->EPSKIP = 0x0; +/* enable all double-buffer */ +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + lpc3511IpState->registerBase->EPBUFCFG = USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK; +#else + lpc3511IpState->registerBase->EPBUFCFG = 0x00000000U; +#endif + /* clear interrupts + * don't clear DEV_INT because the vbus valid interrupt may occurs with keeping usb connected and reseting device. + */ + lpc3511IpState->registerBase->INTSTAT = + (USB_LPC3511IP_INTSTAT_FRAME_INT_MASK | USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK); + /* enable interrupts */ + lpc3511IpState->registerBase->INTEN = USB_LPC3511IP_INTSTAT_DEV_INT_MASK | USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK; + + /* Clear reset flag */ + lpc3511IpState->isResetting = 0U; +} + +/* Config and Enable endpoint */ +static usb_status_t USB_DeviceLpc3511IpEndpointInit(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + usb_device_endpoint_init_struct_t *epInit) +{ + uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(epInit->endpointAddress); + usb_device_lpc3511ip_endpoint_state_struct_t *epState = + USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex); + uint16_t maxPacketSize = epInit->maxPacketSize; + + /* clear the endpoint status bits */ + epState->stateUnion.state = 0x00000000U; + lpc3511IpState->registerBase->EPINUSE &= (~((uint32_t)(0x01UL << endpointIndex))); + /* Save the max packet size of the endpoint */ + epState->stateUnion.stateBitField.maxPacketSize = maxPacketSize; + /* Set the ZLT field */ + epState->stateUnion.stateBitField.zlt = epInit->zlt; + epState->stateUnion.stateBitField.endpointType = epInit->transferType; + + /* get the endpoint default control value */ + if (USB_ENDPOINT_ISOCHRONOUS == epInit->transferType) + { + epState->stateUnion.stateBitField.epControlDefault = + (USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT); + } +#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + else if ( +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + (0U == (lpc3511IpState->hsInterruptIssue)) && +#endif + (0U != lpc3511IpState->controllerSpeed) && (USB_ENDPOINT_INTERRUPT == epInit->transferType)) + { + epState->stateUnion.stateBitField.epControlDefault = + ((USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK | USB_LPC3511IP_ENDPOINT_RFTV_MASK) >> + USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT); + } +#endif +#endif + else + { + epState->stateUnion.stateBitField.epControlDefault = 0x00U; + } + /* set the command/status value */ + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT( + lpc3511IpState, endpointIndex, 0U, + (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT), 0U, 0U); + if ((epInit->endpointAddress & USB_ENDPOINT_NUMBER_MASK) == USB_CONTROL_ENDPOINT) + { + if (0U == (epInit->endpointAddress & USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK)) + { + /* Prime setup packet when the endpoint is control out endpoint. */ + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, 0U, 1U, 0U, 0U, (uint32_t)lpc3511IpState->setupData); + } + } + else + { + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT( + lpc3511IpState, endpointIndex, 1U, + (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT), 0U, + 0U); + } + if ((endpointIndex >> 1) != USB_CONTROL_ENDPOINT) + { + /* toggle reset for the toggle */ + epState->stateUnion.stateBitField.epControlDefault |= + ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT); + } + + epState->epPacketBuffer = NULL; + if ((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT) /* control endpoint */ + { + epState->epPacketBuffer = lpc3511IpState->controlData; + } +#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) + else + { + if (0U != USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState)) + { +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + uint8_t *maxPacketBuffer = USB_DeviceLpcIp3511MallocMaxPacketBuffer( + lpc3511IpState, USB_LPC3511IP_GET_MULTIPLE_OF_64(maxPacketSize) * 2U); +#else + uint8_t *maxPacketBuffer = USB_DeviceLpcIp3511MallocMaxPacketBuffer(lpc3511IpState, maxPacketSize); +#endif + if (maxPacketBuffer == NULL) + { + return kStatus_USB_AllocFail; + } + epState->epPacketBuffer = maxPacketBuffer; + } + } +#endif + + return kStatus_USB_Success; +} + +/*! + * @brief De-initialize a specified endpoint. + * + * The function is used to de-initialize a specified endpoint. + * Current transfer of the endpoint will be canceled and the specified endpoint will be disabled. + * + * @param lpc3511IpState Pointer of the controller state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceLpc3511IpEndpointDeinit(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, uint8_t ep) +{ + uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(ep); + usb_device_lpc3511ip_endpoint_state_struct_t *epState = + USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex); + + /* Cancel the transfer of the endpoint */ + (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, ep); + +#if (defined USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY) + if (0U != USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState)) + { + if ((endpointIndex >> 1U) != USB_CONTROL_ENDPOINT) /* control endpoint */ + { +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + USB_DeviceLpcIp3511ReleaseMaxPacketBuffer( + lpc3511IpState, epState->epPacketBuffer, + USB_LPC3511IP_GET_MULTIPLE_OF_64(epState->stateUnion.stateBitField.maxPacketSize) * 2U); +#else + USB_DeviceLpcIp3511ReleaseMaxPacketBuffer(lpc3511IpState, epState->epPacketBuffer, + epState->stateUnion.stateBitField.maxPacketSize); +#endif + } + epState->epPacketBuffer = NULL; + } +#endif + + /* reset the double buffer */ + lpc3511IpState->registerBase->EPINUSE &= ~((uint32_t)(0x01UL << endpointIndex)); + /* Disable the endpoint */ + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, endpointIndex, 0U, USB_LPC3511IP_ENDPOINT_DISABLE_MASK, 0U, 0U); + /* Clear the max packet size */ + epState->stateUnion.stateBitField.maxPacketSize = 0U; + + return kStatus_USB_Success; +} + +/*! + * @brief Stall a specified endpoint. + * + * The function is used to stall a specified endpoint. + * Current transfer of the endpoint will be canceled and the specified endpoint will be stalled. + * + * @param lpc3511IpState Pointer of the controller state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceLpc3511IpEndpointStall(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, uint8_t ep) +{ + uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(ep); + usb_device_lpc3511ip_endpoint_state_struct_t *epState = + USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex); + + /* Set endpoint stall flag. */ + epState->stateUnion.stateBitField.stalled = 1U; + /* lpc3511IpState->registerBase->EPINUSE &= (~(0x01u << endpointIndex)); */ + /* stall the endpoint */ + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, endpointIndex, 0U, USB_LPC3511IP_ENDPOINT_STALL_MASK, 0U, 0U); + if ((ep & USB_ENDPOINT_NUMBER_MASK) != USB_CONTROL_ENDPOINT) + { + /* toggle reset for the toggle */ + epState->stateUnion.stateBitField.epControlDefault |= + ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT); + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT(lpc3511IpState, endpointIndex, 1U, USB_LPC3511IP_ENDPOINT_STALL_MASK, 0U, + 0U); + } +#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \ + (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))) +#else +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + if (0U != lpc3511IpState->hsInterruptIssue) + { +#endif + if ((0U != lpc3511IpState->controllerSpeed) && + (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType)) + { + lpc3511IpState->registerBase->DEVCMDSTAT |= + (USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK | USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK); + epState->stateUnion.stateBitField.epControlDefault &= + (~((USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK | USB_LPC3511IP_ENDPOINT_RFTV_MASK) >> + USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT)); + } +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + } +#endif +#endif +#endif + + /* cancel the transfer in the endpoint */ + (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, ep); + return kStatus_USB_Success; +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled. + * + * @param lpc3511IpState Pointer of the controller state structure. + * @param ep The endpoint address, Bit7, 0U - USB_OUT, 1U - USB_IN. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceLpc3511IpEndpointUnstall(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, uint8_t ep) +{ + uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(ep); + usb_device_lpc3511ip_endpoint_state_struct_t *epState = + USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex); + + /* Clear the endpoint stall state, the hardware resets the endpoint + * toggle to one for both directions when a setup token is received */ + epState->stateUnion.stateBitField.stalled = 0U; + + /* unstall the endpoint for double buffers */ + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(lpc3511IpState, endpointIndex, 0, (~USB_LPC3511IP_ENDPOINT_STALL_MASK)); + if ((ep & USB_ENDPOINT_NUMBER_MASK) != USB_CONTROL_ENDPOINT) + { + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND(lpc3511IpState, endpointIndex, 1, (~USB_LPC3511IP_ENDPOINT_STALL_MASK)); + + /* toggle reset for the toggle */ + epState->stateUnion.stateBitField.epControlDefault |= + ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT); +#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \ + (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))) +#else +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + if (0U != lpc3511IpState->hsInterruptIssue) + { +#endif + if ((0U != lpc3511IpState->controllerSpeed) && + (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType)) + { + epState->stateUnion.stateBitField.epControlDefault &= + (~((USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK | USB_LPC3511IP_ENDPOINT_RFTV_MASK) >> + USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT)); + } +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + } +#endif +#endif +#endif + } + + if (0U != epState->stateUnion.stateBitField.stallPrimed) + { + epState->stateUnion.stateBitField.stallPrimed = 0u; + (void)USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex); + } + /* cancel the transfer in the endpoint */ + (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, ep); + return kStatus_USB_Success; +} + +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled. + * + * @param lpc3511IpState Pointer of the controller state structure. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceLpc3511IpInterruptSuspend(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = (uint8_t *)NULL; + message.code = (uint8_t)kUSB_DeviceNotifySuspend; + message.length = 0U; + message.isSetup = 0U; + + /* Notify up layer the USB suspend signal detected. */ + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); + + return kStatus_USB_Success; +} + +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled. + * + * @param lpc3511IpState Pointer of the controller state structure. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceLpc3511IpInterruptResume(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = (uint8_t *)NULL; + message.code = (uint8_t)kUSB_DeviceNotifyResume; + message.length = 0U; + message.isSetup = 0U; + + /* Notify up layer the USB suspend signal detected. */ + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); + + return kStatus_USB_Success; +} +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) +/*! + * @brief Un-stall a specified endpoint. + * + * The function is used to un-stall a specified endpoint. + * Current transfer of the endpoint will be canceled and the specified endpoint will be un-stalled. + * + * @param lpc3511IpState Pointer of the controller state structure. + * + * @return A USB error code or kStatus_USB_Success. + */ +static usb_status_t USB_DeviceLpc3511IpInterruptLPMSleep(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = &lpc3511IpState->lpmRemoteWakeUp; + message.code = (uint8_t)kUSB_DeviceNotifyLPMSleep; + message.length = 0U; + message.isSetup = 0U; + + lpc3511IpState->lpmRemoteWakeUp = + (uint8_t)((lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_MASK) >> + USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_SHIFT); + + /* Notify up layer the USB suspend signal detected. */ + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); + + return kStatus_USB_Success; +} + +#endif +#endif + +/* need copy the data before the trasaction buffer is used again */ +static void USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + usb_device_lpc3511ip_endpoint_state_struct_t *epState, + uint32_t length, + uint8_t endpointIndex, + uint8_t odd) +{ + uint8_t *destBuffer; + uint8_t *sourceBuffer; + +#if ((defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY > 0U)) + /*control out doesn't support buffer toggle*/ + if (0U == endpointIndex) + { + odd = 0u; + } +#if USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER + if ((0U != epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed) && (length > 0U) && + ((endpointIndex & 0x01U) == 0U)) +#else + if ((0U != USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState)) && + (0U != epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed) && (length > 0U) && + ((endpointIndex & 0x01U) == 0U)) +#endif +#else + /* control data buffer align is used */ + if (((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT) && + (epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed) && (length > 0U) && + ((endpointIndex & 0x01u) == 0U)) +#endif + { +#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U)) + destBuffer = &(epState->transferBuffer[epState->transferDone - length]); +#else + destBuffer = &(epState->transferBuffer[epState->transferDone]); +#endif +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + sourceBuffer = epState->epPacketBuffer + + odd * USB_LPC3511IP_GET_MULTIPLE_OF_64(epState->stateUnion.stateBitField.maxPacketSize); +#else + sourceBuffer = epState->epPacketBuffer; +#endif + (void)memcpy(destBuffer, sourceBuffer, length); + } +} + +static uint32_t USB_DeviceLpc3511IpTokenUpdate(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + usb_device_lpc3511ip_endpoint_state_struct_t *epState, + uint8_t endpointIndex, + uint8_t changedOdd) +{ + uint32_t length; + uint8_t odd; + +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + if (0U != changedOdd) + { + odd = (uint8_t)epState->stateUnion.stateBitField.consumerOdd; + epState->stateUnion.stateBitField.consumerOdd ^= 1U; + epState->stateUnion.stateBitField.doubleBufferBusy--; + } + else +#endif + { + odd = 0U; + } + +/* for OUT packet, compute the actual packet size. */ +#if ((defined(FSL_FEATURE_USB_VERSION) && (FSL_FEATURE_USB_VERSION >= 200U)) || \ + (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U))) +#else + if ((endpointIndex & 0x01U) == 0x00u) /* OUT */ +#endif + { + /* get the transaction length */ + length = *(lpc3511IpState->epCommandStatusList + endpointIndex * 2U + odd); + +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + if (0U != lpc3511IpState->controllerSpeed) + { + length = + (length & USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_MASK) >> USB_LPC3511IPHS_ENDPOINT_BUFFER_NBYTES_SHIFT; + } + else +#endif + { + length = + (length & USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_MASK) >> USB_LPC3511IPFS_ENDPOINT_BUFFER_NBYTES_SHIFT; + } + length = epState->epBufferStatusUnion[odd].epBufferStatusField.transactionLength - length; + } +#if ((defined(FSL_FEATURE_USB_VERSION) && (FSL_FEATURE_USB_VERSION >= 200U)) || \ + (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U))) +#else + else /* for IN packet, if there is no error, the packet lenght is the primed length. */ + { + /* don't judge the actual packet size */ + length = epState->epBufferStatusUnion[odd].epBufferStatusField.transactionLength; + } +#endif + +#if !((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U)) + USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(lpc3511IpState, epState, length, endpointIndex, odd); +#endif + /* update the transferred length */ + epState->transferDone += length; + + return length; +} + +static void USB_DeviceLpc3511IpInterruptToken(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + uint8_t endpointIndex, + uint8_t isSetup, + uint32_t errorStatus) +{ + usb_device_callback_message_struct_t message; + uint32_t len = 0; + uint32_t length; + uint32_t remainLength; + usb_device_lpc3511ip_endpoint_state_struct_t *epState = + USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex); + +#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \ + (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))) +#else +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + if (0U != lpc3511IpState->hsInterruptIssue) + { +#endif + if ((0U != (epState->stateUnion.stateBitField.epControlDefault & + ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT))) && + (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType) && + (0U != lpc3511IpState->controllerSpeed) && + (0U != (lpc3511IpState->epCommandStatusList[epState->stateUnion.stateBitField.consumerOdd + + (((uint32_t)endpointIndex) * 2U)] & + USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK))) + { + if (0U == (lpc3511IpState->registerBase->EPTOGGLE & ((uint32_t)(0x01UL << endpointIndex)))) + { + uint32_t index; + length = 0U; + for (index = 0U; index < ((uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM) * 4U; ++index) + { + if ((0U != + (lpc3511IpState->epCommandStatusList[index] & USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK)) && + (USB_ENDPOINT_INTERRUPT == + lpc3511IpState->endpointState[index / 2U].stateUnion.stateBitField.endpointType)) + { + length++; + } + } + + if (length <= 1U) + { + lpc3511IpState->registerBase->DEVCMDSTAT &= + ~(USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK | USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK); + } + epState->stateUnion.stateBitField.epControlDefault &= + (~((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT)); +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + /* high-speed */ + epState->stateUnion.stateBitField.epControlDefault |= + ((USB_LPC3511IP_ENDPOINT_RFTV_MASK | USB_LPC3511IP_ENDPOINT_ENDPOINT_TYPE_MASK) >> + USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT); + (void)USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex); +#endif + } + return; + } +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + } +#endif +#endif +#endif + + if ((0U == isSetup) && (0U == epState->stateUnion.stateBitField.transferring)) + { + return; + } + if (0U != isSetup) + { + message.length = 8U; + message.buffer = (lpc3511IpState->setupData); + /* clear the primed control transactions */ + if (0U != (epState->stateUnion.stateBitField.transferring)) + { + epState->stateUnion.stateBitField.transferring = 0U; + if (0U != (lpc3511IpState->epCommandStatusList[0] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)) + { + (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, USB_CONTROL_ENDPOINT); + } + } + if (0U != (lpc3511IpState->endpointState[1].stateUnion.stateBitField.transferring)) + { + lpc3511IpState->endpointState[1].stateUnion.stateBitField.transferring = 0U; + if (0U != (lpc3511IpState->epCommandStatusList[2] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)) + { + (void)USB_DeviceLpc3511IpCancel(lpc3511IpState, (0x80u | USB_CONTROL_ENDPOINT)); + } + } + + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND( + lpc3511IpState, 0, 0, (~(USB_LPC3511IP_ENDPOINT_STALL_MASK | USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))); + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND( + lpc3511IpState, 1, 0, (~(USB_LPC3511IP_ENDPOINT_STALL_MASK | USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))); + + lpc3511IpState->registerBase->INTSTAT = 0x03u; /* clear interrupt */ + /* W1 to clear the setup flag */ + lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK; + } + else + { + length = 0U; +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + if (0U != (lpc3511IpState->epCommandStatusList[epState->stateUnion.stateBitField.consumerOdd + + (((uint32_t)endpointIndex) * 2U)] & + USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)) + { + return; + } +#else + if (0U != (lpc3511IpState->epCommandStatusList[endpointIndex * 2U] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK)) + { + return; + } +#endif + +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + if ((endpointIndex >> 1U) != USB_CONTROL_ENDPOINT) + { + len = USB_DeviceLpc3511IpTokenUpdate(lpc3511IpState, epState, endpointIndex, 1U); + length += len; + + if ((epState->stateUnion.stateBitField.doubleBufferBusy > 0U) && + (0U == (lpc3511IpState->epCommandStatusList[epState->stateUnion.stateBitField.consumerOdd + + (((uint32_t)endpointIndex) * 2U)] & + USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))) + { +#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U)) + USB_DeviceLpc3511IpDoPreviousTransactionMemcpy( + lpc3511IpState, epState, len, endpointIndex, + (uint8_t)(epState->stateUnion.stateBitField.consumerOdd ^ 1U)); +#endif + len = USB_DeviceLpc3511IpTokenUpdate(lpc3511IpState, epState, endpointIndex, 1U); + length += len; + } + } + else +#endif + { + length = USB_DeviceLpc3511IpTokenUpdate(lpc3511IpState, epState, endpointIndex, 0U); + len = length; + } + + /* update remaining length */ + remainLength = epState->transferLength - epState->transferDone; + + /* Whether the transfer is completed or not. + * The transfer is completed when one of the following conditions meet: + * 1. The remaining length is zero. + * 2. The length of current tansaction is not the multiple of max packet size. + */ + if ((length > 0U) && (0U == (length % epState->stateUnion.stateBitField.maxPacketSize)) && (remainLength > 0U)) + { + (void)USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex); +#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U)) + USB_DeviceLpc3511IpDoPreviousTransactionMemcpy( + lpc3511IpState, epState, len, endpointIndex, + (uint8_t)(epState->stateUnion.stateBitField.consumerOdd ^ 1U)); +#endif + return; + } + else + { + epState->stateUnion.stateBitField.transferring = 0U; + message.length = epState->transferDone; + message.buffer = epState->transferBuffer; + + /* process ZLT + * 1. IN endpoint; + * 2. transfer length is the multiple of max packet size. + */ + if ((0U != (endpointIndex & 0x01U)) && (0U != length) && + (0U == (length % epState->stateUnion.stateBitField.maxPacketSize))) + { +#if (defined USB_DEVICE_CONTROLLER_AUTO_CONTROL_TRANSFER_ZLP) && (USB_DEVICE_CONTROLLER_AUTO_CONTROL_TRANSFER_ZLP) + if ((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT) + { + temp = (void *)(&(lpc3511IpState->setupData[0])); + setupPacket = (usb_setup_struct_t *)temp; + /* + * Send ZLT transaction if setup transfer and the required length is longer than actual length + */ + if (USB_SHORT_FROM_LITTLE_ENDIAN(setupPacket->wLength) > epState->transferLength) + { + (void)USB_DeviceLpc3511IpEndpointPrime(lpc3511IpState, epState, 1U, NULL, 0U); + return; + } + } + else +#endif + if ((0U != epState->stateUnion.stateBitField.zlt)) + { + (void)USB_DeviceLpc3511IpEndpointPrime(lpc3511IpState, epState, endpointIndex, NULL, 0U); + return; + } + else + { + /*no action*/ + } + } + } + } + + message.isSetup = isSetup; + message.code = ((uint8_t)(endpointIndex >> 1) | (uint8_t)(((endpointIndex & 0x01U) << 0x07U))); + +#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U)) + USB_DeviceLpc3511IpDoPreviousTransactionMemcpy(lpc3511IpState, epState, len, endpointIndex, + (uint8_t)(epState->stateUnion.stateBitField.consumerOdd ^ 1U)); +#endif + /* Notify the up layer the controller status changed. */ + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); +} + +/*! + * @brief Handle the USB bus reset interrupt. + * + * The function is used to handle the USB bus reset interrupt. + * + * @param lpc3511IpState Pointer of the controller state structure. + * + */ +static void USB_DeviceLpc3511IpInterruptReset(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ + usb_device_callback_message_struct_t message; + + /* Set reset flag */ + lpc3511IpState->isResetting = 1U; + +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + if (0U != lpc3511IpState->controllerSpeed) + { + if (((lpc3511IpState->registerBase->DEVCMDSTAT & USBHSD_DEVCMDSTAT_Speed_MASK) >> + USBHSD_DEVCMDSTAT_Speed_SHIFT) == 0x02U) + { + lpc3511IpState->deviceSpeed = USB_SPEED_HIGH; + } + else if (((lpc3511IpState->registerBase->DEVCMDSTAT & USBHSD_DEVCMDSTAT_Speed_MASK) >> + USBHSD_DEVCMDSTAT_Speed_SHIFT) == 0x01U) + { + lpc3511IpState->deviceSpeed = USB_SPEED_FULL; + } + else + { + /*no action*/ + } + } + else +#endif + { + lpc3511IpState->deviceSpeed = USB_SPEED_FULL; + } + + message.buffer = (uint8_t *)NULL; + message.code = (uint8_t)kUSB_DeviceNotifyBusReset; + message.length = 0U; + message.isSetup = 0U; + /* Notify up layer the USB bus reset signal detected. */ + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); +} + +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE)) +/*! + * @brief Handle detach interrupt. + * + * The function is used to handle the detach interrupt. + * + * @param lpc3511IpState Pointer of the controller state structure. + * + */ +static void USB_DeviceLpc3511IpInterruptDetach(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = (uint8_t *)NULL; + message.code = (uint8_t)kUSB_DeviceNotifyDetach; + message.length = 0U; + message.isSetup = 0U; + + /* Notify up layer the USB VBUS falling signal detected. */ + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); +} + +/*! + * @brief Handle Attach interrupt. + * + * The function is used to handle the attach interrupt. + * + * @param lpc3511IpState Pointer of the controller state structure. + * + */ +static void USB_DeviceLpc3511IpInterruptAttach(usb_device_lpc3511ip_state_struct_t *lpc3511IpState) +{ + usb_device_callback_message_struct_t message; + + message.buffer = (uint8_t *)NULL; + message.code = (uint8_t)kUSB_DeviceNotifyAttach; + message.length = 0U; + message.isSetup = 0U; + + /* Notify up layer the USB VBUS rising signal detected. */ + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); +} +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) +/* The device dcd callback */ +static usb_hsdcd_status_t USB_DeviceLpcIp3511IsrHSDCDCallback(void *handle, uint32_t event, void *param) +{ + usb_hsdcd_status_t error = kStatus_hsdcd_Success; + usb_device_callback_message_struct_t message; + usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)handle; + + if (lpc3511IpState == NULL) + { + return kStatus_hsdcd_Error; + } + + /*messsgae buffer contain event information*/ + message.buffer = (uint8_t *)param; + message.length = 0U; + message.isSetup = 0U; + message.code = (uint8_t)kUSB_DeviceNotifyDcdDetectFinished; + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); + return error; +} + +void USB_DeviceLpcIp3511IsrDCDFunction(void *deviceHandle) +{ + struct usb_device_struct *handle = (struct usb_device_struct *)deviceHandle; + usb_device_lpc3511ip_state_struct_t *lpc3511IpState; + if (NULL == deviceHandle) + { + return; + } + lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)(handle->controllerHandle); + USB_HSDcdIsrFunction(lpc3511IpState->dcdHandle); +} +#endif +usb_status_t USB_DeviceLpc3511IpInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *controllerHandle) +{ + usb_device_lpc3511ip_state_struct_t *lpc3511IpState = NULL; +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) + uint32_t ip3511FsBases[] = USB_BASE_ADDRS; +#endif + uint32_t *endpointListArray[] = LPC_CONTROLLER_ENDPOINT_LIST_ARRAY; + +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + uint32_t hsdcd_base[] = USBHSDCD_BASE_ADDRS; + USBHSDCD_Type *base; + usb_hsdcd_config_struct_t dcdParamConfig; + usb_hsdcd_status_t dcdError = kStatus_hsdcd_Success; +#endif + + uint32_t ip3511HsBases[] = USBHSD_BASE_ADDRS; + if ((controllerId >= (uint8_t)kUSB_ControllerLpcIp3511Hs0) && + (controllerId <= (uint8_t)kUSB_ControllerLpcIp3511Hs1)) + { + if (((uint32_t)controllerId - (uint32_t)kUSB_ControllerLpcIp3511Hs0) >= + (sizeof(ip3511HsBases) / sizeof(uint32_t))) + { + return kStatus_USB_ControllerNotFound; + } + lpc3511IpState = &s_UsbDeviceLpc3511IpState[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 + + USB_DEVICE_CONFIG_LPCIP3511FS]; + lpc3511IpState->controlData = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 + + USB_DEVICE_CONFIG_LPCIP3511FS][CONTROL_TRANSFER_DATA_OFFSET]; + lpc3511IpState->setupData = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 + + USB_DEVICE_CONFIG_LPCIP3511FS][SETUP_TRANSFER_DATA_OFFSET]; + lpc3511IpState->zeroTransactionData = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 + + USB_DEVICE_CONFIG_LPCIP3511FS][ZERO_TRANSFER_DATA_OFFSET]; + /* set the endpoint list */ + lpc3511IpState->epCommandStatusList = + endpointListArray[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 + USB_DEVICE_CONFIG_LPCIP3511FS]; + /* get the ip base address */ + lpc3511IpState->registerBase = + (USB_LPC3511IP_Type *)ip3511HsBases[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0]; +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + base = (USBHSDCD_Type *)hsdcd_base[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0]; + dcdParamConfig.dcdCallback = USB_DeviceLpcIp3511IsrHSDCDCallback; + dcdParamConfig.dcdCallbackParam = (void *)lpc3511IpState; + dcdError = USB_HSDCD_Init(base, &dcdParamConfig, &lpc3511IpState->dcdHandle); + if (kStatus_hsdcd_Success != dcdError) + { + return kStatus_USB_Error; + } +#endif + } + else +#endif +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511FS)) && (USB_DEVICE_CONFIG_LPCIP3511FS > 0U)) + { + /* get the controller instance */ + if ((controllerId < (uint8_t)kUSB_ControllerLpcIp3511Fs0) || + ((controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0) >= (uint8_t)USB_DEVICE_CONFIG_LPCIP3511FS) || + (((uint32_t)controllerId - (uint32_t)kUSB_ControllerLpcIp3511Fs0) >= + (sizeof(ip3511FsBases) / sizeof(uint32_t)))) + { + return kStatus_USB_ControllerNotFound; + } + lpc3511IpState = &s_UsbDeviceLpc3511IpState[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0]; + lpc3511IpState->controlData = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0] + [CONTROL_TRANSFER_DATA_OFFSET]; + lpc3511IpState->setupData = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0] + [SETUP_TRANSFER_DATA_OFFSET]; + lpc3511IpState->zeroTransactionData = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0] + [ZERO_TRANSFER_DATA_OFFSET]; + /* set the endpoint list */ + lpc3511IpState->epCommandStatusList = endpointListArray[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0]; + /* get the ip base address */ + lpc3511IpState->registerBase = + (USB_LPC3511IP_Type *)ip3511FsBases[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0]; + } +#else + { + return kStatus_USB_ControllerNotFound; + } +#endif + + lpc3511IpState->controllerId = controllerId; +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + if ((lpc3511IpState->controllerId >= (uint8_t)kUSB_ControllerLpcIp3511Hs0) && + (lpc3511IpState->controllerId <= (uint8_t)kUSB_ControllerLpcIp3511Hs1)) + { + lpc3511IpState->controllerSpeed = 1U; +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + lpc3511IpState->hsInterruptIssue = ((Chip_GetVersion() == FSL_ROM_VERSION_1B) ? 0U : 1U); +#endif + } + else + { + lpc3511IpState->controllerSpeed = 0U; + } +#endif + +#if ((defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY > 0U)) + /* this controller need max packet buffer copy */ + if (0U != USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState)) + { +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + /* fix coverity and misra 14.3 */ + if (controllerId >= (uint8_t)kUSB_ControllerLpcIp3511Hs0) + { +#if (USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER) + /* for allocating the max packet buffer */ + lpc3511IpState->epReservedBuffer = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0 + + USB_DEVICE_CONFIG_LPCIP3511FS][RESERVED_EP_DATA_OFFSET]; +#else + lpc3511IpState->epReservedBuffer = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0] + [RESERVED_EP_DATA_OFFSET]; +#endif + } + else +#endif + { + lpc3511IpState->epReservedBuffer = + (uint8_t *)&s_SetupAndEpReservedData[controllerId - (uint8_t)kUSB_ControllerLpcIp3511Fs0] + [RESERVED_EP_DATA_OFFSET]; + } + } + for (controllerId = 0; controllerId < ((USB_DEVICE_IP3511_BITS_FOR_RESERVED_BUFFER + 7U) / 8U); ++controllerId) + { + lpc3511IpState->epReservedBufferBits[controllerId] = 0U; + } +#endif + + /* disable the controller */ + lpc3511IpState->registerBase->DEVCMDSTAT &= + (~(USB_LPC3511IP_DEVCMDSTAT_DCON_MASK | USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK | + USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK)); + /* reset and enalbe the controller */ + USB_DeviceLpc3511IpSetDefaultState(lpc3511IpState); + /* enable USB */ + lpc3511IpState->registerBase->DEVCMDSTAT |= (USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#else + | USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK +#endif + ); +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) + lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK; + lpc3511IpState->registerBase->LPM |= USB_LPC3511IP_USB_LPM_HIRD_SW(4); + lpc3511IpState->registerBase->DEVCMDSTAT &= ~(USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK); +#endif + lpc3511IpState->deviceHandle = handle; + *controllerHandle = lpc3511IpState; + + return kStatus_USB_Success; +} + +usb_status_t USB_DeviceLpc3511IpDeinit(usb_device_controller_handle controllerHandle) +{ + usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle; + uint32_t usbAddress; + usb_status_t status = kStatus_USB_Success; + if (controllerHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + /* Clear all interrupt flags. */ + lpc3511IpState->registerBase->INTSTAT = (USB_LPC3511IP_INTSTAT_DEV_INT_MASK | USB_LPC3511IP_INTSTAT_FRAME_INT_MASK | + USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK); + /* Disable all interrupts. */ + lpc3511IpState->registerBase->INTEN = 0U; + /* Clear device address. */ + usbAddress = 0U; + status = USB_DeviceLpc3511IpControlPreSetDeviceAddress(controllerHandle, &usbAddress); + if (kStatus_USB_Success == status) + { + /*no action, just for misra4.7*/ + } +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) + lpc3511IpState->registerBase->DEVCMDSTAT &= ~USB_LPC3511IP_DEVCMDSTAT_LPM_SUP_MASK; +#endif + /* disable the controller */ + lpc3511IpState->registerBase->DEVCMDSTAT &= + (~(USB_LPC3511IP_DEVCMDSTAT_DCON_MASK | USB_LPC3511IP_DEVCMDSTAT_DEV_EN_MASK | + USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK)); +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + (void)USB_HSDCD_Deinit(lpc3511IpState->dcdHandle); +#endif + + return status; +} + +static usb_status_t USB_DeviceLpc3511IpGetActualBufferAndPrime(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + usb_device_lpc3511ip_endpoint_state_struct_t *epState, + uint8_t endpointIndex, + uint8_t changedOdd) +{ + uint8_t *destBuffer; + uint8_t *actualBuffer; + uint32_t length; + uint8_t odd; + uint8_t index; + +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + if (0U != changedOdd) + { + odd = (uint8_t)epState->stateUnion.stateBitField.producerOdd; + } + else +#endif + { + odd = 0; + } + actualBuffer = epState->transferBuffer + epState->transferPrimedLength; + length = epState->transferLength - epState->transferPrimedLength; + /* Data length needs to less than max packet size. */ + if (length > epState->stateUnion.stateBitField.maxPacketSize) + { + length = epState->stateUnion.stateBitField.maxPacketSize; + } + + epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed = 0; + + index = (endpointIndex & 0x01u); /* index mean IN endpoint here */ + if (length > 0U) + { +#if ((defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY > 0U)) +/* if all the enabled IP support the reserved buffer, then don't need the judgement. */ +#if (!USB_DEVICE_IP3511_ALL_IP_SUPPORT_RESERVED_BUFFER) +#define USB_DEVICE_IP3511_NEED_CHECK_BUFFER (1u) + /* lengt > 0 && ((buffer not align with 64) || (buffer is not in the deticated ram))) */ + if (USB_DeviceLpcIp3511MaxPacketNeedCopy(lpc3511IpState)) +#endif +#else +#define USB_DEVICE_IP3511_NEED_CHECK_BUFFER (1u) + /* align the buffer for control transfer */ + if (((endpointIndex >> 1U) == USB_CONTROL_ENDPOINT)) +#endif + { +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if ((defined(FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) && (FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) + uint32_t bufferValue = (uint32_t)actualBuffer; +#if ((defined(__SAUREGION_PRESENT)) && (__SAUREGION_PRESENT > 0U)) + bufferValue &= (0xEFFFFFFFu); /* bit28 is the secure address label */ +#endif +#endif +#endif + /* not 64 bytes align || not in the dedicated ram || ( OUT && not mutiple of 4 ) */ + if ((((uint32_t)actualBuffer & 0x0000003FU) != 0U) || +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if ((defined(FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) && (FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) + ( +#endif +#endif + (((uint32_t)actualBuffer & 0xFFC00000U) != + (lpc3511IpState->registerBase->DATABUFSTART & 0xFFC00000U)) +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if ((defined(FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) && (FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) + + || ((0U != lpc3511IpState->controllerSpeed) && + ((bufferValue < (uint32_t)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS) || + (bufferValue > + ((uint32_t)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS + (uint32_t)FSL_FEATURE_USBHSD_USB_RAM)))) +#endif +#endif +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if ((defined(FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) && (FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)) + ) +#endif +#endif +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + || ((0U != lpc3511IpState->controllerSpeed) && (0U == index) && + (length != epState->stateUnion.stateBitField.maxPacketSize))) +#else + ) +#endif + { + epState->epBufferStatusUnion[odd].epBufferStatusField.epPacketCopyed = 1U; +/* usb copy buffer for this packet */ +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + destBuffer = + (uint8_t *)(epState->epPacketBuffer + (odd * USB_LPC3511IP_GET_MULTIPLE_OF_64( + epState->stateUnion.stateBitField.maxPacketSize))); +#else + destBuffer = (uint8_t *)(epState->epPacketBuffer); +#endif + if (0U != index) /* USB_IN */ + { + (void)memcpy(destBuffer, actualBuffer, length); + } + else + { +#if ((defined(FSL_FEATURE_USB_VERSION) && (FSL_FEATURE_USB_VERSION >= 200U)) || \ + (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U))) +#else + length = epState->stateUnion.stateBitField.maxPacketSize; +#endif + } + actualBuffer = destBuffer; + } + } +#if (defined USB_DEVICE_IP3511_NEED_CHECK_BUFFER) && (USB_DEVICE_IP3511_NEED_CHECK_BUFFER) + else /* cannot do memory copy */ + { + /* not 64 bytes align || not in the dedicated ram || ( OUT && HS && not mutiple of 4 ) */ + if ((((uint32_t)actualBuffer & 0x0000003FU) != 0U) || + (((uint32_t)actualBuffer & 0xFFC00000U) != (lpc3511IpState->registerBase->DATABUFSTART & 0xFFC00000U)) +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + || ((0U != lpc3511IpState->controllerSpeed) && (0U == index) && ((length & 0x00000003u) != 0U))) +#else + ) +#endif + { + return kStatus_USB_Error; + } + } +#endif + } + + /* Send/Receive data when the device is not resetting. */ + if (0U == lpc3511IpState->isResetting) + { + return USB_DeviceLpc3511IpEndpointPrime(lpc3511IpState, epState, endpointIndex, actualBuffer, length); + } + else + { + return kStatus_USB_Error; + } +} +static usb_status_t USB_DeviceLpc3511IpTransaction(usb_device_lpc3511ip_state_struct_t *lpc3511IpState, + usb_device_lpc3511ip_endpoint_state_struct_t *epState, + uint8_t endpointIndex) +{ + usb_status_t status = kStatus_USB_Error; + OSA_SR_ALLOC(); + +#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \ + (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))) +#else +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + if (lpc3511IpState->hsInterruptIssue) + { +#endif + /* high-speed */ + if ((0U != (epState->stateUnion.stateBitField.epControlDefault & + ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT))) && + (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType) && + (0U != lpc3511IpState->controllerSpeed)) + { + /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */ + OSA_ENTER_CRITICAL(); + + lpc3511IpState->registerBase->DEVCMDSTAT |= + (USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AO_MASK | USB_LPC3511IP_DEVCMDSTAT_INTONNAK_AI_MASK); + +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT( + lpc3511IpState, endpointIndex, epState->stateUnion.stateBitField.producerOdd, + (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT) | + (epState->stateUnion.stateBitField.stalled << USB_LPC3511IP_ENDPOINT_STALL_SHIFT), + 0U, (uint32_t)lpc3511IpState->zeroTransactionData); +#else + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT( + lpc3511IpState, endpointIndex, 0, + (epState->stateUnion.stateBitField.epControlDefault << USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT) | + (epState->stateUnion.stateBitField.stalled << USB_LPC3511IP_ENDPOINT_STALL_SHIFT), + 0U, (uint32_t)lpc3511IpState->zeroTransactionData); +#endif + /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */ + OSA_EXIT_CRITICAL(); + return kStatus_USB_Success; + } +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + } +#endif +#endif +#endif + + /* Enter critical */ + OSA_ENTER_CRITICAL(); + if (0U != epState->stateUnion.stateBitField.stalled) + { + if ((endpointIndex >> 1U) != USB_ENDPOINT_CONTROL) + { + epState->stateUnion.stateBitField.stallPrimed = 1u; + status = kStatus_USB_Success; + } + status = kStatus_USB_Error; + OSA_EXIT_CRITICAL(); + return status; + } + OSA_EXIT_CRITICAL(); + + /* 1. transfer size is 0; 2. All are primed */ + if ((epState->transferLength <= epState->transferPrimedLength) && (epState->transferLength != 0U)) + { + return kStatus_USB_Success; + } +#if (defined USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) && (USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE) + if ((endpointIndex >> 1U) != USB_CONTROL_ENDPOINT) + { + /* disable endpoint interrupts, users can use NVIC to disable/enable the USB interrupt to improve the system + * performance */ + OSA_ENTER_CRITICAL(); + /* lpc3511IpState->registerBase->INTEN &= (uint32_t)(~(USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK)); */ +#if ((defined(USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER)) && (USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER > 0U)) + /* for out endpoint,only use buffer toggle, disable prime double buffer at the same time*/ + /*host send data less than maxpacket size and in endpoint prime length more more than maxpacketsize, there will + * be state mismtach*/ + if (0U == (endpointIndex & 0x1U)) + { + status = USB_DeviceLpc3511IpGetActualBufferAndPrime(lpc3511IpState, epState, endpointIndex, 1U); + } + else +#endif + { + do + { + status = USB_DeviceLpc3511IpGetActualBufferAndPrime(lpc3511IpState, epState, endpointIndex, 1U); + if (status != kStatus_USB_Success) + { + break; + } + } while ((epState->transferLength > epState->transferPrimedLength) && + (epState->stateUnion.stateBitField.doubleBufferBusy < 2U)); + } + /* enable endpoint interrupt again, users can use NVIC to disable/enable the USB interrupt to improve the system + * performance */ + OSA_EXIT_CRITICAL(); + } + else +#endif + { + status = USB_DeviceLpc3511IpGetActualBufferAndPrime(lpc3511IpState, epState, endpointIndex, 0U); + } + return status; +} + +usb_status_t USB_DeviceLpc3511IpSend(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle; + uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(endpointAddress); + usb_device_lpc3511ip_endpoint_state_struct_t *epState = + USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex); + + if (1U == epState->stateUnion.stateBitField.transferring) + { + return kStatus_USB_Error; + } + + /* Save the transfer information */ + epState->transferDone = 0U; + epState->transferBuffer = buffer; + epState->transferLength = length; + epState->transferPrimedLength = 0U; + + return USB_DeviceLpc3511IpTransaction(lpc3511IpState, epState, endpointIndex); + +/* prime the control setup transfer if it is control in endpoint and data length is zero + * For IP3511 there is no need to prime, the buffer is always in the command/status list + */ +#if 0 + if ((0U == length) && (USB_CONTROL_ENDPOINT == (endpointAddress & USB_ENDPOINT_NUMBER_MASK))) + { + USB_DeviceLpc3511IpPrimeNextSetup(lpc3511IpState); + } +#endif +} + +usb_status_t USB_DeviceLpc3511IpRecv(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length) +{ + return USB_DeviceLpc3511IpSend(controllerHandle, endpointAddress, buffer, length); +} + +usb_status_t USB_DeviceLpc3511IpCancel(usb_device_controller_handle controllerHandle, uint8_t ep) +{ + /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */ + OSA_SR_ALLOC(); + + usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle; + usb_device_callback_message_struct_t message; + uint8_t endpointIndex = USB_LPC3511IP_ENDPOINT_DES_INDEX(ep); + usb_device_lpc3511ip_endpoint_state_struct_t *epState = + USB_DeviceLpc3511IpGetEndpointStateStruct(lpc3511IpState, endpointIndex); + + /* disable endpoint interrupts, users can use NVIC to disable/enable the USB interrupt to improve the system + * performance */ + OSA_ENTER_CRITICAL(); + /* Cancel the transfer and notify the up layer when the endpoint is busy. */ + if ((0U != epState->stateUnion.stateBitField.transferring) +#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \ + (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))) +#else +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + || ( +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + (0U != lpc3511IpState->hsInterruptIssue) && +#endif + (0U != (epState->stateUnion.stateBitField.epControlDefault & + ((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT))) && + (USB_ENDPOINT_INTERRUPT == epState->stateUnion.stateBitField.endpointType) && + (0U != lpc3511IpState->controllerSpeed) && + (0U != (lpc3511IpState->epCommandStatusList[epState->stateUnion.stateBitField.consumerOdd + + (((uint32_t)endpointIndex) * 2U)] & + USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK)) && + (0U == (lpc3511IpState->registerBase->EPTOGGLE & ((uint32_t)(0x01UL << endpointIndex))))) +#endif +#endif + ) + { +#if (defined(FSL_FEATURE_USBHSD_VERSION) && (FSL_FEATURE_USBHSD_VERSION >= 300U)) && \ + (!(defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK))) +#else +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + if (0U != lpc3511IpState->hsInterruptIssue) + { +#endif + epState->stateUnion.stateBitField.epControlDefault &= + (~((USB_LPC3511IP_ENDPOINT_TOGGLE_RESET_MASK) >> USB_LPC3511IP_ENDPOINT_CONFIGURE_BITS_SHIFT)); +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + } +#endif +#endif +#endif + if ((lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DCON_MASK) != 0U) + { + while (1U == 1U) + { + if ((lpc3511IpState->epCommandStatusList[(uint32_t)endpointIndex * 2U + ((lpc3511IpState->registerBase->EPINUSE & + (((uint32_t)0x00000001U << endpointIndex))) >> + endpointIndex)] & + USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U) + { + /* cancel the transfer in the endpoint command/status */ + lpc3511IpState->registerBase->EPSKIP |= ((uint32_t)0x00000001U << endpointIndex); + while (((lpc3511IpState->registerBase->EPSKIP & ((uint32_t)0x00000001U << endpointIndex)) != 0U) && + ((lpc3511IpState + ->epCommandStatusList[(uint32_t)endpointIndex * 2U + ((lpc3511IpState->registerBase->EPINUSE & + (((uint32_t)0x00000001U << endpointIndex))) >> + endpointIndex)] & + USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U)) + { + } + if ((lpc3511IpState->registerBase->EPSKIP & ((uint32_t)0x00000001U << endpointIndex)) != 0U) + { + lpc3511IpState->registerBase->EPSKIP &= (~((uint32_t)0x00000001U << endpointIndex)); + } + } + + if (((lpc3511IpState->epCommandStatusList[endpointIndex * 2U] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U) || + ((lpc3511IpState->epCommandStatusList[endpointIndex * 2U + 1U] & USB_LPC3511IP_ENDPOINT_ACTIVE_MASK) != 0U)) + { + if ((lpc3511IpState->registerBase->EPINUSE & (((uint32_t)0x00000001U << endpointIndex))) != 0U) + { + lpc3511IpState->registerBase->EPINUSE &= ~((uint32_t)0x00000001U << endpointIndex); + } + else + { + lpc3511IpState->registerBase->EPINUSE |= ((uint32_t)0x00000001U << endpointIndex); + } + } + else + { + break; + } + } + } + else + { + /* Make sure the device is detached from host, host will not send any transaction to device. + * Then the endpoint status entry can be modified directly by software. + */ + lpc3511IpState->epCommandStatusList[endpointIndex * 2U] = USB_LPC3511IP_ENDPOINT_DISABLE_MASK; + lpc3511IpState->epCommandStatusList[endpointIndex * 2U + 1U] = USB_LPC3511IP_ENDPOINT_DISABLE_MASK; + } + + epState->stateUnion.stateBitField.transferring = 0U; + epState->stateUnion.stateBitField.producerOdd = + ((lpc3511IpState->registerBase->EPINUSE & ((uint32_t)((uint32_t)0x00000001U << endpointIndex))) >> endpointIndex); + epState->stateUnion.stateBitField.consumerOdd = + ((lpc3511IpState->registerBase->EPINUSE & ((uint32_t)((uint32_t)0x00000001U << endpointIndex))) >> endpointIndex); + /* clear interrupt status, enable endpoint interrupt again */ + lpc3511IpState->registerBase->INTSTAT = ((uint32_t)0x00000001U << endpointIndex); + + /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */ + OSA_EXIT_CRITICAL(); + + message.length = USB_UNINITIALIZED_VAL_32; + message.buffer = epState->transferBuffer; + message.code = ep; + message.isSetup = 0U; + (void)USB_DeviceNotificationTrigger(lpc3511IpState->deviceHandle, &message); + } + else + { + /* users can use NVIC to disable/enable the USB interrupt to improve the system performance */ + OSA_EXIT_CRITICAL(); + } + return kStatus_USB_Success; +} + +/*seperate this function from USB_DeviceLpc3511IpControl for misra17.2 recursive */ +static usb_status_t USB_DeviceLpc3511IpControlPreSetDeviceAddress(usb_device_controller_handle controllerHandle, + void *param) +{ + usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle; + usb_status_t error = kStatus_USB_Error; + uint32_t tmp32Value; + uint8_t tmp8Value; + if (NULL != param) + { + tmp8Value = *((uint8_t *)param); + tmp32Value = lpc3511IpState->registerBase->DEVCMDSTAT; + tmp32Value &= (~USB_LPC3511IP_DEVCMDSTAT_DEV_ADDR_MASK); + tmp32Value |= ((uint32_t)tmp8Value & USB_LPC3511IP_DEVCMDSTAT_DEV_ADDR_MASK); + lpc3511IpState->registerBase->DEVCMDSTAT = tmp32Value; + error = kStatus_USB_Success; + } + return error; +} + +usb_status_t USB_DeviceLpc3511IpControl(usb_device_controller_handle controllerHandle, + usb_device_control_type_t type, + void *param) +{ + usb_device_lpc3511ip_state_struct_t *lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)controllerHandle; + usb_status_t error = kStatus_USB_Error; + uint32_t tmp32Value; + uint8_t tmp8Value; +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + struct usb_device_struct *deviceHandle; +#endif + usb_device_lpc3511ip_endpoint_state_struct_t *epState; + + if (controllerHandle == NULL) + { + return kStatus_USB_InvalidHandle; + } + +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + deviceHandle = (struct usb_device_struct *)lpc3511IpState->deviceHandle; +#endif + + switch (type) + { + case kUSB_DeviceControlRun: + lpc3511IpState->registerBase->DEVCMDSTAT |= (USB_LPC3511IP_DEVCMDSTAT_DCON_MASK); + lpc3511IpState->registerBase->DEVCMDSTAT &= ~(USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK); + break; + + case kUSB_DeviceControlStop: + lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK; + lpc3511IpState->registerBase->DEVCMDSTAT &= (~USB_LPC3511IP_DEVCMDSTAT_DCON_MASK); + break; + + case kUSB_DeviceControlEndpointInit: + if (NULL != param) + { + error = USB_DeviceLpc3511IpEndpointInit(lpc3511IpState, (usb_device_endpoint_init_struct_t *)param); + } + break; + + case kUSB_DeviceControlEndpointDeinit: + if (NULL != param) + { + tmp8Value = *((uint8_t *)param); + error = USB_DeviceLpc3511IpEndpointDeinit(lpc3511IpState, tmp8Value); + } + break; + + case kUSB_DeviceControlEndpointStall: + if (NULL != param) + { + tmp8Value = *((uint8_t *)param); + error = USB_DeviceLpc3511IpEndpointStall(lpc3511IpState, tmp8Value); + } + break; + + case kUSB_DeviceControlEndpointUnstall: + if (NULL != param) + { + tmp8Value = *((uint8_t *)param); + error = USB_DeviceLpc3511IpEndpointUnstall(lpc3511IpState, tmp8Value); + } + break; + + case kUSB_DeviceControlGetDeviceStatus: + if (NULL != param) + { + *((uint16_t *)param) = + (USB_DEVICE_CONFIG_SELF_POWER << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT)) +#if ((defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP)) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U)) + | ((uint16_t)(((uint32_t)deviceHandle->remotewakeup) + << (USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT))) +#endif + ; + error = kStatus_USB_Success; + } + break; + + case kUSB_DeviceControlGetEndpointStatus: + if (NULL != param) + { + usb_device_endpoint_status_struct_t *endpointStatus = (usb_device_endpoint_status_struct_t *)param; + + if ((((endpointStatus->endpointAddress) & USB_ENDPOINT_NUMBER_MASK)) < + (uint8_t)USB_DEVICE_IP3511_ENDPOINTS_NUM) + { + epState = USB_DeviceLpc3511IpGetEndpointStateStruct( + lpc3511IpState, USB_LPC3511IP_ENDPOINT_DES_INDEX(endpointStatus->endpointAddress)); + endpointStatus->endpointStatus = + (uint16_t)((epState->stateUnion.stateBitField.stalled == 1U) ? kUSB_DeviceEndpointStateStalled : + kUSB_DeviceEndpointStateIdle); + error = kStatus_USB_Success; + } + } + break; + + case kUSB_DeviceControlPreSetDeviceAddress: + error = USB_DeviceLpc3511IpControlPreSetDeviceAddress(controllerHandle, param); + if (kStatus_USB_Success == error) + { + /*no action, just for misra4.7*/ + } + break; + + case kUSB_DeviceControlSetDeviceAddress: + error = kStatus_USB_Success; + break; + + case kUSB_DeviceControlGetSynchFrame: + break; + +#if defined(USB_DEVICE_CONFIG_REMOTE_WAKEUP) && (USB_DEVICE_CONFIG_REMOTE_WAKEUP > 0U) + case kUSB_DeviceControlResume: + /* todo: turn on USB clock and enable the USB clock source */ + lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK; + lpc3511IpState->registerBase->DEVCMDSTAT &= ~USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK; + while (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK)) + { + } + /* the W1C bits */ + lpc3511IpState->registerBase->DEVCMDSTAT &= + ~(USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK | USB_LPC3511IP_DEVCMDSTAT_INTERRUPT_WC_MASK); + error = kStatus_USB_Success; + break; +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) + case kUSB_DeviceControlSleepResume: + /* todo: turn on USB clock and enable the USB clock source */ + lpc3511IpState->registerBase->DEVCMDSTAT |= USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK; + lpc3511IpState->registerBase->DEVCMDSTAT &= ~USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK; + while (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK)) + { + __NOP(); + } + /* the W1C bits */ + lpc3511IpState->registerBase->DEVCMDSTAT &= + ~(USB_LPC3511IP_DEVCMDSTAT_FORCE_NEEDCLK_MASK | USB_LPC3511IP_DEVCMDSTAT_INTERRUPT_WC_MASK); + error = kStatus_USB_Success; + break; +#endif + case kUSB_DeviceControlGetRemoteWakeUp: + *((uint8_t *)param) = + (uint8_t)((lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_MASK) >> + USB_LPC3511IP_DEVCMDSTAT_LPM_REWP_SHIFT); + break; +#endif /* USB_DEVICE_CONFIG_REMOTE_WAKEUP */ + + case kUSB_DeviceControlSetDefaultStatus: + for (tmp32Value = 0U; tmp32Value < (uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM; tmp32Value++) + { + (void)USB_DeviceLpc3511IpEndpointDeinit(lpc3511IpState, (uint8_t)(tmp32Value | (USB_IN << 0x07U))); + (void)USB_DeviceLpc3511IpEndpointDeinit(lpc3511IpState, (uint8_t)(tmp32Value | (USB_OUT << 0x07U))); + } + USB_DeviceLpc3511IpSetDefaultState(lpc3511IpState); + error = kStatus_USB_Success; + break; + + case kUSB_DeviceControlGetSpeed: + if (NULL != param) + { + *((uint8_t *)param) = lpc3511IpState->deviceSpeed; + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlGetOtgStatus: + break; + case kUSB_DeviceControlSetOtgStatus: + break; +#if (defined(USB_DEVICE_CONFIG_USB20_TEST_MODE) && (USB_DEVICE_CONFIG_USB20_TEST_MODE > 0U)) + case kUSB_DeviceControlSetTestMode: + if (NULL != param) + { + tmp8Value = *((uint8_t *)param); +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + lpc3511IpState->registerBase->DEVCMDSTAT |= + ((uint32_t)(tmp8Value) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT); +#endif + error = kStatus_USB_Success; + } + break; +#endif +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + case kUSB_DeviceControlDcdEnable: + if (kStatus_hsdcd_Success == USB_HSDCD_Control(lpc3511IpState->dcdHandle, kUSB_DeviceHSDcdEnable, NULL)) + { + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlDcdDisable: + if (kStatus_hsdcd_Success == USB_HSDCD_Control(lpc3511IpState->dcdHandle, kUSB_DeviceHSDcdDisable, NULL)) + { + error = kStatus_USB_Success; + } + break; + case kUSB_DeviceControlUpdateHwTick: + /*udpate 1ms time tick*/ + error = kStatus_USB_Success; + break; + +#endif + default: + /*no action*/ + break; + } + + return error; +} + +void USB_DeviceLpcIp3511IsrFunction(void *deviceHandle) +{ + struct usb_device_struct *handle = (struct usb_device_struct *)deviceHandle; + usb_device_lpc3511ip_state_struct_t *lpc3511IpState; + uint32_t interruptStatus; + uint32_t usbErrorCode; + uint32_t devState; + + if (NULL == deviceHandle) + { + return; + } + + lpc3511IpState = (usb_device_lpc3511ip_state_struct_t *)(handle->controllerHandle); + /* get and clear interrupt status */ + interruptStatus = lpc3511IpState->registerBase->INTSTAT; + lpc3511IpState->registerBase->INTSTAT = interruptStatus; + interruptStatus &= lpc3511IpState->registerBase->INTEN; + + usbErrorCode = (lpc3511IpState->registerBase->INFO & USB_LPC3511IP_INFO_ERR_CODE_MASK); + + /* device status change interrupt */ + if (0U != (interruptStatus & USB_LPC3511IP_INTSTAT_DEV_INT_MASK)) + { + /* get and clear device state change status */ + devState = lpc3511IpState->registerBase->DEVCMDSTAT; + devState &= ~(USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK); + lpc3511IpState->registerBase->DEVCMDSTAT = (devState | USB_LPC3511IP_DEVCMDSTAT_INTERRUPT_WC_MASK); + + /* For HS: there is interrupt with DEV_INT=1, OTG_C=1 and ADPPROBE=1 when vbus rising. + * For FS: there is no interrupt when vbus rising. The only way is: check the VBUS_DEBOUNCED in the DRES_C + * interrupt with DCON set. + */ +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE)) + if ((0U == lpc3511IpState->deviceState) && + ((0U != (devState & USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)) +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + || ((0U != (lpc3511IpState->registerBase->LPM & USB_LPC3511IP_USB_LPM_ADPPROBE_MASK)) && + (1U == lpc3511IpState->controllerSpeed)) +#endif + )) + { +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if ((defined(USB_DEVICE_IP3511HS_LPM_ADPPROBE_ATTACH_DEBOUNCE_COUNT)) && \ + (USB_DEVICE_IP3511HS_LPM_ADPPROBE_ATTACH_DEBOUNCE_COUNT > 0U)) + /* add one little debounce for HS's attach detection because ADPPROBE is undebounced value */ + uint32_t debounceCount = USB_DEVICE_IP3511HS_LPM_ADPPROBE_ATTACH_DEBOUNCE_COUNT; + if (1U == lpc3511IpState->controllerSpeed) + { + while ((0U != debounceCount) && (0U == (devState & USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK))) + { + if (0U == (lpc3511IpState->registerBase->LPM & USB_LPC3511IP_USB_LPM_ADPPROBE_MASK)) + { + break; + } + debounceCount--; + } + } + + if ((debounceCount == 0U) || (0U != (devState & USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK))) +#endif +#endif + { + lpc3511IpState->deviceState = 1U; + USB_DeviceLpc3511IpInterruptAttach(lpc3511IpState); +#if (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) && \ + (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) + (void)USB_HSDCD_Control(lpc3511IpState->dcdHandle, kUSB_DeviceHSDcdRun, NULL); +#endif + } + } + /* For HS: there is interrupt with DEV_INT=1, OTG_C=1 and ADPPROBE=0 when vbus falling. + * For HS and FS: there is interrupt when vbus falling if DCON is set. + */ + else if ((1U == lpc3511IpState->deviceState) && + (((0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DCON_MASK)) && + (0U == (devState & USB_LPC3511IP_DEVCMDSTAT_VBUS_DEBOUNCED_MASK))) +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + || ((0U == (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DCON_MASK)) && + (0U == (lpc3511IpState->registerBase->LPM & USB_LPC3511IP_USB_LPM_ADPPROBE_MASK)) && + (1U == lpc3511IpState->controllerSpeed)) +#endif + )) + { +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) +#if ((defined USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE) && (USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE > 0U)) + uint32_t delay = 100000U; +#endif +#endif +#endif + lpc3511IpState->deviceState = 0U; +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) +#if ((defined USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE) && (USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE > 0U)) + /* wait at least 125us to let the host to detect the detach */ + USB_PhyDeviceForceEnterFSMode(lpc3511IpState->controllerId, 1); + while (delay--) + { + __NOP(); + } + USB_PhyDeviceForceEnterFSMode(lpc3511IpState->controllerId, 0); +#endif +#endif +#endif + USB_DeviceLpc3511IpInterruptDetach(lpc3511IpState); + } + else + { + /*no action*/ + } +#endif + + /* reset change */ + if (0U != (devState & USB_LPC3511IP_DEVCMDSTAT_DRES_C_MASK)) + { + USB_DeviceLpc3511IpInterruptReset(lpc3511IpState); + } + +/* Suspend/Resume */ +#if ((defined(USB_DEVICE_CONFIG_LOW_POWER_MODE)) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) + if (0U != (devState & USB_LPC3511IP_DEVCMDSTAT_DSUS_C_MASK)) + { + if (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_DSUS_MASK)) + { + (void)USB_DeviceLpc3511IpInterruptSuspend(lpc3511IpState); + } +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) + else if (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_LPM_SUS_MASK)) + { + (void)USB_DeviceLpc3511IpInterruptLPMSleep(lpc3511IpState); + } +#endif + else + { + (void)USB_DeviceLpc3511IpInterruptResume(lpc3511IpState); + } + } + +#endif + +#if 0U /* some soc don't support this bit, need check according to the feature macro */ + /* OTG Status change */ + if (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_OTG_C_MASK) + { + } +#endif + } + + /* endpoint transfers interrupt */ + if (0U != (interruptStatus & USB_LPC3511IP_MAX_PHY_ENDPOINT_MASK)) + { + devState = 0; /* devState means index here */ + if (0U != (interruptStatus & 0x01U)) /* control OUT */ + { + if (0U != (lpc3511IpState->registerBase->DEVCMDSTAT & USB_LPC3511IP_DEVCMDSTAT_SETUP_MASK)) + { + devState = 2U; + if ((lpc3511IpState->endpointState[0].stateUnion.stateBitField.stalled == 1U) || + (lpc3511IpState->endpointState[1].stateUnion.stateBitField.stalled == 1U)) + { + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND( + lpc3511IpState, 0, 0, + (~(USB_LPC3511IP_ENDPOINT_STALL_MASK | USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))); + USB_LPC3511IP_ENDPOINT_SET_ENDPOINT_AND( + lpc3511IpState, 1, 0, + (~(USB_LPC3511IP_ENDPOINT_STALL_MASK | USB_LPC3511IP_ENDPOINT_ACTIVE_MASK))); + lpc3511IpState->endpointState[0].stateUnion.stateBitField.stalled = 0U; + lpc3511IpState->endpointState[1].stateUnion.stateBitField.stalled = 0U; + } + + /* todo: setup token interrupt */ + USB_DeviceLpc3511IpInterruptToken(lpc3511IpState, 0U, 1, usbErrorCode); + } + } + + for (; devState < ((uint32_t)USB_DEVICE_IP3511_ENDPOINTS_NUM * 2U); ++devState) + { + /* check the endpoint interrupt */ + if (0U != (interruptStatus & (0x01UL << devState))) + { + USB_DeviceLpc3511IpInterruptToken(lpc3511IpState, (uint8_t)devState, 0U, usbErrorCode); + } + } + } + +#if 0U + if (interruptStatus & USB_LPC3511IP_INTSTAT_FRAME_INT_MASK) + { + } +#endif +} + +#endif diff --git a/zephyr/middleware/usb/device/usb_device_lpcip3511.h b/zephyr/middleware/usb/device/usb_device_lpcip3511.h new file mode 100644 index 000000000..c285e6b88 --- /dev/null +++ b/zephyr/middleware/usb/device/usb_device_lpcip3511.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_DEVICE_LPC3511IP_H__ +#define __USB_DEVICE_LPC3511IP_H__ + +#include "fsl_device_registers.h" + +/*! + * @addtogroup usb_device_controller_lpcip3511_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The reserved buffer size, the buffer is for the memory copy if the application transfer buffer is + ((not 64 bytes alignment) || (not in the same 64K ram) || (HS && OUT && not multiple of 4)) */ +#define USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE (5U * 1024U) +/*! @brief Use one bit to represent one reserved 64 bytes to allocate the buffer by uint of 64 bytes. */ +#define USB_DEVICE_IP3511_BITS_FOR_RESERVED_BUFFER ((USB_DEVICE_IP3511_ENDPOINT_RESERVED_BUFFER_SIZE + 63U) / 64U) +/*! @brief How many IPs support the reserved buffer */ +#define USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY (USB_DEVICE_CONFIG_LPCIP3511FS + USB_DEVICE_CONFIG_LPCIP3511HS) +/*! @brief Prime all the double endpoint buffer at the same time, if the transfer length is larger than max packet size. + */ +#define USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE (1u) +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#define USB_LPC3511IP_Type USBHSD_Type +#define USB_DEVICE_IP3511_ENDPOINTS_NUM FSL_FEATURE_USBHSD_EP_NUM +#else +#define USB_LPC3511IP_Type USB_Type +#define USB_DEVICE_IP3511_ENDPOINTS_NUM FSL_FEATURE_USB_EP_NUM +#endif + +/* for out endpoint,only use buffer toggle, disable prime double buffer at the same time*/ +/*host send data less than maxpacket size and in endpoint prime length more more than maxpacketsize, there will be state + * mismtach*/ +#if USB_DEVICE_IP3511_DOUBLE_BUFFER_ENABLE +#define USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER (1u) +#else +#define USB_DEVICE_IP3511_DISABLE_OUT_DOUBLE_BUFFER (0u) +#endif + +#define USB_DEVICE_IP3511HS_LPM_ADPPROBE_ATTACH_DEBOUNCE_COUNT (3) + +/* if FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE is true: + * Enable this macro to exit HS mode automatically if the user case is: + * host and device keep cable connected, and host turn off vbus to simulate detachment. + * If user disconnects the cable, there is no issue and don't need enable this macro. + * There is one delay in the isr if enable this macro. + */ +#define USB_DEVICE_IP3511HS_FORCE_EXIT_HS_MODE_ENABLE (0u) + +/*! @brief Endpoint state structure */ +typedef struct _usb_device_lpc3511ip_endpoint_state_struct +{ + uint8_t *transferBuffer; /*!< Address of buffer containing the data to be transmitted */ + uint32_t transferLength; /*!< Length of data to transmit. */ + uint32_t transferDone; /*!< The data length has been transferred*/ + uint32_t transferPrimedLength; /*!< it may larger than transferLength, because the primed length may larger than the + transaction length. */ + uint8_t *epPacketBuffer; /*!< The max packet buffer for copying*/ + union + { + uint32_t state; /*!< The state of the endpoint */ + struct + { + uint32_t maxPacketSize : 11U; /*!< The maximum packet size of the endpoint */ + uint32_t stalled : 1U; /*!< The endpoint is stalled or not */ + uint32_t transferring : 1U; /*!< The endpoint is transferring */ + uint32_t zlt : 1U; /*!< zlt flag */ + uint32_t stallPrimed : 1U; + uint32_t epPacketCopyed : 1U; /*!< whether use the copy buffer */ + uint32_t epControlDefault : 5u; /*!< The EP command/status 26~30 bits */ + uint32_t doubleBufferBusy : 2U; /*!< How many buffers are primed, for control endpoint it is not used */ + uint32_t producerOdd : 1U; /*!< When priming one transaction, prime to this endpoint buffer */ + uint32_t consumerOdd : 1U; /*!< When transaction is done, read result from this endpoint buffer */ + uint32_t endpointType : 2U; + uint32_t reserved1 : 5U; + } stateBitField; + } stateUnion; + union + { + uint16_t epBufferStatus; + /* If double buff is disable, only epBufferStatusUnion[0] is used; + For control endpoint, only epBufferStatusUnion[0] is used. */ + struct + { + uint16_t transactionLength : 11U; + uint16_t epPacketCopyed : 1U; + } epBufferStatusField; + } epBufferStatusUnion[2]; +} usb_device_lpc3511ip_endpoint_state_struct_t; + +/*! @brief LPC USB controller (IP3511) state structure */ +typedef struct _usb_device_lpc3511ip_state_struct +{ + /*!< control data buffer, must align with 64 */ + uint8_t *controlData; + /*!< 8 bytes' setup data, must align with 64 */ + uint8_t *setupData; + /*!< 4 bytes for zero length transaction, must align with 64 */ + uint8_t *zeroTransactionData; + /* Endpoint state structures */ + usb_device_lpc3511ip_endpoint_state_struct_t endpointState[(USB_DEVICE_IP3511_ENDPOINTS_NUM * 2)]; + usb_device_handle deviceHandle; /*!< (4 bytes) Device handle used to identify the device object belongs to */ + USB_LPC3511IP_Type *registerBase; /*!< (4 bytes) ip base address */ + volatile uint32_t *epCommandStatusList; /* endpoint list */ +#if (defined(USB_DEVICE_CONFIG_CHARGER_DETECT) && (USB_DEVICE_CONFIG_CHARGER_DETECT > 0U)) && \ + (defined(FSL_FEATURE_SOC_USBHSDCD_COUNT) && (FSL_FEATURE_SOC_USBHSDCD_COUNT > 0U)) + void *dcdHandle; /*!< Dcd handle used to identify the device object belongs to */ +#endif + uint8_t controllerId; /*!< Controller ID */ + uint8_t isResetting; /*!< Is doing device reset or not */ + uint8_t deviceSpeed; /*!< some controller support the HS */ +#if ((defined(USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY)) && (USB_DEVICE_IP3511_RESERVED_BUFFER_FOR_COPY > 0U)) + uint8_t *epReservedBuffer; + uint8_t epReservedBufferBits[(USB_DEVICE_IP3511_BITS_FOR_RESERVED_BUFFER + 7) / 8]; +#endif +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) + uint8_t controllerSpeed; +#endif +#if (defined(USB_DEVICE_CONFIG_DETACH_ENABLE) && (USB_DEVICE_CONFIG_DETACH_ENABLE)) + uint8_t deviceState; /*!< Is device attached,1 attached,0 detached */ +#endif +#if (defined(USB_DEVICE_CONFIG_LOW_POWER_MODE) && (USB_DEVICE_CONFIG_LOW_POWER_MODE > 0U)) +#if (defined(USB_DEVICE_CONFIG_LPM_L1) && (USB_DEVICE_CONFIG_LPM_L1 > 0U)) + uint8_t lpmRemoteWakeUp; +#endif +#endif +#if ((defined(USB_DEVICE_CONFIG_LPCIP3511HS)) && (USB_DEVICE_CONFIG_LPCIP3511HS > 0U)) +#if (defined(FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK) && \ + (FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK)) + uint8_t hsInterruptIssue; +#endif +#endif +} usb_device_lpc3511ip_state_struct_t; + +/*! + * @name USB device controller (IP3511) functions + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initializes the USB device controller instance. + * + * This function initializes the USB device controller module specified by the controllerId. + * + * @param[in] controllerId The controller ID of the USB IP. See the enumeration type usb_controller_index_t. + * @param[in] handle Pointer of the device handle used to identify the device object belongs to. + * @param[out] controllerHandle An out parameter used to return the pointer of the device controller handle to the + * caller. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceLpc3511IpInit(uint8_t controllerId, + usb_device_handle handle, + usb_device_controller_handle *controllerHandle); + +/*! + * @brief Deinitializes the USB device controller instance. + * + * This function deinitializes the USB device controller module. + * + * @param[in] controllerHandle Pointer of the device controller handle. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceLpc3511IpDeinit(usb_device_controller_handle controllerHandle); + +/*! + * @brief Sends data through a specified endpoint. + * + * This function sends data through a specified endpoint. + * + * @param[in] controllerHandle Pointer of the device controller handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to hold the data need to be sent. + * @param[in] length The data length need to be sent. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value indicates whether the sending request is successful or not. The transfer completion is + * notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for a specific endpoint. + * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer can begin only when the previous transfer is done (a notification is obtained through the + * endpoint + * callback). + */ +usb_status_t USB_DeviceLpc3511IpSend(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Receives data through a specified endpoint. + * + * This function receives data through a specified endpoint. + * + * @param[in] controllerHandle Pointer of the device controller handle. + * @param[in] endpointAddress Endpoint index. + * @param[in] buffer The memory address to save the received data. + * @param[in] length The data length to be received. + * + * @return A USB error code or kStatus_USB_Success. + * + * @note The return value indicates whether the receiving request is successful or not. The transfer completion is + * notified by the + * corresponding callback function. + * Currently, only one transfer request can be supported for a specific endpoint. + * If there is a specific requirement to support multiple transfer requests for a specific endpoint, the application + * should implement a queue in the application level. + * The subsequent transfer can begin only when the previous transfer is done (a notification is obtained through the + * endpoint + * callback). + */ +usb_status_t USB_DeviceLpc3511IpRecv(usb_device_controller_handle controllerHandle, + uint8_t endpointAddress, + uint8_t *buffer, + uint32_t length); + +/*! + * @brief Cancels the pending transfer in a specified endpoint. + * + * The function is used to cancel the pending transfer in a specified endpoint. + * + * @param[in] controllerHandle ointer of the device controller handle. + * @param[in] ep Endpoint address, bit7 is the direction of endpoint, 1U - IN, abd 0U - OUT. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceLpc3511IpCancel(usb_device_controller_handle controllerHandle, uint8_t ep); + +/*! + * @brief Controls the status of the selected item. + * + * The function is used to control the status of the selected item. + * + * @param[in] controllerHandle Pointer of the device controller handle. + * @param[in] type The selected item. Please refer to enumeration type usb_device_control_type_t. + * @param[in,out] param The parameter type is determined by the selected item. + * + * @return A USB error code or kStatus_USB_Success. + */ +usb_status_t USB_DeviceLpc3511IpControl(usb_device_controller_handle controllerHandle, + usb_device_control_type_t type, + void *param); + +/*! @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __USB_DEVICE_LPC3511IP_H__ */ diff --git a/zephyr/middleware/usb/include/usb.h b/zephyr/middleware/usb/include/usb.h new file mode 100644 index 000000000..d2010329b --- /dev/null +++ b/zephyr/middleware/usb/include/usb.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_H__ +#define __USB_H__ + +#include +#include +#include "fsl_common.h" +#include "usb_spec.h" + +/*! + * @addtogroup usb_drv + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Defines USB stack major version */ +#define USB_STACK_VERSION_MAJOR (2UL) +/*! @brief Defines USB stack minor version */ +#define USB_STACK_VERSION_MINOR (8UL) +/*! @brief Defines USB stack bugfix version */ +#define USB_STACK_VERSION_BUGFIX (0U) + +/*! @brief USB stack version definition */ +#define USB_MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) + +/*! @brief USB stack component version definition, changed with component in yaml together */ +#define USB_STACK_COMPONENT_VERSION \ + MAKE_VERSION(USB_STACK_VERSION_MAJOR, USB_STACK_VERSION_MINOR, USB_STACK_VERSION_BUGFIX) + +/* + * Component ID used by tools + * + * FSL_COMPONENT_ID "middleware.usb.stack_common" + */ + +/*! @brief USB error code */ +typedef enum _usb_status +{ + kStatus_USB_Success = 0x00U, /*!< Success */ + kStatus_USB_Error, /*!< Failed */ + + kStatus_USB_Busy, /*!< Busy */ + kStatus_USB_InvalidHandle, /*!< Invalid handle */ + kStatus_USB_InvalidParameter, /*!< Invalid parameter */ + kStatus_USB_InvalidRequest, /*!< Invalid request */ + kStatus_USB_ControllerNotFound, /*!< Controller cannot be found */ + kStatus_USB_InvalidControllerInterface, /*!< Invalid controller interface */ + + kStatus_USB_NotSupported, /*!< Configuration is not supported */ + kStatus_USB_Retry, /*!< Enumeration get configuration retry */ + kStatus_USB_TransferStall, /*!< Transfer stalled */ + kStatus_USB_TransferFailed, /*!< Transfer failed */ + kStatus_USB_AllocFail, /*!< Allocation failed */ + kStatus_USB_LackSwapBuffer, /*!< Insufficient swap buffer for KHCI */ + kStatus_USB_TransferCancel, /*!< The transfer cancelled */ + kStatus_USB_BandwidthFail, /*!< Allocate bandwidth failed */ + kStatus_USB_MSDStatusFail, /*!< For MSD, the CSW status means fail */ + kStatus_USB_EHCIAttached, + kStatus_USB_EHCIDetached, + kStatus_USB_DataOverRun, /*!< The amount of data returned by the endpoint exceeded + either the size of the maximum data packet allowed + from the endpoint or the remaining buffer size. */ +} usb_status_t; + +/*! @brief USB host handle type define */ +typedef void *usb_host_handle; + +/*! @brief USB device handle type define. For device stack it is the whole device handle; for host stack it is the + * attached device instance handle*/ +typedef void *usb_device_handle; + +/*! @brief USB OTG handle type define */ +typedef void *usb_otg_handle; + +/*! @brief USB controller ID */ +typedef enum _usb_controller_index +{ + kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */ + kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved + to be used in the future. */ + kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */ + kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */ + kUSB_ControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ + + kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */ + kUSB_ControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511 + IPs, this is reserved to be used in the future. */ + + kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */ + kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved + to be used in the future. */ + + kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */ + kUSB_ControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs, + this is reserved to be used in the future. */ + kUSB_ControllerDwc30 = 12U, /*!< DWC3 0U */ + kUSB_ControllerDwc31 = 13U, /*!< DWC3 1U Currently, there are no platforms which have two Dwc IPs, this is reserved + to be used in the future.*/ +} usb_controller_index_t; + +/** + * @brief USB stack version fields + */ +typedef struct _usb_version +{ + uint8_t major; /*!< Major */ + uint8_t minor; /*!< Minor */ + uint8_t bugfix; /*!< Bug fix */ +} usb_version_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! @} */ + +#endif /* __USB_H__ */ diff --git a/zephyr/middleware/usb/include/usb_spec.h b/zephyr/middleware/usb/include/usb_spec.h new file mode 100644 index 000000000..977787569 --- /dev/null +++ b/zephyr/middleware/usb/include/usb_spec.h @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __USB_SPEC_H__ +#define __USB_SPEC_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* USB speed (the value cannot be changed because EHCI QH use the value directly)*/ +#define USB_SPEED_FULL (0x00U) +#define USB_SPEED_LOW (0x01U) +#define USB_SPEED_HIGH (0x02U) +#define USB_SPEED_SUPER (0x04U) + +/* Set up packet structure */ +typedef struct _usb_setup_struct +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} usb_setup_struct_t; + +/* USB standard descriptor endpoint type */ +#define USB_ENDPOINT_CONTROL (0x00U) +#define USB_ENDPOINT_ISOCHRONOUS (0x01U) +#define USB_ENDPOINT_BULK (0x02U) +#define USB_ENDPOINT_INTERRUPT (0x03U) + +/* USB standard descriptor transfer direction (cannot change the value because iTD use the value directly) */ +#define USB_OUT (0U) +#define USB_IN (1U) + +/* USB standard descriptor length */ +#define USB_DESCRIPTOR_LENGTH_DEVICE (0x12U) +#define USB_DESCRIPTOR_LENGTH_CONFIGURE (0x09U) +#define USB_DESCRIPTOR_LENGTH_INTERFACE (0x09U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT (0x07U) +#define USB_DESCRIPTOR_LENGTH_ENDPOINT_COMPANION (0x06U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_QUALITIER (0x0AU) +#define USB_DESCRIPTOR_LENGTH_OTG_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_BOS_DESCRIPTOR (5U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_USB20_EXTENSION (0x07U) +#define USB_DESCRIPTOR_LENGTH_DEVICE_CAPABILITY_SUPERSPEED (0x0AU) + +/* USB Device Capability Type Codes */ +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_WIRELESS (0x01U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_USB20_EXTENSION (0x02U) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY_SUPERSPEED (0x03U) + +/* USB standard descriptor type */ +#define USB_DESCRIPTOR_TYPE_DEVICE (0x01U) +#define USB_DESCRIPTOR_TYPE_CONFIGURE (0x02U) +#define USB_DESCRIPTOR_TYPE_STRING (0x03U) +#define USB_DESCRIPTOR_TYPE_INTERFACE (0x04U) +#define USB_DESCRIPTOR_TYPE_ENDPOINT (0x05U) +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALITIER (0x06U) +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED_CONFIGURATION (0x07U) +#define USB_DESCRIPTOR_TYPE_INTERFAACE_POWER (0x08U) +#define USB_DESCRIPTOR_TYPE_OTG (0x09U) +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION (0x0BU) +#define USB_DESCRIPTOR_TYPE_BOS (0x0F) +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY (0x10) + +#define USB_DESCRIPTOR_TYPE_HID (0x21U) +#define USB_DESCRIPTOR_TYPE_HID_REPORT (0x22U) +#define USB_DESCRIPTOR_TYPE_HID_PHYSICAL (0x23U) + +#define USB_DESCRIPTOR_TYPE_ENDPOINT_COMPANION (0x30U) + +/* USB standard request type */ +#define USB_REQUEST_TYPE_DIR_MASK (0x80U) +#define USB_REQUEST_TYPE_DIR_SHIFT (7U) +#define USB_REQUEST_TYPE_DIR_OUT (0x00U) +#define USB_REQUEST_TYPE_DIR_IN (0x80U) + +#define USB_REQUEST_TYPE_TYPE_MASK (0x60U) +#define USB_REQUEST_TYPE_TYPE_SHIFT (5U) +#define USB_REQUEST_TYPE_TYPE_STANDARD (0U) +#define USB_REQUEST_TYPE_TYPE_CLASS (0x20U) +#define USB_REQUEST_TYPE_TYPE_VENDOR (0x40U) + +#define USB_REQUEST_TYPE_RECIPIENT_MASK (0x1FU) +#define USB_REQUEST_TYPE_RECIPIENT_SHIFT (0U) +#define USB_REQUEST_TYPE_RECIPIENT_DEVICE (0x00U) +#define USB_REQUEST_TYPE_RECIPIENT_INTERFACE (0x01U) +#define USB_REQUEST_TYPE_RECIPIENT_ENDPOINT (0x02U) +#define USB_REQUEST_TYPE_RECIPIENT_OTHER (0x03U) + +/* USB standard request */ +#define USB_REQUEST_STANDARD_GET_STATUS (0x00U) +#define USB_REQUEST_STANDARD_CLEAR_FEATURE (0x01U) +#define USB_REQUEST_STANDARD_SET_FEATURE (0x03U) +#define USB_REQUEST_STANDARD_SET_ADDRESS (0x05U) +#define USB_REQUEST_STANDARD_GET_DESCRIPTOR (0x06U) +#define USB_REQUEST_STANDARD_SET_DESCRIPTOR (0x07U) +#define USB_REQUEST_STANDARD_GET_CONFIGURATION (0x08U) +#define USB_REQUEST_STANDARD_SET_CONFIGURATION (0x09U) +#define USB_REQUEST_STANDARD_GET_INTERFACE (0x0AU) +#define USB_REQUEST_STANDARD_SET_INTERFACE (0x0BU) +#define USB_REQUEST_STANDARD_SYNCH_FRAME (0x0CU) + +/* USB standard request GET Status */ +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_SELF_POWERED_SHIFT (0U) +#define USB_REQUEST_STANDARD_GET_STATUS_DEVICE_REMOTE_WARKUP_SHIFT (1U) + +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_MASK (0x01U) +#define USB_REQUEST_STANDARD_GET_STATUS_ENDPOINT_HALT_SHIFT (0U) + +#define USB_REQUEST_STANDARD_GET_STATUS_OTG_STATUS_SELECTOR (0xF000U) + +/* USB standard request CLEAR/SET feature */ +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_ENDPOINT_HALT (0U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_REMOTE_WAKEUP (1U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_DEVICE_TEST_MODE (2U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_B_HNP_ENABLE (3U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_HNP_SUPPORT (4U) +#define USB_REQUEST_STANDARD_FEATURE_SELECTOR_A_ALT_HNP_SUPPORT (5U) + +/* USB standard descriptor configure bmAttributes */ +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_MASK (0x80U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_D7_SHIFT (7U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_MASK (0x40U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_SELF_POWERED_SHIFT (6U) + +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_MASK (0x20U) +#define USB_DESCRIPTOR_CONFIGURE_ATTRIBUTE_REMOTE_WAKEUP_SHIFT (5U) + +/* USB standard descriptor endpoint bmAttributes */ +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_MASK (0x80U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_SHIFT (7U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_OUT (0U) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_DIRECTION_IN (0x80U) + +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_MASK (0x0FU) +#define USB_DESCRIPTOR_ENDPOINT_ADDRESS_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_TYPE_MASK (0x03U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_NUMBER_SHFIT (0U) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_MASK (0x0CU) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SHFIT (2U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_NO_SYNC (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ASYNC (0x04U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_ADAPTIVE (0x08U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_SYNC_TYPE_SYNC (0x0CU) + +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_MASK (0x30U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_SHFIT (4U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_DATA_ENDPOINT (0x00U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_FEEDBACK_ENDPOINT (0x10U) +#define USB_DESCRIPTOR_ENDPOINT_ATTRIBUTE_USAGE_TYPE_IMPLICIT_FEEDBACK_DATA_ENDPOINT (0x20U) + +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_SIZE_MASK (0x07FFu) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_MASK (0x1800u) +#define USB_DESCRIPTOR_ENDPOINT_MAXPACKETSIZE_MULT_TRANSACTIONS_SHFIT (11U) + +/* USB standard descriptor otg bmAttributes */ +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_SRP_MASK (0x01u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_HNP_MASK (0x02u) +#define USB_DESCRIPTOR_OTG_ATTRIBUTES_ADP_MASK (0x04u) + +/* USB standard descriptor device capability usb20 extension bmAttributes */ +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_MASK (0x02U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_LPM_SHIFT (1U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_MASK (0x04U) +#define USB_DESCRIPTOR_DEVICE_CAPABILITY_USB20_EXTENSION_BESL_SHIFT (2U) + +/* Language structure */ +typedef struct _usb_language +{ + uint8_t **string; /* The Strings descriptor array */ + uint32_t *length; /* The strings descriptor length array */ + uint16_t languageId; /* The language id of current language */ +} usb_language_t; + +typedef struct _usb_language_list +{ + uint8_t *languageString; /* The String 0U pointer */ + uint32_t stringLength; /* The String 0U Length */ + usb_language_t *languageList; /* The language list */ + uint8_t count; /* The language count */ +} usb_language_list_t; + +typedef struct _usb_descriptor_common +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bData[1]; /* Data */ +} usb_descriptor_common_t; + +typedef struct _usb_descriptor_device +{ + uint8_t bLength; /* Size of this descriptor in bytes */ + uint8_t bDescriptorType; /* DEVICE Descriptor Type */ + uint8_t bcdUSB[2]; /* UUSB Specification Release Number in Binary-Coded Decimal, e.g. 0x0200U */ + uint8_t bDeviceClass; /* Class code */ + uint8_t bDeviceSubClass; /* Sub-Class code */ + uint8_t bDeviceProtocol; /* Protocol code */ + uint8_t bMaxPacketSize0; /* Maximum packet size for endpoint zero */ + uint8_t idVendor[2]; /* Vendor ID (assigned by the USB-IF) */ + uint8_t idProduct[2]; /* Product ID (assigned by the manufacturer) */ + uint8_t bcdDevice[2]; /* Device release number in binary-coded decimal */ + uint8_t iManufacturer; /* Index of string descriptor describing manufacturer */ + uint8_t iProduct; /* Index of string descriptor describing product */ + uint8_t iSerialNumber; /* Index of string descriptor describing the device serial number */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} usb_descriptor_device_t; + +typedef struct _usb_descriptor_configuration +{ + uint8_t bLength; /* Descriptor size in bytes = 9U */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2U or 7U */ + uint8_t wTotalLength[2]; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this configuration. */ + uint8_t bConfigurationValue; /* Value to set this configuration. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Configuration characteristics */ + uint8_t bMaxPower; /* Maximum power from bus, 2 mA units */ +} usb_descriptor_configuration_t; + +typedef struct _usb_descriptor_interface +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} usb_descriptor_interface_t; + +typedef struct _usb_descriptor_endpoint +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSize[2]; + uint8_t bInterval; +} usb_descriptor_endpoint_t; + +typedef struct _usb_descriptor_endpoint_companion +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bMaxBurst; + uint8_t bmAttributes; + uint8_t wBytesPerInterval[2]; +} usb_descriptor_endpoint_companion_t; + +typedef struct _usb_descriptor_binary_device_object_store +{ + uint8_t bLength; /* Descriptor size in bytes = 5U */ + uint8_t bDescriptorType; /* BOS Descriptor type = 0FU*/ + uint8_t wTotalLength[2]; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bNumDeviceCaps; /*The number of separate device capability descriptors in the BOS*/ +} usb_descriptor_bos_t; + +typedef struct _usb_descriptor_usb20_extension +{ + uint8_t bLength; /* Descriptor size in bytes = 7U */ + uint8_t bDescriptorType; /* DEVICE CAPABILITY Descriptor type = 0x10U*/ + uint8_t bDevCapabilityType; /*Length of this descriptor and all of its sub descriptors*/ + uint8_t bmAttributes[4]; /*Bitmap encoding of supported device level features.*/ +} usb_descriptor_usb20_extension_t; +typedef struct _usb_descriptor_super_speed_device_capability +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bmAttributes; + uint8_t wSpeedsSupported[2]; + uint8_t bFunctionalitySupport; + uint8_t bU1DevExitLat; + uint8_t wU2DevExitLat[2]; +} usb_bos_device_capability_susperspeed_desc_t; +typedef union _usb_descriptor_union +{ + usb_descriptor_common_t common; /* Common descriptor */ + usb_descriptor_device_t device; /* Device descriptor */ + usb_descriptor_configuration_t configuration; /* Configuration descriptor */ + usb_descriptor_interface_t interface; /* Interface descriptor */ + usb_descriptor_endpoint_t endpoint; /* Endpoint descriptor */ + usb_descriptor_endpoint_companion_t endpointCompanion; /* Endpoint companion descriptor */ +} usb_descriptor_union_t; + +#endif /* __USB_SPEC_H__ */ diff --git a/zephyr/middleware/usb/phy/CMakeLists.txt b/zephyr/middleware/usb/phy/CMakeLists.txt new file mode 100644 index 000000000..71e79ed5f --- /dev/null +++ b/zephyr/middleware/usb/phy/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) +zephyr_library_sources_ifdef(CONFIG_USB_MCUX usb_phy.c) diff --git a/zephyr/middleware/usb/phy/usb_phy.c b/zephyr/middleware/usb/phy/usb_phy.c new file mode 100644 index 000000000..016ff6e3c --- /dev/null +++ b/zephyr/middleware/usb/phy/usb_phy.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "usb_dc_mcux.h" +#include "fsl_device_registers.h" + +#include "usb_phy.h" + +void *USB_EhciPhyGetBase(uint8_t controllerId) +{ + void *usbPhyBase = NULL; +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + uint32_t instance; + uint32_t newinstance = 0; + uint32_t usbphy_base_temp[] = USBPHY_BASE_ADDRS; + uint32_t usbphy_base[] = USBPHY_BASE_ADDRS; + uint32_t *temp; + if (controllerId < (uint8_t)kUSB_ControllerEhci0) + { + return NULL; + } + + if ((controllerId == (uint8_t)kUSB_ControllerEhci0) || (controllerId == (uint8_t)kUSB_ControllerEhci1)) + { + controllerId = controllerId - (uint8_t)kUSB_ControllerEhci0; + } + else if ((controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs0) || + (controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs1)) + { + controllerId = controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0; + } + else if ((controllerId == (uint8_t)kUSB_ControllerIp3516Hs0) || (controllerId == (uint8_t)kUSB_ControllerIp3516Hs1)) + { + controllerId = controllerId - (uint8_t)kUSB_ControllerIp3516Hs0; + } + else + { + /*no action*/ + } + + for (instance = 0; instance < (sizeof(usbphy_base_temp) / sizeof(usbphy_base_temp[0])); instance++) + { + if (0U != usbphy_base_temp[instance]) + { + usbphy_base[newinstance++] = usbphy_base_temp[instance]; + } + } + if (controllerId > newinstance) + { + return NULL; + } + temp = (uint32_t *)usbphy_base[controllerId]; + usbPhyBase = (void *)temp; +#endif + return usbPhyBase; +} + +/*! + * @brief ehci phy initialization. + * + * This function initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return (uint8_t)kStatus_USB_Error; + } + +#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U)) + ANATOP->HW_ANADIG_REG_3P0.RW = + (ANATOP->HW_ANADIG_REG_3P0.RW & + (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) | + ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK; + ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET = + ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK; +#endif + +#if (defined USB_ANALOG) + USB_ANALOG->INSTANCE[controllerId - (uint8_t)kUSB_ControllerEhci0].CHRG_DETECT_SET = + USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1); +#endif + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; + if (((uint8_t)kUSB_ControllerIp3516Hs0 == controllerId) || ((uint8_t)kUSB_ControllerIp3516Hs1 == controllerId) || + ((uint8_t)kUSB_ControllerLpcIp3511Hs0 == controllerId) || + ((uint8_t)kUSB_ControllerLpcIp3511Hs1 == controllerId)) + { + usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK; + usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK; + } + if (NULL != phyConfig) + { + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); + } +#endif + + return (uint8_t)kStatus_USB_Success; +} + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return (uint8_t)kStatus_USB_Error; + } + +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */ +#endif + +#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U)) + usbPhyBase->CTRL_CLR |= USBPHY_CTRL_AUTORESUME_EN_MASK; +#else + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK; +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK; + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */ + usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */ + /* PWD register provides overall control of the PHY power state */ + usbPhyBase->PWD = 0U; +#if (defined USBPHY_ANACTRL_PFD_CLKGATE_MASK) + /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD + * pfd clock = 480MHz*18/N, where N=18~35 + * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode + */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */ + usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */ + + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK; + usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK; + while (0U == (usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) + { + } +#endif + if (NULL != phyConfig) + { + /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */ + usbPhyBase->TX = + ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) | + (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) | + USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM))); + } +#endif + + return (uint8_t)kStatus_USB_Success; +} + +/*! + * @brief ehci phy de-initialization. + * + * This function de-initialize ehci phy IP. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + */ +void USB_EhciPhyDeinit(uint8_t controllerId) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } +#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT))) + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */ + usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */ +#endif + usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */ +#endif +} + +/*! + * @brief ehci phy disconnect detection enable or disable. + * + * This function enable/disable host ehci disconnect detection. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable) +{ +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } + + if (0U != enable) + { + usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK; + } + else + { + usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK); + } +#endif +} + +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) +void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable) +{ + USBPHY_Type *usbPhyBase; + + usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId); + if (NULL == usbPhyBase) + { + return; + } + + if (0U != enable) + { + uint32_t delay = 1000000; + usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK; + while ((0U != (usbPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)) && (0U != delay)) + { + delay--; + } + usbPhyBase->USB1_LOOPBACK_SET = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK; + } + else + { + usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK; + usbPhyBase->USB1_LOOPBACK_CLR = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK; + } +} +#endif +#endif diff --git a/zephyr/middleware/usb/phy/usb_phy.h b/zephyr/middleware/usb/phy/usb_phy.h new file mode 100644 index 000000000..014740711 --- /dev/null +++ b/zephyr/middleware/usb/phy/usb_phy.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016 - 2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __USB_PHY_H__ +#define __USB_PHY_H__ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +typedef struct _usb_phy_config_struct +{ + uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */ + uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */ + uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */ +} usb_phy_config_struct_t; + +#if defined(__cplusplus) +extern "C" { +#endif + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief EHCI PHY get USB phy bass address. + * + * This function is used to get USB phy bass address. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * + * @retval USB phy bass address. + */ +extern void *USB_EhciPhyGetBase(uint8_t controllerId); + +/*! + * @brief EHCI PHY initialization. + * + * This function initializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See the #usb_controller_index_t. + * @param[in] freq The external input clock. + * + * @retval kStatus_USB_Success Cancel successfully. + * @retval kStatus_USB_Error The freq value is incorrect. + */ +extern uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief ehci phy initialization for suspend and resume. + * + * This function initialize ehci phy IP for suspend and resume. + * + * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t. + * @param[in] freq the external input clock. + * for example: if the external input clock is 16M, the parameter freq should be 16000000. + * + * @retval kStatus_USB_Success cancel successfully. + * @retval kStatus_USB_Error the freq value is incorrect. + */ +extern uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig); + +/*! + * @brief EHCI PHY deinitialization. + * + * This function deinitializes the EHCI PHY IP. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + */ +extern void USB_EhciPhyDeinit(uint8_t controllerId); + +/*! + * @brief EHCI PHY disconnect detection enable or disable. + * + * This function enable/disable the host EHCI disconnect detection. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +extern void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable); +#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U)) +#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U)) +/*! + * @brief Force the PHY enter FS Mode + * + * on RT500 and RT600, the device doesn't enter FS Mode after vbus is invalide and the controller works as HS. + * + * @param[in] controllerId EHCI controller ID; See #usb_controller_index_t. + * @param[in] enable + * 1U - enable; + * 0U - disable; + */ +extern void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable); +#endif +#endif +#if defined(__cplusplus) +} +#endif + +#endif /* __USB_PHY_H__ */ diff --git a/zephyr/middleware/wireless/framework_5.3.3/CMakeLists.txt b/zephyr/middleware/wireless/framework_5.3.3/CMakeLists.txt new file mode 100644 index 000000000..c4bf46d93 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/CMakeLists.txt @@ -0,0 +1,7 @@ +zephyr_include_directories(Common) +zephyr_include_directories(OSAbstraction/Interface) +zephyr_include_directories(XCVR/${MCUX_DEVICE}) + +add_subdirectory(XCVR/${MCUX_DEVICE}) + +zephyr_library_sources(OSAbstraction/Source/fsl_os_abstraction_zephyr.c) diff --git a/zephyr/middleware/wireless/framework_5.3.3/Common/EmbeddedTypes.h b/zephyr/middleware/wireless/framework_5.3.3/Common/EmbeddedTypes.h new file mode 100644 index 000000000..6953b4d70 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/Common/EmbeddedTypes.h @@ -0,0 +1,215 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* +* \file +* +* This file holds type definitions that maps the standard c-types into types +* with guaranteed sizes. The types are target/platform specific and must be edited +* for each new target/platform. +* The header file also provides definitions for TRUE, FALSE and NULL. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _EMBEDDEDTYPES_H_ +#define _EMBEDDEDTYPES_H_ + + +/************************************************************************************ +* +* INCLUDES +* +************************************************************************************/ + +#include + + +/************************************************************************************ +* +* TYPE DEFINITIONS +* +************************************************************************************/ + +/* boolean types */ +typedef uint8_t bool_t; + +typedef uint8_t index_t; + +/* TRUE/FALSE definition*/ +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/* null pointer definition*/ +#ifndef NULL +#define NULL (( void * )( 0x0UL )) +#endif + +#if defined(__GNUC__) +#define PACKED_STRUCT struct __attribute__ ((__packed__)) +#define PACKED_UNION union __attribute__ ((__packed__)) +#elif defined(__IAR_SYSTEMS_ICC__) +#define PACKED_STRUCT __packed struct +#define PACKED_UNION __packed union +#else +#define PACKED_STRUCT struct +#define PACKED_UNION union +#endif + +typedef unsigned char uintn8_t; +typedef unsigned long uintn32_t; + +typedef unsigned char uchar_t; + +#if !defined(MIN) +#define MIN(a,b) (((a) < (b))?(a):(b)) +#endif + +#if !defined(MAX) +#define MAX(a,b) (((a) > (b))?(a):(b)) +#endif + +/* Compute the number of elements of an array */ +#define NumberOfElements(x) (sizeof(x)/sizeof((x)[0])) + +/* Compute the size of a string initialized with quotation marks */ +#define SizeOfString(string) (sizeof(string) - 1) + +#define GetRelAddr(strct, member) ((uint32_t)&(((strct*)(void *)0)->member)) +#define GetSizeOfMember(strct, member) sizeof(((strct*)(void *)0)->member) + +/* Type definitions for link configuration of instantiable layers */ +#define gInvalidInstanceId_c (instanceId_t)(-1) +typedef uint32_t instanceId_t; + +/* Bit shift definitions */ +#define BIT0 0x01 +#define BIT1 0x02 +#define BIT2 0x04 +#define BIT3 0x08 +#define BIT4 0x10 +#define BIT5 0x20 +#define BIT6 0x40 +#define BIT7 0x80 +#define BIT8 0x100 +#define BIT9 0x200 +#define BIT10 0x400 +#define BIT11 0x800 +#define BIT12 0x1000 +#define BIT13 0x2000 +#define BIT14 0x4000 +#define BIT15 0x8000 +#define BIT16 0x10000 +#define BIT17 0x20000 +#define BIT18 0x40000 +#define BIT19 0x80000 +#define BIT20 0x100000 +#define BIT21 0x200000 +#define BIT22 0x400000 +#define BIT23 0x800000 +#define BIT24 0x1000000 +#define BIT25 0x2000000 +#define BIT26 0x4000000 +#define BIT27 0x8000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +/* Shift definitions */ +#define SHIFT0 (0) +#define SHIFT1 (1) +#define SHIFT2 (2) +#define SHIFT3 (3) +#define SHIFT4 (4) +#define SHIFT5 (5) +#define SHIFT6 (6) +#define SHIFT7 (7) +#define SHIFT8 (8) +#define SHIFT9 (9) +#define SHIFT10 (10) +#define SHIFT11 (11) +#define SHIFT12 (12) +#define SHIFT13 (13) +#define SHIFT14 (14) +#define SHIFT15 (15) +#define SHIFT16 (16) +#define SHIFT17 (17) +#define SHIFT18 (18) +#define SHIFT19 (19) +#define SHIFT20 (20) +#define SHIFT21 (21) +#define SHIFT22 (22) +#define SHIFT23 (23) +#define SHIFT24 (24) +#define SHIFT25 (25) +#define SHIFT26 (26) +#define SHIFT27 (27) +#define SHIFT28 (28) +#define SHIFT29 (29) +#define SHIFT30 (30) +#define SHIFT31 (31) + +#define SHIFT32 (32) +#define SHIFT33 (33) +#define SHIFT34 (34) +#define SHIFT35 (35) +#define SHIFT36 (36) +#define SHIFT37 (37) +#define SHIFT38 (38) +#define SHIFT39 (39) +#define SHIFT40 (40) +#define SHIFT41 (41) +#define SHIFT42 (42) +#define SHIFT43 (43) +#define SHIFT44 (44) +#define SHIFT45 (45) +#define SHIFT46 (46) +#define SHIFT47 (47) +#define SHIFT48 (48) +#define SHIFT49 (49) +#define SHIFT50 (50) +#define SHIFT51 (51) +#define SHIFT52 (52) +#define SHIFT53 (53) +#define SHIFT54 (54) +#define SHIFT55 (55) +#define SHIFT56 (56) +#define SHIFT57 (57) +#define SHIFT58 (58) +#define SHIFT59 (59) +#define SHIFT60 (60) +#define SHIFT61 (61) +#define SHIFT62 (62) +#define SHIFT63 (63) + + +#endif /* _EMBEDDEDTYPES_H_ */ diff --git a/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Interface/fsl_os_abstraction.h b/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Interface/fsl_os_abstraction.h new file mode 100644 index 000000000..8f9745711 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Interface/fsl_os_abstraction.h @@ -0,0 +1,608 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#ifndef _FSL_OS_ABSTRACTION_H_ +#define _FSL_OS_ABSTRACTION_H_ + +#include "EmbeddedTypes.h" +#include "fsl_os_abstraction_config.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ +/*! @brief Type for the Task Priority*/ + typedef uint16_t osaTaskPriority_t; +/*! @brief Type for the timer definition*/ + typedef enum { + osaTimer_Once = 0, /*!< one-shot timer*/ + osaTimer_Periodic = 1 /*!< repeating timer*/ + } osaTimer_t; + /*! @brief Type for a task handler, returned by the OSA_TaskCreate function. */ + typedef void* osaTaskId_t; +/*! @brief Type for the parameter to be passed to the task at its creation */ + typedef void* osaTaskParam_t; + /*! @brief Type for task pointer. Task prototype declaration */ + typedef void (*osaTaskPtr_t) (osaTaskParam_t task_param); +/*! @brief Type for the semaphore handler, returned by the OSA_SemaphoreCreate function. */ + typedef void* osaSemaphoreId_t; +/*! @brief Type for the mutex handler, returned by the OSA_MutexCreate function. */ + typedef void* osaMutexId_t; +/*! @brief Type for the event handler, returned by the OSA_EventCreate function. */ + typedef void* osaEventId_t; +/*! @brief Type for an event flags group, bit 32 is reserved. */ + typedef uint32_t osaEventFlags_t; +/*! @brief Message definition. */ + typedef void* osaMsg_t; +/*! @brief Type for the message queue handler, returned by the OSA_MsgQCreate function. */ + typedef void* osaMsgQId_t; + /*! @brief Type for the Timer handler, returned by the OSA_TimerCreate function. */ + typedef void *osaTimerId_t; +/*! @brief Type for the Timer callback function pointer. */ + typedef void (*osaTimerFctPtr_t) (void const *argument); +/*! @brief Thread Definition structure contains startup information of a thread.*/ +typedef struct osaThreadDef_tag { + osaTaskPtr_t pthread; /*!< start address of thread function*/ + uint32_t tpriority; /*!< initial thread priority*/ + uint32_t instances; /*!< maximum number of instances of that thread function*/ + uint32_t stacksize; /*!< stack size requirements in bytes; 0 is default stack size*/ + uint32_t *tstack; + void *tlink; + uint8_t *tname; + bool_t useFloat; +} osaThreadDef_t; +/*! @brief Thread Link Definition structure .*/ +typedef struct osaThreadLink_tag{ + uint8_t link[12]; + osaTaskId_t osThreadId; + osaThreadDef_t *osThreadDefHandle; + uint32_t *osThreadStackHandle; +}osaThreadLink_t, *osaThreadLinkHandle_t; + +/*! @Timer Definition structure contains timer parameters.*/ +typedef struct osaTimerDef_tag { + osaTimerFctPtr_t pfCallback; /* < start address of a timer function */ + void *argument; +} osaTimerDef_t; +/*! @brief Defines the return status of OSA's functions */ +typedef enum osaStatus_tag +{ + osaStatus_Success = 0U, /*!< Success */ + osaStatus_Error = 1U, /*!< Failed */ + osaStatus_Timeout = 2U, /*!< Timeout occurs while waiting */ + osaStatus_Idle = 3U /*!< Used for bare metal only, the wait object is not ready + and timeout still not occur */ +}osaStatus_t; + + +/*! ********************************************************************************* +************************************************************************************* +* Public macros +************************************************************************************* +********************************************************************************** */ +#if defined (FSL_RTOS_MQX) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_FREE_RTOS) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_UCOSII) + #define USE_RTOS 1 +#elif defined (FSL_RTOS_UCOSIII) + #define USE_RTOS 1 +#else + #define USE_RTOS 0 +#endif + +#define OSA_PRIORITY_IDLE (6) +#define OSA_PRIORITY_LOW (5) +#define OSA_PRIORITY_BELOW_NORMAL (4) +#define OSA_PRIORITY_NORMAL (3) +#define OSA_PRIORITY_ABOVE_NORMAL (2) +#define OSA_PRIORITY_HIGH (1) +#define OSA_PRIORITY_REAL_TIME (0) +#define OSA_TASK_PRIORITY_MAX (0) +#define OSA_TASK_PRIORITY_MIN (15) +#define SIZE_IN_UINT32_UNITS(size) (((size) + sizeof(uint32_t) - 1) / sizeof(uint32_t)) + +/*! @brief Constant to pass as timeout value in order to wait indefinitely. */ +#define osaWaitForever_c ((uint32_t)(-1)) +#define osaEventFlagsAll_c ((osaEventFlags_t)(0x00FFFFFF)) +#define osThreadStackArray(name) osThread_##name##_stack +#define osThreadStackDef(name, stacksize, instances) \ + uint32_t osThreadStackArray(name)[SIZE_IN_UINT32_UNITS(stacksize)*(instances)]; + +/* ==== Thread Management ==== */ + +/* Create a Thread Definition with function, priority, and stack requirements. + * \param name name of the thread function. + * \param priority initial priority of the thread function. + * \param instances number of possible thread instances. + * \param stackSz stack size (in bytes) requirements for the thread function. + * \param useFloat + */ +#if defined(FSL_RTOS_MQX) +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadLink_t osThreadLink_##name[instances] = {0}; \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + osThreadLink_##name, \ + (uint8_t*) #name,\ + (useFloat)} +#elif defined (FSL_RTOS_UCOSII) + #if gTaskMultipleInstancesManagement_c +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadLink_t osThreadLink_##name[instances] = {0}; \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + osThreadLink_##name, \ + (uint8_t*) #name,\ + (useFloat)} +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osThreadStackDef(name, stackSz, instances) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + osThreadStackArray(name), \ + NULL, \ + (uint8_t*) #name,\ + (useFloat)} +#endif +#else +#define OSA_TASK_DEFINE(name, priority, instances, stackSz, useFloat) \ +osaThreadDef_t os_thread_def_##name = { (name), \ + (priority), \ + (instances), \ + (stackSz), \ + NULL, \ + NULL, \ + (uint8_t*) #name,\ + (useFloat)} +#endif +/* Access a Thread defintion. + * \param name name of the thread definition object. + */ +#define OSA_TASK(name) \ +&os_thread_def_##name + +#define OSA_TASK_PROTO(name) \ +extern osaThreadDef_t os_thread_def_##name +/* ==== Timer Management ==== + * Define a Timer object. + * \param name name of the timer object. + * \param function name of the timer call back function. + */ + +#define OSA_TIMER_DEF(name, function) \ +osaTimerDef_t os_timer_def_##name = \ +{ (function), NULL } + +/* Access a Timer definition. + * \param name name of the timer object. + */ +#define OSA_TIMER(name) \ +&os_timer_def_##name + + +/***************************************************************************** +****************************************************************************** +* Public memory declarations +****************************************************************************** +*****************************************************************************/ +extern const uint8_t gUseRtos_c; + + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ +/*! + * @name Task management + * @{ + */ + +/*! + * @brief Creates a task. + * + * This function is used to create task based on the resources defined + * by the macro OSA_TASK_DEFINE. + * + * @param thread_def pointer to the osaThreadDef_t structure which defines the task. + * @param task_param Pointer to be passed to the task when it is created. + * + * @retval taskId The task is successfully created. + * @retval NULL The task can not be created.. + * + * Example: + @code + osaTaskId_t taskId; + OSA_TASK_DEFINE( Job1, OSA_PRIORITY_HIGH, 1, 800, 0);; + taskId = OSA__TaskCreate(OSA__TASK(Job1), (osaTaskParam_t)NULL); + @endcode + */ +osaTaskId_t OSA_TaskCreate(osaThreadDef_t *thread_def, osaTaskParam_t task_param); + +/*! + * @brief Gets the handler of active task. + * + * @return Handler to current active task. + */ +osaTaskId_t OSA_TaskGetId(void); + +/*! + * @brief Puts the active task to the end of scheduler's queue. + * + * When a task calls this function, it gives up the CPU and puts itself to the + * end of a task ready list. + * + * @retval osaStatus_Success The function is called successfully. + * @retval osaStatus_Error Error occurs with this function. + */ +osaStatus_t OSA_TaskYield(void); + +/*! + * @brief Gets the priority of a task. + * + * @param taskId The handler of the task whose priority is received. + * + * @return Task's priority. + */ +osaTaskPriority_t OSA_TaskGetPriority(osaTaskId_t taskId); + +/*! + * @brief Sets the priority of a task. + * + * @param taskId The handler of the task whose priority is set. + * @param taskPriority The priority to set. + * + * @retval osaStatus_Success Task's priority is set successfully. + * @retval osaStatus_Error Task's priority can not be set. + */ +osaStatus_t OSA_TaskSetPriority(osaTaskId_t taskId, osaTaskPriority_t taskPriority); +/*! + * @brief Destroys a previously created task. + * + * @param taskId The handler of the task to destroy. Returned by the OSA_TaskCreate function. + * + * @retval osaStatus_Success The task was successfully destroyed. + * @retval osaStatus_Error Task destruction failed or invalid parameter. + */ +osaStatus_t OSA_TaskDestroy(osaTaskId_t taskId); + +/*! + * @brief Creates a semaphore with a given value. + * + * This function creates a semaphore and sets the value to the parameter + * initValue. + * + * @param initValue Initial value the semaphore will be set to. + * + * @retval handler to the new semaphore if the semaphore is created successfully. + * @retval NULL if the semaphore can not be created. + * + * + */ +osaSemaphoreId_t OSA_SemaphoreCreate(uint32_t initValue); + +/*! + * @brief Destroys a previously created semaphore. + * + * @param semId Pointer to the semaphore to destroy. + * + * @retval osaStatus_Success The semaphore is successfully destroyed. + * @retval osaStatus_Error The semaphore can not be destroyed. + */ +osaStatus_t OSA_SemaphoreDestroy(osaSemaphoreId_t semId); + +/*! + * @brief Pending a semaphore with timeout. + * + * This function checks the semaphore's counting value. If it is positive, + * decreases it and returns osaStatus_Success. Otherwise, a timeout is used + * to wait. + * + * @param semId Pointer to the semaphore. + * @param millisec The maximum number of milliseconds to wait if semaphore is not + * positive. Pass osaWaitForever_c to wait indefinitely, pass 0 + * will return osaStatus_Timeout immediately. + * + * @retval osaStatus_Success The semaphore is received. + * @retval osaStatus_Timeout The semaphore is not received within the specified 'timeout'. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_SemaphoreWait(osaSemaphoreId_t semId, uint32_t millisec); + +/*! + * @brief Signals for someone waiting on the semaphore to wake up. + * + * Wakes up one task that is waiting on the semaphore. If no task is waiting, increases + * the semaphore's counting value. + * + * @param semId Pointer to the semaphore to signal. + * + * @retval osaStatus_Success The semaphore is successfully signaled. + * @retval osaStatus_Error The object can not be signaled or invalid parameter. + * + */ +osaStatus_t OSA_SemaphorePost(osaSemaphoreId_t semId); + +/*! + * @brief Create an unlocked mutex. + * + * This function creates a non-recursive mutex and sets it to unlocked status. + * + * @param none. + * + * @retval handler to the new mutex if the mutex is created successfully. + * @retval NULL if the mutex can not be created. + */ +osaMutexId_t OSA_MutexCreate(void); + +/*! + * @brief Waits for a mutex and locks it. + * + * This function checks the mutex's status. If it is unlocked, locks it and returns the + * osaStatus_Success. Otherwise, waits for a timeout in milliseconds to lock. + * + * @param mutexId Pointer to the Mutex. + * @param millisec The maximum number of milliseconds to wait for the mutex. + * If the mutex is locked, Pass the value osaWaitForever_c will + * wait indefinitely, pass 0 will return osaStatus_Timeout + * immediately. + * + * @retval osaStatus_Success The mutex is locked successfully. + * @retval osaStatus_Timeout Timeout occurred. + * @retval osaStatus_Error Incorrect parameter was passed. + * + * @note This is non-recursive mutex, a task can not try to lock the mutex it has locked. + */ +osaStatus_t OSA_MutexLock(osaMutexId_t mutexId, uint32_t millisec); + +/*! + * @brief Unlocks a previously locked mutex. + * + * @param mutexId Pointer to the Mutex. + * + * @retval osaStatus_Success The mutex is successfully unlocked. + * @retval osaStatus_Error The mutex can not be unlocked or invalid parameter. + */ +osaStatus_t OSA_MutexUnlock(osaMutexId_t mutexId); + +/*! + * @brief Destroys a previously created mutex. + * + * @param mutexId Pointer to the Mutex. + * + * @retval osaStatus_Success The mutex is successfully destroyed. + * @retval osaStatus_Error The mutex can not be destroyed. + * + */ +osaStatus_t OSA_MutexDestroy(osaMutexId_t mutexId); + +/*! + * @brief Initializes an event object with all flags cleared. + * + * This function creates an event object and set its clear mode. If autoClear + * is TRUE, when a task gets the event flags, these flags will be + * cleared automatically. Otherwise these flags must + * be cleared manually. + * + * @param autoClear TRUE The event is auto-clear. + * FALSE The event manual-clear + * @retval handler to the new event if the event is created successfully. + * @retval NULL if the event can not be created. + */ +osaEventId_t OSA_EventCreate(bool_t autoClear); + +/*! + * @brief Sets one or more event flags. + * + * Sets specified flags of an event object. + * + * @param eventId Pointer to the event. + * @param flagsToSet Flags to be set. + * + * @retval osaStatus_Success The flags were successfully set. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_EventSet(osaEventId_t eventId, osaEventFlags_t flagsToSet); + +/*! + * @brief Clears one or more flags. + * + * Clears specified flags of an event object. + * + * @param eventId Pointer to the event. + * @param flagsToClear Flags to be clear. + * + * @retval osaStatus_Success The flags were successfully cleared. + * @retval osaStatus_Error An incorrect parameter was passed. + */ +osaStatus_t OSA_EventClear(osaEventId_t eventId, osaEventFlags_t flagsToClear); + +/*! + * @brief Waits for specified event flags to be set. + * + * This function waits for a combination of flags to be set in an event object. + * Applications can wait for any/all bits to be set. Also this function could + * obtain the flags who wakeup the waiting task. + * + * @param eventId Pointer to the event. + * @param flagsToWait Flags that to wait. + * @param waitAll Wait all flags or any flag to be set. + * @param millisec The maximum number of milliseconds to wait for the event. + * If the wait condition is not met, pass osaWaitForever_c will + * wait indefinitely, pass 0 will return osaStatus_Timeout + * immediately. + * @param setFlags Flags that wakeup the waiting task are obtained by this parameter. + * + * @retval osaStatus_Success The wait condition met and function returns successfully. + * @retval osaStatus_Timeout Has not met wait condition within timeout. + * @retval osaStatus_Error An incorrect parameter was passed. + + * + * @note Please pay attention to the flags bit width, FreeRTOS uses the most + * significant 8 bis as control bits, so do not wait these bits while using + * FreeRTOS. + * + */ +osaStatus_t OSA_EventWait(osaEventId_t eventId, osaEventFlags_t flagsToWait, bool_t waitAll, uint32_t millisec, osaEventFlags_t *pSetFlags); + +/*! + * @brief Destroys a previously created event object. + * + * @param eventId Pointer to the event. + * + * @retval osaStatus_Success The event is successfully destroyed. + * @retval osaStatus_Error Event destruction failed. + */ +osaStatus_t OSA_EventDestroy(osaEventId_t eventId); + +/*! + * @brief Initializes a message queue. + * + * This function allocates memory for and initializes a message queue. Message queue elements are hardcoded as void*. + * + * @param msgNo :number of messages the message queue should accommodate. + * This parameter should not exceed osNumberOfMessages defined in OSAbstractionConfig.h. + * +* @return: Handler to access the queue for put and get operations. If message queue + * creation failed, return NULL. + */ +osaMsgQId_t OSA_MsgQCreate(uint32_t msgNo); + +/*! + * @brief Puts a message at the end of the queue. + * + * This function puts a message to the end of the message queue. If the queue + * is full, this function returns the osaStatus_Error; + * + * @param msgQId pointer to queue returned by the OSA_MsgQCreate function. + * @param pMessage Pointer to the message to be put into the queue. + * + * @retval osaStatus_Success Message successfully put into the queue. + * @retval osaStatus_Error The queue was full or an invalid parameter was passed. + */ +osaStatus_t OSA_MsgQPut(osaMsgQId_t msgQId, osaMsg_t pMessage); + +/*! + * @brief Reads and remove a message at the head of the queue. + * + * This function gets a message from the head of the message queue. If the + * queue is empty, timeout is used to wait. + * + * @param msgQId Queue handler returned by the OSA_MsgQCreate function. + * @param pMessage Pointer to a memory to save the message. + * @param millisec The number of milliseconds to wait for a message. If the + * queue is empty, pass osaWaitForever_c will wait indefinitely, + * pass 0 will return osaStatus_Timeout immediately. + * + * @retval osaStatus_Success Message successfully obtained from the queue. + * @retval osaStatus_Timeout The queue remains empty after timeout. + * @retval osaStatus_Error Invalid parameter. + */ +osaStatus_t OSA_MsgQGet(osaMsgQId_t msgQId, osaMsg_t pMessage, uint32_t millisec); + +/*! + * @brief Destroys a previously created queue. + * + * @param msgQId queue handler returned by the OSA_MsgQCreate function. + * + * @retval osaStatus_Success The queue was successfully destroyed. + * @retval osaStatus_Error Message queue destruction failed. +*/ +osaStatus_t OSA_MsgQDestroy(osaMsgQId_t msgQId); + +/*! + * @brief Enable all interrupts. +*/ +void OSA_InterruptEnable(void); + +/*! + * @brief Disable all interrupts. +*/ +void OSA_InterruptDisable(void); + +/*! + * @brief Enable all interrupts using PRIMASK. +*/ +void OSA_EnableIRQGlobal(void); + +/*! + * @brief Disable all interrupts using PRIMASK. +*/ +void OSA_DisableIRQGlobal(void); + +/*! + * @brief Delays execution for a number of milliseconds. + * + * @param millisec The time in milliseconds to wait. + */ +void OSA_TimeDelay(uint32_t millisec); + +/*! + * @brief This function gets current time in milliseconds. + * + * @retval current time in milliseconds + */ +uint32_t OSA_TimeGetMsec(void); + +/*! + * @brief Installs the interrupt handler. + * + * @param IRQNumber IRQ number of the interrupt. + * @param handler The interrupt handler to install. + */ +void OSA_InstallIntHandler(uint32_t IRQNumber, void (*handler)(void)); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Interface/fsl_os_abstraction_config.h b/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Interface/fsl_os_abstraction_config.h new file mode 100644 index 000000000..43d2927c6 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Interface/fsl_os_abstraction_config.h @@ -0,0 +1,63 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + + +#ifndef _FSL_OS_ABSTRACTION_CONFIG_H_ +#define _FSL_OS_ABSTRACTION_CONFIG_H_ + +#ifndef osNumberOfSemaphores +#define osNumberOfSemaphores 5 +#endif +#ifndef osNumberOfMutexes +#define osNumberOfMutexes 5 +#endif +#ifndef osNumberOfMessageQs +#define osNumberOfMessageQs 0 +#endif +#ifndef osNumberOfMessages +#define osNumberOfMessages 10 +#endif +#ifndef osNumberOfEvents +#define osNumberOfEvents 5 +#endif + +#ifndef gMainThreadStackSize_c +#define gMainThreadStackSize_c 1024 +#endif +#ifndef gMainThreadPriority_c +#define gMainThreadPriority_c 7 +#endif + +#ifndef gTaskMultipleInstancesManagement_c +#define gTaskMultipleInstancesManagement_c 0 +#endif +#endif /* _FSL_OS_ABSTRACTION_CONFIG_H_ */ diff --git a/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Source/fsl_os_abstraction_zephyr.c b/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Source/fsl_os_abstraction_zephyr.c new file mode 100644 index 000000000..514f18690 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/OSAbstraction/Source/fsl_os_abstraction_zephyr.c @@ -0,0 +1,29 @@ +#include +#include +#include + +#include "fsl_os_abstraction.h" + +unsigned int gIrqKey; + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptEnable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptEnable(void) +{ + irq_unlock(gIrqKey); +} + +/*FUNCTION********************************************************************** + * + * Function Name : OSA_InterruptDisable + * Description : self explanatory. + * + *END**************************************************************************/ +void OSA_InterruptDisable(void) +{ + gIrqKey = irq_lock(); +} diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/BLEDefaults.h b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/BLEDefaults.h new file mode 100644 index 000000000..bfaa0e9b1 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/BLEDefaults.h @@ -0,0 +1,433 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* \file BLEDefaults.h +* This is a header file for the default register values of the transceiver +* used for BLE mode. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef __BLE_DEFAULTS_H__ +#define __BLE_DEFAULTS_H__ + + +/*! ********************************************************************************* +************************************************************************************* +* Constants +************************************************************************************* +********************************************************************************** */ +#define USE_DCOC_MAGIC_NUMBERS 0 /* Set to 1 to use RAW register settings */ +#define OVERRIDE_ADC_SCALE_FACTOR 1 /* Use a manually defined ADC_SCALE_FACTOR */ + + +/* XCVR_CTRL Defaults */ + +/* XCVR_CTRL */ +#define BLE_TGT_PWR_SRC_def_c 0x01 +#define BLE_PROTOCOL_def_c 0x00 + +/* TSM Defaults (no PA ramp)*/ + +/*TSM_CTRL*/ +#define BKPT_def_c 0xff +#define ABORT_ON_FREQ_TARG_def_c 0x00 +#define ABORT_ON_CYCLE_SLIP_def_c 0x00 +#define ABORT_ON_CTUNE_def_c 0x00 +#define RX_ABORT_DIS_def_c 0x00 +#define TX_ABORT_DIS_def_c 0x00 +#define DATA_PADDING_EN_def_c 0x01 /* Turn on Data Padding */ +#define PA_RAMP_SEL_def_c 0x01 /* Use 2uS Ramp */ +#define FORCE_RX_EN_def_c 0x00 +#define FORCE_TX_EN_def_c 0x00 + +/*PA_POWER*/ +#define PA_POWER_def_c 0x00 + +/*PA_BIAS_TBL0*/ +#define PA_BIAS3_def_c 0x00 +#define PA_BIAS2_def_c 0x00 +#define PA_BIAS1_def_c 0x00 +#define PA_BIAS0_def_c 0x00 + +/*PA_BIAS_TBL1*/ +#define PA_BIAS7_def_c 0x00 +#define PA_BIAS6_def_c 0x00 +#define PA_BIAS5_def_c 0x00 +#define PA_BIAS4_def_c 0x00 + +/*DATA_PAD_CTRL*/ +#define DATA_PAD_1ST_IDX_55_def_c 0x3E +#define DATA_PAD_1ST_IDX_AA_def_c 0x1E + +/*TX DIG, PLL DIG */ +#define HPM_LSB_INVERT_def_c 0x3 +#define HPM_DENOM_def_c 0x100 +#define HPM_BANK_DELAY_def_c 0x4 +#define HPM_SDM_DELAY_def_c 0x2 +#define LP_SDM_DELAY_def_c 0x9 +#define PLL_LFILT_CNTL_def_c 0x03 +#define FSK_MODULATION_SCALE_1_def_c 0x0800 + +/*Analog: BBW Filter */ + +/* XCVR_TZA_CTRL */ +#define BLE_TZA_CAP_TUNE_def_c 3 + +/* XCVR_BBF_CTRL */ +#define BLE_BBF_CAP_TUNE_def_c 4 +#define BLE_BBF_RES_TUNE2_def_c 6 + +/*RX DIG: AGC, DCOC, and filtering */ + +/*RX_CHF_COEFn*/ +/*Dig Channel- 580kHz (no IIR), 545kHz (with 700kHz IIR) */ +#define RX_CHF_COEF0_def_c 0xFE +#define RX_CHF_COEF1_def_c 0xFC +#define RX_CHF_COEF2_def_c 0xFA +#define RX_CHF_COEF3_def_c 0xFC +#define RX_CHF_COEF4_def_c 0x03 +#define RX_CHF_COEF5_def_c 0x0F +#define RX_CHF_COEF6_def_c 0x1B +#define RX_CHF_COEF7_def_c 0x23 + +/*RX_DIG_CTRL*/ +#define RX_DIG_CTRL_def_c 0x10 +#define RX_CH_FILT_BYPASS_def_c 0x00 +#define RX_DEC_FILT_OSR_BLE_def_c 0x01 +#define RX_INTERP_EN_def_c 0x00 +#define RX_NORM_EN_BLE_def_c 0x00 +#define RX_RSSI_EN_def_c 0x01 +#define RX_AGC_EN_def_c 0x01 +#define RX_DCOC_EN_def_c 0x01 +#define RX_DCOC_CAL_EN_def_c 0x01 + +/* AGC_CTRL */ +/* AGC_CTRL_0 */ +#define AGC_DOWN_RSSI_THRESH_def_c 0xFF +#define AGC_UP_RSSI_THRESH_def_c 0xd0 +#define AGC_DOWN_TZA_STEP_SZ_def_c 0x04 +#define AGC_DOWN_BBF_STEP_SZ_def_c 0x02 +#define AGC_UP_SRC_def_c 0x00 +#define AGC_UP_EN_def_c 0x01 +#define FREEZE_AGC_SRC_def_c 0x02 +#define AGC_FREEZE_EN_def_c 0x01 +#define SLOW_AGC_SRC_def_c 0x02 +#define SLOW_AGC_EN_def_c 0x01 + +/* AGC_CTRL_1 */ +#define TZA_GAIN_SETTLE_TIME_def_c 0x0c +#define PRESLOW_EN_def_c 0x01 +#define USER_BBF_GAIN_EN_def_c 0x00 +#define USER_LNM_GAIN_EN_def_c 0x00 +#define BBF_USER_GAIN_def_c 0x00 +#define LNM_USER_GAIN_def_c 0x00 +#define LNM_ALT_CODE_def_c 0x00 +#define BBF_ALT_CODE_def_c 0x00 + +/* AGC_CTRL_2 */ +#define AGC_FAST_EXPIRE_def_c 0x2 +#define TZA_PDET_THRESH_HI_def_c 0x02 +#define TZA_PDET_THRESH_LO_def_c 0x01 +#define BBF_PDET_THRESH_HI_def_c 0x06 +#define BBF_PDET_THRESH_LO_def_c 0x01 +#define BBF_GAIN_SETTLE_TIME_def_c 0x0c +#define TZA_PDET_RST_def_c 0x00 +#define BBF_PDET_RST_def_c 0x00 + +/* AGC_CTRL_3 */ +#define AGC_UP_STEP_SZ_def_c 0x02 +#define AGC_H2S_STEP_SZ_def_c 0x18 +#define AGC_RSSI_DELT_H2S_def_c 0x0e +#define AGC_PDET_LO_DLY_def_c 0x07 +#define AGC_UNFREEZE_TIME_def_c 0xfff + +/* RSSI_CTRL 0*/ +#define RSSI_ADJ_def_c 0x00 +#define RSSI_IIR_WEIGHT_def_c 0x03 +#define RSSI_IIR_CW_WEIGHT_ENABLEDdef_c 0x02 +#define RSSI_IIR_CW_WEIGHT_BYPASSEDdef_c 0x00 +#define RSSI_DEC_EN_def_c 0x01 +#define RSSI_HOLD_EN_def_c 0x01 +#define RSSI_HOLD_SRC_def_c 0x00 +#define RSSI_USE_VALS_def_c 0x01 + +/* RSSI_CTRL_1 */ +#define RSSI_ED_THRESH1_H_def_c 0x04 +#define RSSI_ED_THRESH0_H_def_c 0x04 +#define RSSI_ED_THRESH1_def_c 0xAC +#define RSSI_ED_THRESH0_def_c 0xA4 + +/* AGC_GAIN_TBL_03_00 */ +#define LNM_GAIN_00_def_c 0x00 +#define BBF_GAIN_00_def_c 0x00 +#define LNM_GAIN_01_def_c 0x00 +#define BBF_GAIN_01_def_c 0x00 +#define LNM_GAIN_02_def_c 0x00 +#define BBF_GAIN_02_def_c 0x01 +#define LNM_GAIN_03_def_c 0x01 +#define BBF_GAIN_03_def_c 0x00 + +/* AGC_GAIN_TBL_07_04 */ +#define LNM_GAIN_04_def_c 0x01 +#define BBF_GAIN_04_def_c 0x01 +#define LNM_GAIN_05_def_c 0x02 +#define BBF_GAIN_05_def_c 0x01 +#define LNM_GAIN_06_def_c 0x02 +#define BBF_GAIN_06_def_c 0x02 +#define LNM_GAIN_07_def_c 0x02 +#define BBF_GAIN_07_def_c 0x03 + +/* AGC_GAIN_TBL_11_08 */ +#define LNM_GAIN_08_def_c 0x02 +#define BBF_GAIN_08_def_c 0x04 +#define LNM_GAIN_09_def_c 0x03 +#define BBF_GAIN_09_def_c 0x03 +#define LNM_GAIN_10_def_c 0x03 +#define BBF_GAIN_10_def_c 0x04 +#define LNM_GAIN_11_def_c 0x03 +#define BBF_GAIN_11_def_c 0x05 + +/* AGC_GAIN_TBL_15_12 */ +#define LNM_GAIN_12_def_c 0x04 +#define BBF_GAIN_12_def_c 0x04 +#define LNM_GAIN_13_def_c 0x04 +#define BBF_GAIN_13_def_c 0x05 +#define LNM_GAIN_14_def_c 0x04 +#define BBF_GAIN_14_def_c 0x06 +#define LNM_GAIN_15_def_c 0x05 +#define BBF_GAIN_15_def_c 0x05 + +/* AGC_GAIN_TBL_19_16 */ +#define LNM_GAIN_16_def_c 0x05 +#define BBF_GAIN_16_def_c 0x06 +#define LNM_GAIN_17_def_c 0x05 +#define BBF_GAIN_17_def_c 0x07 +#define LNM_GAIN_18_def_c 0x06 +#define BBF_GAIN_18_def_c 0x06 +#define LNM_GAIN_19_def_c 0x06 +#define BBF_GAIN_19_def_c 0x07 + +/* AGC_GAIN_TBL_23_20 */ +#define LNM_GAIN_20_def_c 0x06 +#define BBF_GAIN_20_def_c 0x08 +#define LNM_GAIN_21_def_c 0x07 +#define BBF_GAIN_21_def_c 0x07 +#define LNM_GAIN_22_def_c 0x07 +#define BBF_GAIN_22_def_c 0x08 +#define LNM_GAIN_23_def_c 0x07 +#define BBF_GAIN_23_def_c 0x09 + +/* AGC_GAIN_TBL_26_24 */ +#define LNM_GAIN_24_def_c 0x08 +#define BBF_GAIN_24_def_c 0x08 +#define LNM_GAIN_25_def_c 0x08 +#define BBF_GAIN_25_def_c 0x09 +#define LNM_GAIN_26_def_c 0x08 +#define BBF_GAIN_26_def_c 0x0A + +/* TCA_AGC gain adjust */ +#define TCA_AGC_VAL_0_def_c 0x1E +#define TCA_AGC_VAL_1_def_c 0x34 +#define TCA_AGC_VAL_2_def_c 0x25 +#define TCA_AGC_VAL_3_def_c 0x3B +#define TCA_AGC_VAL_4_def_c 0x51 +#define TCA_AGC_VAL_5_def_c 0x69 +#define TCA_AGC_VAL_6_def_c 0x81 +#define TCA_AGC_VAL_7_def_c 0x99 +#define TCA_AGC_VAL_8_def_c 0xB1 + +/* BBF_RES_TUNE gain adjust */ +#define BBF_RES_TUNE_VAL_0_def_c 0x00 +#define BBF_RES_TUNE_VAL_1_def_c 0x00 +#define BBF_RES_TUNE_VAL_2_def_c 0x00 +#define BBF_RES_TUNE_VAL_3_def_c 0x01 +#define BBF_RES_TUNE_VAL_4_def_c 0x01 +#define BBF_RES_TUNE_VAL_5_def_c 0x00 +#define BBF_RES_TUNE_VAL_6_def_c 0x00 +#define BBF_RES_TUNE_VAL_7_def_c 0x00 +#define BBF_RES_TUNE_VAL_8_def_c 0x01 +#define BBF_RES_TUNE_VAL_9_def_c 0x02 +#define BBF_RES_TUNE_VAL_10_def_c 0x02 + + +/*! ********************************************************************************* +* DCOC can be setup based on a set of raw register values (MAGIC NUMBERS) +* or based on a set of equations which allow for easier correction of DCOC +* operation during debug or testing. Setting the USE_DCOC_MAGIC_NUMBERS flag +* selects the use of raw register values +********************************************************************************** */ + +/* Common DCOC settings, independent of USE_DCOC_MAGIC_NUMBERS flag */ +/* DCOC_CTRL_0 */ +#define DCOC_CAL_DURATION_def_c 0x12 /* Max: 1F */ +#define DCOC_CORR_HOLD_TIME_def_c 0x51 /* Max: 7F - track continuously */ +#define DCOC_CORR_DLY_def_c 0x0C +#define ALPHA_RADIUS_IDX_def_c 0x03 +#define ALPHAC_SCALE_IDX_def_c 0x01 +#define SIGN_SCALE_IDX_def_c 0x03 +#define DCOC_CORRECT_EN_def_c 0x01 +#define DCOC_TRACK_EN_def_c 0x01 +#define DCOC_MAN_def_c 0x00 + +/* DCOC Tracking & GearShift Control (Misc Registers) */ +#define DCOC_ALPHA_RADIUS_GS_IDX_def_c 05 /* Register: XCVR_ADC_TEST_CTRL */ +#define DCOC_ALPHAC_SCALE_GS_IDX_def_c 01 /* Register: XCVR_BBF_CTRL */ +#define DCOC_TRK_EST_GS_CNT_def_c 00 /* Register: XCVR_ANA_SPARE */ +#define IQMC_DC_GAIN_ADJ_EN_def_c 01 /* Register: XCVR_RX_ANA_CTRL */ + +/* DCOC_CTRL_1 */ +#define TZA_CORR_POL_def_c 1 +#define BBF_CORR_POL_def_c 1 +#define TRACK_FROM_ZERO_def_c 0 + +/* DCOC_CAL_GAIN */ +#define DCOC_TZA_CAL_GAIN1_def_c 0x04 +#define DCOC_BBF_CAL_GAIN1_def_c 0x04 +#define DCOC_TZA_CAL_GAIN2_def_c 0x08 +#define DCOC_BBF_CAL_GAIN2_def_c 0x04 +#define DCOC_TZA_CAL_GAIN3_def_c 0x04 +#define DCOC_BBF_CAL_GAIN3_def_c 0x08 + +/* DCOC_CAL_IIR */ +#define DCOC_CAL_IIR3A_IDX_def_c 0x01 +#define DCOC_CAL_IIR2A_IDX_def_c 0x02 +#define DCOC_CAL_IIR1A_IDX_def_c 0x02 + +#if USE_DCOC_MAGIC_NUMBERS /* Define raw register contents */ + +/* DCOC_CAL_RCP */ +#define ALPHA_CALC_RECIP_def_c 0x00 +#define TMP_CALC_RECIP_def_c 0x00 + +/* TCA_AGC_LIN_VAL_2_0 */ +#define TCA_AGC_LIN_VAL_0_def_c 0x00 +#define TCA_AGC_LIN_VAL_1_def_c 0x00 +#define TCA_AGC_LIN_VAL_2_def_c 0x00 + +/* TCA_AGC_LIN_VAL_5_3 */ +#define TCA_AGC_LIN_VAL_3_def_c 0x00 +#define TCA_AGC_LIN_VAL_4_def_c 0x00 +#define TCA_AGC_LIN_VAL_5_def_c 0x00 + +/* TCA_AGC_LIN_VAL_8_6 */ +#define TCA_AGC_LIN_VAL_6_def_c 0x00 +#define TCA_AGC_LIN_VAL_7_def_c 0x00 +#define TCA_AGC_LIN_VAL_8_def_c 0x00 + +/* BBF_RES_TUNE_LIN_VAL_3_0 */ +#define BBF_RES_TUNE_LIN_VAL_0_def_c 0x00 +#define BBF_RES_TUNE_LIN_VAL_1_def_c 0x00 +#define BBF_RES_TUNE_LIN_VAL_2_def_c 0x00 +#define BBF_RES_TUNE_LIN_VAL_3_def_c 0x00 + +/* BBF_RES_TUNE_LIN_VAL_7_4 */ +#define BBF_RES_TUNE_LIN_VAL_4_def_c 0x00 +#define BBF_RES_TUNE_LIN_VAL_5_def_c 0x00 +#define BBF_RES_TUNE_LIN_VAL_6_def_c 0x00 +#define BBF_RES_TUNE_LIN_VAL_7_def_c 0x00 + +/* BBF_RES_TUNE_LIN_VAL_10_8 */ +#define BBF_RES_TUNE_LIN_VAL_0_def_c 0x00 +#define BBF_RES_TUNE_LIN_VAL_0_def_c 0x00 +#define BBF_RES_TUNE_LIN_VAL_0_def_c 0x00 + +/* DCOC_TZA_STEP */ +#define DCOC_TZA_STEP_GAIN_00_def_c 0x00 +#define DCOC_TZA_STEP_RCP_00_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_01_def_c 0x00 +#define DCOC_TZA_STEP_RCP_01_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_02_def_c 0x00 +#define DCOC_TZA_STEP_RCP_02_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_03_def_c 0x00 +#define DCOC_TZA_STEP_RCP_03_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_04_def_c 0x00 +#define DCOC_TZA_STEP_RCP_04_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_05_def_c 0x00 +#define DCOC_TZA_STEP_RCP_05_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_06_def_c 0x00 +#define DCOC_TZA_STEP_RCP_06_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_07_def_c 0x00 +#define DCOC_TZA_STEP_RCP_07_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_08_def_c 0x00 +#define DCOC_TZA_STEP_RCP_08_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_09_def_c 0x00 +#define DCOC_TZA_STEP_RCP_09_def_c 0x00 +#define DCOC_TZA_STEP_GAIN_10_def_c 0x00 +#define DCOC_TZA_STEP_RCP_10_def_c 0x00 + +/* DCOC_CTRL_1 DCOC_CTRL_2 */ +#define BBF_STEP_def_c 0x00 +#define BBF_STEP_RECIP_def_c 0x00 + +/* DCOC_CAL_RCP */ +#define RCP_GLHmGLLxGBL_def_c 0x00 +#define RCP_GBHmGBL_def_c 0x00 + +#else /* USE_DCOC_MAGIC_NUMBERS == 0 */ + +/* Uses unsigned inputs for val and biaspt */ +#define DCOC_ADD_BIAS(val,biaspt) ((val > biaspt) ? ((val-biaspt)) : ((biaspt+val))) /* Use when taking DCOC_OFFSET_n values to use for manual corrections */ +#define DCOC_REMOVE_BIAS(val,biaspt) ((val >= biaspt) ? ((val-biaspt)) : ((biaspt+val))) /* Use when writing desired values to DCOC_OFFSET_n register. */ + +#define DB_TO_LINEAR(x) (pow(10,((x)/(double)20.0))) +#define ABS(x) ((x) > 0 ? (x) : -(x)) +#define MAX(x,y) ((x) > (y) ? (x) : (y)) +/* This scale factor will be copied to a variable which is overwritten by a trimmed variable if one is available from IFR. */ +#if OVERRIDE_ADC_SCALE_FACTOR +#define ADC_SCALE_FACTOR 2.25 /* Range: 1.8 to 2.2. Different ADC_GAIN needed for DCOC_Q CAL (I/Q gain mismatch) */ +#else +#define ADC_SCALE_FACTOR (DB_TO_LINEAR(-1.7)*(0x800)/((double)(1000))) +#endif +#define TZA_DCOC_STEP_RAW (((1.0)*1200)/((double)(0x100))) +#define BBF_DCOC_STEP_RAW (((1.0)*1200)/((double)(0x40))) + +#define TCA_GAIN_DB_0_def_c ((double)(-0.525)) /* (-3)) */ +#define TCA_GAIN_DB_1_def_c ((double)(4.883)) /* (3)) */ +#define TCA_GAIN_DB_2_def_c ((double)(9.355)) /* (9)) */ +#define TCA_GAIN_DB_3_def_c ((double)(14.731)) /* (15)) */ +#define TCA_GAIN_DB_4_def_c ((double)(20.188)) /* (21)) */ +#define TCA_GAIN_DB_5_def_c ((double)(26.320)) /* (27)) */ +#define TCA_GAIN_DB_6_def_c ((double)(32.309)) /* (33)) */ +#define TCA_GAIN_DB_7_def_c ((double)(38.249)) /* (39)) */ +#define TCA_GAIN_DB_8_def_c ((double)(44.120)) /* (45)) */ + +#define BBF_GAIN_DB_0_def_c ((double)(0)) /* (0)) */ +#define BBF_GAIN_DB_1_def_c ((double)(3.071)) /* (3)) */ +#define BBF_GAIN_DB_2_def_c ((double)(6.144)) /* (6)) */ +#define BBF_GAIN_DB_3_def_c ((double)(9.266)) /* (9)) */ +#define BBF_GAIN_DB_4_def_c ((double)(12.299)) /* (12)) */ +#define BBF_GAIN_DB_5_def_c ((double)(15.242)) /* (15)) */ +#define BBF_GAIN_DB_6_def_c ((double)(18.114)) /* (18)) */ +#define BBF_GAIN_DB_7_def_c ((double)(21.198)) /* (21)) */ +#define BBF_GAIN_DB_8_def_c ((double)(24.584)) /* (24)) */ +#define BBF_GAIN_DB_9_def_c ((double)(27.885)) /* (27)) */ +#define BBF_GAIN_DB_10_def_c ((double)(30.95)) /* (30)) */ + +#endif /* USE_DCOC_MAGIC_NUMBERS */ + +#endif /* __BLE_DEFAULTS_H__*/ \ No newline at end of file diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/CMakeLists.txt b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/CMakeLists.txt new file mode 100644 index 000000000..00cb894f5 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/CMakeLists.txt @@ -0,0 +1,5 @@ +zephyr_library_sources( + ifr_mkw40z4_radio.c + KW4xXcvrDrv.c + tsm_ll_timing.c +) diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/KW4xXcvrDrv.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/KW4xXcvrDrv.c new file mode 100644 index 000000000..184652ea6 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/KW4xXcvrDrv.c @@ -0,0 +1,2332 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* \file KW4xXcvrDrv.c +* This is a source file for the transceiver driver. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "BLEDefaults.h" +#include "ZigbeeDefaults.h" +#include "KW4xXcvrDrv.h" +#include "fsl_os_abstraction.h" +#include "fsl_device_registers.h" + +#include "tsm_ll_timing.h" +#include "ifr_mkw40z4_radio.h" + +#if !USE_DCOC_MAGIC_NUMBERS +#include +#endif + +#ifdef gXcvrXtalTrimEnabled_d +#include "Flash_Adapter.h" +#endif + +#define INCLUDE_OLD_DRV_CODE (0) +#define wait(param) while(param) +#define ASSERT(condition) if(condition) while(1); + +/*! ********************************************************************************* +************************************************************************************* +* Private type definitions +************************************************************************************* +********************************************************************************** */ +typedef enum +{ + FIRST_INIT = 0, + MODE_CHANGE = 1 +} MODE_CHG_SEL_T; + +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ +/* Channel Filter coeff for BLE */ +const uint8_t gBLERxChfCoeff[8] = { + RX_CHF_COEF0_def_c, + RX_CHF_COEF1_def_c, + RX_CHF_COEF2_def_c, + RX_CHF_COEF3_def_c, + RX_CHF_COEF4_def_c, + RX_CHF_COEF5_def_c, + RX_CHF_COEF6_def_c, + RX_CHF_COEF7_def_c +}; + +/* Channel Filter coeff for Zigbee */ +const uint8_t gZigbeeRxChfCoeff[8] = { + RX_CHF_COEF0_Zigbee_def_c, + RX_CHF_COEF1_Zigbee_def_c, + RX_CHF_COEF2_Zigbee_def_c, + RX_CHF_COEF3_Zigbee_def_c, + RX_CHF_COEF4_Zigbee_def_c, + RX_CHF_COEF5_Zigbee_def_c, + RX_CHF_COEF6_Zigbee_def_c, + RX_CHF_COEF7_Zigbee_def_c, +}; + +const uint8_t gPABiasTbl[8] = PA_BIAS_ENTRIES; /* See tsm_timing_ble.h for PA_BIAS_ENTRIES */ +panic_fptr panic_function_ptr = NULL; +uint8_t panic_fptr_is_valid = 0; /* Flag to store validity of the panic function pointer */ +static uint8_t gen1_dcgain_trims_enabled = 0; +static uint8_t HWDCoffsetCal = 0; +static uint32_t trim_status = 0xFFFF; /* Status of trims from IFR, default to all failed */ +static uint16_t ifr_version = 0xFFFF; /* IFR data format version number, default to maxint. */ + +/*! ********************************************************************************* +************************************************************************************* +* Public memory declarations +************************************************************************************* +********************************************************************************** */ +const pllChannel_t mapTable [channelMapTableSize] = +{ + {0x00000025, 0x07C00000}, /* 0 */ + {0x00000025, 0x07C80000}, /* 1 */ + {0x00000025, 0x07D00000}, /* 2 */ + {0x00000025, 0x07D80000}, /* 3 */ + {0x00000025, 0x07E00000}, /* 4 */ + {0x00000025, 0x07E80000}, /* 5 */ + {0x00000025, 0x07F00000}, /* 6 */ + {0x00000025, 0x07F80000}, /* 7 */ + {0x00000025, 0x00000000}, /* 8 */ + {0x00000025, 0x00080000}, /* 9 */ + {0x00000025, 0x00100000}, /* 10 */ + {0x00000025, 0x00180000}, /* 11 */ + {0x00000025, 0x00200000}, /* 12 */ + {0x00000025, 0x00280000}, /* 13 */ + {0x00000025, 0x00300000}, /* 14 */ + {0x00000025, 0x00380000}, /* 15 */ + {0x00000025, 0x00400000}, /* 16 */ + {0x00000025, 0x00480000}, /* 17 */ + {0x00000025, 0x00500000}, /* 18 */ + {0x00000025, 0x00580000}, /* 19 */ + {0x00000025, 0x00600000}, /* 20 */ + {0x00000025, 0x00680000}, /* 21 */ + {0x00000025, 0x00700000}, /* 22 */ + {0x00000025, 0x00780000}, /* 23 */ + {0x00000025, 0x00800000}, /* 24 */ + {0x00000025, 0x00880000}, /* 25 */ + {0x00000025, 0x00900000}, /* 26 */ + {0x00000025, 0x00980000}, /* 27 */ + {0x00000025, 0x00A00000}, /* 28 */ + {0x00000025, 0x00A80000}, /* 29 */ + {0x00000025, 0x00B00000}, /* 30 */ + {0x00000025, 0x00B80000}, /* 31 */ + {0x00000025, 0x00C00000}, /* 32 */ + {0x00000025, 0x00C80000}, /* 33 */ + {0x00000025, 0x00D00000}, /* 34 */ + {0x00000025, 0x00D80000}, /* 35 */ + {0x00000025, 0x00E00000}, /* 36 */ + {0x00000025, 0x00E80000}, /* 37 */ + {0x00000025, 0x00F00000}, /* 38 */ + {0x00000025, 0x00F80000}, /* 39 */ + {0x00000025, 0x01000000}, /* 40 */ + {0x00000026, 0x07080000}, /* 41 */ + {0x00000026, 0x07100000}, /* 42 */ + {0x00000026, 0x07180000}, /* 43 */ + {0x00000026, 0x07200000}, /* 44 */ + {0x00000026, 0x07280000}, /* 45 */ + {0x00000026, 0x07300000}, /* 46 */ + {0x00000026, 0x07380000}, /* 47 */ + {0x00000026, 0x07400000}, /* 48 */ + {0x00000026, 0x07480000}, /* 49 */ + {0x00000026, 0x07500000}, /* 50 */ + {0x00000026, 0x07580000}, /* 51 */ + {0x00000026, 0x07600000}, /* 52 */ + {0x00000026, 0x07680000}, /* 53 */ + {0x00000026, 0x07700000}, /* 54 */ + {0x00000026, 0x07780000}, /* 55 */ + {0x00000026, 0x07800000}, /* 56 */ + {0x00000026, 0x07880000}, /* 57 */ + {0x00000026, 0x07900000}, /* 58 */ + {0x00000026, 0x07980000}, /* 59 */ + {0x00000026, 0x07A00000}, /* 60 */ + {0x00000026, 0x07A80000}, /* 61 */ + {0x00000026, 0x07B00000}, /* 62 */ + {0x00000026, 0x07B80000}, /* 63 */ + {0x00000026, 0x07C00000}, /* 64 */ + {0x00000026, 0x07C80000}, /* 65 */ + {0x00000026, 0x07D00000}, /* 66 */ + {0x00000026, 0x07D80000}, /* 67 */ + {0x00000026, 0x07E00000}, /* 68 */ + {0x00000026, 0x07E80000}, /* 69 */ + {0x00000026, 0x07F00000}, /* 70 */ + {0x00000026, 0x07F80000}, /* 71 */ + {0x00000026, 0x00000000}, /* 72 */ + {0x00000026, 0x00080000}, /* 73 */ + {0x00000026, 0x00100000}, /* 74 */ + {0x00000026, 0x00180000}, /* 75 */ + {0x00000026, 0x00200000}, /* 76 */ + {0x00000026, 0x00280000}, /* 77 */ + {0x00000026, 0x00300000}, /* 78 */ + {0x00000026, 0x00380000}, /* 79 */ + {0x00000026, 0x00400000}, /* 80 */ + {0x00000026, 0x00480000}, /* 81 */ + {0x00000026, 0x00500000}, /* 82 */ + {0x00000026, 0x00580000}, /* 83 */ + {0x00000026, 0x00600000}, /* 84 */ + {0x00000026, 0x00680000}, /* 85 */ + {0x00000026, 0x00700000}, /* 86 */ + {0x00000026, 0x00780000}, /* 87 */ + {0x00000026, 0x00800000}, /* 88 */ + {0x00000026, 0x00880000}, /* 89 */ + {0x00000026, 0x00900000}, /* 90 */ + {0x00000026, 0x00980000}, /* 91 */ + {0x00000026, 0x00A00000}, /* 92 */ + {0x00000026, 0x00A80000}, /* 93 */ + {0x00000026, 0x00B00000}, /* 94 */ + {0x00000026, 0x00B80000}, /* 95 */ + {0x00000026, 0x00C00000}, /* 96 */ + {0x00000026, 0x00C80000}, /* 97 */ + {0x00000026, 0x00D00000}, /* 98 */ + {0x00000026, 0x00D80000}, /* 99 */ + {0x00000026, 0x00E00000}, /* 100 */ + {0x00000026, 0x00E80000}, /* 101 */ + {0x00000026, 0x00F00000}, /* 102 */ + {0x00000026, 0x00F80000}, /* 103 */ + {0x00000026, 0x01000000}, /* 104 */ + {0x00000027, 0x07080000}, /* 105 */ + {0x00000027, 0x07100000}, /* 106 */ + {0x00000027, 0x07180000}, /* 107 */ + {0x00000027, 0x07200000}, /* 108 */ + {0x00000027, 0x07280000}, /* 109 */ + {0x00000027, 0x07300000}, /* 110 */ + {0x00000027, 0x07380000}, /* 111 */ + {0x00000027, 0x07400000}, /* 112 */ + {0x00000027, 0x07480000}, /* 113 */ + {0x00000027, 0x07500000}, /* 114 */ + {0x00000027, 0x07580000}, /* 115 */ + {0x00000027, 0x07600000}, /* 116 */ + {0x00000027, 0x07680000}, /* 117 */ + {0x00000027, 0x07700000}, /* 118 */ + {0x00000027, 0x07780000}, /* 119 */ + {0x00000027, 0x07800000}, /* 120 */ + {0x00000027, 0x07880000}, /* 121 */ + {0x00000027, 0x07900000}, /* 122 */ + {0x00000027, 0x07980000}, /* 123 */ + {0x00000027, 0x07A00000}, /* 124 */ + {0x00000027, 0x07A80000}, /* 125 */ + {0x00000027, 0x07B00000}, /* 126 */ + {0x00000027, 0x07B80000} /* 127 */ +}; + +/* Following are software trimmed values. They are initialized to potential + * blind trim values with the intent that IFR trims overwrite these blind + * trim values + */ +float adc_gain_trimmed = ADC_SCALE_FACTOR; +uint8_t zb_tza_cap_tune = ZGBE_TZA_CAP_TUNE_def_c; +uint8_t zb_bbf_cap_tune = ZGBE_BBF_CAP_TUNE_def_c; +uint8_t zb_bbf_res_tune2 = ZGBE_BBF_RES_TUNE2_def_c; +uint8_t ble_tza_cap_tune = BLE_TZA_CAP_TUNE_def_c; +uint8_t ble_bbf_cap_tune = BLE_BBF_CAP_TUNE_def_c; +uint8_t ble_bbf_res_tune2 = BLE_BBF_RES_TUNE2_def_c; + +/*! ********************************************************************************* +************************************************************************************* +* Private prototypes +************************************************************************************* +********************************************************************************** */ +/* Common initialization and mode change routine, called by XcvrInit() and XcvRModeChange() */ +void XcvrInit_ModeChg_Common ( radio_mode_t radioMode, MODE_CHG_SEL_T mode_change ); + +xcvrStatus_t XcvrCalcSetupDcoc ( void ); +void XcvrManualDCOCCal (uint8_t chnum); + +void XcvrSetTsmDefaults ( radio_mode_t radioMode ); +void XcvrSetRxDigDefaults ( const uint8_t * filt_coeff_ptr, uint8_t iir3a_idx, uint8_t iir2a_idx, uint8_t iir1a_idx, uint8_t rssi_hold_src ); +void XcvrSetTxDigPLLDefaults( radio_mode_t radioMode ); +void XcvrSetAnalogDefaults ( radio_mode_t radioMode ); + +/* Separate out Mode Switch portion of init routines + * call these routines with the target mode during a mode switch + */ +void XcvrSetTsmDef_ModeSwitch ( radio_mode_t radioMode ); +void XcvrSetRxDigDef_ModeSwitch ( const uint8_t * filt_coeff_ptr, uint8_t iir3a_idx, uint8_t iir2a_idx, uint8_t iir1a_idx, uint8_t rssi_hold_src ); +void XcvrSetTxDigPLLDef_ModeSwitch( radio_mode_t radioMode ); +void XcvrSetAnalogDef_ModeSwitch ( radio_mode_t radioMode ); + +void XcvrPanic (uint32_t panic_id, uint32_t location); +void XcvrDelay(uint32_t time); + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +* \brief This function initializes the transceiver for operation in a particular +* radioMode (BLE or Zigbee) +* +* \param[in] radioMode - the operating mode to which the radio should be initialized. +* +* \ingroup PublicAPIs +* +* \details +* +***********************************************************************************/ +void XcvrInit ( radio_mode_t radioMode ) +{ + XcvrInit_ModeChg_Common(radioMode,FIRST_INIT); +#ifdef gXcvrXtalTrimEnabled_d + if( 0xFFFFFFFF != gHardwareParameters.xtalTrim ) + { + XcvrSetXtalTrim( (uint8_t)gHardwareParameters.xtalTrim ); + } +#endif +} + +/*! ********************************************************************************* +* \brief This function changes the radio operating mode between BLE and Zigbee +* +* \param[in] radioMode - the new operating mode for the radio +* +* \ingroup PublicAPIs +* +* \details +* +***********************************************************************************/ +xcvrStatus_t XcvrChangeMode ( radio_mode_t radioMode ) +{ + XcvrInit_ModeChg_Common(radioMode, MODE_CHANGE); + return gXcvrSuccess_c; +} + +/*! ********************************************************************************* +* \brief This function allows a callback function to be registered allowing the +* transceiver software to call a PANIC function in case of software error +* +* \param[in] fptr - a pointer to a function which implements system PANIC +* +* \ingroup PublicAPIs +* +* \details +* +***********************************************************************************/ +void XcvrRegisterPanicCb ( panic_fptr fptr ) +{ + panic_function_ptr = fptr; + panic_fptr_is_valid = 1; +} + +/*! ********************************************************************************* +* \brief This function allows a upper layer software to poll the health of the +* transceiver to detect problems in the radio operation. +* +* \return radio_status - current status of the radio, 0 = no failures. Any other +* value indicates a failure, see ::healthStatus_t for the possible values +* which may all be OR'd together as needed. +* +* \ingroup PublicAPIs +* +* \details +* +***********************************************************************************/ +healthStatus_t XcvrHealthCheck ( void ) +{ + healthStatus_t retval = NO_ERRORS; + /* Read PLL status bits and set return values */ + if (XCVR_BRD_PLL_LOCK_DETECT_CTFF(XCVR) == 1) + { + retval |= PLL_CTUNE_FAIL; + } + if (XCVR_BRD_PLL_LOCK_DETECT_CSFF(XCVR) == 1) + { + retval |= PLL_CYCLE_SLIP_FAIL; + } + if (XCVR_BRD_PLL_LOCK_DETECT_FTFF(XCVR) == 1) + { + retval |= PLL_FREQ_TARG_FAIL; + } + if (XCVR_BRD_PLL_LOCK_DETECT_TAFF(XCVR) == 1) + { + retval |= PLL_TSM_ABORT_FAIL; + } + /* Once errors have been captured, clear the sticky flags. + * Sticky bits are W1C so this clears them. + */ + XCVR_PLL_LOCK_DETECT = (uint32_t)(XCVR_PLL_LOCK_DETECT); + return retval; +} + +/*! ********************************************************************************* +* \brief This function allows a upper layer software to control the state of the +* Fast Antenna Diversity (FAD) and Low Power Preamble Search (LPPS) features for +* the Zigbee radio. +* +* \param control - desired setting for combined FAD/LPPS feature. +* +* \ingroup PublicAPIs +* +* \details +* FAD and LPPS are mutually exclusive features, they cannot be enabled at +* the same time so this API enforces that restriction. +* This API only controls the transceiver functionality related to FAD and +* LPPS, it does not affect any link layer functionality that may be required. +* \note +* This code does NOT set the pin muxing for the GPIO pins required for this +* feature. TSM_GPIO2 and TSM_GPIO3 pins are used for TX and RX respectively. +***********************************************************************************/ +void XcvrFadLppsControl(FAD_LPPS_CTRL_T control) +{ + switch (control) + { + case NONE: + /* Disable FAD */ + XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */ + XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */ + /* Disable LPPS */ + XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(XCVR, 0); + break; + case FAD_ENABLED: + /* Enable FAD */ + XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, END_OF_TX_WU_BLE)); + XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, END_OF_RX_WU_BLE, 0xFF, 0xFF)); + /* Disable LPPS */ + XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(XCVR, 0); + break; + case LPPS_ENABLED: + /* Disable FAD */ + XCVR_TSM_TIMING42 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */ + XCVR_TSM_TIMING43 = (uint32_t)(TSM_REG_VALUE(0xFF, 0xFF, 0xFF, 0xFF)); /* Disabled TSM signal */ + /* Enable LPPS */ + XCVR_LPPS_CTRL = (uint32_t)(XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_MASK | + XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_MASK | + XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_MASK | + XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_MASK | + XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_MASK | + XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_MASK | + XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_MASK + ); + XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(XCVR, 1); + break; + default: + /* PANIC? */ + break; + } +} + +/*! ********************************************************************************* +* \brief This function calls the system panic function for radio errors. +* +* \param[in] panic_id The identifier for the radio error. +* \param[in] location The location (address) in the code where the error happened. +* +* +* \ingroup PrivateAPIs +* +* \details This function is a common flow for both first init of the radio as well as +* mode change of the radio. +* +***********************************************************************************/ +void XcvrPanic (uint32_t panic_id, uint32_t location) +{ + if (panic_fptr_is_valid) + { + (*panic_function_ptr)(panic_id, location, (uint32_t)0, (uint32_t)0); + } + else + { + while(1); /* No panic function registered. */ + } +} + +/*! ********************************************************************************* +* \brief This function initializes or changes the mode of the transceiver. +* +* \param[in] radioMode The target operating mode of the radio. +* \param[in] mode_change Whether this is an initialization or a mode change (FIRST_INIT == Init, MODE_CHANGE==mode change). +* +* +* \ingroup PrivateAPIs +* +* \details This function is a common flow for both first init of the radio as well as +* mode change of the radio. +* +***********************************************************************************/ +void XcvrInit_ModeChg_Common ( radio_mode_t radioMode, MODE_CHG_SEL_T mode_change ) +{ + static radio_mode_t last_mode = INVALID_MODE; + + uint8_t osr; + uint8_t norm_en; + uint8_t chf_bypass; + IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = + { + {ADC_GAIN, 0, FALSE}, /* Fetch the ADC GAIN parameter if available. */ + {ZB_FILT_TRIM, 0, FALSE}, /* Fetch the Zigbee BBW filter trim if available. */ + {BLE_FILT_TRIM, 0, FALSE}, /* Fetch the BLE BBW filter trim if available. */ + {TRIM_STATUS, 0, FALSE}, /* Fetch the trim status word if available. */ + {TRIM_VERSION, 0, FALSE} /* Fetch the trim version number if available. */ + }; + +#define NUM_TRIM_TBL_ENTRIES sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T) + + if( radioMode == last_mode ) + { + return; + } + else + { + last_mode = radioMode; + } + + /* Check that this is the proper chip version */ + if ((RSIM_ANA_TEST >> 24) & 0xF != 0x2) + { + XcvrPanic(WRONG_RADIO_ID_DETECTED,(uint32_t)&XcvrInit_ModeChg_Common); + } + + + /* Enable XCVR_DIG, LTC and DCDC clock always, independent of radio mode. + * Only enable one of BTLL or Zigbee. + */ + switch (radioMode) + { + case BLE: + SIM_SCGC5 |= SIM_SCGC5_BTLL_MASK | SIM_SCGC5_PHYDIG_MASK; + break; + case ZIGBEE: + SIM_SCGC5 |= SIM_SCGC5_ZigBee_MASK | SIM_SCGC5_PHYDIG_MASK; + break; + default: + break; + } + + HWDCoffsetCal = 0; /* Default to using SW DCOC calibration */ + + gen1_dcgain_trims_enabled = 0; + handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES); + + /* Transfer values from sw_trim_tbl[] to static variables used in radio operation */ + { + uint16_t i; + for (i=0;i>IFR_TZA_CAP_TUNE_SHIFT); + zb_bbf_cap_tune = ((sw_trim_tbl[i].trim_value & IFR_BBF_CAP_TUNE_MASK)>>IFR_BBF_CAP_TUNE_SHIFT); + zb_bbf_res_tune2 = ((sw_trim_tbl[i].trim_value & IFR_RES_TUNE2_MASK)>>IFR_RES_TUNE2_SHIFT); + break; + /* BLE_FILT_TRIM */ + case BLE_FILT_TRIM: + ble_tza_cap_tune = ((sw_trim_tbl[i].trim_value & IFR_TZA_CAP_TUNE_MASK)>>IFR_TZA_CAP_TUNE_SHIFT); + ble_bbf_cap_tune = ((sw_trim_tbl[i].trim_value & IFR_BBF_CAP_TUNE_MASK)>>IFR_BBF_CAP_TUNE_SHIFT); + ble_bbf_res_tune2 = ((sw_trim_tbl[i].trim_value & IFR_RES_TUNE2_MASK)>>IFR_RES_TUNE2_SHIFT); + break; + case TRIM_STATUS: + trim_status = sw_trim_tbl[i].trim_value; + break; + case TRIM_VERSION: + ifr_version = sw_trim_tbl[i].trim_value & 0xFFFF; + break; + default: + break; + } + } + } + } + + { + static uint32_t tempstatus = 0; + tempstatus = (trim_status & (BGAP_VOLTAGE_TRIM_FAILED | IQMC_GAIN_ADJ_FAILED | IQMC_GAIN_ADJ_FAILED | IQMC_DC_GAIN_ADJ_FAILED)); + /* Determine whether this IC can support HW DC Offset Calibration. + * Must be v3 or greater trim version and != 0xFFFF + * Must have BGAP, IQMC and IQ DC GAIN calibration SUCCESS + * OR - may be over-ridden by a compile time flag to force HW DCOC cal + */ + if (((ifr_version >= 3) && + (ifr_version != 0xFFFF) && + (ifr_version != 0xFFFE) && /* Special version number indicating fallback IFR table used due to untrimmed part. */ + (tempstatus == 0)) || + (ENGINEERING_TRIM_BYPASS)) + { + HWDCoffsetCal = 1; + } + } + + XCVR_BWR_BGAP_CTRL_BGAP_ATST_ON(XCVR, 0); + + if (mode_change == MODE_CHANGE) + { + /* Change only mode dependent analog & TSM settings */ + XcvrSetAnalogDef_ModeSwitch(radioMode); + XcvrSetTsmDef_ModeSwitch(radioMode); + } + else + { + /* Setup initial analog & TSM settings */ + XcvrSetAnalogDefaults(radioMode); + XcvrSetTsmDefaults(radioMode); + } + + /* RX Channel filter coeffs and TSM settings are specific to modes */ + switch (radioMode) + { + case BLE: + if (mode_change == MODE_CHANGE) + { + XcvrSetRxDigDef_ModeSwitch(&gBLERxChfCoeff[0], DCOC_CAL_IIR3A_IDX_def_c, DCOC_CAL_IIR2A_IDX_def_c, DCOC_CAL_IIR1A_IDX_def_c, RSSI_HOLD_SRC_def_c); + } + else + { + XcvrSetRxDigDefaults(&gBLERxChfCoeff[0], DCOC_CAL_IIR3A_IDX_def_c, DCOC_CAL_IIR2A_IDX_def_c, DCOC_CAL_IIR1A_IDX_def_c, RSSI_HOLD_SRC_def_c); + } + XCVR_BWR_CTRL_PROTOCOL(XCVR, BLE_PROTOCOL_def_c); /* BLE protocol selection */ + XCVR_BWR_CTRL_TGT_PWR_SRC(XCVR, BLE_TGT_PWR_SRC_def_c); + XCVR_BWR_AGC_CTRL_0_FREEZE_AGC_SRC(XCVR, FREEZE_AGC_SRC_def_c); /* Freeze AGC */ + osr = RX_DEC_FILT_OSR_BLE_def_c; /* OSR 4 */ + norm_en = RX_NORM_EN_BLE_def_c; /* Normalizer OFF */ + chf_bypass = RX_CH_FILT_BYPASS_def_c; /* BLE Channel filter setting */ + + /* DCOC_CTRL_0 & RX_DIG_CTRL settings done separately from other RX_DIG*/ + /* DCOC_CTRL_0 */ + XCVR_DCOC_CTRL_0 = (uint32_t)( + (ALPHAC_SCALE_IDX_def_c << XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT) | + (ALPHA_RADIUS_IDX_def_c << XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT) | + (SIGN_SCALE_IDX_def_c << XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT) | + (DCOC_CAL_DURATION_def_c << XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT) | + (DCOC_CORR_DLY_def_c << XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT) | + (DCOC_CORR_HOLD_TIME_def_c << XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT) | + (DCOC_MAN_def_c << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT) | + (DCOC_TRACK_EN_def_c << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT) | + (DCOC_CORRECT_EN_def_c << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT) + ); + break; + case ZIGBEE: + if (mode_change == MODE_CHANGE) + { + XcvrSetRxDigDef_ModeSwitch(&gZigbeeRxChfCoeff[0], IIR3A_IDX_Zigbee_def_c, IIR2A_IDX_Zigbee_def_c, IIR1A_IDX_Zigbee_def_c, RSSI_HOLD_SRC_Zigbee_def_c); + } + else + { + XcvrSetRxDigDefaults(&gZigbeeRxChfCoeff[0], IIR3A_IDX_Zigbee_def_c, IIR2A_IDX_Zigbee_def_c, IIR1A_IDX_Zigbee_def_c, RSSI_HOLD_SRC_Zigbee_def_c); + } + XCVR_BWR_CTRL_PROTOCOL(XCVR, Zigbee_PROTOCOL_def_c); /* Zigbee protocol selection */ + XCVR_BWR_CTRL_TGT_PWR_SRC(XCVR, Zigbee_TGT_PWR_SRC_def_c); + XCVR_BWR_AGC_CTRL_0_FREEZE_AGC_SRC(XCVR, FREEZE_AGC_SRC_Zigbee_def_c); /* Freeze AGC */ + /* Correlation zero count for Zigbee preamble detection */ + XCVR_BWR_CORR_CTRL_CORR_NVAL(XCVR, CORR_NVAL_Zigbee_def_c); + /* Correlation threshold */ + XCVR_BWR_CORR_CTRL_CORR_VT(XCVR, CORR_VT_Zigbee_def_c); + osr = RX_DEC_FILT_OSR_Zigbee_def_c; /* OSR 8 */ + norm_en = RX_NORM_EN_Zigbee_def_c; /* Normalizer On */ + chf_bypass = RX_CH_FILT_BYPASS_Zigbee_def_c; /* Zigbee Channel filter setting */ + + /* DCOC_CTRL_0 & RX_DIG_CTRL settings done separately from other RX_DIG*/ + /* DCOC_CTRL_0 */ + XCVR_DCOC_CTRL_0 = (uint32_t)( + (ALPHAC_SCALE_IDX_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT) | + (ALPHA_RADIUS_IDX_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT) | + (SIGN_SCALE_IDX_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT) | + (DCOC_CAL_DURATION_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT) | + (DCOC_CORR_DLY_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT) | + (DCOC_CORR_HOLD_TIME_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT) | + (DCOC_MAN_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT) | + (DCOC_TRACK_EN_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT) | + (DCOC_CORRECT_EN_Zigbee_def_c << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT) + ); + break; + default: + break; + } + + if (mode_change == MODE_CHANGE) + { + XcvrSetTxDigPLLDef_ModeSwitch(radioMode); + } + else + { + XcvrSetTxDigPLLDefaults(radioMode); + } + + XCVR_DCOC_CTRL_0 = (uint32_t)((XCVR_DCOC_CTRL_0 & (uint32_t)~(uint32_t)( + XCVR_DCOC_CTRL_0_DCOC_MAN_MASK | + XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_MASK | + XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK + )) | (uint32_t)( + (DCOC_MAN_def_c << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT) | + (DCOC_TRACK_EN_def_c << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT) | + (DCOC_CORRECT_EN_def_c << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT) + )); + + /* DCOC_CTRL_0 & RX_DIG_CTRL settings done separately from other RX_DIG*/ + /* RX_DIG_CTRL */ + XCVR_RX_DIG_CTRL = (uint32_t)((XCVR_RX_DIG_CTRL & (uint32_t)~(uint32_t)( + XCVR_RX_DIG_CTRL_RX_RSSI_EN_MASK | + XCVR_RX_DIG_CTRL_RX_AGC_EN_MASK | + XCVR_RX_DIG_CTRL_RX_DCOC_EN_MASK | + XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK | + XCVR_RX_DIG_CTRL_RX_NORM_EN_MASK | + XCVR_RX_DIG_CTRL_RX_INTERP_EN_MASK | + XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK | + XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK + )) | (uint32_t)( + (RX_RSSI_EN_def_c << XCVR_RX_DIG_CTRL_RX_RSSI_EN_SHIFT) | + (RX_AGC_EN_def_c << XCVR_RX_DIG_CTRL_RX_AGC_EN_SHIFT) | + (RX_DCOC_EN_def_c << XCVR_RX_DIG_CTRL_RX_DCOC_EN_SHIFT) | + (osr << XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT) | + (norm_en << XCVR_RX_DIG_CTRL_RX_NORM_EN_SHIFT) | + (RX_INTERP_EN_def_c << XCVR_RX_DIG_CTRL_RX_INTERP_EN_SHIFT) | + (chf_bypass << XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT) | + (0 << XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT) /* DCOC_CAL_EN set to zero here, changed below if appropriate */ + )); + + if (HWDCoffsetCal) + { + XCVR_BWR_RX_DIG_CTRL_RX_DCOC_CAL_EN(XCVR, 1); /* DCOC_CAL 1=Enabled */ + } + else + { + /* DCOC Calibration issue workaround. Performs a manual DCOC calibration and disables RX_DCOC_CAL_EN + * Manipulates AGC settings during the calibration and then reverts them + */ + if (mode_change == FIRST_INIT) + { + switch (radioMode) + { + case BLE: + XcvrManualDCOCCal(20); /* Use channel 20 for BLE calibration @ ~mid-band */ + break; + case ZIGBEE: + XcvrManualDCOCCal(18); /* Use channel 18 for Zigbee calibration @ ~mid-band */ + break; + default: + break; + } + } + } +} + +/*! ********************************************************************************* +* \brief This function sets the default vaues of the TSM registers. +* +* \param[in] radioMode Radio mode is used to enable mode specific settings. +* +* \ingroup PrivateAPIs +* +* \details This function also sets link layer registers to account for TX and +* delays. +* +***********************************************************************************/ +void XcvrSetTsmDefaults ( radio_mode_t radioMode ) +{ + /*TSM_CTRL*/ + XCVR_TSM_CTRL = (uint32_t)((XCVR_TSM_CTRL & (uint32_t)~(uint32_t)( + XCVR_TSM_CTRL_BKPT_MASK | + XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK | + XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK | + XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK | + XCVR_TSM_CTRL_RX_ABORT_DIS_MASK | + XCVR_TSM_CTRL_TX_ABORT_DIS_MASK | + XCVR_TSM_CTRL_DATA_PADDING_EN_MASK | + XCVR_TSM_CTRL_PA_RAMP_SEL_MASK | + XCVR_TSM_CTRL_FORCE_RX_EN_MASK | + XCVR_TSM_CTRL_FORCE_TX_EN_MASK + )) | (uint32_t)( + (BKPT_def_c << XCVR_TSM_CTRL_BKPT_SHIFT) | + (ABORT_ON_FREQ_TARG_def_c << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT) | + (ABORT_ON_CYCLE_SLIP_def_c << XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT) | + (ABORT_ON_CTUNE_def_c << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT) | + (RX_ABORT_DIS_def_c << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT) | + (TX_ABORT_DIS_def_c << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT) | + (DATA_PADDING_EN_def_c << XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT) | + (PA_RAMP_SEL_def_c << XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT) | + (FORCE_RX_EN_def_c << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT) | + (FORCE_TX_EN_def_c << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT) + )); + + /* Perform mode specific portion of TSM setup using mode switch routine */ + XcvrSetTsmDef_ModeSwitch(radioMode); + + /* Only init OVRD registers if a non-default setting is needed */ + /*PA_POWER*/ + XCVR_BWR_PA_POWER_PA_POWER(XCVR, PA_POWER_def_c); + + /*PA_BIAS_TBL0*/ + XCVR_PA_BIAS_TBL0 = (uint32_t)((XCVR_PA_BIAS_TBL0 & (uint32_t)~(uint32_t)( + XCVR_PA_BIAS_TBL0_PA_BIAS3_MASK | + XCVR_PA_BIAS_TBL0_PA_BIAS2_MASK | + XCVR_PA_BIAS_TBL0_PA_BIAS1_MASK | + XCVR_PA_BIAS_TBL0_PA_BIAS0_MASK + )) | (uint32_t)( + (gPABiasTbl[3] << XCVR_PA_BIAS_TBL0_PA_BIAS3_SHIFT) | + (gPABiasTbl[2] << XCVR_PA_BIAS_TBL0_PA_BIAS2_SHIFT) | + (gPABiasTbl[1] << XCVR_PA_BIAS_TBL0_PA_BIAS1_SHIFT) | + (gPABiasTbl[0] << XCVR_PA_BIAS_TBL0_PA_BIAS0_SHIFT) + )); + + /*PA_BIAS_TBL1*/ + XCVR_PA_BIAS_TBL1 = (uint32_t)((XCVR_PA_BIAS_TBL1 & (uint32_t)~(uint32_t)( + XCVR_PA_BIAS_TBL1_PA_BIAS7_MASK | + XCVR_PA_BIAS_TBL1_PA_BIAS6_MASK | + XCVR_PA_BIAS_TBL1_PA_BIAS5_MASK | + XCVR_PA_BIAS_TBL1_PA_BIAS4_MASK + )) | (uint32_t)( + (gPABiasTbl[7] << XCVR_PA_BIAS_TBL1_PA_BIAS7_SHIFT) | + (gPABiasTbl[6] << XCVR_PA_BIAS_TBL1_PA_BIAS6_SHIFT) | + (gPABiasTbl[5] << XCVR_PA_BIAS_TBL1_PA_BIAS5_SHIFT) | + (gPABiasTbl[4] << XCVR_PA_BIAS_TBL1_PA_BIAS4_SHIFT) + )); +} + +/*! ********************************************************************************* +* \brief This function sets the radio mode specific default vaues of the TSM registers. +* +* \param[in] radioMode Radio mode is used to enable mode specific settings. +* +* \ingroup PrivateAPIs +* +* \details This function also sets link layer registers to account for TX and +* delays. +* +***********************************************************************************/ +void XcvrSetTsmDef_ModeSwitch ( radio_mode_t radioMode ) +{ + /* Setup TSM timing registers and LL timing registers at the same time */ + switch (radioMode) + { + case BLE: + tsm_ll_timing_init(BLE_RADIO); + break; + case ZIGBEE: + tsm_ll_timing_init(ZIGBEE_RADIO); + break; + default: + break; + } +} + +/*! ********************************************************************************* +* \brief This function sets the default vaues of the RX DIG registers. +* +* \param[in] filt_coeff_ptr pointer to an array of 8 UINT8_T receive filter coefficients. +* \param[in] iir3a_idx value of the 3rd IIR index +* \param[in] iir2a_idx value of the 2nd IIR index +* \param[in] iir1a_idx value of the 1st IIR index +* +* \ingroup PrivateAPIs +* +* \details Sets up RX digital registers with command and mode specific settings. +* +* \note Only uses read-modify-write when only part of the register is being written. +* +***********************************************************************************/ +void XcvrSetRxDigDefaults ( const uint8_t * filt_coeff_ptr, uint8_t iir3a_idx, uint8_t iir2a_idx, uint8_t iir1a_idx, uint8_t rssi_hold_src ) +{ + /* Program RSSI registers */ + /* RSSI_CTRL_0 */ + XCVR_RSSI_CTRL_0 = (uint32_t)((XCVR_RSSI_CTRL_0 & (uint32_t)~(uint32_t)( + XCVR_RSSI_CTRL_0_RSSI_USE_VALS_MASK | + XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_MASK | + XCVR_RSSI_CTRL_0_RSSI_DEC_EN_MASK | + XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK | + XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK | + XCVR_RSSI_CTRL_0_RSSI_ADJ_MASK + )) | (uint32_t)( + (RSSI_USE_VALS_def_c << XCVR_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT) | + (RSSI_HOLD_EN_def_c << XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT) | + (RSSI_DEC_EN_def_c << XCVR_RSSI_CTRL_0_RSSI_DEC_EN_SHIFT) | + (RSSI_IIR_WEIGHT_def_c << XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT) | + (RSSI_IIR_CW_WEIGHT_BYPASSEDdef_c << XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT) | + (RSSI_ADJ_def_c << XCVR_RSSI_CTRL_0_RSSI_ADJ_SHIFT) + )); + + /* RSSI_CTRL_1 */ + XCVR_RSSI_CTRL_1 = (uint32_t)((XCVR_RSSI_CTRL_1 & (uint32_t)~(uint32_t)( + XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_MASK | + XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_MASK | + XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_MASK | + XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_MASK + )) | (uint32_t)( + (RSSI_ED_THRESH1_H_def_c << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_SHIFT) | + (RSSI_ED_THRESH0_H_def_c << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_SHIFT) | + (RSSI_ED_THRESH1_def_c << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_SHIFT) | + (RSSI_ED_THRESH0_def_c << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_SHIFT) + )); + + /* Program AGC registers */ + /* AGC_CTRL_0 */ + XCVR_AGC_CTRL_0 = (uint32_t)((XCVR_AGC_CTRL_0 & (uint32_t)~(uint32_t)( + XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK | + XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK | + XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_MASK | + XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_MASK | + XCVR_AGC_CTRL_0_AGC_UP_SRC_MASK | + XCVR_AGC_CTRL_0_AGC_UP_EN_MASK | + XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_MASK | + XCVR_AGC_CTRL_0_AGC_FREEZE_EN_MASK | + XCVR_AGC_CTRL_0_SLOW_AGC_SRC_MASK | + XCVR_AGC_CTRL_0_SLOW_AGC_EN_MASK + )) | (uint32_t)( + (AGC_DOWN_RSSI_THRESH_def_c << XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT) | + (AGC_UP_RSSI_THRESH_def_c << XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT) | + (AGC_DOWN_BBF_STEP_SZ_def_c << XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_SHIFT) | + (AGC_DOWN_TZA_STEP_SZ_def_c << XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_SHIFT) | + (AGC_UP_SRC_def_c << XCVR_AGC_CTRL_0_AGC_UP_SRC_SHIFT) | + (AGC_UP_EN_def_c << XCVR_AGC_CTRL_0_AGC_UP_EN_SHIFT) | + (FREEZE_AGC_SRC_def_c << XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_SHIFT) | + (AGC_FREEZE_EN_def_c << XCVR_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT) | + (SLOW_AGC_SRC_def_c << XCVR_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT) | + (SLOW_AGC_EN_def_c << XCVR_AGC_CTRL_0_SLOW_AGC_EN_SHIFT) + )); + + /* AGC_CTRL_1 */ + XCVR_AGC_CTRL_1 = (uint32_t)((XCVR_AGC_CTRL_1 & (uint32_t)~(uint32_t)( + XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_MASK | + XCVR_AGC_CTRL_1_PRESLOW_EN_MASK | + XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_MASK | + XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_MASK | + XCVR_AGC_CTRL_1_BBF_USER_GAIN_MASK | + XCVR_AGC_CTRL_1_LNM_USER_GAIN_MASK | + XCVR_AGC_CTRL_1_LNM_ALT_CODE_MASK | + XCVR_AGC_CTRL_1_BBF_ALT_CODE_MASK + )) | (uint32_t)( + (TZA_GAIN_SETTLE_TIME_def_c << XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_SHIFT) | + (PRESLOW_EN_def_c << XCVR_AGC_CTRL_1_PRESLOW_EN_SHIFT) | + (USER_BBF_GAIN_EN_def_c << XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_SHIFT) | + (USER_LNM_GAIN_EN_def_c << XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_SHIFT) | + (BBF_USER_GAIN_def_c << XCVR_AGC_CTRL_1_BBF_USER_GAIN_SHIFT) | + (LNM_USER_GAIN_def_c << XCVR_AGC_CTRL_1_LNM_USER_GAIN_SHIFT) | + (LNM_ALT_CODE_def_c << XCVR_AGC_CTRL_1_LNM_ALT_CODE_SHIFT) | + (BBF_ALT_CODE_def_c << XCVR_AGC_CTRL_1_BBF_ALT_CODE_SHIFT) + )); + + /* AGC_CTRL_2 */ + XCVR_AGC_CTRL_2 = (uint32_t)((XCVR_AGC_CTRL_2 & (uint32_t)~(uint32_t)( + XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK | + XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_MASK | + XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_MASK | + XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_MASK | + XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_MASK | + XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_MASK + )) | (uint32_t)( + (AGC_FAST_EXPIRE_def_c << XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT) | + (TZA_PDET_THRESH_HI_def_c << XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_SHIFT) | + (TZA_PDET_THRESH_LO_def_c << XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_SHIFT) | + (BBF_PDET_THRESH_HI_def_c << XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_SHIFT) | + (BBF_PDET_THRESH_LO_def_c << XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_SHIFT) | + (BBF_GAIN_SETTLE_TIME_def_c << XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_SHIFT) + )); + + /* AGC_CTRL_3 */ + XCVR_AGC_CTRL_3 = (uint32_t)((XCVR_AGC_CTRL_3 & (uint32_t)~(uint32_t)( + XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK | + XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK | + XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK | + XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK | + XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK + )) | (uint32_t)( + (AGC_UP_STEP_SZ_def_c << XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT) | + (AGC_H2S_STEP_SZ_def_c << XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT) | + (AGC_RSSI_DELT_H2S_def_c << XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT) | + (AGC_PDET_LO_DLY_def_c << XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT) | + (AGC_UNFREEZE_TIME_def_c << XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT) + )); + + /* AGC_GAIN_TBL*** registers */ + XCVR_AGC_GAIN_TBL_03_00 = (uint32_t)( + (BBF_GAIN_00_def_c << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_SHIFT) | + (LNM_GAIN_00_def_c << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_SHIFT) | + (BBF_GAIN_01_def_c << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_SHIFT) | + (LNM_GAIN_01_def_c << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_SHIFT) | + (BBF_GAIN_02_def_c << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_SHIFT) | + (LNM_GAIN_02_def_c << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_SHIFT) | + (BBF_GAIN_03_def_c << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_SHIFT) | + (LNM_GAIN_03_def_c << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_SHIFT) + ); + + XCVR_AGC_GAIN_TBL_07_04 = (uint32_t)( + (BBF_GAIN_04_def_c << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_SHIFT) | + (LNM_GAIN_04_def_c << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_SHIFT) | + (BBF_GAIN_05_def_c << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_SHIFT) | + (LNM_GAIN_05_def_c << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_SHIFT) | + (BBF_GAIN_06_def_c << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_SHIFT) | + (LNM_GAIN_06_def_c << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_SHIFT) | + (BBF_GAIN_07_def_c << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_SHIFT) | + (LNM_GAIN_07_def_c << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_SHIFT) + ); + + XCVR_AGC_GAIN_TBL_11_08 = (uint32_t)( + (BBF_GAIN_08_def_c << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_SHIFT) | + (LNM_GAIN_08_def_c << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_SHIFT) | + (BBF_GAIN_09_def_c << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_SHIFT) | + (LNM_GAIN_09_def_c << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_SHIFT) | + (BBF_GAIN_10_def_c << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_SHIFT) | + (LNM_GAIN_10_def_c << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_SHIFT) | + (BBF_GAIN_11_def_c << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_SHIFT) | + (LNM_GAIN_11_def_c << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_SHIFT) + ); + + XCVR_AGC_GAIN_TBL_15_12 = (uint32_t)( + (BBF_GAIN_12_def_c << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_SHIFT) | + (LNM_GAIN_12_def_c << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_SHIFT) | + (BBF_GAIN_13_def_c << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_SHIFT) | + (LNM_GAIN_13_def_c << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_SHIFT) | + (BBF_GAIN_14_def_c << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_SHIFT) | + (LNM_GAIN_14_def_c << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_SHIFT) | + (BBF_GAIN_15_def_c << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_SHIFT) | + (LNM_GAIN_15_def_c << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_SHIFT) + ); + + XCVR_AGC_GAIN_TBL_19_16 = (uint32_t)( + (BBF_GAIN_16_def_c << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_SHIFT) | + (LNM_GAIN_16_def_c << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_SHIFT) | + (BBF_GAIN_17_def_c << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_SHIFT) | + (LNM_GAIN_17_def_c << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_SHIFT) | + (BBF_GAIN_18_def_c << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_SHIFT) | + (LNM_GAIN_18_def_c << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_SHIFT) | + (BBF_GAIN_19_def_c << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_SHIFT) | + (LNM_GAIN_19_def_c << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_SHIFT) + ); + + XCVR_AGC_GAIN_TBL_23_20 = (uint32_t)( + (BBF_GAIN_20_def_c << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_SHIFT) | + (LNM_GAIN_20_def_c << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_SHIFT) | + (BBF_GAIN_21_def_c << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_SHIFT) | + (LNM_GAIN_21_def_c << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_SHIFT) | + (BBF_GAIN_22_def_c << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_SHIFT) | + (LNM_GAIN_22_def_c << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_SHIFT) | + (BBF_GAIN_23_def_c << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_SHIFT) | + (LNM_GAIN_23_def_c << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_SHIFT) + ); + + XCVR_AGC_GAIN_TBL_26_24 = (uint32_t)( + (BBF_GAIN_24_def_c << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_SHIFT) | + (LNM_GAIN_24_def_c << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_SHIFT) | + (BBF_GAIN_25_def_c << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_SHIFT) | + (LNM_GAIN_25_def_c << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_SHIFT) | + (BBF_GAIN_26_def_c << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_SHIFT) | + (LNM_GAIN_26_def_c << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_SHIFT) + ); + + XCVR_TCA_AGC_VAL_3_0 = (uint32_t)( + (TCA_AGC_VAL_3_def_c<< XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_SHIFT) | + (TCA_AGC_VAL_2_def_c<< XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_SHIFT) | + (TCA_AGC_VAL_1_def_c<< XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_SHIFT) | + (TCA_AGC_VAL_0_def_c<< XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_SHIFT) + ); + + XCVR_TCA_AGC_VAL_7_4 = (uint32_t)( + (TCA_AGC_VAL_7_def_c<< XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_SHIFT) | + (TCA_AGC_VAL_6_def_c<< XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_SHIFT) | + (TCA_AGC_VAL_5_def_c<< XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_SHIFT) | + (TCA_AGC_VAL_4_def_c<< XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_SHIFT) + ); + + XCVR_TCA_AGC_VAL_8 = (uint32_t)( + (TCA_AGC_VAL_8_def_c<< XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_SHIFT) + ); + + XCVR_BBF_RES_TUNE_VAL_7_0 = (uint32_t)( + (BBF_RES_TUNE_VAL_7_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_SHIFT) | + (BBF_RES_TUNE_VAL_6_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_SHIFT) | + (BBF_RES_TUNE_VAL_5_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_SHIFT) | + (BBF_RES_TUNE_VAL_4_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_SHIFT) | + (BBF_RES_TUNE_VAL_3_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_SHIFT) | + (BBF_RES_TUNE_VAL_2_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_SHIFT) | + (BBF_RES_TUNE_VAL_1_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_SHIFT) | + (BBF_RES_TUNE_VAL_0_def_c<< XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_SHIFT) + ); + + XCVR_BBF_RES_TUNE_VAL_10_8 = (uint32_t)( + (BBF_RES_TUNE_VAL_10_def_c<< XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_SHIFT) | + (BBF_RES_TUNE_VAL_9_def_c<< XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_SHIFT) | + (BBF_RES_TUNE_VAL_8_def_c<< XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_SHIFT) + ); + + /* Program DCOC registers */ + XcvrCalcSetupDcoc(); + + /* Use mode switch routine to setup the defaults that depend on radio mode */ + XcvrSetRxDigDef_ModeSwitch(filt_coeff_ptr, iir3a_idx, iir2a_idx, iir1a_idx, rssi_hold_src); +} + +/*! ********************************************************************************* +* \brief This function sets the radio mode dependent default values of the RX DIG registers. +* +* \param[in] in_filt_coeff_ptr pointer to an array of 8 UINT8_T receive filter coefficients. +* \param[in] iir3a_idx value of the 3rd IIR index +* \param[in] iir2a_idx value of the 2nd IIR index +* \param[in] iir1a_idx value of the 1st IIR index +* +* \ingroup PrivateAPIs +* +* \details Sets up RX digital registers with command and mode specific settings. +* +* \note Only uses read-modify-write when only part of the register is being written. +* +**********************************************************************************/ +void XcvrSetRxDigDef_ModeSwitch ( const uint8_t * in_filt_coeff_ptr, uint8_t iir3a_idx, uint8_t iir2a_idx, uint8_t iir1a_idx, uint8_t rssi_hold_src ) +{ + uint8_t * filt_coeff_ptr = (uint8_t *)in_filt_coeff_ptr; + + /*RX_CHF_COEFn*/ + XCVR_RX_CHF_COEF0 = *filt_coeff_ptr++; + XCVR_RX_CHF_COEF1 = *filt_coeff_ptr++; + XCVR_RX_CHF_COEF2 = *filt_coeff_ptr++; + XCVR_RX_CHF_COEF3 = *filt_coeff_ptr++; + XCVR_RX_CHF_COEF4 = *filt_coeff_ptr++; + XCVR_RX_CHF_COEF5 = *filt_coeff_ptr++; + XCVR_RX_CHF_COEF6 = *filt_coeff_ptr++; + XCVR_RX_CHF_COEF7 = *filt_coeff_ptr; + + /* DCOC_CAL_IIR */ + XCVR_DCOC_CAL_IIR = (uint32_t)((XCVR_DCOC_CAL_IIR & (uint32_t)~(uint32_t)( + XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK | + XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK | + XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK + )) | (uint32_t)( + (iir1a_idx << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT) | + (iir2a_idx << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT) | + (iir3a_idx << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT) + )); + + XCVR_BWR_RSSI_CTRL_0_RSSI_HOLD_SRC(XCVR, rssi_hold_src); +} + +/*! ********************************************************************************* +* \brief This function programs a set of DCOC registers either from raw values +* or from calculated (equations) values. +* +* \return Status of the operation. +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +xcvrStatus_t XcvrCalcSetupDcoc ( void ) +{ +#if !USE_DCOC_MAGIC_NUMBERS + + /* Define variables to replace all of the #defined constants which are used + * below and which are defined in BLEDefaults.h for the case where + * USE_DCOC_MAGIC_NUMBERS == 1 + */ + + /* DCOC_CAL_RCP */ +#define ALPHA_CALC_RECIP_def_c 0x00 +#define TMP_CALC_RECIP_def_c 0x00 + + /* TCA_AGC_LIN_VAL_2_0 */ + uint16_t TCA_AGC_LIN_VAL_0_def_c; + uint16_t TCA_AGC_LIN_VAL_1_def_c; + uint16_t TCA_AGC_LIN_VAL_2_def_c; + + /* TCA_AGC_LIN_VAL_5_3 */ + uint16_t TCA_AGC_LIN_VAL_3_def_c; + uint16_t TCA_AGC_LIN_VAL_4_def_c; + uint16_t TCA_AGC_LIN_VAL_5_def_c; + + /* TCA_AGC_LIN_VAL_8_6 */ + uint16_t TCA_AGC_LIN_VAL_6_def_c; + uint16_t TCA_AGC_LIN_VAL_7_def_c; + uint16_t TCA_AGC_LIN_VAL_8_def_c; + + /* BBF_RES_TUNE_LIN_VAL_3_0 */ + uint8_t BBF_RES_TUNE_LIN_VAL_0_def_c; + uint8_t BBF_RES_TUNE_LIN_VAL_1_def_c; + uint8_t BBF_RES_TUNE_LIN_VAL_2_def_c; + uint8_t BBF_RES_TUNE_LIN_VAL_3_def_c; + + /* BBF_RES_TUNE_LIN_VAL_7_4 */ + uint8_t BBF_RES_TUNE_LIN_VAL_4_def_c; + uint8_t BBF_RES_TUNE_LIN_VAL_5_def_c; + uint8_t BBF_RES_TUNE_LIN_VAL_6_def_c; + uint8_t BBF_RES_TUNE_LIN_VAL_7_def_c; + + /* BBF_RES_TUNE_LIN_VAL_10_8 */ + uint8_t BBF_RES_TUNE_LIN_VAL_8_def_c; + uint8_t BBF_RES_TUNE_LIN_VAL_9_def_c; + uint8_t BBF_RES_TUNE_LIN_VAL_10_def_c; + + /* DCOC_TZA_STEP */ + uint16_t DCOC_TZA_STEP_GAIN_00_def_c; + uint16_t DCOC_TZA_STEP_RCP_00_def_c; + uint16_t DCOC_TZA_STEP_GAIN_01_def_c; + uint16_t DCOC_TZA_STEP_RCP_01_def_c; + uint16_t DCOC_TZA_STEP_GAIN_02_def_c; + uint16_t DCOC_TZA_STEP_RCP_02_def_c; + uint16_t DCOC_TZA_STEP_GAIN_03_def_c; + uint16_t DCOC_TZA_STEP_RCP_03_def_c; + uint16_t DCOC_TZA_STEP_GAIN_04_def_c; + uint16_t DCOC_TZA_STEP_RCP_04_def_c; + uint16_t DCOC_TZA_STEP_GAIN_05_def_c; + uint16_t DCOC_TZA_STEP_RCP_05_def_c; + uint16_t DCOC_TZA_STEP_GAIN_06_def_c; + uint16_t DCOC_TZA_STEP_RCP_06_def_c; + uint16_t DCOC_TZA_STEP_GAIN_07_def_c; + uint16_t DCOC_TZA_STEP_RCP_07_def_c; + uint16_t DCOC_TZA_STEP_GAIN_08_def_c; + uint16_t DCOC_TZA_STEP_RCP_08_def_c; + uint16_t DCOC_TZA_STEP_GAIN_09_def_c; + uint16_t DCOC_TZA_STEP_RCP_09_def_c; + uint16_t DCOC_TZA_STEP_GAIN_10_def_c; + uint16_t DCOC_TZA_STEP_RCP_10_def_c; + + /* DCOC_CTRL_1 DCOC_CTRL_2 */ + uint16_t BBF_STEP_def_c; + uint16_t BBF_STEP_RECIP_def_c; + + /* DCOC_CAL_RCP */ + uint16_t RCP_GLHmGLLxGBL_def_c; + uint16_t RCP_GBHmGBL_def_c; + + /* Equations to calculate these values */ + TCA_AGC_LIN_VAL_0_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_0_def_c)); + TCA_AGC_LIN_VAL_1_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_1_def_c)); + TCA_AGC_LIN_VAL_2_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_2_def_c)); + + TCA_AGC_LIN_VAL_3_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_3_def_c)); + TCA_AGC_LIN_VAL_4_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_4_def_c)); + TCA_AGC_LIN_VAL_5_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_5_def_c)); + + TCA_AGC_LIN_VAL_6_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_6_def_c)); + TCA_AGC_LIN_VAL_7_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_7_def_c)); + TCA_AGC_LIN_VAL_8_def_c = (uint16_t)round(0x4*DB_TO_LINEAR(TCA_GAIN_DB_8_def_c)); + + BBF_RES_TUNE_LIN_VAL_0_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_0_def_c)); + BBF_RES_TUNE_LIN_VAL_1_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_1_def_c)); + BBF_RES_TUNE_LIN_VAL_2_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_2_def_c)); + BBF_RES_TUNE_LIN_VAL_3_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_3_def_c)); + + BBF_RES_TUNE_LIN_VAL_4_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_4_def_c)); + BBF_RES_TUNE_LIN_VAL_5_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_5_def_c)); + BBF_RES_TUNE_LIN_VAL_6_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_6_def_c)); + BBF_RES_TUNE_LIN_VAL_7_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_7_def_c)); + + BBF_RES_TUNE_LIN_VAL_8_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_8_def_c)); + BBF_RES_TUNE_LIN_VAL_9_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_9_def_c)); + + if ((0x8*DB_TO_LINEAR(BBF_GAIN_DB_10_def_c)) > 255) + { + BBF_RES_TUNE_LIN_VAL_10_def_c = (uint8_t)(0xFF); + } + else + { + BBF_RES_TUNE_LIN_VAL_10_def_c = (uint8_t)round(0x8*DB_TO_LINEAR(BBF_GAIN_DB_10_def_c)); + } + + if (gen1_dcgain_trims_enabled) + { + double temp_prd = TZA_DCOC_STEP_RAW * adc_gain_trimmed; + DCOC_TZA_STEP_GAIN_00_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_0_def_c) * 0x8); + DCOC_TZA_STEP_RCP_00_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_0_def_c))); + DCOC_TZA_STEP_GAIN_01_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_1_def_c) * 0x8); + DCOC_TZA_STEP_RCP_01_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_1_def_c))); + DCOC_TZA_STEP_GAIN_02_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_2_def_c) * 0x8); + DCOC_TZA_STEP_RCP_02_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_2_def_c))); + DCOC_TZA_STEP_GAIN_03_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_3_def_c) * 0x8); + DCOC_TZA_STEP_RCP_03_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_3_def_c))); + DCOC_TZA_STEP_GAIN_04_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_4_def_c) * 0x8); + DCOC_TZA_STEP_RCP_04_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_4_def_c))); + DCOC_TZA_STEP_GAIN_05_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_5_def_c) * 0x8); + DCOC_TZA_STEP_RCP_05_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_5_def_c))); + DCOC_TZA_STEP_GAIN_06_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_6_def_c) * 0x8); + DCOC_TZA_STEP_RCP_06_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_6_def_c))); + DCOC_TZA_STEP_GAIN_07_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_7_def_c) * 0x8); + DCOC_TZA_STEP_RCP_07_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_7_def_c))); + DCOC_TZA_STEP_GAIN_08_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_8_def_c) * 0x8); + DCOC_TZA_STEP_RCP_08_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_8_def_c))); + DCOC_TZA_STEP_GAIN_09_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_9_def_c) * 0x8); + DCOC_TZA_STEP_RCP_09_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_9_def_c))); + DCOC_TZA_STEP_GAIN_10_def_c = (uint16_t)round(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_10_def_c) * 0x8); + DCOC_TZA_STEP_RCP_10_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(temp_prd * DB_TO_LINEAR(BBF_GAIN_DB_10_def_c))); + + BBF_STEP_def_c = (uint16_t)round(BBF_DCOC_STEP_RAW * adc_gain_trimmed *0x8); + BBF_STEP_RECIP_def_c = (uint16_t)round((((double)(1.0))*(0x8000))/(BBF_DCOC_STEP_RAW * adc_gain_trimmed)); + } + + RCP_GLHmGLLxGBL_def_c = (uint16_t)(round(((double)(2048*1.0))/((DB_TO_LINEAR(TCA_GAIN_DB_8_def_c)-DB_TO_LINEAR(TCA_GAIN_DB_4_def_c))*DB_TO_LINEAR(BBF_GAIN_DB_4_def_c)))); + RCP_GBHmGBL_def_c = (uint16_t)(round(((double)(1024*1.0))/((DB_TO_LINEAR(BBF_GAIN_DB_8_def_c)-DB_TO_LINEAR(BBF_GAIN_DB_4_def_c))))); + +#endif /* !USE_DCOC_MAGIC_NUMBERS */ + + /* Write the registers with either the raw or calculated values. + * NOTE: Values will be either #define constants or local variables. + */ + + /* Miscellaneous DCOC Tracking & GearShift Control Settings (Misc Registers) */ + XCVR_ADC_TEST_CTRL = (uint32_t)((XCVR_ADC_TEST_CTRL & (uint32_t)~(uint32_t)( + XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_MASK + )) | (uint32_t)( + (DCOC_ALPHA_RADIUS_GS_IDX_def_c << XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT) + )); + + XCVR_RX_ANA_CTRL = (uint32_t)((XCVR_RX_ANA_CTRL & (uint32_t)~(uint32_t)( + XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_MASK + )) | (uint32_t)( + (IQMC_DC_GAIN_ADJ_EN_def_c << XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_SHIFT) + )); + + XCVR_ANA_SPARE = (uint32_t)((XCVR_ANA_SPARE & (uint32_t)~(uint32_t)( + XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_MASK | + XCVR_ANA_SPARE_HPM_LSB_INVERT_MASK + )) | (uint32_t)( + (DCOC_TRK_EST_GS_CNT_def_c << XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_SHIFT) | + (HPM_LSB_INVERT_def_c << XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT) + )); + + /* DCOC_CAL_GAIN */ + XCVR_DCOC_CAL_GAIN = (uint32_t)((XCVR_DCOC_CAL_GAIN & (uint32_t)~(uint32_t)( + XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_MASK | + XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_MASK | + XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_MASK | + XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_MASK | + XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_MASK | + XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_MASK + )) | (uint32_t)( + (DCOC_BBF_CAL_GAIN1_def_c << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_SHIFT) | + (DCOC_TZA_CAL_GAIN1_def_c << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_SHIFT) | + (DCOC_BBF_CAL_GAIN2_def_c << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_SHIFT) | + (DCOC_TZA_CAL_GAIN2_def_c << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_SHIFT) | + (DCOC_BBF_CAL_GAIN3_def_c << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_SHIFT) | + (DCOC_TZA_CAL_GAIN3_def_c << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_SHIFT) + )); + + /* DCOC_CALC_RCP */ + XCVR_DCOC_CAL_RCP = (uint32_t)((XCVR_DCOC_CAL_RCP & (uint32_t)~(uint32_t)( + XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK | + XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK + )) | (uint32_t)( + (TMP_CALC_RECIP_def_c << XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT) | + (ALPHA_CALC_RECIP_def_c << XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT) + )); + + /* TCA_AGC_LIN_VAL_2_0 */ + XCVR_TCA_AGC_LIN_VAL_2_0 = (uint32_t)((XCVR_TCA_AGC_LIN_VAL_2_0 & (uint32_t)~(uint32_t)( + XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_MASK | + XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_MASK | + XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_MASK + )) | (uint32_t)( + (TCA_AGC_LIN_VAL_0_def_c << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_SHIFT) | + (TCA_AGC_LIN_VAL_1_def_c << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_SHIFT) | + (TCA_AGC_LIN_VAL_2_def_c << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_SHIFT) + )); + + /* TCA_AGC_LIN_VAL_5_3 */ + XCVR_TCA_AGC_LIN_VAL_5_3 = (uint32_t)((XCVR_TCA_AGC_LIN_VAL_5_3 & (uint32_t)~(uint32_t)( + XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_MASK | + XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_MASK | + XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_MASK + )) | (uint32_t)( + (TCA_AGC_LIN_VAL_3_def_c << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_SHIFT) | + (TCA_AGC_LIN_VAL_4_def_c << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_SHIFT) | + (TCA_AGC_LIN_VAL_5_def_c << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_SHIFT) + )); + + /* TCA_AGC_LIN_VAL_8_6 */ + XCVR_TCA_AGC_LIN_VAL_8_6 = (uint32_t)((XCVR_TCA_AGC_LIN_VAL_8_6 & (uint32_t)~(uint32_t)( + XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_MASK | + XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_MASK | + XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_MASK + )) | (uint32_t)( + (TCA_AGC_LIN_VAL_6_def_c << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_SHIFT) | + (TCA_AGC_LIN_VAL_7_def_c << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_SHIFT) | + (TCA_AGC_LIN_VAL_8_def_c << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_SHIFT) + )); + + /* BBF_RES_TUNE_LIN_VAL_3_0 */ + XCVR_BBF_RES_TUNE_LIN_VAL_3_0 = (uint32_t)((XCVR_BBF_RES_TUNE_LIN_VAL_3_0 & (uint32_t)~(uint32_t)( + XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_MASK | + XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_MASK | + XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_MASK | + XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_MASK + )) | (uint32_t)( + (BBF_RES_TUNE_LIN_VAL_0_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_SHIFT) | + (BBF_RES_TUNE_LIN_VAL_1_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_SHIFT) | + (BBF_RES_TUNE_LIN_VAL_2_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_SHIFT) | + (BBF_RES_TUNE_LIN_VAL_3_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_SHIFT) + )); + + /* BBF_RES_TUNE_LIN_VAL_7_4 */ + XCVR_BBF_RES_TUNE_LIN_VAL_7_4 = (uint32_t)((XCVR_BBF_RES_TUNE_LIN_VAL_7_4 & (uint32_t)~(uint32_t)( + XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_MASK | + XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_MASK | + XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_MASK | + XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_MASK + )) | (uint32_t)( + (BBF_RES_TUNE_LIN_VAL_4_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_SHIFT) | + (BBF_RES_TUNE_LIN_VAL_5_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_SHIFT) | + (BBF_RES_TUNE_LIN_VAL_6_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_SHIFT) | + (BBF_RES_TUNE_LIN_VAL_7_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_SHIFT) + )); + + /* BBF_RES_TUNE_LIN_VAL_10_8 */ + XCVR_BBF_RES_TUNE_LIN_VAL_10_8 = (uint32_t)((XCVR_BBF_RES_TUNE_LIN_VAL_10_8 & (uint32_t)~(uint32_t)( + XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_MASK | + XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_MASK | + XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_MASK + )) | (uint32_t)( + (BBF_RES_TUNE_LIN_VAL_8_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_SHIFT) | + (BBF_RES_TUNE_LIN_VAL_9_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_SHIFT) | + (BBF_RES_TUNE_LIN_VAL_10_def_c << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_SHIFT) + )); + + if (gen1_dcgain_trims_enabled) /* Only run this code when Gen 1 DC GAIN trims are being used. */ + { + /* DCOC_TZA_STEP_GAIN & RCP 00-10 */ + XCVR_DCOC_TZA_STEP_00 = (uint32_t)((XCVR_DCOC_TZA_STEP_00 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_00_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_00_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_01 = (uint32_t)((XCVR_DCOC_TZA_STEP_01 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_01_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_01_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_02 = (uint32_t)((XCVR_DCOC_TZA_STEP_02 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_02_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_02_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_03 = (uint32_t)((XCVR_DCOC_TZA_STEP_03 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_03_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_03_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_04 = (uint32_t)((XCVR_DCOC_TZA_STEP_04 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_04_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_04_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_05 = (uint32_t)((XCVR_DCOC_TZA_STEP_05 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_05_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_05_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_06 = (uint32_t)((XCVR_DCOC_TZA_STEP_06 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_06_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_06_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_07 = (uint32_t)((XCVR_DCOC_TZA_STEP_07 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_07_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_07_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_08 = (uint32_t)((XCVR_DCOC_TZA_STEP_08 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_08_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_08_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_09 = (uint32_t)((XCVR_DCOC_TZA_STEP_09 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_09_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_09_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + + XCVR_DCOC_TZA_STEP_10 = (uint32_t)((XCVR_DCOC_TZA_STEP_10 & (uint32_t)~(uint32_t)( + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK | + XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK + )) | (uint32_t)( + (DCOC_TZA_STEP_RCP_10_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT) | + (DCOC_TZA_STEP_GAIN_10_def_c << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT) + )); + } + + /* DCOC_CTRL_1 */ + XCVR_DCOC_CTRL_1 = (uint32_t)((XCVR_DCOC_CTRL_1 & (uint32_t)~(uint32_t)( + XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_MASK | + XCVR_DCOC_CTRL_1_BBA_CORR_POL_MASK | + XCVR_DCOC_CTRL_1_TZA_CORR_POL_MASK + )) | (uint32_t)( + (TRACK_FROM_ZERO_def_c << XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_SHIFT) | + (BBF_CORR_POL_def_c << XCVR_DCOC_CTRL_1_BBA_CORR_POL_SHIFT) | + (TZA_CORR_POL_def_c << XCVR_DCOC_CTRL_1_TZA_CORR_POL_SHIFT) + )); + + if (gen1_dcgain_trims_enabled) + { + XCVR_BWR_DCOC_CTRL_1_BBF_DCOC_STEP(XCVR, BBF_STEP_def_c); /* Only write this field if Gen1 DC GAIN trims being used. */ + } + + /* DCOC_CTRL_2 */ + if (gen1_dcgain_trims_enabled) + { + XCVR_BWR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(XCVR, BBF_STEP_RECIP_def_c); + } + + /* DCOC_CAL_RCP */ + XCVR_DCOC_CAL_RCP = (uint32_t)((XCVR_DCOC_CAL_RCP & (uint32_t)~(uint32_t)( + XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK | + XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK + )) | (uint32_t)( + (RCP_GBHmGBL_def_c << XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT) | + (RCP_GLHmGLLxGBL_def_c << XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT) + )); + + return gXcvrSuccess_c; +} + +/*! ********************************************************************************* +* \brief This function sets up the TX_DIG and PLL settings +* +* \param[in] radioMode - the operating mode for the radio to be configured +* +* \return status of the operation. +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrSetTxDigPLLDefaults( radio_mode_t radioMode ) +{ + /* Configure the High Port Sigma Delta */ + XCVR_BWR_ANA_SPARE_HPM_LSB_INVERT(XCVR, HPM_LSB_INVERT_def_c); + XCVR_BWR_PLL_HPM_SDM_FRACTION_HPM_DENOM(XCVR, HPM_DENOM_def_c); + + /* Configure the PLL Modulation Delays */ + XCVR_BWR_PLL_DELAY_MATCH_HPM_BANK_DELAY(XCVR, HPM_BANK_DELAY_def_c); + XCVR_BWR_PLL_DELAY_MATCH_HPM_SDM_DELAY(XCVR, HPM_SDM_DELAY_def_c); + XCVR_BWR_PLL_DELAY_MATCH_LP_SDM_DELAY(XCVR, LP_SDM_DELAY_def_c); + + /* Configure PLL Loop Filter Configuration from Default value */ + XCVR_BWR_PLL_CTRL_PLL_LFILT_CNTL(XCVR, PLL_LFILT_CNTL_def_c); + + /* Change FSK_MODULATION_SCALE_1 from it Default value */ + XCVR_BWR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(XCVR, FSK_MODULATION_SCALE_1_def_c); + + /* PLL Dithering */ + XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_OVRD(XCVR, 1); /* Enable over-riding dither control */ + XCVR_BWR_PLL_LP_MOD_CTRL_LPM_DTH_SCL(XCVR, 0x8); /* Set dither range */ + XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_CTRL(XCVR, 1); /* Turn on dither all the time */ + + /* Use mode switch routine to setup the defaults that depend on radio mode (none at this time) */ + XcvrSetTxDigPLLDef_ModeSwitch(radioMode); +} + +/*! ********************************************************************************* +* \brief This function sets up the TX_DIG and PLL radio mode specific settings +* +* \param[in] radioMode - the operating mode for the radio to be configured +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrSetTxDigPLLDef_ModeSwitch( radio_mode_t radioMode ) +{ + +} + +/*! ********************************************************************************* +* \brief This function sets up the analog settings +* +* \param[in] radioMode - the operating mode for the radio to be configured +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrSetAnalogDefaults ( radio_mode_t radioMode ) +{ + /* Use mode switch routine to setup the defaults that depend on radio mode */ + XcvrSetAnalogDef_ModeSwitch(radioMode); + + /* Regulator trim and ADC trims */ + XCVR_BWR_PLL_CTRL2_PLL_VCO_REG_SUPPLY(XCVR, 1); + XCVR_BWR_ADC_TUNE_ADC_R1_TUNE(XCVR, 5); + XCVR_BWR_ADC_TUNE_ADC_R2_TUNE(XCVR, 5); + XCVR_BWR_ADC_TUNE_ADC_C1_TUNE(XCVR, 8); + XCVR_BWR_ADC_TUNE_ADC_C2_TUNE(XCVR, 8); + + XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP1_ADJ(XCVR, 5); + XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP2_ADJ(XCVR, 7); + XCVR_BWR_ADC_ADJ_ADC_IB_DAC1_ADJ(XCVR, 2); + XCVR_BWR_ADC_ADJ_ADC_IB_DAC2_ADJ(XCVR, 2); + XCVR_BWR_ADC_ADJ_ADC_IB_FLSH_ADJ(XCVR, 6); + XCVR_BWR_ADC_ADJ_ADC_FLSH_RES_ADJ(XCVR, 0); + + XCVR_BWR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(XCVR, 2); + XCVR_BWR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(XCVR, 4); + XCVR_BWR_ADC_TRIMS_ADC_VCM_TRIM(XCVR, 4); + + /* Raise QGEN and ADC_ANA and ADC_DIG supplies */ + XCVR_BWR_ADC_REGS_ADC_ANA_REG_SUPPLY(XCVR, 9); + XCVR_BWR_ADC_REGS_ADC_REG_DIG_SUPPLY(XCVR, 9); + XCVR_BWR_QGEN_CTRL_QGEN_REG_SUPPLY(XCVR, 9); +} + +/*! ********************************************************************************* +* \brief This function sets up the radio mode specific analog settings +* +* \param[in] radioMode - the operating mode for the radio to be configured +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrSetAnalogDef_ModeSwitch ( radio_mode_t radioMode ) +{ + switch (radioMode) + { + case BLE: + /* TZA_CTRL for BLE */ + XCVR_BWR_TZA_CTRL_TZA_CAP_TUNE(XCVR, ble_tza_cap_tune); + + /* BBF_CTRL for BLE */ + XCVR_BBF_CTRL = (uint32_t)((XCVR_BBF_CTRL & (uint32_t)~(uint32_t)( + XCVR_BBF_CTRL_BBF_CAP_TUNE_MASK | + XCVR_BBF_CTRL_BBF_RES_TUNE2_MASK | + XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_MASK + )) | (uint32_t)( + (ble_bbf_cap_tune << XCVR_BBF_CTRL_BBF_CAP_TUNE_SHIFT) | + (ble_bbf_res_tune2 << XCVR_BBF_CTRL_BBF_RES_TUNE2_SHIFT) | + (DCOC_ALPHAC_SCALE_GS_IDX_def_c << XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT) + )); + break; + case ZIGBEE: + /* TZA_CTRL for Zigbee */ + XCVR_BWR_TZA_CTRL_TZA_CAP_TUNE(XCVR, zb_tza_cap_tune); + + /* BBF_CTRL for Zigbee */ + XCVR_BBF_CTRL = (uint32_t)((XCVR_BBF_CTRL & (uint32_t)~(uint32_t)( + XCVR_BBF_CTRL_BBF_CAP_TUNE_MASK | + XCVR_BBF_CTRL_BBF_RES_TUNE2_MASK | + XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_MASK + )) | (uint32_t)( + (zb_bbf_cap_tune << XCVR_BBF_CTRL_BBF_CAP_TUNE_SHIFT) | + (zb_bbf_res_tune2 << XCVR_BBF_CTRL_BBF_RES_TUNE2_SHIFT) | + (DCOC_ALPHAC_SCALE_GS_IDX_def_c << XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT) + )); + break; + default: + break; + } +} + +/*! ********************************************************************************* +* \brief This function controls the enable/disable of RSSI IIR narrowband filter +* used in Zigbee CCA tests for narrowband RSSI measurement. +* +* \param[in] IIRnbEnable - enable or disable the narrowband IIR filter +* +* \ingroup PublicAPIs +* +* \details +* +***********************************************************************************/ +void XcvrEnaNBRSSIMeas( bool_t IIRnbEnable ) +{ + if (IIRnbEnable) + { + /* enable narrowband IIR filter for RSSI */ + XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(XCVR, RSSI_IIR_CW_WEIGHT_ENABLEDdef_c); + } + else + { + /* Disable narrowband IIR filter for RSSI */ + XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(XCVR, RSSI_IIR_CW_WEIGHT_BYPASSEDdef_c); + } +} + +/* Customer level trim functions */ +/*! ********************************************************************************* +* \brief This function sets the XTAL trim field to control crystal osc frequency. +* +* \param[in] xtalTrim - value to control the trim of the crystal osc. +* +* \return status of the operation. +* +* \ingroup PublicAPIs +* +* \details +* +***********************************************************************************/ +xcvrStatus_t XcvrSetXtalTrim(int8_t xtalTrim) +{ + XCVR_BWR_XTAL_CTRL_XTAL_TRIM(XCVR, xtalTrim); + return gXcvrSuccess_c; +} + +/*! ********************************************************************************* +* \brief This function reads the XTAL trim field +* +* \return the current value of the crystal osc trim. +* +* \ingroup PublicAPIs +* +* \details +* +***********************************************************************************/ +int8_t XcvrGetXtalTrim(void) +{ + return (int8_t)XCVR_BRD_XTAL_CTRL_XTAL_TRIM(XCVR); +} + +/*! ********************************************************************************* +* \brief This function sets the AGC gain setting table entry and the DCOC table +* entry to be used. +* +* \param[in] entry: Entry number from AGC table to use. +* +* \return status of the operation. +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +xcvrStatus_t XcvrSetGain ( uint8_t entry ) +{ +#if INCLUDE_OLD_DRV_CODE + if (entry > 26) + { + return gXcvrInvalidParameters_c; + } + + XCVR_AGC_CTRL_1_WR((uint32_t)((XCVR_AGC_CTRL_1_RD & (uint32_t)~(uint32_t)( + XCVR_AGC_CTRL_1_AGC_IDLE_GAIN_MASK + )) | (uint32_t)( + (entry << XCVR_AGC_CTRL_1_AGC_IDLE_GAIN_SHIFT) + ))); +#endif + return gXcvrSuccess_c; +} + +/*! ********************************************************************************* +* \brief This function sets the channel for test mode and overrides the BLE and Zigbee channel. +* +* \param[in] channel: Channel number. +* \param[in] useMappedChannel: Selects to use the channel map table (TRUE) or to use the manual frequency setting based on a SW table of numerator and denominator values for the PLL. +* +* \return status of the operation. +* +* \ingroup PrivateAPIs +* +* \details This function overrides both the BLE and Zigbee channel values from the respective LLs. +* +***********************************************************************************/ +xcvrStatus_t XcvrOverrideChannel ( uint8_t channel, uint8_t useMappedChannel ) +{ + if(channel == 0xFF) + { + /* Clear all of the overrides and restore to LL channel control */ + + XCVR_PLL_CHAN_MAP = (uint32_t)((XCVR_PLL_CHAN_MAP & (uint32_t)~(uint32_t)( + XCVR_PLL_CHAN_MAP_CHANNEL_NUM_MASK | + XCVR_PLL_CHAN_MAP_ZOC_MASK | + XCVR_PLL_CHAN_MAP_BOC_MASK + ))); + + /* Stop using the manual frequency setting */ + XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(XCVR, 0); + + return gXcvrSuccess_c; + } + + if(channel >= 128) + { + return gXcvrInvalidParameters_c; + } + + if(useMappedChannel == TRUE) + { + XCVR_PLL_CHAN_MAP = (uint32_t)((XCVR_PLL_CHAN_MAP & (uint32_t)~(uint32_t)( + XCVR_PLL_CHAN_MAP_CHANNEL_NUM_MASK | + XCVR_PLL_CHAN_MAP_BOC_MASK | + XCVR_PLL_CHAN_MAP_ZOC_MASK + )) | (uint32_t)( + (channel << XCVR_PLL_CHAN_MAP_CHANNEL_NUM_SHIFT) | + (0x01 << XCVR_PLL_CHAN_MAP_BOC_SHIFT) | + (0x01 << XCVR_PLL_CHAN_MAP_ZOC_SHIFT) + )); + } + else + { + XCVR_PLL_CHAN_MAP = (uint32_t)((XCVR_PLL_CHAN_MAP & (uint32_t)~(uint32_t)( + XCVR_PLL_CHAN_MAP_BOC_MASK | + XCVR_PLL_CHAN_MAP_ZOC_MASK + )) | (uint32_t)( + (0x01 << XCVR_PLL_CHAN_MAP_BOC_SHIFT) | + (0x01 << XCVR_PLL_CHAN_MAP_ZOC_SHIFT) + )); + + XCVR_BWR_PLL_LP_SDM_CTRL3_LPM_DENOM(XCVR, gPllDenom_c); + XCVR_BWR_PLL_LP_SDM_CTRL2_LPM_NUM(XCVR, mapTable[channel].numerator); + XCVR_BWR_PLL_LP_SDM_CTRL1_LPM_INTG(XCVR, mapTable[channel].integer); + + /* Stop using the LL channel map and use the manual frequency setting */ + XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(XCVR, 1); + } + + return gXcvrSuccess_c; +} + +/*! ********************************************************************************* +* \brief This function sets the frequency at the PLL for test mode and overrides the BLE/ZB channel +* +* \param[in] freq: Frequency in KHz. +* \param[in] refOsc: Osc in MHz. +* +* \return status of the operation. +* +* \ingroup PrivateAPIs +* +* \details + +The Manual carrier frequency selected can be calculated using the formula below: +Radio Carrier Frequency = ((Reference Clock Frequency x 2) x (LPM_INTG + +(LPM_NUM / LPM_DENOM)) +WARNING : The fraction (LPM_NUM / LPM_DENOM) must be in the range of -0.55 +to +0.55 for valid Sigma Delta Modulator operation. + +* +***********************************************************************************/ +xcvrStatus_t XcvrOverrideFrequency ( uint32_t freq , uint32_t refOsc) +{ + int32_t intg; + int32_t num; + int32_t denom = 0x04000000; + uint32_t sdRate = 64000000; + double fract_check; + + intg = (uint32_t) freq / sdRate; + + /* CTUNE Target must be loaded manually +/- 6MHz should be ok for PLL Lock. */ + XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(XCVR, freq/1000000); + XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TD(XCVR,1); /*CTUNE Target Disable */ + + XCVR_PLL_CHAN_MAP |= XCVR_PLL_CHAN_MAP_BOC_MASK | XCVR_PLL_CHAN_MAP_ZOC_MASK; + + XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(XCVR, 1); + + fract_check = (freq % sdRate); + fract_check /= sdRate; + + if (fract_check >= 0.55) + { + fract_check--; + intg++; + } + + num = refOsc; + num = (int32_t) (fract_check * denom); + + if (num < 0) + num = (((1 << 28) - 1) & ((1 << 28) - 1) - ABS(num)) + 1; + + XCVR_BWR_PLL_LP_SDM_CTRL1_LPM_INTG(XCVR, intg); + XCVR_BWR_PLL_LP_SDM_CTRL2_LPM_NUM(XCVR, num); + XCVR_BWR_PLL_LP_SDM_CTRL3_LPM_DENOM(XCVR, denom); + + return gXcvrSuccess_c; +} + +/*! ********************************************************************************* +* \brief This function reads the RF PLL values and returns the programmed frequency +* +* \return Frequency generated by the PLL. +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +uint32_t XcvrGetFreq ( void ) +{ + uint32_t pll_int, pll_denom; + int64_t pll_num; + + pll_int = XCVR_BRD_PLL_LP_SDM_CTRL1_LPM_INTG(XCVR); + pll_num = XCVR_BRD_PLL_LP_SDM_CTRL2_LPM_NUM(XCVR); + + if ( (pll_num & 0x0000000004000000) == 0x0000000004000000) + pll_num = 0xFFFFFFFFF8000000 + pll_num; /* Sign extend the numerator */ + + pll_denom = XCVR_BRD_PLL_LP_SDM_CTRL3_LPM_DENOM(XCVR); + + /* Original formula: ((float) pll_int + ((float)pll_num / (float)pll_denom)) * 64 */ + return (uint32_t)(pll_int << 6) + ((pll_num << 6) / pll_denom); /* Calculate the frequency in MHz */ +} + +/*! ********************************************************************************* +* \brief This function overrides the TSM module and starts the RX warmup procedure +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrForceRxWu ( void ) +{ + /* Set "FORCE_RX_EN" in TSM Control register */ + XCVR_BWR_TSM_CTRL_FORCE_RX_EN(XCVR, 1); +} + +/*! ********************************************************************************* +* \brief This function overrides the TSM module and starts the RX warmdown procedure +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrForceRxWd ( void ) +{ + /* Clear "FORCE_RX_EN" in TSM Control register */ + XCVR_BWR_TSM_CTRL_FORCE_RX_EN(XCVR, 0); +} + +/*! ********************************************************************************* +* \brief This function overrides the TSM module and starts the TX warmup procedure +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrForceTxWu ( void ) +{ + XCVR_BWR_TSM_CTRL_FORCE_TX_EN(XCVR, 1); +} + +/*! ********************************************************************************* +* \brief This function overrides the TSM module and starts the TX warmdown procedure +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrForceTxWd ( void ) +{ + XCVR_BWR_TSM_CTRL_FORCE_TX_EN(XCVR, 0); + + /* Clear "TX_CW_NOMOD" bit in TX Digital Control register */ + XCVR_BWR_TX_DIG_CTRL_DFT_MODE(XCVR, 0); /* Normal radio operation */ +} + +/*! ********************************************************************************* +* \brief This function performs an unmodulated TX test. +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrTxTest ( void ) +{ + volatile uint32_t rez[128], i; + + for(i=0;i<=127;i++) + { + XcvrOverrideChannel (i, 0); + rez[i] = XcvrGetFreq (); + XcvrForceTxWu(); + XcvrDelay(30000); + XcvrForceTxWd(); + } + + XcvrOverrideChannel (0xFF, 1); +} + +/*! ********************************************************************************* +* \brief Temporary delay function +* +* \param[in] time the number of counts to decrement through in a wait loop. +* +* \return none. +* +* \ingroup PrivateAPIs +* +* \details +* +***********************************************************************************/ +void XcvrDelay(volatile uint32_t time){ + while(time>0){ + time--; + } +} + +/*! ********************************************************************************* +* \brief Manual DCOC calibration function to support board level calibration. +* +* \param[in] chnum Channel number. +* +* \ingroup PrivateAPIs +* +* \details +* Performs manual DCOC calibration and sets TZA and BBF gains per this calibration. +* Disables DCOC_CAL_EN to prevent TSM signals from triggering calibration. +* Intended to enable software development to continue during DCOC cal debug. +* +***********************************************************************************/ +void XcvrManualDCOCCal (uint8_t chnum) +{ + static uint8_t DAC_idx; + static int16_t dc_meas_i; + static int16_t dc_meas_q; + static int16_t dc_meas_total; + static uint8_t curr_min_dc_tza_i_idx, curr_min_dc_tza_q_idx; + static int16_t curr_min_dc_tza_i, curr_min_dc_tza_q; + static int16_t curr_min_dc_total; + static uint8_t curr_min_dc_bbf_i_idx, curr_min_dc_bbf_q_idx; + static int16_t curr_min_dc_bbf_i, curr_min_dc_bbf_q; + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t dcoc_cal_gain_state; + uint8_t gearshift_state; + + XcvrOverrideChannel(chnum,TRUE); + + dcoc_ctrl_0_stack = XCVR_DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + dcoc_ctrl_1_stack = XCVR_DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + dcoc_cal_gain_state = XCVR_DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + gearshift_state = XCVR_BRD_ANA_SPARE_DCOC_TRK_EST_GS_CNT(XCVR); /* Save state of gearshift control for later restore */ + + /* Set DCOC_CTRL_0, DCOC_CAL_GAIN, and GEARSHIFT to appropriate values for manual nulling of DC */ + XCVR_DCOC_CTRL_0 = ((0x2 << XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT) | + (0x3 << XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT) | + (0x3 << XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT) | + (0x12 << XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT) | + (0x52 << XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT) | + (0x10 << XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT) | + (0x1 << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT) | + (0x1 << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT) | + (0x1 << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT) + ); + XCVR_DCOC_CTRL_1 = ((0x0 << XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_SHIFT) | + (0x1 << XCVR_DCOC_CTRL_1_BBA_CORR_POL_SHIFT) | + (0x1 << XCVR_DCOC_CTRL_1_TZA_CORR_POL_SHIFT) + ); + XCVR_DCOC_CAL_GAIN = ((0x03 << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_SHIFT) | + (0x02 << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_SHIFT) | + (0x08 << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_SHIFT) | + (0x02 << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_SHIFT) | + (0x03 << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_SHIFT) | + (0x08 << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_SHIFT) + ); + + XCVR_BWR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(XCVR, 0x00); + + /* Search for optimal DC DAC settings */ + XCVR_BWR_DCOC_CTRL_0_DCOC_TRACK_EN(XCVR, 1); /* DCOC track */ + XCVR_BWR_RX_DIG_CTRL_RX_AGC_EN(XCVR, 0); /* AGC Control */ + XCVR_BWR_RX_DIG_CTRL_RX_DCOC_EN(XCVR, 1); /* DCOC_EN */ + XCVR_BWR_RX_DIG_CTRL_RX_DCOC_CAL_EN(XCVR, 0); /* DCOC_CAL 0=disabled; 1=Enabled */ + XcvrForceRxWu(); + XcvrDelay(2000); + + XCVR_BWR_DCOC_CTRL_0_DCOC_MAN(XCVR, 1); /* Force dcoc dacs to use manual override */ + + /* Go through gain table to get each setting */ + + static uint8_t tbl_idx; + uint8_t * tbl_ptr=(uint8_t *)(&XCVR_AGC_GAIN_TBL_03_00); + static uint8_t tbl_val; + for (tbl_idx = 0; tbl_idx <27; tbl_idx++) + { + tbl_val = *tbl_ptr; + tbl_ptr++; + XCVR_BWR_AGC_CTRL_1_LNM_USER_GAIN(XCVR, ((0xF0&tbl_val)>>4)); /* Set Manual Gain Index for LNM */ + XCVR_BWR_AGC_CTRL_1_BBF_USER_GAIN(XCVR, (0x0F&tbl_val)); /* Set Manual Gain Index for BBF */ + XCVR_BWR_AGC_CTRL_1_USER_LNM_GAIN_EN(XCVR, 1); /* Use Manual Gain for LNM */ + XCVR_BWR_AGC_CTRL_1_USER_BBF_GAIN_EN(XCVR, 1); /* Use Manual Gain for BBF */ + + XcvrDelay(32*3); + + /* Init fixed, mid-point values for BBF while sweeping TZA */ + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(XCVR, 0x20); /* Set bbf I to mid */ + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, 0x20); /* Set bbf Q to mid */ + + /* Measure optimal TZA DAC setting */ + curr_min_dc_tza_i = 2000; + curr_min_dc_tza_q = 2000; + curr_min_dc_total = 4000; + DAC_idx=0; + + if(0) /* Set to 1 for brute force, takes a long time */ + { + do + { + XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(XCVR, (0x00FF & DAC_idx)); + XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(XCVR, (0xFF00 & DAC_idx)>>8); + XcvrDelay(32*2); + /* Take I measurement */ + dc_meas_i = XCVR_BRD_DCOC_DC_EST_DC_EST_I(XCVR); + dc_meas_i = dc_meas_i | ((dc_meas_i & 0x800) ? 0xF000 : 0x0); + dc_meas_i = (dc_meas_i < 0) ? (-1*dc_meas_i) : (dc_meas_i); + + /* Take Q measurement */ + dc_meas_q = XCVR_BRD_DCOC_DC_EST_DC_EST_Q(XCVR); + dc_meas_q = dc_meas_q | ((dc_meas_q & 0x800) ? 0xF000 : 0x0); + dc_meas_q = (dc_meas_q < 0) ? (-1*dc_meas_q) : (dc_meas_q); + dc_meas_total = dc_meas_i + dc_meas_q; + if(dc_meas_total < curr_min_dc_total) + { + curr_min_dc_total = dc_meas_total; + curr_min_dc_tza_i_idx = (0x00FF & DAC_idx); + curr_min_dc_tza_q_idx = (0xFF00 & DAC_idx)>>8; + } + + if(dc_meas_i < curr_min_dc_tza_i) + { + curr_min_dc_tza_i = dc_meas_i; + } + if(dc_meas_q < curr_min_dc_tza_q) + { + curr_min_dc_tza_q = dc_meas_q; + } + DAC_idx++; + } while (DAC_idx > 0); /* Relies on 8 bit increment rolling over to zero. */ + } + else + { + do /* First do I channel because it is aggressor */ + { + XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(XCVR, DAC_idx); + XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(XCVR, 0x80); + XcvrDelay(32*2); + + /* Take I measurement */ + dc_meas_i = XCVR_BRD_DCOC_DC_EST_DC_EST_I(XCVR); + dc_meas_i = dc_meas_i | ((dc_meas_i & 0x800) ? 0xF000 : 0x0); + dc_meas_i = (dc_meas_i < 0) ? (-1*dc_meas_i) : (dc_meas_i); + if(dc_meas_i < curr_min_dc_tza_i) + { + curr_min_dc_tza_i = dc_meas_i; + curr_min_dc_tza_i_idx = DAC_idx; + } + DAC_idx++; + } while (DAC_idx > 0); /* Relies on 8 bit increment rolling over to zero. */ + DAC_idx=0; + do /* First do Q channel */ + { + XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(XCVR, curr_min_dc_tza_i_idx); + XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(XCVR, DAC_idx); + XcvrDelay(32*2); + /* Take Q measurement */ + dc_meas_q = XCVR_BRD_DCOC_DC_EST_DC_EST_Q(XCVR); + dc_meas_q = dc_meas_q | ((dc_meas_q & 0x800) ? 0xF000 : 0x0); + dc_meas_q = (dc_meas_q < 0) ? (-1*dc_meas_q) : (dc_meas_q); + if(dc_meas_q < curr_min_dc_tza_q) + { + curr_min_dc_tza_q = dc_meas_q; + curr_min_dc_tza_q_idx = DAC_idx; + } + DAC_idx++; + } while (DAC_idx > 0); /* relies on 8 bit increment rolling over to zero. */ + } + /* Now set the manual TZA settings from this sweep */ + XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(XCVR, curr_min_dc_tza_i_idx); + XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(XCVR, curr_min_dc_tza_q_idx); + curr_min_dc_tza_i_idx = (curr_min_dc_tza_i_idx >= 0x80) ? ((curr_min_dc_tza_i_idx-0x80)) : ((0x80+curr_min_dc_tza_i_idx)); + curr_min_dc_tza_q_idx = (curr_min_dc_tza_q_idx >= 0x80) ? ((curr_min_dc_tza_q_idx-0x80)) : ((0x80+curr_min_dc_tza_q_idx)); + + /* Measure optimal BBF I DAC setting (I and Q split as there are I->Q DC changes) */ + curr_min_dc_bbf_i = curr_min_dc_tza_i; + curr_min_dc_bbf_i_idx = 0x20; + for (DAC_idx=0;DAC_idx<=63;DAC_idx+=1) + { + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(XCVR, DAC_idx); /* Adjust I bbf DAC */ + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, 0x20); //set bbf Q to mid + XcvrDelay(32*2); + dc_meas_i = XCVR_BRD_DCOC_DC_EST_DC_EST_I(XCVR); /* Take I measurement */ + dc_meas_i = dc_meas_i | ((dc_meas_i & 0x800) ? 0xF000 : 0x0); + dc_meas_i = (dc_meas_i < 0) ? (-1*dc_meas_i) : (dc_meas_i); + if(dc_meas_i < curr_min_dc_bbf_i) + { + curr_min_dc_bbf_i = dc_meas_i; + curr_min_dc_bbf_i_idx = DAC_idx; + } + } + + /* Measure optimal BBF Q DAC setting (I and Q split as there are I->Q DC changes) */ + curr_min_dc_bbf_q = curr_min_dc_tza_q; + curr_min_dc_bbf_q_idx = 0x20; + for (DAC_idx=0;DAC_idx<=63;DAC_idx+=1) + { + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(XCVR, curr_min_dc_bbf_i_idx); /* Set bbf I to calibrated value */ + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, DAC_idx); /* Adjust bbf Q */ + XcvrDelay(32*2); + dc_meas_q = XCVR_BRD_DCOC_DC_EST_DC_EST_Q(XCVR); /* Take Q measurement */ + dc_meas_q = dc_meas_q | ((dc_meas_q & 0x800) ? 0xF000 : 0x0); + XcvrDelay(32*2); + dc_meas_q = (dc_meas_q < 0) ? (-1*dc_meas_q) : (dc_meas_q); + if(dc_meas_q < curr_min_dc_bbf_q) + { + curr_min_dc_bbf_q = dc_meas_q; + curr_min_dc_bbf_q_idx = DAC_idx; + } + } + /* Now set the manual BBF Q settings from this sweep */ + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, curr_min_dc_bbf_q_idx); /* Set bbf Q to new manual value */ + XcvrDelay(32*15); + + dc_meas_i = XCVR_BRD_DCOC_DC_EST_DC_EST_I(XCVR); /* Take final I measurement */ + XcvrDelay(32*10); + dc_meas_q = XCVR_BRD_DCOC_DC_EST_DC_EST_Q(XCVR); /* Take final Q measurement */ + dc_meas_q = dc_meas_q | ((dc_meas_q & 0x800) ? 0xF000 : 0x0); + dc_meas_i = dc_meas_i | ((dc_meas_i & 0x800) ? 0xF000 : 0x0); + XcvrDelay(32*2); + + /* Store this gain setting's dc dac values */ + XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(XCVR, tbl_idx,curr_min_dc_tza_q_idx); + XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(XCVR, tbl_idx,curr_min_dc_tza_i_idx); + curr_min_dc_bbf_i_idx = (curr_min_dc_bbf_i_idx >= 0x20) ? ((curr_min_dc_bbf_i_idx-0x20)) : (0x20+(curr_min_dc_bbf_i_idx)); + curr_min_dc_bbf_q_idx = (curr_min_dc_bbf_q_idx >= 0x20) ? ((curr_min_dc_bbf_q_idx-0x20)) : (0x20+(curr_min_dc_bbf_q_idx)); + XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(XCVR, tbl_idx,curr_min_dc_bbf_q_idx); + XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(XCVR, tbl_idx,curr_min_dc_bbf_i_idx); + } + + /* Now set the manual BBF settings from this sweep */ + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(XCVR, curr_min_dc_bbf_i_idx); /* Set bbf I to new manual value */ + XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(XCVR, curr_min_dc_bbf_q_idx); /* Set bbf Q to new manual value */ + XCVR_BWR_DCOC_CTRL_0_DCOC_TRACK_EN(XCVR, DCOC_TRACK_EN_def_c); /* Disable tracking */ + XCVR_BWR_DCOC_CTRL_0_DCOC_MAN(XCVR, 0); /* Force dcoc dacs to not use manual override */ + + XCVR_BWR_DCOC_CTRL_1_BBA_CORR_POL(XCVR, 1); + XCVR_BWR_DCOC_CTRL_1_TZA_CORR_POL(XCVR, 1); + XcvrForceRxWd(); + XcvrDelay(200); + + /* Revert AGC settings to normal values for usage */ + XCVR_BWR_AGC_CTRL_1_USER_LNM_GAIN_EN(XCVR, 0); /* Use Manual Gain for LNM */ + XCVR_BWR_AGC_CTRL_1_USER_BBF_GAIN_EN(XCVR, 0); /* Use Manual Gain for BBF */ + XCVR_BWR_RX_DIG_CTRL_RX_AGC_EN(XCVR, RX_AGC_EN_def_c); /* AGC Control enabled */ + XCVR_DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_BWR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(XCVR, gearshift_state); /* Restore gearshift state to prior setting */ + XCVR_DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XcvrOverrideChannel(0xFF,TRUE); /* Release channel overrides */ +} + +/*! ********************************************************************************* +* \brief IQ Mismatch Calibration. Performs IQMCalibrationIter calibrations, averages and set the calibration values in the XCVR_IQMC_CAL register +* +* \ingroup PublicAPIs +* +* \details IQMC requires a tone input of 250 kHz (+/-75 kHz) to be applied at the RF port and RF/Ana gains set up to for a 0-5 dBm signal at ADC +* +***********************************************************************************/ +void XcvrIQMCal ( void ) +{ + uint8_t CH_filt_bypass_state; + uint8_t Decimator_OSR_state; + uint16_t IQMC_gain_cal_trials[IQMCalibrationTrials]={0}; + uint16_t IQMC_phase_cal_trials[IQMCalibrationTrials]={0}; + uint8_t cnt; + uint32_t cal_wait_time; + uint32_t IQMC_gain_adj_sum = 0; + uint32_t IQMC_phase_adj_sum = 0; + uint16_t IQMC_gain_adj_mean = 0; + uint16_t IQMC_phase_adj_mean = 0; + + /* Read current Rx Decimation OSR Value and Channel Filter State. Set Decimation Filter OSR to 2 and Bypass Rx Channel Filter */ + Decimator_OSR_state = XCVR_BRD_RX_DIG_CTRL_RX_DEC_FILT_OSR(XCVR); + CH_filt_bypass_state = XCVR_BRD_RX_DIG_CTRL_RX_CH_FILT_BYPASS(XCVR); + XCVR_BWR_RX_DIG_CTRL_RX_DEC_FILT_OSR(XCVR, 2); /* Set Decimation OSR to 2 */ + XCVR_BWR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(XCVR, 1); /* Bypass Channel Filter */ + + for (cnt=0;cnt> XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT) +#define XCVR_BRD_ANA_SPARE_HPM_LSB_INVERT(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT, XCVR_ANA_SPARE_HPM_LSB_INVERT_WIDTH)) + +/*! @brief Set the HPM_LSB_INVERT field to a new value. */ +#define XCVR_WR_ANA_SPARE_HPM_LSB_INVERT(base, value) (XCVR_RMW_ANA_SPARE(base, XCVR_ANA_SPARE_HPM_LSB_INVERT_MASK, XCVR_ANA_SPARE_HPM_LSB_INVERT(value))) +#define XCVR_BWR_ANA_SPARE_HPM_LSB_INVERT(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), ((uint32_t)(value) << XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT), XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT, XCVR_ANA_SPARE_HPM_LSB_INVERT_WIDTH)) +/*@}*/ + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ +typedef enum +{ + gXcvrSuccess_c = 0, + gXcvrInvalidParameters_c, + gXcvrUnsupportedOperation_c +} xcvrStatus_t; + +typedef enum +{ + NO_ERRORS = 0, + PLL_CTUNE_FAIL = 1, + PLL_CYCLE_SLIP_FAIL = 2, + PLL_FREQ_TARG_FAIL = 4, + PLL_TSM_ABORT_FAIL = 8, +} healthStatus_t; + +typedef struct pllChannel_tag +{ + unsigned int integer; + unsigned int numerator; +} pllChannel_t; + +typedef enum +{ + BLE = 0x00, + ZIGBEE = 0x01, + INVALID_MODE = 0xFF +} radio_mode_t; + +typedef enum +{ + NONE = 0, + FAD_ENABLED = 1, + LPPS_ENABLED = 2 +} FAD_LPPS_CTRL_T; + +typedef enum +{ + WRONG_RADIO_ID_DETECTED = 1, + CALIBRATION_INVALID = 2, +} XCVR_PANIC_ID_T; + +typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2); + +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +#ifdef __cplusplus +extern "C" { +#endif + +/* Normal radio functions */ +void XcvrInit ( radio_mode_t radioMode ); /* Full XCVR initialization for a radio mode */ +xcvrStatus_t XcvrChangeMode ( radio_mode_t radioMode ); /* Change from one radio mode to another */ +void XcvrEnaNBRSSIMeas( bool_t IIRnbEnable ); +xcvrStatus_t XcvrOverrideFrequency ( uint32_t freq, uint32_t refOsc ); +void XcvrRegisterPanicCb ( panic_fptr fptr ); /* allow upper layers to provide PANIC callback */ +healthStatus_t XcvrHealthCheck ( void ); /* allow upper layers to poll the radio health */ +void XcvrFadLppsControl(FAD_LPPS_CTRL_T control); + +/* Customer level trim functions */ +xcvrStatus_t XcvrSetXtalTrim(int8_t xtalTrim); +int8_t XcvrGetXtalTrim(void); + +/* Radio debug functions */ +xcvrStatus_t XcvrSetGain ( uint8_t entry ); +xcvrStatus_t XcvrOverrideChannel ( uint8_t channel, uint8_t useMappedChannel ); +uint32_t XcvrGetFreq ( void ); +void XcvrForceRxWu ( void ); +void XcvrForceRxWd ( void ); +void XcvrForceTxWu ( void ); +void XcvrForceTxWd ( void ); +void XcvrTxTest ( void ); +void XcvrIQMCal ( void ); /* Manual IQ Mismatch Calibration */ +void XcvrManualDCOCCal (uint8_t chnum); /* Allow tests to run multiple SW DC calibrations */ + +#ifdef __cplusplus +} +#endif + +#endif /* __KW4X_XCVR_DRV_H__ */ \ No newline at end of file diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ZigbeeDefaults.h b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ZigbeeDefaults.h new file mode 100644 index 000000000..165e9a97e --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ZigbeeDefaults.h @@ -0,0 +1,105 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* \file ZigbeeDefaults.h +* This is a header file for the default register values of the transceiver used +* for Zigbee mode. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef __ZIGBEE_DEFAULTS_H__ +#define __ZIGBEE_DEFAULTS_H__ + +/*! ********************************************************************************* +************************************************************************************* +* Constants +************************************************************************************* +********************************************************************************** */ +/* XCVR_CTRL Defaults */ + +/* XCVR_CTRL */ +#define Zigbee_TGT_PWR_SRC_def_c 0x02 +#define Zigbee_PROTOCOL_def_c 0x04 + +/* TSM Defaults (no PA ramp)*/ + +/*Analog: BBW Filter */ + +/* XCVR_TZA_CTRL */ +#define ZGBE_TZA_CAP_TUNE_def_c 0 + +/* XCVR_BBF_CTRL */ +#define ZGBE_BBF_CAP_TUNE_def_c 0 +#define ZGBE_BBF_RES_TUNE2_def_c 0 + +/*RX DIG: AGC DCOC and filtering */ + +/*RX_DIG_CTRL*/ +#define RX_DEC_FILT_OSR_Zigbee_def_c 0x02 +#define RX_NORM_EN_Zigbee_def_c 0x01 +#define RX_CH_FILT_BYPASS_Zigbee_def_c 0x00 + +/* AGC_CTRL_0 */ +#define FREEZE_AGC_SRC_Zigbee_def_c 0x02 + +/* RSSI_CTRL 0*/ +#define RSSI_HOLD_SRC_Zigbee_def_c 0x03 + +/* DCOC_CTRL_0 */ +#define DCOC_CAL_DURATION_Zigbee_def_c 0x15 /* Max: 1F */ +#define DCOC_CORR_HOLD_TIME_Zigbee_def_c 0x58 /* 0x7F makes corrections continuous. */ +#define DCOC_CORR_DLY_Zigbee_def_c 0x15 +#define ALPHA_RADIUS_IDX_Zigbee_def_c 0x02 /* 1/4 */ +#define ALPHAC_SCALE_IDX_Zigbee_def_c 0x01 /* 1/4 */ +#define SIGN_SCALE_IDX_Zigbee_def_c 0x03 /* 1/32 */ +#define DCOC_CORRECT_EN_Zigbee_def_c 0x01 +#define DCOC_TRACK_EN_Zigbee_def_c 0x01 +#define DCOC_MAN_Zigbee_def_c 0x00 + +/*RX_CHF_COEFn*/ +/*Dig Channel Setting 2015/05/28 - 860kHz Rx BW: Kaiser 3.0: */ +#define RX_CHF_COEF0_Zigbee_def_c 0xFE +#define RX_CHF_COEF1_Zigbee_def_c 0xFD +#define RX_CHF_COEF2_Zigbee_def_c 0x05 +#define RX_CHF_COEF3_Zigbee_def_c 0x08 +#define RX_CHF_COEF4_Zigbee_def_c 0xF5 +#define RX_CHF_COEF5_Zigbee_def_c 0xEA +#define RX_CHF_COEF6_Zigbee_def_c 0x10 +#define RX_CHF_COEF7_Zigbee_def_c 0x49 + +/* DCOC_CAL_IIR */ +#define IIR3A_IDX_Zigbee_def_c 0x001 +#define IIR2A_IDX_Zigbee_def_c 0x002 +#define IIR1A_IDX_Zigbee_def_c 0x002 + +/* CORR_CTRL */ +#define CORR_VT_Zigbee_def_c 0x6B +#define CORR_NVAL_Zigbee_def_c 3 + + +#endif /* __ZIGBEE_DEFAULTS_H__*/ \ No newline at end of file diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/fsl_xcvr.h b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/fsl_xcvr.h new file mode 100644 index 000000000..0a0c1cd36 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/fsl_xcvr.h @@ -0,0 +1,36 @@ +#ifndef _FSL_XCVR_H_ +#define _FSL_XCVR_H_ + +#include "MKW40Z4.h" +#include "KW4xXcvrDrv.h" + +#define Radio_1_IRQn ZigBee_IRQn +#define ZIGBEE_MODE ZIGBEE +#define XCVR_TSM XCVR +#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK ZLL_RX_FRAME_FILTER_FRM_VER_MASK +#define ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(x) ZLL_RX_FRAME_FILTER_FRM_VER(x) +#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK XCVR_END_OF_SEQ_END_OF_RX_WU_MASK +#define XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT XCVR_END_OF_SEQ_END_OF_RX_WU_SHIFT +#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK XCVR_END_OF_SEQ_END_OF_TX_WU_MASK +#define XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT XCVR_END_OF_SEQ_END_OF_TX_WU_SHIFT + +/*! @brief Data rate selections. Imported from MKW41Z4. */ +typedef enum _data_rate +{ + DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */ + DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */ + DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */ +#if RADIO_IS_GEN_3P0 + DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */ +#endif /* RADIO_IS_GEN_3P0 */ + DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */ +} data_rate_t; + +xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) +{ + XcvrInit(radio_mode); + + return gXcvrSuccess_c; +} + +#endif /* _FSL_XCVR_H_ */ diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ifr_mkw40z4_radio.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ifr_mkw40z4_radio.c new file mode 100644 index 000000000..3c2ec4361 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW40Z4/ifr_mkw40z4_radio.c @@ -0,0 +1,392 @@ +/*! +* Copyright (c) 2015, Freescale Semiconductor, Inc. +* All rights reserved. +* +* \file ifr_mkw40z4_radio.c +* MKW40Z4 Radio IFR pack/unpack function. +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +/*! ********************************************************************************* +************************************************************************************* +* Include +************************************************************************************* +********************************************************************************** */ +#include "EmbeddedTypes.h" +#include "ifr_mkw40z4_radio.h" +#include "MKW40Z4.h" +#include "KW4xXcvrDrv.h" +#include "fsl_device_registers.h" +#include "fsl_os_abstraction.h" + +/*! ********************************************************************************* +************************************************************************************* +* Private macros +************************************************************************************* +********************************************************************************** */ +#define IFR_RAM (0) + +#define mem32(x) (*(volatile uint32_t *)(x)) + +/*! ********************************************************************************* +************************************************************************************* +* Public memory declarations +************************************************************************************* +********************************************************************************** */ +const uint32_t BLOCK_1_IFR[]= +{ + 0xABCDFFFE, /* Version #FFFE indicates default trim values */ + 0x4005C47C, /* IQMC_DC_GAIN_ADJ id */ + 0x00000400, /* IQMC_DC_GAIN_ADJ default value */ + 0x4005C050, /* XCVR_IQMC_CAL id */ + 0x00000400, /* IQMC_PHASE_ADJ=0x000 and IQMC_GAIN_ADJ=0x400 (default value) */ + 0x4005C43C, /* XCVR_BGAP_CTRL id */ + 0x00000087, /* XCVR_BGAP_CTRL=0x08 */ + 0x00000002, /* ZB_FILT_TRIM id */ + 0x00440000, /* ZB_FILT_TRIM = BBF_CAP_TUNE<3:0>=0x3, BBF_RES_TUNE2<3:0>=0x3, TZA_CAP_TUNE<3:0>=0x3 */ + 0x00000003, /* BLE_FILT_TRIM id */ + 0x00640004, /* BLE_FILT_TRIM = BBF_CAP_TUNE<3:0>=0x3, BBF_RES_TUNE2<3:0>=0x6, TZA_CAP_TUNE<3:0>=0x3 */ + 0x4005C024, /* BBF_DCOC_STEP */ + 0x00000147, + 0x4005C028, /* BBF_DCOC_STEP_RCP */ + 0x00000322, + 0x4005C110, /* TZA_DCOC_STEP & STEP_RCP */ + 0x005C0B21, + 0x4005C114, + 0x008D0743, + 0x4005C118, + 0x00D304DA, + 0x4005C11C, + 0x0136034E, + 0x4005C120, + 0x01C30245, + 0x4005C124, + 0x02890194, + 0x4005C128, + 0x03A3011A, + 0x4005C12C, + 0x053000C5, + 0x4005C130, + 0x0761008B, + 0x4005C134, + 0x0A790062, + 0x4005C138, + 0x0ED70045, + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0F /* End of File */ +}; + +/*! ********************************************************************************* +************************************************************************************* +* Private prototypes +************************************************************************************* +********************************************************************************** */ +void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data); + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +* \brief Read Resource IFR +* +* Read command for reading from IFR +* +* \param[in] read_addr flash address +* +* \return Packed data containing radio trims only. +* +********************************************************************************** */ +uint32_t read_resource_ifr(uint32_t read_addr) +{ + uint32_t packed_data; + uint8_t flash_addr23_16,flash_addr15_8,flash_addr7_0; + uint8_t read_data31_24,read_data23_16,read_data15_8,read_data7_0; + + flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000)>>16); + flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00)>>8); + flash_addr7_0 = (uint8_t)(read_addr & 0xFF); + +#if SILICON + while((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT)==0); /* Wait till CCIF=1 */ +#endif /* SILICON */ + + if ((FTFA->FSTAT & FTFA_FSTAT_ACCERR_MASK)== FTFA_FSTAT_ACCERR_MASK ) + { + FTFA->FSTAT = (1<FSTAT = FTFA_FSTAT_CCIF_MASK; + while((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT)==0); /* Wait till CCIF=1 */ + + /* Enable Interrupts */ + OSA_InterruptEnable(); + + /* Start reading */ + read_data31_24 = FTFA->FCCOB4; + read_data23_16 = FTFA->FCCOB5; + read_data15_8 = FTFA->FCCOB6; + read_data7_0 = FTFA->FCCOB7; + + packed_data = (read_data31_24<<24)|(read_data23_16<<16)|(read_data15_8<<8)|(read_data7_0<<0); + + return packed_data; +} + +uint32_t read_resource(uint16_t resource_id) +{ + uint32_t ifr_addr; + + /* Return the test arrays of packed bits */ + switch (resource_id) + { + case 0x84: +#if IFR_RAM + return 0x4370; /* TZA_CAP_TUNE=0b0100; BBF_CAP_TUNE=4’b0011; BBF_RES_TUNE2=4’b0111 */ +#else + ifr_addr = read_resource_ifr(0x84); + return ifr_addr; +#endif + break; + case 0x98: +#if IFR_RAM + return 0x40000000; /* IQMC_GAIN)ADJ=0b10000000000 */ +#else + ifr_addr = read_resource_ifr(0x98); + return ifr_addr; +#endif + break; + case 0x9C: +#if IFR_RAM + return 0x37000000; /* BGAP_V Trim = 0b0011 & BGAP_I Trim=0b0111 */ +#else + ifr_addr = read_resource_ifr(0x9C); + return ifr_addr; +#endif + case 0x90: + ifr_addr = read_resource_ifr(0x90); + return ifr_addr; + + case 0x80: + ifr_addr = read_resource_ifr(0x80); + return ifr_addr; + + case 0x88: + ifr_addr = read_resource_ifr(0x88); + return ifr_addr; + + break; + default: + return 0x12345678; + break; + } +} + +/*! ********************************************************************************* +* \brief Store a SW trim value in the table passed in from calling function. +* +* \param[in] sw_trim_tbl pointer to the software trim table to hold SW trim values +* \param[in] num_entries the number of entries in the SW trim table +* \param[in] addr the software trim ID +* \param[in] data the value of the software trim +* +* \return None. +* +********************************************************************************** */ +void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data) +{ + uint16_t i; + if (sw_trim_tbl != NULL) + { + for (i=0;i +#include "EmbeddedTypes.h" + +/*! ********************************************************************************* +************************************************************************************* +* Macros +************************************************************************************* +********************************************************************************** */ +#define IFR_EOF_SYMBOL (0xFEED0E0F) /* Denotes the "End of File" for IFR data */ +#define IFR_VERSION_HDR (0xABCD0000) /* Constant value for upper 16 bits of IFR data header */ +#define IFR_VERSION_MASK (0x0000FFFF) /* Mask for version number (lower 16 bits) of IFR data header */ +#define IFR_SW_ID_MIN (0x00000000) /* Lower limit of SW trim IDs */ +#define IFR_SW_ID_MAX (0x0000FFFF) /* Lower limit of SW trim IDs */ + +#define IS_A_SW_ID(x) ((IFR_SW_ID_MIN=x)) +#define IS_VALID_REG_ADDR(x) (((x)&0xFFFF0000) == 0x40050000) /* Valid addresses are 0x4005xxxx */ + +#define MAKE_MASK(size) ((1<<(size))-1) +#define MAKE_MASKSHFT(size,bitpos) (MAKE_MASK(size)< +#include "tsm_ll_timing.h" +#include "fsl_device_registers.h" + +/*! ********************************************************************************* +************************************************************************************* +* Constants +************************************************************************************* +********************************************************************************** */ +#define USE_RAM_TESTING 0 +#define END_OF_SEQ_END_OF_TX_WU_MASK 0xFF +#define END_OF_SEQ_END_OF_TX_WU_SHIFT 0 + +#define END_OF_SEQ_END_OF_TX_WD_MASK 0xFF00 +#define END_OF_SEQ_END_OF_TX_WD_SHIFT 8 + +#define END_OF_SEQ_END_OF_RX_WU_MASK 0xFF0000 +#define END_OF_SEQ_END_OF_RX_WU_SHIFT 16 + +#define END_OF_SEQ_END_OF_RX_WD_MASK 0xFF000000 +#define END_OF_SEQ_END_OF_RX_WD_SHIFT 24 + +#define BLE_REG_BASE 0x4005B000 +#define TX_RX_ON_DELAY ( 0x190 ) /* 32-bit:0x190 address */ +#define TX_RX_SYNTH_DELAY ( 0x198 ) /* 32-bit:0x198 address */ + +#define PLL_REG_EN_INDEX (0) +#define PLL_VCO_REG_EN_INDEX (1) +#define PLL_QGEN_REG_EN_INDEX (2) +#define PLL_TCA_TX_REG_EN_INDEX (3) +#define ADC_REG_EN_INDEX (4) +#define PLL_REF_CLK_EN_INDEX (5) +#define ADC_CLK_EN_INDEX (6) +#define PLL_VCO_AUTOTUNE_INDEX (7) +#define PLL_CYCLE_SLIP_LD_EN_INDEX (8) +#define PLL_VCO_EN_INDEX (9) +#define PLL_VCO_BUF_RX_EN_INDEX (10) +#define PLL_VCO_BUF_TX_EN_INDEX (11) +#define PLL_PA_BUF_EN_INDEX (12) +#define PLL_LDV_EN_INDEX (13) +#define PLL_RX_LDV_RIPPLE_MUX_EN_INDEX (14) +#define PLL_TX_LDV_RIPPLE_MUX_EN_INDEX (15) +#define PLL_FILTER_CHARGE_EN_INDEX (16) +#define PLL_PHDET_EN_INDEX (17) +#define QGEN25_EN_INDEX (18) +#define TX_EN_INDEX (19) +#define ADC_EN_INDEX (20) +#define ADC_I_Q_EN_INDEX (21) +#define ADC_DAC_EN_INDEX (22) +#define ADC_RST_EN_INDEX (23) +#define BBF_EN_INDEX (24) +#define TCA_EN_INDEX (25) +#define PLL_DIG_EN_INDEX (26) +#define TX_DIG_EN_INDEX (27) +#define RX_DIG_EN_INDEX (28) +#define RX_INIT_INDEX (29) +#define SIGMA_DELTA_EN_INDEX (30) +#define ZBDEM_RX_EN_INDEX (31) +#define DCOC_EN_INDEX (32) +#define DCOC_INIT_EN_INDEX (33) +#define FREQ_TARG_LD_EN_INDEX (34) +#define SAR_ADC_TRIG_EN_INDEX (35) +#define TSM_SPARE0_EN_INDEX (36) +#define TSM_SPARE1_EN_INDEX (37) +#define TSM_SPARE2_EN_INDEX (38) +#define TSM_SPARE03_EN_INDEX (39) +#define GPIO0_TRIG_EN_INDEX (40) +#define GPIO1_TRIG_EN_INDEX (41) +#define GPIO2_TRIG_EN_INDEX (42) +#define GPIO3_TRIG_EN_INDEX (43) + +/*! ********************************************************************************* +************************************************************************************* +* Private memory declarations +************************************************************************************* +********************************************************************************** */ + +/* Array of initialization values for TSM Timing registers. + * Stored in the same order as the registers so that it can be copied easily. + */ +static const uint32_t ble_tsm_init_blt [NUM_TSM_TIMING_REGS] = +{ + TSM_REG_VALUE(PLL_REG_EN_RX_WD, PLL_REG_EN_RX_WU, PLL_REG_EN_TX_WD, PLL_REG_EN_TX_WU), + TSM_REG_VALUE(PLL_VCO_REG_EN_RX_WD, PLL_VCO_REG_EN_RX_WU, PLL_VCO_REG_EN_TX_WD, PLL_VCO_REG_EN_TX_WU), + TSM_REG_VALUE(PLL_QGEN_REG_EN_RX_WD, PLL_QGEN_REG_EN_RX_WU, PLL_QGEN_REG_EN_TX_WD, PLL_QGEN_REG_EN_TX_WU), + TSM_REG_VALUE(PLL_TCA_TX_REG_EN_RX_WD, PLL_TCA_TX_REG_EN_RX_WU, PLL_TCA_TX_REG_EN_TX_WD, PLL_TCA_TX_REG_EN_TX_WU), + TSM_REG_VALUE(ADC_REG_EN_RX_WD, ADC_REG_EN_RX_WU, ADC_REG_EN_TX_WD, ADC_REG_EN_TX_WU), + TSM_REG_VALUE(PLL_REF_CLK_EN_RX_WD, PLL_REF_CLK_EN_RX_WU, PLL_REF_CLK_EN_TX_WD, PLL_REF_CLK_EN_TX_WU), + TSM_REG_VALUE(ADC_CLK_EN_RX_WD, ADC_CLK_EN_RX_WU, ADC_CLK_EN_TX_WD, ADC_CLK_EN_TX_WU), + TSM_REG_VALUE(PLL_VCO_AUTOTUNE_RX_WD, PLL_VCO_AUTOTUNE_RX_WU, PLL_VCO_AUTOTUNE_TX_WD, PLL_VCO_AUTOTUNE_TX_WU), + TSM_REG_VALUE(PLL_CYCLE_SLIP_LD_EN_RX_WD, PLL_CYCLE_SLIP_LD_EN_RX_WU, PLL_CYCLE_SLIP_LD_EN_TX_WD, PLL_CYCLE_SLIP_LD_EN_TX_WU), + TSM_REG_VALUE(PLL_VCO_EN_RX_WD, PLL_VCO_EN_RX_WU, PLL_VCO_EN_TX_WD, PLL_VCO_EN_TX_WU), + TSM_REG_VALUE(PLL_VCO_BUF_RX_EN_RX_WD, PLL_VCO_BUF_RX_EN_RX_WU, PLL_VCO_BUF_RX_EN_TX_WD, PLL_VCO_BUF_RX_EN_TX_WU), + TSM_REG_VALUE(PLL_VCO_BUF_TX_EN_RX_WD, PLL_VCO_BUF_TX_EN_RX_WU, PLL_VCO_BUF_TX_EN_TX_WD, PLL_VCO_BUF_TX_EN_TX_WU), + TSM_REG_VALUE(PLL_PA_BUF_EN_RX_WD, PLL_PA_BUF_EN_RX_WU, PLL_PA_BUF_EN_TX_WD, PLL_PA_BUF_EN_TX_WU), + TSM_REG_VALUE(PLL_LDV_EN_RX_WD, PLL_LDV_EN_RX_WU, PLL_LDV_EN_TX_WD, PLL_LDV_EN_TX_WU), + TSM_REG_VALUE(PLL_RX_LDV_RIPPLE_MUX_EN_RX_WD, PLL_RX_LDV_RIPPLE_MUX_EN_RX_WU, PLL_RX_LDV_RIPPLE_MUX_EN_TX_WD, PLL_RX_LDV_RIPPLE_MUX_EN_TX_WU), + TSM_REG_VALUE(PLL_TX_LDV_RIPPLE_MUX_EN_RX_WD, PLL_TX_LDV_RIPPLE_MUX_EN_RX_WU, PLL_TX_LDV_RIPPLE_MUX_EN_TX_WD, PLL_TX_LDV_RIPPLE_MUX_EN_TX_WU), + TSM_REG_VALUE(PLL_FILTER_CHARGE_EN_RX_WD, PLL_FILTER_CHARGE_EN_RX_WU, PLL_FILTER_CHARGE_EN_TX_WD, PLL_FILTER_CHARGE_EN_TX_WU), + TSM_REG_VALUE(PLL_PHDET_EN_RX_WD, PLL_PHDET_EN_RX_WU, PLL_PHDET_EN_TX_WD, PLL_PHDET_EN_TX_WU), + TSM_REG_VALUE(QGEN25_EN_RX_WD, QGEN25_EN_RX_WU, QGEN25_EN_TX_WD, QGEN25_EN_TX_WU), + TSM_REG_VALUE(TX_EN_RX_WD, TX_EN_RX_WU, TX_EN_TX_WD, TX_EN_TX_WU), + TSM_REG_VALUE(ADC_EN_RX_WD, ADC_EN_RX_WU, ADC_EN_TX_WD, ADC_EN_TX_WU), + TSM_REG_VALUE(ADC_I_Q_EN_RX_WD, ADC_I_Q_EN_RX_WU, ADC_I_Q_EN_TX_WD, ADC_I_Q_EN_TX_WU), + TSM_REG_VALUE(ADC_DAC_EN_RX_WD, ADC_DAC_EN_RX_WU, ADC_DAC_EN_TX_WD, ADC_DAC_EN_TX_WU), + TSM_REG_VALUE(ADC_RST_EN_RX_WD, ADC_RST_EN_RX_WU, ADC_RST_EN_TX_WD, ADC_RST_EN_TX_WU), + TSM_REG_VALUE(BBF_EN_RX_WD, BBF_EN_RX_WU, BBF_EN_TX_WD, BBF_EN_TX_WU), + TSM_REG_VALUE(TCA_EN_RX_WD, TCA_EN_RX_WU, TCA_EN_TX_WD, TCA_EN_TX_WU), + TSM_REG_VALUE(PLL_DIG_EN_RX_WD, PLL_DIG_EN_RX_WU, PLL_DIG_EN_TX_WD, PLL_DIG_EN_TX_WU), + TSM_REG_VALUE(TX_DIG_EN_RX_WD, TX_DIG_EN_RX_WU, TX_DIG_EN_TX_WD, TX_DIG_EN_TX_WU), + TSM_REG_VALUE(RX_DIG_EN_RX_WD, RX_DIG_EN_RX_WU, RX_DIG_EN_TX_WD, RX_DIG_EN_TX_WU), + TSM_REG_VALUE(RX_INIT_RX_WD, RX_INIT_RX_WU, RX_INIT_TX_WD, RX_INIT_TX_WU), + TSM_REG_VALUE(SIGMA_DELTA_EN_RX_WD, SIGMA_DELTA_EN_RX_WU, SIGMA_DELTA_EN_TX_WD, SIGMA_DELTA_EN_TX_WU), + TSM_REG_VALUE(ZBDEM_RX_EN_RX_WD, ZBDEM_RX_EN_RX_WU, ZBDEM_RX_EN_TX_WD, ZBDEM_RX_EN_TX_WU), + TSM_REG_VALUE(DCOC_EN_RX_WD, DCOC_EN_RX_WU, DCOC_EN_TX_WD, DCOC_EN_TX_WU), + TSM_REG_VALUE(DCOC_INIT_EN_RX_WD, DCOC_INIT_EN_RX_WU, DCOC_INIT_EN_TX_WD, DCOC_INIT_EN_TX_WU), + TSM_REG_VALUE(FREQ_TARG_LD_EN_RX_WD, FREQ_TARG_LD_EN_RX_WU, FREQ_TARG_LD_EN_TX_WD, FREQ_TARG_LD_EN_TX_WU), + TSM_REG_VALUE(SAR_ADC_TRIG_EN_RX_WD, SAR_ADC_TRIG_EN_RX_WU, SAR_ADC_TRIG_EN_TX_WD, SAR_ADC_TRIG_EN_TX_WU), + TSM_REG_VALUE(TSM_SPARE0_EN_RX_WD, TSM_SPARE0_EN_RX_WU, TSM_SPARE0_EN_TX_WD, TSM_SPARE0_EN_TX_WU), + TSM_REG_VALUE(TSM_SPARE1_EN_RX_WD, TSM_SPARE1_EN_RX_WU, TSM_SPARE1_EN_TX_WD, TSM_SPARE1_EN_TX_WU), + TSM_REG_VALUE(TSM_SPARE2_EN_RX_WD, TSM_SPARE2_EN_RX_WU, TSM_SPARE2_EN_TX_WD, TSM_SPARE2_EN_TX_WU), + TSM_REG_VALUE(TSM_SPARE03_EN_RX_WD, TSM_SPARE03_EN_RX_WU, TSM_SPARE03_EN_TX_WD, TSM_SPARE03_EN_TX_WU), + TSM_REG_VALUE(GPIO0_TRIG_EN_RX_WD, GPIO0_TRIG_EN_RX_WU, GPIO0_TRIG_EN_TX_WD, GPIO0_TRIG_EN_TX_WU), + TSM_REG_VALUE(GPIO1_TRIG_EN_RX_WD, GPIO1_TRIG_EN_RX_WU, GPIO1_TRIG_EN_TX_WD, GPIO1_TRIG_EN_TX_WU), + TSM_REG_VALUE(GPIO2_TRIG_EN_RX_WD, GPIO2_TRIG_EN_RX_WU, GPIO2_TRIG_EN_TX_WD, GPIO2_TRIG_EN_TX_WU), + TSM_REG_VALUE(GPIO3_TRIG_EN_RX_WD, GPIO3_TRIG_EN_RX_WU, GPIO3_TRIG_EN_TX_WD, GPIO3_TRIG_EN_TX_WU), +}; + +/*! ********************************************************************************* +************************************************************************************* +* Public functions +************************************************************************************* +********************************************************************************** */ + +/* Frequency remap initialization performs any required init for both + * the LL and TSM registers to implement proper time sequences. + */ +void tsm_ll_timing_init(PHY_RADIO_T mode) +{ + uint8_t i; +#if USE_RAM_TESTING + /* Test only code which places the timing values in a RAM array */ + static uint32_t tsm_values_test[NUM_TSM_TIMING_REGS]; + uint32_t * tsm_reg_ptr = &tsm_values_test[0]; +#else + /* Normal operational code */ + uint32_t * tsm_reg_ptr = (uint32_t *)&XCVR_TSM_TIMING00; +#endif + + /* Setup TSM timing registers with time sequences for BLE unconditionally */ + /* NOTE: This code depends on the array of init values being in the proper order! */ + for (i=0;iEND_OF_TX_WU_BLE),TX_Warmup_is_too_long_for_specified_TX_ON_Delay); +STATIC_ASSERT((RX_ON_DELAY>(END_OF_RX_WU_BLE+1)),RX_Warmup_is_too_long_for_specified_RX_ON_Delay); +#define TX_SYNTH_DELAY (TX_ON_DELAY-(END_OF_TX_WU_BLE-0)) /* END_OF_TX_WU_BLE from tsm_timing_ble.h */ +#define RX_SYNTH_DELAY (RX_ON_DELAY-(END_OF_RX_WU_BLE-1)) /* END_OF_RX_WU_BLE from tsm_timing_ble.h */ +#define TX_RX_ON_DELAY_VALUE ((TX_ON_DELAY<PLL_LOCKED_TIME_RX) ? DCOC_COMPLETED_TIME_RX : PLL_LOCKED_TIME_RX) +#define RX_INIT_RX_WU (RX_DIG_EN_RX_WU) +#define END_OF_RX_WU_BLE (RX_DIG_EN_RX_WU+RX_INIT_TIME+RX_INIT_SETTLE_TIME) /* End of RX WU */ + +/* Unused signals */ +#define PLL_VCO_BUF_TX_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define PLL_PA_BUF_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define PLL_TX_LDV_RIPPLE_MUX_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TX_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TX_DIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define ZBDEM_RX_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define SAR_ADC_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TSM_SPARE0_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TSM_SPARE1_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TSM_SPARE2_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TSM_SPARE03_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define GPIO0_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define GPIO1_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define GPIO2_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define GPIO3_TRIG_EN_RX_WU (TSM_SIG_DIS) /* Not used in RX scenarios */ + +/* RX warmdown sequence timings */ +#define PLL_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_VCO_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_QGEN_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_TCA_TX_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define ADC_REG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_VCO_AUTOTUNE_RX_WD (PLL_LOCK_START_TIME_RX) /* Turn off AUTOTUNE at the start of the PLL locking sequence */ +#define PLL_VCO_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define QGEN25_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_VCO_BUF_RX_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_DIG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_RX_LDV_RIPPLE_MUX_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_FILTER_CHARGE_EN_RX_WD (PLL_FILTER_CHARGE_EN_RX_WU+10) /* 10us pulse */ +#define PLL_PHDET_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_LDV_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define SIGMA_DELTA_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_REF_CLK_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define FREQ_TARG_LD_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define PLL_CYCLE_SLIP_LD_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define ADC_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define ADC_DAC_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define ADC_CLK_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define ADC_I_Q_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define ADC_RST_EN_RX_WD (ADC_RST_EN_RX_WU+ADC_RST_TIME) /* Pulse length = ADC_RST_TIME */ +#define BBF_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define TCA_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define DCOC_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define DCOC_INIT_EN_RX_WD (DCOC_INIT_EN_RX_WU+DCOC_INIT_TIME) /* Pulse length = DCOC_INIT_TIME */ +#define RX_DIG_EN_RX_WD (END_OF_RX_WU_BLE+1) /* Common end of warmdown */ +#define RX_INIT_RX_WD (RX_INIT_RX_WU+RX_INIT_TIME) /* Pulse length = RX_INIT_TIME */ + +#if (DCOC_ADJUST_WORKAROUND) +#define GPIO0_TRIG_EN_RX_WD (DCOC_COMPLETED_TIME_RX) /* Release this signal at end of allocated time */ +#else +#define GPIO0_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#endif + +/* Unused signals */ +#define PLL_VCO_BUF_TX_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define PLL_PA_BUF_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define PLL_TX_LDV_RIPPLE_MUX_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TX_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TX_DIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define ZBDEM_RX_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define SAR_ADC_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TSM_SPARE0_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TSM_SPARE1_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TSM_SPARE2_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define TSM_SPARE03_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define GPIO1_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define GPIO2_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ +#define GPIO3_TRIG_EN_RX_WD (TSM_SIG_DIS) /* Not used in RX scenarios */ + +#define END_OF_RX_WD_BLE (END_OF_RX_WU_BLE+1) /* RX warmdown has no delay */ + +#define END_OF_SEQ_VALUE ( (END_OF_RX_WD_BLE<CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxPattern_c) | + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK; + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskNoModTx +***********************************************************************************/ +void XcvrFskNoModTx(void) +{ + XcvrFskIdle(); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxNoMod_Carrier_c); + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskIdle +***********************************************************************************/ +void XcvrFskIdle(void) +{ + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | + XCVR_TX_DIG_CTRL_LFSR_EN_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK); + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; + XCVR_MISC->DTEST_CTRL &= ~XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskTxRand +***********************************************************************************/ +void XcvrFskTxRand(void) +{ + XcvrFskIdle(); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | + XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK); + XCVR_TX_DIG->CTRL |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(gDftTxRandom_c) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(0) | /* length 9 */ + XCVR_TX_DIG_CTRL_LFSR_EN_MASK; + XCVR_MISC->DTEST_CTRL |= XCVR_CTRL_DTEST_CTRL_DTEST_EN_MASK; + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +/*! ********************************************************************************* +* XcvrFskLoadPattern +***********************************************************************************/ +void XcvrFskLoadPattern(uint32_t u32Pattern) +{ + XCVR_TX_DIG->DFT_PATTERN = u32Pattern; +} + +/*! ********************************************************************************* +* XcvrFskGetInstantRssi +***********************************************************************************/ +uint8_t XcvrFskGetInstantRssi(void) +{ + uint8_t u8Rssi; + uint32_t t1,t2,t3; + t1 = XCVR_RX_DIG->RX_DIG_CTRL; + t2 = XCVR_RX_DIG->RSSI_CTRL_0; + t3 = XCVR_PHY->CFG1; + XCVR_RX_DIG->RX_DIG_CTRL = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | /* 1=OSR8, 2=OSR16, 4=OSR32 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0) | /* Source Rate 0 is default */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(22) | /* Dec filt gain for SRC rate == 0 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1) ; + + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(0x5); + + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(0x3); + + uint32_t temp = XCVR_PHY->CFG1; + temp &= ~XCVR_PHY_CFG1_CTS_THRESH_MASK; + temp |= XCVR_PHY_CFG1_CTS_THRESH(0xFF); + XCVR_PHY->CFG1 = temp; + + XCVR_ForceRxWu(); + for(uint32_t i = 0; i < 10000; i++) + { + __asm("nop"); + } + u8Rssi = (uint8_t)((XCVR_RX_DIG->RSSI_CTRL_1 & + XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_MASK) >> + XCVR_RX_DIG_RSSI_CTRL_1_RSSI_OUT_SHIFT); + XCVR_ForceRxWd(); + + XCVR_RX_DIG->RX_DIG_CTRL = t1; + XCVR_RX_DIG->RSSI_CTRL_0 = t2; + XCVR_PHY->CFG1 = t3; + return u8Rssi; +} + +/*! ********************************************************************************* +* XcvrFskSetTxPower +***********************************************************************************/ +void XcvrFskSetTxPower(uint8_t u8TxPow) +{ + return; +} + +/*! ********************************************************************************* +* XcvrFskSetTxChannel +***********************************************************************************/ +void XcvrFskSetTxChannel(uint8_t u8TxChan) +{ + return; +} + +/*! ********************************************************************************* +* XcvrFskRestoreTXControl +* After calling this function user should switch to +* previous protocol and set the protocol channel to default +***********************************************************************************/ +void XcvrFskRestoreTXControl(void) +{ + return; +} + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h new file mode 100644 index 000000000..a3be92c53 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/XCVR_Test/xcvr_test_fsk.h @@ -0,0 +1,157 @@ +/*! +* Copyright 2016-2017 NXP +* +* \file +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef __XCVR_TEST_FSK_H__ +#define __XCVR_TEST_FSK_H__ + +/*! ********************************************************************************* +************************************************************************************* +* Public type definitions +************************************************************************************* +********************************************************************************** */ + +/*! ********************************************************************************* +************************************************************************************* +* Public prototypes +************************************************************************************* +********************************************************************************** */ +/*! ********************************************************************************* +* \brief This function returns instant RSSI value and returns it as unsigned byte. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Initialization of the xcvr is necessary prior to calling this function +* +***********************************************************************************/ +extern uint8_t XcvrFskGetInstantRssi(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous modulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Initialization of the xcvr and calling XcvrFskLoadPattern are necessary +* prior to calling this function +* +***********************************************************************************/ +extern void XcvrFskModTx(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous unmodulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskNoModTx(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into idle. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskIdle(void); + +/*! ********************************************************************************* +* \brief This function sets the transceiver into continuous modulated transmission. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details The modulation used is a pseudo-random pattern generated using a LFSR. +* +***********************************************************************************/ +extern void XcvrFskTxRand(void); + +/*! ********************************************************************************* +* \brief This function loads a 32 bit value into the pattern register used by XcvrFskModTx. +* +* \param[in] u32Pattern The pattern to be loaded. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskLoadPattern(uint32_t u32Pattern); + +/*! ********************************************************************************* +* \brief This function gives tx power control to xcvr and sets the power to u8TxPow. +* +* \param[in] u8TxPow Values should be between 0x00 and 0x0F. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskSetTxPower(uint8_t u8TxPow); + +/*! ********************************************************************************* +* \brief This function gives tx channel control to xcvr and sets the channel to u8TxChan. +* +* \param[in] u8TxChan Values should be between 0 and 39. +* +* \ingroup TestFunctions +* +* \details +* +***********************************************************************************/ +extern void XcvrFskSetTxChannel(uint8_t u8TxChan); + +/*! ********************************************************************************* +* \brief This function gives tx channel control and power to the upper layer. +* +* \param[in] None. +* +* \ingroup TestFunctions +* +* \details Call this function only if XcvrFskSetTxChannel or XcvrFskSetTxPower were called +* previously. +* +***********************************************************************************/ +extern void XcvrFskRestoreTXControl(void); + +#endif + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c new file mode 100644 index 000000000..319a104a0 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ant_config.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t ant_mode_config = +{ + .radio_mode = ANT_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK +#if !RADIO_IS_GEN_2P1 + | SIM_SCGC5_ANT_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(3) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = RW0PS(0, 0x1B) | + RW0PS(1, 0x1CU) | + RW0PS(2, 0x1CU) | + RW0PS(3, 0x1CU) | + RW0PS(4, 0x1DU) | + RW0PS(5, 0x1DU) | + RW0PS(6, 0x1EU & 0x3U), /* Phase info #6 overlaps two initialization words - only need two lowest bits*/ + .phy_pre_ref1_init = (0x1E) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift */ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1EU) | + RW1PS(11, 0x1DU) | + RW1PS(12, 0x1DU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1D) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift */ + RW2PS(13, 0x1CU) | + RW2PS(14, 0x1CU) | + RW2PS(15, 0x1CU), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xF8) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config = +{ + .radio_mode = ANT_MODE, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, + + /* ANT 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c new file mode 100644 index 000000000..054b0ccfe --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_ble_config.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t ble_mode_config = +{ + .radio_mode = BLE_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_BTLL_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(0) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = RW0PS(0, 0x19) | + RW0PS(1, 0x19U) | + RW0PS(2, 0x1AU) | + RW0PS(3, 0x1BU) | + RW0PS(4, 0x1CU) | + RW0PS(5, 0x1CU) | + RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ + .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1DU) | + RW1PS(11, 0x1CU) | + RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ + RW2PS(13, 0x1BU) | + RW2PS(14, 0x1AU) | + RW2PS(15, 0x19U), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(220) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) /* Per SMB */ +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config = +{ + .radio_mode = BLE_MODE, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* BLE 26MHz Channel Filter */ + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, + + /* BLE 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c new file mode 100644 index 000000000..4277d3a1f --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_common_config.c @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_common_config_t xcvr_common_config = +{ + /* XCVR_ANA configs */ + .ana_sy_ctrl1.mask = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL_MASK, + .ana_sy_ctrl1.init = XCVR_ANALOG_SY_CTRL_1_SY_LPF_FILT_CTRL(3), /* PLL Analog Loop Filter */ + +#define hpm_vcm_tx 0 +#define hpm_vcm_cal 1 +#define hpm_fdb_res_tx 0 +#define hpm_fdb_res_cal 1 +#define modulation_word_manual 0 +#define mod_disable 0 +#define hpm_mod_manual 0 +#define hpm_mod_disable 0 +#define hpm_sdm_out_manual 0 +#define hpm_sdm_out_disable 0 +#define channel_num 0 +#define boc 0 +#define bmr 1 +#define zoc 0 +#define ctune_ldf_lev 8 +#define ftf_rx_thrsh 33 +#define ftw_rx 0 +#define ftf_tx_thrsh 6 +#define ftw_tx 0 +#define freq_count_go 0 +#define freq_count_time 0 +#define hpm_sdm_in_manual 0 +#define hpm_sdm_out_invert 0 +#define hpm_sdm_in_disable 0 +#define hpm_lfsr_size 4 +#define hpm_dth_scl 0 +#define hpm_dth_en 1 +#define hpm_integer_scale 0 +#define hpm_integer_invert 0 +#define hpm_cal_invert 1 +#define hpm_mod_in_invert 1 +#define hpm_cal_not_bumped 0 +#define hpm_cal_count_scale 0 +#define hp_cal_disable 0 +#define hpm_cal_factor_manual 0 +#define hpm_cal_array_size 1 +#define hpm_cal_time 0 +#define hpm_sdm_denom 256 +#define hpm_count_adjust 0 +#define pll_ld_manual 0 +#define pll_ld_disable 0 +#define lpm_sdm_inv 0 +#define lpm_disable 0 +#define lpm_dth_scl 8 +#define lpm_d_ctrl 1 +#define lpm_d_ovrd 1 +#define lpm_scale 8 +#define lpm_sdm_use_neg 0 +#define hpm_array_bias 0 +#define lpm_intg 38 +#define sdm_map_disable 0 +#define lpm_sdm_delay 4 +#define hpm_sdm_delay 0 +#define hpm_integer_delay 0 +#define ctune_target_manual 0 +#define ctune_target_disable 0 +#define ctune_adjust 0 +#define ctune_manual 0 +#define ctune_disable 0 + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_hpm_bump = XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_CAL(hpm_fdb_res_cal) | + XCVR_PLL_DIG_HPM_BUMP_HPM_FDB_RES_TX(hpm_fdb_res_tx) | + XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_CAL(hpm_vcm_cal) | + XCVR_PLL_DIG_HPM_BUMP_HPM_VCM_TX(hpm_vcm_tx), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_mod_ctrl = XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_DISABLE(hpm_mod_disable) | + XCVR_PLL_DIG_MOD_CTRL_HPM_MOD_MANUAL(hpm_mod_manual) | + XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_DISABLE(hpm_sdm_out_disable) | + XCVR_PLL_DIG_MOD_CTRL_HPM_SDM_OUT_MANUAL(hpm_sdm_out_manual) | + XCVR_PLL_DIG_MOD_CTRL_MOD_DISABLE(mod_disable) | + XCVR_PLL_DIG_MOD_CTRL_MODULATION_WORD_MANUAL(modulation_word_manual), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_chan_map = XCVR_PLL_DIG_CHAN_MAP_BMR(bmr) | + XCVR_PLL_DIG_CHAN_MAP_BOC(boc) | + XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel_num) +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC(zoc) +#endif /* !RADIO_IS_GEN_2P1 */ + , + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_lock_detect = XCVR_PLL_DIG_LOCK_DETECT_CTUNE_LDF_LEV(ctune_ldf_lev) | + XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_GO(freq_count_go) | + XCVR_PLL_DIG_LOCK_DETECT_FREQ_COUNT_TIME(freq_count_time) | + XCVR_PLL_DIG_LOCK_DETECT_FTF_RX_THRSH(ftf_rx_thrsh) | + XCVR_PLL_DIG_LOCK_DETECT_FTF_TX_THRSH(ftf_tx_thrsh) | + XCVR_PLL_DIG_LOCK_DETECT_FTW_RX(ftw_rx) | + XCVR_PLL_DIG_LOCK_DETECT_FTW_TX(ftw_tx), + +/*-------------------------------------------------------------------------------------------------*/ + + .pll_hpm_ctrl = XCVR_PLL_DIG_HPM_CTRL_HPM_CAL_INVERT(hpm_cal_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_EN(hpm_dth_en) | + XCVR_PLL_DIG_HPM_CTRL_HPM_DTH_SCL(hpm_dth_scl) | + XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_INVERT(hpm_integer_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_INTEGER_SCALE(hpm_integer_scale) | + XCVR_PLL_DIG_HPM_CTRL_HPM_LFSR_SIZE(hpm_lfsr_size) | + XCVR_PLL_DIG_HPM_CTRL_HPM_MOD_IN_INVERT(hpm_mod_in_invert) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_DISABLE(hpm_sdm_in_disable) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_IN_MANUAL(hpm_sdm_in_manual) | + XCVR_PLL_DIG_HPM_CTRL_HPM_SDM_OUT_INVERT(hpm_sdm_out_invert), +/*-------------------------------------------------------------------------------------------------*/ +#if !RADIO_IS_GEN_2P1 + .pll_hpmcal_ctrl = XCVR_PLL_DIG_HPMCAL_CTRL_HP_CAL_DISABLE(hp_cal_disable) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_ARRAY_SIZE(hpm_cal_array_size) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_COUNT_SCALE(hpm_cal_count_scale) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_FACTOR_MANUAL(hpm_cal_factor_manual) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_NOT_BUMPED(hpm_cal_not_bumped) | + XCVR_PLL_DIG_HPMCAL_CTRL_HPM_CAL_TIME(hpm_cal_time), +#endif /* !RADIO_IS_GEN_2P1 */ +/*-------------------------------------------------------------------------------------------------*/ + .pll_hpm_sdm_res = XCVR_PLL_DIG_HPM_SDM_RES_HPM_COUNT_ADJUST(hpm_count_adjust) | + XCVR_PLL_DIG_HPM_SDM_RES_HPM_DENOM(hpm_sdm_denom), +/*-------------------------------------------------------------------------------------------------*/ + .pll_lpm_ctrl = XCVR_PLL_DIG_LPM_CTRL_LPM_D_CTRL(lpm_d_ctrl) | + XCVR_PLL_DIG_LPM_CTRL_LPM_D_OVRD(lpm_d_ovrd) | + XCVR_PLL_DIG_LPM_CTRL_LPM_DISABLE(lpm_disable) | + XCVR_PLL_DIG_LPM_CTRL_LPM_DTH_SCL(lpm_dth_scl) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SCALE(lpm_scale) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_INV(lpm_sdm_inv) | + XCVR_PLL_DIG_LPM_CTRL_LPM_SDM_USE_NEG(lpm_sdm_use_neg) | + XCVR_PLL_DIG_LPM_CTRL_PLL_LD_DISABLE(pll_ld_disable) | + XCVR_PLL_DIG_LPM_CTRL_PLL_LD_MANUAL(pll_ld_manual), +/*-------------------------------------------------------------------------------------------------*/ + .pll_lpm_sdm_ctrl1 = XCVR_PLL_DIG_LPM_SDM_CTRL1_HPM_ARRAY_BIAS(hpm_array_bias) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(lpm_intg) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE(sdm_map_disable), +/*-------------------------------------------------------------------------------------------------*/ + .pll_delay_match = XCVR_PLL_DIG_DELAY_MATCH_HPM_INTEGER_DELAY(hpm_integer_delay) | + XCVR_PLL_DIG_DELAY_MATCH_HPM_SDM_DELAY(hpm_sdm_delay) | + XCVR_PLL_DIG_DELAY_MATCH_LPM_SDM_DELAY(lpm_sdm_delay), +/*-------------------------------------------------------------------------------------------------*/ + .pll_ctune_ctrl = XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_ADJUST(ctune_adjust) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_DISABLE(ctune_disable) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_MANUAL(ctune_manual) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_DISABLE(ctune_target_disable) | + XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(ctune_target_manual), +/*-------------------------------------------------------------------------------------------------*/ + + /* XCVR_RX_DIG configs */ + /* NOTE: Clock specific settings are embedded in the mode dependent configs */ + .rx_dig_ctrl_init = XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_NEGEDGE(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_CH_FILT_BYPASS(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_RAW_EN(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_ADC_POL(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_NORM_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_RSSI_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_IQ_SWAP(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_HZD_CORR_DIS(1), + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_SLOW_AGC_SRC(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_FREEZE_PRE_OR_AA(0) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_EN(1) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_SRC(0) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_BBA_STEP_SZ(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_LNA_STEP_SZ(2) | + XCVR_RX_DIG_AGC_CTRL_0_AGC_UP_RSSI_THRESH(0xe7), + + .agc_ctrl_3_init = XCVR_RX_DIG_AGC_CTRL_3_AGC_UNFREEZE_TIME(21) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_PDET_LO_DLY(2) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_RSSI_DELT_H2S(20) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_H2S_STEP_SZ(6) | + XCVR_RX_DIG_AGC_CTRL_3_AGC_UP_STEP_SZ(2), + + /* DCOC configs */ + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(16) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ +#if (RADIO_IS_GEN_2P1) + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | +#endif /* (RADIO_IS_GEN_2P1) */ + XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | + XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_DURATION(20) | /* Only the duration changes between 26MHz and 32MHz ref osc settings */ +#if (RADIO_IS_GEN_2P1) + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CAL_CHECK_EN(0) | +#endif /* (RADIO_IS_GEN_2P1) */ + XCVR_RX_DIG_DCOC_CTRL_0_TRACK_FROM_ZERO(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1) | + XCVR_RX_DIG_DCOC_CTRL_0_TZA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_BBA_CORR_POL(0) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1), + + .dcoc_ctrl_1_init = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_MIN_AGC_IDX(26), + + .dc_resid_ctrl_init = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ITER_FREEZE(4) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_ALPHA(1) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_EXT_DC_EN(1) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_MIN_AGC_IDX(26), + + .dcoc_cal_gain_init = XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN1(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN1(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN2(1) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN2(2) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_BBA_CAL_GAIN3(3) | + XCVR_RX_DIG_DCOC_CAL_GAIN_DCOC_LNA_CAL_GAIN3(1) , + + .dcoc_cal_rcp_init = XCVR_RX_DIG_DCOC_CAL_RCP_ALPHA_CALC_RECIP(1) | + XCVR_RX_DIG_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(711), + + .lna_gain_val_3_0 = XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_0(0x1DU) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_1(0x32U) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_2(0x09U) | + XCVR_RX_DIG_LNA_GAIN_VAL_3_0_LNA_GAIN_VAL_3(0x38U), + + .lna_gain_val_7_4 = XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_4(0x4FU) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_5(0x5BU) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_6(0x72U) | + XCVR_RX_DIG_LNA_GAIN_VAL_7_4_LNA_GAIN_VAL_7(0x8AU), + .lna_gain_val_8 = XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_8(0xA0U) | + XCVR_RX_DIG_LNA_GAIN_VAL_8_LNA_GAIN_VAL_9(0xB6U), + + .bba_res_tune_val_7_0 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_0(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_1(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_2(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_3(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_4(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_5(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_6(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_7_0_BBA_RES_TUNE_VAL_7(0xF), + .bba_res_tune_val_10_8 = XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_8(0x0) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_9(0x1) | + XCVR_RX_DIG_BBA_RES_TUNE_VAL_10_8_BBA_RES_TUNE_VAL_10(0x2), + + .lna_gain_lin_val_2_0_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_0(0) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_1(0) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_2_0_LNA_GAIN_LIN_VAL_2(1), + + .lna_gain_lin_val_5_3_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_3(3) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_4(5) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_5_3_LNA_GAIN_LIN_VAL_5(7), + + .lna_gain_lin_val_8_6_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_6(14) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_7(27) | + XCVR_RX_DIG_LNA_GAIN_LIN_VAL_8_6_LNA_GAIN_LIN_VAL_8(50), + + .lna_gain_lin_val_9_init = XCVR_RX_DIG_LNA_GAIN_LIN_VAL_9_LNA_GAIN_LIN_VAL_9(91), + + .bba_res_tune_lin_val_3_0_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_0(8) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_1(11) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_2(16) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_3_0_BBA_RES_TUNE_LIN_VAL_3(22), + + .bba_res_tune_lin_val_7_4_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_4(31) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_5(44) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_6(62) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_7_4_BBA_RES_TUNE_LIN_VAL_7(42), /* Has 2 fractional bits unlike other BBA_RES_TUNE_LIN_VALs */ + + .bba_res_tune_lin_val_10_8_init = XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_8(128) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_9(188) | + XCVR_RX_DIG_BBA_RES_TUNE_LIN_VAL_10_8_BBA_RES_TUNE_LIN_VAL_10(288), + + .dcoc_bba_step_init = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(939) | + XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(279), + + .dcoc_tza_step_00_init = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(77) | + XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(3404), + .dcoc_tza_step_01_init = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(108) | + XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(2439), + .dcoc_tza_step_02_init = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(155) | + XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(1691), + .dcoc_tza_step_03_init = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(220) | + XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(1192), + .dcoc_tza_step_04_init = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(314) | + XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(835), + .dcoc_tza_step_05_init = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(436) | + XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(601), + .dcoc_tza_step_06_init = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(614) | + XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(427), + .dcoc_tza_step_07_init = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(845) | + XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(310), + .dcoc_tza_step_08_init = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(1256) | + XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(209), + .dcoc_tza_step_09_init = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(1805) | + XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(145), + .dcoc_tza_step_10_init = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(2653) | + XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(99), +#if (RADIO_IS_GEN_2P1) + .dcoc_cal_fail_th_init = XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_BETA_F_TH(20) | + XCVR_RX_DIG_DCOC_CAL_FAIL_TH_DCOC_CAL_ALPHA_F_TH(10), + .dcoc_cal_pass_th_init = XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_BETA_P_TH(16) | + XCVR_RX_DIG_DCOC_CAL_PASS_TH_DCOC_CAL_ALPHA_P_TH(2), +#endif /* (RADIO_IS_GEN_2P1) */ + /* AGC Configs */ + .agc_gain_tbl_03_00_init = XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_00(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_00(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_01(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_01(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_02(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_02(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_LNA_GAIN_03(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_03_00_BBA_GAIN_03(2), + + .agc_gain_tbl_07_04_init = XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_04(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_04(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_05(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_05(0) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_06(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_06(1) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_LNA_GAIN_07(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_07_04_BBA_GAIN_07(2), + + .agc_gain_tbl_11_08_init = XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_08(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_08(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_09(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_09(2) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_10(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_10(3) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_LNA_GAIN_11(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_11_08_BBA_GAIN_11(4), + + .agc_gain_tbl_15_12_init = XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_12(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_12(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_13(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_13(5) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_14(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_14(4) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_LNA_GAIN_15(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_15_12_BBA_GAIN_15(5), + + .agc_gain_tbl_19_16_init = XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_16(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_16(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_17(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_17(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_18(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_18(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_LNA_GAIN_19(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_19_16_BBA_GAIN_19(7), + + .agc_gain_tbl_23_20_init = XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_20(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_20(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_21(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_21(7) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_22(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_22(6) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_LNA_GAIN_23(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_23_20_BBA_GAIN_23(7), + + .agc_gain_tbl_26_24_init = XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_24(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_24(8) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_25(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_25(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_LNA_GAIN_26(9) | + XCVR_RX_DIG_AGC_GAIN_TBL_26_24_BBA_GAIN_26(10), + + .rssi_ctrl_0_init = XCVR_RX_DIG_RSSI_CTRL_0_RSSI_USE_VALS(1) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_SRC(0) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_EN(1) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_AVG(1) | +#else + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_N_WINDOW_NB(1) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_HOLD_DELAY(4) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_WEIGHT(3) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_VLD_SETTLE(3) | + XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(0xE8) , + + .cca_ed_lqi_ctrl_0_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CORR_THRESH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_CORR_CNTR_THRESH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_LQI_CNTR(0x1A) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_0_SNR_ADJ(0), + + .cca_ed_lqi_ctrl_1_init = XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_DELAY(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_RSSI_NOISE_AVG_FACTOR(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_WEIGHT(0x4) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_RSSI_SENS(0x7) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_DIS(0) | +#if !RADIO_IS_GEN_2P1 + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SEL_SNR_MODE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MEAS_TRANS_TO_IDLE(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_CCA1_ED_EN_DIS(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_MEAS_COMPLETE(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_MAN_AA_MATCH(0) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_SNR_LQI_WEIGHT(0x5) | + XCVR_RX_DIG_CCA_ED_LQI_CTRL_1_LQI_BIAS(0x2), + + /* XCVR_TSM configs */ + .tsm_ctrl = XCVR_TSM_CTRL_PA_RAMP_SEL(PA_RAMP_SEL) | + XCVR_TSM_CTRL_DATA_PADDING_EN(DATA_PADDING_EN) | + XCVR_TSM_CTRL_TSM_IRQ0_EN(0) | + XCVR_TSM_CTRL_TSM_IRQ1_EN(0) | + XCVR_TSM_CTRL_RAMP_DN_DELAY(0x4) | + XCVR_TSM_CTRL_TX_ABORT_DIS(0) | + XCVR_TSM_CTRL_RX_ABORT_DIS(0) | + XCVR_TSM_CTRL_ABORT_ON_CTUNE(0) | + XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(0) | + XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(0) | + XCVR_TSM_CTRL_BKPT(0xFF) , + + .tsm_ovrd2_init = XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(0) | XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK, + .end_of_seq_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(END_OF_RX_WU_26MHZ) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), + .end_of_seq_init_32mhz = B3(END_OF_RX_WD) | B2(END_OF_RX_WU) | B1(END_OF_TX_WD) | B0(END_OF_TX_WU), + +#if !RADIO_IS_GEN_2P1 + .lpps_ctrl_init = B3(102) | B2(40) | B1(0) | B0(0), +#endif /* !RADIO_IS_GEN_2P1 */ + + .tsm_fast_ctrl2_init_26mhz = B3(102 + ADD_FOR_26MHZ) | B2(40 + ADD_FOR_26MHZ) | B1(66) | B0(8), + .tsm_fast_ctrl2_init_32mhz = B3(102) | B2(40) | B1(66) | B0(8), + + .pa_ramp_tbl_0_init = XCVR_TSM_PA_RAMP_TBL0_PA_RAMP0(PA_RAMP_0) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP1(PA_RAMP_1) | + XCVR_TSM_PA_RAMP_TBL0_PA_RAMP2(PA_RAMP_2) | XCVR_TSM_PA_RAMP_TBL0_PA_RAMP3(PA_RAMP_3), + .pa_ramp_tbl_1_init = XCVR_TSM_PA_RAMP_TBL1_PA_RAMP4(PA_RAMP_4) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP5(PA_RAMP_5) | + XCVR_TSM_PA_RAMP_TBL1_PA_RAMP6(PA_RAMP_6) | XCVR_TSM_PA_RAMP_TBL1_PA_RAMP7(PA_RAMP_7), + + .recycle_count_init_26mhz = B3(0) | B2(0x1C + ADD_FOR_26MHZ) | B1(0x06) | B0(0x66 + ADD_FOR_26MHZ), + .recycle_count_init_26mhz = B3(0) | B2(0x1C) | B1(0x06) | B0(0x66), + + .tsm_timing_00_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_hf_en */ + .tsm_timing_01_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_adcdac_en */ + .tsm_timing_02_init = B3(END_OF_RX_WD) | B2(0x00) | B1(0xFF) | B0(0xFF), /* bb_ldo_bba_en */ + .tsm_timing_03_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_pd_en */ + .tsm_timing_04_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_fdbk_en */ + .tsm_timing_05_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vcolo_en */ + .tsm_timing_06_init = B3(END_OF_RX_WD) | B2(0x00) | B1(END_OF_TX_WD) | B0(0x00), /* bb_ldo_vtref_en */ + .tsm_timing_07_init = B3(0x05) | B2(0x00) | B1(0x05) | B0(0x00), /* bb_ldo_fdbk_bleed_en */ + .tsm_timing_08_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_bleed_en */ + .tsm_timing_09_init = B3(0x03) | B2(0x00) | B1(0x03) | B0(0x00), /* bb_ldo_vcolo_fastcharge_en */ + + .tsm_timing_10_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_pll_ref_clk_en */ + .tsm_timing_11_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* bb_xtal_dac_ref_clk_en */ + .tsm_timing_12_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_vco_ref_clk_en */ + .tsm_timing_13_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_vco_autotune_en */ + .tsm_timing_14_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x31+ADD_FOR_26MHZ) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), /* sy_pd_cycle_slip_ld_ft_en */ + .tsm_timing_14_init_32mhz = B3(END_OF_RX_WD) | B2(0x31 + AUX_PLL_DELAY) | B1(END_OF_TX_WU + PD_CYCLE_SLIP_TX_LO_ADJ) | B0(0x63 + PD_CYCLE_SLIP_TX_HI_ADJ), + .tsm_timing_15_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_vco_en */ + .tsm_timing_16_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1C + ADD_FOR_26MHZ) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_buf_en */ + .tsm_timing_16_init_32mhz = B3(END_OF_RX_WD) | B2(0x1C + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_17_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x55), /* sy_lo_tx_buf_en */ + .tsm_timing_18_init = B3(END_OF_RX_WD) | B2(0x05 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x05), /* sy_divn_en */ + .tsm_timing_19_init = B3(0x18+AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0x4C) | B0(0x03), /* sy_pd_filter_charge_en */ + + .tsm_timing_20_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x03), /* sy_pd_en */ + .tsm_timing_21_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x04), /* sy_lo_divn_en */ + .tsm_timing_22_init = B3(END_OF_RX_WD) | B2(0x04 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* sy_lo_rx_en */ + .tsm_timing_23_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x04), /*sy_lo_tx_en */ + .tsm_timing_24_init = B3(0x18) | B2(0x00) | B1(0x4C) | B0(0x00), /* sy_divn_cal_en */ + .tsm_timing_25_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_lna_mixer_en */ + .tsm_timing_25_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_26_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x58), /* tx_pa_en */ + .tsm_timing_27_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_i_q_en */ + .tsm_timing_27_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_28_init_26mhz = B3(0x21 + ADD_FOR_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_adc_reset_en */ + .tsm_timing_28_init_32mhz = B3(0x21 + AUX_PLL_DELAY) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_29_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1E + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_i_q_en */ + .tsm_timing_29_init_32mhz = B3(END_OF_RX_WD) | B2(0x1E + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + + .tsm_timing_30_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_pdet_en */ + .tsm_timing_30_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_31_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1F + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_bba_tza_dcoc_en */ + .tsm_timing_31_init_32mhz = B3(END_OF_RX_WD) | B2(0x1F + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_32_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x1D + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_i_q_en */ + .tsm_timing_32_init_32mhz = B3(END_OF_RX_WD) | B2(0x1D + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_33_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_tza_pdet_en */ + .tsm_timing_33_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_34_init = B3(END_OF_RX_WD) | B2(0x07 + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x07), /* pll_dig_en */ + .tsm_timing_35_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD), /* tx_dig_en - Byte 0 comes from mode specific settings */ + .tsm_timing_36_init_26mhz = B3(END_OF_RX_WD) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_dig_en */ + .tsm_timing_36_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_37_init_26mhz = B3(0x67 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_init */ + .tsm_timing_37_init_32mhz = B3(0x67 + AUX_PLL_DELAY) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_38_init = B3(END_OF_RX_WD) | B2(0x0E + AUX_PLL_DELAY) | B1(END_OF_TX_WD) | B0(0x42), /* sigma_delta_en */ + .tsm_timing_39_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x66 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rx_phy_en */ + .tsm_timing_39_init_32mhz = B3(END_OF_RX_WD) | B2(0x66 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + + .tsm_timing_40_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_en */ + .tsm_timing_40_init_32mhz = B3(END_OF_RX_WD) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_41_init_26mhz = B3(0x27 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x26 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* dcoc_init */ + .tsm_timing_41_init_32mhz = B3(0x27 + AUX_PLL_DELAY) | B2(0x26 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_51_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_bias_en */ + .tsm_timing_52_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x06 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_fcal_en */ + .tsm_timing_52_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x06 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_53_init = B3(END_OF_RX_WD) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_lf_pd_en */ + .tsm_timing_54_init_26mhz = B3(0x17 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B2(0x03 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_pd_lf_filter_charge_en */ + .tsm_timing_54_init_32mhz = B3(0x17 + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_55_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_adc_buf_en */ + .tsm_timing_55_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_56_init_26mhz = B3(END_OF_RX_WD_26MHZ) | B2(0x20 + ADD_FOR_26MHZ + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /* rxtx_auxpll_dig_buf_en */ + .tsm_timing_56_init_32mhz = B3(END_OF_RX_WD) | B2(0x20 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), + .tsm_timing_57_init = B3(0x1A + AUX_PLL_DELAY) | B2(0x03 + AUX_PLL_DELAY) | B1(0xFF) | B0(0xFF), /*rxtx_rccal_en */ + .tsm_timing_58_init = B3(0xFF) | B2(0xFF) | B1(END_OF_TX_WD) | B0(0x03), /* tx_hpm_dac_en */ + +/* XCVR_TX_DIG configs */ +#define radio_dft_mode 0 +#define lfsr_length 4 +#define lfsr_en 0 +#define dft_clk_sel 4 +#define tx_dft_en 0 +#define soc_test_sel 0 +#define tx_capture_pol 0 +#define freq_word_adj 0 +#define lrm 0 +#define data_padding_pat_1 0x55 +#define data_padding_pat_0 0xAA +#define gfsk_multiply_table_manual 0 +#define gfsk_mi 1 +#define gfsk_mld 0 +#define gfsk_fld 0 +#define gfsk_mod_index_scaling 0 +#define tx_image_filter_ovrd_en 0 +#define tx_image_filter_0_ovrd 0 +#define tx_image_filter_1_ovrd 0 +#define tx_image_filter_2_ovrd 0 +#define gfsk_filter_coeff_manual2 0xC0630401 +#define gfsk_filter_coeff_manual1 0xBB29960D +#define fsk_modulation_scale_0 0x1800 +#define fsk_modulation_scale_1 0x0800 +#define dft_mod_patternval 0 +#define ctune_bist_go 0 +#define ctune_bist_thrshld 0 +#define pa_am_mod_freq 0 +#define pa_am_mod_entries 0 +#define pa_am_mod_en 0 +#define syn_bist_go 0 +#define syn_bist_all_channels 0 +#define freq_count_threshold 0 +#define hpm_inl_bist_go 0 +#define hpm_dnl_bist_go 0 +#define dft_max_ram_size 0 + + .tx_ctrl = XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(radio_dft_mode) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | + XCVR_TX_DIG_CTRL_LFSR_EN(lfsr_en) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(tx_dft_en) | + XCVR_TX_DIG_CTRL_SOC_TEST_SEL(soc_test_sel) | + XCVR_TX_DIG_CTRL_TX_CAPTURE_POL(tx_capture_pol) | + XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(freq_word_adj), +/*-------------------------------------------------------------------------------------------------*/ + .tx_data_padding = XCVR_TX_DIG_DATA_PADDING_LRM(lrm) | + XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_1(data_padding_pat_1) | + XCVR_TX_DIG_DATA_PADDING_DATA_PADDING_PAT_0(data_padding_pat_0), +/*-------------------------------------------------------------------------------------------------*/ + .tx_dft_pattern = XCVR_TX_DIG_DFT_PATTERN_DFT_MOD_PATTERN(dft_mod_patternval), +#if !RADIO_IS_GEN_2P1 +/*-------------------------------------------------------------------------------------------------*/ + .rf_dft_bist_1 = XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_GO(ctune_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_1_CTUNE_BIST_THRSHLD(ctune_bist_thrshld) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_FREQ(pa_am_mod_freq) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_ENTRIES(pa_am_mod_entries) | + XCVR_TX_DIG_RF_DFT_BIST_1_PA_AM_MOD_EN(pa_am_mod_en), +/*-------------------------------------------------------------------------------------------------*/ + .rf_dft_bist_2 = XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_GO(syn_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_SYN_BIST_ALL_CHANNELS(syn_bist_all_channels) | + XCVR_TX_DIG_RF_DFT_BIST_2_FREQ_COUNT_THRESHOLD(freq_count_threshold) | + XCVR_TX_DIG_RF_DFT_BIST_2_HPM_INL_BIST_GO(hpm_inl_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_HPM_DNL_BIST_GO(hpm_dnl_bist_go) | + XCVR_TX_DIG_RF_DFT_BIST_2_DFT_MAX_RAM_SIZE(dft_max_ram_size), +#endif /* !RADIO_IS_GEN_2P1 */ +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c new file mode 100644 index 000000000..8bb5e3637 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p3_h_0p5_config.c @@ -0,0 +1,353 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x7BCDEB39, + .phy_pre_ref1_init = 0xCEF7DEF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xda) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = (107U) << 0 | /* coeff 2/13 */ + (164U) << 7 | /* coeff 6/9 */ + (125U) << 16 | /* coef 3/12 */ + (169U) << 23, /* coeff 7/8 */ + .tx_gfsk_coeff2_26mhz = (72U) << 0 | /* coeff 0/15 */ + (90U) << 8 | /* coeff 1/14 */ + (141U) << 16 | /* coeff 4/11 */ + (155U) << 24, /* coeff 5/10 */ + .tx_gfsk_coeff1_32mhz = (70U) << 0 | /* coeff 2/13 */ + (216U) << 7 | /* coeff 6/9 */ + (105U) << 16 | /* coef 3/12 */ + (233U) << 23, /* coeff 7/8 */ + .tx_gfsk_coeff2_32mhz = (25U) << 0 | /* coeff 0/15 */ + (44U) << 8 | /* coeff 1/14 */ + (145U) << 16 | /* coeff 4/11 */ + (184U) << 24, /* coeff 5/10 */ +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0011, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0028, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0055, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0061, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0025, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0043, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005C, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0023, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0068, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001D, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x003F, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0072, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p3_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0014, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003C, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0064, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1), + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c new file mode 100644 index 000000000..55366cf74 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p32_config.c @@ -0,0 +1,341 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0xBBDE739B, + .phy_pre_ref1_init = 0xDEFBDEF7, + .phy_pre_ref2_init = 0x0000E739, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xF0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(14) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFB, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0016, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0049, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0069, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0073, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0025, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0043, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005D, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x006B, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF6, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0044, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0064, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0077, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p32, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x4) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x000B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0068, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0086, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c new file mode 100644 index 000000000..d57d0696e --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p5_config.c @@ -0,0 +1,356 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + .phy_pre_ref0_init = RW0PS(0, 0x19) | + RW0PS(1, 0x19U) | + RW0PS(2, 0x1AU) | + RW0PS(3, 0x1BU) | + RW0PS(4, 0x1CU) | + RW0PS(5, 0x1CU) | + RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ + .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ + RW1PS(7, 0x1EU) | + RW1PS(8, 0x1EU) | + RW1PS(9, 0x1EU) | + RW1PS(10, 0x1DU) | + RW1PS(11, 0x1CU) | + RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ + .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ + RW2PS(13, 0x1BU) | + RW2PS(14, 0x1AU) | + RW2PS(15, 0x19U), + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(205) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* BLE 26MHz Channel Filter */ + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, + + /* BLE 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF5, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079, + + /* 32MHz */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEF, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE7, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0019, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0080, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF1, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000A, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0027, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0046, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0061, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0071, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c new file mode 100644 index 000000000..cc680b610 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_0p7_config.c @@ -0,0 +1,341 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x37ACE2F7, + .phy_pre_ref1_init = 0xADF3BDEF, + .phy_pre_ref2_init = 0x0000BE33, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xCD) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(2) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x000C, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003D, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008F, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFDF, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE3, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_0p7, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c new file mode 100644 index 000000000..49c6dc75c --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p5_h_1p0_config.c @@ -0,0 +1,340 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0xF38B5273, + .phy_pre_ref1_init = 0x8CEF9CE6, + .phy_pre_ref2_init = 0x00009D2D, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xb0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT + TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(3) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEB, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE9, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0008, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x003A, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0090, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0007, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF0, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE1, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0034, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFD, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF3, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0021, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x0013, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFC9, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x005E, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFF4E, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x018F, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0012, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0011, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFE1, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEE, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0034, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFB7, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x003B, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x004F, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFF5B, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0xFFB5, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x018B, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config = +{ + .radio_mode = GFSK_BT_0p5_h_1p0, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x000C, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0011, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000B, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE0, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x002A, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x009E, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF9, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x000F, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0019, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x000C, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFCD, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFD7, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0017, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0075, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00BB, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c new file mode 100644 index 000000000..46f6c8508 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_gfsk_bt_0p7_h_0p5_config.c @@ -0,0 +1,353 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x79CDEB39, + .phy_pre_ref1_init = 0xCE77DEF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xb0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = (27U) << 0 | /* Coeff 2/13 */ + (276U) << 7 | /* Coeff 6/9 */ + (62U) << 16 | /* Coef 3/12 */ + (326U) << 23, /* Coeff 7/8 */ + .tx_gfsk_coeff2_26mhz = (3U) << 0 | /* Coeff 0/15 */ + (10U) << 8 | /* Coeff 1/14 */ + (121U) << 16 | /* Coeff 4/11 */ + (198U) << 24, /* Coeff 5/10 */ + .tx_gfsk_coeff1_32mhz = (1U) << 0 | /* Coeff 2/13 */ + (330U) << 7 | /* Coeff 6/9 */ + (7U) << 16 | /* Coef 3/12 */ + (510U) << 23, /* Coeff 7/8 */ + .tx_gfsk_coeff2_32mhz = (0U) << 0 | /* Coeff 0/15 */ + (0U) << 8 | /* Coeff 1/14 */ + (37U) << 16 | /* Coeff 4/11 */ + (138U) << 24, /* Coeff 5/10 */ +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF4, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005E, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEB, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFED, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0041, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0065, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x007A, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = +{ + .radio_mode = GFSK_BT_0p7_h_0p5, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, + + /* 32MHz Channel Filter */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c new file mode 100644 index 000000000..dcfc95747 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_mode_datarate_config.c @@ -0,0 +1,212 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* ========================= DATA RATE ONLY settings ===============*/ +/*! + * @brief XCVR 1Mbps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_1mbps_config = +{ + .data_rate = DR_1MBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0xF) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x20) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(0) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(10) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(21), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(12) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(26), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(3), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(3) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(33) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(6), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(40) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(7), +}; + +/*! + * @brief XCVR 500K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_500kbps_config = +{ + .data_rate = DR_500KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x10), + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(36), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(32) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), +}; + +/*! + * @brief XCVR 250K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_250kbps_config = +{ + .data_rate = DR_250KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x4) | +#if !RADIO_IS_GEN_2P1 + XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PHY_EL_CFG_EL_INTERVAL(0x8) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(4) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(16) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(34), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(20) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(42), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(0) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(13) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(16) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c new file mode 100644 index 000000000..44eb38c1f --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_msk_config.c @@ -0,0 +1,343 @@ +/* + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* MODE only configuration */ +const xcvr_mode_config_t msk_mode_config = +{ + .radio_mode = MSK, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(9) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(4) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x79CDEB38, + .phy_pre_ref1_init = 0xCE77DFF7, + .phy_pre_ref2_init = 0x0000CEB7, + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(208U) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), +#else + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +/* MODE & DATA RATE combined configuration */ +const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_1MBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + /* MSK 1MBPS channel filter @ 26MHz RF OSC */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF9, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF0, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEA, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEC, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x001B, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0042, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0066, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x007C, + + /* MSK 1MBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE9, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF7, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0082, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xa) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + /* MSK 500KBPS channel filter @ 26MHz RF OSC */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0004, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFC, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFE7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0038, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006F, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0092, + + /* MSK 500KBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0006, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0009, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF3, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE2, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0031, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0071, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x009C, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config = +{ + .radio_mode = MSK, + .data_rate = DR_250KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, + + /* MSK 250KBPS channel filter @ 32MHz RF OSC */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c new file mode 100644 index 000000000..47d6f5f05 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/cfgs_kw4x_3x_2x/fsl_xcvr_zgbe_config.c @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_xcvr.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +const xcvr_mode_config_t zgbe_mode_config = +{ + .radio_mode = ZIGBEE_MODE, + .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_ZigBee_MASK, + + /* XCVR_MISC configs */ + .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, + .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(4) | + XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | + XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(2), + + /* XCVR_PHY configs */ + .phy_pre_ref0_init = 0x0, /* Not used in Zigbee */ + .phy_pre_ref1_init = 0x0, /* Not used in Zigbee */ + .phy_pre_ref2_init = 0x0, /* Not used in Zigbee */ + + .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(0) | + XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | + XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | + XCVR_PHY_CFG1_BSM_EN_BLE(0) | + XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | + XCVR_PHY_CFG1_CTS_THRESH(0xC0) | + XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), + + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) +#if !RADIO_IS_GEN_2P1 + | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) +#endif /* !RADIO_IS_GEN_2P1 */ + , + + /* XCVR_PLL_DIG configs */ + + /* XCVR_RX_DIG configs */ + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), + + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(1) | /* Depends on protocol */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ + + .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), + /* XCVR_TSM configs */ +#if (DATA_PADDING_EN) + .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+ZGBE_TX_DIG_EN_TX_HI_ADJ), /* DATA_PADDING adjustments are specified relative to the non-Zigbee base timing */ +#else + .tsm_timing_35_init = B0(ZGBE_TX_DIG_EN_ASSERT), +#endif /* (DATA_PADDING_EN) */ + + /* XCVR_TX_DIG configs */ + .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | + XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | + XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0) , + .tx_gfsk_coeff1_26mhz = 0, + .tx_gfsk_coeff2_26mhz = 0, + .tx_gfsk_coeff1_32mhz = 0, + .tx_gfsk_coeff2_32mhz = 0, +}; + +const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config = +{ + .radio_mode = ZIGBEE_MODE, + .data_rate = DR_500KBPS, + + .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, + .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(1), /* VCO KVM */ + + .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, + .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(1) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(1), /* BBA_BW_SEL and BBA2_BW_SEL */ + .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, + .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(1), /*TZA_BW_SEL */ + + .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | + XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , + + /* AGC configs */ + .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(8) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | + XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | + XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(5) | + XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), + + /* All constant values are represented as 16 bits, register writes will remove unused bits */ + .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0002, + .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0008, + .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, + .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0000, + .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE8, + .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFD7, + .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFE6, + .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0022, + .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0075, + .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00B2, + + /* IEEE 802.15.4 32MHz Channel Filter -- 1.55/1.25/5/0.97/B5 */ + .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFF, + .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0005, + .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0004, + .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, + .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001D, + .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0025, + .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFCE, + .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFA1, + .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0040, + .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0124, + + .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , + .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | + XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , + + .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), + .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), +}; + +/* CUSTOM datarate dependent config structure for ONLY 802.15.4 */ +/*! + * @brief XCVR 500K bps DATA RATE specific configure structure + */ +const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config = +{ + .data_rate = DR_500KBPS, + .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ZB_WIN_SIZE(0) | + XCVR_PHY_EL_CFG_EL_WIN_SIZE(0x8) | + XCVR_PHY_EL_CFG_EL_INTERVAL(0x10) , + .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(1) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_OSR(2) | + XCVR_RX_DIG_RX_DIG_CTRL_RX_DEC_FILT_GAIN(16), + + .agc_ctrl_1_init_26mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(13) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + .agc_ctrl_1_init_32mhz = XCVR_RX_DIG_AGC_CTRL_1_LNA_GAIN_SETTLE_TIME(10) | + XCVR_RX_DIG_AGC_CTRL_1_PRESLOW_EN(PRESLOW_ENA), + + .dcoc_ctrl_0_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(13) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(29), + .dcoc_ctrl_0_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_DLY(21) | + XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(47), + + .dcoc_ctrl_1_init_26mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_ctrl_1_init_32mhz = XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_IDX(2) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_TRK_EST_GS_CNT(0) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_SIGN_SCALE_GS_IDX(1) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHAC_SCALE_GS_IDX(3) | + XCVR_RX_DIG_DCOC_CTRL_1_DCOC_ALPHA_RADIUS_GS_IDX(2), + + .dcoc_cal_iir_init_26mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(2), + .dcoc_cal_iir_init_32mhz = XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(1) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(2) | + XCVR_RX_DIG_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(1), + + .dc_resid_ctrl_26mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(26) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(4), + .dc_resid_ctrl_32mhz = XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_NWIN(48) | + XCVR_RX_DIG_DC_RESID_CTRL_DC_RESID_DLY(0), +}; + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/dbg_ram_capture.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/dbg_ram_capture.c new file mode 100644 index 000000000..b119a82d4 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/dbg_ram_capture.c @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "fsl_device_registers.h" +#include "fsl_xcvr.h" +#include "dbg_ram_capture.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if RADIO_IS_GEN_3P0 +#define PKT_RAM_SIZE_16B_WORDS (1152) /* Number of 16bit entries in each Packet RAM bank */ +#else +#define PKT_RAM_SIZE_16B_WORDS (544) /* Number of 16bit entries in each Packet RAM bank */ +#endif /* RADIO_IS_GEN_3P0 */ +#define SIGN_EXTND_12_16(x) ((x) | (((x) & 0x800) ? 0xF000 : 0x0)) +#define SIGN_EXTND_5_8(x) ((x) | (((x) & 0x10) ? 0xE0 : 0x0)) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +void dbg_ram_init(void) +{ + XCVR_RX_DIG->RX_DIG_CTRL |= XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns on clocking to DMA/DBG blocks */ + XCVR_MISC->PACKET_RAM_CTRL |= XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to just XCVR */ + + /* Some external code must perform the RX warmup request. */ +} + + +dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer) +{ + dbgRamStatus_t status = DBG_RAM_SUCCESS; + uint32_t temp; + volatile uint8_t *pkt_ram_ptr0, *pkt_ram_ptr1; + uint8_t * output_ptr; + uint16_t i; + + /* Some external code must perform the RX warmup request after the dbg_ram_init() call */ + + if (result_buffer == NULL) + { + status = DBG_RAM_FAIL_NULL_POINTER; + } + else + { + if (buffer_sz_bytes > (544*2*2)) + { + status = DBG_RAM_FAIL_SAMPLE_NUM_LIMIT; + } + else + { + temp = XCVR_MISC->PACKET_RAM_CTRL & ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; + switch (dbg_page) + { + case DBG_PAGE_RXDIGIQ: + case DBG_PAGE_RAWADCIQ: + case DBG_PAGE_DCESTIQ: + XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); + + while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) + { + /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ + } + /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ + output_ptr = result_buffer; +#if !RADIO_IS_GEN_2P1 + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); + pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_1[0]); +#else + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); + pkt_ram_ptr1 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[XCVR_PKT_RAM_PACKET_RAM_COUNT>>1]); /* Second packet RAM starts halfway through */ +#endif /* !RADIO_IS_GEN_2P1 */ + /* For *IQ pages I and Q are stored alternately in packet ram 0 & 1 */ + for (i = 0; i < buffer_sz_bytes / 4; i++) + { + *output_ptr++ = *pkt_ram_ptr0++; + *output_ptr++ = *pkt_ram_ptr0++; + *output_ptr++ = *pkt_ram_ptr1++; + *output_ptr++ = *pkt_ram_ptr1++; + } + + break; + case DBG_PAGE_RXINPH: + case DBG_PAGE_DEMOD_HARD: + case DBG_PAGE_DEMOD_SOFT: + case DBG_PAGE_DEMOD_DATA: + case DBG_PAGE_DEMOD_CFO_PH: + XCVR_MISC->PACKET_RAM_CTRL = temp | XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE(dbg_page); + while (!(XCVR_MISC->PACKET_RAM_CTRL & XCVR_CTRL_PACKET_RAM_CTRL_DBG_RAM_FULL(2))) + { + /* Waiting for PKT_RAM to fill, wait for PKT_RAM_1 full to ensure complete memory is filled. */ + } + /* Copy to output by bytes to avoid any access size problems in 16 bit packet RAM. */ + output_ptr = result_buffer; +#if !RADIO_IS_GEN_2P1 + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM_0[0]); +#else + pkt_ram_ptr0 = (volatile uint8_t *)&(XCVR_PKT_RAM->PACKET_RAM[0]); +#endif /* !RADIO_IS_GEN_2P1 */ + /* This is for non I/Q */ + for (i = 0; i < buffer_sz_bytes; i++) + { + *output_ptr = *pkt_ram_ptr0; + pkt_ram_ptr0++; + output_ptr++; + } + break; + case DBG_PAGE_IDLE: + default: + status = DBG_RAM_FAIL_PAGE_ERROR; /* Illegal capture page request. */ + break; + } + } + } + + XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_DBG_PAGE_MASK; /* Clear DBG_PAGE to terminate the acquisition */ + + /* Process the samples and copy to output pointer */ + + XCVR_MISC->PACKET_RAM_CTRL &= ~XCVR_CTRL_PACKET_RAM_CTRL_XCVR_RAM_ALLOW_MASK; /* Make PKT RAM available to protocol blocks */ + XCVR_RX_DIG->RX_DIG_CTRL &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DMA_DTEST_EN_MASK; /* Turns off clocking to DMA/DBG blocks */ + + return status; +} + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/dbg_ram_capture.h b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/dbg_ram_capture.h new file mode 100644 index 000000000..fabba7dae --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/dbg_ram_capture.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _DBG_RAM_CAPTURE_H_ +/* clang-format off */ +#define _DBG_RAM_CAPTURE_H_ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_device_registers.h" + +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Page definitions */ +#define DBG_PAGE_IDLE (0x00) +#define DBG_PAGE_RXDIGIQ (0x01) +#define DBG_PAGE_RAWADCIQ (0x04) +#define DBG_PAGE_DCESTIQ (0x07) +#define DBG_PAGE_RXINPH (0x0A) +#define DBG_PAGE_DEMOD_HARD (0x0B) +#define DBG_PAGE_DEMOD_SOFT (0x0C) +#define DBG_PAGE_DEMOD_DATA (0x0D) +#define DBG_PAGE_DEMOD_CFO_PH (0x0E) + +typedef enum _dbgRamStatus +{ + DBG_RAM_SUCCESS = 0, + DBG_RAM_FAIL_SAMPLE_NUM_LIMIT = 1, + DBG_RAM_FAIL_PAGE_ERROR = 2, + DBG_RAM_FAIL_NULL_POINTER = 3, + DBG_RAM_INVALID_TRIG_SETTING = 4, + DBG_RAM_FAIL_NOT_ENOUGH_SAMPLES = 5, + DBG_RAM_CAPTURE_NOT_COMPLETE = 6, /* Not an error response, but an indication that capture isn't complete for status polling */ +} dbgRamStatus_t; + +#if RADIO_IS_GEN_3P0 +typedef enum _dbgRamStartTriggerType +{ + NO_START_TRIG = 0, + START_ON_FSK_PREAMBLE_FOUND = 1, + START_ON_FSK_AA_MATCH = 2, + START_ON_ZBDEMOD_PREAMBLE_FOUND = 3, + START_ON_ZBDEMOD_SFD_MATCH = 4, + START_ON_AGC_DCOC_GAIN_CHG = 5, + START_ON_TSM_RX_DIG_EN = 6, + START_ON_TSM_SPARE2_EN = 7, + INVALID_START_TRIG = 8 +} dbgRamStartTriggerType; + +typedef enum _dbgRamStopTriggerType +{ + NO_STOP_TRIG = 0, + STOP_ON_FSK_PREAMBLE_FOUND = 1, + STOP_ON_FSK_AA_MATCH = 2, + STOP_ON_ZBDEMOD_PREAMBLE_FOUND = 3, + STOP_ON_ZBDEMOD_SFD_MATCH = 4, + STOP_ON_AGC_DCOC_GAIN_CHG = 5, + STOP_ON_TSM_RX_DIG_EN = 6, + STOP_ON_TSM_SPARE3_EN = 7, + STOP_ON_TSM_PLL_UNLOCK = 8, + STOP_ON_BLE_CRC_ERROR_INC = 9, + STOP_ON_CRC_FAIL_ZGBE_GENFSK = 10, + STOP_ON_GENFSK_HEADER_FAIL = 11, + INVALID_STOP_TRIG = 12 +} dbgRamStopTriggerType; +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief This function prepares for sample capture to packet RAM. + * + * \return None. + * + * \details + * This routine assumes that some other functions in the calling routine both set + * the channel and force RX warmup before calling ::dbg_ram_capture(). + ***********************************************************************************/ +void dbg_ram_init(void); + +/*! ********************************************************************************* + * \brief This function performs any state restoration at the completion of PKT RAM capture. + * + * \details + * Any clocks enabled to the packet RAM capture circuitry are disabled. + ***********************************************************************************/ +void dbg_ram_release(void); + +#if RADIO_IS_GEN_3P0 +/*! ********************************************************************************* + * \brief This function initiates the capture of transceiver data to the transceiver packet RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] dbg_start_trigger - The trigger to start acquisition (must be "no trigger" if a stop trigger is enabled). + * \param[in] dbg_stop_trigger - The trigger to stop acquisition (must be "no trigger" if a start trigger is enabled). + * + * \return Status of the request. + * + * \details + * This function starts the process of capturing data to the packet RAM. Depending upon the start and stop trigger + * settings, the actual capture process can take an indeterminate amount of time. Other APIs are provided to + * perform a blocking wait for completion or allow polling for completion of the capture. + * After any capture has completed, a separate routine must be called to postprocess the capture and copy all + * data out of the packet RAM into a normal RAM buffer. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_start_capture(uint8_t dbg_page, dbgRamStartTriggerType start_trig, dbgRamStopTriggerType stop_trig); + +/*! ********************************************************************************* + * \brief This function performs a blocking wait for completion of the capture of transceiver data to the transceiver packet RAM. + * + * \return Status of the request, DBG_RAM_SUCCESS if capture is complete. + * + * \details + * This function performs a wait loop for capture completion and may take an indeterminate amount of time for + * some capture trigger types. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_wait_for_complete(void); /* Blocking wait for capture completion, no matter what trigger type */ + +/*! ********************************************************************************* + * \brief This function polls the state of the capture of transceiver data to the transceiver packet RAM. + * + * \return Status of the request, DBG_RAM_SUCCESS if capture is complete, DBG_RAM_CAPTURE_NOT_COMPLETE if not complete. + * + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_poll_capture_status(void); /* Non-blocking completion check, just reads the current status of the capure */ + +/*! ********************************************************************************* + * \brief This function processes the captured data into a usable order and copies from packet RAM to normal RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) + * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. + * + * \return None. + * + * \details + * Data is copied from packet RAM in bytes to ensure no access problems. Data is unpacked from packet RAM + * (either sequentially captured or simultaneously captured) into a linear RAM buffer in system RAM. + * If a start trigger is enabled then the first buffer_sz_bytes that are captured are copied out. + * If a stop trigger is enabled then the last buffer_sz_bytes that are captured are copied out. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_postproc_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); /* postprocess a capture to unpack data */ + +#else +/*! ********************************************************************************* + * \brief This function captures transceiver data to the transceiver packet RAM. + * + * \param[in] dbg_page - The page selector (DBG_PAGE). + * \param[in] buffer_sz_bytes - The size of the output buffer (in bytes) + * \param[in] result_buffer - The pointer to the output buffer of a size large enough for the samples. + * + * \return None. + * + * \details + * The capture to packet RAM always captures a full PKT_RAM worth of samples. The samples will be + * copied to the buffer pointed to by result_buffer parameter until buffer_sz_bytes worth of data have + * been copied. Data will be copied + * NOTE: This routine has a slight hazard of getting stuck waiting for debug RAM to fill up when RX has + * not been enabled or RX ends before the RAM fills up (such as when capturing packet data ). It is + * intended to be used with manually triggered RX where RX data will continue as long as needed. + ***********************************************************************************/ +dbgRamStatus_t dbg_ram_capture(uint8_t dbg_page, uint16_t buffer_sz_bytes, void * result_buffer); +#endif /* RADIO_IS_GEN_3P0 */ + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _DBG_RAM_CAPTURE_H_ */ + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.c new file mode 100644 index 000000000..e1b9dcf55 --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.c @@ -0,0 +1,2123 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "EmbeddedTypes.h" +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_xcvr.h" +#include "fsl_xcvr_trim.h" +#include +#include "ifr_radio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define channelMapTableSize (128U) +#define gPllDenom_c 0x02000000U /* Denominator is a constant value */ +#define ABS(x) ((x) > 0 ? (x) : -(x)) + +#ifndef TRUE +#define TRUE (true) +#endif + +#ifndef FALSE +#define FALSE (false) +#endif +#define RF_OSCILLATOR_STAYS_ON (false) /* Control whether RF_OSC can be left on all the time. */ +#define RF_OSCILLATOR_READY ((RSIM->CONTROL & RSIM_CONTROL_RF_OSC_READY_MASK) != 0x0U) + +#ifndef EXTERNAL_CLOCK_GEN +#define EXTERNAL_CLOCK_GEN 0 +#endif + +#define ANT_A 1 +#define ANT_B 0 + +#ifndef XCVR_COEX_RF_ACTIVE_PIN +#define XCVR_COEX_RF_ACTIVE_PIN ANT_B +#endif /* XCVR_COEX_RF_ACTIVE_PIN */ + +typedef struct xcvr_pllChannel_tag +{ + unsigned int integer; + unsigned int numerator; +} xcvr_pllChannel_t; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address); +void rf_osc_startup(void); +void rf_osc_shutdown(void); +extern double trunc (double); +extern double round (double); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static panic_fptr s_PanicFunctionPtr = NULL; +const xcvr_pllChannel_t mapTable [channelMapTableSize] = +{ + {0x00000025, 0x07C00000}, /* 0 */ + {0x00000025, 0x07C80000}, /* 1 */ + {0x00000025, 0x07D00000}, /* 2 */ + {0x00000025, 0x07D80000}, /* 3 */ + {0x00000025, 0x07E00000}, /* 4 */ + {0x00000025, 0x07E80000}, /* 5 */ + {0x00000025, 0x07F00000}, /* 6 */ + {0x00000025, 0x07F80000}, /* 7 */ + {0x00000025, 0x00000000}, /* 8 */ + {0x00000025, 0x00080000}, /* 9 */ + {0x00000025, 0x00100000}, /* 10 */ + {0x00000025, 0x00180000}, /* 11 */ + {0x00000025, 0x00200000}, /* 12 */ + {0x00000025, 0x00280000}, /* 13 */ + {0x00000025, 0x00300000}, /* 14 */ + {0x00000025, 0x00380000}, /* 15 */ + {0x00000025, 0x00400000}, /* 16 */ + {0x00000025, 0x00480000}, /* 17 */ + {0x00000025, 0x00500000}, /* 18 */ + {0x00000025, 0x00580000}, /* 19 */ + {0x00000025, 0x00600000}, /* 20 */ + {0x00000025, 0x00680000}, /* 21 */ + {0x00000025, 0x00700000}, /* 22 */ + {0x00000025, 0x00780000}, /* 23 */ + {0x00000025, 0x00800000}, /* 24 */ + {0x00000025, 0x00880000}, /* 25 */ + {0x00000025, 0x00900000}, /* 26 */ + {0x00000025, 0x00980000}, /* 27 */ + {0x00000025, 0x00A00000}, /* 28 */ + {0x00000025, 0x00A80000}, /* 29 */ + {0x00000025, 0x00B00000}, /* 30 */ + {0x00000025, 0x00B80000}, /* 31 */ + {0x00000025, 0x00C00000}, /* 32 */ + {0x00000025, 0x00C80000}, /* 33 */ + {0x00000025, 0x00D00000}, /* 34 */ + {0x00000025, 0x00D80000}, /* 35 */ + {0x00000025, 0x00E00000}, /* 36 */ + {0x00000025, 0x00E80000}, /* 37 */ + {0x00000025, 0x00F00000}, /* 38 */ + {0x00000025, 0x00F80000}, /* 39 */ + {0x00000025, 0x01000000}, /* 40 */ + {0x00000026, 0x07080000}, /* 41 */ + {0x00000026, 0x07100000}, /* 42 */ + {0x00000026, 0x07180000}, /* 43 */ + {0x00000026, 0x07200000}, /* 44 */ + {0x00000026, 0x07280000}, /* 45 */ + {0x00000026, 0x07300000}, /* 46 */ + {0x00000026, 0x07380000}, /* 47 */ + {0x00000026, 0x07400000}, /* 48 */ + {0x00000026, 0x07480000}, /* 49 */ + {0x00000026, 0x07500000}, /* 50 */ + {0x00000026, 0x07580000}, /* 51 */ + {0x00000026, 0x07600000}, /* 52 */ + {0x00000026, 0x07680000}, /* 53 */ + {0x00000026, 0x07700000}, /* 54 */ + {0x00000026, 0x07780000}, /* 55 */ + {0x00000026, 0x07800000}, /* 56 */ + {0x00000026, 0x07880000}, /* 57 */ + {0x00000026, 0x07900000}, /* 58 */ + {0x00000026, 0x07980000}, /* 59 */ + {0x00000026, 0x07A00000}, /* 60 */ + {0x00000026, 0x07A80000}, /* 61 */ + {0x00000026, 0x07B00000}, /* 62 */ + {0x00000026, 0x07B80000}, /* 63 */ + {0x00000026, 0x07C00000}, /* 64 */ + {0x00000026, 0x07C80000}, /* 65 */ + {0x00000026, 0x07D00000}, /* 66 */ + {0x00000026, 0x07D80000}, /* 67 */ + {0x00000026, 0x07E00000}, /* 68 */ + {0x00000026, 0x07E80000}, /* 69 */ + {0x00000026, 0x07F00000}, /* 70 */ + {0x00000026, 0x07F80000}, /* 71 */ + {0x00000026, 0x00000000}, /* 72 */ + {0x00000026, 0x00080000}, /* 73 */ + {0x00000026, 0x00100000}, /* 74 */ + {0x00000026, 0x00180000}, /* 75 */ + {0x00000026, 0x00200000}, /* 76 */ + {0x00000026, 0x00280000}, /* 77 */ + {0x00000026, 0x00300000}, /* 78 */ + {0x00000026, 0x00380000}, /* 79 */ + {0x00000026, 0x00400000}, /* 80 */ + {0x00000026, 0x00480000}, /* 81 */ + {0x00000026, 0x00500000}, /* 82 */ + {0x00000026, 0x00580000}, /* 83 */ + {0x00000026, 0x00600000}, /* 84 */ + {0x00000026, 0x00680000}, /* 85 */ + {0x00000026, 0x00700000}, /* 86 */ + {0x00000026, 0x00780000}, /* 87 */ + {0x00000026, 0x00800000}, /* 88 */ + {0x00000026, 0x00880000}, /* 89 */ + {0x00000026, 0x00900000}, /* 90 */ + {0x00000026, 0x00980000}, /* 91 */ + {0x00000026, 0x00A00000}, /* 92 */ + {0x00000026, 0x00A80000}, /* 93 */ + {0x00000026, 0x00B00000}, /* 94 */ + {0x00000026, 0x00B80000}, /* 95 */ + {0x00000026, 0x00C00000}, /* 96 */ + {0x00000026, 0x00C80000}, /* 97 */ + {0x00000026, 0x00D00000}, /* 98 */ + {0x00000026, 0x00D80000}, /* 99 */ + {0x00000026, 0x00E00000}, /* 100 */ + {0x00000026, 0x00E80000}, /* 101 */ + {0x00000026, 0x00F00000}, /* 102 */ + {0x00000026, 0x00F80000}, /* 103 */ + {0x00000026, 0x01000000}, /* 104 */ + {0x00000027, 0x07080000}, /* 105 */ + {0x00000027, 0x07100000}, /* 106 */ + {0x00000027, 0x07180000}, /* 107 */ + {0x00000027, 0x07200000}, /* 108 */ + {0x00000027, 0x07280000}, /* 109 */ + {0x00000027, 0x07300000}, /* 110 */ + {0x00000027, 0x07380000}, /* 111 */ + {0x00000027, 0x07400000}, /* 112 */ + {0x00000027, 0x07480000}, /* 113 */ + {0x00000027, 0x07500000}, /* 114 */ + {0x00000027, 0x07580000}, /* 115 */ + {0x00000027, 0x07600000}, /* 116 */ + {0x00000027, 0x07680000}, /* 117 */ + {0x00000027, 0x07700000}, /* 118 */ + {0x00000027, 0x07780000}, /* 119 */ + {0x00000027, 0x07800000}, /* 120 */ + {0x00000027, 0x07880000}, /* 121 */ + {0x00000027, 0x07900000}, /* 122 */ + {0x00000027, 0x07980000}, /* 123 */ + {0x00000027, 0x07A00000}, /* 124 */ + {0x00000027, 0x07A80000}, /* 125 */ + {0x00000027, 0x07B00000}, /* 126 */ + {0x00000027, 0x07B80000} /* 127 */ +}; + +/* Registers for timing of TX & RX */ +#if RADIO_IS_GEN_3P0 +uint16_t tx_rx_on_delay = TX_RX_ON_DELinit; +uint16_t tx_rx_synth_delay = TX_RX_SYNTH_init; +#else +#if RF_OSC_26MHZ == 1 +uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL_26MHZ; +#else +uint16_t tx_rx_on_delay = TX_RX_ON_DELAY_VAL; +#endif /* RF_OSC_26MHZ == 1 */ +uint16_t tx_rx_synth_delay = TX_RX_SYNTH_DELAY_VAL; +#endif /* RADIO_IS_GEN_3P0 */ + +/* NOTE: These arrays MUST be ordered in the same order as the radio_mode_t enumeration. */ +#if RADIO_IS_GEN_3P0 +const xcvr_mode_datarate_config_t * mode_configs_dr_2mbps[NUM_RADIO_MODES] = +{ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + &xcvr_GFSK_BT_0p5_h_0p5_2mbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_2mbps_config, + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + (xcvr_mode_datarate_config_t *)NULL, /* 2Mbps rate not supported for this mode */ + &xcvr_GFSK_BT_0p3_h_0p5_2mbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_2mbps_config, + &xcvr_MSK_2mbps_config, +}; +#endif /* RADIO_IS_GEN_3P0 */ + +const xcvr_mode_datarate_config_t * mode_configs_dr_1mbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ + &xcvr_ANT_1mbps_config, +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_1mbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_1mbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_1mbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_1mbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_1mbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_1mbps_config, + &xcvr_MSK_1mbps_config, +}; + +const xcvr_mode_datarate_config_t * mode_configs_dr_500kbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, /* Invalid option */ +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 setting */ + &xcvr_ANT_1mbps_config, /* Invalid option */ +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_500kbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_500kbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_500kbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_500kbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_500kbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_500kbps_config, + &xcvr_MSK_500kbps_config, +}; +const xcvr_mode_datarate_config_t * mode_configs_dr_250kbps[NUM_RADIO_MODES] = +{ + &xcvr_BLE_1mbps_config, /* Invalid option */ +#if RADIO_IS_GEN_2P1 + NULL, + NULL, +#else + &xcvr_ZIGBEE_500kbps_config, /* 802.15.4 only supports one configuration */ + &xcvr_ANT_1mbps_config, /* Invalid option */ +#endif /* RADIO_IS_GEN_2P1 */ + &xcvr_GFSK_BT_0p5_h_0p5_250kbps_config, + &xcvr_GFSK_BT_0p5_h_0p32_250kbps_config, + &xcvr_GFSK_BT_0p5_h_0p7_250kbps_config, + &xcvr_GFSK_BT_0p5_h_1p0_250kbps_config, + &xcvr_GFSK_BT_0p3_h_0p5_250kbps_config, + &xcvr_GFSK_BT_0p7_h_0p5_250kbps_config, + &xcvr_MSK_250kbps_config, +}; + +static xcvr_currConfig_t current_xcvr_config; + +void rf_osc_startup(void) +{ + if (!RF_OSCILLATOR_READY) + { + RSIM->CONTROL |= RSIM_CONTROL_RF_OSC_EN_MASK; + } + while (!RF_OSCILLATOR_READY) + { + /* Wait for RF_OSC_READY to be asserted before continuing */ + } +} + +void rf_osc_shutdown(void) +{ + if (!RF_OSCILLATOR_STAYS_ON) + { + RSIM->CONTROL &= ~RSIM_CONTROL_RF_OSC_EN_MASK; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ +xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate) +{ + const xcvr_mode_datarate_config_t * mode_datarate_config; + const xcvr_datarate_config_t * datarate_config ; + const xcvr_mode_config_t * radio_mode_cfg; + const xcvr_common_config_t * radio_common_config; + + xcvrStatus_t status; + + IFR_SW_TRIM_TBL_ENTRY_T sw_trim_tbl[] = + { + {TRIM_STATUS, 0, FALSE}, /*< Fetch the trim status word if available.*/ + {TRIM_VERSION, 0, FALSE} /*< Fetch the trim version number if available.*/ + }; + const uint8_t NUM_TRIM_TBL_ENTRIES = sizeof(sw_trim_tbl)/sizeof(IFR_SW_TRIM_TBL_ENTRY_T); + +#ifndef SIMULATION + +#if (EXTERNAL_CLOCK_GEN) + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RF_OSC_BYPASS_EN_MASK; /* Only when external clock is being used */ +#endif /* EXTERNAL_CLOCK_GEN */ + +#if RADIO_IS_GEN_2P0 + RSIM->RF_OSC_CTRL &= ~RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_MASK; /* Set EXT_OSC_OVRD value to zero */ + RSIM->RF_OSC_CTRL |= RSIM_RF_OSC_CTRL_RADIO_EXT_OSC_OVRD_EN_MASK; /* Enable over-ride with zero value */ +#endif /* RADIO_IS_GEN_2P0 */ + + /* Check that this is the proper radio version */ + { + uint8_t radio_id = ((RSIM->MISC & RSIM_MISC_RADIO_VERSION_MASK)>>RSIM_MISC_RADIO_VERSION_SHIFT); + + if ( +#if RADIO_IS_GEN_3P0 + (radio_id != 0x5) /* KW3 Gen3 */ +#elif RADIO_IS_GEN_2P1 + (radio_id != 0x5) /* KW35 Gen2.1 */ +#else + (radio_id != 0x3) && /* KW41/31/21 v1 */ + (radio_id != 0xB) /* KW41/31/21 v1.1 */ +#endif /* RADIO_IS_GEN_3P0 */ + ) + { + XcvrPanic(WRONG_RADIO_ID_DETECTED, (uint32_t)&XCVR_Init); + } + } + +#if RADIO_IS_GEN_3P0 + /* Assert Radio Run Request and wait for ack from SPM. */ + RSIM->POWER |= RSIM_POWER_RSIM_RUN_REQUEST_MASK; + while ((RSIM->POWER & RSIM_POWER_SPM_RUN_ACK_STAT_MASK) == 0) + { + } + RSIM->CONTROL |= RSIM_CONTROL_RSIM_CGC_XCVR_EN_MASK; + rf_osc_startup(); /* Start RF_OSC to allow radio registers access */ +#else + SIM->SCGC5 |= SIM_SCGC5_PHYDIG_MASK; + + /* Load IFR trim values */ + handle_ifr(&sw_trim_tbl[0], NUM_TRIM_TBL_ENTRIES); +#endif /* RADIO_IS_GEN_3P0 */ + +#endif /* ifndef SIMULATION */ + + /* Perform the desired XCVR initialization and configuration */ + status = XCVR_GetDefaultConfig(radio_mode, data_rate, + (const xcvr_common_config_t **)&radio_common_config, + (const xcvr_mode_config_t **)&radio_mode_cfg, + (const xcvr_mode_datarate_config_t **)&mode_datarate_config, + (const xcvr_datarate_config_t **)&datarate_config); + + if (status == gXcvrSuccess_c) + { + status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, + (const xcvr_mode_config_t *)radio_mode_cfg, + (const xcvr_mode_datarate_config_t *)mode_datarate_config, + (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_FIRST_INIT); + current_xcvr_config.radio_mode = radio_mode; + current_xcvr_config.data_rate = data_rate; + } + + return status; +} + +void XCVR_Deinit(void) +{ +#if RADIO_IS_GEN_3P0 + rf_osc_shutdown(); + RSIM->POWER |= RSIM_POWER_RSIM_STOP_MODE_MASK; /* Set radio stop mode to RVLLS */ + RSIM->POWER &= ~RSIM_POWER_RSIM_RUN_REQUEST_MASK; /* Clear RUN request */ +#else + +#endif /* RADIO_IS_GEN_3P0 */ +} + +xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, + data_rate_t data_rate, + const xcvr_common_config_t ** com_config, + const xcvr_mode_config_t ** mode_config, + const xcvr_mode_datarate_config_t ** mode_datarate_config, + const xcvr_datarate_config_t ** datarate_config) +{ + xcvrStatus_t status = gXcvrSuccess_c; + /* Common configuration pointer */ + *com_config = (const xcvr_common_config_t *)&xcvr_common_config; + + /* Mode dependent configuration pointer */ + switch (radio_mode) + { +#if !RADIO_IS_GEN_2P1 + case ZIGBEE_MODE: + *mode_config = ( const xcvr_mode_config_t *)&zgbe_mode_config; /* Zigbee configuration */ + break; + case ANT_MODE: + *mode_config = ( const xcvr_mode_config_t *)&ant_mode_config; /* ANT configuration */ + break; +#endif /* !RADIO_IS_GEN_2P1 */ + case BLE_MODE: + *mode_config = ( const xcvr_mode_config_t *)&ble_mode_config; /* BLE configuration */ + break; + case GFSK_BT_0p5_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p5_mode_config; /* GFSK_BT_0p5_h_0p5 configuration */ + break; + case GFSK_BT_0p5_h_0p32: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p32_mode_config; /* GFSK_BT_0p5_h_0p32 configuration */ + break; + case GFSK_BT_0p5_h_0p7: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_0p7_mode_config; /* GFSK_BT_0p5_h_0p7 configuration */ + break; + case GFSK_BT_0p5_h_1p0: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p5_h_1p0_mode_config; /* GFSK_BT_0p5_h_1p0 configuration */ + break; + case GFSK_BT_0p3_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p3_h_0p5_mode_config; /* GFSK_BT_0p3_h_0p5 configuration */ + break; + case GFSK_BT_0p7_h_0p5: + *mode_config = ( const xcvr_mode_config_t *)&gfsk_bt_0p7_h_0p5_mode_config; /* GFSK_BT_0p7_h_0p5 configuration */ + break; + case MSK: + *mode_config = ( const xcvr_mode_config_t *)&msk_mode_config; /* MSK configuration */ + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + + /* Data rate dependent and modeXdatarate dependent configuration pointers */ + if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ + { + switch (data_rate) + { +#if RADIO_IS_GEN_3P0 + case DR_2MBPS: + if ((radio_mode == GFSK_BT_0p5_h_0p7) || (radio_mode == GFSK_BT_0p5_h_1p0) || (radio_mode == ZIGBEE_MODE) || (radio_mode == BLE_MODE) || (radio_mode == ANT_MODE)) + { + status = gXcvrInvalidParameters_c; + } + else + { + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_2mbps_config; /* 2Mbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_2mbps[radio_mode]; + } + break; +#endif /* RADIO_IS_GEN_3P0 */ + case DR_1MBPS: + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_1mbps_config; /* 1Mbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_1mbps[radio_mode]; + break; + case DR_500KBPS: + if (radio_mode == ZIGBEE_MODE) + { + /* See fsl_xcvr_zgbe_config.c for settings */ +#if !RADIO_IS_GEN_2P1 + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_802_15_4_500kbps_config; /* 500Kbps datarate configurations */ +#endif /* !RADIO_IS_GEN_2P1 */ + } + else + { + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_500kbps_config; /* 500Kbps datarate configurations */ + } + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_500kbps[radio_mode]; + break; + case DR_250KBPS: + *datarate_config = (const xcvr_datarate_config_t *)&xcvr_250kbps_config; /* 250Kbps datarate configurations */ + *mode_datarate_config = (const xcvr_mode_datarate_config_t *)mode_configs_dr_250kbps[radio_mode]; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + return status; +} + +xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config, + int16_t tempDegC, + XCVR_INIT_MODE_CHG_T first_init) +{ + xcvrStatus_t config_status = gXcvrSuccess_c; + uint32_t temp; + + /* Turn on the module clocks before doing anything */ +#if RADIO_IS_GEN_3P0 + RSIM->CONTROL |= mode_config->scgc5_clock_ena_bits; /* Same bit storage is used but RSIM bit assignments are applied */ +#else + SIM->SCGC5 |= mode_config->scgc5_clock_ena_bits; +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_ANA configs */ + /*******************************************************************************/ + + /* Configure PLL Loop Filter */ + if (first_init) + { + XCVR_ANA->SY_CTRL_1 &= ~com_config->ana_sy_ctrl1.mask; + XCVR_ANA->SY_CTRL_1 |= com_config->ana_sy_ctrl1.init; + } + + /* Configure VCO KVM */ + XCVR_ANA->SY_CTRL_2 &= ~mode_datarate_config->ana_sy_ctrl2.mask; + XCVR_ANA->SY_CTRL_2 |= mode_datarate_config->ana_sy_ctrl2.init; + + /* Configure analog filter bandwidth */ + XCVR_ANA->RX_BBA &= ~mode_datarate_config->ana_rx_bba.mask; + XCVR_ANA->RX_BBA |= mode_datarate_config->ana_rx_bba.init; + XCVR_ANA->RX_TZA &= ~mode_datarate_config->ana_rx_tza.mask; + XCVR_ANA->RX_TZA |= mode_datarate_config->ana_rx_tza.init; + +#if RADIO_IS_GEN_2P0 + if (first_init) + { + temp = XCVR_ANA->TX_DAC_PA; + temp &= ~XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS_MASK; + temp |= XCVR_ANALOG_TX_DAC_PA_TX_PA_BUMP_VBIAS(4); + XCVR_ANA->TX_DAC_PA = temp; + + temp = XCVR_ANA->BB_LDO_2; + temp &= ~XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM_MASK; + temp |= XCVR_ANALOG_BB_LDO_2_BB_LDO_VCOLO_TRIM(0); + XCVR_ANA->BB_LDO_2 = temp; + + temp = XCVR_ANA->RX_LNA; + temp &= ~XCVR_ANALOG_RX_LNA_RX_LNA_BUMP_MASK; + temp |= XCVR_ANALOG_RX_LNA_RX_LNA_BUMP(1); + XCVR_ANA->RX_LNA = temp; + + temp = XCVR_ANA->BB_LDO_1; + temp &= ~XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM_MASK; + temp |= XCVR_ANALOG_BB_LDO_1_BB_LDO_FDBK_TRIM(1); + XCVR_ANA->BB_LDO_1 = temp; + } +#endif /* RADIO_IS_GEN_2P0 */ + + /*******************************************************************************/ + /* XCVR_MISC configs */ + /*******************************************************************************/ + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~(mode_config->xcvr_ctrl.mask | XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ_MASK); + temp |= mode_config->xcvr_ctrl.init; + +#if RF_OSC_26MHZ == 1 + { + temp |= XCVR_CTRL_XCVR_CTRL_REF_CLK_FREQ(1); + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_MISC->XCVR_CTRL = temp; + +#if RADIO_IS_GEN_2P1 + XCVR_MISC->FAD_CTRL &= ~XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK; +#endif /* RADIO_IS_GEN_2P1 */ + + /*******************************************************************************/ + /* XCVR_PHY configs */ + /*******************************************************************************/ +#if RADIO_IS_GEN_3P0 + XCVR_PHY->PHY_FSK_PD_CFG0 = mode_config->phy_fsk_pd_cfg0; + XCVR_PHY->PHY_FSK_PD_CFG1 = mode_config->phy_fsk_pd_cfg1; + XCVR_PHY->PHY_FSK_CFG = mode_config->phy_fsk_cfg; + XCVR_PHY->PHY_FSK_MISC = mode_config->phy_fsk_misc | mode_datarate_config->phy_fsk_misc_mode_datarate; + XCVR_PHY->FSK_FAD_CTRL = mode_config->phy_fad_ctrl; +#else + XCVR_PHY->PHY_PRE_REF0 = mode_config->phy_pre_ref0_init; + XCVR_PHY->PRE_REF1 = mode_config->phy_pre_ref1_init; + XCVR_PHY->PRE_REF2 = mode_config->phy_pre_ref2_init; + XCVR_PHY->CFG1 = mode_config->phy_cfg1_init; + XCVR_PHY->CFG2 = mode_datarate_config->phy_cfg2_init; + XCVR_PHY->EL_CFG = mode_config->phy_el_cfg_init | datarate_config->phy_el_cfg_init; /* EL_WIN_SIZE and EL_INTERVAL are datarate dependent, */ +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_PLL_DIG configs */ + /*******************************************************************************/ + if (first_init) + { + XCVR_PLL_DIG->HPM_BUMP = com_config->pll_hpm_bump; + XCVR_PLL_DIG->MOD_CTRL = com_config->pll_mod_ctrl; + XCVR_PLL_DIG->CHAN_MAP = com_config->pll_chan_map; + XCVR_PLL_DIG->LOCK_DETECT = com_config->pll_lock_detect; + XCVR_PLL_DIG->HPM_CTRL = com_config->pll_hpm_ctrl; +#if !RADIO_IS_GEN_2P1 + XCVR_PLL_DIG->HPMCAL_CTRL = com_config->pll_hpmcal_ctrl; +#endif /* !RADIO_IS_GEN_2P1 */ + XCVR_PLL_DIG->HPM_SDM_RES = com_config->pll_hpm_sdm_res; + XCVR_PLL_DIG->LPM_CTRL = com_config->pll_lpm_ctrl; + XCVR_PLL_DIG->LPM_SDM_CTRL1 = com_config->pll_lpm_sdm_ctrl1; + XCVR_PLL_DIG->DELAY_MATCH = com_config->pll_delay_match; + XCVR_PLL_DIG->CTUNE_CTRL = com_config->pll_ctune_ctrl; + } + + /*******************************************************************************/ + /* XCVR_RX_DIG configs */ + /*******************************************************************************/ + + /* Configure RF Aux PLL for proper operation based on external clock frequency */ + if (first_init) + { + temp = XCVR_ANA->RX_AUXPLL; + temp &= ~XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST_MASK; +#if RF_OSC_26MHZ == 1 + { + temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(4); + } +#else + { + temp |= XCVR_ANALOG_RX_AUXPLL_VCO_DAC_REF_ADJUST(7); + } +#endif /* RF_OSC_26MHZ == 1 */ + XCVR_ANA->RX_AUXPLL = temp; + } + + /* Configure RX_DIG_CTRL */ +#if RF_OSC_26MHZ == 1 + { + temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ + mode_config->rx_dig_ctrl_init_26mhz | /* Mode specific portion of RX_DIG_CTRL init */ + datarate_config->rx_dig_ctrl_init_26mhz | /* Datarate specific portion of RX_DIG_CTRL init */ + XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_EN_MASK; /* Always enable the sample rate converter for 26MHz */ + } +#else + { + temp = com_config->rx_dig_ctrl_init | /* Common portion of RX_DIG_CTRL init */ + mode_config->rx_dig_ctrl_init_32mhz | /* Mode specific portion of RX_DIG_CTRL init */ + datarate_config->rx_dig_ctrl_init_32mhz | /* Datarate specific portion of RX_DIG_CTRL init */ + 0; /* Always disable the sample rate converter for 32MHz */ + } +#endif /* RF_OSC_26MHZ == 1 */ + + temp |= com_config->rx_dig_ctrl_init; /* Common portion of RX_DIG_CTRL init */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + /* DCOC_CAL_IIR */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_26mhz; + } +#else + { + XCVR_RX_DIG->DCOC_CAL_IIR = datarate_config->dcoc_cal_iir_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* DC_RESID_CTRL */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_26mhz; + } +#else + { + XCVR_RX_DIG->DC_RESID_CTRL = com_config->dc_resid_ctrl_init | datarate_config->dc_resid_ctrl_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* DCOC_CTRL_0 & _1 */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_26mhz | datarate_config->dcoc_ctrl_0_init_26mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_26mhz; +#endif /* RADIO_IS_GEN_3P0 */ + + } +#else + { + XCVR_RX_DIG->DCOC_CTRL_0 = com_config->dcoc_ctrl_0_init_32mhz | datarate_config->dcoc_ctrl_0_init_32mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = com_config->dcoc_ctrl_1_init | datarate_config->dcoc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->DCOC_CTRL_2 = datarate_config->dcoc_ctrl_2_init_32mhz; +#endif /* RADIO_IS_GEN_3P0 */ + } +#endif /* RF_OSC_26MHZ == 1 */ + if (first_init) + { + /* DCOC_CAL_GAIN */ + XCVR_RX_DIG->DCOC_CAL_GAIN = com_config->dcoc_cal_gain_init; + + /* DCOC_CAL_RCP */ + XCVR_RX_DIG->DCOC_CAL_RCP = com_config->dcoc_cal_rcp_init; + XCVR_RX_DIG->LNA_GAIN_VAL_3_0 = com_config->lna_gain_val_3_0; + XCVR_RX_DIG->LNA_GAIN_VAL_7_4 = com_config->lna_gain_val_7_4; + XCVR_RX_DIG->LNA_GAIN_VAL_8 = com_config->lna_gain_val_8; + XCVR_RX_DIG->BBA_RES_TUNE_VAL_7_0 = com_config->bba_res_tune_val_7_0; + XCVR_RX_DIG->BBA_RES_TUNE_VAL_10_8 = com_config->bba_res_tune_val_10_8; + + /* LNA_GAIN_LIN_VAL */ + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_2_0 = com_config->lna_gain_lin_val_2_0_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_5_3 = com_config->lna_gain_lin_val_5_3_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_8_6 = com_config->lna_gain_lin_val_8_6_init; + XCVR_RX_DIG->LNA_GAIN_LIN_VAL_9 = com_config->lna_gain_lin_val_9_init; + + /* BBA_RES_TUNE_LIN_VAL */ + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_3_0 = com_config->bba_res_tune_lin_val_3_0_init; + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_7_4 = com_config->bba_res_tune_lin_val_7_4_init; + XCVR_RX_DIG->BBA_RES_TUNE_LIN_VAL_10_8 = com_config->bba_res_tune_lin_val_10_8_init; + + /* BBA_STEP */ + XCVR_RX_DIG->DCOC_BBA_STEP = com_config->dcoc_bba_step_init; + + /* DCOC_TZA_STEP */ + XCVR_RX_DIG->DCOC_TZA_STEP_0 = com_config->dcoc_tza_step_00_init; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = com_config->dcoc_tza_step_01_init; + XCVR_RX_DIG->DCOC_TZA_STEP_2 = com_config->dcoc_tza_step_02_init; + XCVR_RX_DIG->DCOC_TZA_STEP_3 = com_config->dcoc_tza_step_03_init; + XCVR_RX_DIG->DCOC_TZA_STEP_4 = com_config->dcoc_tza_step_04_init; + XCVR_RX_DIG->DCOC_TZA_STEP_5 = com_config->dcoc_tza_step_05_init; + XCVR_RX_DIG->DCOC_TZA_STEP_6 = com_config->dcoc_tza_step_06_init; + XCVR_RX_DIG->DCOC_TZA_STEP_7 = com_config->dcoc_tza_step_07_init; + XCVR_RX_DIG->DCOC_TZA_STEP_8 = com_config->dcoc_tza_step_08_init; + XCVR_RX_DIG->DCOC_TZA_STEP_9 = com_config->dcoc_tza_step_09_init; + XCVR_RX_DIG->DCOC_TZA_STEP_10 = com_config->dcoc_tza_step_10_init; + +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + /* DCOC_CAL_FAIL and DCOC_CAL_PASS */ + XCVR_RX_DIG->DCOC_CAL_FAIL_TH = com_config->dcoc_cal_fail_th_init; + XCVR_RX_DIG->DCOC_CAL_PASS_TH = com_config->dcoc_cal_pass_th_init; +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + } + + /* AGC_CTRL_0 .. _3 */ + XCVR_RX_DIG->AGC_CTRL_0 = com_config->agc_ctrl_0_init | mode_config->agc_ctrl_0_init; + +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_26mhz | datarate_config->agc_ctrl_1_init_26mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_26mhz; + } +#else + { + XCVR_RX_DIG->AGC_CTRL_1 = com_config->agc_ctrl_1_init_32mhz | datarate_config->agc_ctrl_1_init_32mhz; /* Combine common and datarate specific settings */ + XCVR_RX_DIG->AGC_CTRL_2 = mode_datarate_config->agc_ctrl_2_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + if (first_init) + { + XCVR_RX_DIG->AGC_CTRL_3 = com_config->agc_ctrl_3_init; + + /* AGC_GAIN_TBL_** */ + XCVR_RX_DIG->AGC_GAIN_TBL_03_00 = com_config->agc_gain_tbl_03_00_init; + XCVR_RX_DIG->AGC_GAIN_TBL_07_04 = com_config->agc_gain_tbl_07_04_init; + XCVR_RX_DIG->AGC_GAIN_TBL_11_08 = com_config->agc_gain_tbl_11_08_init; + XCVR_RX_DIG->AGC_GAIN_TBL_15_12 = com_config->agc_gain_tbl_15_12_init; + XCVR_RX_DIG->AGC_GAIN_TBL_19_16 = com_config->agc_gain_tbl_19_16_init; + XCVR_RX_DIG->AGC_GAIN_TBL_23_20 = com_config->agc_gain_tbl_23_20_init; + XCVR_RX_DIG->AGC_GAIN_TBL_26_24 = com_config->agc_gain_tbl_26_24_init; + + /* RSSI_CTRL_0 */ + XCVR_RX_DIG->RSSI_CTRL_0 = com_config->rssi_ctrl_0_init; + +#if RADIO_IS_GEN_3P0 + XCVR_RX_DIG->RSSI_CTRL_1 = com_config->rssi_ctrl_1_init; +#endif /* RADIO_IS_GEN_3P0 */ + + /* CCA_ED_LQI_0 and _1 */ + XCVR_RX_DIG->CCA_ED_LQI_CTRL_0 = com_config->cca_ed_lqi_ctrl_0_init; + XCVR_RX_DIG->CCA_ED_LQI_CTRL_1 = com_config->cca_ed_lqi_ctrl_1_init; + } + + /* Channel filter coefficients */ +#if RF_OSC_26MHZ == 1 + { + XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_0; + XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_1; + XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_2; + XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_3; + XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_4; + XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_5; + XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_6; + XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_7; + XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_8; + XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_9; + XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_10; + XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_26mhz.rx_chf_coef_11; + } +#else + { + XCVR_RX_DIG->RX_CHF_COEF_0 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_0; + XCVR_RX_DIG->RX_CHF_COEF_1 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_1; + XCVR_RX_DIG->RX_CHF_COEF_2 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_2; + XCVR_RX_DIG->RX_CHF_COEF_3 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_3; + XCVR_RX_DIG->RX_CHF_COEF_4 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_4; + XCVR_RX_DIG->RX_CHF_COEF_5 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_5; + XCVR_RX_DIG->RX_CHF_COEF_6 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_6; + XCVR_RX_DIG->RX_CHF_COEF_7 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_7; + XCVR_RX_DIG->RX_CHF_COEF_8 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_8; + XCVR_RX_DIG->RX_CHF_COEF_9 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_9; + XCVR_RX_DIG->RX_CHF_COEF_10 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_10; + XCVR_RX_DIG->RX_CHF_COEF_11 = mode_datarate_config->rx_chf_coeffs_32mhz.rx_chf_coef_11; + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_RX_DIG->RX_RCCAL_CTRL0 = mode_datarate_config->rx_rccal_ctrl_0; + XCVR_RX_DIG->RX_RCCAL_CTRL1 = mode_datarate_config->rx_rccal_ctrl_1; + + /*******************************************************************************/ + /* XCVR_TSM configs */ + /*******************************************************************************/ + XCVR_TSM->CTRL = com_config->tsm_ctrl; + +#if RADIO_IS_GEN_2P0 + if ((mode_config->radio_mode != ZIGBEE_MODE) && (mode_config->radio_mode != BLE_MODE)) + { + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_DATA_PADDING_EN_MASK; + } +#endif /* RADIO_IS_GEN_2P0 */ + + if (first_init) + { +#if !RADIO_IS_GEN_2P1 + XCVR_MISC->LPPS_CTRL = com_config->lpps_ctrl_init; /* Register is in XCVR_MISC but grouped with TSM for intialization */ +#endif /* !RADIO_IS_GEN_2P1 */ + + XCVR_TSM->OVRD2 = com_config->tsm_ovrd2_init; + /* TSM registers and timings - dependent upon clock frequency */ +#if RF_OSC_26MHZ == 1 + { + XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_26mhz; + XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_26mhz; + XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_26mhz; + XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_26mhz; + XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_26mhz; + XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_26mhz; + XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_26mhz; + XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_26mhz; + XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_26mhz; + XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_26mhz; + XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_26mhz; + XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_26mhz; + XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_26mhz; + XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_26mhz; + XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_26mhz; + XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_26mhz; + XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_26mhz; + XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_26mhz; + XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_26mhz; + XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_26mhz; + XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_26mhz; + XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_26mhz; + } +#else + { + XCVR_TSM->END_OF_SEQ = com_config->end_of_seq_init_32mhz; + XCVR_TSM->FAST_CTRL2 = com_config->tsm_fast_ctrl2_init_32mhz; + XCVR_TSM->RECYCLE_COUNT = com_config->recycle_count_init_32mhz; + XCVR_TSM->TIMING14 = com_config->tsm_timing_14_init_32mhz; + XCVR_TSM->TIMING16 = com_config->tsm_timing_16_init_32mhz; + XCVR_TSM->TIMING25 = com_config->tsm_timing_25_init_32mhz; + XCVR_TSM->TIMING27 = com_config->tsm_timing_27_init_32mhz; + XCVR_TSM->TIMING28 = com_config->tsm_timing_28_init_32mhz; + XCVR_TSM->TIMING29 = com_config->tsm_timing_29_init_32mhz; + XCVR_TSM->TIMING30 = com_config->tsm_timing_30_init_32mhz; + XCVR_TSM->TIMING31 = com_config->tsm_timing_31_init_32mhz; + XCVR_TSM->TIMING32 = com_config->tsm_timing_32_init_32mhz; + XCVR_TSM->TIMING33 = com_config->tsm_timing_33_init_32mhz; + XCVR_TSM->TIMING36 = com_config->tsm_timing_36_init_32mhz; + XCVR_TSM->TIMING37 = com_config->tsm_timing_37_init_32mhz; + XCVR_TSM->TIMING39 = com_config->tsm_timing_39_init_32mhz; + XCVR_TSM->TIMING40 = com_config->tsm_timing_40_init_32mhz; + XCVR_TSM->TIMING41 = com_config->tsm_timing_41_init_32mhz; + XCVR_TSM->TIMING52 = com_config->tsm_timing_52_init_32mhz; + XCVR_TSM->TIMING54 = com_config->tsm_timing_54_init_32mhz; + XCVR_TSM->TIMING55 = com_config->tsm_timing_55_init_32mhz; + XCVR_TSM->TIMING56 = com_config->tsm_timing_56_init_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + /* TSM timings independent of clock frequency */ + XCVR_TSM->TIMING00 = com_config->tsm_timing_00_init; + XCVR_TSM->TIMING01 = com_config->tsm_timing_01_init; + XCVR_TSM->TIMING02 = com_config->tsm_timing_02_init; + XCVR_TSM->TIMING03 = com_config->tsm_timing_03_init; + XCVR_TSM->TIMING04 = com_config->tsm_timing_04_init; + XCVR_TSM->TIMING05 = com_config->tsm_timing_05_init; + XCVR_TSM->TIMING06 = com_config->tsm_timing_06_init; + XCVR_TSM->TIMING07 = com_config->tsm_timing_07_init; + XCVR_TSM->TIMING08 = com_config->tsm_timing_08_init; + XCVR_TSM->TIMING09 = com_config->tsm_timing_09_init; + XCVR_TSM->TIMING10 = com_config->tsm_timing_10_init; + XCVR_TSM->TIMING11 = com_config->tsm_timing_11_init; + XCVR_TSM->TIMING12 = com_config->tsm_timing_12_init; + XCVR_TSM->TIMING13 = com_config->tsm_timing_13_init; + XCVR_TSM->TIMING15 = com_config->tsm_timing_15_init; + XCVR_TSM->TIMING17 = com_config->tsm_timing_17_init; + XCVR_TSM->TIMING18 = com_config->tsm_timing_18_init; + XCVR_TSM->TIMING19 = com_config->tsm_timing_19_init; + XCVR_TSM->TIMING20 = com_config->tsm_timing_20_init; + XCVR_TSM->TIMING21 = com_config->tsm_timing_21_init; + XCVR_TSM->TIMING22 = com_config->tsm_timing_22_init; + XCVR_TSM->TIMING23 = com_config->tsm_timing_23_init; + XCVR_TSM->TIMING24 = com_config->tsm_timing_24_init; + XCVR_TSM->TIMING26 = com_config->tsm_timing_26_init; + XCVR_TSM->TIMING34 = com_config->tsm_timing_34_init; + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init; + XCVR_TSM->TIMING38 = com_config->tsm_timing_38_init; + XCVR_TSM->TIMING51 = com_config->tsm_timing_51_init; + XCVR_TSM->TIMING53 = com_config->tsm_timing_53_init; + XCVR_TSM->TIMING57 = com_config->tsm_timing_57_init; + XCVR_TSM->TIMING58 = com_config->tsm_timing_58_init; + +#if RF_OSC_26MHZ == 1 + { + XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU_26MHZ) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD_26MHZ); + } +#else + { + XCVR_TSM->END_OF_SEQ = XCVR_TSM_END_OF_SEQ_END_OF_TX_WU(END_OF_TX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_TX_WD(END_OF_TX_WD) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU(END_OF_RX_WU) | + XCVR_TSM_END_OF_SEQ_END_OF_RX_WD(END_OF_RX_WD); + } +#endif /* RF_OSC_26MHZ == 1 */ + + XCVR_TSM->PA_RAMP_TBL0 = com_config->pa_ramp_tbl_0_init; + XCVR_TSM->PA_RAMP_TBL1 = com_config->pa_ramp_tbl_1_init; + +#if RADIO_IS_GEN_3P0 + XCVR_TSM->PA_RAMP_TBL2 = com_config->pa_ramp_tbl_2_init; + XCVR_TSM->PA_RAMP_TBL3 = com_config->pa_ramp_tbl_3_init; + + /* Apply PA_RAMP_TIME == 4usec adjustments to TX_WD signals */ +#if (PA_RAMP_TIME == 4) + XCVR_TSM->TIMING00 += B1(2); /* (bb_ldo_hf_en) */ + XCVR_TSM->TIMING01 += B1(2); /* (bb_ldo_adcdac_en) */ + XCVR_TSM->TIMING03 += B1(2); /* (bb_ldo_pd_en) */ + XCVR_TSM->TIMING04 += B1(2); /* (bb_ldo_fdbk_en) */ + XCVR_TSM->TIMING05 += B1(2); /* (bb_ldo_vcolo_en) */ + XCVR_TSM->TIMING06 += B1(2); /* (bb_ldo_vtref_en) */ + XCVR_TSM->TIMING10 += B1(2); /* (bb_xtal_pll_ref_clk_en) */ + XCVR_TSM->TIMING11 += B1(2); /* (bb_xtal_dac_ref_clk_en) */ + XCVR_TSM->TIMING15 += B1(2); /* (sy_vco_en) */ + XCVR_TSM->TIMING17 += B1(2); /* (sy_lo_tx_buf_en) */ + XCVR_TSM->TIMING18 += B1(2); /* (sy_divn_en) */ + XCVR_TSM->TIMING20 += B1(2); /* (sy_pd_en) */ + XCVR_TSM->TIMING21 += B1(2); /* (sy_lo_divn_en) */ + XCVR_TSM->TIMING23 += B1(2); /* (sy_lo_tx_en) */ + XCVR_TSM->TIMING26 += B1(2); /* (tx_pa_en) */ + XCVR_TSM->TIMING34 += B1(2); /* (pll_dig_en) */ + XCVR_TSM->TIMING35 += B1(2); /* (tx_dig_en) */ + XCVR_TSM->TIMING38 += B1(2); /* (sigma_delta_en) */ + XCVR_TSM->TIMING58 += B1(2) /* (tx_hpm_dac_en) */ + temp = XCVR_TSM->TIMING14; + temp &= 0xFFFF0000; + temp |= B0(END_OF_TX_WU - 4) | B1(END_OF_TX_WU + 1); /* (sy_pd_cycle_slip_ld_ft_en) */ + XCVR_TSM->TIMING14 = temp; +#endif /* (PA_RAMP_TIME == 4) */ +#endif /* RADIO_IS_GEN_3P0 */ + } + +#if RADIO_IS_GEN_3P0 + if (mode_config->radio_mode == ZIGBEE_MODE) + { + temp = XCVR_TSM->TIMING35; + temp &= ~(B0(0xFF)); + if (DATA_PADDING_EN == 1) + { + temp |= B0(END_OF_TX_WU - 2 - 8); /* Adjust for data padding time */ + } + else + { + temp |= B0(END_OF_TX_WU - 2); /* No data padding adjustment */ + } + XCVR_TSM->TIMING35 = temp; + } +#else + + if ((mode_datarate_config->radio_mode == MSK) && ((mode_datarate_config->data_rate == DR_500KBPS) || (mode_datarate_config->data_rate == DR_250KBPS))) + { + /* Apply a specific value of TX_DIG_EN which assumes no DATA PADDING */ + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | B0(TX_DIG_EN_ASSERT_MSK500); /* LSbyte is mode specific */ + } + else + { + XCVR_TSM->TIMING35 = com_config->tsm_timing_35_init | mode_config->tsm_timing_35_init; /* LSbyte is mode specific, other bytes are common */ + } +#endif /* RADIO_IS_GEN_3P0 */ + + /*******************************************************************************/ + /* XCVR_TX_DIG configs */ + /*******************************************************************************/ +#if RF_OSC_26MHZ == 1 + { + XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_26mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ + XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_26mhz; + XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_26mhz; + } +#else + { + XCVR_TX_DIG->FSK_SCALE = mode_datarate_config->tx_fsk_scale_32mhz; /* Applies only to 802.15.4 & MSK but won't harm other protocols */ + XCVR_TX_DIG->GFSK_COEFF1 = mode_config->tx_gfsk_coeff1_32mhz; + XCVR_TX_DIG->GFSK_COEFF2 = mode_config->tx_gfsk_coeff2_32mhz; + } +#endif /* RF_OSC_26MHZ == 1 */ + + if (first_init) + { + XCVR_TX_DIG->CTRL = com_config->tx_ctrl; + XCVR_TX_DIG->DATA_PADDING = com_config->tx_data_padding; + XCVR_TX_DIG->DFT_PATTERN = com_config->tx_dft_pattern; + +#if !RADIO_IS_GEN_2P1 + XCVR_TX_DIG->RF_DFT_BIST_1 = com_config->rf_dft_bist_1; + XCVR_TX_DIG->RF_DFT_BIST_2 = com_config->rf_dft_bist_2; +#endif /* !RADIO_IS_GEN_2P1 */ + } + + XCVR_TX_DIG->GFSK_CTRL = mode_config->tx_gfsk_ctrl; + +#ifndef SIMULATION +#if (TRIM_BBA_DCOC_DAC_AT_INIT) + if (first_init) + { + uint32_t end_of_rx_wu = 0; + XCVR_ForceRxWu(); + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + +// if (!rx_bba_dcoc_dac_trim_shortIQ()) + if (!rx_bba_dcoc_dac_trim_DCest()) + { + config_status = gXcvrTrimFailure_c; + } + + XCVR_ForceRxWd(); + DCOC_DAC_INIT_Cal(1); + } +#endif /* TRIM_BBA_DCOC_DAC_AT_INIT */ +#endif /* ifndef SIMULATION */ + return config_status; +} + +void XCVR_Reset(void) +{ +#if RADIO_IS_GEN_3P0 +#else + RSIM->CONTROL |= RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* Assert radio software reset */ + RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset */ + RSIM->CONTROL &= ~RSIM_CONTROL_RADIO_RESET_BIT_MASK; /* De-assert radio software reset a second time per RADIO_RESET bit description */ +#endif /* RADIO_IS_GEN_3P0 */ +} + +xcvrStatus_t XCVR_ChangeMode (radio_mode_t new_radio_mode, data_rate_t new_data_rate) /* Change from one radio mode to another */ +{ + xcvrStatus_t status; + const xcvr_mode_datarate_config_t * mode_datarate_config; + const xcvr_datarate_config_t * datarate_config ; + const xcvr_mode_config_t * radio_mode_cfg; + const xcvr_common_config_t * radio_common_config; + + status = XCVR_GetDefaultConfig(new_radio_mode, new_data_rate, (void *)&radio_common_config, (void *)&radio_mode_cfg, (void *)&mode_datarate_config, (void *)&datarate_config ); + + if (status == gXcvrSuccess_c) + { + status = XCVR_Configure((const xcvr_common_config_t *)radio_common_config, + (const xcvr_mode_config_t *)radio_mode_cfg, + (const xcvr_mode_datarate_config_t *)mode_datarate_config, + (const xcvr_datarate_config_t *)datarate_config, 25, XCVR_MODE_CHANGE); + current_xcvr_config.radio_mode = new_radio_mode; + current_xcvr_config.data_rate = new_data_rate; + } + + return status; +} + +void XCVR_EnaNBRSSIMeas( uint8_t IIRnbEnable ) +{ + if (IIRnbEnable) + { + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; + } + else + { + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK; + } +} + +xcvrStatus_t XCVR_OverrideFrequency ( uint32_t freq, uint32_t refOsc ) +{ + double integer_used_in_Hz, + integer_used_in_LSB, + numerator_fraction, + numerator_in_Hz, + numerator_in_LSB, + numerator_unrounded, + real_int_and_fraction, + real_fraction, + requested_freq_in_LSB, + sdm_lsb; + uint32_t temp; + static uint32_t integer_truncated, + integer_to_use; + static int32_t numerator_rounded; + + /* Configure for Coarse Tune */ + uint32_t coarse_tune_target = freq / 1000000; + + temp = XCVR_PLL_DIG->CTUNE_CTRL; + temp &= ~XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK; + temp |= XCVR_PLL_DIG_CTUNE_CTRL_CTUNE_TARGET_MANUAL(coarse_tune_target); + XCVR_PLL_DIG->CTUNE_CTRL = temp; + + /* Calculate the Low Port values */ + sdm_lsb = refOsc / 131072.0; + + real_int_and_fraction = freq / (refOsc * 2.0); + + integer_truncated = (uint32_t) trunc(real_int_and_fraction); + + real_fraction = real_int_and_fraction - integer_truncated; + + if (real_fraction > 0.5) + { + integer_to_use = integer_truncated + 1; + } + else + { + integer_to_use = integer_truncated; + } + + numerator_fraction = real_int_and_fraction - integer_to_use; + + integer_used_in_Hz = integer_to_use * refOsc * 2; + integer_used_in_LSB = integer_used_in_Hz / sdm_lsb; + + numerator_in_Hz = numerator_fraction * refOsc * 2; + numerator_in_LSB = numerator_in_Hz / sdm_lsb; + + requested_freq_in_LSB = integer_used_in_LSB + numerator_in_LSB; + + numerator_unrounded = (requested_freq_in_LSB - integer_used_in_LSB) * 256; + + numerator_rounded = (int32_t)round(numerator_unrounded); + + /* Write the Low Port Integer and Numerator */ + temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; + temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; + temp |= (XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(integer_to_use) | + XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK); + XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; + + XCVR_PLL_DIG->LPM_SDM_CTRL2 = numerator_rounded; + + return gXcvrSuccess_c; +} + +void XCVR_RegisterPanicCb ( panic_fptr fptr ) /* Allow upper layers to provide PANIC callback */ +{ + s_PanicFunctionPtr = fptr; +} + +void XcvrPanic(XCVR_PANIC_ID_T panic_id, uint32_t panic_address) +{ + if ( s_PanicFunctionPtr != NULL) + { + s_PanicFunctionPtr(panic_id, panic_address, 0, 0); + } + else + { + uint8_t dummy; + + while(1) + { + dummy = dummy; + } + } +} + +healthStatus_t XCVR_HealthCheck ( void ) /* Allow upper layers to poll the radio health */ +{ + return (healthStatus_t)NO_ERRORS; +} + +void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control) +{ + +} + +/* Helper function to map radio mode to LL usage */ +link_layer_t map_mode_to_ll(radio_mode_t mode) +{ + link_layer_t llret; + switch (mode) + { + case BLE_MODE: + llret = BLE_LL; + break; + case ZIGBEE_MODE: + llret = ZIGBEE_LL; + break; + case ANT_MODE: + llret = ANT_LL; + break; + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + case MSK: + llret = GENFSK_LL; + break; + default: + llret = UNASSIGNED_LL; + break; + } + return llret; +} + +#if RADIO_IS_GEN_3P0 +void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address) +{ + XCVR_PHY->NTW_ADR_BSM = bsm_ntw_address; +} + +uint32_t XCVR_GetBSM_NTW_Address(void) +{ + return XCVR_PHY->NTW_ADR_BSM; +} +#endif /* RADIO_IS_GEN_3P0 */ + +/* Setup IRQ mapping to LL interrupt outputs in XCVR_CTRL */ +xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping) +{ + link_layer_t int0 = map_mode_to_ll(irq0_mapping); + link_layer_t int1 = map_mode_to_ll(irq1_mapping); + xcvrStatus_t statusret; + /* Make sure the two LL's requested aren't the same */ + if (int0 == int1) + { + statusret = gXcvrInvalidParameters_c; + } + else + { + uint32_t temp; + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~(XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK); + temp |= (XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL(int0) | XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL(int1)); + XCVR_MISC->XCVR_CTRL = temp; + statusret = gXcvrSuccess_c; + } + return statusret; +} + +/* Get current state of IRQ mapping for either radio INT0 or INT1 */ +link_layer_t XCVR_GetIRQMapping(uint8_t int_num) +{ + if (int_num == 0) + { + return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO0_IRQ_SEL_SHIFT); + } + else + { + return (link_layer_t)((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_MASK)>>XCVR_CTRL_XCVR_CTRL_RADIO1_IRQ_SEL_SHIFT); + } +} + +/* Get current state of radio mode and data rate */ +xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config) +{ + xcvrStatus_t status = gXcvrInvalidParameters_c; + if (curr_config != NULL) + { + curr_config->radio_mode = current_xcvr_config.radio_mode; + curr_config->data_rate = current_xcvr_config.data_rate; + status = gXcvrSuccess_c; + } + return status; +} + +/* Customer level trim functions */ +xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim) +{ + xcvrStatus_t status = gXcvrInvalidParameters_c; + + if ((xtalTrim & 0x80) == 0) + { + uint32_t temp; + temp = RSIM->ANA_TRIM; + temp &= ~RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK; + RSIM->ANA_TRIM = temp | RSIM_ANA_TRIM_BB_XTAL_TRIM(xtalTrim); + status = gXcvrSuccess_c; + } + return status; +} + +uint8_t XCVR_GetXtalTrim(void) +{ + uint8_t temp_xtal; + temp_xtal = ((RSIM->ANA_TRIM & RSIM_ANA_TRIM_BB_XTAL_TRIM_MASK)>>RSIM_ANA_TRIM_BB_XTAL_TRIM_SHIFT); + return temp_xtal; +} + +/* RSSI adjustment */ +xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj) +{ + XCVR_RX_DIG->RSSI_CTRL_0 &= ~XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK; + XCVR_RX_DIG->RSSI_CTRL_0 |= XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ(adj); + return gXcvrSuccess_c; +} + +int8_t XCVR_GetRssiAdjustment(void) +{ + int8_t adj; + adj = (XCVR_RX_DIG->RSSI_CTRL_0 & XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RX_DIG_RSSI_CTRL_0_RSSI_ADJ_SHIFT; + return adj; +} + +/* Radio debug functions */ +xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel) +{ + uint32_t temp; + + if (channel == 0xFF) + { + /* Clear all of the overrides and restore to LL channel control */ + temp = XCVR_PLL_DIG->CHAN_MAP; + temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ +#if RADIO_IS_GEN_3P0 + | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK +#endif /* RADIO_IS_GEN_3P0 */ + ); + + XCVR_PLL_DIG->CHAN_MAP = temp; + + /* Stop using the manual frequency setting */ + XCVR_PLL_DIG->LPM_SDM_CTRL1 &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; + + return gXcvrSuccess_c; + } + + if (channel >= 128) + { + return gXcvrInvalidParameters_c; + } + + if (useMappedChannel) + { + temp = (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK)>>XCVR_CTRL_XCVR_CTRL_PROTOCOL_SHIFT; /* Extract PROTOCOL bitfield */ + + switch (temp) + { +#if !RADIO_IS_GEN_2P1 + case 0x3: /* ANT protocol */ + ANT->CHANNEL_NUM = channel; + break; +#endif /* !RADIO_IS_GEN_2P1 */ + case 0x8: /* GENFSK protocol */ + case 0x9: /* MSK protocol */ + GENFSK->CHANNEL_NUM = channel; + break; + default: /* All other protocols */ + temp = XCVR_PLL_DIG->CHAN_MAP; + temp &= ~(XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM_MASK +#if RADIO_IS_GEN_3P0 + | XCVR_PLL_DIG_CHAN_MAP_HOP_TBL_CFG_OVRD_EN_MASK +#endif /* RADIO_IS_GEN_3P0 */ + ); + temp |= (XCVR_PLL_DIG_CHAN_MAP_CHANNEL_NUM(channel) | XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + ); + XCVR_PLL_DIG->CHAN_MAP = temp; + break; + } + } + else + { + XCVR_PLL_DIG->CHAN_MAP |= (XCVR_PLL_DIG_CHAN_MAP_BOC_MASK +#if !RADIO_IS_GEN_2P1 + | XCVR_PLL_DIG_CHAN_MAP_ZOC_MASK +#endif /* !RADIO_IS_GEN_2P1 */ + ); + + XCVR_PLL_DIG->LPM_SDM_CTRL3 = XCVR_PLL_DIG_LPM_SDM_CTRL3_LPM_DENOM(gPllDenom_c); + XCVR_PLL_DIG->LPM_SDM_CTRL2 = XCVR_PLL_DIG_LPM_SDM_CTRL2_LPM_NUM(mapTable[channel].numerator); + + temp = XCVR_PLL_DIG->LPM_SDM_CTRL1; + temp &= ~XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK; + temp |= XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG(mapTable[channel].integer); + XCVR_PLL_DIG->LPM_SDM_CTRL1 = temp; + + /* Stop using the LL channel map and use the manual frequency setting */ + XCVR_PLL_DIG->LPM_SDM_CTRL1 |= XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK; + } + + return gXcvrSuccess_c; +} + +uint32_t XCVR_GetFreq ( void ) +{ + uint32_t pll_int; + uint32_t pll_num_unsigned; + int32_t pll_num; + uint32_t pll_denom; + float freq_float; + + if (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_SDM_MAP_DISABLE_MASK) /* Not using mapped channels */ + { + pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_MASK) >> + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SHIFT; + + pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_CTRL2; + pll_denom = XCVR_PLL_DIG->LPM_SDM_CTRL3; + } + else + { + /* Using mapped channels so need to read from the _SELECTED fields to get the values being used */ + pll_int = (XCVR_PLL_DIG->LPM_SDM_CTRL1 & XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >> + XCVR_PLL_DIG_LPM_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT; + + pll_num_unsigned = XCVR_PLL_DIG->LPM_SDM_RES1; + pll_denom = XCVR_PLL_DIG->LPM_SDM_RES2; + } + + uint32_t freq = 0; + +#if RF_OSC_26MHZ == 1 + uint32_t ref_clk = 26U; +#else + uint32_t ref_clk = 32U; +#endif /* RF_OSC_26MHZ == 1 */ + + /* Check if sign bit is asserted */ + if (pll_num_unsigned & 0x04000000U) + { + /* Sign extend the numerator */ + pll_num = (~pll_num_unsigned + 1) & 0x03FFFFFFU; + + /* Calculate the frequency in MHz */ + freq_float = (ref_clk * 2 * (pll_int - ((float)pll_num / pll_denom))); + } + else + { + /* Calculate the frequency in MHz */ + pll_num = pll_num_unsigned; + freq_float = (ref_clk * 2 * (pll_int + ((float)pll_num / (float)pll_denom))); + } + + freq = (uint32_t)freq_float; + + return freq; +} + +void XCVR_ForceRxWu(void) +{ + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_RX_EN_MASK; +} + +void XCVR_ForceRxWd(void) +{ + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_RX_EN_MASK; +} + +void XCVR_ForceTxWu(void) +{ + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +void XCVR_ForceTxWd(void) +{ + XCVR_TSM->CTRL &= ~XCVR_TSM_CTRL_FORCE_TX_EN_MASK; +} + +xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol) +{ + uint32_t temp; + if ((protocol != 6) && (protocol != 7)) + { + return gXcvrInvalidParameters_c; /* Failure */ + } + + if ((rf_channel_freq < 2360) || (rf_channel_freq >2487)) + { + return gXcvrInvalidParameters_c; /* failure */ + } + + /* Set the DFT Mode */ + temp = XCVR_TX_DIG->CTRL; + temp &= ~XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK; + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(1); + XCVR_TX_DIG->CTRL = temp; + + /* Choose Protocol 6 or 7 if using the Channel Number register */ + temp = XCVR_MISC->XCVR_CTRL; + temp &= ~XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK; + temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(protocol); + XCVR_MISC->XCVR_CTRL = temp; + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(rf_channel_freq-2360,1); + + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + + return gXcvrSuccess_c; /* Success */ +} + +xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern) +{ + uint32_t temp; + uint8_t dft_mode = 0; + uint8_t dft_clk_sel = 0; + xcvrStatus_t status = gXcvrSuccess_c; + + XCVR_ChangeMode(radio_mode, data_rate); + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(channel_num, 1); + + switch (radio_mode) + { + case ZIGBEE_MODE: + dft_mode = 6; /* OQPSK configuration */ + break; + case ANT_MODE: + case BLE_MODE: + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + dft_mode = 2; /* GFSK configuration */ + break; + case MSK: + dft_mode = 4; /* MSK configuration */ + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + + if (status == gXcvrSuccess_c) /* Only attempt this pointer assignment process if prior switch() statement completed successfully */ + { + switch (data_rate) + { + case DR_1MBPS: + dft_clk_sel = 4; + break; + case DR_500KBPS: + dft_clk_sel = 3; + break; + case DR_250KBPS: + dft_clk_sel = 2; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + temp = XCVR_TX_DIG->CTRL; + temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | XCVR_TX_DIG_CTRL_LFSR_EN_MASK); + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(1) | + XCVR_TX_DIG_CTRL_LFSR_EN(0); + XCVR_TX_DIG->CTRL = temp; + + XCVR_TX_DIG->DFT_PATTERN = tx_pattern; + + if (status == gXcvrSuccess_c) + { + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + } + + return status; +} + +xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length) +{ + uint32_t temp; + uint8_t dft_mode = 0; + uint8_t dft_clk_sel = 0; + xcvrStatus_t status = gXcvrSuccess_c; + uint8_t bitrate_setting = 0xFF; + + if (lfsr_length > 5) + { + return gXcvrInvalidParameters_c; + } + + XCVR_ChangeMode(radio_mode, data_rate); + + /* Select the RF Channel, using the Channel Number register */ + XCVR_OverrideChannel(channel_num, 1); + + switch (radio_mode) + { + case ZIGBEE_MODE: + dft_mode = 7; /* OQPSK configuration */ + break; + case ANT_MODE: + case BLE_MODE: + case GFSK_BT_0p5_h_0p5: + case GFSK_BT_0p5_h_0p32: + case GFSK_BT_0p5_h_0p7: + case GFSK_BT_0p5_h_1p0: + case GFSK_BT_0p3_h_0p5: + case GFSK_BT_0p7_h_0p5: + dft_mode = 3; /* GFSK configuration */ + bitrate_setting = data_rate; + break; + case MSK: + dft_mode = 5; /* MSK configuration */ + break; + + default: + status = gXcvrInvalidParameters_c; + break; + } + + if (status == gXcvrSuccess_c) + { + switch (data_rate) + { + case DR_1MBPS: + dft_clk_sel = 4; + break; + case DR_500KBPS: + dft_clk_sel = 3; + break; + case DR_250KBPS: + dft_clk_sel = 2; + break; + default: + status = gXcvrInvalidParameters_c; + break; + } + } + + if (bitrate_setting < 4) + { + GENFSK->BITRATE = bitrate_setting; + } + + temp = XCVR_TX_DIG->CTRL; + temp &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | + XCVR_TX_DIG_CTRL_LFSR_LENGTH_MASK | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | + XCVR_TX_DIG_CTRL_LFSR_EN_MASK); + temp |= XCVR_TX_DIG_CTRL_RADIO_DFT_MODE(dft_mode) | + XCVR_TX_DIG_CTRL_LFSR_LENGTH(lfsr_length) | + XCVR_TX_DIG_CTRL_DFT_CLK_SEL(dft_clk_sel) | + XCVR_TX_DIG_CTRL_TX_DFT_EN(0) | + XCVR_TX_DIG_CTRL_LFSR_EN(1); + XCVR_TX_DIG->CTRL = temp; + + if (status == gXcvrSuccess_c) + { + /* Warm-up the Radio */ + XCVR_ForceTxWu(); + } + + return status; +} + +void XCVR_DftTxOff(void) +{ + XCVR_ForceTxWd(); + XCVR_MISC->XCVR_CTRL |= XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in LL registers */ + /* Clear the RF Channel over-ride */ + XCVR_OverrideChannel(0xFF,1); + XCVR_TX_DIG->CTRL &= ~(XCVR_TX_DIG_CTRL_RADIO_DFT_MODE_MASK | /* Clear DFT_MODE */ + XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK | /* Clear DFT_CLK_SEL */ + XCVR_TX_DIG_CTRL_TX_DFT_EN_MASK | /* Clear DFT_EN */ + XCVR_TX_DIG_CTRL_LFSR_EN_MASK);/* Clear LFSR_EN */ +} + +xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power) +{ + if (pa_power > 0x3F) + { + return gXcvrInvalidParameters_c; /* Failure */ + } + + if (pa_power != 1) + { + pa_power = pa_power & 0xFEU; /* Ensure LSbit is cleared */ + } + + XCVR_MISC->XCVR_CTRL &= ~XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK; /* Use PA_POWER in TSM registers */ + XCVR_TSM->PA_POWER = pa_power; + + return gXcvrSuccess_c; /* Success */ +} + +xcvrStatus_t XCVR_CoexistenceInit(void) +{ +#if gMWS_UseCoexistence_d + uint32_t temp = 0x00U; + uint32_t end_of_tx_wu = 0x00U; + uint32_t end_of_rx_wu = 0x00U; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + uint32_t tsm_timing47 = 0x00U; +#else /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_B) */ + uint32_t tsm_timing48 = 0x00U; +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + uint32_t tsm_timing50 = 0x00U; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + // RF_ACTIVE = ANT_B (PTC1, gpio1_trig_en) + uint32_t tsm_timing48 = 0x00U; + // RF_PRIORITY = ANT_A (PTC4, gpio0_trig_en) + uint32_t tsm_timing47 = 0x00U; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + uint16_t tsm_timing43_rx = 0x00; + uint16_t tsm_timing43_tx = 0x00; + + /* Select GPIO mode for FAD pins */ + temp = XCVR_MISC->FAD_CTRL; + temp &= ~(XCVR_CTRL_FAD_CTRL_FAD_NOT_GPIO_MASK); + XCVR_MISC->FAD_CTRL = temp; + + /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ + end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + +/***************** + * TX SEQUENCE * + *****************/ + + if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_tx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Save the TX RF_ACTIVE start time. */ + tsm_timing43_tx = end_of_tx_wu - temp; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#else + tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing50 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing48 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK); + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence. */ + tsm_timing47 = (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + +/***************** + * RX SEQUENCE * + *****************/ + + if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_rx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Save the RX RF_ACTIVE start time. */ + tsm_timing43_rx = end_of_rx_wu - temp; + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); +#else + tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ + tsm_timing50 |= ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); + +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; +#else + temp = XCVR_TSM->TIMING48; + temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing48; + XCVR_TSM->TIMING48 = temp; +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ + + temp = XCVR_TSM->TIMING50; + temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing50; + XCVR_TSM->TIMING50 = temp; + +#if (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) + GPIOC->PDDR |= 0x18; + PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#else + GPIOC->PDDR |= 0x0A; + PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[3] = (PORTC->PCR[3] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#endif /* (XCVR_COEX_RF_ACTIVE_PIN == ANT_A) */ +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ + +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set RF_ACTIVE pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence. */ + tsm_timing48 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + + /* Set PRIORITY pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start. */ + tsm_timing47 |= (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + + /* RF_ACTIVE */ + temp = XCVR_TSM->TIMING48; + temp &= ~(XCVR_TSM_TIMING48_GPIO1_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING48_GPIO1_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing48; + XCVR_TSM->TIMING48 = temp; + + /* RF_PRIORITY */ + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; + + /* Overwrite pins settings */ + GPIOC->PDDR |= 0x12; + PORTC->PCR[4] = (PORTC->PCR[4] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); + PORTC->PCR[1] = (PORTC->PCR[1] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(2); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + tsm_timing43_tx += gMWS_CoexConfirmWaitTime_d; + + if (tsm_timing43_tx > end_of_tx_wu - 1) + { + tsm_timing43_tx = end_of_tx_wu - 1; + } + + tsm_timing43_rx += gMWS_CoexConfirmWaitTime_d; + + if (tsm_timing43_rx > end_of_rx_wu - 1) + { + tsm_timing43_rx = end_of_rx_wu - 1; + } + + XCVR_TSM->TIMING43 = ((((uint32_t)(tsm_timing43_tx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_HI_MASK) | + (((uint32_t)(tsm_timing43_tx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_TX_LO_MASK) | + (((uint32_t)(tsm_timing43_rx) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_HI_MASK) | + (((uint32_t)(tsm_timing43_rx + 2) << XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_SHIFT) & XCVR_TSM_TIMING43_TSM_SPARE0_EN_RX_LO_MASK)); + + BTLE_RF->MISC_CTRL = 0x02; + + XCVR_TSM->CTRL |= XCVR_TSM_CTRL_TSM_IRQ0_EN_MASK; + + /* Save the updated registers values. */ + XCVR_CoexistenceSaveRestoreTimings(1); +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + +xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority) +{ +#if gMWS_UseCoexistence_d + uint32_t temp = 0x00U; + uint32_t end_of_tx_wu = 0x00U; + uint32_t end_of_rx_wu = 0x00U; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + uint32_t tsm_timing50 = 0x00U; +#endif +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + uint32_t tsm_timing47 = 0x00U; +#endif + + /* Read the END_OF_TX_WU and END_OF_RX_WU for XCVR */ + end_of_tx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT; + end_of_rx_wu = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> + XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + +/***************** + * RX * + *****************/ + + if (XCVR_COEX_HIGH_PRIO == rxPriority) + { + if (end_of_rx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_rx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence and clear it gMWS_CoexPrioSignalTime_d uS before RX start for high priority RX. */ + tsm_timing50 = ((((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + (((uint32_t)(end_of_rx_wu - gMWS_CoexPrioSignalTime_d) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any RX sequence */ + tsm_timing47 = (((uint32_t)(end_of_rx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + else + { + /* Low priority RX */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing50 = (((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + +/***************** + * TX * + *****************/ + if (XCVR_COEX_HIGH_PRIO == txPriority) + { + if (end_of_tx_wu < gMWS_CoexRfActiveAssertTime_d) + { + temp = end_of_tx_wu; + } + else + { + temp = gMWS_CoexRfActiveAssertTime_d; + } + + /* Set STATUS pin HIGH gMWS_CoexRfActiveAssertTime_d uS prior to any TX sequence for HIGH priority TX. */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing50 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + tsm_timing47 |= (((uint32_t)(end_of_tx_wu - temp) << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + else + { +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + /* Set STATUS pin HIGH at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ + tsm_timing50 |= (((uint32_t)(end_of_tx_wu) << XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + /* Set STATUS pin LOW at END_OF_TX_WU prior to any TX sequence for LOW priority TX. */ + tsm_timing47 = (((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK) | + ((0xFFU << XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_SHIFT) & + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK)); +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + } + +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + temp = XCVR_TSM->TIMING50; + temp &= ~(XCVR_TSM_TIMING50_GPIO3_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING50_GPIO3_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing50; + XCVR_TSM->TIMING50 = temp; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) */ +#if (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) + temp = XCVR_TSM->TIMING47; + temp &= ~(XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_HI_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_TX_LO_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_HI_MASK | + XCVR_TSM_TIMING47_GPIO0_TRIG_EN_RX_LO_MASK); + temp |= tsm_timing47; + XCVR_TSM->TIMING47 = temp; +#endif /* (gMWS_Coex_Model_d == gMWS_Coex_Prio_Only_d) */ + + /* Save the updated registers values. */ + XCVR_CoexistenceSaveRestoreTimings(1); +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + +xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings) +{ +#if gMWS_UseCoexistence_d + static uint32_t tsm_ovrd0_saved = 0x00; + static uint32_t tsm_ovrd1_saved = 0x00; + static uint32_t tsm_ovrd2_saved = 0x00; + static uint32_t tsm_ovrd3_saved = 0x00; + static uint32_t tsm_timing47_saved = 0x00; + static uint32_t tsm_timing48_saved = 0x00; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + static uint32_t tsm_timing49_saved = 0x00; + static uint32_t tsm_timing50_saved = 0x00; +#endif + + if (saveTimings == 0) + { + /* Restore registers values. */ + XCVR_TSM->OVRD0 = tsm_ovrd0_saved; + XCVR_TSM->OVRD1 = tsm_ovrd1_saved; + XCVR_TSM->OVRD2 = tsm_ovrd2_saved; + XCVR_TSM->OVRD3 = tsm_ovrd3_saved; + + XCVR_TSM->TIMING47 = tsm_timing47_saved; + XCVR_TSM->TIMING48 = tsm_timing48_saved; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + XCVR_TSM->TIMING49 = tsm_timing49_saved; + XCVR_TSM->TIMING50 = tsm_timing50_saved; +#endif + } + else + { + /* Save registers values. */ + tsm_ovrd0_saved = XCVR_TSM->OVRD0; + tsm_ovrd1_saved = XCVR_TSM->OVRD1; + tsm_ovrd2_saved = XCVR_TSM->OVRD2; + tsm_ovrd3_saved = XCVR_TSM->OVRD3; + tsm_timing47_saved = XCVR_TSM->TIMING47; + tsm_timing48_saved = XCVR_TSM->TIMING48; +#if (gMWS_Coex_Model_d == gMWS_Coex_Status_Prio_d) + tsm_timing49_saved = XCVR_TSM->TIMING49; + tsm_timing50_saved = XCVR_TSM->TIMING50; +#endif + } +#endif /* gMWS_UseCoexistence_d */ + + return gXcvrSuccess_c; +} + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.h b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.h new file mode 100644 index 000000000..9403f81df --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr.h @@ -0,0 +1,1236 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _FSL_XCVR_H_ +/* clang-format off */ +#define _FSL_XCVR_H_ +/* clang-format on */ + +#include "fsl_device_registers.h" +#include "fsl_xcvr_trim.h" + +#if gMWS_UseCoexistence_d +#include "MWS.h" +#endif /* gMWS_UseCoexistence_d */ +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* KW4xZ/KW3xZ/KW2xZ Radio type */ +#define RADIO_IS_GEN_2P0 (1) + +/* Default RF OSC definition. Allows for compile time clock frequency definition */ +#ifdef CLOCK_MAIN + +#else +#if RF_OSC_26MHZ == 1 +#define CLOCK_MAIN (EXT_CLK_26_MHZ) /* See ext_clock_config_t for this value */ +#else +#define CLOCK_MAIN (EXT_CLK_32_MHZ) /* See ext_clock_config_t for this value */ +#endif /* RF_OSC_26MHZ == 1 */ +#endif /* CLOCK_MAIN */ + +#define TBD_ZERO (0) +#define FSL_XCVR_DRIVER_VERSION (MAKE_VERSION(0, 1, 0)) + +#define B0(x) (((uint32_t)(((uint32_t)(x)) << 0)) & 0xFFU) +#define B1(x) (((uint32_t)(((uint32_t)(x)) << 8)) & 0xFF00U) +#define B2(x) (((uint32_t)(((uint32_t)(x)) << 16)) & 0xFF0000U) +#define B3(x) (((uint32_t)(((uint32_t)(x)) << 24)) & 0xFF000000U) + +#define USE_DEFAULT_PRE_REF (0) +#define TRIM_BBA_DCOC_DAC_AT_INIT (1) +#define PRESLOW_ENA (1) + +/* GEN3 TSM defines */ +#if RADIO_IS_GEN_3P0 + +/* TSM timings initializations for Gen3 radio */ +/* NOTE: These timings are stored in 32MHz or 26MHz "baseline" settings, selected by conditional compile below */ +/* The init structures for 32Mhz and 26MHz are made identical to allow the same code in fsl_xcvr.c to apply the */ +/* settings for all radio generations. The Gen2 radio init value storage had a different structure so this preserves compatibility */ +#if RF_OSC_26MHZ == 1 +#define TSM_TIMING00init (0x6d006f00U) /* (bb_ldo_hf_en) */ +#define TSM_TIMING01init (0x6d006f00U) /* (bb_ldo_adcdac_en) */ +#define TSM_TIMING02init (0x6d00ffffU) /* (bb_ldo_bba_en) */ +#define TSM_TIMING03init (0x6d006f00U) /* (bb_ldo_pd_en) */ +#define TSM_TIMING04init (0x6d006f00U) /* (bb_ldo_fdbk_en) */ +#define TSM_TIMING05init (0x6d006f00U) /* (bb_ldo_vcolo_en) */ +#define TSM_TIMING06init (0x6d006f00U) /* (bb_ldo_vtref_en) */ +#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ +#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ +#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ +#define TSM_TIMING10init (0x6d036f03U) /* (bb_xtal_pll_ref_clk_en) */ +#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ +#define TSM_TIMING12init (0x6d03ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ +#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ +#define TSM_TIMING14init (0x6d356863U) /* (sy_pd_cycle_slip_ld_ft_en) */ +#define TSM_TIMING15init (0x6d036f03U) /* (sy_vco_en) */ +#define TSM_TIMING16init (0x6d20ffffU) /* (sy_lo_rx_buf_en) */ +#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ +#define TSM_TIMING18init (0x6d056f05U) /* (sy_divn_en) */ +#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ +#define TSM_TIMING20init (0x6d036f03U) /* (sy_pd_en) */ +#define TSM_TIMING21init (0x6d046f04U) /* (sy_lo_divn_en) */ +#define TSM_TIMING22init (0x6d04ffffU) /* (sy_lo_rx_en) */ +#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ +#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ +#define TSM_TIMING25init (0x6d21ffffU) /* (rx_lna_mixer_en) */ +#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ +#define TSM_TIMING27init (0x6d24ffffU) /* (rx_adc_i_q_en) */ +#define TSM_TIMING28init (0x2524ffffU) /* (rx_adc_reset_en) */ +#define TSM_TIMING29init (0x6d22ffffU) /* (rx_bba_i_q_en) */ +#define TSM_TIMING30init (0x6d24ffffU) /* (rx_bba_pdet_en) */ +#define TSM_TIMING31init (0x6d23ffffU) /* (rx_bba_tza_dcoc_en) */ +#define TSM_TIMING32init (0x6d21ffffU) /* (rx_tza_i_q_en) */ +#define TSM_TIMING33init (0x6d24ffffU) /* (rx_tza_pdet_en) */ +#define TSM_TIMING34init (0x6d076f07U) /* (pll_dig_en) */ +#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ +#define TSM_TIMING36init (0x6d6affffU) /* (rx_dig_en) */ +#define TSM_TIMING37init (0x6b6affffU) /* (rx_init) */ +#define TSM_TIMING38init (0x6d0e6f42U) /* (sigma_delta_en) */ +#define TSM_TIMING39init (0x6d6affffU) /* (rx_phy_en) */ +#define TSM_TIMING40init (0x6d2affffU) /* (dcoc_en) */ +#define TSM_TIMING41init (0x2b2affffU) /* (dcoc_init) */ +#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ +#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ +#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ +#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ +#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ +#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ +#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ +#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ +#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ +#define TSM_TIMING51init (0x6d03ffffU) /* (rxtx_auxpll_bias_en) */ +#define TSM_TIMING52init (0x1b06ffffU) /* (rxtx_auxpll_fcal_en) */ +#define TSM_TIMING53init (0x6d03ffffU) /* (rxtx_auxpll_lf_pd_en) */ +#define TSM_TIMING54init (0x1b03ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ +#define TSM_TIMING55init (0x6d24ffffU) /* (rxtx_auxpll_adc_buf_en) */ +#define TSM_TIMING56init (0x6d24ffffU) /* (rxtx_auxpll_dig_buf_en) */ +#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ +#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ +#define END_OF_SEQinit (0x6d6c6f67U) /* */ +#define TX_RX_ON_DELinit (0x00008a86U) /* */ +#define TX_RX_SYNTH_init (0x00002318U) /* */ +#else +#define TSM_TIMING00init (0x69006f00U) /* (bb_ldo_hf_en) */ +#define TSM_TIMING01init (0x69006f00U) /* (bb_ldo_adcdac_en) */ +#define TSM_TIMING02init (0x6900ffffU) /* (bb_ldo_bba_en) */ +#define TSM_TIMING03init (0x69006f00U) /* (bb_ldo_pd_en) */ +#define TSM_TIMING04init (0x69006f00U) /* (bb_ldo_fdbk_en) */ +#define TSM_TIMING05init (0x69006f00U) /* (bb_ldo_vcolo_en) */ +#define TSM_TIMING06init (0x69006f00U) /* (bb_ldo_vtref_en) */ +#define TSM_TIMING07init (0x05000500U) /* (bb_ldo_fdbk_bleed_en) */ +#define TSM_TIMING08init (0x03000300U) /* (bb_ldo_vcolo_bleed_en) */ +#define TSM_TIMING09init (0x03000300U) /* (bb_ldo_vcolo_fastcharge_en) */ +#define TSM_TIMING10init (0x69036f03U) /* (bb_xtal_pll_ref_clk_en) */ +#define TSM_TIMING11init (0xffff6f03U) /* (bb_xtal_dac_ref_clk_en) */ +#define TSM_TIMING12init (0x6903ffffU) /* (rxtx_auxpll_vco_ref_clk_en) */ +#define TSM_TIMING13init (0x18004c00U) /* (sy_vco_autotune_en) */ +#define TSM_TIMING14init (0x69316863U) /* (sy_pd_cycle_slip_ld_ft_en) */ +#define TSM_TIMING15init (0x69036f03U) /* (sy_vco_en) */ +#define TSM_TIMING16init (0x691cffffU) /* (sy_lo_rx_buf_en) */ +#define TSM_TIMING17init (0xffff6f58U) /* (sy_lo_tx_buf_en) */ +#define TSM_TIMING18init (0x69056f05U) /* (sy_divn_en) */ +#define TSM_TIMING19init (0x18034c03U) /* (sy_pd_filter_charge_en) */ +#define TSM_TIMING20init (0x69036f03U) /* (sy_pd_en) */ +#define TSM_TIMING21init (0x69046f04U) /* (sy_lo_divn_en) */ +#define TSM_TIMING22init (0x6904ffffU) /* (sy_lo_rx_en) */ +#define TSM_TIMING23init (0xffff6f04U) /* (sy_lo_tx_en) */ +#define TSM_TIMING24init (0x18004c00U) /* (sy_divn_cal_en) */ +#define TSM_TIMING25init (0x691dffffU) /* (rx_lna_mixer_en) */ +#define TSM_TIMING26init (0xffff6e58U) /* (tx_pa_en) */ +#define TSM_TIMING27init (0x6920ffffU) /* (rx_adc_i_q_en) */ +#define TSM_TIMING28init (0x2120ffffU) /* (rx_adc_reset_en) */ +#define TSM_TIMING29init (0x691effffU) /* (rx_bba_i_q_en) */ +#define TSM_TIMING30init (0x6920ffffU) /* (rx_bba_pdet_en) */ +#define TSM_TIMING31init (0x691fffffU) /* (rx_bba_tza_dcoc_en) */ +#define TSM_TIMING32init (0x691dffffU) /* (rx_tza_i_q_en) */ +#define TSM_TIMING33init (0x6920ffffU) /* (rx_tza_pdet_en) */ +#define TSM_TIMING34init (0x69076f07U) /* (pll_dig_en) */ +#define TSM_TIMING35init (0xffff6f5fU) /* (tx_dig_en) */ +#define TSM_TIMING36init (0x6966ffffU) /* (rx_dig_en) */ +#define TSM_TIMING37init (0x6766ffffU) /* (rx_init) */ +#define TSM_TIMING38init (0x690e6f42U) /* (sigma_delta_en) */ +#define TSM_TIMING39init (0x6966ffffU) /* (rx_phy_en) */ +#define TSM_TIMING40init (0x6926ffffU) /* (dcoc_en) */ +#define TSM_TIMING41init (0x2726ffffU) /* (dcoc_init) */ +#define TSM_TIMING42init (0xffffffffU) /* (sar_adc_trig_en) */ +#define TSM_TIMING43init (0xffffffffU) /* (tsm_spare0_en) */ +#define TSM_TIMING44init (0xffffffffU) /* (tsm_spare1_en) */ +#define TSM_TIMING45init (0xffffffffU) /* (tsm_spare2_en) */ +#define TSM_TIMING46init (0xffffffffU) /* (tsm_spare3_en) */ +#define TSM_TIMING47init (0xffffffffU) /* (gpio0_trig_en) */ +#define TSM_TIMING48init (0xffffffffU) /* (gpio1_trig_en) */ +#define TSM_TIMING49init (0xffffffffU) /* (gpio2_trig_en) */ +#define TSM_TIMING50init (0xffffffffU) /* (gpio3_trig_en) */ +#define TSM_TIMING51init (0x6903ffffU) /* (rxtx_auxpll_bias_en) */ +#define TSM_TIMING52init (0x1706ffffU) /* (rxtx_auxpll_fcal_en) */ +#define TSM_TIMING53init (0x6903ffffU) /* (rxtx_auxpll_lf_pd_en) */ +#define TSM_TIMING54init (0x1703ffffU) /* (rxtx_auxpll_pd_lf_filter_charge_en) */ +#define TSM_TIMING55init (0x6920ffffU) /* (rxtx_auxpll_adc_buf_en) */ +#define TSM_TIMING56init (0x6920ffffU) /* (rxtx_auxpll_dig_buf_en) */ +#define TSM_TIMING57init (0x1a03ffffU) /* (rxtx_rccal_en) */ +#define TSM_TIMING58init (0xffff6f03U) /* (tx_hpm_dac_en) */ +#define END_OF_SEQinit (0x69686f67U) /* */ +#define TX_RX_ON_DELinit (0x00008a86U) /* */ +#define TX_RX_SYNTH_init (0x00002318U) /* */ +#endif /* RF_OSC_26MHZ == 1 */ + +#define AUX_PLL_DELAY (0) +/* TSM bitfield shift and value definitions */ +#define TX_DIG_EN_ASSERT (95) /* Assertion time for TX_DIG_EN, used in mode specific settings */ +#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ +/* EDIT THIS LINE TO CONTROL PA_RAMP! */ +#define PA_RAMP_TIME (2) /* Only allowable values are [0, 1, 2, or 4] in Gen3 */ +#define PA_RAMP_SEL_0US (0) +#define PA_RAMP_SEL_1US (1) +#define PA_RAMP_SEL_2US (2) +#define PA_RAMP_SEL_4US (3) +#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4)) +#error "Invalid value for PA_RAMP_TIME macro" +#endif /* Error check of PA RAMP TIME */ + +#define ADD_FOR_26MHZ (4) +#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ +/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ +#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) + #if (PA_RAMP_TIME == 0) + #define PA_RAMP_SEL PA_RAMP_SEL_0US + #define DATA_PADDING_EN (0) + #else + #define DATA_PADDING_EN (1) + #if (PA_RAMP_TIME == 1) + #define PA_RAMP_SEL PA_RAMP_SEL_1US + #else + #define PA_RAMP_SEL PA_RAMP_SEL_2US + #endif /* (PA_RAMP_TIME == 1) */ + #endif /* (PA_RAMP_TIME == 0) */ +#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 1) || (PA_RAMP_TIME == 2)) */ + #if (PA_RAMP_TIME == 4) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) + #define PA_RAMP_SEL PA_RAMP_SEL_4US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME == 4) */ + #error "Invalid value for PA_RAMP_TIME macro" + #endif /* (PA_RAMP_TIME == 4) */ +#endif/* (PA_RAMP_TIME == 4) */ + +#define END_OF_RX_WU (104 + AUX_PLL_DELAY) + +#if RF_OSC_26MHZ == 1 +#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ +#else +#define END_OF_RX_WD (END_OF_RX_WU + 1) +#endif /* RF_OSC_26MHZ == 1 */ + +#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) +#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) + +/* PA Bias Table - Gen3 version */ +#define PA_RAMP_0 0x1 +#define PA_RAMP_1 0x2 +#define PA_RAMP_2 0x4 +#define PA_RAMP_3 0x6 +#define PA_RAMP_4 0x8 +#define PA_RAMP_5 0xc +#define PA_RAMP_6 0x10 +#define PA_RAMP_7 0x14 +#define PA_RAMP_8 0x18 +#define PA_RAMP_9 0x1c +#define PA_RAMP_10 0x22 +#define PA_RAMP_11 0x28 +#define PA_RAMP_12 0x2c +#define PA_RAMP_13 0x30 +#define PA_RAMP_14 0x36 +#define PA_RAMP_15 0x3c + +#else /* Gen2 TSM definitions */ +/* GEN2 TSM defines */ +#define AUX_PLL_DELAY (0) +/* TSM bitfield shift and value definitions */ +#define TX_DIG_EN_ASSERT (95) +#define ZGBE_TX_DIG_EN_ASSERT (TX_DIG_EN_ASSERT - 1) /* Zigbee TX_DIG_EN must assert 1 tick sooner, see adjustment below based on data padding */ +/* EDIT THIS LINE TO CONTROL PA_RAMP! */ +#define PA_RAMP_TIME (2) /* Only allowable values are [0, 2, 4, or 8] for PA RAMP times in Gen2.0 */ +#define PA_RAMP_SEL_0US (0) +#define PA_RAMP_SEL_2US (1) +#define PA_RAMP_SEL_4US (2) +#define PA_RAMP_SEL_8US (3) + +#if !((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2) || (PA_RAMP_TIME == 4) || (PA_RAMP_TIME == 8)) +#error "Invalid value for PA_RAMP_TIME macro" +#endif /* Error check of PA RAMP TIME */ +#define ADD_FOR_26MHZ (4) +#define END_OF_TX_WU_NORAMP (103) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +#define END_OF_TX_WD_NORAMP (111) /* NOTE: NORAMP and 2us ramp time behaviors are identical for TX WU and WD */ +/* Redefine the values of END_OF_TX_WU and END_OF_TX_WD based on whether DATA PADDING is enabled and the selection of ramp time */ +/* These two constants are then used on both common configuration and mode specific configuration files to define the TSM timing values */ +#if ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP) + #define TX_SYNTH_DELAY_ADJ (0) + #define PD_CYCLE_SLIP_TX_HI_ADJ (0) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-5) /* Only applies to Zigbee mode */ + #if (PA_RAMP_TIME == 0) + #define PA_RAMP_SEL PA_RAMP_SEL_0US + #define DATA_PADDING_EN (0) + #define TX_DIG_EN_TX_HI_ADJ (-2) + #else + #define DATA_PADDING_EN (1) + #define TX_DIG_EN_TX_HI_ADJ (0) + #define PA_RAMP_SEL PA_RAMP_SEL_2US + #endif /* (PA_RAMP_TIME == 0) */ +#else /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ + #if (PA_RAMP_TIME == 4) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 2) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 4) + #define TX_SYNTH_DELAY_ADJ (2) + #define PD_CYCLE_SLIP_TX_HI_ADJ (2) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define TX_DIG_EN_TX_HI_ADJ (0) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (-3) /* Only applies to Zigbee mode */ + #define PA_RAMP_SEL PA_RAMP_SEL_4US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME==4) */ + #if ((PA_RAMP_TIME == 8) && (!RADIO_IS_GEN_3P0)) + #define END_OF_TX_WU (END_OF_TX_WU_NORAMP + 6) + #define END_OF_TX_WD (END_OF_TX_WD_NORAMP + 12) + #define TX_SYNTH_DELAY_ADJ (6) + #define PD_CYCLE_SLIP_TX_HI_ADJ (6) + #define PD_CYCLE_SLIP_TX_LO_ADJ (1) + #define TX_DIG_EN_TX_HI_ADJ (4) + #define ZGBE_TX_DIG_EN_TX_HI_ADJ (1) /* Only applies to Zigbee mode */ + #define PA_RAMP_SEL PA_RAMP_SEL_8US + #define DATA_PADDING_EN (1) + #else /* (PA_RAMP_TIME == 8) */ + #error "Invalid value for PA_RAMP_TIME macro" + #endif /* (PA_RAMP_TIME == 8) */ + #endif/* (PA_RAMP_TIME == 4) */ +#endif /* ((PA_RAMP_TIME == 0) || (PA_RAMP_TIME == 2)) */ + +#define TX_DIG_EN_ASSERT_MSK500 (END_OF_TX_WU - 3) + +#define END_OF_RX_WU (104 + AUX_PLL_DELAY) +#if RF_OSC_26MHZ == 1 +#define END_OF_RX_WD (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) /* Need to handle normal signals extending when 26MHZ warmdown is extended */ +#else +#define END_OF_RX_WD (END_OF_RX_WU + 1) +#endif /* RF_OSC_26MHZ == 1 */ +#define END_OF_RX_WU_26MHZ (END_OF_RX_WU + ADD_FOR_26MHZ) +#define END_OF_RX_WD_26MHZ (END_OF_RX_WU + 1 + ADD_FOR_26MHZ) + +/* PA Bias Table */ +#define PA_RAMP_0 0x1 +#define PA_RAMP_1 0x2 +#define PA_RAMP_2 0x4 +#define PA_RAMP_3 0x8 +#define PA_RAMP_4 0xe +#define PA_RAMP_5 0x16 +#define PA_RAMP_6 0x22 +#define PA_RAMP_7 0x2e + +/* BLE LL timing definitions */ +#define TX_ON_DELAY (0x85) /* Adjusted TX_ON_DELAY to make turnaround time 150usec */ +#define RX_ON_DELAY (29 + END_OF_RX_WU) +#define RX_ON_DELAY_26MHZ (29 + END_OF_RX_WU_26MHZ) +#define TX_RX_ON_DELAY_VAL (TX_ON_DELAY << 8 | RX_ON_DELAY) +#define TX_RX_ON_DELAY_VAL_26MHZ (TX_ON_DELAY << 8 | RX_ON_DELAY_26MHZ) +#define TX_SYNTH_DELAY (TX_ON_DELAY - END_OF_TX_WU - TX_SYNTH_DELAY_ADJ) /* Adjustment to TX_SYNTH_DELAY due to DATA_PADDING */ +#define RX_SYNTH_DELAY (0x18) +#define TX_RX_SYNTH_DELAY_VAL (TX_SYNTH_DELAY << 8 | RX_SYNTH_DELAY) + +/* PHY reference waveform assembly */ +#define RW0PS(loc, val) (((val) & 0x1F) << ((loc) * 5)) /* Ref Word 0 - loc is the phase info symbol number, val is the value of the phase info */ +#define RW1PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 32)) /* Ref Word 1 - loc is the phase info symbol number, val is the value of the phase info */ +#define RW2PS(loc, val) (((val) & 0x1F) << (((loc) * 5) - 64)) /* Ref Word 2 - loc is the phase info symbol number, val is the value of the phase info */ +#endif /* RADIO_IS_GEN_3P0 */ + +/*! @brief Error codes for the XCVR driver. */ +typedef enum _xcvrStatus +{ + gXcvrSuccess_c = 0, + gXcvrInvalidParameters_c, + gXcvrUnsupportedOperation_c, + gXcvrTrimFailure_c +} xcvrStatus_t; + +/*! @brief Health status returned from PHY upon status check function return. */ +typedef enum _healthStatus +{ + NO_ERRORS = 0, + PLL_CTUNE_FAIL = 1, + PLL_CYCLE_SLIP_FAIL = 2, + PLL_FREQ_TARG_FAIL = 4, + PLL_TSM_ABORT_FAIL = 8, +} healthStatus_t; + +/*! @brief Health status returned from PHY upon status check function return. */ +typedef enum _ext_clock_config +{ + EXT_CLK_32_MHZ = 0, + EXT_CLK_26_MHZ = 1, +} ext_clock_config_t; + +/*! @brief Radio operating mode setting types. */ +typedef enum _radio_mode +{ + BLE_MODE = 0, + ZIGBEE_MODE = 1, + ANT_MODE = 2, + + /* BT=0.5, h=** */ + GFSK_BT_0p5_h_0p5 = 3, /* < BT=0.5, h=0.5 [BLE at 1MBPS data rate; CS4 at 250KBPS data rate] */ + GFSK_BT_0p5_h_0p32 = 4, /* < BT=0.5, h=0.32*/ + GFSK_BT_0p5_h_0p7 = 5, /* < BT=0.5, h=0.7 [ CS1 at 500KBPS data rate] */ + GFSK_BT_0p5_h_1p0 = 6, /* < BT=0.5, h=1.0 [ CS4 at 250KBPS data rate] */ + + /* BT=** h=0.5 */ + GFSK_BT_0p3_h_0p5 = 7, /* < BT=0.3, h=0.5 [ CS2 at 1MBPS data rate] */ + GFSK_BT_0p7_h_0p5 = 8, /* < BT=0.7, h=0.5 */ + + MSK = 9, + NUM_RADIO_MODES = 10, +} radio_mode_t; + +/*! @brief Link layer types. */ +typedef enum _link_layer +{ + BLE_LL = 0, /* Must match bit assignment in RADIO1_IRQ_SEL */ + ZIGBEE_LL = 1, /* Must match bit assignment in RADIO1_IRQ_SEL */ + ANT_LL = 2, /* Must match bit assignment in RADIO1_IRQ_SEL */ + GENFSK_LL = 3, /* Must match bit assignment in RADIO1_IRQ_SEL */ + UNASSIGNED_LL = 4, /* Must match bit assignment in RADIO1_IRQ_SEL */ +} link_layer_t; + +/*! @brief Data rate selections. */ +typedef enum _data_rate +{ + DR_1MBPS = 0, /* Must match bit assignment in BITRATE field */ + DR_500KBPS = 1, /* Must match bit assignment in BITRATE field */ + DR_250KBPS = 2, /* Must match bit assignment in BITRATE field */ +#if RADIO_IS_GEN_3P0 + DR_2MBPS = 3, /* Must match bit assignment in BITRATE field */ +#endif /* RADIO_IS_GEN_3P0 */ + DR_UNASSIGNED = 4, /* Must match bit assignment in BITRATE field */ +} data_rate_t; + +/*! @brief Control settings for Fast Antenna Diversity */ +typedef enum _FAD_LPPS_CTRL +{ + NONE = 0, + FAD_ENABLED = 1, + LPPS_ENABLED = 2 +} FAD_LPPS_CTRL_T; + +/*! @brief XCVR XCVR Panic codes for indicating panic reason. */ +typedef enum _XCVR_PANIC_ID +{ + WRONG_RADIO_ID_DETECTED = 1, + CALIBRATION_INVALID = 2, +} XCVR_PANIC_ID_T; + +/*! @brief Initialization or mode change selection for config routine. */ +typedef enum _XCVR_INIT_MODE_CHG +{ + XCVR_MODE_CHANGE = 0, + XCVR_FIRST_INIT = 1, +} XCVR_INIT_MODE_CHG_T; + +typedef enum _XCVR_COEX_PRIORITY +{ + XCVR_COEX_LOW_PRIO = 0, + XCVR_COEX_HIGH_PRIO = 1 +} XCVR_COEX_PRIORITY_T; + +/*! @brief Current configuration of the radio. */ +typedef struct xcvr_currConfig_tag +{ + radio_mode_t radio_mode; + data_rate_t data_rate; +} xcvr_currConfig_t; + +/*! + * @brief XCVR RX_DIG channel filter coefficient storage + * Storage of the coefficients varies from 6 bits to 10 bits so all use int16_t for storage. + */ +typedef struct _xcvr_rx_chf_coeffs +{ + uint16_t rx_chf_coef_0; /* < 6 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_1; /* < 6 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_2; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_3; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_4; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_5; /* < 7 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_6; /* < 8 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_7; /* < 8 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_8; /* < 9 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_9; /* < 9 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_10; /* < 10 bit two's complement stored in a uint16_t */ + uint16_t rx_chf_coef_11; /* < 10 bit two's complement stored in a uint16_t */ +} xcvr_rx_chf_coeffs_t; + +/*! + * @brief XCVR masked init type for 32 bit registers + * Initialization uses the mask to clear selected fields of the register and then OR's in the init value. All init values must be in their proper field position. + */ +typedef struct _xcvr_masked_init_32 +{ + uint32_t mask; + uint32_t init; +} xcvr_masked_init_32_t; + +/*! + * @brief XCVR common configure structure + */ +typedef struct _xcvr_common_config +{ + /* XCVR_ANA configs */ + xcvr_masked_init_32_t ana_sy_ctrl1; + + /* XCVR_PLL_DIG configs */ + uint32_t pll_hpm_bump; + uint32_t pll_mod_ctrl; + uint32_t pll_chan_map; + uint32_t pll_lock_detect; + uint32_t pll_hpm_ctrl; +#if !RADIO_IS_GEN_2P1 + uint32_t pll_hpmcal_ctrl; +#endif /* !RADIO_IS_GEN_2P1 */ + uint32_t pll_hpm_sdm_res; + uint32_t pll_lpm_ctrl; + uint32_t pll_lpm_sdm_ctrl1; + uint32_t pll_delay_match; + uint32_t pll_ctune_ctrl; + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with mode specific init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init; + uint32_t dcoc_cal_gain_init; + uint32_t dc_resid_ctrl_init; /* NOTE: This will be OR'd with datarate specific init for DCOC_RESID_CTRL to form complete register initialization */ + uint32_t dcoc_cal_rcp_init; + uint32_t lna_gain_val_3_0; + uint32_t lna_gain_val_7_4; + uint32_t lna_gain_val_8; + uint32_t bba_res_tune_val_7_0; + uint32_t bba_res_tune_val_10_8; + uint32_t lna_gain_lin_val_2_0_init; + uint32_t lna_gain_lin_val_5_3_init; + uint32_t lna_gain_lin_val_8_6_init; + uint32_t lna_gain_lin_val_9_init; + uint32_t bba_res_tune_lin_val_3_0_init; + uint32_t bba_res_tune_lin_val_7_4_init; + uint32_t bba_res_tune_lin_val_10_8_init; + uint32_t dcoc_bba_step_init; + uint32_t dcoc_tza_step_00_init; + uint32_t dcoc_tza_step_01_init; + uint32_t dcoc_tza_step_02_init; + uint32_t dcoc_tza_step_03_init; + uint32_t dcoc_tza_step_04_init; + uint32_t dcoc_tza_step_05_init; + uint32_t dcoc_tza_step_06_init; + uint32_t dcoc_tza_step_07_init; + uint32_t dcoc_tza_step_08_init; + uint32_t dcoc_tza_step_09_init; + uint32_t dcoc_tza_step_10_init; +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + uint32_t dcoc_cal_fail_th_init; + uint32_t dcoc_cal_pass_th_init; +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ + uint32_t agc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ + uint32_t agc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with datarate specific init to form complete register initialization */ + uint32_t agc_ctrl_3_init; + /* Other agc config inits moved to modeXdatarate config table */ + uint32_t agc_gain_tbl_03_00_init; + uint32_t agc_gain_tbl_07_04_init; + uint32_t agc_gain_tbl_11_08_init; + uint32_t agc_gain_tbl_15_12_init; + uint32_t agc_gain_tbl_19_16_init; + uint32_t agc_gain_tbl_23_20_init; + uint32_t agc_gain_tbl_26_24_init; + uint32_t rssi_ctrl_0_init; +#if RADIO_IS_GEN_3P0 + uint32_t rssi_ctrl_1_init; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t cca_ed_lqi_ctrl_0_init; + uint32_t cca_ed_lqi_ctrl_1_init; + + /* XCVR_TSM configs */ + uint32_t tsm_ctrl; + uint32_t tsm_ovrd2_init; + uint32_t end_of_seq_init_26mhz; + uint32_t end_of_seq_init_32mhz; +#if !RADIO_IS_GEN_2P1 + uint32_t lpps_ctrl_init; +#endif /* !RADIO_IS_GEN_2P1 */ + uint32_t tsm_fast_ctrl2_init_26mhz; + uint32_t tsm_fast_ctrl2_init_32mhz; + uint32_t recycle_count_init_26mhz; + uint32_t recycle_count_init_32mhz; + uint32_t pa_ramp_tbl_0_init; + uint32_t pa_ramp_tbl_1_init; +#if RADIO_IS_GEN_3P0 + uint32_t pa_ramp_tbl_2_init; + uint32_t pa_ramp_tbl_3_init; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t tsm_timing_00_init; + uint32_t tsm_timing_01_init; + uint32_t tsm_timing_02_init; + uint32_t tsm_timing_03_init; + uint32_t tsm_timing_04_init; + uint32_t tsm_timing_05_init; + uint32_t tsm_timing_06_init; + uint32_t tsm_timing_07_init; + uint32_t tsm_timing_08_init; + uint32_t tsm_timing_09_init; + uint32_t tsm_timing_10_init; + uint32_t tsm_timing_11_init; + uint32_t tsm_timing_12_init; + uint32_t tsm_timing_13_init; + uint32_t tsm_timing_14_init_26mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ + uint32_t tsm_timing_14_init_32mhz; /* tsm_timing_14 has mode specific LSbyte (both LS bytes) */ + uint32_t tsm_timing_15_init; + uint32_t tsm_timing_16_init_26mhz; + uint32_t tsm_timing_16_init_32mhz; + uint32_t tsm_timing_17_init; + uint32_t tsm_timing_18_init; + uint32_t tsm_timing_19_init; + uint32_t tsm_timing_20_init; + uint32_t tsm_timing_21_init; + uint32_t tsm_timing_22_init; + uint32_t tsm_timing_23_init; + uint32_t tsm_timing_24_init; + uint32_t tsm_timing_25_init_26mhz; + uint32_t tsm_timing_25_init_32mhz; + uint32_t tsm_timing_26_init; + uint32_t tsm_timing_27_init_26mhz; + uint32_t tsm_timing_27_init_32mhz; + uint32_t tsm_timing_28_init_26mhz; + uint32_t tsm_timing_28_init_32mhz; + uint32_t tsm_timing_29_init_26mhz; + uint32_t tsm_timing_29_init_32mhz; + uint32_t tsm_timing_30_init_26mhz; + uint32_t tsm_timing_30_init_32mhz; + uint32_t tsm_timing_31_init_26mhz; + uint32_t tsm_timing_31_init_32mhz; + uint32_t tsm_timing_32_init_26mhz; + uint32_t tsm_timing_32_init_32mhz; + uint32_t tsm_timing_33_init_26mhz; + uint32_t tsm_timing_33_init_32mhz; + uint32_t tsm_timing_34_init; + uint32_t tsm_timing_35_init; /* tsm_timing_35 has a mode specific LSbyte*/ + uint32_t tsm_timing_36_init_26mhz; + uint32_t tsm_timing_36_init_32mhz; + uint32_t tsm_timing_37_init_26mhz; + uint32_t tsm_timing_37_init_32mhz; + uint32_t tsm_timing_38_init; + uint32_t tsm_timing_39_init_26mhz; + uint32_t tsm_timing_39_init_32mhz; + uint32_t tsm_timing_40_init_26mhz; + uint32_t tsm_timing_40_init_32mhz; + uint32_t tsm_timing_41_init_26mhz; + uint32_t tsm_timing_41_init_32mhz; + uint32_t tsm_timing_51_init; + uint32_t tsm_timing_52_init_26mhz; + uint32_t tsm_timing_52_init_32mhz; + uint32_t tsm_timing_53_init; + uint32_t tsm_timing_54_init_26mhz; + uint32_t tsm_timing_54_init_32mhz; + uint32_t tsm_timing_55_init_26mhz; + uint32_t tsm_timing_55_init_32mhz; + uint32_t tsm_timing_56_init_26mhz; + uint32_t tsm_timing_56_init_32mhz; + uint32_t tsm_timing_57_init; + uint32_t tsm_timing_58_init; + + /* XCVR_TX_DIG configs */ + uint32_t tx_ctrl; + uint32_t tx_data_padding; + uint32_t tx_dft_pattern; +#if !RADIO_IS_GEN_2P1 + uint32_t rf_dft_bist_1; + uint32_t rf_dft_bist_2; +#endif /* !RADIO_IS_GEN_2P1 */ +} xcvr_common_config_t; + +/*! @brief XCVR mode specific configure structure (varies by radio mode) */ +typedef struct _xcvr_mode_config +{ + radio_mode_t radio_mode; + uint32_t scgc5_clock_ena_bits; + + /* XCVR_MISC configs */ + xcvr_masked_init_32_t xcvr_ctrl; + + /* XCVR_PHY configs */ +#if RADIO_IS_GEN_3P0 + uint32_t phy_fsk_pd_cfg0; + uint32_t phy_fsk_pd_cfg1; + uint32_t phy_fsk_cfg; + uint32_t phy_fsk_misc; + uint32_t phy_fad_ctrl; +#else + uint32_t phy_pre_ref0_init; + uint32_t phy_pre_ref1_init; + uint32_t phy_pre_ref2_init; + uint32_t phy_cfg1_init; + uint32_t phy_el_cfg_init; /* Should leave EL_WIN_SIZE and EL_INTERVAL to the data_rate specific configuration */ +#endif /* RADIO_IS_GEN_3P0 */ + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t agc_ctrl_0_init; /* NOTE: Common init and mode init will be OR'd together for AGC_CTRL_0 to form complete register initialization */ + + /* XCVR_TSM configs */ +#if (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) + uint32_t tsm_timing_35_init; /* Only the LSbyte is mode specific */ +#endif /* (RADIO_IS_GEN_2P0 || RADIO_IS_GEN_2P1) */ + + /* XCVR_TX_DIG configs */ + uint32_t tx_gfsk_ctrl; + uint32_t tx_gfsk_coeff1_26mhz; + uint32_t tx_gfsk_coeff2_26mhz; + uint32_t tx_gfsk_coeff1_32mhz; + uint32_t tx_gfsk_coeff2_32mhz; +} xcvr_mode_config_t; + +/*! + * @brief XCVR modeXdatarate specific configure structure (varies by radio mode AND data rate) + * This structure is used to store all of the XCVR settings which are dependent upon both radio mode and data rate. It is used as an overlay + * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. + */ +typedef struct _xcvr_mode_datarate_config +{ + radio_mode_t radio_mode; + data_rate_t data_rate; + + /* XCVR_ANA configs */ + xcvr_masked_init_32_t ana_sy_ctrl2; + xcvr_masked_init_32_t ana_rx_bba; + xcvr_masked_init_32_t ana_rx_tza; + + /* XCVR_PHY configs */ +#if RADIO_IS_GEN_3P0 + uint32_t phy_fsk_misc_mode_datarate; +#else + uint32_t phy_cfg2_init; +#endif /* RADIO_IS_GEN_3P0 */ + + uint32_t agc_ctrl_2_init_26mhz; + uint32_t agc_ctrl_2_init_32mhz; + xcvr_rx_chf_coeffs_t rx_chf_coeffs_26mhz; /* 26MHz ext clk */ + xcvr_rx_chf_coeffs_t rx_chf_coeffs_32mhz; /* 32MHz ext clk */ + uint32_t rx_rccal_ctrl_0; + uint32_t rx_rccal_ctrl_1; + + /* XCVR_TX_DIG configs */ + uint32_t tx_fsk_scale_26mhz; /* Only used by MSK mode, but dependent on datarate */ + uint32_t tx_fsk_scale_32mhz; /* Only used by MSK mode, but dependent on datarate */ +} xcvr_mode_datarate_config_t; + +/*! + * @brief XCVR datarate specific configure structure (varies by data rate) + * This structure is used to store all of the XCVR settings which are dependent upon data rate. It is used as an overlay + * on top of the xcvr_mode_config_t structure to supply definitions which are either not in that table or which must be overridden for data rate. + */ +typedef struct _xcvr_datarate_config +{ + data_rate_t data_rate; + + /* XCVR_PHY configs */ + uint32_t phy_el_cfg_init; /* Note: EL_ENABLE is set in xcvr_mode_config_t settings */ + + /* XCVR_RX_DIG configs */ + uint32_t rx_dig_ctrl_init_26mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t rx_dig_ctrl_init_32mhz; /* NOTE: Common init, mode init, and datarate init will be OR'd together for RX_DIG_CTRL to form complete register initialization */ + uint32_t agc_ctrl_1_init_26mhz; + uint32_t agc_ctrl_1_init_32mhz; + uint32_t dcoc_ctrl_0_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_0_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_0 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init_26mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ + uint32_t dcoc_ctrl_1_init_32mhz; /* NOTE: This will be OR'd with common init for DCOC_CTRL_1 to form complete register initialization */ + uint32_t dcoc_ctrl_2_init_26mhz; + uint32_t dcoc_ctrl_2_init_32mhz; + uint32_t dcoc_cal_iir_init_26mhz; + uint32_t dcoc_cal_iir_init_32mhz; + uint32_t dc_resid_ctrl_26mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ + uint32_t dc_resid_ctrl_32mhz;/* NOTE: This will be OR'd with common init for DCOC_RESID_CTRL to form complete register initialization */ +} xcvr_datarate_config_t; + +/*! + * @brief LPUART callback function type + * + * The panic callback function is defined by system if system need to be informed of XCVR fatal errors. + * refer to #XCVR_RegisterPanicCb + */ +typedef void (*panic_fptr)(uint32_t panic_id, uint32_t location, uint32_t extra1, uint32_t extra2); + +/* Make available const structures from config files */ +extern const xcvr_common_config_t xcvr_common_config; +extern const xcvr_mode_config_t zgbe_mode_config; +extern const xcvr_mode_config_t ble_mode_config; +extern const xcvr_mode_config_t ant_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p7_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_0p32_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p5_h_1p0_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p3_h_0p5_mode_config; +extern const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config; +extern const xcvr_mode_config_t msk_mode_config; + +#if RADIO_IS_GEN_3P0 +extern const xcvr_datarate_config_t xcvr_2mbps_config; +#endif /* RADIO_IS_GEN_3P0 */ +extern const xcvr_datarate_config_t xcvr_1mbps_config; +extern const xcvr_datarate_config_t xcvr_500kbps_config; +extern const xcvr_datarate_config_t xcvr_250kbps_config; +extern const xcvr_datarate_config_t xcvr_802_15_4_500kbps_config; /* Custom datarate settings for 802.15.4 since it is 2MChips/sec */ + +#if RADIO_IS_GEN_3P0 +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_2mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_2mbps_config; +#endif /* RADIO_IS_GEN_3P0 */ +extern const xcvr_mode_datarate_config_t xcvr_BLE_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_ZIGBEE_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_ANT_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p32_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p7_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_1p0_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p3_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_1mbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_500kbps_config; +extern const xcvr_mode_datarate_config_t xcvr_MSK_250kbps_config; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name XCVR functional Operation + * @{ + */ + +/*! + * @brief Initializes an XCVR instance. + * + * This function initializes the XCVR module according to the radio_mode and data_rate settings. This the only function call required to + * start up the XCVR in most situations. + * + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @note This function encompasses the ::XCVRGetDefafultConfig() and ::XCVR_Configure() functions. + */ +xcvrStatus_t XCVR_Init(radio_mode_t radio_mode, data_rate_t data_rate); + +/*! + * @brief Deinitializes an XCVR instance. + * + * This function gate the XCVR module clock and set all register value to reset value. + * + */ +void XCVR_Deinit(void); + +/*! + * @brief Initializes XCVR configure structure. + * + * This function updates pointers to the XCVR configure structures with default values. + * The configurations are divided into a common structure, a set of radio mode specific + * structures (one per radio_mode), a set of mode&datarate specific structures (for each mode at + * each datarate), and a set of data rate specific structures. + * The pointers provided by this routine point to const structures which can be + * copied to variable structures if changes to settings are required. + * + * @param radio_mode [in] The radio mode for which the configuration structures are requested. + * @param data_rate [in] The data rate for which the configuration structures are requested. + * @param com_config [in,out] Pointer to a pointer to the common configuration settings structure. + * @param mode_config [in,out] Pointer to a pointer to the mode specific configuration settings structure. + * @param mode_datarate_config [in,out] Pointer to a pointer to the modeXdata rate specific configuration settings structure. + * @param datarate_config [in,out] Pointer to a pointer to the data rate specific configuration settings structure. + * @return 0 success, others failure + * @see XCVR_Configure + */ +xcvrStatus_t XCVR_GetDefaultConfig(radio_mode_t radio_mode, + data_rate_t data_rate, + const xcvr_common_config_t ** com_config, + const xcvr_mode_config_t ** mode_config, + const xcvr_mode_datarate_config_t ** mode_datarate_config, + const xcvr_datarate_config_t ** datarate_config); + +/*! + * @brief Initializes an XCVR instance. + * + * This function initializes the XCVR module with user-defined settings. + * + * @param com_config Pointer to the common configuration settings structure. + * @param mode_config Pointer to the mode specific configuration settings structure. + * @param mode_datarate_config Pointer to a pointer to the modeXdata rate specific configuration settings structure. + * @param datarate_config Pointer to a pointer to the data rate specific configuration settings structure. + * @param tempDegC temperature of the die in degrees C. + * @param ext_clk indicates the external clock setting, 32MHz or 26MHz. + * @param first_init indicates whether the call is to initialize (== 1) or the call is to perform a mode change (== 0) + * @return 0 succeed, others failed + */ +xcvrStatus_t XCVR_Configure(const xcvr_common_config_t *com_config, + const xcvr_mode_config_t *mode_config, + const xcvr_mode_datarate_config_t *mode_datarate_config, + const xcvr_datarate_config_t *datarate_config, + int16_t tempDegC, + XCVR_INIT_MODE_CHG_T first_init); + +/*! + * @brief Set XCVR register to reset value. + * + * This function set XCVR register to the reset value. + * + */ +void XCVR_Reset(void); + +/*! + * @brief Change the operating mode of the radio. + * + * This function changes the XCVR to a new radio operating mode. + * + * @param new_radio_mode The radio mode for which the XCVR should be configured. + * @param new_data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @return status of the mode change. + */ + xcvrStatus_t XCVR_ChangeMode(radio_mode_t new_radio_mode, data_rate_t new_data_rate); + +/*! + * @brief Enable Narrowband RSSI measurement. + * + * This function enables the narrowband RSSI measurement + * + * @param IIRnbEnable true causes the NB RSSI to be enabled, false disabled. + */ +void XCVR_EnaNBRSSIMeas(uint8_t IIRnbEnable); + +/*! + * @brief Set an arbitrary frequency for RX and TX for the radio. + * + * This function sets the radio frequency used for RX and RX.. + * + * @param freq target frequency setting in Hz. + * @param refOsc reference oscillator setting in Hz. + * @return status of the frequency change. + * @details + */ + xcvrStatus_t XCVR_OverrideFrequency(uint32_t freq, uint32_t refOsc); + +/*! + * @brief Register a callback from upper layers. + * + * This function registers a callback from the upper layers for the radio to call in case of fatal errors. + * + * @param fptr The function pointer to a panic callback. + */ +void XCVR_RegisterPanicCb(panic_fptr fptr); /* allow upper layers to provide PANIC callback */ + +/*! + * @brief Read the health status of the XCVR to detect errors. + * + * This function enables the upper layers to request the current radio health. + * + * @return The health status of the radio.. + */ +healthStatus_t XCVR_HealthCheck(void); /* allow upper layers to poll the radio health */ + +/*! + * @brief Control FAD and LPPS features. + * + * This function controls the Fast Antenna Diversity (FAD) and Low Power Preamble Search. + * + * @param fptr control the FAD and LPPS settings. + * + */ + void XCVR_FadLppsControl(FAD_LPPS_CTRL_T control); + +/*! + * @brief Change the mapping of the radio IRQs. + * + * This function changes the mapping of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. + * + * @param irq0_mapping the LL which should be mapped to the INT0 line. + * @param irq1_mapping the LL which should be mapped to the INT1 line. + * @return status of the mapping request. + * @ note The radio_mode_t parameters map to ::link_layer_t selections for the LL which is connected to the INT line. + * @warning + * The same LL must NOT be mapped to both INT lines. + */ + xcvrStatus_t XCVR_SetIRQMapping(radio_mode_t irq0_mapping, radio_mode_t irq1_mapping); + +#if RADIO_IS_GEN_3P0 +/*! + * @brief Sets the network address used by the PHY during BLE Bit Streaming Mode. + * + * This function programs the register in the PHY which contains the network address used during BSM. + * + * @param bsm_ntw_address the address to be used during BSM. + * @ note This routine does NOT enable BSM. + */ +void XCVR_SetBSM_NTW_Address(uint32_t bsm_ntw_address); + +/*! + * @brief Reads the currently programmed network address used by the PHY during BLE Bit Streaming Mode. + * + * This function reads the register in the PHY which contains the network address used during BSM. + * + * @return bsm_ntw_address the address to be used during BSM. + * @ note This routine does NOT enable BSM. + */ +uint32_t XCVR_GetBSM_NTW_Address(void); +#endif /* RADIO_IS_GEN_3P0 */ + +/*! + * @brief Get the mapping of the one of the radio IRQs. + * + * This function reads the setting for the mapping of one of the radio LL IRQ signals to the 2.4G Radio INT0 and 2.4G Radio INT1 lines. + * + * @param int_num the number, 0 or 1, of the INT line to fetched. + * @return the mapping setting of the specified line. + * @note Any value passed into this routine other than 0 will be treated as a 1. + */ + link_layer_t XCVR_GetIRQMapping(uint8_t int_num); + +/*! + * @brief Get the current configuration of the XCVR. + * + * This function fetches the current configuration (radio mode and radio data rate) of the XCVR to allow LL to properly config data rates, etc + * + * @param curr_config pointer to a structure to be updated with the current mode and data rate. + * @return the status of the request, success or invalid parameter (null pointer). + * @note This API will return meaningless results if called before the radio is initialized... + */ +xcvrStatus_t XCVR_GetCurrentConfig(xcvr_currConfig_t * curr_config); + +/******************************************************************************* + * Customer level trim functions + ******************************************************************************/ +/*! + * @brief Controls setting the XTAL trim value.. + * + * This function enables the upper layers set a crystal trim compensation facor + * + * @param xtalTrim the trim value to apply to the XTAL trimming register. Only the 7 LSB are valid, setting the 8th bit returns an error. + * @return The health status of the radio.. + */ +xcvrStatus_t XCVR_SetXtalTrim(uint8_t xtalTrim); + +/*! + * @brief Controls getting the XTAL trim value.. + * + * This function enables the upper layers to read the current XTAL compensation factors. + * The returned value is in the range 0..127 (7 bits). + * + * @return The XTAL trim compensation factors.. + */ +uint8_t XCVR_GetXtalTrim(void); + +/*! + * @brief Controls setting the RSSI adjustment.. + * + * This function enables the upper layers to set an RSSI adjustment value. + * + * @param adj the adjustment value to apply to the RSSI adjustment register. The value must be a signed 8-bit value, in 1/4 dBm step. + * @return The health status of the radio.. + */ +xcvrStatus_t XCVR_SetRssiAdjustment(int8_t adj); + +/*! + * @brief Controls getting the RSSI adjustment.. + * + * This function enables the upper layers to read the current XCVR RSSI adjustment value. + * The returned value is a signed 8-bit value, in 1/4 dBm step. + * + * @return The RSSI adjustment value.. + */ +int8_t XCVR_GetRssiAdjustment(void); + +/*! + * @brief Controls setting the PLL to a particular channel. + * + * This function enables setting the radio channel for TX and RX. + * + * @param channel the channel number to set + * @param useMappedChannel when true, channel is assumed to be from the protocol specific channel map. when false, channel is assumed to be from the 128 general channel list.. + * @return The status of the channel over-ride. + */ +xcvrStatus_t XCVR_OverrideChannel(uint8_t channel, uint8_t useMappedChannel); + +/*! + * @brief Reads the current frequency for RX and TX for the radio. + * + * This function reads the radio frequency used for RX and RX.. + * + * @return Current radio frequency setting. + */ +uint32_t XCVR_GetFreq(void); + +/*! + * @brief Force receiver warmup. + * + * This function forces the initiation of a receiver warmup sequence. + * + */ +void XCVR_ForceRxWu(void); + +/*! + * @brief Force receiver warmdown. + * + * This function forces the initiation of a receiver warmdown sequence. + * + */ + void XCVR_ForceRxWd(void); + +/*! + * @brief Force transmitter warmup. + * + * This function forces the initiation of a transmit warmup sequence. + * + */ +void XCVR_ForceTxWu(void); + +/*! + * @brief Force transmitter warmdown. + * + * This function forces the initiation of a transmit warmdown sequence. + * + */ +void XCVR_ForceTxWd(void); + +/*! + * @brief Starts transmit with a TX pattern register data sequence. + * + * This function starts transmitting using the DFT pattern register mode. + * + * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @param tx_pattern - the data pattern to transmit on. + * @return The status of the pattern reg transmit. + * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode + * and data rate. + */ +xcvrStatus_t XCVR_DftTxPatternReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint32_t tx_pattern); + +/*! + * @brief Starts transmit with a TX LFSR register data sequence. + * + * This function starts transmitting using the DFT LFSR register mode. + * + * @param channel_num - the protocol specific channel to transmit on. Valid values are defined in the CHANNEL_NUM register documentation. + * @param radio_mode The radio mode for which the XCVR should be configured. + * @param data_rate The data rate for which the XCVR should be configured. Only matters when GFSK/MSK radio_mode is selected. + * @param lfsr_length - the length of the LFSR sequence to use. + * @return The status of the LFSR reg transmit. + * @note The XCVR_DftTxOff() function must be called to turn off TX and revert all settings. This routine calls XCVR_ChangeMode() with the desired radio mode + * and data rate. + */ +xcvrStatus_t XCVR_DftTxLfsrReg(uint16_t channel_num, radio_mode_t radio_mode, data_rate_t data_rate, uint8_t lfsr_length); + +/*! + * @brief Controls clearing all TX DFT settings. + * + * This function reverts all TX DFT settings from the test modes to normal operating mode. + * + */ +void XCVR_DftTxOff(void); + +/*! + * @brief Controls setting the PA power level. + * + * This function enables setting the PA power level to a specific setting, overriding any link layer settings. + * + * @param pa_power - the power level to set. Valid values are 0, 1, and even values from 2 to 0x3E, inclusive. + * @return The status of the PA power over-ride. + */ +xcvrStatus_t XCVR_ForcePAPower(uint8_t pa_power); + +/*! + * @brief Starts CW TX. + * + * This function starts transmitting CW (no modulation). + * + * @param rf_channel_freq - the RF channel to transmit on. Valid values are integer values from 2360 to 2487MHz, inclusive. + * @param protocol - the protocol setting to use, valid settings are 6 (GFSK) and 7 (FSK). + * @return The status of the CW transmit. + */ +xcvrStatus_t XCVR_DftTxCW(uint16_t rf_channel_freq, uint8_t protocol); + +xcvrStatus_t XCVR_CoexistenceInit(void); +xcvrStatus_t XCVR_CoexistenceSetPriority(XCVR_COEX_PRIORITY_T rxPriority, XCVR_COEX_PRIORITY_T txPriority); +xcvrStatus_t XCVR_CoexistenceSaveRestoreTimings(uint8_t saveTimings); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_XCVR_H_ */ + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr_trim.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr_trim.c new file mode 100644 index 000000000..d91dd1eba --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr_trim.c @@ -0,0 +1,995 @@ +/* +* Copyright 2016-2017 NXP +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ + +#include "fsl_device_registers.h" +#include "fsl_common.h" +#include "fsl_xcvr.h" +#include "fsl_xcvr_trim.h" +#include "dbg_ram_capture.h" +#include "math.h" + +/******************************************************************************* +* Definitions +******************************************************************************/ + + +/******************************************************************************* +* Prototypes +******************************************************************************/ +void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val); +float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ); +extern float roundf (float); + +/******************************************************************************* +* Variables +******************************************************************************/ +const int8_t TsettleCal = 10; +static GAIN_CALC_TBL_ENTRY2_T measurement_tbl2[NUM_I_Q_CHAN][NUM_SWEEP_STEP_ENTRIES2]; +static const int8_t sweep_step_values2[NUM_SWEEP_STEP_ENTRIES2] = +{ + 0, /* Baseline entry is first and not used in this table */ + -16, + +16, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + -4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4, + +4 +}; + +/******************************************************************************* + * Macros + ******************************************************************************/ +#define ISIGN(x) !((uint16_t)x & 0x8000) +#define ABS(x) ((x) > 0 ? (x) : -(x)) + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! ********************************************************************************* + * \brief This function performs a trim of the BBA DCOC DAC on the DUT + * + * \return status - 1 if passed, 0 if failed. + * + * \ingroup PublicAPIs + * + * \details + * Requires the RX to be warmed up before this function is called. + * + ***********************************************************************************/ +uint8_t rx_bba_dcoc_dac_trim_shortIQ(void) +{ + uint8_t i; + float temp_mi = 0; + float temp_mq = 0; + float temp_pi = 0; + float temp_pq = 0; + float temp_step = 0; + uint8_t bbf_dacinit_i, bbf_dacinit_q; + + uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only. */ + uint32_t bbf_dcoc_step; + uint32_t bbf_dcoc_step_rcp; + TZAdcocstep_t tza_dcoc_step[11]; + uint8_t status = 0; + + /* Save register values. */ + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + + XcvrCalDelay(1000); + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore. */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore. */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore. */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore. */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore. */ + + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode. */ + XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN(0); /* Turn OFF AGC */ + + XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) ; /* Set LNA Manual Gain */ + XCVR_RX_DIG->AGC_CTRL_1 = (XCVR_RX_DIG->AGC_CTRL_1 & ~XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN_MASK) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) ; /* Set BBA Manual Gain */ + + XCVR_RX_DIG->RX_DIG_CTRL = (XCVR_RX_DIG->RX_DIG_CTRL & ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) | XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN(0); /* Enable HW DC Calibration -- Disable for SW-DCOC */ + XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode. */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); + /* Set DCOC Tracking State. */ + XCVR_RX_DIG->DCOC_CTRL_0 = (XCVR_RX_DIG->DCOC_CTRL_0 & ~XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC_MASK) | XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(0); /* Disables DCOC Tracking when set to 0 */ + /* Apply Manual Gain. */ + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x02) | XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x00) ; + XcvrCalDelay(TsettleCal); + + dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Capture DC null setting. */ + + bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); + bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U) >> 8; + + DC_Measure_short(I_CHANNEL, NOMINAL2); + DC_Measure_short(Q_CHANNEL, NOMINAL2); + + /* SWEEP Q CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(Q_CHANNEL, BBF_NEG); + + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(Q_CHANNEL, BBF_POS); + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial. */ + XcvrCalDelay(TsettleCal); + + /* SWEEP I CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(I_CHANNEL, BBF_NEG); + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = (XCVR_RX_DIG->DCOC_DAC_INIT & ~XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I_MASK) | XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16); + XcvrCalDelay(TsettleCal); + DC_Measure_short(I_CHANNEL, BBF_POS); + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DACs to initial. */ + XcvrCalDelay(TsettleCal); + + /* Calculate BBF DCOC STEPS, RECIPROCALS */ + temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + + temp_step = (temp_mi+temp_pi + temp_mq+temp_pq) / 4; + + bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); + + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) + { + bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + + /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH. */ + for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) /* Relying on enumeration ordering. */ + { + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL. */ + switch(i){ + case TZA_STEP_N0: + temp_step = (bbf_dcoc_step >> 3U) / 3.6F; + break; + case TZA_STEP_N1: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16)/(xcvr_common_config.dcoc_tza_step_00_init >> 16); + break; + case TZA_STEP_N2: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16)/(xcvr_common_config.dcoc_tza_step_01_init >> 16); + break; + case TZA_STEP_N3: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16)/(xcvr_common_config.dcoc_tza_step_02_init >> 16); + break; + case TZA_STEP_N4: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16)/(xcvr_common_config.dcoc_tza_step_03_init >> 16); + break; + case TZA_STEP_N5: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16)/(xcvr_common_config.dcoc_tza_step_04_init >> 16); + break; + case TZA_STEP_N6: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16)/(xcvr_common_config.dcoc_tza_step_05_init >> 16); + break; + case TZA_STEP_N7: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16)/(xcvr_common_config.dcoc_tza_step_06_init >> 16); + break; + case TZA_STEP_N8: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16)/(xcvr_common_config.dcoc_tza_step_07_init >> 16); + break; + case TZA_STEP_N9: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16)/(xcvr_common_config.dcoc_tza_step_08_init >> 16); + break; + case TZA_STEP_N10: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16)/(xcvr_common_config.dcoc_tza_step_09_init >> 16); + break; + default: + break; + } + + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + } + + /* Make the trims active. */ + XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp) ; + XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp) ; + + status = 1; /* Success */ + } + else + { + status = 0; /* Failure */ + } + + /* Restore Registers. */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings. */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings. */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings. */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting. */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore. */ + + return status; +} + +/*! ********************************************************************************* + * \brief This function performs one point of the DC GAIN calibration process on the DUT + * + * \param[in] chan - whether the I or Q channel is being tested. + * \param[in] stage - whether the BBF or TZA gain stage is being tested. + * \param[in] dcoc_init_val - the value being set in the ***DCOC_INIT_* register by the parent. + * \param[in] ext_measmt - the external measurement (in milliVolts) captured by the parent after the ***DCOC_INIT_* register was setup. + * + * \ingroup PublicAPIs + * + * \details + * Relies on a static array to store each point of data for later processing in ::DC_GainCalc(). + * + ***********************************************************************************/ +void DC_Measure_short(IQ_t chan, DAC_SWEEP_STEP2_t dcoc_init_val) +{ + int16_t dc_meas_i = 0; + int16_t dc_meas_q = 0; + int16_t sum_dc_meas_i = 0; + int16_t sum_dc_meas_q = 0; + + { + int8_t i; + const int8_t iterations = 1; + sum_dc_meas_i = 0; + sum_dc_meas_q = 0; + + for (i = 0; i < iterations; i++) + { + rx_dc_sample_average(&dc_meas_i, &dc_meas_q); + sum_dc_meas_i = sum_dc_meas_i + dc_meas_i; + sum_dc_meas_q = sum_dc_meas_q + dc_meas_q; + } + sum_dc_meas_i = sum_dc_meas_i / iterations; + sum_dc_meas_q = sum_dc_meas_q / iterations; + } + + measurement_tbl2[chan][dcoc_init_val].step_value = sweep_step_values2[dcoc_init_val]; + + if (chan == I_CHANNEL) + { + measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_i; + } + else + { + measurement_tbl2[chan][dcoc_init_val].internal_measurement = dc_meas_q; + } +} + +/*! ********************************************************************************* + * \brief This function calculates one point of DC DAC step based on digital samples of I or Q. + * + * \param[in] meas_ptr - pointer to the structure containing the measured data from internal measurement. + * \param[in] baseline_meas_ptr - pointer to the structure containing the baseline measured data from internal measurement. + * + * \return result of the calculation, the measurement DCOC DAC step value for this measurement point. + * + ***********************************************************************************/ +float calc_dcoc_dac_step(GAIN_CALC_TBL_ENTRY2_T * meas_ptr, GAIN_CALC_TBL_ENTRY2_T * baseline_meas_ptr ) +{ + static int16_t norm_dc_code; + static float dc_step; + + /* Normalize internal measurement */ + norm_dc_code = meas_ptr->internal_measurement - baseline_meas_ptr->internal_measurement; + dc_step = (float)(norm_dc_code) / (float)(meas_ptr->step_value); + dc_step = (dc_step < 0)? -dc_step: dc_step; + + return dc_step; +} + +/*! ********************************************************************************* + * \brief Temporary delay function + * + * \param[in] none. + * + * \return none. + * + * \details + * + ***********************************************************************************/ +void XcvrCalDelay(uint32_t time) +{ + while(time * 32 > 0) /* Time delay is roughly in uSec. */ + { + time--; + } +} + +/*! ********************************************************************************* + * \brief This function calculates the average (DC value) based on a smaller set of digital samples of I and Q. + * + * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. + * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. + * + ***********************************************************************************/ +void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg) +{ + static uint32_t samples[128]; /* 544*2*2 (entire packet ram1/2 size) */ + uint16_t i; + uint32_t rx_sample; + uint16_t * sample_ptr; + uint32_t temp, end_of_rx_wu; + uint32_t num_iq_samples; + float avg_i = 0; + float avg_q = 0; + + num_iq_samples = 128; + + /* Clear the entire allocated sample buffer */ + for (i = 0; i < num_iq_samples; i++) + { + samples[i]=0; + } + + /* Assume this has been called *AFTER* RxWu has completed. */ + /* XCVR_ForceRxWu(); */ + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase) */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + dbg_ram_init(); + /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ +#if RADIO_IS_GEN_3P0 + dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); + dbg_ram_wait_for_complete(); + dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); + dbg_ram_release(); +#else + (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); +#endif /* RADIO_IS_GEN_3P0 */ + + /* Sign extend the IQ samples in place in the sample buffer. */ + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i++) + { + rx_sample = *sample_ptr; + rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + *sample_ptr = rx_sample; + sample_ptr++; + } + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i += 2) + { + static int16_t i_value; + static int16_t q_value; + + /* Average I & Q channels separately. */ + i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits. */ + q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits. */ + avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ + avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ + } + XcvrCalDelay(10); + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * \brief This function calculates the average (DC value) based on a larger set of digital samples of I and Q. + * + * \param[in] i_avg - pointer to the location for storing the calculated average for I channel samples. + * \param[in] q_avg - pointer to the location for storing the calculated average for Q channel samples. + * + ***********************************************************************************/ +void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg) +{ + static uint32_t samples[512]; /* 544*2*2 (entire packet ram1/2 size) */ + uint16_t i; + uint32_t rx_sample; + uint16_t * sample_ptr; + uint32_t temp, end_of_rx_wu; + uint32_t num_iq_samples; + float avg_i = 0; + float avg_q = 0; + + num_iq_samples = 512; + + /* Clear the entire allocated sample buffer. */ + for (i = 0; i < num_iq_samples; i++) + { + samples[i]=0; + } + + /* Assume this has been called *AFTER* RxWu has completed. */ + /* XCVR_ForceRxWu(); */ + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + dbg_ram_init(); + /* Argument below is # of bytes, so *2 (I+Q) and *2 (2bytes/sample) */ +#if RADIO_IS_GEN_3P0 + dbg_ram_start_capture(DBG_PAGE_RXDIGIQ, NO_START_TRIG, NO_STOP_TRIG); + dbg_ram_wait_for_complete(); + dbg_ram_postproc_capture(DBG_PAGE_RXDIGIQ,num_iq_samples * 2 * 2, &samples[0]); + dbg_ram_release(); +#else + (void)dbg_ram_capture(DBG_PAGE_RXDIGIQ, num_iq_samples * 2 * 2, &samples[0]); +#endif /* RADIO_IS_GEN_3P0 */ + + /* Sign extend the IQ samples in place in the sample buffer. */ + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i++) + { + rx_sample = *sample_ptr; + rx_sample |= ((rx_sample & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + *sample_ptr = rx_sample; + sample_ptr++; + } + + sample_ptr = (uint16_t *)(&samples[0]); + for (i = 0; i < num_iq_samples * 2; i += 2) + { + static int16_t i_value; + static int16_t q_value; + + /* Average I & Q channels separately. */ + i_value = *(sample_ptr + i); /* Sign extend from 12 to 16 bits */ + q_value = *(sample_ptr + i + 1); /* Sign extend from 12 to 16 bits */ + avg_i += ((float)i_value - avg_i) / (float)(i + 1); /* Rolling average I */ + avg_q += ((float)q_value - avg_q) / (float)(i + 1); /* Rolling average Q */ + } + + XcvrCalDelay(10); + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * rx_dc_est_average : Get DC EST values and return the Average + ***********************************************************************************/ +void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber) +{ + float avg_i = 0; + float avg_q = 0; + uint16_t i = 0; + static uint32_t dc_temp, temp; + uint32_t end_of_rx_wu = 0; + static int16_t dc_meas_i; + static int16_t dc_meas_q; + + /* Wait for TSM to reach the end of warmup (unless you want to capture some samples during DCOC cal phase). */ + temp = XCVR_TSM->END_OF_SEQ; + end_of_rx_wu = (temp & XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_TSM_END_OF_SEQ_END_OF_RX_WU_SHIFT; + while ((( XCVR_MISC->XCVR_STATUS & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_CTRL_XCVR_STATUS_TSM_COUNT_SHIFT ) != end_of_rx_wu) {}; + + /* Read DCOC DC EST register. */ + for (i = 0; i < SampleNumber; i++) + { + dc_temp = XCVR_RX_DIG->DCOC_DC_EST; + dc_meas_i = dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_I_MASK; + temp = dc_meas_i; + temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + dc_meas_i = temp; + avg_i += (float) dc_meas_i; + + dc_meas_q = (dc_temp & XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_RX_DIG_DCOC_DC_EST_DC_EST_Q_SHIFT; + temp = dc_meas_q; + temp |= ((temp & 0x800U) ? 0xF000U : 0x0U); /* Sign extend from 12 to 16 bits. */ + dc_meas_q = temp; + avg_q += (float) dc_meas_q; + } + + avg_i /= (float) SampleNumber; + avg_q /= (float) SampleNumber; + + *i_avg = (int16_t)avg_i; + *q_avg = (int16_t)avg_q; +} + +/*! ********************************************************************************* + * \brief This function performs a trim of the BBA DCOC DAC on the DUT + * + * \return status - 1 if passed, 0 if failed. + * + * \ingroup PublicAPIs + * + * \details + * Requires the RX to be warmed up before this function is called. + * + ***********************************************************************************/ +uint8_t rx_bba_dcoc_dac_trim_DCest(void) +{ + uint8_t i; + float temp_mi = 0; + float temp_mq = 0; + float temp_pi = 0; + float temp_pq = 0; + float temp_step = 0; + + uint32_t bbf_dcoc_step; + uint32_t bbf_dcoc_step_rcp; + TZAdcocstep_t tza_dcoc_step[11]; + uint8_t status = 0; + + uint8_t bbf_dacinit_i, bbf_dacinit_q; + uint8_t tza_dacinit_i, tza_dacinit_q; + int16_t dc_meas_i; + int16_t dc_meas_q; + uint32_t dcoc_init_reg_value_dcgain = 0x80802020; /* Used in 2nd & 3rd Generation DCOC Trims only */ + uint32_t temp; + + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + + /* Save register */ + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + + /* Register config */ + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ + temp = XCVR_RX_DIG->RX_DIG_CTRL; + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ + + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(0x20) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(0x20) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(0x80) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(0x80); + + XcvrCalDelay(TsettleCal); + + /* Set default DCOC DAC INIT Value */ + dcoc_init_reg_value_dcgain = XCVR_RX_DIG->DCOC_DAC_INIT; /* Store DCOC DAC INIT values */ + bbf_dacinit_i = (dcoc_init_reg_value_dcgain & 0x000000FFU); + bbf_dacinit_q = (dcoc_init_reg_value_dcgain & 0x0000FF00U)>>8; + tza_dacinit_i = (dcoc_init_reg_value_dcgain & 0x00FF0000U)>>16; + tza_dacinit_q = dcoc_init_reg_value_dcgain >> 24; + + XcvrCalDelay(TsettleCal * 4); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; + measurement_tbl2[Q_CHANNEL][NOMINAL2].step_value = sweep_step_values2[NOMINAL2]; + measurement_tbl2[I_CHANNEL][NOMINAL2].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][NOMINAL2].internal_measurement = dc_meas_q; + + /* SWEEP I/Q CHANNEL */ + /* BBF NEG STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i - 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q - 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + XcvrCalDelay(TsettleCal * 2); + + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][BBF_NEG].step_value = -16; + measurement_tbl2[Q_CHANNEL][BBF_NEG].step_value = -16; + measurement_tbl2[I_CHANNEL][BBF_NEG].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][BBF_NEG].internal_measurement = dc_meas_q; + + + /* BBF POS STEP */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(bbf_dacinit_i + 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(bbf_dacinit_q + 16) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(tza_dacinit_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(tza_dacinit_q); + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + measurement_tbl2[I_CHANNEL][BBF_POS].step_value = +16; + measurement_tbl2[Q_CHANNEL][BBF_POS].step_value = +16; + measurement_tbl2[I_CHANNEL][BBF_POS].internal_measurement = dc_meas_i; + measurement_tbl2[Q_CHANNEL][BBF_POS].internal_measurement = dc_meas_q; + + XCVR_RX_DIG->DCOC_DAC_INIT = dcoc_init_reg_value_dcgain; /* Return DAC setting to initial */ + + /* Calculate BBF DCOC STEPS, RECIPROCALS */ + temp_mi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_NEG], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_mq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_NEG], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + temp_pi = calc_dcoc_dac_step(&measurement_tbl2[I_CHANNEL][BBF_POS], &measurement_tbl2[I_CHANNEL][NOMINAL2]); + temp_pq = calc_dcoc_dac_step(&measurement_tbl2[Q_CHANNEL][BBF_POS], &measurement_tbl2[Q_CHANNEL][NOMINAL2]); + + temp_step = (temp_mi + temp_pi + temp_mq + temp_pq) / 4; + bbf_dcoc_step = (uint32_t)roundf(temp_step * 8U); + + if ((bbf_dcoc_step > 265) & (bbf_dcoc_step < 305)) + { + bbf_dcoc_step_rcp = (uint32_t)roundf((float)0x8000U / temp_step); + + /* Calculate TZA DCOC STEPS & RECIPROCALS and IQ_DC_GAIN_MISMATCH */ + for (i = TZA_STEP_N0; i <= TZA_STEP_N10; i++) + { + /* Calculate TZA DCOC STEPSIZE & its RECIPROCAL */ + switch(i){ + case TZA_STEP_N0: + temp_step = (bbf_dcoc_step>>3U) / 3.6F; + break; + case TZA_STEP_N1: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_01_init >> 16) / (xcvr_common_config.dcoc_tza_step_00_init >> 16); + break; + case TZA_STEP_N2: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_02_init >> 16) / (xcvr_common_config.dcoc_tza_step_01_init >> 16); + break; + case TZA_STEP_N3: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_03_init >> 16) / (xcvr_common_config.dcoc_tza_step_02_init >> 16); + break; + case TZA_STEP_N4: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_04_init >> 16) / (xcvr_common_config.dcoc_tza_step_03_init >> 16); + break; + case TZA_STEP_N5: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_05_init >> 16) / (xcvr_common_config.dcoc_tza_step_04_init >> 16); + break; + case TZA_STEP_N6: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_06_init >> 16) / (xcvr_common_config.dcoc_tza_step_05_init >> 16); + break; + case TZA_STEP_N7: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_07_init >> 16) / (xcvr_common_config.dcoc_tza_step_06_init >> 16); + break; + case TZA_STEP_N8: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_08_init >> 16) / (xcvr_common_config.dcoc_tza_step_07_init >> 16); + break; + case TZA_STEP_N9: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_09_init >> 16) / (xcvr_common_config.dcoc_tza_step_08_init >> 16); + break; + case TZA_STEP_N10: + temp_step = temp_step * (xcvr_common_config.dcoc_tza_step_10_init >> 16) / (xcvr_common_config.dcoc_tza_step_09_init >> 16); + break; + default: + break; + } + + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step = (uint32_t)roundf(temp_step * 8); + tza_dcoc_step[i-TZA_STEP_N0].dcoc_step_rcp = (uint32_t)roundf((float)0x8000 / temp_step); + } + + /* Make the trims active */ + XCVR_RX_DIG->DCOC_BBA_STEP = XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP(bbf_dcoc_step) | XCVR_RX_DIG_DCOC_BBA_STEP_BBA_DCOC_STEP_RECIP(bbf_dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_0 = XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_GAIN_0(tza_dcoc_step[0].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_0_DCOC_TZA_STEP_RCP_0(tza_dcoc_step[0].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_1 = XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_GAIN_1(tza_dcoc_step[1].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_1_DCOC_TZA_STEP_RCP_1(tza_dcoc_step[1].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_2 = XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_GAIN_2(tza_dcoc_step[2].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_2_DCOC_TZA_STEP_RCP_2(tza_dcoc_step[2].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_3 = XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_GAIN_3(tza_dcoc_step[3].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_3_DCOC_TZA_STEP_RCP_3(tza_dcoc_step[3].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_4 = XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_GAIN_4(tza_dcoc_step[4].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_4_DCOC_TZA_STEP_RCP_4(tza_dcoc_step[4].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_5 = XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_GAIN_5(tza_dcoc_step[5].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_5_DCOC_TZA_STEP_RCP_5(tza_dcoc_step[5].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_6 = XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_GAIN_6(tza_dcoc_step[6].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_6_DCOC_TZA_STEP_RCP_6(tza_dcoc_step[6].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_7 = XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_GAIN_7(tza_dcoc_step[7].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_7_DCOC_TZA_STEP_RCP_7(tza_dcoc_step[7].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_8 = XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_GAIN_8(tza_dcoc_step[8].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_8_DCOC_TZA_STEP_RCP_8(tza_dcoc_step[8].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_9 = XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_GAIN_9(tza_dcoc_step[9].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_9_DCOC_TZA_STEP_RCP_9(tza_dcoc_step[9].dcoc_step_rcp); + XCVR_RX_DIG->DCOC_TZA_STEP_10 = XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_GAIN_10(tza_dcoc_step[10].dcoc_step) | XCVR_RX_DIG_DCOC_TZA_STEP_10_DCOC_TZA_STEP_RCP_10(tza_dcoc_step[10].dcoc_step_rcp); + + status = 1; /* Success */ + } + else + { + status = 0; /* Failure */ + } + + /* Restore Registers */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ + + return status; +} + +/*! ********************************************************************************* + * DCOC_DAC_INIT_Cal : slope sign seek depending on measure's sign + ***********************************************************************************/ +void DCOC_DAC_INIT_Cal(uint8_t standalone_operation) +{ + int16_t dc_meas_i = 2000, dc_meas_i_p = 2000; + int16_t dc_meas_q = 2000, dc_meas_q_p = 2000; + uint8_t curr_tza_dac_i, curr_tza_dac_q; + uint8_t curr_bba_dac_i, curr_bba_dac_q; + uint8_t p_tza_dac_i = 0, p_tza_dac_q = 0; + uint8_t p_bba_dac_i = 0, p_bba_dac_q = 0; + uint8_t i = 0; + uint8_t bba_gain = 11; + bool TZA_I_OK = 0, TZA_Q_OK = 0, BBA_I_OK = 0, BBA_Q_OK = 0; + + uint32_t dcoc_ctrl_0_stack; + uint32_t dcoc_ctrl_1_stack; + uint32_t agc_ctrl_1_stack; + uint32_t rx_dig_ctrl_stack; + uint32_t dcoc_cal_gain_state; + uint32_t xcvr_ctrl_stack = 0; + + uint32_t temp; + + /* Save registers */ + dcoc_ctrl_0_stack = XCVR_RX_DIG->DCOC_CTRL_0; /* Save state of DCOC_CTRL_0 for later restore */ + dcoc_ctrl_1_stack = XCVR_RX_DIG->DCOC_CTRL_1; /* Save state of DCOC_CTRL_1 for later restore */ + rx_dig_ctrl_stack = XCVR_RX_DIG->RX_DIG_CTRL; /* Save state of RX_DIG_CTRL for later restore */ + agc_ctrl_1_stack = XCVR_RX_DIG->AGC_CTRL_1; /* Save state of RX_DIG_CTRL for later restore */ + dcoc_cal_gain_state = XCVR_RX_DIG->DCOC_CAL_GAIN; /* Save state of DCOC_CAL_GAIN for later restore */ + + /* WarmUp */ + if (standalone_operation) + { + temp = XCVR_MISC->XCVR_CTRL; + xcvr_ctrl_stack = temp; + temp &= ~(XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK); + temp |= XCVR_CTRL_XCVR_CTRL_PROTOCOL(0); + XCVR_MISC->XCVR_CTRL = temp; + XCVR_OverrideChannel(12, 1); /* Calibrate on channel #12, 2.426 GHz in BLE map */ + XCVR_ForceRxWu(); + XcvrCalDelay(2000); + } + + /* Register config */ + /* Ensure AGC, DCOC and RX_DIG_CTRL is in correct mode */ + temp = XCVR_RX_DIG->RX_DIG_CTRL; + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_AGC_EN_MASK; /* Turn OFF AGC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK; /* Disable for SW control of DCOC */ + temp &= ~XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN_MASK; /* Disable for SW control of DCOC */ + XCVR_RX_DIG->RX_DIG_CTRL = temp; + + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | /* Enable LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | /* Enable BBA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0x0) | /* Set LNA Manual Gain */ + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(0x0); /* Set BBA Manual Gain */ + + /* DCOC_CTRL_0 @ 4005_C02C -- Define default DCOC DAC settings in manual mode */ + temp = XCVR_RX_DIG->DCOC_CTRL_0; + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_MAN(1); /* Enable Manual DCOC */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_SRC(1); /* Ensure DCOC Tracking is enabled */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_TRK_EST_OVR(1); /* Enable DC Estimator */ + temp |= XCVR_RX_DIG_DCOC_CTRL_0_DCOC_CORRECT_EN(1); /* Ensure DC correction is enabled */ + XCVR_RX_DIG->DCOC_CTRL_0 = temp; + + XcvrCalDelay(TsettleCal); + + /* Set default DCOC DAC INIT Value */ + /* LNA and BBA DAC Sweep */ + curr_bba_dac_i = 0x20; + curr_bba_dac_q = 0x20; + curr_tza_dac_i = 0x80; + curr_tza_dac_q = 0x80; + + /* Perform a first DC measurement to ensure that measurement is not clipping */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + + do + { + bba_gain--; + /* Set DAC user gain */ + XCVR_RX_DIG->AGC_CTRL_1 = XCVR_RX_DIG_AGC_CTRL_1_USER_LNA_GAIN_EN(1) | + XCVR_RX_DIG_AGC_CTRL_1_LNA_USER_GAIN(0) | /* 2 */ + XCVR_RX_DIG_AGC_CTRL_1_USER_BBA_GAIN_EN(1) | + XCVR_RX_DIG_AGC_CTRL_1_BBA_USER_GAIN(bba_gain) ; /* 10 */ + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + } while ((ABS(dc_meas_i) > 1900) | (ABS(dc_meas_q) > 1900)); + + for (i = 0; i < 0x0F; i++) + { + /* I channel : */ + if (!TZA_I_OK) + { + if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (i > 0)) + { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) + { + curr_tza_dac_i = p_tza_dac_i; + } + + TZA_I_OK = 1; + } + else + { + p_tza_dac_i = curr_tza_dac_i; + + if (ISIGN(dc_meas_i)) /* If positif */ + { + curr_tza_dac_i--; + } + else + { + curr_tza_dac_i++; + } + } + } + else /* Sweep BBA I */ + { + if (!BBA_I_OK) + { + if ((ISIGN(dc_meas_i) != ISIGN(dc_meas_i_p)) && (curr_bba_dac_i != 0x20)) + { + if (ABS(dc_meas_i) != MIN(ABS(dc_meas_i), ABS(dc_meas_i_p))) + { + curr_bba_dac_i = p_bba_dac_i; + } + + BBA_I_OK = 1; + } + else + { + p_bba_dac_i = curr_bba_dac_i; + if (ISIGN(dc_meas_i)) /* If positif */ + { + curr_bba_dac_i--; + } + else + { + curr_bba_dac_i++; + } + } + } + } + + /* Q channel : */ + if (!TZA_Q_OK) + { + if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (i > 0)) + { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) + { + curr_tza_dac_q = p_tza_dac_q; + } + TZA_Q_OK = 1; + } + else + { + p_tza_dac_q = curr_tza_dac_q; + if (ISIGN(dc_meas_q)) /* If positif */ + { + curr_tza_dac_q--; + } + else + { + curr_tza_dac_q++; + } + } + } + else /* Sweep BBA Q */ + { + if (!BBA_Q_OK) + { + if ((ISIGN(dc_meas_q) != ISIGN(dc_meas_q_p)) && (curr_bba_dac_q != 0x20)) + { + if (ABS(dc_meas_q) != MIN(ABS(dc_meas_q), ABS(dc_meas_q_p))) + { + curr_bba_dac_q = p_bba_dac_q; + } + BBA_Q_OK = 1; + } + else + { + p_bba_dac_q = curr_bba_dac_q; + if (ISIGN(dc_meas_q)) /* If positif */ + { + curr_bba_dac_q--; + } + else + { + curr_bba_dac_q++; + } + } + } + } + + /* DC OK break : */ + if (TZA_I_OK && TZA_Q_OK && BBA_I_OK && BBA_Q_OK) + { + break; + } + + dc_meas_i_p = dc_meas_i; /* Store as previous value */ + dc_meas_q_p = dc_meas_q; /* Store as previous value */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + XcvrCalDelay(TsettleCal * 2); + rx_dc_est_average(&dc_meas_i, &dc_meas_q, 64); + } + + /* Apply optimized DCOC DAC INIT : */ + XCVR_RX_DIG->DCOC_DAC_INIT = XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_I(curr_bba_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_BBA_DCOC_INIT_Q(curr_bba_dac_q) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_I(curr_tza_dac_i) | + XCVR_RX_DIG_DCOC_DAC_INIT_TZA_DCOC_INIT_Q(curr_tza_dac_q); + + /* WarmDown */ + if (standalone_operation) + { + XCVR_ForceRxWd(); /* Don't leave the receiver running. */ + XcvrCalDelay(200); + XCVR_OverrideChannel(0xFF,1); /* Release channel overrides */ + XCVR_MISC->XCVR_CTRL = xcvr_ctrl_stack; + } + + /* Restore register */ + XCVR_RX_DIG->DCOC_CTRL_0 = dcoc_ctrl_0_stack; /* Restore DCOC_CTRL_0 state to prior settings */ + XCVR_RX_DIG->DCOC_CTRL_1 = dcoc_ctrl_1_stack; /* Restore DCOC_CTRL_1 state to prior settings */ + XCVR_RX_DIG->RX_DIG_CTRL = rx_dig_ctrl_stack; /* Restore RX_DIG_CTRL state to prior settings */ + XCVR_RX_DIG->DCOC_CAL_GAIN = dcoc_cal_gain_state; /* Restore DCOC_CAL_GAIN state to prior setting */ + XCVR_RX_DIG->AGC_CTRL_1 = agc_ctrl_1_stack; /* Save state of RX_DIG_CTRL for later restore */ +} + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr_trim.h b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr_trim.h new file mode 100644 index 000000000..9054b9e2a --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/fsl_xcvr_trim.h @@ -0,0 +1,132 @@ +/* +* Copyright 2016-2017 NXP +* +* Redistribution and use in source and binary forms, with or without modification, +* are permitted provided that the following conditions are met: +* +* o Redistributions of source code must retain the above copyright notice, this list +* of conditions and the following disclaimer. +* +* o Redistributions in binary form must reproduce the above copyright notice, this +* list of conditions and the following disclaimer in the documentation and/or +* other materials provided with the distribution. +* +* o Neither the name of Freescale Semiconductor, Inc. nor the names of its +* contributors may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +*/ +#ifndef _FSL_XCVR_TRIM_H_ +/* Clang-format off. */ +#define _FSL_XCVR_TRIM_H_ +/* Clang-format on. */ + +#include "fsl_device_registers.h" +/*! +* @addtogroup xcvr +* @{ +*/ + +/*! @file*/ + +/************************************************************************************ +************************************************************************************* +* Public constant definitions +************************************************************************************* +************************************************************************************/ + +/************************************************************************************ +************************************************************************************* +* Public type definitions +************************************************************************************* +************************************************************************************/ + +/* \brief The enumerations used to define the I & Q channel selections. */ +typedef enum +{ + I_CHANNEL = 0, + Q_CHANNEL = 1, + NUM_I_Q_CHAN = 2 +} IQ_t; + +typedef enum /* Enumeration of ADC_GAIN_CAL 2 */ +{ + NOMINAL2 = 0, + BBF_NEG = 1, + BBF_POS = 2, + TZA_STEP_N0 = 3, + TZA_STEP_N1 = 4, + TZA_STEP_N2 = 5, + TZA_STEP_N3 = 6, + TZA_STEP_N4 = 7, + TZA_STEP_N5 = 8, + TZA_STEP_N6 = 9, + TZA_STEP_N7 = 10, + TZA_STEP_N8 = 11, + TZA_STEP_N9 = 12, + TZA_STEP_N10 = 13, + TZA_STEP_P0 = 14, + TZA_STEP_P1 = 15, + TZA_STEP_P2 = 16, + TZA_STEP_P3 = 17, + TZA_STEP_P4 = 18, + TZA_STEP_P5 = 19, + TZA_STEP_P6 = 20, + TZA_STEP_P7 = 21, + TZA_STEP_P8 = 22, + TZA_STEP_P9 = 23, + TZA_STEP_P10 = 24, + + NUM_SWEEP_STEP_ENTRIES2 = 25 /* Including the baseline entry #0. */ +} DAC_SWEEP_STEP2_t; + +/* \brief Defines an entry in an array of structs to describe TZA DCOC STEP and TZA_DCOC_STEP_RECIPROCAL. */ +typedef struct +{ + uint16_t dcoc_step; + uint16_t dcoc_step_rcp; +// uint16_t dcoc_step_q; +// uint16_t dcoc_step_rcp_q; +} TZAdcocstep_t; + +typedef struct +{ + int8_t step_value; /* The offset from nominal DAC value (see sweep_step_values[]) */ + int16_t internal_measurement; /* The value (average code) measured from DMA samples. */ +// uint8_t valid; /* Set to TRUE (non zero) when a value is written to this table entry. */ +} GAIN_CALC_TBL_ENTRY2_T; + +/******************************************************************************* +* Definitions +******************************************************************************/ +void rx_dc_sample_average(int16_t * i_avg, int16_t * q_avg); +void rx_dc_sample_average_long(int16_t * i_avg, int16_t * q_avg); +uint8_t rx_bba_dcoc_dac_trim_shortIQ(void); +void XcvrCalDelay(uint32_t time); +void rx_dc_est_average(int16_t * i_avg, int16_t * q_avg, uint16_t SampleNumber); +uint8_t rx_bba_dcoc_dac_trim_DCest(void); +void DCOC_DAC_INIT_Cal(uint8_t standalone_operation); + + + + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_XCVR_TRIM_H_ */ + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ifr_radio.c b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ifr_radio.c new file mode 100644 index 000000000..a8680a7ee --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ifr_radio.c @@ -0,0 +1,530 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "fsl_device_registers.h" +#include "fsl_xcvr.h" +#include "ifr_radio.h" +#include "fsl_os_abstraction.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define IFR_RAM (0) + +#if RADIO_IS_GEN_3P0 +#define RDINDX (0x41U) +#define K3_BASE_INDEX (0x11U) /* Based for read index */ +#else +#define RDRSRC (0x03U) +#define KW4x_512_BASE (0x20000U) +#define KW4x_256_BASE (0x10000U) +#endif /* RADIO_IS_GEN_3P0 */ + +#if RADIO_IS_GEN_2P1 +#define FTFA (FTFE) +#endif /* RADIO_IS_GEN_2P1 */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +uint32_t read_another_ifr_word(void); +uint32_t read_first_ifr_word(uint32_t read_addr); + +#if RADIO_IS_GEN_3P0 +uint64_t read_index_ifr(uint32_t read_addr); +#else +/*! ********************************************************************************* + * @brief Reads a location in block 1 IFR for use by the radio. + * + * This function handles reading IFR data from flash memory for trim loading. + * + * @param read_addr the address in the IFR to be read. + * + * @details This function wraps both the Gen2 read_resource command and the Gen2.1 and Gen3 read_index +***********************************************************************************/ +#if RADIO_IS_GEN_2P1 +uint64_t read_resource_ifr(uint32_t read_addr); +#else +uint32_t read_resource_ifr(uint32_t read_addr); +#endif /* RADIO_IS_GEN_2P1 */ +#endif /* RADIO_IS_GEN_3P0 */ + +void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data); + +/******************************************************************************* + * Variables + ******************************************************************************/ +static uint32_t ifr_read_addr; + +#if RADIO_IS_GEN_3P0 +static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */ +static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */ +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + /* Trim table is empty for Gen3 by default */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#else +#if RADIO_IS_GEN_2P0 +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + 0x4005912CU, /* RSIM_ANA_TRIM address */ + 0x784B0000U, /* RSIM_ANA_TRIM default value */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#else +static uint64_t packed_data_long; /* Storage for 2 32 bit values to be read by read_index */ +static uint8_t num_words_avail; /* Number of 32 bit words available in packed_data_long storage */ +const uint32_t BLOCK_1_IFR[]= +{ + /* Revised fallback table which should work with untrimmed parts */ + 0xABCDFFFEU, /* Version #FFFE indicates default trim values */ + + 0x4005912CU, /* RSIM_ANA_TRIM address */ + 0x784B0000U, /* RSIM_ANA_TRIM default value */ + + /* No TRIM_STATUS in SW fallback array. */ + 0xFEED0E0FU /* End of File */ +}; +#endif /* RADIO_IS_GEN_2P0 */ +#endif /* RADIO_IS_GEN_3P0 */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! ********************************************************************************* + * \brief Read command for reading the first 32bit word from IFR, encapsulates different + * flash IFR read mechanisms for multiple generations of SOC + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * +***********************************************************************************/ +uint32_t read_first_ifr_word(uint32_t read_addr) +{ + ifr_read_addr = read_addr; + return read_another_ifr_word(); +} + +/*! ********************************************************************************* + * \brief Read command for reading additional 32bit words from IFR. Encapsulates multiple IFR read mechanisms. + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * + * \remarks PRE-CONDITIONS: + * The function read_first_ifr_word() must have been called so that the ifr_read_addr variable is setup prior to use. + * +***********************************************************************************/ +uint32_t read_another_ifr_word(void) +{ + uint32_t packed_data; + +#if (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) + /* Using some static storage and alternating reads to read_index_ifr to replace read_resource_ifr */ + if (num_words_avail == 0) + { +#if RADIO_IS_GEN_3P0 + packed_data_long = read_index_ifr(ifr_read_addr); +#else /* Use 64 bit return version of read_resource */ + packed_data_long = read_resource_ifr(ifr_read_addr); +#endif /* RADIO_IS_GEN_3P0 */ + + num_words_avail = 2; + ifr_read_addr++; /* Read index addresses increment by 1 */ + } + + packed_data = (uint32_t)(packed_data_long & 0xFFFFFFFF); + packed_data_long = packed_data_long >> 32; + num_words_avail--; +#else + packed_data = read_resource_ifr(ifr_read_addr); + ifr_read_addr += 4; /* Read resource addresses increment by 4 */ +#endif /* (RADIO_IS_GEN_3P0 || RADIO_IS_GEN_2P1) */ + + return packed_data; +} + +#if RADIO_IS_GEN_3P0 +/*! ********************************************************************************* + * \brief Read command for reading from IFR using RDINDEX command + * + * \param read_addr flash address + * + * \return 8 bytes of packed data containing radio trims only + * +***********************************************************************************/ +uint64_t read_index_ifr(uint32_t read_addr) +{ + uint8_t rdindex = read_addr; + uint64_t read_data; + uint8_t i; + + while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 to make sure not interrupting a prior operation */ + + if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) + { + FTFE->FSTAT = (1 << FTFE_FSTAT_ACCERR_SHIFT); /* Write 1 to ACCEER to clear errors */ + } + + FTFE->FCCOB[0] = RDINDX; + FTFE->FCCOB[1] = rdindex; + + OSA_InterrupDisable(); + FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK; + while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Pack read data back into 64 bit type */ + read_data = FTFE->FCCOB[11]; /* MSB goes in first, will be shifted left sequentially */ + for (i = 10; i > 3; i--) + { + read_data = read_data << 8; + read_data |= FTFE->FCCOB[i]; + } + + return read_data; +} +#else + +/*! ********************************************************************************* + * \brief Read command for reading from IFR + * + * \param read_addr flash address + * + * \return packed data containing radio trims only + * +***********************************************************************************/ +#if RADIO_IS_GEN_2P0 +uint32_t read_resource_ifr(uint32_t read_addr) +{ + + uint32_t packed_data; + uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; + uint32_t read_data31_24, read_data23_16, read_data15_8, read_data7_0; + + flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16); + flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8); + flash_addr7_0 = (uint8_t)(read_addr & 0xFF); + + while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */ + + if ((FTFA->FSTAT & FTFA_FSTAT_ACCERR_MASK) == FTFA_FSTAT_ACCERR_MASK ) + { + FTFA->FSTAT = (1<FCCOB0 = RDRSRC; + FTFA->FCCOB1 = flash_addr23_16; + FTFA->FCCOB2 = flash_addr15_8; + FTFA->FCCOB3 = flash_addr7_0; + FTFA->FCCOB8 = 0x00; + + OSA_InterruptDisable(); + FTFA->FSTAT = FTFA_FSTAT_CCIF_MASK; + while ((FTFA_FSTAT_CCIF_MASK & FTFA->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Start reading */ + read_data31_24 = FTFA->FCCOB4; /* FTFA->FCCOB[4] */ + read_data23_16 = FTFA->FCCOB5; /* FTFA->FCCOB[5] */ + read_data15_8 = FTFA->FCCOB6; /* FTFA->FCCOB[6] */ + read_data7_0 = FTFA->FCCOB7; /* FTFA->FCCOB[7] */ + + packed_data = (read_data31_24 << 24) | (read_data23_16 << 16) | (read_data15_8 << 8) | (read_data7_0 << 0); + + return packed_data; +} +#else +uint64_t read_resource_ifr(uint32_t read_addr) +{ + + uint64_t packed_data; + uint8_t flash_addr23_16, flash_addr15_8, flash_addr7_0; + uint8_t read_data[8]; + uint64_t temp_64; + uint8_t i; + + flash_addr23_16 = (uint8_t)((read_addr & 0xFF0000) >> 16); + flash_addr15_8 = (uint8_t)((read_addr & 0x00FF00) >> 8); + flash_addr7_0 = (uint8_t)(read_addr & 0xFF); + while((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + + if ((FTFE->FSTAT & FTFE_FSTAT_ACCERR_MASK) == FTFE_FSTAT_ACCERR_MASK ) + { + FTFE->FSTAT = (1<FCCOB0 = RDRSRC; + FTFE->FCCOB1 = flash_addr23_16; + FTFE->FCCOB2 = flash_addr15_8; + FTFE->FCCOB3 = flash_addr7_0; + FTFE->FCCOB4 = 0x00; + + OSA_InterruptDisable(); + FTFE->FSTAT = FTFE_FSTAT_CCIF_MASK; + while ((FTFE_FSTAT_CCIF_MASK & FTFE->FSTAT) == 0); /* Wait till CCIF=1 */ + OSA_InterruptEnable(); + + /* Start reading */ + read_data[7] = FTFE->FCCOB4; + read_data[6] = FTFE->FCCOB5; + read_data[5] = FTFE->FCCOB6; + read_data[4] = FTFE->FCCOB7; + read_data[3] = FTFE->FCCOB8; + read_data[2] = FTFE->FCCOB9; + read_data[1] = FTFE->FCCOBA; + read_data[0] = FTFE->FCCOBB; + + packed_data = 0; + for (i = 0; i < 8; i++) + { + temp_64 = read_data[i]; + packed_data |= temp_64 << (i * 8); + } + + return packed_data; +} + +#endif /* RADIO_IS_GEN_2P0 */ +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief Store a SW trim value in the table passed in from calling function. + * + * \param sw_trim_tbl pointer to the software trim table to hold SW trim values + * \param num_entries the number of entries in the SW trim table + * \param addr the software trim ID + * \param data the value of the software trim + * +***********************************************************************************/ +void store_sw_trim(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries, uint32_t addr, uint32_t data) +{ + uint16_t i; + + if (sw_trim_tbl != NULL) + { + for (i = 0; i < num_entries; i++) + { + if (addr == sw_trim_tbl[i].trim_id) + { + sw_trim_tbl[i].trim_value = data; + sw_trim_tbl[i].valid = 1; + break; /* Don't need to scan the array any further... */ + } + } + } +} + +/*! ********************************************************************************* + * \brief Process block 1 IFR data. + * + * \param sw_trim_tbl pointer to the software trim table to hold SW trim values + * \param num_entries the number of entries in the SW trim table + * + * \remarks + * Uses a IFR v2 formatted default array if the IFR is blank or corrupted. + * Stores SW trim values to an array passed into this function. + * +***********************************************************************************/ +void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries) +{ + uint32_t dest_addr; + uint32_t read_addr; + uint32_t dest_data; + uint32_t packed_data; + uint32_t *ifr_ptr; + +#if RADIO_IS_GEN_3P0 + num_words_avail = 0; /* Prep for handling 64 bit words from flash */ +#endif /* RADIO_IS_GEN_3P0 */ + +#if RADIO_IS_GEN_3P0 + read_addr = K3_BASE_INDEX; +#else +#ifdef CPU_MKW41Z256VHT4 + read_addr = KW4x_256_BASE; +#else + read_addr = KW4x_512_BASE; +#endif /* CPU_MKW41Z256VHT4 */ +#endif /* RADIO_IS_GEN_3P0 */ + + /* Read first entry in IFR table */ + packed_data = read_first_ifr_word(read_addr); + if ((packed_data&~IFR_VERSION_MASK) == IFR_VERSION_HDR) + { + /* Valid header was found, process real IFR data */ + XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK); + store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array*/ + packed_data = read_another_ifr_word(); + + while (packed_data !=IFR_EOF_SYMBOL) + { + if (IS_A_SW_ID(packed_data)) /* SW Trim case (non_reg writes) */ + { + dest_addr = packed_data; + packed_data = read_another_ifr_word(); + dest_data = packed_data; + /* Place SW trim in array for driver SW to use */ + store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); + } + else + { + if (IS_VALID_REG_ADDR(packed_data)) /* Valid register write address */ + { + dest_addr = packed_data; + packed_data = read_another_ifr_word(); + dest_data = packed_data; + *(uint32_t *)(dest_addr) = dest_data; + } + else + { /* Invalid address case */ + + } + } + + packed_data=read_another_ifr_word(); + } + } + else + { + /* Valid header is not present, use blind IFR trim table */ + ifr_ptr = (void *)BLOCK_1_IFR; + packed_data = *ifr_ptr; + XCVR_MISC->OVERWRITE_VER = (packed_data & IFR_VERSION_MASK); + store_sw_trim(sw_trim_tbl, num_entries, 0xABCD, (packed_data & IFR_VERSION_MASK)); /* Place IFR version # in SW trim array */ + ifr_ptr++; + packed_data= *ifr_ptr; + + while (packed_data != IFR_EOF_SYMBOL) + { + if (IS_A_SW_ID(packed_data)) + { + /* SW Trim case (non_reg writes) */ + dest_addr = packed_data; + ifr_ptr++; + packed_data = *(ifr_ptr); + dest_data = packed_data; + /* Place SW trim in array for driver SW to use */ + store_sw_trim(sw_trim_tbl, num_entries, dest_addr, dest_data); + } + else + { + dest_addr = packed_data; + ifr_ptr++; + packed_data = *ifr_ptr; + dest_data = packed_data; + + /* Valid register write address */ + if (IS_VALID_REG_ADDR(dest_addr)) + { + *(uint32_t *)(dest_addr) = dest_data; + } + else + { + /* Invalid address case */ + } + } + + ifr_ptr++; + packed_data= *ifr_ptr; + } + } +} + +#if RADIO_IS_GEN_3P0 + +#else +uint32_t handle_ifr_die_id(void) +{ + uint32_t id_x, id_y; + uint32_t id; + + id = read_resource_ifr(0x90); + id_x = id & 0x00FF0000; + id_y = id & 0x000000FF; + + return (id_x | id_y); +} + +uint32_t handle_ifr_die_kw_type(void) +{ + uint32_t zb, ble; + + zb = read_resource_ifr(0x80) & 0x8000; + ble= read_resource_ifr(0x88) & 0x100000; + + return (zb | ble); +} + +#endif /* RADIO_IS_GEN_3P0 */ + +/*! ********************************************************************************* + * \brief Dumps block 1 IFR data to an array. + * + * \param dump_tbl pointer to the table to hold the dumped IFR values + * \param num_entries the number of entries to dump + * + * \remarks + * Starts at the first address in IFR and dumps sequential entries. + * +***********************************************************************************/ +void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries) +{ +#if RADIO_IS_GEN_3P0 + uint32_t ifr_address = 0x20000; +#else + uint32_t ifr_address = 0x20000; +#endif /* RADIO_IS_GEN_3P0 */ + uint32_t * dump_ptr = dump_tbl; + uint8_t i; + + *dump_ptr = read_first_ifr_word(ifr_address); + dump_ptr++; + + for (i = 0; i < num_entries - 1; i++) + { + *dump_ptr = read_another_ifr_word(); + dump_ptr++; + } +} + diff --git a/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ifr_radio.h b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ifr_radio.h new file mode 100644 index 000000000..e02277f5a --- /dev/null +++ b/zephyr/middleware/wireless/framework_5.3.3/XCVR/MKW41Z4/ifr_radio.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __IFR_RADIO_H__ +/* clang-format off */ +#define __IFR_RADIO_H__ +/* clang-format on */ + +#include +/* clang-format off */ +#define _FSL_XCVR_H_ +/* clang-format on */ + +/*! + * @addtogroup xcvr + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define IFR_EOF_SYMBOL (0xFEED0E0FU) /* < Denotes the "End of File" for IFR data */ +#define IFR_VERSION_HDR (0xABCD0000U) /* < Constant value for upper 16 bits of IFR data header */ +#define IFR_VERSION_MASK (0x0000FFFFU) /* < Mask for version number (lower 16 bits) of IFR data header */ +#define IFR_SW_ID_MIN (0x00000000U) /* < Lower limit of SW trim IDs */ +#define IFR_SW_ID_MAX (0x0000FFFFU) /* < Lower limit of SW trim IDs */ + +#define IS_A_SW_ID(x) ((IFR_SW_ID_MIN < (x)) && (IFR_SW_ID_MAX >= (x))) + +/* K3 valid registers support */ +#if (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) +#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x41000000U) /* Valid addresses are 0x410xxxxx */ +#endif /* (defined(CPU_K32W042S1M2CAx_M0P) || defined(CPU_K32W042S1M2VPJ_M0P)) */ +/* KW41 and KW35/36 valid registers support */ +#if (defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) || \ + defined(CPU_MKW31Z256VHT4) || defined(CPU_MKW31Z512VHT4) || \ + defined(CPU_MKW21Z256VHT4) || defined(CPU_MKW21Z512VHT4) || \ + defined(CPU_MKW35A512VFP4) || defined(CPU_MKW36A512VFP4) ) + +#define IS_VALID_REG_ADDR(x) (((x) & 0xFFFF0000U) == 0x40050000U) /* Valid addresses are 0x4005xxxx */ +#endif + +#define MAKE_MASK(size) ((1 << (size)) - 1) +#define MAKE_MASKSHFT(size, bitpos) (MAKE_MASK(size) << (bitpos)) + +#define IFR_TZA_CAP_TUNE_MASK (0x0000000FU) +#define IFR_TZA_CAP_TUNE_SHIFT (0) +#define IFR_BBF_CAP_TUNE_MASK (0x000F0000U) +#define IFR_BBF_CAP_TUNE_SHIFT (16) +#define IFR_RES_TUNE2_MASK (0x00F00000U) +#define IFR_RES_TUNE2_SHIFT (20) + +/* \var typedef uint8_t IFR_ERROR_T */ +/* \brief The IFR error reporting type. */ +/* See #IFR_ERROR_T_enum for the enumeration definitions. */ +typedef uint8_t IFR_ERROR_T; + +/* \brief The enumerations used to describe IFR errors. */ +enum IFR_ERROR_T_enum +{ + IFR_SUCCESS = 0, + INVALID_POINTER = 1, /* < NULL pointer error */ + INVALID_DEST_SIZE_SHIFT = 2, /* < the bits won't fit as specified in the destination */ +}; + +/* \var typedef uint16_t SW_TRIM_ID_T */ +/* \brief The SW trim ID type. */ +/* See #SW_TRIM_ID_T_enum for the enumeration definitions. */ +typedef uint16_t SW_TRIM_ID_T; + +/* \brief The enumerations used to define SW trim IDs. */ +enum SW_TRIM_ID_T_enum +{ + Q_RELATIVE_GAIN_BY_PART = 0, /* < Q vs I relative gain trim ID */ + ADC_GAIN = 1, /* < ADC gain trim ID */ + ZB_FILT_TRIM = 2, /* < Baseband Bandwidth filter trim ID for BLE */ + BLE_FILT_TRIM = 3, /* < Baseband Bandwidth filter trim ID for BLE */ + TRIM_STATUS = 4, /* < Status result of the trim process (error indications) */ + TRIM_VERSION = 0xABCD, /* < Version number of the IFR trim algorithm/format. */ +}; + +/* \var typedef uint32_t IFR_TRIM_STATUS_T */ +/* \brief The definition of failure bits stored in IFR trim status word. */ +/* See #IFR_TRIM_STATUS_T_enum for the enumeration definitions. */ +typedef uint32_t IFR_TRIM_STATUS_T; + +/* \brief The enumerations used to describe trim algorithm failures in the status entry in IFR. */ +/* This enum represents multiple values which can be OR'd together in a single status word. */ +enum IFR_TRIM_STATUS_T_enum +{ + TRIM_ALGORITHM_SUCCESS = 0, + BGAP_VOLTAGE_TRIM_FAILED = 1, /* < algorithm failure in BGAP voltagetrim */ + IQMC_GAIN_ADJ_FAILED = 2, /* < algorithm failure in IQMC gain trim */ + IQMC_PHASE_ADJ_FAILED = 4, /* < algorithm failure in IQMC phase trim */ + IQMC_DC_GAIN_ADJ_FAILED = 8, /* < */ + ADC_GAIN_TRIM_FAILED = 10, /* <*/ + ZB_FILT_TRIM_FAILED = 20, /* < */ + BLE_FILT_TRIM_FAILED = 40, /* < */ +}; + +/* \var typedef struct IFR_SW_TRIM_TBL_ENTRY_T */ +/* \brief Structure defining an entry in a table used to contain values to be passed back from IFR */ +/* handling routine to XCVR driver software. */ +typedef struct +{ + SW_TRIM_ID_T trim_id; /* < The assigned ID */ + uint32_t trim_value; /* < The value fetched from IFR.*/ + uint8_t valid; /* < validity of the trim_value field after IFR processing is complete (TRUE/FALSE).*/ +} IFR_SW_TRIM_TBL_ENTRY_T; + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief Reads a location in block 1 IFR for use by the radio. + * + * This function handles reading IFR data from flash memory for trim loading. + * + * @param read_addr the address in the IFR to be read. + */ +uint32_t read_resource_ifr(uint32_t read_addr); + +/*! + * @brief Reads a location in a simulated data array to support IFR handler testing. + * + * This function handles reading data from a const table for testing the trim loading functions. + * + * @param read_addr the address in the IFR to be read. + */ +uint32_t read_resource(uint16_t resource_id); + +/*! + * @brief Main IFR handler function called by XCVR driver software to process trim table. + * + * This function handles reading data from IFR and either loading to registers or storing to a SW trim values table. + * + * @param sw_trim_tbl pointer to the table used to store software trim values. + * @param num_entries the number of entries that can be stored in the SW trim table. + */ +void handle_ifr(IFR_SW_TRIM_TBL_ENTRY_T * sw_trim_tbl, uint16_t num_entries); + +/*! + * @brief Handler function to read die_id from IFR locations.. + * + * This function handles reading die ID value for debug and testing usage. + * + * @return the value of the die ID field. + */ +uint32_t handle_ifr_die_id(void); + +/*! + * @brief Handler function to read KW chip version from IFR locations.. + * + * This function handles reading KW chip version for debug and testing usage. + * + * @return the value of the KW version field. + */ +uint32_t handle_ifr_die_kw_type(void); + +/*! + * @brief Debug function to dump the IFR contents to a RAM array. + * + * This function handles reading data from IFR and storing to a RAM array for debug. + * + * @param dump_tbl pointer to the table used to store IFR entry values. + * @param num_entries the number of entries that can be stored in the dump table. + */ +void dump_ifr(uint32_t * dump_tbl, uint8_t num_entries); + +#endif /*__IFR_RADIO_H__ */ + diff --git a/zephyr/module.yml b/zephyr/module.yml new file mode 100644 index 000000000..792659868 --- /dev/null +++ b/zephyr/module.yml @@ -0,0 +1,4 @@ +name: hal_nxp +build: + cmake-ext: True + kconfig-ext: True From 195ba7f50dba0d1ab89f1940d9844ca989a08d7a Mon Sep 17 00:00:00 2001 From: Pieter De Gendt Date: Tue, 19 Oct 2021 15:35:55 +0800 Subject: [PATCH 2/4] mcux: Build SRC driver Build the status reset controller driver if hwinfo is enabled --- zephyr/hal_nxp.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/zephyr/hal_nxp.cmake b/zephyr/hal_nxp.cmake index c2079435a..aaef23df6 100644 --- a/zephyr/hal_nxp.cmake +++ b/zephyr/hal_nxp.cmake @@ -111,7 +111,7 @@ include_driver_ifdef(CONFIG_MEMC_MCUX_FLEXSPI flexspi driver_flexspi) include_driver_ifdef(CONFIG_PWM_MCUX_SCTIMER sctimer driver_sctimer) include_driver_ifdef(CONFIG_HAS_MCUX_RDC rdc driver_rdc) include_driver_ifdef(CONFIG_UART_MCUX_IUART iuart driver_iuart) - +include_driver_ifdef(CONFIG_HWINFO_MCUX_SRC src driver_src) #include device specific drivers if (${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") zephyr_include_directories(devices/${MCUX_DEVICE}/xip) From a3a7be5eb119afc0c44abae2cfed2ca5d743d9d4 Mon Sep 17 00:00:00 2001 From: Andrei Auchynnikau Date: Tue, 19 Oct 2021 15:41:29 +0800 Subject: [PATCH 3/4] mcux: add imx adc driver compiling add rtadc zephyr driver compiling Signed-off-by: Andrei Ovchinnikov --- zephyr/hal_nxp.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/zephyr/hal_nxp.cmake b/zephyr/hal_nxp.cmake index aaef23df6..3cc0cadaa 100644 --- a/zephyr/hal_nxp.cmake +++ b/zephyr/hal_nxp.cmake @@ -112,6 +112,7 @@ include_driver_ifdef(CONFIG_PWM_MCUX_SCTIMER sctimer driver_sctimer) include_driver_ifdef(CONFIG_HAS_MCUX_RDC rdc driver_rdc) include_driver_ifdef(CONFIG_UART_MCUX_IUART iuart driver_iuart) include_driver_ifdef(CONFIG_HWINFO_MCUX_SRC src driver_src) +include_driver_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR adc_12b1msps_sar driver_adc_12b1msps_sar) #include device specific drivers if (${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") zephyr_include_directories(devices/${MCUX_DEVICE}/xip) From 7b98fcc5d9b11e8fda1f1b600444acc7f0054336 Mon Sep 17 00:00:00 2001 From: Daniel DeGrasse Date: Tue, 19 Oct 2021 15:45:51 +0800 Subject: [PATCH 4/4] modules: mcux: Enabled GPT driver when GPT Timer KConfig is selected Enabled GPT driver in CMakeLists.txt when the GPT driver is used as a timer within Zephyr Signed-off-by: Daniel DeGrasse --- zephyr/hal_nxp.cmake | 1 + 1 file changed, 1 insertion(+) diff --git a/zephyr/hal_nxp.cmake b/zephyr/hal_nxp.cmake index 3cc0cadaa..4f908405b 100644 --- a/zephyr/hal_nxp.cmake +++ b/zephyr/hal_nxp.cmake @@ -113,6 +113,7 @@ include_driver_ifdef(CONFIG_HAS_MCUX_RDC rdc driver_rdc) include_driver_ifdef(CONFIG_UART_MCUX_IUART iuart driver_iuart) include_driver_ifdef(CONFIG_HWINFO_MCUX_SRC src driver_src) include_driver_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR adc_12b1msps_sar driver_adc_12b1msps_sar) +include_driver_ifdef(CONFIG_MCUX_GPT_TIMER gpt driver_gpt) #include device specific drivers if (${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") zephyr_include_directories(devices/${MCUX_DEVICE}/xip)