Feature/enable zephyr integration

CMakeLists.txt

@@ -0,0 +1,78 @@
+if(CONFIG_HAS_MCUX OR CONFIG_HAS_IMX_HAL)
+  zephyr_library()
+endif()
+
+set(MCUX_SDK_PROJECT_NAME ${ZEPHYR_CURRENT_LIBRARY})
+# Translate the SoC name and part number into the mcux device and cpu
+# name respectively.
+string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE)
+
+if("${MCUX_DEVICE}" STREQUAL "LPC54114")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm4)
+elseif("${MCUX_DEVICE}" STREQUAL "LPC54114_M0")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm0plus)
+  set(MCUX_DEVICE LPC54114)
+elseif("${MCUX_DEVICE}" STREQUAL "LPC55S16")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
+elseif("${MCUX_DEVICE}" STREQUAL "LPC55S28")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
+elseif("${MCUX_DEVICE}" STREQUAL "LPC55S69_CPU0")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33_core0)
+  set(MCUX_DEVICE LPC55S69)
+elseif("${MCUX_DEVICE}" STREQUAL "LPC55S69_CPU1")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33_core1)
+  set(MCUX_DEVICE LPC55S69)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1052")
+  string(REGEX REPLACE "(.*)[AB]$" "CPU_\\1B" MCUX_CPU ${CONFIG_SOC_PART_NUMBER})
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT685S_CM33")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33)
+  set(MCUX_DEVICE MIMXRT685S)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1176_CM4")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm4)
+  set(MCUX_DEVICE MIMXRT1176)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1176_CM7")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm7)
+  set(MCUX_DEVICE MIMXRT1176)
+else()
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
+endif()
+
+zephyr_include_directories(devices/${MCUX_DEVICE})
+zephyr_include_directories(devices/${MCUX_DEVICE}/drivers)
+# The mcux uses the cpu name to expose SoC-specific features of a
+# given peripheral. For example, the UART peripheral may be
+# instantiated with/without a hardware FIFO, and the size of that FIFO
+# may be different for each instance in a given SoC. See
+# fsl_device_registers.h and ${MCUX_DEVICE}_features.h
+zephyr_compile_definitions(${MCUX_CPU})
+
+# Build mcux device-specific objects. Although it is not normal
+# practice, drilling down like this avoids the need for repetitive
+# build scripts for every mcux device.
+zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_clock.c)
+if (${MCUX_DEVICE} MATCHES "LPC|MIMXRT6")
+  zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_power.c)
+  zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_reset.c)
+
+  if ((${MCUX_DEVICE} MATCHES "MIMXRT6") AND (CONFIG_PM))
+    zephyr_code_relocate(devices/${MCUX_DEVICE}/drivers/fsl_power.c SRAM)
+  endif()
+endif()
+
+if (${MCUX_DEVICE} MATCHES "MIMXRT117")
+  zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_romapi.c)
+  zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_pmu.c)
+  zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_dcdc.c)
+  zephyr_library_sources(devices/${MCUX_DEVICE}/drivers/fsl_anatop_ai.c)
+  if ("${MCUX_DEVICE}" STREQUAL "MIMXRT1176_CM4")
+    zephyr_include_directories(devices/${MCUX_DEVICE}/cm4/)
+    zephyr_library_sources_ifdef(
+      CONFIG_HAS_MCUX_CACHE
+      devices/${MCUX_DEVICE}/cm4/fsl_cache.c
+    )
+  endif()
+endif()
+
+#Include Entry cmake component
+include(${CMAKE_CURRENT_LIST_DIR}/zephyr/hal_nxp.cmake)
+enable_language(C ASM)

zephyr/components/phyksz8081/fsl_phy.c

@@ -0,0 +1,301 @@
+/*
+* Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+* All rights reserved.
+*
+ * SPDX-License-Identifier: BSD-3-Clause
+*/
+
+#include "fsl_phy.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Defines the timeout macro. */
+#define PHY_TIMEOUT_COUNT 100000U
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
+{
+    uint32_t bssReg;
+    uint32_t counter = PHY_TIMEOUT_COUNT;
+    uint32_t idReg    = 0;
+    status_t result = kStatus_Success;
+    uint32_t instance = ENET_GetInstance(base);
+    uint32_t timeDelay;
+    uint32_t ctlReg = 0;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Set SMI first. */
+    CLOCK_EnableClock(s_enetClock[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    ENET_SetSMI(base, srcClock_Hz, false);
+
+    /* Initialization after PHY stars to work. */
+    while ((idReg != PHY_CONTROL_ID1) && (counter != 0U))
+    {
+        (void)PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
+        counter--;
+    }
+
+    if (counter == 0U)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Reset PHY. */
+    counter = PHY_TIMEOUT_COUNT;
+    result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
+    if (result == kStatus_Success)
+    {
+#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
+        uint32_t data = 0;
+        result        = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+        result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
+
+        /* Set the negotiation. */
+        result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
+                           (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
+                            PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
+        if (result == kStatus_Success)
+        {
+            result =
+                PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
+            if (result == kStatus_Success)
+            {
+                /* Check auto negotiation complete. */
+                while (counter-- != 0U)
+                {
+                    result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
+                    if ( result == kStatus_Success)
+                    {
+                        (void)PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
+                        if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U) && ((ctlReg & PHY_LINK_READY_MASK) != 0U))
+                        {
+                            /* Wait a moment for Phy status stable. */
+                            for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay++)
+                            {
+                                __ASM("nop");
+                            }
+                            break;
+                        } 
+                    } 
+
+                    if (counter == 0U)
+                    {
+                        return kStatus_PHY_AutoNegotiateFail;
+                    }
+                }
+            }
+        }
+    }
+
+    return result;
+}
+
+status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
+{
+    uint32_t counter;
+
+    /* Clear the SMI interrupt event. */
+    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+    /* Starts a SMI write command. */
+    ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
+
+    /* Wait for SMI complete. */
+    for (counter = PHY_TIMEOUT_COUNT; counter > 0U; counter--)
+    {
+        if ((ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) != 0U)
+        {
+            break;
+        }
+    }
+
+    /* Check for timeout. */
+    if (counter == 0U)
+    {
+        return kStatus_PHY_SMIVisitTimeout;
+    }
+
+    /* Clear MII interrupt event. */
+    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+    return kStatus_Success;
+}
+
+status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
+{
+    assert(dataPtr);
+
+    uint32_t counter;
+
+    /* Clear the MII interrupt event. */
+    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+    /* Starts a SMI read command operation. */
+    ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
+
+    /* Wait for MII complete. */
+    for (counter = PHY_TIMEOUT_COUNT; counter > 0U; counter--)
+    {
+        if ((ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK) != 0U)
+        {
+            break;
+        }
+    }
+
+    /* Check for timeout. */
+    if (counter == 0U)
+    {
+        return kStatus_PHY_SMIVisitTimeout;
+    }
+
+    /* Get data from MII register. */
+    *dataPtr = ENET_ReadSMIData(base);
+
+    /* Clear MII interrupt event. */
+    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
+
+    return kStatus_Success;
+}
+
+status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable)
+{
+    status_t result;
+    uint32_t data = 0;
+
+    /* Set the loop mode. */
+    if (enable)
+    {
+        if (mode == kPHY_LocalLoop)
+        {
+            if (speed == kPHY_Speed100M)
+            {
+                data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
+            }
+            else
+            {
+                data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
+            }
+            return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
+        }
+        else
+        {
+            /* First read the current status in control register. */
+            result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
+            if (result == kStatus_Success)
+            {
+                return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
+            }
+        }
+    }
+    else
+    {
+        /* Disable the loop mode. */
+        if (mode == kPHY_LocalLoop)
+        {
+            /* First read the current status in control register. */
+            result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
+            if (result == kStatus_Success)
+            {
+                data &= ~PHY_BCTL_LOOP_MASK;
+                return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
+            }
+        }
+        else
+        {
+            /* First read the current status in control one register. */
+            result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
+            if (result == kStatus_Success)
+            {
+                return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
+            }
+        }
+    }
+    return result;
+}
+
+status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
+{
+    assert(status);
+
+    status_t result = kStatus_Success;
+    uint32_t data;
+
+    /* Read the basic status register. */
+    result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
+    if (result == kStatus_Success)
+    {
+        if ((PHY_BSTATUS_LINKSTATUS_MASK & data) == 0U)
+        {
+            /* link down. */
+            *status = false;
+        }
+        else
+        {
+            /* link up. */
+            *status = true;
+        }
+    }
+    return result;
+}
+
+status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
+{
+    assert(duplex);
+
+    status_t result = kStatus_Success;
+    uint32_t data, ctlReg;
+
+    /* Read the control two register. */
+    result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
+    if (result == kStatus_Success)
+    {
+        data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
+        if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
+        {
+            /* Full duplex. */
+            *duplex = kPHY_FullDuplex;
+        }
+        else
+        {
+            /* Half duplex. */
+            *duplex = kPHY_HalfDuplex;
+        }
+
+        data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
+        if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
+        {
+            /* 100M speed. */
+            *speed = kPHY_Speed100M;
+        }
+        else
+        { /* 10M speed. */
+            *speed = kPHY_Speed10M;
+        }
+    }
+
+    return result;
+}