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<!DOCTYPE html>
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<meta name="description" content="A Fast Forward Error Correction Toolbox (AFF3CT)">
<meta name="author" content="Adrien CASSAGNE">
<title>AFF3CT - A Fast Forward Error Correction Toolbox</title>
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<body>
<nav class="navbar navbar-expand-md navbar-dark fixed-top bg-dark">
<a class="navbar-brand" href="index.html">AFF3CT</a>
<button class="navbar-toggler" type="button" data-toggle="collapse" data-target="#navbarCollapse" aria-controls="navbarCollapse" aria-expanded="false" aria-label="Toggle navigation">
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<li class="nav-item"><a class="nav-link" href="publications.html"><i class="fa fa-newspaper" aria-hidden="true"> </i>Publications</a></li>
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<li class="nav-item"><a class="nav-link" href="download.html"><i class="fas fa-download" aria-hidden="true"> </i>Download</a></li>
<li class="nav-item"><a class="nav-link" href="https://aff3ct.readthedocs.io" target="_blank" onclick="return trackOutboundLink('https://aff3ct.readthedocs.io');"><i class="fas fa-book" aria-hidden="true"> </i>Documentation</a></li>
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<li class="nav-item"><a class="nav-link" href="consortium.html"><i class="fas fa-hands-helping" aria-hidden="true"> </i>Consortium <span class="excl"><i class="fas fa-exclamation"></i></span></a></li>
</ul>
<ul class="navbar-nav navbar-right">
<li class="nav-item"><a class="nav-link" href="comparator.html"><i class="fas fa-chart-bar" aria-hidden="true"> </i>BER/FER Comparator</a></li>
<li class="nav-item"><a class="nav-link" href="turbo_reader.html"><i class="fas fa-code-branch" aria-hidden="true"> </i>Turbo Code Reader</a></li>
<li class="nav-item dropdown">
<a class="nav-link dropdown-toggle" href="#" id="dropdown_hof" data-toggle="dropdown" aria-haspopup="true" aria-expanded="false"><i class="fa fa-list" aria-hidden="true"> </i>Software Decoders Hall of Fame </a>
<div class="dropdown-menu dropdown-menu-right" aria-labelledby="dropdown_hof">
<h6 class="dropdown-header">Synoptic tables</h6>
<a class="dropdown-item" href="hof_turbo.html">Turbo Codes</a>
<a class="dropdown-item" href="hof_ldpc.html">LDPC Codes</a>
<a class="dropdown-item" href="hof_polar.html">Polar Codes</a>
</div>
</li>
</ul>
</div>
</nav>
<div class="jumbotron">
<div class="container marketing">
<h1 class="display-4">A Fast Forward Error Correction Toolbox!</h1>
<p class="lead"><strong>AFF3CT</strong> is an <strong>Open-source</strong> software (MIT license) dedicated to the <strong>Forward Error Correction</strong> (FEC or channel coding) simulations. It is written in <strong>C++11</strong> and it supports a large range of codes: from the well-spread <strong>Turbo codes</strong> to the new <strong>Polar codes</strong> including the <strong>Low-Density Parity-Check (LDPC)</strong> codes. A particular emphasis is given to <strong>the simulation throughput performance</strong> (hundreds of Mb/s on today's CPUs) and the portability of the code.</p>
<hr class="my-4">
<p>The source code is freely available and hosted by GitHub.</p>
<a class="btn btn-primary btn-lg" href="https://github.com/aff3ct/aff3ct" role="button" target="_blank" style="margin-top:5px" onclick="return trackOutboundLink('https://github.com/aff3ct/aff3ct');"><i class="fab fa-github fa-lg" aria-hidden="true"> </i>Source code on GitHub »</a>
<a class="btn btn-primary btn-lg" href="download.html" role="button" style="margin-top:5px"><i class="fas fa-cloud-download-alt fa-lg" aria-hidden="true"> </i>Download »</a>
</div>
</div>
<div class="container marketing">
<div class="row">
<div class="col-md-12">
<div class="alert alert-primary" role="alert">
<strong><u>[New!] Job offer (2021-05-17)</u></strong><br/>
We are looking for an engineer to work with us in the AFF3CT development. If you are interested, please <a target="_blank" href="resources/job/Fiche_Poste_Ing_EVASION.pdf" onclick="return trackOutboundLink('https://aff3ct.github.io/resources/job/Fiche_Poste_Ing_EVASION.pdf');">download the job offer <i class="fas fa-file-pdf" aria-hidden="true"></i></a> (in French) and contact us.
The position is expected to start in early June 2021.
</div>
<div class="alert alert-danger" role="alert">
<strong><u>Call for Consortium (2020-03-16)</u></strong><br/>
We are currently launching a call for the <strong>AFF3CT consortium</strong>, please refer to the dedicated page if you are interested in.
<br/>
<a class="btn btn-danger" href="consortium.html" role="button" style="margin-top:5px"><i class="fas fa-hands-helping fa-lg" aria-hidden="true"> </i>AFF3CT Consortium Call</a>
</div>
</div>
</div>
<hr class="featurette-divider-small">
<div class="row featurette">
<div class="col-md-6">
<h2 class="featurette-heading">Run simulations on your computer. <span class="text-muted">Experiment various configurations.</span></h2>
<p class="lead">Choose between <strong>Polar</strong>, <strong>Turbo</strong>, <strong>LDPC</strong> (Low-Density Parity-Check), <strong>RSC</strong> (Recursive Systematic Convolutional), <strong>TPC</strong> (Turbo Product Code), <strong>BCH</strong> (Bose, Ray-Chaudhuri and Hocquenghem), <strong>RS</strong> (Reed-Solomon), <strong>Repetition</strong> and <strong>RA</strong> (Repeat and Accumulate) codes. Play with a set of decoders with different complexities and characteristics. <a href="fec_libraries.html">See comparison with other FEC libraries</a>.</p>
</div>
<div class="col-md-6">
<img class="featurette-image img-fluid d-block mx-auto" src="images/aff3ct2.png" alt="AFF3CT run">
</div>
</div>
<hr class="featurette-divider">
<div class="row featurette">
<div class="col-md-6 order-md-5">
<h2 class="featurette-heading">Compare the decoding performance of BER/FER references. <span class="text-muted">Available online.</span></h2>
<p class="lead">Browse a large database of references that have been <strong>pre-simulated with AFF3CT</strong>. Many channel codes and configurations are available. <strong>Load your personal results from files</strong> and see how they perform. <a href="comparator.html">Start using the BER/FER comparator</a>.</p>
</div>
<div class="col-md-6 order-md-1">
<img class="featurette-image img-fluid d-block mx-auto" src="images/comparator_preview.png" alt="BER/FER comparator preview">
</div>
</div>
<a name="performances"></a>
<hr class="featurette-divider">
<div class="row featurette">
<div class="col-md-7">
<h2 class="featurette-heading">Unleash the power of your CPU <span class="text-muted">with fixed-point arithmetic.</span></h2>
<p class="lead">AFF3CT takes advantage of the <strong>8-bit</strong> and <strong>16-bit</strong> built-in fixed-point and saturated arithmetic of your CPU. This enables <strong>high performance</strong> on General Purpose Processors while it gives you the opportunity <strong>to estimate the decoding performance on real hardware</strong>. <a href="#performances" id="performancesId">See simulator throughput performances on modern architectures.</a></p>
</div>
<div class="col-md-5">
<img class="featurette-image img-fluid d-block mx-auto" src="images/bfer/bfer_6144.svg" alt="FER curves">
</div>
</div>
<hr class="featurette-divider">
<div class="row featurette">
<div class="col-md-10 order-md-5">
<h2 class="featurette-heading">A Cross-platform <span class="text-muted">and Open-source software.</span></h2>
<p class="lead">AFF3CT runs on <strong>Linux <i class="fab fa-linux" aria-hidden="true"></i></strong>, <strong>macOS <i class="fab fa-apple" aria-hidden="true"></i></strong> and <strong>Windows <i class="fab fa-windows" aria-hidden="true"></i></strong>. It has been optimized for <strong>x86</strong> targets (with the <strong>SSE</strong> and <strong>AVX</strong> set of instructions) and for <strong>ARM</strong> devices (with the <strong>NEON</strong> set of instructions). The code SIMDization rest upon the <a href="https://github.com/aff3ct/MIPP" target="_blank" onclick="return trackOutboundLink('https://github.com/aff3ct/MIPP');">MIPP wrapper</a>. AFF3CT is Open-source and it is currently developed, the code is written in <strong>C++11</strong> style where it intensively uses <strong>the template meta-programming technique</strong>.</p>
</div>
<div class="col-md-2 order-md-1">
<img class="featurette-image img-fluid d-block mx-auto" src="images/cross_platform.png" alt="Cross-platform">
</div>
</div>
<!-- Modal -->
<div class="modal fade" id="performancesModal" tabindex="-1" role="dialog" aria-labelledby="performancesModalLabel" aria-hidden="true">
<div class="modal-dialog mw-100 w-75" role="document">
<div class="modal-content">
<div class="modal-header">
<h4 class="modal-title" id="performancesModalLabel">AFF3CT simulation speedup and throughput on modern architectures</h4>
<button type="button" class="close" data-dismiss="modal" aria-label="Close">
<span aria-hidden="true">×</span>
</button>
</div>
<div class="modal-body">
<div class="row">
<div class="col-xl-12">
<div class="table-responsive">
<table class="table table-striped table-hover">
<thead class="thead-inverse">
<tr>
<!-- CPU --> <th class=""><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Central Process Unit">CPU</span></th>
<!-- Vendor --> <th class=""><span>Vendor</span></th>
<!-- Archi --> <th class=""><span>Architecture</span></th>
<!-- SIMD --> <th class=""><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Single Instruction Multiple Data">SIMD</span></th>
<!-- SIMD length --> <th class=""><span>SIMD length</span></th>
<!-- Proc. --> <th class=""><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Number of processors"># Proc.</span></th>
<!-- Cores --> <th class=""><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Number of cores per processor"># Cores per proc.</span></th>
<!-- Freq. --> <th class=""><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="CPU clock frequency">Freq. (GHz)</span></th>
<!-- SMT --> <th class=""><span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Simultaneous Multi-Threading or Hyper-Threading">SMT</span></th>
<!-- TB --> <th class=""><span>Turbo Boost</span></th>
</tr>
</thead>
<tbody>
<tr>
<!-- CPU --> <td><a href="https://en.wikichip.org/wiki/cavium/thunderx2/cn9975" target="_blank" onclick="return trackOutboundLink('https://en.wikichip.org/wiki/cavium/thunderx2/cn9975');">ThunderX2 CN9975</a></td>
<!-- Vendor --> <td>Cavium</td>
<!-- Archi --> <td>ARMv8.1</td>
<!-- SIMD --> <td>NEON</td>
<!-- SIMD length --> <td>128-bit</td>
<!-- Proc. --> <td>2</td>
<!-- Cores --> <td>28</td>
<!-- Freq. --> <td>2.00</td>
<!-- SMT --> <td>4</td>
<!-- TB --> <td>Unavailable</td>
</tr>
<tr>
<!-- CPU --> <td><a href="https://ark.intel.com/fr/products/94034/Intel-Xeon-Phi-Processor-7230-16GB-1-30-GHz-64-core-" target="_blank" onclick="return trackOutboundLink('https://ark.intel.com/fr/products/94034/Intel-Xeon-Phi-Processor-7230-16GB-1-30-GHz-64-core-');">Xeon Phi 7230</a></td>
<!-- Vendor --> <td>Intel</td>
<!-- Archi --> <td>Knights Landing</td>
<!-- SIMD --> <td>AVX-512F</td>
<!-- SIMD length --> <td>512-bit</td>
<!-- Proc. --> <td>1</td>
<!-- Cores --> <td>64</td>
<!-- Freq. --> <td>1.30</td>
<!-- SMT --> <td>4</td>
<!-- TB --> <td>On</td>
</tr>
<tr>
<!-- CPU --> <td><a href="https://ark.intel.com/fr/products/81908/Intel-Xeon-Processor-E5-2680-v3-30M-Cache-2-50-GHz-" target="_blank" onclick="return trackOutboundLink('https://ark.intel.com/fr/products/81908/Intel-Xeon-Processor-E5-2680-v3-30M-Cache-2-50-GHz-');">Xeon E5-2680 v3</a></td>
<!-- Vendor --> <td>Intel</td>
<!-- Archi --> <td>Haswell</td>
<!-- SIMD --> <td>AVX2</td>
<!-- SIMD length --> <td>256-bit</td>
<!-- Proc. --> <td>2</td>
<!-- Cores --> <td>12</td>
<!-- Freq. --> <td>2.50</td>
<!-- SMT --> <td>1</td>
<!-- TB --> <td>Off</td>
</tr>
<tr>
<!-- CPU --> <td><a href="https://ark.intel.com/products/120485/Intel-Xeon-Gold-6140-Processor-24-75M-Cache-2-30-GHz-" target="_blank" onclick="return trackOutboundLink('https://ark.intel.com/products/120485/Intel-Xeon-Gold-6140-Processor-24-75M-Cache-2-30-GHz-');">Xeon Gold 6140</a></td>
<!-- Vendor --> <td>Intel</td>
<!-- Archi --> <td>Skylake</td>
<!-- SIMD --> <td>AVX-512F+BW</td>
<!-- SIMD length --> <td>512-bit</td>
<!-- Proc. --> <td>2</td>
<!-- Cores --> <td>18</td>
<!-- Freq. --> <td>2.30</td>
<!-- SMT --> <td>2</td>
<!-- TB --> <td>On</td>
</tr>
<tr>
<!-- CPU --> <td><a href="https://ark.intel.com/products/120487/Intel-Xeon-Gold-6142-Processor-22M-Cache-2-60-GHz-" target="_blank" onclick="return trackOutboundLink('https://ark.intel.com/products/120487/Intel-Xeon-Gold-6142-Processor-22M-Cache-2-60-GHz-');">Xeon Gold 6142</a></td>
<!-- Vendor --> <td>Intel</td>
<!-- Archi --> <td>Skylake</td>
<!-- SIMD --> <td>AVX-512F+BW</td>
<!-- SIMD length --> <td>512-bit</td>
<!-- Proc. --> <td>2</td>
<!-- Cores --> <td>16</td>
<!-- Freq. --> <td>2.60</td>
<!-- SMT --> <td>1</td>
<!-- TB --> <td>Off</td>
</tr>
</tbody>
</table>
</div>
</div>
</div>
<div class="mb-4"></div>
<div class="row">
<div class="col-xl-6">
<img src="images/speedup.svg" alt="speedup" title="AFF3CT Simulator Speedups" class="img-fluid d-block mx-auto" style="width: 100%">
</div>
<div class="col-xl-6">
<img src="images/throughput.svg" alt="throughput" title="AFF3CT Simulator Throughputs" class="img-fluid d-block mx-auto" style="width: 100%">
</div>
</div>
<div class="mb-4"></div>
<div class="row">
<div class="col-xl-12">
<p>
A N=2048 and K=1723 Polar code (<span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Fully Adaptive Successive Cancellation List">FA-SCL</span> decoder, L=32, 32-bit GZip <code>0x04C11DB7</code> <span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Cyclic Redundancy Check">CRC</span>) is simulated with a <span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Binary Phase-Shift Keying">BPSK</span> modulation and over an <span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Additive White Gaussian Noise">AWGN</span> channel (E_b/N_0 = 4.5 dB, <span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Bit Error Rate">BER</span> = 4.34e-10). The frozen bits of the Polar code have been generated with the <span class="tt" data-toggle="tooltip" data-placement="top" data-html="true" title="Gaussian Approximation">GA</span> method. The communication chain is fully vectorized with the <a href="https://github.com/aff3ct/MIPP" target="_blank" onclick="return trackOutboundLink('https://github.com/aff3ct/MIPP');">MIPP wrapper</a> and multi-threaded with C++11 threads. For all the CPU targets, the code has been compiled with the <a href="https://gcc.gnu.org/gcc-8/" target="_blank" onclick="return trackOutboundLink('https://gcc.gnu.org/gcc-8/');">C++ GNU compiler version 8.2</a>, with the following optimization flags: <code>-O3 -funroll-loops -march=native</code>.
</p>
</div>
</div>
<div class="mb-4"></div>
<hr>
<div class="row">
<div class="col-xl-12">
<div class="shell-wrap">
<p class="shell-top-bar">AFF3CT command line (<a href="https://github.com/aff3ct/aff3ct/tree/4d14567865c91f571dd91cfc7504f38d998bf6ab" target="_blank" onclick="return trackOutboundLink('https://github.com/aff3ct/aff3ct/tree/4d14567865c91f571dd91cfc7504f38d998bf6ab');">v2.2.2-14-g4d14567</a>)</p>
<ul class="shell-body">
<li><span class="aff3ct">aff3ct</span> -p <span class="num">8</span> --sim-type <span class="str">BFER</span> -m <span class="num">4.5</span> -M <span class="num">4.5</span> -C <span class="str">POLAR</span> -K <span class="num">1755</span> -N <span class="num">2048</span> --src-type <span class="str">AZCW</span> --crc-type <span class="str">32-GZIP</span> --crc-implem <span class="str">FAST</span> --enc-fb-gen-method <span class="str">GA</span> --chn-type <span class="str">AWGN</span> --chn-implem <span class="str">FAST</span> --qnt-type <span class="str">POW2</span> --qnt-implem <span class="str">FAST</span> --qnt-bits <span class="num">6</span> --qnt-dec <span class="num">1</span> --dec-type <span class="str">ASCL</span> --dec-implem <span class="str">FAST</span> --dec-simd <span class="str">INTRA</span> -L <span class="num">32</span> --dec-polar-nodes <span class="str">"{R0,R0L,R1,REP_2-8,REPL,SPC_4}"</span></li>
</ul>
</div>
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