Merge branch 'llvm-integer-cast-ops' of https://github.com/opencompl/…

…lean-mlir into llvm-integer-cast-ops

SSA/Projects/InstCombine/tests/logs/2006-12-08-Select-ICmp.txt

@@ -10,6 +10,7 @@
 <<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 =======
 4: "visible" has unsupported operation: builtin.unregistered: llvm.select
 
@@ -20,6 +21,8 @@
 
 =======
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 1: "determinant"
 5: "determinant" is empty
 

SSA/Projects/InstCombine/tests/logs/2010-03-03-ExtElim.txt

@@ -19,6 +19,7 @@
 <<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 =======
 4: "PR16462_1" has unsupported operation after optimization: builtin.unregistered: llvm.select
 
@@ -31,6 +32,8 @@
 
 =======
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 4: "PR16462_1" has unsupported operation after optimization: builtin.unregistered: llvm.icmp
 
 1: "PR16462_2"
@@ -43,6 +46,7 @@
 <<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 =======
 4: "PR16462_2" has unsupported operation after optimization: builtin.unregistered: llvm.select
 
@@ -53,5 +57,7 @@
 
 =======
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 4: "PR16462_2" has unsupported operation after optimization: builtin.unregistered: llvm.icmp
 

SSA/Projects/InstCombine/tests/logs/and-xor-or.txt

@@ -395,11 +395,14 @@
 
 1: "sext_or_chain_two_uses1"
 7: "sext_or_chain_two_uses1" is unchanged by InstCombine
+<<<<<<< HEAD
 
 <<<<<<< HEAD
 <<<<<<< HEAD
 =======
 4: "sext_or_chain_two_uses1" has unsupported operation: llvm.udiv
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 
 4: "sext_or_chain_two_uses1" has unsupported operation: llvm.udiv
 
@@ -408,11 +411,14 @@
 >>>>>>> edb64a33 (Updated tests)
 1: "sext_or_chain_two_uses2"
 7: "sext_or_chain_two_uses2" is unchanged by InstCombine
+<<<<<<< HEAD
 
 <<<<<<< HEAD
 <<<<<<< HEAD
 =======
 4: "sext_or_chain_two_uses2" has unsupported operation: llvm.udiv
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 
 4: "sext_or_chain_two_uses2" has unsupported operation: llvm.udiv
 

SSA/Projects/InstCombine/tests/logs/and.txt

@@ -305,15 +305,19 @@
 <<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 4: "test31" has unsupported operation after optimization: builtin.unregistered: llvm.zext
 =======
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 2: llvm.func
 2: llvm.mlir.constant
 2: llvm.mlir.constant
 2: llvm.zext
 2: llvm.shl
 2: llvm.and
 2: llvm.return
+<<<<<<< HEAD
 >>>>>>> bd0a83c7 (Updated the generated tests)
 
 1: "and_demanded_bits_splat_vec"
@@ -326,6 +330,8 @@
 >>>>>>> 4bf2f937 (Re-ran the sccripts)
 =======
 4: "test31" has unsupported operation after optimization: builtin.unregistered: llvm.zext
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 
 1: "and_demanded_bits_splat_vec"
 8: "and_demanded_bits_splat_vec" contains vectors which are unsupported
@@ -935,6 +941,7 @@
 
 4: "signbit_splat_mask_use1" has unsupported operation: builtin.unregistered: llvm.icmp
 
+<<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
 =======
@@ -943,6 +950,8 @@
 >>>>>>> 4bf2f937 (Re-ran the sccripts)
 =======
 >>>>>>> edb64a33 (Updated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 1: "signbit_splat_mask_use2"
 4: "signbit_splat_mask_use2" has unsupported operation: llvm.call
 
@@ -1426,6 +1435,7 @@
 <<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 4: "and_zext" has unsupported operation after optimization: builtin.unregistered: llvm.zext
 
 1: "and_zext_commuted"
@@ -1443,17 +1453,28 @@
 4: "and_zext_commuted" has unsupported operation after optimization: builtin.unregistered: llvm.zext
 >>>>>>> edb64a33 (Updated tests)
 =======
+=======
 2: llvm.func
 2: llvm.zext
 2: llvm.and
 2: llvm.return
 
+1: "and_zext_commuted"
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
+2: llvm.func
+2: llvm.zext
+2: llvm.and
+2: llvm.return
+<<<<<<< HEAD
+
 1: "and_zext_commuted"
 2: llvm.func
 2: llvm.zext
 2: llvm.and
 2: llvm.return
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 
 1: "and_zext_multiuse"
 4: "and_zext_multiuse" has unsupported operation: llvm.call

SSA/Projects/InstCombine/tests/logs/apint-shift.txt

@@ -230,9 +230,12 @@
 =======
 
 1: "test15a"
+<<<<<<< HEAD
 4: "test15a" has unsupported operation after optimization: builtin.unregistered: llvm.zext
 >>>>>>> edb64a33 (Updated tests)
 =======
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 2: llvm.func
 2: llvm.mlir.constant
 2: llvm.mlir.constant
@@ -241,7 +244,10 @@
 2: llvm.zext
 2: llvm.shl
 2: llvm.return
+<<<<<<< HEAD
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 
 1: "test16"
 4: "test16" has unsupported operation: builtin.unregistered: llvm.icmp

SSA/Projects/InstCombine/tests/logs/binop-cast.txt

@@ -11,13 +11,19 @@
 <<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 4: "and_sext_to_sel" has unsupported operation after optimization: builtin.unregistered: llvm.sext
 =======
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 2: llvm.func
 2: llvm.sext
 2: llvm.and
 2: llvm.return
+<<<<<<< HEAD
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 
 1: "and_sext_to_sel_constant_vec"
 8: "and_sext_to_sel_constant_vec" contains vectors which are unsupported
@@ -44,6 +50,7 @@
 1: "and_sext_to_sel_multi_use"
 4: "and_sext_to_sel_multi_use" has unsupported operation: llvm.call
 
+<<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
 =======
@@ -63,6 +70,11 @@
 >>>>>>> 4bf2f937 (Re-ran the sccripts)
 =======
 >>>>>>> edb64a33 (Updated tests)
+=======
+1: "and_sext_to_sel_multi_use_constant_mask"
+4: "and_sext_to_sel_multi_use_constant_mask" has unsupported operation: llvm.call
+
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 1: "and_not_sext_to_sel"
 4: "and_not_sext_to_sel" has unsupported operation: llvm.call
 
@@ -97,13 +109,19 @@
 <<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 4: "or_sext_to_sel" has unsupported operation after optimization: builtin.unregistered: llvm.sext
 =======
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 2: llvm.func
 2: llvm.sext
 2: llvm.or
 2: llvm.return
+<<<<<<< HEAD
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 
 1: "or_sext_to_sel_constant_vec"
 8: "or_sext_to_sel_constant_vec" contains vectors which are unsupported
@@ -179,6 +197,7 @@
 <<<<<<< HEAD
 <<<<<<< HEAD
 <<<<<<< HEAD
+<<<<<<< HEAD
 4: "and_add_bool_to_select" has unsupported operation after optimization: builtin.unregistered: llvm.zext
 =======
 4: "and_add_bool_to_select" has unsupported operation: builtin.unregistered: llvm.select
@@ -187,13 +206,18 @@
 4: "and_add_bool_to_select" has unsupported operation after optimization: builtin.unregistered: llvm.zext
 >>>>>>> edb64a33 (Updated tests)
 =======
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 2: llvm.func
 2: llvm.mlir.constant
 2: llvm.zext
 2: llvm.add
 2: llvm.and
 2: llvm.return
+<<<<<<< HEAD
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 
 1: "and_add_bool_no_fold"
 4: "and_add_bool_no_fold" has unsupported operation: builtin.unregistered: llvm.icmp
@@ -205,6 +229,7 @@
 
 1: "and_add_bool_to_select_multi_use"
 <<<<<<< HEAD
+<<<<<<< HEAD
 4: "and_add_bool_to_select_multi_use" has unsupported operation after optimization: builtin.unregistered: llvm.zext
 =======
 4: "and_add_bool_no_fold" has unsupported operation: builtin.unregistered: llvm.select
@@ -222,12 +247,17 @@
 4: "and_add_bool_to_select_multi_use" has unsupported operation after optimization: builtin.unregistered: llvm.zext
 >>>>>>> edb64a33 (Updated tests)
 =======
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7
 2: llvm.func
 2: llvm.mlir.constant
 2: llvm.zext
 2: llvm.add
 2: llvm.and
 2: llvm.add
 2: llvm.return
+<<<<<<< HEAD
 >>>>>>> bd0a83c7 (Updated the generated tests)
+=======
+>>>>>>> 3d133a8a07b3d7eb59d68a5bf0131917e72bade7