report_benchmark.py: fix Dhrystone cycles after PR #2484 #2488
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after commit 111df66 the CVA6 configuration used for Dhrystone benchmark is rv64gc_zba_zbb_zbs_zbc instead of rv64imafdc_zicsr_zifencei therefore the number of cycles is reduced
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after commit 111df66 the CVA6 configuration used for Dhrystone benchmark is rv64gc_zba_zbb_zbs_zbc instead of rv64imafdc_zicsr_zifencei
therefore the number of cycles is reduced