Merge pull request #693 from pascalgouedo/dd_pgo

CV32E40Pv2 final updates.

Project-Descriptions-and-Plans/CV32E40Pv2/Milestone-data/RTL_v1.8.3/index.html

@@ -9,7 +9,7 @@
     <h1>Documentation for CORE-V verification</h1>
     <p><b>Simulation verification</b> methodology used for all CORE-V cores is described in following document:  <a href="https://docs.openhwgroup.org/projects/core-v-verif/en/latest/quick_start.html">CORE-V Verification Strategy</a></p>
     <p>For CV32E40Pv2, <b>RISC-V ISA Formal Verification</b> methodology was used and is described <a href="https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_RISCV_vPlan_v1.1.pdf">here</a>.</p>
-    <p>Documentation for the various CORE-V cores are maintained in <a href="https://github.com/openhwgroup/core-v-docs">core-v-docs</a>, the OpenHW Group's CORE-V documentation repo.</p>
+    <p>Documentation for the various CORE-V cores are maintained in <a href="https://github.com/openhwgroup/programs">programs</a>, the OpenHW Group's CORE-V documentation repo.</p>
     <p></p>
     <p>As much as is practical, we try to add documentation where you actually use it.<br>
        Most directories in this repository will have a <b>README.md</b> and GitHub

docs/source/cores.rst

@@ -32,11 +32,11 @@ RTL Frozen Cores
 
 `(Released) CORE-V CV32E40Pv1 User Manual <https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/cv32e40p_v1.0.0_doc/>`_.
 
+`(v1.8.3) CORE-V CV32E40Pv2 User Manual <https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/cv32e40p_v1.8.3`_.
+
 RTL In Development
 ##################
 
-`(Draft) CORE-V CV32E40Pv2 User Manual <https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/>`_.
-
 `(Draft) CORE-V CV32E40S User Manual <https://docs.openhwgroup.org/projects/cv32e40s-user-manual/en/latest/>`_.
 
 `(Draft) CORE-V CV32E40X User Manual <https://docs.openhwgroup.org/projects/cv32e40x-user-manual/en/latest/>`_.