diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 1cd85eec3e..78ee8b2ca7 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -44,6 +44,7 @@ set CM3_CTIBASE		{0x3C016000}
 
 # sysctrl power-ap unlock offsets
 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
+set _sysctrl_ap_num 7
 
 # All the ARMV8s are the next processors.
 #		   CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
@@ -266,9 +267,11 @@ set _TARGETNAME $_CHIPNAME.cpu
 set _CTINAME $_CHIPNAME.cti
 
 # sysctrl is always present
-cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
+	-ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
 
-target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
+	-ap-num $_sysctrl_ap_num -defer-examine \
 	-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
 
 $_TARGETNAME.sysctrl configure -event reset-assert { }