ref design 2022.05 - change clock frequency in CCC_FIC_x_CLK?

[rroulleau]

I am trying to change the clock frequency of CLOCK_AND_RESET->FIC_2_CLK in libero ref 2022.05 release. When I change the clock frequency to let's say 25MHz the board running linux no longer boot and the HSS is stuck to line "[3.662371] HSS_MMCInit(): Attempting to select SDCARD" without the 'Passed'.
In previous release I did not encounter this problem. I notice in the ref 2022.05, each FIC_x_CLK is connected to the MSS FIC_x_ACLK, is it link with some setting in the MSS or HSS? or Does the FIC_x_ACLK has a constraint on the clock frequency?
Thanks,

[hughbreslin]

Hey @rroulleau

Have you got the DLL enabled for the FIC 2 clock? The DLL is enabled by default as the clock frequency is >= 125MHz, if you drop the frequency below this the DLL needs to be bypassed / disabled.

This is an MSS configurator change and you will need to update the MSS component in your Libero design for it to have an effect (the DLL settings aren't exported to the XML and are contained in the bitstream) and re-generate your bitstream. When you bypass the DLL its lock signal is tied high.

I would say the HSS is getting stuck trying to access the SDIO register on FIC3, if any of the DLLs don't lock the fabric will be held in reset and the MSS will trap trying to access the FIC.

[rroulleau]

Thanks a lot for the explanation and the quick response!