Error in AXI Address SHIM used for PCIe? #176
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Hi, I had issues to get PCIe root complex running. It noticed it works on older reference designs (2021.11 or older) but not on newer versions. The difference is that the AXI address shim was changed to verilog code in newer designs. Previous reference designs added the address offset using AND and OR gates. But the logic differs between old block design and the verilog code. The verilog code adds an AND between AWVALID and WVALID
The older designs added an OR connection between AWVALID and WVALID. I got the newer reference design (2022.05) running when I change the verilog code to:
Is there a reason the offset is added as combination of AWVALID and WVALID? AWADDR should not be depending on WVALID. Best regards, |
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Replies: 2 comments 2 replies
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Hi @abuerkler Thanks for pointing this out.
This was done some time ago - there was a reason but I cannot remember off the top of my head. You're correct there shouldn't be a dependency here but I believe there were some issues getting endpoints to come up without this, it hasn't seemed to have caused an issue until now. Can I check what endpoint you're using? Just as an FYI we are going to be updating the address shim in an upcoming release and this can be looked at again as part of that work. |
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Hey @abuerkler the AXI address shim has been updated and is no longer using the WVALID signal :) This is available on our master branch now. Just to note the shim has been changed to offset addresses to 0x14_xxxx_xxxx instead of 0x10_xxxx_xxxx (i.e the non-cached DDR memory). This won't be fully supported by software until our release at the end of this month but just to highlight the fix is implemented and available. Its a minor change to switch the shim to use 0x10_xxxx_xxxx again if you want to use this HDL. |
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Hey @abuerkler the AXI address shim has been updated and is no longer using the WVALID signal :) This is available on our master branch now.
Just to note the shim has been changed to offset addresses to 0x14_xxxx_xxxx instead of 0x10_xxxx_xxxx (i.e the non-cached DDR memory). This won't be fully supported by software until our release at the end of this month but just to highlight the fix is implemented and available. Its a minor change to switch the shim to use 0x10_xxxx_xxxx again if you want to use this HDL.