Accessing MSS peripherals from the FPGA fabric

[andrenemat]

Does the MSS in PolarFire Soc have option to provide access to its peripherals from FPGA fabric via one of its FICs i.e. can any of FIC0/1/2 as a target be used to access the MSS internal peripherals?
As far as we can see from the generated Memory map the address space for the FIC Targets is well beyond the space where the peripherals reside.

[hughbreslin]

Hey @andrenemat

once you have the MPU configured correctly you should be able to access the MSS peripherals from at least FIC 0 / FIC 1 from the table below (I can't entirely remember what CPLEX-MMIO represents, I'm pretty sure its the peripherals so FIC 2 should also work):

	FIC0-FM	FIC1-FM	FIC2-FM
FIC0-FS	Y	Y	N
FIC1-FS	Y	Y	N
FIC3-FS	Y	Y	N
Athena	Y	Y	N
AHB0	Y	Y	N
AHB1	Y	Y	N
DDR-NC	Y	Y	Y
CPLEX-MMIO	Y	Y	Y

This may be an enhancement for the memory map generation so it supports fabric initiators being at the top of the address tree if it isn't generating correctly

[andrenemat]

I must be missing something.

The address space for FIC 0 is 0x60000000 to 0x7FFFFFFF, for FIC1 it is 0xE0000000 to 0xFFFFFFFF, and for FIC3 it is 0x40000000 to 0x5FFFFFFF. The peripherals are somewhere in between 0x20000000 and 0x20126FFF. It appears that the address space for peripherals is not accessible by any of the FICs.

Unless I have to use the software to read data from say the peripheral address space and send it out on the FIC address space and do the reverse for writes? Or can I set up a DMA to transfer the data between the FIC address space and the peripheral address space?

Can you please point me in the right direction how this should work?

[hughbreslin]

Those are the addresses for the FIC 0, FIC 1 and FIC 3 as MSS initiators and a fabric target. In this case we’re talking about fabric initiators and an MSS target. For example FIC 2 is used to transfer data to DDR in the vectorblox reference design example - if we used the MSS initiator address ranges this should be impossible but it works as the FIC targets have different addresses ranges to the FIC initiators.

[andrenemat]

Thanks a lot, good point. So if I set up say FIC0 initiator in the Fabric and then FIC0 target in the MSS, I can set the target address range to say 20000000 to 20000FFF for MMUART0?

[andrenemat]

It is clear that the Initiator’s address space differs from the one available at the Target, it’s completely understandable and that’s how it should be, no issues accessing DDR memory space of the MSS.
My question is how do I make APB0 and APB1 addresses within MSS visible via FIC0/1/2 Target channels. Or, should I consider those visible by default, so whenever I query the peripheral’s address, let say 0x2010_8000 of the I2C_B_LO, the request will be properly routed, though that address within Memory Map doesn’t appear as visible on any of FICx channels?

[hughbreslin]

The only thing that stands in the way is the MPU to the AXI switch, it’s shown in figure 3-1 of the TRM. Once the MPU is configured correctly you should have access to the address space you need. It’s not configured by default in the reference design so you should have access, if you have any issues I would check the configuration of the MPU and ensure your FIC has access to the address space you require.

[andrenemat]

Thanks @hughbreslin . So when I implement an AXI Initiator in the fabric, what address should I exactly write to it for example to get to 0x2010_8000 of the I2C_B_LO? How can we tell the AXI switch that the data is going to S5 and from there to the APB bus?