How to configure PLL(CCC)

[Usutatsu]

I want to know how to configure the PLL(CCC).
CCC has 4 unit, CCC_NW, CCC_NN, CCC_SW and CCC_SN.

The latest reference designe of ICICLE Kit is using CCC_NW as FPGA fabric clock generator.
However I want to use CCC_SW or CCC_SN as FPGA fabric clock gerator and output fabric clock through GPIO.

Where do I change to set which part of the CCC to use?

Can anyone help me know what it is?

[MuralidharPMiV]

The PolarFireSoc has MSS and Fabric integrated. The MSS can be driven either from dedicated MSS Ref Clock or the North West CCC 3 and 4 output ports.

If you want to use the other CCCs in the Fabric side, you may use them. You need to just instantiate them in LiberoSoc through the catalog. You can constrain the CCC location using the Floor Planner PDC of the Constraint manager.

[MuralidharPMiV]

Please look at the set_location constraint to fix the CCC in a particular location in the FPGA.
Please refer to the below link
http://coredocs.s3.amazonaws.com/Libero/2022_2/Tool/pf_pdc_ug.pdf

An example constraint for the SW CCC is below
set_location -inst_name PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0 -fixed false -x 2460 -y 5

To locate the CCC, you may use the Floor Planner in the constraint manager of the LiberoSoc and when we hover over a FPGA resource, we will be able to find the location of the resource.

An example of finding the SW CCC coordinates of the CCC is as below

[MuralidharPMiV]

The simple way to assign the CCCs in a particular location is to use the Preferred input pins of the particular CCCs in different locations of the FPGA. Please look at the section 4 in the PolarFireSoc Clocking resources User guide.
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/UserGuides/Microchip_PolarFire_FPGA_and_PolarFire_SoC_FPGA_Clocking_Resources_User_Guide_VB.pdf
The Public pin Assignment tables provide the pin descriptions of various pins and you will be able to find out the preferred CCC input pins for the Various CCCs in different locations.

[Usutatsu]

Thank you for your comments.
I followed your advice and changed the contents of the NW_PLL.pdc file to use CCC_SW.

We then added a port to the design to output CCC_SW_PLL0_OUT0, the output of CCC_SW, from the GPIO, and set the added port to connect to the pins of C10.
However, when I run place and route, it seems that QSPI_CLK is connected to C10 and CCC_SW_PLL0_OUT0 is connected to V12.
Is there any way to fix this?