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Hi, Yes, the processor supports 64-bit writes. When doing a write to DDR, the DDR controller calculates the ECC bits per beat ( data width). If the data being written is less than the data width of DQ, (e.g. 8-bits being written by software to a x32 (36 inc ECC) a read modify write is carried out by the controller, so the ECC is calculated correctly before being written. |
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Is DDR data with ECC concatenated into 64-bit for Polarfire SoC? For example, concatenating two 32-bit data into 64 bit data for ECC.
Does the processor support 64-bit? If so, is processing 64-bit data more efficient than processing 32-bit data?
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