MSS GPIO2 pin using a PLIC interrupt with polarfire SOC

[govindsi]

We have MSS GPIO2 port 21 which is connected as interrupt signals to MSS_INT_F2M port to be used a PLIC interrupt.
This is being used a IRQ line for an i2c client.

GPIO2_21 -> MSS:MSS_INT_F2M[7:7]

FPGA side:

sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO2_21_BIBUF}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_M2F_21" "GPIO2_21_BIBUF:D"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_OE_M2F_21" "GPIO2_21_BIBUF:E"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_F2M_21" "GPIO2_21_BIBUF:Y"}
sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO2_21}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:MSS_INT_F2M[7:7]" "GPIO2_21_BIBUF:Y"}

Linux side Mapping:

Interrupt configuration in i2c client dtsi.

         interrupt-parent = <&plic>;
         interrupts = <125>;

As per TRM ( page 102) https://www.microsemi.com/document-portal/doc_download/1245725-polarfire-soc-fpga-mss-technical-reference-manual

MSS_INT_F2M[31:0] 32 [136:105] [149:118] — [47:16] [47:16] [47:16] [47:16]

IRQ no should be ------->118 + 7 (MSS:MSS_INT_F2M[7:7] ) = 125

GPIO configuration is valid.

root@buildroot:/sys/class/gpio# ls
export gpiochip476 gpiochip480 unexport
root@buildroot:/sys/class/gpio# echo 501 > export ----------------> 480 + 21(gpio21) = 501
root@buildroot:/sys/class/gpio/gpio501# cat direction
in

Issue: there is interrupt flood on GPIO21, which is not expected and later interrupt gets masked due to the flood.
Seems its still missing some mapping.
What could be missing to map the MSS GPIO2 pin 21 as PLIC interrupt?

Some of the key registers dumped and looks good.
SUBBLK_CLOCK_CR=3ffdffff
SUBBLK_RESET_CR=0
gpio_cfg= 0x02
GPIO_INTERRUPT_FAB_CR=0 and tried with GPIO_INTERRUPT_FAB_CR=ffffffff as well

[hughbreslin]

Hey @govindsi are you trying to map the GPIO as an interrupt or the f2m? They're separate things, my understanding is you're driving the f2m input from the GPIO bibuf but it looks like you're configuring the GPIO as an input which is confusing me.

The F2M interrupt is separate to the GPIO interrupt.

[govindsi]

Hello @hughbreslin , I am trying to map the f2m. Pls ignore gpio i/p configuration.

Initially i tried with using GPIO interrupt without f2m input from the GPIO bibuf. But it didn't worked. Then , changed to f2m.
I am wondering, if some other config is missing?

CASE 1: GPIO2 21 as interrupt:
&gpio2 {
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>;
status = "okay";
ngpios = <32>;
};

Configuration in i2c client dt node:

interrupt-parent = <&gpio2>;
interrupts = <21 2>;

CASE 2: GPIO2 21 as f2m:
interrupt-parent = <&plic>;
interrupts = <125>;

Is there any working example, where GPIO2 bank irq are used. I saw raspberry PI sense HAT overlay was using as gpio irq for joystick in icicle, but seems that is also disabled.

[hughbreslin]

Hey @govindsi

I'm still a bit confused to be honest - to try and give some info that could help you:

1. PCIe uses one of the FTM interrupts
2. There is a GPIO example in the /opt/microchip directory of the linux image - sources here

Can you give me a bit more clarity on what CASE 2? GPIO2 21 as f2m? FTM and GPIO are totally independent so I think I'm just getting confused on the terminology.

[govindsi]

We have C4 pin mapped to GPIO2_21, which is the irq line from an external charger chip. For case 2, i want to use this interrupt as fabric to MSS interrupt. Based on F2M mapping https://onlinedocs.microchip.com/oxy/GUID-199548F4-607C-436B-80C7-E4F280C1CAD2-en-US-1/GUID-CC94F07F-3D07-41AC-90A3-C07597C728F6.html, i have registered irq 125, but i am getting spurious interrupt with a flood.
Pls let me know if i have some misunderstanding in f2m uses.

#MSS GPIO_21
set_io -port_name GPIO2_21 -pin_name C4 -fixed true -DIRECTION INOUT -io_std LVCMOS33 -OUT_DRIVE 2 -RES_PULL Up

sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {GPIO2_21_BIBUF}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_M2F_21" "GPIO2_21_BIBUF:D"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_OE_M2F_21" "GPIO2_21_BIBUF:E"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_F2M_21" "GPIO2_21_BIBUF:Y"}
sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO2_21}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:MSS_INT_F2M[7:7]" "GPIO2_21_BIBUF:Y"}

[hughbreslin]

Could you try marking your input as "-RES_PULL Down" instead of Up. if the input is floating it'll be pulled up which could cause the interrupt storm.

I think every reference to GPIO_2_F2M_21 here is really just the input from your chip, it might be clearer to do some renaming. Also the bibuf probably isn't needed here as this is solely an input and not bidirectional. I'm not sure what state the output enable will be in from the GPIO if you aren't using the GPIO so maybe try going with a direct connection from your input (C4) to the F2M input of the MSS and remove the bibuf after setting the pull down resistor.

[govindsi]

Apologies for delayed reply, We did the changes, still the interrupt storm is seen. Do you suspect any other missing config?

#MSS GPIO_21
set_io -port_name GPIO2_21 -pin_name C4 -fixed true -DIRECTION IN -io_std LVCMOS33 -RES_PULL Down

sd_instantiate_macro -sd_name ${sd_name} -macro_name {INBUF} -instance_name {GPIO2_21_IBUF}
sd_rename_port -sd_name ${sd_name} -current_port_name {PAD} -new_port_name {GPIO2_21}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:GPIO_2_F2M_21" "GPIO2_21_IBUF:Y"}
sd_connect_pins -sd_name ${sd_name} -pin_names {"MSS:MSS_INT_F2M[7:7]" "GPIO2_21_IBUF:Y"}