mpfs-hal-ddr-demo & getting DDR testing to pass

[rockoguido]

trying to executed the mpfs-hal-ddr-demo on both the Icicle Kit and the SEV-Kit. I can changed configurations and build and load for either target, I just never get the DDR setup to complete. execution just stays in the loop that looks like..

while((ddr_status & DDR_SETUP_DONE) != DDR_SETUP_DONE)
{
ddr_status = ddr_state_machine(DDR_SS_MONITOR);
next_time = report_status_functions(DDR_BOOT_PROGRESS, next_time);
}

The behavior feels like DDR training is not done hence the DDR testing never succeeds, just hoping others have been down this path

Thx!
Dave

[mallynch]

Hi Dave, I assume you are using SoftConsole to build the Demo. As a staring point, can you check you are using the correct build configuration. You should select Icicle-Kit-LIM-Debug build configuration when debugging the Icicle kit. Thanks

[mallynch]

Hi Dave, As a next step, can you make sure you program the board to be in mode0 before you start debugging. You only need to do this one. Mode zero0 insures the board is waiting for a debug session on power-up, as opposed to trying to run a program from eNVM. To put the board in mode0, from SoftConsole use the following menu : <run -> External tools -> PolarFire SoC program -idle boot mode 0>
Thanks

[rockoguido]

Hello. Thanks for the quick response! Yes I am building in SoftConsole and of course loading the image to the target via SoftConsole. I also checked that I am using the correct build configuration. As a test if I deviate from the correct buid then the image does not even load correctly, that was just a quick sanity check. Am I to assume that the DDR training occurs before executing this application on the target? Thx! Dave Campanella Principal Embedded Solutions Engineer / FAE Microchip Technology Inc. 165 Technology Dr Irvine, CA 92618 +1 925 989 0569 (mobile) +1 760 304 0172 (office) ***@***.******@***.***> [Text Description automatically generated] <http://www.microchip.com/emasters>Visit our new learning site at www.microchip.com/mu<http://www.microchip.com/mu> From: mallynch ***@***.***> Sent: Friday, July 28, 2023 1:37 AM To: polarfire-soc/polarfire-soc-documentation ***@***.***> Cc: Dave Campanella - C68141 ***@***.***>; Author ***@***.***> Subject: Re: [polarfire-soc/polarfire-soc-documentation] mpfs-hal-ddr-demo & getting DDR testing to pass (Discussion #348) EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe Hi Dave, I assume you are using SoftConsole to build the Demo. As a staring point, can you check you are using the correct build configuration. You should select Icicle-Kit-LIM-Debug build configuration when debugging the Icicle kit. Thanks — Reply to this email directly, view it on GitHub<#348 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AXJPF66KKECZTIW2SDDJMNTXSN2ZFANCNFSM6AAAAAA226H574>. You are receiving this because you authored the thread.Message ID: ***@***.******@***.***>>