AXI-STREAM DMA start operation #366
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Hello, I am a little confused about the bare metal program:
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Replies: 4 comments
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Hi ZGDIGE, The CoreAXI4DMAController Streaming Example demonstrates the CoreAXI4DMAController performing fabric-to-memory DMA stream transfers using its AXI4-Stream slave interface. The CoreAXI4DMAController Block Transfer Example demonstrates the CoreAXI4DMAController performing memory-to-memory DMA block transfers using its AXI4 master DMA interface. For further information, please refer to the CoreAXI4DMAController Handbook and the CoreAXI4DMAController example projects. Regards |
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Hello p-owens, In the CoreAXI4DMAController Streaming Example, APB does not write the start signal directly to the DMA controller, but generates the TVALID signal. I read the handbook again. In 3.3.4, the DMA controller provides external start bits or start registers for internal descriptors. Because the stream descriptor is not an internal descriptor, there should be no need for external start bits and start registers. When the destination data ready bit is written, the bandwidth will be allocated by the DMA arbiter, which means that the stream transmission will be started at this time. I don't know if I understand it correctly. Regards |
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ZGDIGE, When the Regarding the destination data ready bit, see section 3.23 “Stream Descriptor Support”: The AXI4-Stream master initiates AXI4-Stream transfers, not the CoreAXI4DMAController. If part of a stream transaction has filled up the internal stream cache, no further transfers in the AXI4-Stream transaction will be acknowledged until the Destination Data Ready bit is asserted. N.B.: There is no section 3.3.4 in the current (v2.1) of the CoreAXI4DMAController handbook. Hope that clears it up for you. Best |
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Hi p-owens, |
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ZGDIGE,
When the
START
register of theAXI4_STREAM_DATA_GENERATOR
module is written to, the module places valid data onTDATA
and assertsTVALID
to indicate to the slave (the CoreAXI4DMAController) that there is valid data present at the output.The
TVALID
signal is part of the AXI4-Stream protocol signals, it is used in the handshake process between a master and a slave before an AXI4-Stream transfer can occur.Regarding the destination data ready bit, see section 3.23 “Stream Descriptor Support”:
“The Destination Data Ready bit is used by control masters to denote when a buffer has been allocated for the reception of the stream data in the AXI4 memory-map address space.”
The CoreAXI4DMA…