MSS DDR controller and ECC functionality

[andrenemat]

Dear all,

A few questions regarding the ECC features of the MSS DDR controller:

• If a single error detected the corrected value comes out to the data bus, then is that memory location being corrected too or it stays intact?
• Is the location of the error reported in any register?
• How does Double Error Detection work, what does it do? Does it report the location?
• Is there any memory scrubbing implemented within the controller if the ECC is enabled?

Thanks a lot