DDR4 baremetal read and write operations

[Nileena00]

anybody know how to validate Functional throughput of DDR4 (1600Mbps) using a baremetal code

[hughbreslin]

The DMA benchmarks show the performance of DDR copying to internal memory and also DDR to DDR transfers in this section - note its the non-cached as the cache will interfere with performance benchmarks.

Those results will show reads, for writes you could look at different internal memories to DDR, for example L2 LIM to non-cached ddr here.

The bare metal project here was used to generate the results

[Nileena00]

thankyou!

[Nileena00]

The DMA benchmarks show the performance of DDR copying to internal memory and also DDR to DDR transfers in this section - note its the non-cached as the cache will interfere with performance benchmarks.

Those results will show reads, for writes you could look at different internal memories to DDR, for example L2 LIM to non-cached ddr here.

The bare metal project here was used to generate the results

the ddr_test option by using test patterns i.e., example provided in https://github.com/polarfire-soc/polarfire-soc-bare-metal-examples/tree/main/driver-examples/mss/mpfs-hal/mpfs-hal-ddr-demo can be only done in image_loaded_bootloader = 0 ?
since the baremetal code on eNVM worked and but as hss payload successfuly built and flashed but getting stuck during ddr_test?

[hughbreslin]

The HSS will train DDR when it comes up, if you're using a payload with the HSS it shouldn't train the DDR as well. The HSS will run the DDR testing and training and also has a DDR memory test feature available

[nileena-dev]

i tried to implement this ddr read and write in my custom board as payload where it successfully read and write . but sometime for the first time after boot in write and read (cached) i am getting DEADBEEF while reading. may i know why?

this is the code running

static void ddr_test (uint32_t num_access)
{
uint64_t start_address = (uint64_t)(&__text_start);
uint64_t mem_size = LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 +
(LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 + 1U);
uint32_t max_num_access = mem_size/8U;
if (num_access > max_num_access)
{
num_access = max_num_access;
}
if(start_address >= 0x80000000UL && start_address <= 0xBFFFFFFFUL)
{
sprintf(info_string,"Executing from DDR \r\n");
MSS_UART_polled_tx(&g_mss_uart0_lo, info_string,strlen(info_string));
}
else
{
ASSERT(0);
}
setup_ddr_segments(DEFAULT_SEG_SETUP);
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\r Accessing DDR Non Cached ");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
ddr_read_write_fn((uint64_t*)(LIBERO_SETTING_DDR_64_NON_CACHE + (1024 * 128)),
(uint32_t)num_access,SW_CONFIG_PATTERN);
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\r Finished ");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\r Accessing DDR Cached ");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
ddr_read_write_fn((uint64_t*)(LIBERO_SETTING_DDR_64_CACHE + (1024 * 128)),
(uint32_t)(num_access * 32),SW_CONFIG_PATTERN);
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\r Finished ");
MSS_UART_polled_tx_string(g_uart,(const uint8_t*)
"\n\n\r ****************************************************** \n\r");
setup_ddr_segments(LIBERO_SEG_SETUP);
}